开源软件构建与测试

_service:tar_scm:libdrm.spec Changed

_service Changed

_service:tar_scm:libdrm-2.4.115.tar.xz.sig Deleted

_service:tar_scm:libdrm-2.4.119.tar.xz.sig Added

_service:tar_scm:libdrm-2.4.115.tar.xz/.gitlab-ci.yml -> _service:tar_scm:libdrm-2.4.119.tar.xz/.gitlab-ci.yml Changed

@@ -41,10 +41,10 @@
     BUILD_OS: debian
     FDO_DISTRIBUTION_VERSION: buster
     FDO_DISTRIBUTION_PACKAGES: 'build-essential docbook-xsl libatomic-ops-dev libcairo2-dev libcunit1-dev libpciaccess-dev meson ninja-build pkg-config python3 python3-pip python3-wheel python3-setuptools python3-docutils valgrind'
-    FDO_DISTRIBUTION_EXEC: 'pip3 install meson==0.53.0'
+    FDO_DISTRIBUTION_EXEC: 'pip3 install meson==0.59.0'
     # bump this tag every time you change something which requires rebuilding the
     # base image
-    FDO_DISTRIBUTION_TAG: "2022-08-22.0"
+    FDO_DISTRIBUTION_TAG: "2023-09-01.0"
 
 .debian-x86_64:
   extends:
@@ -67,11 +67,11 @@
 .os-freebsd:
   variables:
     BUILD_OS: freebsd
-    FDO_DISTRIBUTION_VERSION: "13.0"
-    FDO_DISTRIBUTION_PACKAGES: 'meson ninja pkgconf libpciaccess libpthread-stubs py39-docutils cairo'
+    FDO_DISTRIBUTION_VERSION: "13.2"
+    FDO_DISTRIBUTION_PACKAGES: 'meson ninja pkgconf libpciaccess py39-docutils cairo'
     # bump this tag every time you change something which requires rebuilding the
     # base image
-    FDO_DISTRIBUTION_TAG: "2022-08-22.0"
+    FDO_DISTRIBUTION_TAG: "2023-07-20.0"
 
 .freebsd-x86_64:
   extends:

_service:tar_scm:libdrm-2.4.115.tar.xz/amdgpu/amdgpu-symbols.txt -> _service:tar_scm:libdrm-2.4.119.tar.xz/amdgpu/amdgpu-symbols.txt Changed

_service:tar_scm:libdrm-2.4.115.tar.xz/amdgpu/amdgpu.h -> _service:tar_scm:libdrm-2.4.119.tar.xz/amdgpu/amdgpu.h Changed

@@ -1283,6 +1283,22 @@
                                  unsigned size, void *value);
 
 /**
+ * Query information about VM faults
+ *
+ * The return sizeof(struct drm_amdgpu_info_gpuvm_fault)
+ *
+ * \param   dev         - \c in Device handle. See #amdgpu_device_initialize()
+ * \param   size        - \c in Size of the returned value.
+ * \param   value       - \c out Pointer to the return value.
+ *
+ * \return   0 on success\n
+ *          <0 - Negative POSIX Error code
+ *
+*/
+int amdgpu_query_gpuvm_fault_info(amdgpu_device_handle dev, unsigned size,
+				  void *value);
+
+/**
  * Read a set of consecutive memory-mapped registers.
  * Not all registers are allowed to be read by userspace.
  *
@@ -1369,6 +1385,11 @@
 int amdgpu_va_range_free(amdgpu_va_handle va_range_handle);
 
 /**
+ * Return the starting address of the allocated virtual address range.
+ */
+uint64_t amdgpu_va_get_start_addr(amdgpu_va_handle va_handle);
+
+/**
 * Query virtual address range
 *
 * UMD can query GPU VM range supported by each device

_service:tar_scm:libdrm-2.4.115.tar.xz/amdgpu/amdgpu_bo.c -> _service:tar_scm:libdrm-2.4.119.tar.xz/amdgpu/amdgpu_bo.c Changed

_service:tar_scm:libdrm-2.4.115.tar.xz/amdgpu/amdgpu_cs.c -> _service:tar_scm:libdrm-2.4.119.tar.xz/amdgpu/amdgpu_cs.c Changed

_service:tar_scm:libdrm-2.4.115.tar.xz/amdgpu/amdgpu_gpu_info.c -> _service:tar_scm:libdrm-2.4.119.tar.xz/amdgpu/amdgpu_gpu_info.c Changed

_service:tar_scm:libdrm-2.4.115.tar.xz/amdgpu/amdgpu_internal.h -> _service:tar_scm:libdrm-2.4.119.tar.xz/amdgpu/amdgpu_internal.h Changed

_service:tar_scm:libdrm-2.4.115.tar.xz/amdgpu/amdgpu_vamgr.c -> _service:tar_scm:libdrm-2.4.119.tar.xz/amdgpu/amdgpu_vamgr.c Changed

_service:tar_scm:libdrm-2.4.115.tar.xz/amdgpu/meson.build -> _service:tar_scm:libdrm-2.4.119.tar.xz/amdgpu/meson.build Changed

_service:tar_scm:libdrm-2.4.115.tar.xz/core-symbols.txt -> _service:tar_scm:libdrm-2.4.119.tar.xz/core-symbols.txt Changed

_service:tar_scm:libdrm-2.4.115.tar.xz/data/amdgpu.ids -> _service:tar_scm:libdrm-2.4.119.tar.xz/data/amdgpu.ids Changed

_service:tar_scm:libdrm-2.4.115.tar.xz/etnaviv/meson.build -> _service:tar_scm:libdrm-2.4.119.tar.xz/etnaviv/meson.build Changed

_service:tar_scm:libdrm-2.4.115.tar.xz/exynos/meson.build -> _service:tar_scm:libdrm-2.4.119.tar.xz/exynos/meson.build Changed

_service:tar_scm:libdrm-2.4.115.tar.xz/freedreno/meson.build -> _service:tar_scm:libdrm-2.4.119.tar.xz/freedreno/meson.build Changed

_service:tar_scm:libdrm-2.4.115.tar.xz/include/drm/amdgpu_drm.h -> _service:tar_scm:libdrm-2.4.119.tar.xz/include/drm/amdgpu_drm.h Changed

@@ -94,6 +94,9 @@
  *
  * %AMDGPU_GEM_DOMAIN_OA	Ordered append, used by 3D or Compute engines
  * for appending data.
+ *
+ * %AMDGPU_GEM_DOMAIN_DOORBELL	Doorbell. It is an MMIO region for
+ * signalling user mode queues.
  */
 #define AMDGPU_GEM_DOMAIN_CPU		0x1
 #define AMDGPU_GEM_DOMAIN_GTT		0x2
@@ -101,12 +104,14 @@
 #define AMDGPU_GEM_DOMAIN_GDS		0x8
 #define AMDGPU_GEM_DOMAIN_GWS		0x10
 #define AMDGPU_GEM_DOMAIN_OA		0x20
+#define AMDGPU_GEM_DOMAIN_DOORBELL	0x40
 #define AMDGPU_GEM_DOMAIN_MASK		(AMDGPU_GEM_DOMAIN_CPU | \
 					 AMDGPU_GEM_DOMAIN_GTT | \
 					 AMDGPU_GEM_DOMAIN_VRAM | \
 					 AMDGPU_GEM_DOMAIN_GDS | \
 					 AMDGPU_GEM_DOMAIN_GWS | \
-					 AMDGPU_GEM_DOMAIN_OA)
+					 AMDGPU_GEM_DOMAIN_OA | \
+					 AMDGPU_GEM_DOMAIN_DOORBELL)
 
 /* Flag that CPU access will be required for the case of VRAM domain */
 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED	(1 << 0)
@@ -140,6 +145,32 @@
  * not require GTT memory accounting
  */
 #define AMDGPU_GEM_CREATE_PREEMPTIBLE		(1 << 11)
+/* Flag that BO can be discarded under memory pressure without keeping the
+ * content.
+ */
+#define AMDGPU_GEM_CREATE_DISCARDABLE		(1 << 12)
+/* Flag that BO is shared coherently between multiple devices or CPU threads.
+ * May depend on GPU instructions to flush caches to system scope explicitly.
+ *
+ * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and
+ * may override the MTYPE selected in AMDGPU_VA_OP_MAP.
+ */
+#define AMDGPU_GEM_CREATE_COHERENT		(1 << 13)
+/* Flag that BO should not be cached by GPU. Coherent without having to flush
+ * GPU caches explicitly
+ *
+ * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and
+ * may override the MTYPE selected in AMDGPU_VA_OP_MAP.
+ */
+#define AMDGPU_GEM_CREATE_UNCACHED		(1 << 14)
+/* Flag that BO should be coherent across devices when using device-level
+ * atomics. May depend on GPU instructions to flush caches to device scope
+ * explicitly, promoting them to system scope automatically.
+ *
+ * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and
+ * may override the MTYPE selected in AMDGPU_VA_OP_MAP.
+ */
+#define AMDGPU_GEM_CREATE_EXT_COHERENT		(1 << 15)
 
 struct drm_amdgpu_gem_create_in  {
 	/** the requested memory size */
@@ -218,15 +249,17 @@
 /* unknown cause */
 #define AMDGPU_CTX_UNKNOWN_RESET	3
 
-/* indicate gpu reset occured after ctx created */
+/* indicate gpu reset occurred after ctx created */
 #define AMDGPU_CTX_QUERY2_FLAGS_RESET    (1<<0)
-/* indicate vram lost occured after ctx created */
+/* indicate vram lost occurred after ctx created */
 #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1)
 /* indicate some job from this context once cause gpu hang */
 #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY   (1<<2)
 /* indicate some errors are detected by RAS */
 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE   (1<<3)
 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE   (1<<4)
+/* indicate that the reset hasn't completed yet */
+#define AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS (1<<5)
 
 /* Context priority level */
 #define AMDGPU_CTX_PRIORITY_UNSET       -2048
@@ -529,6 +562,8 @@
 #define AMDGPU_VM_MTYPE_UC		(4 << 5)
 /* Use Read Write MTYPE instead of default MTYPE */
 #define AMDGPU_VM_MTYPE_RW		(5 << 5)
+/* don't allocate MALL */
+#define AMDGPU_VM_PAGE_NOALLOC		(1 << 9)
 
 struct drm_amdgpu_gem_va {
 	/** GEM object handle */
@@ -559,7 +594,8 @@
  */
 #define AMDGPU_HW_IP_VCN_ENC      7
 #define AMDGPU_HW_IP_VCN_JPEG     8
-#define AMDGPU_HW_IP_NUM          9
+#define AMDGPU_HW_IP_VPE          9
+#define AMDGPU_HW_IP_NUM          10
 
 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
 
@@ -572,6 +608,7 @@
 #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES	0x07
 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT    0x08
 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL  0x09
+#define AMDGPU_CHUNK_ID_CP_GFX_SHADOW   0x0a
 
 struct drm_amdgpu_cs_chunk {
 	__u32		chunk_id;
@@ -688,6 +725,15 @@
 	};
 };
 
+#define AMDGPU_CS_CHUNK_CP_GFX_SHADOW_FLAGS_INIT_SHADOW         0x1
+
+struct drm_amdgpu_cs_chunk_cp_gfx_shadow {
+	__u64 shadow_va;
+	__u64 csa_va;
+	__u64 gds_va;
+	__u64 flags;
+};
+
 /*
  *  Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU
  *
@@ -695,6 +741,7 @@
 #define AMDGPU_IDS_FLAGS_FUSION         0x1
 #define AMDGPU_IDS_FLAGS_PREEMPTION     0x2
 #define AMDGPU_IDS_FLAGS_TMZ            0x4
+#define AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD 0x8
 
 /* indicate if acceleration can be working */
 #define AMDGPU_INFO_ACCEL_WORKING		0x00
@@ -747,6 +794,20 @@
 	#define AMDGPU_INFO_FW_DMCUB		0x14
 	/* Subquery id: Query TOC firmware version */
 	#define AMDGPU_INFO_FW_TOC		0x15
+	/* Subquery id: Query CAP firmware version */
+	#define AMDGPU_INFO_FW_CAP		0x16
+	/* Subquery id: Query GFX RLCP firmware version */
+	#define AMDGPU_INFO_FW_GFX_RLCP		0x17
+	/* Subquery id: Query GFX RLCV firmware version */
+	#define AMDGPU_INFO_FW_GFX_RLCV		0x18
+	/* Subquery id: Query MES_KIQ firmware version */
+	#define AMDGPU_INFO_FW_MES_KIQ		0x19
+	/* Subquery id: Query MES firmware version */
+	#define AMDGPU_INFO_FW_MES		0x1a
+	/* Subquery id: Query IMU firmware version */
+	#define AMDGPU_INFO_FW_IMU		0x1b
+	/* Subquery id: Query VPE firmware version */
+	#define AMDGPU_INFO_FW_VPE		0x1c
 
 /* number of bytes moved for TTM migration */
 #define AMDGPU_INFO_NUM_BYTES_MOVED		0x0f
@@ -800,6 +861,10 @@
 	#define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK		0x8
 	/* Subquery id: Query GPU stable pstate memory clock */
 	#define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK		0x9
+	/* Subquery id: Query GPU peak pstate shader clock */
+	#define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK			0xa
+	/* Subquery id: Query GPU peak pstate memory clock */
+	#define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK			0xb
 /* Number of VRAM page faults on CPU access. */
 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS	0x1E
 #define AMDGPU_INFO_VRAM_LOST_COUNTER		0x1F
@@ -839,6 +904,10 @@
 	#define AMDGPU_INFO_VIDEO_CAPS_DECODE		0
 	/* Subquery id: Encode */
 	#define AMDGPU_INFO_VIDEO_CAPS_ENCODE		1
+/* Query the max number of IBs per gang per submission */
+#define AMDGPU_INFO_MAX_IBS			0x22
+/* query last page fault info */
+#define AMDGPU_INFO_GPUVM_FAULT			0x23
 
 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT	0
 #define AMDGPU_INFO_MMR_SE_INDEX_MASK	0xff
@@ -990,6 +1059,8 @@
 #define AMDGPU_VRAM_TYPE_DDR4  8
 #define AMDGPU_VRAM_TYPE_GDDR6 9
 #define AMDGPU_VRAM_TYPE_DDR5  10
+#define AMDGPU_VRAM_TYPE_LPDDR4 11
+#define AMDGPU_VRAM_TYPE_LPDDR5 12
 
 struct drm_amdgpu_info_device {
 	/** PCI Device ID */
@@ -1015,7 +1086,8 @@
 	__u32 enabled_rb_pipes_mask;
 	__u32 num_rb_pipes;
 	__u32 num_hw_gfx_contexts;
-	__u32 _pad;
+	/* PCIe version (the smaller of the GPU and the CPU/motherboard) */
+	__u32 pcie_gen;
 	__u64 ids_flags;
 	/** Starting virtual address for UMDs. */
 	__u64 virtual_address_offset;
@@ -1062,7 +1134,8 @@
 	__u32 gs_prim_buffer_depth;
 	/* max gs wavefront per vgt*/
 	__u32 max_gs_waves_per_vgt;
-	__u32 _pad1;
+	/* PCIe number of lanes (the smaller of the GPU and the CPU/motherboard) */
+	__u32 pcie_num_lanes;
 	/* always on cu bitmap */

_service:tar_scm:libdrm-2.4.115.tar.xz/include/drm/drm.h -> _service:tar_scm:libdrm-2.4.119.tar.xz/include/drm/drm.h Changed

@@ -629,8 +629,8 @@
 /**
  * DRM_CAP_VBLANK_HIGH_CRTC
  *
- * If set to 1, the kernel supports specifying a CRTC index in the high bits of
- * &drm_wait_vblank_request.type.
+ * If set to 1, the kernel supports specifying a :ref:`CRTC index<crtc_index>`
+ * in the high bits of &drm_wait_vblank_request.type.
  *
  * Starting kernel version 2.6.39, this capability is always set to 1.
  */
@@ -667,8 +667,11 @@
  * Bitfield of supported PRIME sharing capabilities. See &DRM_PRIME_CAP_IMPORT
  * and &DRM_PRIME_CAP_EXPORT.
  *
- * PRIME buffers are exposed as dma-buf file descriptors. See
- * Documentation/gpu/drm-mm.rst, section "PRIME Buffer Sharing".
+ * Starting from kernel version 6.6, both &DRM_PRIME_CAP_IMPORT and
+ * &DRM_PRIME_CAP_EXPORT are always advertised.
+ *
+ * PRIME buffers are exposed as dma-buf file descriptors.
+ * See :ref:`prime_buffer_sharing`.
  */
 #define DRM_CAP_PRIME			0x5
 /**
@@ -676,6 +679,8 @@
  *
  * If this bit is set in &DRM_CAP_PRIME, the driver supports importing PRIME
  * buffers via the &DRM_IOCTL_PRIME_FD_TO_HANDLE ioctl.
+ *
+ * Starting from kernel version 6.6, this bit is always set in &DRM_CAP_PRIME.
  */
 #define  DRM_PRIME_CAP_IMPORT		0x1
 /**
@@ -683,6 +688,8 @@
  *
  * If this bit is set in &DRM_CAP_PRIME, the driver supports exporting PRIME
  * buffers via the &DRM_IOCTL_PRIME_HANDLE_TO_FD ioctl.
+ *
+ * Starting from kernel version 6.6, this bit is always set in &DRM_CAP_PRIME.
  */
 #define  DRM_PRIME_CAP_EXPORT		0x2
 /**
@@ -750,15 +757,14 @@
 /**
  * DRM_CAP_SYNCOBJ
  *
- * If set to 1, the driver supports sync objects. See
- * Documentation/gpu/drm-mm.rst, section "DRM Sync Objects".
+ * If set to 1, the driver supports sync objects. See :ref:`drm_sync_objects`.
  */
 #define DRM_CAP_SYNCOBJ		0x13
 /**
  * DRM_CAP_SYNCOBJ_TIMELINE
  *
  * If set to 1, the driver supports timeline operations on sync objects. See
- * Documentation/gpu/drm-mm.rst, section "DRM Sync Objects".
+ * :ref:`drm_sync_objects`.
  */
 #define DRM_CAP_SYNCOBJ_TIMELINE	0x14
 
@@ -903,6 +909,27 @@
 	__u32 pad;
 };
 
+/**
+ * struct drm_syncobj_eventfd
+ * @handle: syncobj handle.
+ * @flags: Zero to wait for the point to be signalled, or
+ *         &DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE to wait for a fence to be
+ *         available for the point.
+ * @point: syncobj timeline point (set to zero for binary syncobjs).
+ * @fd: Existing eventfd to sent events to.
+ * @pad: Must be zero.
+ *
+ * Register an eventfd to be signalled by a syncobj. The eventfd counter will
+ * be incremented by one.
+ */
+struct drm_syncobj_eventfd {
+	__u32 handle;
+	__u32 flags;
+	__u64 point;
+	__s32 fd;
+	__u32 pad;
+};
+
 
 struct drm_syncobj_array {
 	__u64 handles;
@@ -966,6 +993,19 @@
 #define DRM_IOCTL_GET_STATS             DRM_IOR( 0x06, struct drm_stats)
 #define DRM_IOCTL_SET_VERSION		DRM_IOWR(0x07, struct drm_set_version)
 #define DRM_IOCTL_MODESET_CTL           DRM_IOW(0x08, struct drm_modeset_ctl)
+/**
+ * DRM_IOCTL_GEM_CLOSE - Close a GEM handle.
+ *
+ * GEM handles are not reference-counted by the kernel. User-space is
+ * responsible for managing their lifetime. For example, if user-space imports
+ * the same memory object twice on the same DRM file description, the same GEM
+ * handle is returned by both imports, and user-space needs to ensure
+ * &DRM_IOCTL_GEM_CLOSE is performed once only. The same situation can happen
+ * when a memory object is allocated, then exported and imported again on the
+ * same DRM file description. The &DRM_IOCTL_MODE_GETFB2 IOCTL is an exception
+ * and always returns fresh new GEM handles even if an existing GEM handle
+ * already refers to the same memory object before the IOCTL is performed.
+ */
 #define DRM_IOCTL_GEM_CLOSE		DRM_IOW (0x09, struct drm_gem_close)
 #define DRM_IOCTL_GEM_FLINK		DRM_IOWR(0x0a, struct drm_gem_flink)
 #define DRM_IOCTL_GEM_OPEN		DRM_IOWR(0x0b, struct drm_gem_open)
@@ -1006,7 +1046,37 @@
 #define DRM_IOCTL_UNLOCK		DRM_IOW( 0x2b, struct drm_lock)
 #define DRM_IOCTL_FINISH		DRM_IOW( 0x2c, struct drm_lock)
 
+/**
+ * DRM_IOCTL_PRIME_HANDLE_TO_FD - Convert a GEM handle to a DMA-BUF FD.
+ *
+ * User-space sets &drm_prime_handle.handle with the GEM handle to export and
+ * &drm_prime_handle.flags, and gets back a DMA-BUF file descriptor in
+ * &drm_prime_handle.fd.
+ *
+ * The export can fail for any driver-specific reason, e.g. because export is
+ * not supported for this specific GEM handle (but might be for others).
+ *
+ * Support for exporting DMA-BUFs is advertised via &DRM_PRIME_CAP_EXPORT.
+ */
 #define DRM_IOCTL_PRIME_HANDLE_TO_FD    DRM_IOWR(0x2d, struct drm_prime_handle)
+/**
+ * DRM_IOCTL_PRIME_FD_TO_HANDLE - Convert a DMA-BUF FD to a GEM handle.
+ *
+ * User-space sets &drm_prime_handle.fd with a DMA-BUF file descriptor to
+ * import, and gets back a GEM handle in &drm_prime_handle.handle.
+ * &drm_prime_handle.flags is unused.
+ *
+ * If an existing GEM handle refers to the memory object backing the DMA-BUF,
+ * that GEM handle is returned. Therefore user-space which needs to handle
+ * arbitrary DMA-BUFs must have a user-space lookup data structure to manually
+ * reference-count duplicated GEM handles. For more information see
+ * &DRM_IOCTL_GEM_CLOSE.
+ *
+ * The import can fail for any driver-specific reason, e.g. because import is
+ * only supported for DMA-BUFs allocated on this DRM device.
+ *
+ * Support for importing DMA-BUFs is advertised via &DRM_PRIME_CAP_IMPORT.
+ */
 #define DRM_IOCTL_PRIME_FD_TO_HANDLE    DRM_IOWR(0x2e, struct drm_prime_handle)
 
 #define DRM_IOCTL_AGP_ACQUIRE		DRM_IO(  0x30)
@@ -1044,10 +1114,40 @@
 #define DRM_IOCTL_MODE_GETPROPBLOB	DRM_IOWR(0xAC, struct drm_mode_get_blob)
 #define DRM_IOCTL_MODE_GETFB		DRM_IOWR(0xAD, struct drm_mode_fb_cmd)
 #define DRM_IOCTL_MODE_ADDFB		DRM_IOWR(0xAE, struct drm_mode_fb_cmd)
+/**
+ * DRM_IOCTL_MODE_RMFB - Remove a framebuffer.
+ *
+ * This removes a framebuffer previously added via ADDFB/ADDFB2. The IOCTL
+ * argument is a framebuffer object ID.
+ *
+ * Warning: removing a framebuffer currently in-use on an enabled plane will
+ * disable that plane. The CRTC the plane is linked to may also be disabled
+ * (depending on driver capabilities).
+ */
 #define DRM_IOCTL_MODE_RMFB		DRM_IOWR(0xAF, unsigned int)
 #define DRM_IOCTL_MODE_PAGE_FLIP	DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip)
 #define DRM_IOCTL_MODE_DIRTYFB		DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd)
 
+/**
+ * DRM_IOCTL_MODE_CREATE_DUMB - Create a new dumb buffer object.
+ *
+ * KMS dumb buffers provide a very primitive way to allocate a buffer object
+ * suitable for scanout and map it for software rendering. KMS dumb buffers are
+ * not suitable for hardware-accelerated rendering nor video decoding. KMS dumb
+ * buffers are not suitable to be displayed on any other device than the KMS
+ * device where they were allocated from. Also see
+ * :ref:`kms_dumb_buffer_objects`.
+ *
+ * The IOCTL argument is a struct drm_mode_create_dumb.
+ *
+ * User-space is expected to create a KMS dumb buffer via this IOCTL, then add
+ * it as a KMS framebuffer via &DRM_IOCTL_MODE_ADDFB and map it via
+ * &DRM_IOCTL_MODE_MAP_DUMB.
+ *
+ * &DRM_CAP_DUMB_BUFFER indicates whether this IOCTL is supported.
+ * &DRM_CAP_DUMB_PREFERRED_DEPTH and &DRM_CAP_DUMB_PREFER_SHADOW indicate
+ * driver preferences for dumb buffers.
+ */
 #define DRM_IOCTL_MODE_CREATE_DUMB DRM_IOWR(0xB2, struct drm_mode_create_dumb)
 #define DRM_IOCTL_MODE_MAP_DUMB    DRM_IOWR(0xB3, struct drm_mode_map_dumb)
 #define DRM_IOCTL_MODE_DESTROY_DUMB    DRM_IOWR(0xB4, struct drm_mode_destroy_dumb)
@@ -1080,8 +1180,58 @@
 #define DRM_IOCTL_SYNCOBJ_TRANSFER	DRM_IOWR(0xCC, struct drm_syncobj_transfer)
 #define DRM_IOCTL_SYNCOBJ_TIMELINE_SIGNAL	DRM_IOWR(0xCD, struct drm_syncobj_timeline_array)
 
+/**
+ * DRM_IOCTL_MODE_GETFB2 - Get framebuffer metadata.
+ *
+ * This queries metadata about a framebuffer. User-space fills
+ * &drm_mode_fb_cmd2.fb_id as the input, and the kernels fills the rest of the
+ * struct as the output.
+ *
+ * If the client is DRM master or has &CAP_SYS_ADMIN, &drm_mode_fb_cmd2.handles

_service:tar_scm:libdrm-2.4.115.tar.xz/include/drm/drm_fourcc.h -> _service:tar_scm:libdrm-2.4.119.tar.xz/include/drm/drm_fourcc.h Changed

@@ -88,6 +88,18 @@
  *
  * The authoritative list of format modifier codes is found in
  * `include/uapi/drm/drm_fourcc.h`
+ *
+ * Open Source User Waiver
+ * -----------------------
+ *
+ * Because this is the authoritative source for pixel formats and modifiers
+ * referenced by GL, Vulkan extensions and other standards and hence used both
+ * by open source and closed source driver stacks, the usual requirement for an
+ * upstream in-kernel or open source userspace user does not apply.
+ *
+ * To ensure, as much as feasible, compatibility across stacks and avoid
+ * confusion with incompatible enumerations stakeholders for all relevant driver
+ * stacks should approve additions.
  */
 
 #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
@@ -311,6 +323,8 @@
  * index 1 = Cr:Cb plane, 39:0 Cr1:Cb1:Cr0:Cb0 little endian
  */
 #define DRM_FORMAT_NV15		fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */
+#define DRM_FORMAT_NV20		fourcc_code('N', 'V', '2', '0') /* 2x1 subsampled Cr:Cb plane */
+#define DRM_FORMAT_NV30		fourcc_code('N', 'V', '3', '0') /* non-subsampled Cr:Cb plane */
 
 /*
  * 2 plane YCbCr MSB aligned
@@ -646,6 +660,49 @@
 #define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12)
 
 /*
+ * Intel Color Control Surfaces (CCS) for display ver. 14 render compression.
+ *
+ * The main surface is tile4 and at plane index 0, the CCS is linear and
+ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
+ * main surface. In other words, 4 bits in CCS map to a main surface cache
+ * line pair. The main surface pitch is required to be a multiple of four
+ * tile4 widths.
+ */
+#define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS fourcc_mod_code(INTEL, 13)
+
+/*
+ * Intel Color Control Surfaces (CCS) for display ver. 14 media compression
+ *
+ * The main surface is tile4 and at plane index 0, the CCS is linear and
+ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
+ * main surface. In other words, 4 bits in CCS map to a main surface cache
+ * line pair. The main surface pitch is required to be a multiple of four
+ * tile4 widths. For semi-planar formats like NV12, CCS planes follow the
+ * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
+ * planes 2 and 3 for the respective CCS.
+ */
+#define I915_FORMAT_MOD_4_TILED_MTL_MC_CCS fourcc_mod_code(INTEL, 14)
+
+/*
+ * Intel Color Control Surface with Clear Color (CCS) for display ver. 14 render
+ * compression.
+ *
+ * The main surface is tile4 and is at plane index 0 whereas CCS is linear
+ * and at index 1. The clear color is stored at index 2, and the pitch should
+ * be ignored. The clear color structure is 256 bits. The first 128 bits
+ * represents Raw Clear Color Red, Green, Blue and Alpha color each represented
+ * by 32 bits. The raw clear color is consumed by the 3d engine and generates
+ * the converted clear color of size 64 bits. The first 32 bits store the Lower
+ * Converted Clear Color value and the next 32 bits store the Higher Converted
+ * Clear Color value when applicable. The Converted Clear Color values are
+ * consumed by the DE. The last 64 bits are used to store Color Discard Enable
+ * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
+ * corresponds to an area of 4x1 tiles in the main surface. The main surface
+ * pitch is required to be a multiple of 4 tile widths.
+ */
+#define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC fourcc_mod_code(INTEL, 15)
+
+/*
  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
  *
  * Macroblocks are laid in a Z-shape, and each pixel data is following the

_service:tar_scm:libdrm-2.4.115.tar.xz/include/drm/drm_mode.h -> _service:tar_scm:libdrm-2.4.119.tar.xz/include/drm/drm_mode.h Changed

@@ -312,16 +312,48 @@
 	__u32 src_w;
 };
 
+/**
+ * struct drm_mode_get_plane - Get plane metadata.
+ *
+ * Userspace can perform a GETPLANE ioctl to retrieve information about a
+ * plane.
+ *
+ * To retrieve the number of formats supported, set @count_format_types to zero
+ * and call the ioctl. @count_format_types will be updated with the value.
+ *
+ * To retrieve these formats, allocate an array with the memory needed to store
+ * @count_format_types formats. Point @format_type_ptr to this array and call
+ * the ioctl again (with @count_format_types still set to the value returned in
+ * the first ioctl call).
+ */
 struct drm_mode_get_plane {
+	/**
+	 * @plane_id: Object ID of the plane whose information should be
+	 * retrieved. Set by caller.
+	 */
 	__u32 plane_id;
 
+	/** @crtc_id: Object ID of the current CRTC. */
 	__u32 crtc_id;
+	/** @fb_id: Object ID of the current fb. */
 	__u32 fb_id;
 
+	/**
+	 * @possible_crtcs: Bitmask of CRTC's compatible with the plane. CRTC's
+	 * are created and they receive an index, which corresponds to their
+	 * position in the bitmask. Bit N corresponds to
+	 * :ref:`CRTC index<crtc_index>` N.
+	 */
 	__u32 possible_crtcs;
+	/** @gamma_size: Never used. */
 	__u32 gamma_size;
 
+	/** @count_format_types: Number of formats. */
 	__u32 count_format_types;
+	/**
+	 * @format_type_ptr: Pointer to ``__u32`` array of formats that are
+	 * supported by the plane. These formats do not require modifiers.
+	 */
 	__u64 format_type_ptr;
 };
 
@@ -456,6 +488,9 @@
 	 * This is not an object ID. This is a per-type connector number. Each
 	 * (type, type_id) combination is unique across all connectors of a DRM
 	 * device.
+	 *
+	 * The (type, type_id) combination is not a stable identifier: the
+	 * type_id can change depending on the driver probe order.
 	 */
 	__u32 connector_type_id;
 
@@ -509,22 +544,74 @@
  */
 #define DRM_MODE_PROP_ATOMIC        0x80000000
 
+/**
+ * struct drm_mode_property_enum - Description for an enum/bitfield entry.
+ * @value: numeric value for this enum entry.
+ * @name: symbolic name for this enum entry.
+ *
+ * See struct drm_property_enum for details.
+ */
 struct drm_mode_property_enum {
 	__u64 value;
 	char nameDRM_PROP_NAME_LEN;
 };
 
+/**
+ * struct drm_mode_get_property - Get property metadata.
+ *
+ * User-space can perform a GETPROPERTY ioctl to retrieve information about a
+ * property. The same property may be attached to multiple objects, see
+ * "Modeset Base Object Abstraction".
+ *
+ * The meaning of the @values_ptr field changes depending on the property type.
+ * See &drm_property.flags for more details.
+ *
+ * The @enum_blob_ptr and @count_enum_blobs fields are only meaningful when the
+ * property has the type &DRM_MODE_PROP_ENUM or &DRM_MODE_PROP_BITMASK. For
+ * backwards compatibility, the kernel will always set @count_enum_blobs to
+ * zero when the property has the type &DRM_MODE_PROP_BLOB. User-space must
+ * ignore these two fields if the property has a different type.
+ *
+ * User-space is expected to retrieve values and enums by performing this ioctl
+ * at least twice: the first time to retrieve the number of elements, the
+ * second time to retrieve the elements themselves.
+ *
+ * To retrieve the number of elements, set @count_values and @count_enum_blobs
+ * to zero, then call the ioctl. @count_values will be updated with the number
+ * of elements. If the property has the type &DRM_MODE_PROP_ENUM or
+ * &DRM_MODE_PROP_BITMASK, @count_enum_blobs will be updated as well.
+ *
+ * To retrieve the elements themselves, allocate an array for @values_ptr and
+ * set @count_values to its capacity. If the property has the type
+ * &DRM_MODE_PROP_ENUM or &DRM_MODE_PROP_BITMASK, allocate an array for
+ * @enum_blob_ptr and set @count_enum_blobs to its capacity. Calling the ioctl
+ * again will fill the arrays.
+ */
 struct drm_mode_get_property {
-	__u64 values_ptr; /* values and blob lengths */
-	__u64 enum_blob_ptr; /* enum and blob id ptrs */
+	/** @values_ptr: Pointer to a ``__u64`` array. */
+	__u64 values_ptr;
+	/** @enum_blob_ptr: Pointer to a struct drm_mode_property_enum array. */
+	__u64 enum_blob_ptr;
 
+	/**
+	 * @prop_id: Object ID of the property which should be retrieved. Set
+	 * by the caller.
+	 */
 	__u32 prop_id;
+	/**
+	 * @flags: ``DRM_MODE_PROP_*`` bitfield. See &drm_property.flags for
+	 * a definition of the flags.
+	 */
 	__u32 flags;
+	/**
+	 * @name: Symbolic property name. User-space should use this field to
+	 * recognize properties.
+	 */
 	char nameDRM_PROP_NAME_LEN;
 
+	/** @count_values: Number of elements in @values_ptr. */
 	__u32 count_values;
-	/* This is only used to count enum values, not blobs. The _blobs is
-	 * simply because of a historical reason, i.e. backwards compat. */
+	/** @count_enum_blobs: Number of elements in @enum_blob_ptr. */
 	__u32 count_enum_blobs;
 };
 
@@ -579,41 +666,73 @@
 #define DRM_MODE_FB_INTERLACED	(1<<0) /* for interlaced framebuffers */
 #define DRM_MODE_FB_MODIFIERS	(1<<1) /* enables ->modifer */
 
+/**
+ * struct drm_mode_fb_cmd2 - Frame-buffer metadata.
+ *
+ * This struct holds frame-buffer metadata. There are two ways to use it:
+ *
+ * - User-space can fill this struct and perform a &DRM_IOCTL_MODE_ADDFB2
+ *   ioctl to register a new frame-buffer. The new frame-buffer object ID will
+ *   be set by the kernel in @fb_id.
+ * - User-space can set @fb_id and perform a &DRM_IOCTL_MODE_GETFB2 ioctl to
+ *   fetch metadata about an existing frame-buffer.
+ *
+ * In case of planar formats, this struct allows up to 4 buffer objects with
+ * offsets and pitches per plane. The pitch and offset order are dictated by
+ * the format FourCC as defined by ``drm_fourcc.h``, e.g. NV12 is described as:
+ *
+ *     YUV 4:2:0 image with a plane of 8-bit Y samples followed by an
+ *     interleaved U/V plane containing 8-bit 2x2 subsampled colour difference
+ *     samples.
+ *
+ * So it would consist of a Y plane at ``offsets0`` and a UV plane at
+ * ``offsets1``.
+ *
+ * To accommodate tiled, compressed, etc formats, a modifier can be specified.
+ * For more information see the "Format Modifiers" section. Note that even
+ * though it looks like we have a modifier per-plane, we in fact do not. The
+ * modifier for each plane must be identical. Thus all combinations of
+ * different data layouts for multi-plane formats must be enumerated as
+ * separate modifiers.
+ *
+ * All of the entries in @handles, @pitches, @offsets and @modifier must be
+ * zero when unused. Warning, for @offsets and @modifier zero can't be used to
+ * figure out whether the entry is used or not since it's a valid value (a zero
+ * offset is common, and a zero modifier is &DRM_FORMAT_MOD_LINEAR).
+ */
 struct drm_mode_fb_cmd2 {
+	/** @fb_id: Object ID of the frame-buffer. */
 	__u32 fb_id;
+	/** @width: Width of the frame-buffer. */
 	__u32 width;
+	/** @height: Height of the frame-buffer. */
 	__u32 height;
-	__u32 pixel_format; /* fourcc code from drm_fourcc.h */
-	__u32 flags; /* see above flags */
+	/**
+	 * @pixel_format: FourCC format code, see ``DRM_FORMAT_*`` constants in
+	 * ``drm_fourcc.h``.
+	 */
+	__u32 pixel_format;
+	/**
+	 * @flags: Frame-buffer flags (see &DRM_MODE_FB_INTERLACED and
+	 * &DRM_MODE_FB_MODIFIERS).
+	 */
+	__u32 flags;
 
-	/*
-	 * In case of planar formats, this ioctl allows up to 4
-	 * buffer objects with offsets and pitches per plane.
-	 * The pitch and offset order is dictated by the fourcc,

_service:tar_scm:libdrm-2.4.115.tar.xz/intel/meson.build -> _service:tar_scm:libdrm-2.4.119.tar.xz/intel/meson.build Changed

_service:tar_scm:libdrm-2.4.115.tar.xz/intel/uthash.h -> _service:tar_scm:libdrm-2.4.119.tar.xz/intel/uthash.h Changed

_service:tar_scm:libdrm-2.4.115.tar.xz/meson.build -> _service:tar_scm:libdrm-2.4.119.tar.xz/meson.build Changed

@@ -21,9 +21,9 @@
 project(
   'libdrm',
   'c',
-  version : '2.4.115',
+  version : '2.4.119',
   license : 'MIT',
-  meson_version : '>= 0.53',
+  meson_version : '>= 0.59',
   default_options : 'buildtype=debugoptimized', 'c_std=c11',
 )
 
@@ -40,11 +40,6 @@
 with_install_tests = get_option('install-test-programs')
 with_tests = get_option('tests')
 
-if 'freebsd', 'dragonfly', 'netbsd'.contains(host_machine.system())
-  dep_pthread_stubs = dependency('pthread-stubs', version : '>= 0.4')
-else
-  dep_pthread_stubs = 
-endif
 dep_threads = dependency('threads')
 
 cc = meson.get_compiler('c')
@@ -89,109 +84,61 @@
 
 dep_pciaccess = dependency('pciaccess', version : '>= 0.10', required : get_option('intel'))
 
-with_intel = false
-_intel = get_option('intel')
-if not _intel.disabled()
-  if _intel.enabled() and not with_atomics
-    error('libdrm_intel requires atomics.')
-  else
-    with_intel = (_intel.enabled() or host_machine.cpu_family().startswith('x86')) and with_atomics and dep_pciaccess.found()
-  endif
-endif
+with_intel = get_option('intel') \
+  .require(with_atomics, error_message : 'libdrm_intel requires atomics') \
+  .require(dep_pciaccess.found(), error_message : 'libdrm_intel requires libpciaccess') \
+  .disable_auto_if(not host_machine.cpu_family().startswith('x86')) \
+  .allowed()
 summary('Intel', with_intel)
 
-with_radeon = false
-_radeon = get_option('radeon')
-if not _radeon.disabled()
-  if _radeon.enabled() and not with_atomics
-    error('libdrm_radeon requires atomics.')
-  endif
-  with_radeon = with_atomics
-endif
+with_radeon = get_option('radeon') \
+  .require(with_atomics, error_message : 'libdrm_radeon requires atomics') \
+  .allowed()
 summary('Radeon', with_radeon)
 
-with_amdgpu = false
-_amdgpu = get_option('amdgpu')
-if not _amdgpu.disabled()
-  if _amdgpu.enabled() and not with_atomics
-    error('libdrm_amdgpu requires atomics.')
-  endif
-  with_amdgpu = with_atomics
-endif
+with_amdgpu = get_option('amdgpu') \
+  .require(with_atomics, error_message : 'libdrm_amdgpu requires atomics') \
+  .allowed()
 summary('AMDGPU', with_amdgpu)
 
-with_nouveau = false
-_nouveau = get_option('nouveau')
-if not _nouveau.disabled()
-  if _nouveau.enabled() and not with_atomics
-    error('libdrm_nouveau requires atomics.')
-  endif
-  with_nouveau = with_atomics
-endif
+with_nouveau = get_option('nouveau') \
+  .require(with_atomics, error_message : 'libdrm_nouveau requires atomics') \
+  .allowed()
 summary('Nouveau', with_nouveau)
 
-with_vmwgfx = false
-_vmwgfx = get_option('vmwgfx')
-if not _vmwgfx.disabled()
-  with_vmwgfx = true
-endif
+with_vmwgfx = get_option('vmwgfx').allowed()
 summary('vmwgfx', with_vmwgfx)
 
-with_omap = false
-_omap = get_option('omap')
-if _omap.enabled()
-  if not with_atomics
-    error('libdrm_omap requires atomics.')
-  endif
-  with_omap = true
-endif
+with_omap = get_option('omap') \
+  .require(with_atomics, error_message : 'libdrm_omap requires atomics') \
+  .enabled()
 summary('OMAP', with_omap)
 
-with_freedreno = false
-_freedreno = get_option('freedreno')
-if not _freedreno.disabled()
-  if _freedreno.enabled() and not with_atomics
-    error('libdrm_freedreno requires atomics.')
-  else
-    with_freedreno = (_freedreno.enabled() or 'arm', 'aarch64'.contains(host_machine.cpu_family())) and with_atomics
-  endif
-endif
+with_freedreno = get_option('freedreno') \
+  .require(with_atomics, error_message : 'libdrm_freedreno requires atomics') \
+  .disable_auto_if(not 'arm', 'aarch64'.contains(host_machine.cpu_family())) \
+  .allowed()
 summary('Freedreno', with_freedreno)
 summary('Freedreon-kgsl', with_freedreno_kgsl)
 
-with_tegra = false
-_tegra = get_option('tegra')
-if _tegra.enabled()
-  if not with_atomics
-    error('libdrm_tegra requires atomics.')
-  endif
-  with_tegra = true
-endif
+with_tegra = get_option('tegra') \
+  .require(with_atomics, error_message : 'libdrm_tegra requires atomics') \
+  .disable_auto_if(not 'arm', 'aarch64'.contains(host_machine.cpu_family())) \
+  .enabled()
 summary('Tegra', with_tegra)
 
-with_etnaviv = false
-_etnaviv = get_option('etnaviv')
-if not _etnaviv.disabled()
-  if _etnaviv.enabled() and not with_atomics
-    error('libdrm_etnaviv requires atomics.')
-  endif
-  with_etnaviv = _etnaviv.enabled() or (
-    with_atomics and 
-      'loongarch64', 'mips', 'mips64',
-      'arm', 'aarch64', 'arc',
-    .contains(host_machine.cpu_family())
-  )
-endif
+with_etnaviv = get_option('etnaviv') \
+  .require(with_atomics, error_message : 'libdrm_etnaviv requires atomics') \
+  .disable_auto_if(not 'arm', 'aarch64', 'arc', 'mips', 'mips64', 'loongarch64'.contains(host_machine.cpu_family())) \
+  .allowed()
 summary('Etnaviv', with_etnaviv)
 
 with_exynos = get_option('exynos').enabled()
 summary('EXYNOS', with_exynos)
 
-with_vc4 = false
-_vc4 = get_option('vc4')
-if not _vc4.disabled()
-  with_vc4 = _vc4.enabled() or 'arm', 'aarch64'.contains(host_machine.cpu_family())
-endif
+with_vc4 = get_option('vc4') \
+  .disable_auto_if(not 'arm', 'aarch64'.contains(host_machine.cpu_family())) \
+  .allowed()
 summary('VC4', with_vc4)
 
 # Among others FreeBSD does not have a separate dl library.
@@ -279,6 +226,11 @@
   error('cannot enable freedreno-kgsl without freedreno support')
 endif
 config.set10('_GNU_SOURCE', true)
+
+if target_machine.endian() == 'big'
+  config.set('HAVE_BIG_ENDIAN', 1)
+endif
+
 config_file = configure_file(
   configuration : config,
   output : 'config.h',
@@ -319,7 +271,7 @@
   args : 
     '--lib', libdrm,
     '--symbols-file', files('core-symbols.txt'),
-    '--nm', prog_nm.path(),
+    '--nm', prog_nm.full_path(),
   ,
 )

_service:tar_scm:libdrm-2.4.115.tar.xz/nouveau/meson.build -> _service:tar_scm:libdrm-2.4.119.tar.xz/nouveau/meson.build Changed

_service:tar_scm:libdrm-2.4.115.tar.xz/nouveau/nouveau-symbols.txt -> _service:tar_scm:libdrm-2.4.119.tar.xz/nouveau/nouveau-symbols.txt Changed

_service:tar_scm:libdrm-2.4.115.tar.xz/nouveau/nouveau.c -> _service:tar_scm:libdrm-2.4.119.tar.xz/nouveau/nouveau.c Changed

_service:tar_scm:libdrm-2.4.115.tar.xz/nouveau/nouveau.h -> _service:tar_scm:libdrm-2.4.119.tar.xz/nouveau/nouveau.h Changed

_service:tar_scm:libdrm-2.4.115.tar.xz/omap/meson.build -> _service:tar_scm:libdrm-2.4.119.tar.xz/omap/meson.build Changed

_service:tar_scm:libdrm-2.4.115.tar.xz/radeon/meson.build -> _service:tar_scm:libdrm-2.4.119.tar.xz/radeon/meson.build Changed

_service:tar_scm:libdrm-2.4.115.tar.xz/tegra/meson.build -> _service:tar_scm:libdrm-2.4.119.tar.xz/tegra/meson.build Changed

_service:tar_scm:libdrm-2.4.115.tar.xz/tests/amdgpu/amdgpu_stress.c -> _service:tar_scm:libdrm-2.4.119.tar.xz/tests/amdgpu/amdgpu_stress.c Changed

@@ -30,6 +30,7 @@
 #include <errno.h>
 #include <unistd.h>
 #include <stdlib.h>
+#include <inttypes.h>
 
 #include "drm.h"
 #include "xf86drmMode.h"
@@ -175,7 +176,7 @@
 
 	resourcesnum_buffers = bo;
 	virtualnum_buffers = addr;
-	fprintf(stdout, "Allocated BO number %u at 0x%lx, domain 0x%x, size %lu\n",
+	fprintf(stdout, "Allocated BO number %u at 0x%" PRIx64 ", domain 0x%x, size %" PRIu64 "\n",
 		num_buffers++, addr, domain, size);
 	return 0;
 }
@@ -273,7 +274,7 @@
 	delta = stop.tv_nsec + stop.tv_sec * 1000000000UL;
 	delta -= start.tv_nsec + start.tv_sec * 1000000000UL;
 
-	fprintf(stdout, "Submitted %u IBs to copy from %u(%lx) to %u(%lx) %lu bytes took %lu usec\n",
+	fprintf(stdout, "Submitted %u IBs to copy from %u(%" PRIx64 ") to %u(%" PRIx64 ") %" PRIu64 " bytes took %" PRIu64 " usec\n",
 		count, from, virtualfrom, to, virtualto, copied, delta / 1000);
 	return 0;
 }
@@ -293,7 +294,7 @@
 	char ext2;
 
 	ext0 = 0;
-	if (sscanf(optarg, "%li%1kmgKMG", &size, ext) < 1) {
+	if (sscanf(optarg, "%" PRIi64 "%1kmgKMG", &size, ext) < 1) {
 		fprintf(stderr, "Can't parse size arg: %s\n", optarg);
 		exit(EXIT_FAILURE);
 	}
@@ -375,7 +376,7 @@
 			next_arg(argc, argv, "Missing buffer size");
 			size = parse_size();
 			if (size < getpagesize()) {
-				fprintf(stderr, "Buffer size to small %lu\n", size);
+				fprintf(stderr, "Buffer size to small %" PRIu64 "\n", size);
 				exit(EXIT_FAILURE);
 			}
 			r = alloc_bo(domain, size);

_service:tar_scm:libdrm-2.4.115.tar.xz/tests/amdgpu/amdgpu_test.c -> _service:tar_scm:libdrm-2.4.119.tar.xz/tests/amdgpu/amdgpu_test.c Changed

@@ -296,18 +296,23 @@
 
 /** Help string for command line parameters */
 static const char usage =
-	"Usage: %s -hlpr <-s <suite id>> -t <test id> -f "
-	"-b <pci_bus_id> -d <pci_device_id>\n"
-	"where:\n"
-	"       l - Display all suites and their tests\n"
-	"       r - Run the tests on render node\n"
-	"       b - Specify device's PCI bus id to run tests\n"
-	"       d - Specify device's PCI device id to run tests (optional)\n"
-	"       p - Display information of AMDGPU devices in system\n"
-	"       f - Force executing inactive suite or test\n"
-	"       h - Display this help\n";
+	"Usage: %s -hlpr -s <suite id> -e <s>.<t> -e ... -t <test id> -f "
+	"-b <pci_bus_id> -d <pci_device_id>\n"
+	"Where,\n"
+	"  -b      Specify device's PCI bus id to run tests\n"
+	"  -d      Specify device's PCI device id to run tests (optional)\n"
+	"  -e <s>.<t>  Disable test <t> of suite <s>. If only <s> is given, then disable\n"
+	"          the whole suite. Can be specified more than once on the command line\n"
+	"          to disable multiple tests or suites.\n"
+	"  -f      Force executing inactive suite or test\n"
+	"  -h      Display this help\n"
+	"  -l      Display all test suites and their tests\n"
+	"  -p      Display information of AMDGPU devices in system\n"
+	"  -r      Run the tests on render node\n"
+	"  -s <s>  Enable only test suite <s>\n"
+	"  -t <t>  Enable only test <t> of test suite <s>\n";
 /** Specified options strings for getopt */
-static const char options   = "hlrps:t:b:d:f";
+static const char options   = "hlrps:t:e:b:d:f";
 
 /* Open AMD devices.
  * Return the number of AMD device opened.
@@ -662,6 +667,48 @@
 #endif
 }
 
+#ifndef ARRAY_SIZE
+#define ARRAY_SIZE(_A) (sizeof(_A)/sizeof(_A0))
+#endif
+
+static void amdgpu_test_disable(long suite, long test)
+{
+	const char *suite_name;
+
+	if (suite < 1)
+		return;
+
+	/* The array is 0-based, so subract 1. */
+	suite--;
+	if (suite >= ARRAY_SIZE(suites) - 1)
+		return;
+
+	suite_name = suitessuite.pName;
+	if (test < 1) {
+		fprintf(stderr, "Deactivating suite %s\n", suite_name);
+		amdgpu_set_suite_active(suite_name, CU_FALSE);
+	} else {
+		int ii;
+
+		/* The array is 0-based so subtract 1. */
+		test--;
+		for (ii = 0; suitessuite.pTestsii.pName; ii++) {
+			if (ii == test) {
+				fprintf(stderr, "Deactivating %s:%s\n",
+					suite_name,
+					suitessuite.pTestsii.pName);
+				amdgpu_set_test_active(suite_name,
+						       suitessuite.pTestsii.pName,
+						       CU_FALSE);
+				break;
+			}
+		}
+
+		if (suitessuite.pTestsii.pName == NULL)
+			fprintf(stderr, "No such suite.test %ld.%ld\n", suite, test);
+	}
+}
+
 /* The main() function for setting up and running the tests.
  * Returns a CUE_SUCCESS on successful running, another
  * CUnit error code on failure.
@@ -680,48 +727,21 @@
 	int display_list = 0;
 	int force_run = 0;
 
-	for (i = 0; i < MAX_CARDS_SUPPORTED; i++)
-		drm_amdgpui = -1;
-
-
-	/* Parse command line string */
+	/* Parse command line string.
+	 * Process various command line options as early as possible.
+	 */
 	opterr = 0;		/* Do not print error messages from getopt */
 	while ((c = getopt(argc, argv, options)) != -1) {
 		switch (c) {
-		case 'l':
-			display_list = 1;
-			break;
-		case 's':
-			suite_id = atoi(optarg);
-			break;
-		case 't':
-			test_id = atoi(optarg);
-			break;
-		case 'b':
-			pci_bus_id = atoi(optarg);
-			break;
-		case 'd':
-			sscanf(optarg, "%x", &pci_device_id);
-			break;
-		case 'p':
-			display_devices = 1;
-			break;
-		case 'r':
-			open_render_node = 1;
-			break;
-		case 'f':
-			force_run = 1;
-			break;
-		case '?':
 		case 'h':
 			fprintf(stderr, usage, argv0);
 			exit(EXIT_SUCCESS);
-		default:
-			fprintf(stderr, usage, argv0);
-			exit(EXIT_FAILURE);
 		}
 	}
 
+	for (i = 0; i < MAX_CARDS_SUPPORTED; i++)
+		drm_amdgpui = -1;
+
 	if (amdgpu_open_devices(open_render_node) <= 0) {
 		perror("Cannot open AMDGPU device");
 		exit(EXIT_FAILURE);
@@ -732,12 +752,37 @@
 		exit(EXIT_FAILURE);
 	}
 
+	/* Parse command line string */
+	opterr = 0;		/* Do not print error messages from getopt */
+	optind = 1;
+	while ((c = getopt(argc, argv, options)) != -1) {
+		switch (c) {
+		case 'p':
+			display_devices = 1;
+			break;
+		}
+	}
+
 	if (display_devices) {
 		amdgpu_print_devices();
 		amdgpu_close_devices();
 		exit(EXIT_SUCCESS);
 	}
 
+	/* Parse command line string */
+	opterr = 0;		/* Do not print error messages from getopt */
+	optind = 1;
+	while ((c = getopt(argc, argv, options)) != -1) {
+		switch (c) {
+		case 'b':
+			pci_bus_id = atoi(optarg);
+			break;
+		case 'd':
+			sscanf(optarg, "%x", &pci_device_id);
+			break;
+		}
+	}
+
 	if (pci_bus_id > 0 || pci_device_id) {
 		/* A device was specified to run the test */
 		test_device_index = amdgpu_find_device(pci_bus_id,
@@ -780,11 +825,85 @@
 	/* Disable suites and individual tests based on misc. conditions */
 	amdgpu_disable_suites();
 
+	/* Parse command line string */
+	opterr = 0;		/* Do not print error messages from getopt */
+	optind = 1;
+	while ((c = getopt(argc, argv, options)) != -1) {
+		switch (c) {
+		case 'l':
+			display_list = 1;
+			break;
+		}
+	}
+
 	if (display_list) {
 		display_test_suites();
 		goto end;
 	}
 
+	/* Parse command line string */
+	opterr = 0;		/* Do not print error messages from getopt */
+	optind = 1;

_service:tar_scm:libdrm-2.4.115.tar.xz/tests/amdgpu/hotunplug_tests.c -> _service:tar_scm:libdrm-2.4.119.tar.xz/tests/amdgpu/hotunplug_tests.c Changed

_service:tar_scm:libdrm-2.4.115.tar.xz/tests/amdgpu/vcn_tests.c -> _service:tar_scm:libdrm-2.4.119.tar.xz/tests/amdgpu/vcn_tests.c Changed

@@ -177,6 +177,7 @@
 static uint32_t *ib_size_in_dw;
 
 static rvcn_decode_buffer_t *decode_buffer;
+struct amdgpu_vcn_bo session_ctx_buf;
 
 static amdgpu_bo_handle resourcesMAX_RESOURCES;
 static unsigned num_resources;
@@ -561,7 +562,9 @@
 
 	num_resources  = 0;
 	alloc_resource(&msg_buf, 4096, AMDGPU_GEM_DOMAIN_GTT);
+	alloc_resource(&session_ctx_buf, 32 * 4096, AMDGPU_GEM_DOMAIN_VRAM);
 	resourcesnum_resources++ = msg_buf.handle;
+	resourcesnum_resources++ = session_ctx_buf.handle;
 	resourcesnum_resources++ = ib_handle;
 
 	r = amdgpu_bo_cpu_map(msg_buf.handle, (void **)&msg_buf.ptr);
@@ -571,9 +574,11 @@
 	memcpy(msg_buf.ptr, vcn_dec_create_msg, sizeof(vcn_dec_create_msg));
 
 	len = 0;
-	if (vcn_dec_sw_ring == true)
+
+	vcn_dec_cmd(session_ctx_buf.addr, 5, &len);
+	if (vcn_dec_sw_ring == true) {
 		vcn_dec_cmd(msg_buf.addr, 0, &len);
-	else {
+	} else {
 		ib_cpulen++ = regvcn_reg_index.data0;
 		ib_cpulen++ = msg_buf.addr;
 		ib_cpulen++ = regvcn_reg_index.data1;
@@ -650,6 +655,7 @@
 	dt_addr = ALIGN(dpb_addr + dpb_size, 4*1024);
 
 	len = 0;
+	vcn_dec_cmd(session_ctx_buf.addr, 0x5, &len);
 	vcn_dec_cmd(msg_addr, 0x0, &len);
 	vcn_dec_cmd(dpb_addr, 0x1, &len);
 	vcn_dec_cmd(dt_addr, 0x2, &len);
@@ -702,9 +708,10 @@
 	memcpy(msg_buf.ptr, vcn_dec_destroy_msg, sizeof(vcn_dec_destroy_msg));
 
 	len = 0;
-	if (vcn_dec_sw_ring == true)
+	vcn_dec_cmd(session_ctx_buf.addr, 5, &len);
+	if (vcn_dec_sw_ring == true) {
 		vcn_dec_cmd(msg_buf.addr, 0, &len);
-	else {
+	} else {
 		ib_cpulen++ = regvcn_reg_index.data0;
 		ib_cpulen++ = msg_buf.addr;
 		ib_cpulen++ = regvcn_reg_index.data1;
@@ -727,6 +734,7 @@
 	CU_ASSERT_EQUAL(r, 0);
 
 	free_resource(&msg_buf);
+	free_resource(&session_ctx_buf);
 }
 
 static void amdgpu_cs_vcn_enc_create(void)
@@ -808,6 +816,8 @@
 	ib_cpulen++ = 0;
 	ib_cpulen++ = 0;	/* pre encode mode */
 	ib_cpulen++ = 0;	/* chroma enabled : false */
+	ib_cpulen++ = 0;
+	ib_cpulen++ = 0;
 	*st_size = (len - st_offset) * 4;
 
 	/* slice control */
@@ -829,7 +839,7 @@
 	ib_cpulen++ = 1;	/* quarter pel enabled */
 	ib_cpulen++ = 100;	/* BASELINE profile */
 	ib_cpulen++ = 11;	/* level */
-	if (vcn_ip_version_major == 3) {
+	if (vcn_ip_version_major >= 3) {
 		ib_cpulen++ = 0;	/* b_picture_enabled */
 		ib_cpulen++ = 0;	/* weighted_bipred_idc */
 	}
@@ -870,7 +880,7 @@
 	ib_cpulen++ = 0;	/* scene change sensitivity */
 	ib_cpulen++ = 0;	/* scene change min idr interval */
 	ib_cpulen++ = 0;
-	if (vcn_ip_version_major == 3)
+	if (vcn_ip_version_major >= 3)
 		ib_cpulen++ = 0;
 	*st_size = (len - st_offset) * 4;
 
@@ -913,6 +923,7 @@
 	ib_cpulen++ = 1;
 	ib_cpulen++ = 0;
 	ib_cpulen++ = 1;
+	ib_cpulen++ = 0;
 	*st_size = (len - st_offset) * 4;
 
 	/* op init rc */
@@ -1265,10 +1276,16 @@
 	CU_ASSERT_EQUAL(r, 0);
 }
 
+static void amdgpu_cs_vcn_ib_zero_count(int *len, int num)
+{
+	for (int i = 0; i < num; i++)
+		ib_cpu(*len)++ = 0;
+}
+
 static void amdgpu_cs_vcn_enc_encode_frame(int frame_type)
 {
-	struct amdgpu_vcn_bo bs_buf, fb_buf, vbv_buf;
-	int len, r, i;
+	struct amdgpu_vcn_bo bs_buf, fb_buf, input_buf;
+	int len, r;
 	unsigned width = 160, height = 128, buf_size;
 	uint32_t *p_task_size = NULL;
 	uint32_t task_offset = 0, st_offset;
@@ -1288,12 +1305,12 @@
 	num_resources = 0;
 	alloc_resource(&bs_buf, 4096, AMDGPU_GEM_DOMAIN_GTT);
 	alloc_resource(&fb_buf, 4096, AMDGPU_GEM_DOMAIN_GTT);
-	alloc_resource(&vbv_buf, buf_size, AMDGPU_GEM_DOMAIN_GTT);
+	alloc_resource(&input_buf, buf_size, AMDGPU_GEM_DOMAIN_GTT);
 	resourcesnum_resources++ = enc_buf.handle;
 	resourcesnum_resources++ = cpb_buf.handle;
 	resourcesnum_resources++ = bs_buf.handle;
 	resourcesnum_resources++ = fb_buf.handle;
-	resourcesnum_resources++ = vbv_buf.handle;
+	resourcesnum_resources++ = input_buf.handle;
 	resourcesnum_resources++ = ib_handle;
 
 
@@ -1305,13 +1322,13 @@
 	memset(fb_buf.ptr, 0, 4096);
 	r = amdgpu_bo_cpu_unmap(fb_buf.handle);
 
-	r = amdgpu_bo_cpu_map(vbv_buf.handle, (void **)&vbv_buf.ptr);
+	r = amdgpu_bo_cpu_map(input_buf.handle, (void **)&input_buf.ptr);
 	CU_ASSERT_EQUAL(r, 0);
 
 	for (int i = 0; i < ALIGN(height, 32) * 3 / 2; i++)
-		memcpy(vbv_buf.ptr + i * ALIGN(width, 256), frame + i * width, width);
+		memcpy(input_buf.ptr + i * ALIGN(width, 256), frame + i * width, width);
 
-	r = amdgpu_bo_cpu_unmap(vbv_buf.handle);
+	r = amdgpu_bo_cpu_unmap(input_buf.handle);
 	CU_ASSERT_EQUAL(r, 0);
 
 	len = 0;
@@ -1346,7 +1363,7 @@
 		if(vcn_ip_version_major == 1)
 			ib_cpulen++ = 0x00000020;	/* RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU vcn 1 */
 		else
-			ib_cpulen++ = 0x0000000a;	/* RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU vcn 2,3 */
+			ib_cpulen++ = 0x0000000a;	/* RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU other vcn */
 		ib_cpulen++ = 0x00000002;	/* RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS */
 		ib_cpulen++ = 0x00000011;	/* sps len */
 		ib_cpulen++ = 0x00000001;	/* start code */
@@ -1362,7 +1379,7 @@
 		if(vcn_ip_version_major == 1)
 			ib_cpulen++ = 0x00000020;	/* RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU vcn 1*/
 		else
-			ib_cpulen++ = 0x0000000a;	/* RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU vcn 2,3*/
+			ib_cpulen++ = 0x0000000a;	/* RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU other vcn*/
 		ib_cpulen++ = 0x00000003;	/* RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS */
 		ib_cpulen++ = 0x00000008;	/* pps len */
 		ib_cpulen++ = 0x00000001;	/* start code */
@@ -1376,7 +1393,7 @@
 	if(vcn_ip_version_major == 1)
 		ib_cpulen++ = 0x0000000a; /* RENCODE_IB_PARAM_SLICE_HEADER vcn 1 */
 	else
-		ib_cpulen++ = 0x0000000b; /* RENCODE_IB_PARAM_SLICE_HEADER vcn 2,3 */
+		ib_cpulen++ = 0x0000000b; /* RENCODE_IB_PARAM_SLICE_HEADER other vcn */
 	if (frame_type == 2) {
 		ib_cpulen++ = 0x65000000;
 		ib_cpulen++ = 0x11040000;
@@ -1385,8 +1402,7 @@
 		ib_cpulen++ = 0x34210000;
 	}
 	ib_cpulen++ = 0xe0000000;
-	for(i = 0; i < 13; i++)
-		ib_cpulen++ = 0x00000000;
+	amdgpu_cs_vcn_ib_zero_count(&len, 13);
 
 	ib_cpulen++ = 0x00000001;
 	ib_cpulen++ = 0x00000008;
@@ -1398,24 +1414,22 @@
 	ib_cpulen++ = 0x00000000;
 	ib_cpulen++ = 0x00000001;
 	ib_cpulen++ = 0x00000003;
-	for(i = 0; i < 22; i++)
-		ib_cpulen++ = 0x00000000;
-
+	amdgpu_cs_vcn_ib_zero_count(&len, 22);
 	*st_size = (len - st_offset) * 4;
 
 	/* encode params */
 	st_offset = len;
 	st_size = &ib_cpulen++;	/* size */
 	if(vcn_ip_version_major == 1)
-		ib_cpulen++ = 0x0000000b;	/* RENCODE_IB_PARAM_ENCODE_PARAMS vcn 1*/
+		ib_cpulen++ = 0x0000000b;	/* RENCODE_IB_PARAM_ENCODE_PARAMS vcn 1 */

_service:tar_scm:libdrm-2.4.115.tar.xz/tests/modetest/buffers.c -> _service:tar_scm:libdrm-2.4.119.tar.xz/tests/modetest/buffers.c Changed

@@ -124,16 +124,36 @@
 	int ret;
 
 	switch (format) {
+	case DRM_FORMAT_C1:
+		bpp = 1;
+		break;
+
+	case DRM_FORMAT_C2:
+		bpp = 2;
+		break;
+
+	case DRM_FORMAT_C4:
+		bpp = 4;
+		break;
+
 	case DRM_FORMAT_C8:
 	case DRM_FORMAT_NV12:
 	case DRM_FORMAT_NV21:
 	case DRM_FORMAT_NV16:
 	case DRM_FORMAT_NV61:
+	case DRM_FORMAT_NV24:
+	case DRM_FORMAT_NV42:
 	case DRM_FORMAT_YUV420:
 	case DRM_FORMAT_YVU420:
 		bpp = 8;
 		break;
 
+	case DRM_FORMAT_NV15:
+	case DRM_FORMAT_NV20:
+	case DRM_FORMAT_NV30:
+		bpp = 10;
+		break;
+
 	case DRM_FORMAT_ARGB4444:
 	case DRM_FORMAT_XRGB4444:
 	case DRM_FORMAT_ABGR4444:
@@ -144,6 +164,7 @@
 	case DRM_FORMAT_BGRX4444:
 	case DRM_FORMAT_ARGB1555:
 	case DRM_FORMAT_XRGB1555:
+	case DRM_FORMAT_XRGB1555 | DRM_FORMAT_BIG_ENDIAN:
 	case DRM_FORMAT_ABGR1555:
 	case DRM_FORMAT_XBGR1555:
 	case DRM_FORMAT_RGBA5551:
@@ -151,6 +172,7 @@
 	case DRM_FORMAT_BGRA5551:
 	case DRM_FORMAT_BGRX5551:
 	case DRM_FORMAT_RGB565:
+	case DRM_FORMAT_RGB565 | DRM_FORMAT_BIG_ENDIAN:
 	case DRM_FORMAT_BGR565:
 	case DRM_FORMAT_UYVY:
 	case DRM_FORMAT_VYUY:
@@ -198,6 +220,7 @@
 	switch (format) {
 	case DRM_FORMAT_NV12:
 	case DRM_FORMAT_NV21:
+	case DRM_FORMAT_NV15:
 	case DRM_FORMAT_YUV420:
 	case DRM_FORMAT_YVU420:
 		virtual_height = height * 3 / 2;
@@ -205,9 +228,16 @@
 
 	case DRM_FORMAT_NV16:
 	case DRM_FORMAT_NV61:
+	case DRM_FORMAT_NV20:
 		virtual_height = height * 2;
 		break;
 
+	case DRM_FORMAT_NV24:
+	case DRM_FORMAT_NV42:
+	case DRM_FORMAT_NV30:
+		virtual_height = height * 3;
+		break;
+
 	default:
 		virtual_height = height;
 		break;
@@ -244,6 +274,8 @@
 	case DRM_FORMAT_NV21:
 	case DRM_FORMAT_NV16:
 	case DRM_FORMAT_NV61:
+	case DRM_FORMAT_NV15:
+	case DRM_FORMAT_NV20:
 		offsets0 = 0;
 		handles0 = bo->handle;
 		pitches0 = bo->pitch;
@@ -255,6 +287,20 @@
 		planes1 = virtual + offsets1;
 		break;
 
+	case DRM_FORMAT_NV24:
+	case DRM_FORMAT_NV42:
+	case DRM_FORMAT_NV30:
+		offsets0 = 0;
+		handles0 = bo->handle;
+		pitches0 = bo->pitch;
+		pitches1 = pitches0 * 2;
+		offsets1 = pitches0 * height;
+		handles1 = bo->handle;
+
+		planes0 = virtual;
+		planes1 = virtual + offsets1;
+		break;
+
 	case DRM_FORMAT_YUV420:
 	case DRM_FORMAT_YVU420:
 		offsets0 = 0;
@@ -272,6 +318,9 @@
 		planes2 = virtual + offsets2;
 		break;
 
+	case DRM_FORMAT_C1:
+	case DRM_FORMAT_C2:
+	case DRM_FORMAT_C4:
 	case DRM_FORMAT_C8:
 	case DRM_FORMAT_ARGB4444:
 	case DRM_FORMAT_XRGB4444:
@@ -283,6 +332,7 @@
 	case DRM_FORMAT_BGRX4444:
 	case DRM_FORMAT_ARGB1555:
 	case DRM_FORMAT_XRGB1555:
+	case DRM_FORMAT_XRGB1555 | DRM_FORMAT_BIG_ENDIAN:
 	case DRM_FORMAT_ABGR1555:
 	case DRM_FORMAT_XBGR1555:
 	case DRM_FORMAT_RGBA5551:
@@ -290,6 +340,7 @@
 	case DRM_FORMAT_BGRA5551:
 	case DRM_FORMAT_BGRX5551:
 	case DRM_FORMAT_RGB565:
+	case DRM_FORMAT_RGB565 | DRM_FORMAT_BIG_ENDIAN:
 	case DRM_FORMAT_BGR565:
 	case DRM_FORMAT_BGR888:
 	case DRM_FORMAT_RGB888:
@@ -338,3 +389,22 @@
 
 	free(bo);
 }
+
+void bo_dump(struct bo *bo, const char *filename)
+{
+	FILE *fp;
+
+	if (!bo || !filename)
+		return;
+
+	fp = fopen(filename, "wb");
+	if (fp) {
+		void *addr;
+
+		bo_map(bo, &addr);
+		printf("Dumping buffer %p to file %s.\n", bo->ptr, filename);
+		fwrite(bo->ptr, 1, bo->size, fp);
+		bo_unmap(bo);
+		fclose(fp);
+	}
+}

_service:tar_scm:libdrm-2.4.115.tar.xz/tests/modetest/buffers.h -> _service:tar_scm:libdrm-2.4.119.tar.xz/tests/modetest/buffers.h Changed

_service:tar_scm:libdrm-2.4.115.tar.xz/tests/modetest/meson.build -> _service:tar_scm:libdrm-2.4.119.tar.xz/tests/modetest/meson.build Changed

_service:tar_scm:libdrm-2.4.115.tar.xz/tests/modetest/modetest.c -> _service:tar_scm:libdrm-2.4.119.tar.xz/tests/modetest/modetest.c Changed

@@ -70,6 +70,7 @@
 
 static enum util_fill_pattern primary_fill = UTIL_PATTERN_SMPTE;
 static enum util_fill_pattern secondary_fill = UTIL_PATTERN_TILES;
+static drmModeModeInfo user_mode;
 
 struct crtc {
 	drmModeCrtc *crtc;
@@ -128,6 +129,7 @@
 
 	int use_atomic;
 	drmModeAtomicReq *req;
+	int32_t writeback_fence_fd;
 };
 
 static inline int64_t U642I64(uint64_t val)
@@ -137,8 +139,19 @@
 
 static float mode_vrefresh(drmModeModeInfo *mode)
 {
-	return  mode->clock * 1000.00
-			/ (mode->htotal * mode->vtotal);
+	unsigned int num, den;
+
+	num = mode->clock;
+	den = mode->htotal * mode->vtotal;
+
+	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
+		num *= 2;
+	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
+		den *= 2;
+	if (mode->vscan > 1)
+		den *= mode->vscan;
+
+	return num * 1000.00 / den;
 }
 
 #define bit_name_fn(res)					\
@@ -317,7 +330,7 @@
 			printf(": ");
 		}
 
-		printf(" %s", modifier_to_string(iter.mod));
+		printf(" %s(0x%"PRIx64")", modifier_to_string(iter.mod), iter.mod);
 	}
 
 	printf("\n");
@@ -804,13 +817,15 @@
 	unsigned int num_cons;
 	uint32_t crtc_id;
 	char mode_str64;
-	char format_str5;
+	char format_str8; /* need to leave room for "_BE" and terminating \0 */
 	float vrefresh;
 	unsigned int fourcc;
 	drmModeModeInfo *mode;
 	struct crtc *crtc;
 	unsigned int fb_id2, current_fb_id;
 	struct timeval start;
+	unsigned int out_fb_id;
+	struct bo *out_bo;
 
 	int swap_count;
 };
@@ -826,7 +841,7 @@
 	unsigned int old_fb_id;
 	struct bo *bo;
 	struct bo *old_bo;
-	char format_str5; /* need to leave room for terminating \0 */
+	char format_str8; /* need to leave room for "_BE" and terminating \0 */
 	unsigned int fourcc;
 };
 
@@ -839,7 +854,25 @@
 	int i;
 
 	connector = get_connector_by_id(dev, con_id);
-	if (!connector || !connector->count_modes)
+	if (!connector)
+		return NULL;
+
+	if (strchr(mode_str, ',')) {
+		i = sscanf(mode_str, "%hu,%hu,%hu,%hu,%hu,%hu,%hu,%hu",
+			     &user_mode.hdisplay, &user_mode.hsync_start,
+			     &user_mode.hsync_end, &user_mode.htotal,
+			     &user_mode.vdisplay, &user_mode.vsync_start,
+			     &user_mode.vsync_end, &user_mode.vtotal);
+		if (i == 8) {
+			user_mode.clock = roundf(user_mode.htotal * user_mode.vtotal * vrefresh / 1000);
+			user_mode.vrefresh = roundf(vrefresh);
+			snprintf(user_mode.name, sizeof(user_mode.name), "custom%dx%d", user_mode.hdisplay, user_mode.vdisplay);
+
+			return &user_mode;
+		}
+	}
+
+	if (!connector->count_modes)
 		return NULL;
 
 	/* Pick by Index */
@@ -1040,7 +1073,7 @@
 
 	if (ret < 0)
 		fprintf(stderr, "failed to set %s %i property %s to %" PRIu64 ": %s\n",
-			obj_type, p->obj_id, p->name, p->value, strerror(errno));
+			obj_type, p->obj_id, p->name, p->value, strerror(-ret));
 
 	return true;
 }
@@ -1116,15 +1149,23 @@
 static void set_gamma(struct device *dev, unsigned crtc_id, unsigned fourcc)
 {
 	unsigned blob_id = 0;
+	const struct util_format_info *info;
 	/* TODO: support 1024-sized LUTs, when the use-case arises */
 	struct drm_color_lut gamma_lut256;
 	int i, ret;
 
-	if (fourcc == DRM_FORMAT_C8) {
-		/* TODO: Add C8 support for more patterns */
-		util_smpte_c8_gamma(256, gamma_lut);
+	info = util_format_info_find(fourcc);
+	if (info->ncolors) {
+		memset(gamma_lut, 0, sizeof(gamma_lut));
+		/* TODO: Add index support for more patterns */
+		util_smpte_fill_lut(info->ncolors, gamma_lut);
 		drmModeCreatePropertyBlob(dev->fd, gamma_lut, sizeof(gamma_lut), &blob_id);
 	} else {
+		/*
+		 * Initialize gamma_lut to a linear table for the legacy API below.
+		 * The modern property API resets to a linear/pass-thru table if blob_id
+		 * is 0, hence no PropertyBlob is created here.
+		 */
 		for (i = 0; i < 256; i++) {
 			gamma_luti.red =
 			gamma_luti.green =
@@ -1135,6 +1176,7 @@
 	add_property_optional(dev, crtc_id, "DEGAMMA_LUT", 0);
 	add_property_optional(dev, crtc_id, "CTM", 0);
 	if (!add_property_optional(dev, crtc_id, "GAMMA_LUT", blob_id)) {
+		/* If we can't add the GAMMA_LUT property, try the legacy API. */
 		uint16_t r256, g256, b256;
 
 		for (i = 0; i < 256; i++) {
@@ -1144,7 +1186,7 @@
 		}
 
 		ret = drmModeCrtcSetGamma(dev->fd, crtc_id, 256, r, g, b);
-		if (ret)
+		if (ret && errno != ENOSYS)
 			fprintf(stderr, "failed to set gamma: %s\n", strerror(errno));
 	}
 }
@@ -1441,6 +1483,24 @@
 	return 0;
 }
 
+static bool pipe_has_writeback_connector(struct device *dev, struct pipe_arg *pipes,
+		unsigned int count)
+{
+	drmModeConnector *connector;
+	unsigned int i, j;
+
+	for (j = 0; j < count; j++) {
+		struct pipe_arg *pipe = &pipesj;
+
+		for (i = 0; i < pipe->num_cons; i++) {
+			connector = get_connector_by_id(dev, pipe->con_idsi);
+			if (connector && connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
+				return true;
+		}
+	}
+	return false;
+}
+
 static int pipe_attempt_connector(struct device *dev, drmModeConnector *con,
 		struct pipe_arg *pipe)
 {
@@ -1503,7 +1563,8 @@
 
 	for (i = 0; i < res->count_connectors; i++) {
 		con = res->connectorsi.connector;
-		if (!con || con->connection != DRM_MODE_CONNECTED)
+		if (!con || con->connection != DRM_MODE_CONNECTED ||
+		    con->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
 			continue;
 		connected++;
 	}
@@ -1550,32 +1611,35 @@
 	return NULL;
 }
 
-static void set_mode(struct device *dev, struct pipe_arg *pipes, unsigned int count)
+static unsigned int set_mode(struct device *dev, struct pipe_arg **pipe_args, unsigned int count)
 {
 	unsigned int i, j;
 	int ret, x = 0;
 	int preferred = count == 0;
+	struct pipe_arg *pipes;

_service:tar_scm:libdrm-2.4.115.tar.xz/tests/util/format.c -> _service:tar_scm:libdrm-2.4.119.tar.xz/tests/util/format.c Changed

@@ -40,7 +40,10 @@
 
 static const struct util_format_info format_info = {
 	/* Indexed */
-	{ DRM_FORMAT_C8, "C8" },
+	{ DRM_FORMAT_C1, "C1", .ncolors = 2 },
+	{ DRM_FORMAT_C2, "C2", .ncolors = 4 },
+	{ DRM_FORMAT_C4, "C4", .ncolors = 16 },
+	{ DRM_FORMAT_C8, "C8", .ncolors = 256 },
 	/* YUV packed */
 	{ DRM_FORMAT_UYVY, "UYVY", MAKE_YUV_INFO(YUV_YCbCr | YUV_CY, 2, 2, 2) },
 	{ DRM_FORMAT_VYUY, "VYUY", MAKE_YUV_INFO(YUV_YCrCb | YUV_CY, 2, 2, 2) },
@@ -51,6 +54,11 @@
 	{ DRM_FORMAT_NV21, "NV21", MAKE_YUV_INFO(YUV_YCrCb, 2, 2, 2) },
 	{ DRM_FORMAT_NV16, "NV16", MAKE_YUV_INFO(YUV_YCbCr, 2, 1, 2) },
 	{ DRM_FORMAT_NV61, "NV61", MAKE_YUV_INFO(YUV_YCrCb, 2, 1, 2) },
+	{ DRM_FORMAT_NV24, "NV24", MAKE_YUV_INFO(YUV_YCbCr, 1, 1, 2) },
+	{ DRM_FORMAT_NV42, "NV42", MAKE_YUV_INFO(YUV_YCrCb, 1, 1, 2) },
+	{ DRM_FORMAT_NV15, "NV15", MAKE_YUV_INFO(YUV_YCbCr, 2, 2, 2) },
+	{ DRM_FORMAT_NV20, "NV20", MAKE_YUV_INFO(YUV_YCbCr, 2, 1, 2) },
+	{ DRM_FORMAT_NV30, "NV30", MAKE_YUV_INFO(YUV_YCbCr, 1, 1, 2) },
 	/* YUV planar */
 	{ DRM_FORMAT_YUV420, "YU12", MAKE_YUV_INFO(YUV_YCbCr, 2, 2, 1) },
 	{ DRM_FORMAT_YVU420, "YV12", MAKE_YUV_INFO(YUV_YCrCb, 2, 2, 1) },
@@ -73,6 +81,9 @@
 	{ DRM_FORMAT_BGRX5551, "BX15", MAKE_RGB_INFO(5, 1, 5, 6, 5, 11, 0, 0) },
 	{ DRM_FORMAT_RGB565, "RG16", MAKE_RGB_INFO(5, 11, 6, 5, 5, 0, 0, 0) },
 	{ DRM_FORMAT_BGR565, "BG16", MAKE_RGB_INFO(5, 0, 6, 5, 5, 11, 0, 0) },
+	/* Big-endian RGB16 */
+	{ DRM_FORMAT_XRGB1555 | DRM_FORMAT_BIG_ENDIAN, "XR15_BE", MAKE_RGB_INFO(5, 10, 5, 5, 5, 0, 0, 0) },
+	{ DRM_FORMAT_RGB565 | DRM_FORMAT_BIG_ENDIAN, "RG16_BE", MAKE_RGB_INFO(5, 11, 6, 5, 5, 0, 0, 0) },
 	/* RGB24 */
 	{ DRM_FORMAT_BGR888, "BG24", MAKE_RGB_INFO(8, 0, 8, 8, 8, 16, 0, 0) },
 	{ DRM_FORMAT_RGB888, "RG24", MAKE_RGB_INFO(8, 16, 8, 8, 8, 0, 0, 0) },

_service:tar_scm:libdrm-2.4.115.tar.xz/tests/util/format.h -> _service:tar_scm:libdrm-2.4.119.tar.xz/tests/util/format.h Changed

_service:tar_scm:libdrm-2.4.115.tar.xz/tests/util/kms.c -> _service:tar_scm:libdrm-2.4.119.tar.xz/tests/util/kms.c Changed

_service:tar_scm:libdrm-2.4.115.tar.xz/tests/util/pattern.c -> _service:tar_scm:libdrm-2.4.119.tar.xz/tests/util/pattern.c Changed

@@ -23,6 +23,7 @@
  * IN THE SOFTWARE.
  */
 
+#include <stdbool.h>
 #include <stdint.h>
 #include <stdio.h>
 #include <stdlib.h>
@@ -61,6 +62,33 @@
 	  .u = MAKE_YUV_601_U(r, g, b), \
 	  .v = MAKE_YUV_601_V(r, g, b) }
 
+static inline uint16_t swap16(uint16_t x)
+{
+	return ((x & 0x00ffU) << 8) | ((x & 0xff00U) >> 8);
+}
+
+static inline uint32_t swap32(uint32_t x)
+{
+	return ((x & 0x000000ffU) << 24) |
+	       ((x & 0x0000ff00U) <<  8) |
+	       ((x & 0x00ff0000U) >>  8) |
+	       ((x & 0xff000000U) >> 24);
+}
+
+#ifdef HAVE_BIG_ENDIAN
+#define cpu_to_be16(x)			(x)
+#define cpu_to_le16(x)			swap16(x)
+#define cpu_to_le32(x)			swap32(x)
+#define fb_foreign_endian(format)	(!((format) & DRM_FORMAT_BIG_ENDIAN))
+#else
+#define cpu_to_be16(x)			swap16(x)
+#define cpu_to_le16(x)			(x)
+#define cpu_to_le32(x)			(x)
+#define fb_foreign_endian(format)	((format) & DRM_FORMAT_BIG_ENDIAN)
+#endif
+
+#define cpu_to_fb16(x)	(fb_be ? cpu_to_be16(x) : cpu_to_le16(x))
+
 /* This function takes 8-bit color values */
 static inline uint32_t shiftcolor8(const struct util_color_component *comp,
 				  uint32_t value)
@@ -162,7 +190,7 @@
 				  unsigned int height, unsigned int stride)
 {
 	const struct color_yuv colors_top = {
-		MAKE_YUV_601(191, 192, 192),	/* grey */
+		MAKE_YUV_601(192, 192, 192),	/* grey */
 		MAKE_YUV_601(192, 192, 0),	/* yellow */
 		MAKE_YUV_601(0, 192, 192),	/* cyan */
 		MAKE_YUV_601(0, 192, 0),	/* green */
@@ -260,12 +288,154 @@
 	}
 }
 
+static void write_pixels_10bpp(unsigned char *mem,
+			       unsigned short a,
+			       unsigned short b,
+			       unsigned short c,
+			       unsigned short d)
+{
+	  mem0 = (a & 0xff);
+	  mem1 = ((a >> 8) & 0x3) | ((b & 0x3f) << 2);
+	  mem2 = ((b >> 6) & 0xf) | ((c & 0xf) << 4);
+	  mem3 = ((c >> 4) & 0x3f) | ((d & 0x3) << 6);
+	  mem4 = ((d >> 2) & 0xff);
+}
+
+static void fill_smpte_yuv_planar_10bpp(const struct util_yuv_info *yuv,
+					unsigned char *y_mem,
+					unsigned char *uv_mem,
+					unsigned int width,
+					unsigned int height,
+					unsigned int stride)
+{
+	const struct color_yuv colors_top = {
+		MAKE_YUV_601(192, 192, 192),	/* grey */
+		MAKE_YUV_601(192, 192, 0),	/* yellow */
+		MAKE_YUV_601(0, 192, 192),	/* cyan */
+		MAKE_YUV_601(0, 192, 0),	/* green */
+		MAKE_YUV_601(192, 0, 192),	/* magenta */
+		MAKE_YUV_601(192, 0, 0),	/* red */
+		MAKE_YUV_601(0, 0, 192),	/* blue */
+	};
+	const struct color_yuv colors_middle = {
+		MAKE_YUV_601(0, 0, 192),	/* blue */
+		MAKE_YUV_601(19, 19, 19),	/* black */
+		MAKE_YUV_601(192, 0, 192),	/* magenta */
+		MAKE_YUV_601(19, 19, 19),	/* black */
+		MAKE_YUV_601(0, 192, 192),	/* cyan */
+		MAKE_YUV_601(19, 19, 19),	/* black */
+		MAKE_YUV_601(192, 192, 192),	/* grey */
+	};
+	const struct color_yuv colors_bottom = {
+		MAKE_YUV_601(0, 33, 76),	/* in-phase */
+		MAKE_YUV_601(255, 255, 255),	/* super white */
+		MAKE_YUV_601(50, 0, 106),	/* quadrature */
+		MAKE_YUV_601(19, 19, 19),	/* black */
+		MAKE_YUV_601(9, 9, 9),		/* 3.5% */
+		MAKE_YUV_601(19, 19, 19),	/* 7.5% */
+		MAKE_YUV_601(29, 29, 29),	/* 11.5% */
+		MAKE_YUV_601(19, 19, 19),	/* black */
+	};
+	unsigned int cs = yuv->chroma_stride;
+	unsigned int xsub = yuv->xsub;
+	unsigned int ysub = yuv->ysub;
+	unsigned int xstep = cs * xsub;
+	unsigned int x;
+	unsigned int y;
+
+	/* Luma */
+	for (y = 0; y < height * 6 / 9; ++y) {
+		for (x = 0; x < width; x += 4)
+			write_pixels_10bpp(&y_mem(x * 5) / 4,
+				colors_top(x+0) * 7 / width.y << 2,
+				colors_top(x+1) * 7 / width.y << 2,
+				colors_top(x+2) * 7 / width.y << 2,
+				colors_top(x+3) * 7 / width.y << 2);
+		y_mem += stride;
+	}
+
+	for (; y < height * 7 / 9; ++y) {
+		for (x = 0; x < width; x += 4)
+			write_pixels_10bpp(&y_mem(x * 5) / 4,
+				colors_middle(x+0) * 7 / width.y << 2,
+				colors_middle(x+1) * 7 / width.y << 2,
+				colors_middle(x+2) * 7 / width.y << 2,
+				colors_middle(x+3) * 7 / width.y << 2);
+		y_mem += stride;
+	}
+
+	for (; y < height; ++y) {
+		for (x = 0; x < width * 5 / 7; x += 4)
+			write_pixels_10bpp(&y_mem(x * 5) / 4,
+				colors_bottom(x+0) * 4 / (width * 5 / 7).y << 2,
+				colors_bottom(x+1) * 4 / (width * 5 / 7).y << 2,
+				colors_bottom(x+2) * 4 / (width * 5 / 7).y << 2,
+				colors_bottom(x+3) * 4 / (width * 5 / 7).y << 2);
+		for (; x < width * 6 / 7; x += 4)
+			write_pixels_10bpp(&y_mem(x * 5) / 4,
+				colors_bottom((x+0) - width * 5 / 7) * 3 / (width / 7) + 4.y << 2,
+				colors_bottom((x+1) - width * 5 / 7) * 3 / (width / 7) + 4.y << 2,
+				colors_bottom((x+2) - width * 5 / 7) * 3 / (width / 7) + 4.y << 2,
+				colors_bottom((x+3) - width * 5 / 7) * 3 / (width / 7) + 4.y << 2);
+		for (; x < width; x += 4)
+			write_pixels_10bpp(&y_mem(x * 5) / 4,
+				colors_bottom7.y << 2,
+				colors_bottom7.y << 2,
+				colors_bottom7.y << 2,
+				colors_bottom7.y << 2);
+		y_mem += stride;
+	}
+
+	/* Chroma */
+	for (y = 0; y < height * 6 / 9; y += ysub) {
+		for (x = 0; x < width; x += xstep)
+			write_pixels_10bpp(&uv_mem(x * 5) / xstep,
+				colors_top(x+0) * 7 / width.u << 2,
+				colors_top(x+0) * 7 / width.v << 2,
+				colors_top(x+xsub) * 7 / width.u << 2,
+				colors_top(x+xsub) * 7 / width.v << 2);
+		uv_mem += stride * cs / xsub;
+	}
+
+	for (; y < height * 7 / 9; y += ysub) {
+		for (x = 0; x < width; x += xstep)
+			write_pixels_10bpp(&uv_mem(x * 5) / xstep,
+				colors_middle(x+0) * 7 / width.u << 2,
+				colors_middle(x+0) * 7 / width.v << 2,
+				colors_middle(x+xsub) * 7 / width.u << 2,
+				colors_middle(x+xsub) * 7 / width.v << 2);
+		uv_mem += stride * cs / xsub;
+	}
+
+	for (; y < height; y += ysub) {
+		for (x = 0; x < width * 5 / 7; x += xstep)
+			write_pixels_10bpp(&uv_mem(x * 5) / xstep,
+				colors_bottom(x+0) * 4 / (width * 5 / 7).u << 2,
+				colors_bottom(x+0) * 4 / (width * 5 / 7).v << 2,
+				colors_bottom(x+xsub) * 4 / (width * 5 / 7).u << 2,
+				colors_bottom(x+xsub) * 4 / (width * 5 / 7).v << 2);
+		for (; x < width * 6 / 7; x += xstep)
+			write_pixels_10bpp(&uv_mem(x * 5) / xstep,
+				colors_bottom((x+0) - width * 5 / 7) * 3 / (width / 7) + 4.u << 2,
+				colors_bottom((x+0) - width * 5 / 7) * 3 / (width / 7) + 4.v << 2,
+				colors_bottom((x+xsub) - width * 5 / 7) * 3 / (width / 7) + 4.u << 2,
+				colors_bottom((x+xsub) - width * 5 / 7) * 3 / (width / 7) + 4.v << 2);
+		for (; x < width; x += xstep)
+			write_pixels_10bpp(&uv_mem(x * 5) / xstep,
+				colors_bottom7.u << 2,
+				colors_bottom7.v << 2,
+				colors_bottom7.u << 2,
+				colors_bottom7.v << 2);
+		uv_mem += stride * cs / xsub;
+	}
+}
+
 static void fill_smpte_yuv_packed(const struct util_yuv_info *yuv, void *mem,
 				  unsigned int width, unsigned int height,
 				  unsigned int stride)

_service:tar_scm:libdrm-2.4.115.tar.xz/tests/util/pattern.h -> _service:tar_scm:libdrm-2.4.119.tar.xz/tests/util/pattern.h Changed

_service:tar_scm:libdrm-2.4.115.tar.xz/xf86drm.c -> _service:tar_scm:libdrm-2.4.119.tar.xz/xf86drm.c Changed

@@ -829,8 +829,6 @@
     switch (type) {
     case DRM_NODE_PRIMARY:
         return DRM_DEV_NAME;
-    case DRM_NODE_CONTROL:
-        return DRM_CONTROL_DEV_NAME;
     case DRM_NODE_RENDER:
         return DRM_RENDER_DEV_NAME;
     }
@@ -1026,8 +1024,6 @@
     switch (type) {
     case DRM_NODE_PRIMARY:
         return 0;
-    case DRM_NODE_CONTROL:
-        return 64;
     case DRM_NODE_RENDER:
         return 128;
     default:
@@ -1048,8 +1044,6 @@
         // If not in /dev/drm/ we have the type in the name
         if (sscanf(name, "dri/card%d\n", &id) >= 1)
            return DRM_NODE_PRIMARY;
-        else if (sscanf(name, "dri/control%d\n", &id) >= 1)
-           return DRM_NODE_CONTROL;
         else if (sscanf(name, "dri/renderD%d\n", &id) >= 1)
            return DRM_NODE_RENDER;
         return -1;
@@ -1057,19 +1051,20 @@
 
     minor = id;
 #endif
-    int type = minor >> 6;
-
-    if (minor < 0)
-        return -1;
+    char pathDRM_NODE_NAME_MAX;
+    const char *dev_name;
+    int i;
 
-    switch (type) {
-    case DRM_NODE_PRIMARY:
-    case DRM_NODE_CONTROL:
-    case DRM_NODE_RENDER:
-        return type;
-    default:
-        return -1;
+    for (i = DRM_NODE_PRIMARY; i < DRM_NODE_MAX; i++) {
+        dev_name = drmGetDeviceName(i);
+        if (!dev_name)
+           continue;
+        snprintf(path, sizeof(path), dev_name, DRM_DIR_NAME, minor);
+        if (!access(path, F_OK))
+           return i;
     }
+
+    return -1;
 }
 
 static const char *drmGetMinorName(int type)
@@ -1077,8 +1072,6 @@
     switch (type) {
     case DRM_NODE_PRIMARY:
         return DRM_PRIMARY_MINOR_NAME;
-    case DRM_NODE_CONTROL:
-        return DRM_CONTROL_MINOR_NAME;
     case DRM_NODE_RENDER:
         return DRM_RENDER_MINOR_NAME;
     default:
@@ -1265,7 +1258,7 @@
  *
  * \param name driver name. Not referenced if bus ID is supplied.
  * \param busid bus ID. Zero if not known.
- * \param type the device node type to open, PRIMARY, CONTROL or RENDER
+ * \param type the device node type to open, PRIMARY or RENDER
  *
  * \return a file descriptor on success, or a negative value on error.
  *
@@ -1298,7 +1291,7 @@
 
 drm_public int drmOpenControl(int minor)
 {
-    return drmOpenMinor(minor, 0, DRM_NODE_CONTROL);
+    return -EINVAL;
 }
 
 drm_public int drmOpenRender(int minor)
@@ -3704,12 +3697,9 @@
     switch (type) {
     case DRM_NODE_PRIMARY:
          break;
-    case DRM_NODE_CONTROL:
-         id -= 64;
-         break;
     case DRM_NODE_RENDER:
          id -= 128;
-          break;
+         break;
     }
     if (id < 0)
         return -EINVAL;
@@ -3821,10 +3811,6 @@
 
 static int drmGetNodeType(const char *name)
 {
-    if (strncmp(name, DRM_CONTROL_MINOR_NAME,
-        sizeof(DRM_CONTROL_MINOR_NAME ) - 1) == 0)
-        return DRM_NODE_CONTROL;
-
     if (strncmp(name, DRM_RENDER_MINOR_NAME,
         sizeof(DRM_RENDER_MINOR_NAME) - 1) == 0)
         return DRM_NODE_RENDER;
@@ -4701,6 +4687,23 @@
 #endif
 }
 
+drm_public int drmGetNodeTypeFromDevId(dev_t devid)
+{
+    int maj, min, node_type;
+
+    maj = major(devid);
+    min = minor(devid);
+
+    if (!drmNodeIsDRM(maj, min))
+        return -EINVAL;
+
+    node_type = drmGetMinorType(maj, min);
+    if (node_type == -1)
+        return -ENODEV;
+
+    return node_type;
+}
+
 /**
  * Get information about the opened drm device
  *
@@ -5118,6 +5121,20 @@
     return ret;
 }
 
+drm_public int drmSyncobjEventfd(int fd, uint32_t handle, uint64_t point, int ev_fd,
+                                 uint32_t flags)
+{
+    struct drm_syncobj_eventfd args;
+
+    memclear(args);
+    args.handle = handle;
+    args.point = point;
+    args.fd = ev_fd;
+    args.flags = flags;
+
+    return drmIoctl(fd, DRM_IOCTL_SYNCOBJ_EVENTFD, &args);
+}
+
 static char *
 drmGetFormatModifierFromSimpleTokens(uint64_t modifier)
 {

_service:tar_scm:libdrm-2.4.115.tar.xz/xf86drm.h -> _service:tar_scm:libdrm-2.4.119.tar.xz/xf86drm.h Changed

@@ -44,7 +44,7 @@
 #endif
 
 #ifndef DRM_MAX_MINOR
-#define DRM_MAX_MINOR   16
+#define DRM_MAX_MINOR   64 /* deprecated */
 #endif
 
 #if defined(__linux__)
@@ -79,18 +79,18 @@
 #ifdef __OpenBSD__
 #define DRM_DIR_NAME  "/dev"
 #define DRM_PRIMARY_MINOR_NAME  "drm"
-#define DRM_CONTROL_MINOR_NAME  "drmC"
+#define DRM_CONTROL_MINOR_NAME  "drmC" /* deprecated */
 #define DRM_RENDER_MINOR_NAME   "drmR"
 #else
 #define DRM_DIR_NAME  "/dev/dri"
 #define DRM_PRIMARY_MINOR_NAME  "card"
-#define DRM_CONTROL_MINOR_NAME  "controlD"
+#define DRM_CONTROL_MINOR_NAME  "controlD" /* deprecated */
 #define DRM_RENDER_MINOR_NAME   "renderD"
 #define DRM_PROC_NAME "/proc/dri/" /* For backward Linux compatibility */
 #endif
 
 #define DRM_DEV_NAME          "%s/" DRM_PRIMARY_MINOR_NAME "%d"
-#define DRM_CONTROL_DEV_NAME  "%s/" DRM_CONTROL_MINOR_NAME "%d"
+#define DRM_CONTROL_DEV_NAME  "%s/" DRM_CONTROL_MINOR_NAME "%d" /* deprecated */
 #define DRM_RENDER_DEV_NAME   "%s/" DRM_RENDER_MINOR_NAME  "%d"
 
 #define DRM_NODE_NAME_MAX \
@@ -98,7 +98,7 @@
      + MAX3(sizeof(DRM_PRIMARY_MINOR_NAME), \
             sizeof(DRM_CONTROL_MINOR_NAME), \
             sizeof(DRM_RENDER_MINOR_NAME)) \
-     + sizeof("144") /* highest possible node number */ \
+     + sizeof("1048575") /* highest possible node number 2^MINORBITS - 1 */ \
      + 1) /* NULL-terminator */
 
 #define DRM_ERR_NO_DEVICE  (-1001)
@@ -596,14 +596,14 @@
 extern int           drmOpen(const char *name, const char *busid);
 
 #define DRM_NODE_PRIMARY 0
-#define DRM_NODE_CONTROL 1
+#define DRM_NODE_CONTROL 1 /* deprecated: never returned */
 #define DRM_NODE_RENDER  2
 #define DRM_NODE_MAX     3
 
 extern int           drmOpenWithType(const char *name, const char *busid,
                                      int type);
 
-extern int           drmOpenControl(int minor);
+extern int           drmOpenControl(int minor); /* deprecated: always fails */
 extern int           drmOpenRender(int minor);
 extern int           drmClose(int fd);
 extern drmVersionPtr drmGetVersion(int fd);
@@ -808,7 +808,7 @@
 extern char *drmGetDeviceNameFromFd(int fd);
 
 /* Improved version of drmGetDeviceNameFromFd which attributes for any type of
- * device/node - card, control or renderD.
+ * device/node - card or renderD.
  */
 extern char *drmGetDeviceNameFromFd2(int fd);
 extern int drmGetNodeTypeFromFd(int fd);
@@ -919,6 +919,13 @@
 
 extern int drmGetDeviceFromDevId(dev_t dev_id, uint32_t flags, drmDevicePtr *device);
 
+/**
+ * Get the node type (DRM_NODE_PRIMARY or DRM_NODE_RENDER) from a device ID.
+ *
+ * Returns negative errno on error.
+ */
+extern int drmGetNodeTypeFromDevId(dev_t devid);
+
 extern int drmDevicesEqual(drmDevicePtr a, drmDevicePtr b);
 
 extern int drmSyncobjCreate(int fd, uint32_t flags, uint32_t *handle);
@@ -947,6 +954,8 @@
 			      uint32_t dst_handle, uint64_t dst_point,
 			      uint32_t src_handle, uint64_t src_point,
 			      uint32_t flags);
+extern int drmSyncobjEventfd(int fd, uint32_t handle, uint64_t point, int ev_fd,
+                             uint32_t flags);
 
 extern char *
 drmGetFormatModifierVendor(uint64_t modifier);

_service:tar_scm:libdrm-2.4.115.tar.xz/xf86drmMode.c -> _service:tar_scm:libdrm-2.4.119.tar.xz/xf86drmMode.c Changed

_service:tar_scm:libdrm-2.4.115.tar.xz/xf86drmMode.h -> _service:tar_scm:libdrm-2.4.119.tar.xz/xf86drmMode.h Changed

Changes of Revision 3