开源软件构建与测试

Changes of Revision 3

_service:tar_scm:pyparsing.spec Changed

@@ -1,10 +1,10 @@
 Name:            pyparsing
-Version:         3.0.9
+Version:         3.1.1
 Release:         1
 Summary:         A Python Parsing Module
 License:         MIT
 URL:             https://github.com/pyparsing/pyparsing/
-Source0:         https://github.com/pyparsing/pyparsing/releases/download/pyparsing_%{version}/pyparsing-%{version}.tar.gz
+Source0:         https://github.com/pyparsing/pyparsing/releases/download/%{version}/pyparsing-%{version}.tar.gz
 
 BuildArch:       noarch
 BuildRequires:   dos2unix python3-devel python3-setuptools python3-tox python3-coverage python3-flit-core
@@ -68,6 +68,27 @@
 %doc CHANGES README.rst docs examples
 
 %changelog
+* Mon Jan 29 2024 yixiangzhike <yixiangzhike007@163.com> - 3.1.1-1
+- update version to 3.1.1
+  - Fixed bug in NotAny where expr parse action was not being run
+  - Fix regex matching for Python quoted strings
+  - Make create_diagram() code compatible with latest version of railroad-diagrams
+  - Support Python 3.12
+  - Small perf optimization for `expr | ""` mapping to `Optional(expr)`
+  - Redo QuotedString '\' escape handling as a state machine
+  - Add ParseResults.deepcopy()
+  - Remove ^ and $ tags from pp.common.url regex
+  - Added DelimitedList class, for better handling of naming and diagramming
+  - Deprecate ParserElement.validate()
+  - Added new class method ParserElement.using_each
+  - Fix bug in delimited_list
+  - Added python_quoted_string; fixed exception messages for ParseElementEnhance subclasses
+  - Enable packrat in verilogParse.py by default
+  - Add embed argument to create_diagram
+  - Add support for slice in expr notation
+  - Fixed bug in srange
+  - Added Lox language parser
+
 * Fri Jul 28 2023 zhuofeng <zhuofeng2@huawei.com> - 3.0.9-1
 - update version to 3.0.9

_service Changed

_service:tar_scm:pyparsing-3.0.9.tar.gz/.github/FUNDING.yml Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/.github/SECURITY.md Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/.github/workflows/ci.yml Deleted

@@ -1,58 +0,0 @@
-name: Continuous Integration
-on:
-  push:
-    branches:
-      - master
-
-  pull_request:
-    paths:
-      - .github/workflows/cis.yml
-      - pyparsing/*
-      - pyproject.toml
-      - tox.ini
-
-jobs:
-  tests:
-    name: Unit tests
-    runs-on: ${{ matrix.os || 'ubuntu-latest' }}
-    strategy:
-      matrix:
-        include:
-          - python-version: "3.6"
-            toxenv: py36
-          - python-version: "3.7"
-            toxenv: py37
-          - python-version: "3.8"
-            toxenv: py38
-          - python-version: "3.9"
-            toxenv: py39
-          - python-version: "3.10"
-            toxenv: py310
-          - python-version: "3.10"
-            toxenv: py310
-            os: macos-latest
-          - python-version: "pypy-3.7"
-            toxenv: pypy3
-    env:
-      TOXENV: ${{ matrix.toxenv }}
-    steps:
-      - uses: actions/checkout@v2
-
-      - name: Set up Python ${{ matrix.python-version }}
-        uses: actions/setup-python@v2
-        with:
-          python-version: ${{ matrix.python-version }}
-
-      - name: Install dependencies
-        run: |
-          python -m pip install --upgrade pip
-          python -m pip install tox codecov railroad-diagrams Jinja2
-
-      - name: Test
-        run: tox -e ALL
-
-      - name: Upload coverage to Codecov
-        if: ${{ matrix.os == 'ubuntu-latest' && matrix.python-version == '3.10' }}
-        env:
-          CODECOV_TOKEN: ${{ secrets.CODECOV_TOKEN }}
-        run: codecov

_service:tar_scm:pyparsing-3.0.9.tar.gz/docs/_static/pyparsingClassDiagram_3.0.0.jpg Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/docs/pyparsing_class_diagram.svg Deleted

@@ -1,836 +0,0 @@
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@@ -1,121 +0,0 @@
-#
-# chemicalFormulas.py
-#
-# Copyright (c) 2003,2019 Paul McGuire
-#
-
-import pyparsing as pp
-
-atomicWeight = {
-    "O": 15.9994,
-    "H": 1.00794,
-    "Na": 22.9897,
-    "Cl": 35.4527,
-    "C": 12.0107,
-}
-
-digits = "0123456789"
-
-# Version 1
-element = pp.Word(pp.alphas.upper(), pp.alphas.lower(), max=2).set_name("element")
-# for stricter matching, use this Regex instead
-# element = Regex("Acglmrstu|Baehikr?|Cadeflmorsu?|Dbsy|"
-#                 "Ersu|Femr?|Gade|Hefgos?|Inr?|Kr?|Lairu|"
-#                 "Mdgnot|Nabdeiop?|Os?|Pabdmortu?|Rabefghnu|"
-#                 "Sbcegimnr?|Tabcehilm|U(ubhopqst)?|V|W|Xe|Yb?|Znr")
-elementRef = pp.Group(element + pp.Optional(pp.Word(digits), default="1"))
-formula = elementRef...
-
-
-def sum_atomic_weights(element_list):
-    return sum(atomicWeightelem * int(qty) for elem, qty in element_list)
-
-
-formula.runTests(
-    """\
-    H2O
-    C6H5OH
-    NaCl
-    """,
-    fullDump=False,
-    postParse=lambda _, tokens: "Molecular weight: {}".format(
-        sum_atomic_weights(tokens)
-    ),
-)
-print()
-
-# Version 2 - access parsed items by results name
-elementRef = pp.Group(
-    element("symbol") + pp.Optional(pp.Word(digits), default="1")("qty")
-)
-formula = elementRef...
-
-
-def sum_atomic_weights_by_results_name(element_list):
-    return sum(atomicWeightelem.symbol * int(elem.qty) for elem in element_list)
-
-
-formula.runTests(
-    """\
-    H2O
-    C6H5OH
-    NaCl
-    """,
-    fullDump=False,
-    postParse=lambda _, tokens: "Molecular weight: {}".format(
-        sum_atomic_weights_by_results_name(tokens)
-    ),
-)
-print()
-
-# Version 3 - convert integers during parsing process
-integer = pp.Word(digits).setParseAction(lambda t: int(t0)).setName("integer")
-elementRef = pp.Group(element("symbol") + pp.Optional(integer, default=1)("qty"))
-formula = elementRef....setName("chemical_formula")
-
-
-def sum_atomic_weights_by_results_name_with_converted_ints(element_list):
-    return sum(atomicWeightelem.symbol * int(elem.qty) for elem in element_list)
-
-
-formula.runTests(
-    """\
-    H2O
-    C6H5OH
-    NaCl
-    """,
-    fullDump=False,
-    postParse=lambda _, tokens: "Molecular weight: {}".format(
-        sum_atomic_weights_by_results_name_with_converted_ints(tokens)
-    ),
-)
-print()
-
-# Version 4 - parse and convert integers as subscript digits
-subscript_digits = "₀₁₂₃₄₅₆₇₈₉"
-subscript_int_map = {e1: e0 for e in enumerate(subscript_digits)}
-
-
-def cvt_subscript_int(s):
-    ret = 0
-    for c in s0:
-        ret = ret * 10 + subscript_int_mapc
-    return ret
-
-
-subscript_int = pp.Word(subscript_digits).addParseAction(cvt_subscript_int).set_name("subscript")
-
-elementRef = pp.Group(element("symbol") + pp.Optional(subscript_int, default=1)("qty"))
-formula = elementRef1, ....setName("chemical_formula")
-formula.runTests(
-    """\
-    H₂O
-    C₆H₅OH
-    NaCl
-    """,
-    fullDump=False,
-    postParse=lambda _, tokens: "Molecular weight: {}".format(
-        sum_atomic_weights_by_results_name_with_converted_ints(tokens)
-    ),
-)
-print()

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@@ -1,84 +0,0 @@
-# parseActions.py
-#
-#   A sample program a parser to match a date string of the form "YYYY/MM/DD",
-# and return it as a datetime, or raise an exception if not a valid date.
-#
-# Copyright 2012, Paul T. McGuire
-#
-from datetime import datetime
-import pyparsing as pp
-from pyparsing import pyparsing_common as ppc
-
-# define an integer string, and a parse action to convert it
-# to an integer at parse time
-integer = pp.Word(pp.nums).setName("integer")
-
-
-def convertToInt(tokens):
-    # no need to test for validity - we can't get here
-    # unless tokens0 contains all numeric digits
-    return int(tokens0)
-
-
-integer.setParseAction(convertToInt)
-# or can be written as one line as
-# integer = Word(nums).setParseAction(lambda t: int(t0))
-
-# define a pattern for a year/month/day date
-date_expr = integer("year") + "/" + integer("month") + "/" + integer("day")
-date_expr.ignore(pp.pythonStyleComment)
-
-
-def convertToDatetime(s, loc, tokens):
-    try:
-        # note that the year, month, and day fields were already
-        # converted to ints from strings by the parse action defined
-        # on the integer expression above
-        return datetime(tokens.year, tokens.month, tokens.day).date()
-    except Exception as ve:
-        errmsg = "'%s/%s/%s' is not a valid date, %s" % (
-            tokens.year,
-            tokens.month,
-            tokens.day,
-            ve,
-        )
-        raise pp.ParseException(s, loc, errmsg)
-
-
-date_expr.setParseAction(convertToDatetime)
-
-
-date_expr.runTests(
-    """\
-    2000/1/1
-
-    # invalid month
-    2000/13/1
-
-    # 1900 was not a leap year
-    1900/2/29
-
-    # but 2000 was
-    2000/2/29
-    """
-)
-
-
-# if dates conform to ISO8601, use definitions in pyparsing_common
-date_expr = ppc.iso8601_date.setParseAction(ppc.convertToDate())
-date_expr.ignore(pp.pythonStyleComment)
-
-date_expr.runTests(
-    """\
-    2000-01-01
-
-    # invalid month
-    2000-13-01
-
-    # 1900 was not a leap year
-    1900-02-29
-
-    # but 2000 was
-    2000-02-29
-    """
-)

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@@ -1,106 +0,0 @@
-# excelExpr.py
-#
-# Copyright 2010, Paul McGuire
-#
-# A partial implementation of a parser of Excel formula expressions.
-#
-from pyparsing import (
-    CaselessKeyword,
-    Suppress,
-    Word,
-    alphas,
-    alphanums,
-    nums,
-    Optional,
-    Group,
-    oneOf,
-    Forward,
-    infixNotation,
-    opAssoc,
-    dblQuotedString,
-    delimitedList,
-    Combine,
-    Literal,
-    QuotedString,
-    ParserElement,
-    pyparsing_common as ppc,
-)
-
-ParserElement.enablePackrat()
-
-EQ, LPAR, RPAR, COLON, COMMA = map(Suppress, "=():,")
-EXCL, DOLLAR = map(Literal, "!$")
-sheetRef = Word(alphas, alphanums) | QuotedString("'", escQuote="''")
-colRef = Optional(DOLLAR) + Word(alphas, max=2)
-rowRef = Optional(DOLLAR) + Word(nums)
-cellRef = Combine(
-    Group(Optional(sheetRef + EXCL)("sheet") + colRef("col") + rowRef("row"))
-)
-
-cellRange = (
-    Group(cellRef("start") + COLON + cellRef("end"))("range")
-    | cellRef
-    | Word(alphas, alphanums)
-)
-
-expr = Forward()
-
-COMPARISON_OP = oneOf("< = > >= <= != <>")
-condExpr = expr + COMPARISON_OP + expr
-
-ifFunc = (
-    CaselessKeyword("if")
-    - LPAR
-    + Group(condExpr)("condition")
-    + COMMA
-    + Group(expr)("if_true")
-    + COMMA
-    + Group(expr)("if_false")
-    + RPAR
-)
-
-
-def stat_function(name):
-    return Group(CaselessKeyword(name) + Group(LPAR + delimitedList(expr) + RPAR))
-
-
-sumFunc = stat_function("sum")
-minFunc = stat_function("min")
-maxFunc = stat_function("max")
-aveFunc = stat_function("ave")
-funcCall = ifFunc | sumFunc | minFunc | maxFunc | aveFunc
-
-multOp = oneOf("* /")
-addOp = oneOf("+ -")
-numericLiteral = ppc.number
-operand = numericLiteral | funcCall | cellRange | cellRef
-arithExpr = infixNotation(
-    operand,
-    
-        (multOp, 2, opAssoc.LEFT),
-        (addOp, 2, opAssoc.LEFT),
-    ,
-)
-
-textOperand = dblQuotedString | cellRef
-textExpr = infixNotation(
-    textOperand,
-    
-        ("&", 2, opAssoc.LEFT),
-    ,
-)
-
-expr <<= arithExpr | textExpr
-
-
-(EQ + expr).runTests(
-    """\
-    =3*A7+5
-    =3*Sheet1!$A$7+5
-    =3*'Sheet 1'!$A$7+5
-    =3*'O''Reilly''s sheet'!$A$7+5
-    =if(Sum(A1:A25)>42,Min(B1:B25),if(Sum(C1:C25)>3.14, (Min(C1:C25)+3)*18,Max(B1:B25)))
-    =sum(a1:a25,10,min(b1,c2,d3))
-    =if("T"&a2="TTime", "Ready", "Not ready")
-"""
-)

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@@ -1,67 +0,0 @@
-# escrito por Marco Alfonso, 2004 Noviembre
-
-# importamos los símbolos requeridos desde el módulo
-from pyparsing import (
-    Word,
-    alphas,
-    oneOf,
-    nums,
-    Group,
-    OneOrMore,
-    pyparsing_unicode as ppu,
-)
-
-# usamos las letras en latin1, que incluye las como 'ñ', 'á', 'é', etc.
-alphas = ppu.Latin1.alphas
-
-# Aqui decimos que la gramatica "saludo" DEBE contener
-# una palabra compuesta de caracteres alfanumericos
-# (Word(alphas)) mas una ',' mas otra palabra alfanumerica,
-# mas '!' y esos seian nuestros tokens
-saludo = Word(alphas) + "," + Word(alphas) + oneOf("! . ?")
-tokens = saludo.parseString("Hola, Mundo !")
-
-# Ahora parseamos una cadena, "Hola, Mundo!",
-# el metodo parseString, nos devuelve una lista con los tokens
-# encontrados, en caso de no haber errores...
-for i, token in enumerate(tokens):
-    print("Token %d -> %s" % (i, token))
-
-# imprimimos cada uno de los tokens Y listooo!!, he aquí a salida
-# Token 0 -> Hola
-# Token 1 -> ,
-# Token 2-> Mundo
-# Token 3 -> !
-
-# ahora cambia el parseador, aceptando saludos con mas que una sola palabra antes que ','
-saludo = Group(OneOrMore(Word(alphas))) + "," + Word(alphas) + oneOf("! . ?")
-tokens = saludo.parseString("Hasta mañana, Mundo !")
-
-for i, token in enumerate(tokens):
-    print("Token %d -> %s" % (i, token))
-
-# Ahora parseamos algunas cadenas, usando el metodo runTests
-saludo.runTests(
-    """\
-    Hola, Mundo!
-    Hasta mañana, Mundo !
-""",
-    fullDump=False,
-)
-
-# Por supuesto, se pueden "reutilizar" gramáticas, por ejemplo:
-numimag = Word(nums) + "i"
-numreal = Word(nums)
-numcomplex = numreal + "+" + numimag
-print(numcomplex.parseString("3+5i"))
-
-# Funcion para cambiar a complejo numero durante parsear:
-def hace_python_complejo(t):
-    valid_python = "".join(t).replace("i", "j")
-    return complex(valid_python)
-
-
-numcomplex.setParseAction(hace_python_complejo)
-print(numcomplex.parseString("3+5i"))
-
-# Excelente!!, bueno, los dejo, me voy a seguir tirando código...

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@@ -1,42 +0,0 @@
-#
-# htmlStripper.py
-#
-#  Sample code for stripping HTML markup tags and scripts from
-#  HTML source files.
-#
-# Copyright (c) 2006, 2016, Paul McGuire
-#
-from urllib.request import urlopen
-from pyparsing import (
-    makeHTMLTags,
-    commonHTMLEntity,
-    replaceHTMLEntity,
-    htmlComment,
-    anyOpenTag,
-    anyCloseTag,
-    LineEnd,
-    replaceWith,
-)
-
-scriptOpen, scriptClose = makeHTMLTags("script")
-scriptBody = scriptOpen + scriptOpen.tag_body + scriptClose
-commonHTMLEntity.setParseAction(replaceHTMLEntity)
-
-# get some HTML
-targetURL = "https://wiki.python.org/moin/PythonDecoratorLibrary"
-with urlopen(targetURL) as targetPage:
-    targetHTML = targetPage.read().decode("UTF-8")
-
-# first pass, strip out tags and translate entities
-firstPass = (
-    (htmlComment | scriptBody | commonHTMLEntity | anyOpenTag | anyCloseTag)
-    .suppress()
-    .transformString(targetHTML)
-)
-
-# first pass leaves many blank lines, collapse these down
-repeatedNewlines = LineEnd() * (2,)
-repeatedNewlines.setParseAction(replaceWith("\n\n"))
-secondPass = repeatedNewlines.transformString(firstPass)
-
-print(secondPass)

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/htmlTableParser.py Deleted

@@ -1,77 +0,0 @@
-#
-# htmlTableParser.py
-#
-# Example of parsing a simple HTML table into a list of rows, and optionally into a little database
-#
-# Copyright 2019, Paul McGuire
-#
-
-import pyparsing as pp
-import urllib.request
-
-
-# define basic HTML tags, and compose into a Table
-table, table_end = pp.makeHTMLTags("table")
-thead, thead_end = pp.makeHTMLTags("thead")
-tbody, tbody_end = pp.makeHTMLTags("tbody")
-tr, tr_end = pp.makeHTMLTags("tr")
-th, th_end = pp.makeHTMLTags("th")
-td, td_end = pp.makeHTMLTags("td")
-a, a_end = pp.makeHTMLTags("a")
-
-# method to strip HTML tags from a string - will be used to clean up content of table cells
-strip_html = (pp.anyOpenTag | pp.anyCloseTag).suppress().transformString
-
-# expression for parsing <a href="url">text</a> links, returning a (text, url) tuple
-link = pp.Group(a + a.tag_body("text") + a_end.suppress())
-
-
-def extract_text_and_url(t):
-    return (t0.text, t0.href)
-
-
-link.addParseAction(extract_text_and_url)
-
-# method to create table rows of header and data tags
-def table_row(start_tag, end_tag):
-    body = start_tag.tag_body
-    body.addParseAction(pp.tokenMap(str.strip), pp.tokenMap(strip_html))
-    row = pp.Group(
-        tr.suppress()
-        + pp.ZeroOrMore(start_tag.suppress() + body + end_tag.suppress())
-        + tr_end.suppress()
-    )
-    return row
-
-
-th_row = table_row(th, th_end)
-td_row = table_row(td, td_end)
-
-# define expression for overall table - may vary slightly for different pages
-html_table = (
-    table
-    + tbody
-    + pp.Optional(th_row("headers"))
-    + pp.ZeroOrMore(td_row)("rows")
-    + tbody_end
-    + table_end
-)
-
-
-# read in a web page containing an interesting HTML table
-with urllib.request.urlopen(
-    "https://en.wikipedia.org/wiki/List_of_tz_database_time_zones"
-) as page:
-    page_html = page.read().decode()
-
-tz_table = html_table.searchString(page_html)0
-
-# convert rows to dicts
-rows = dict(zip(tz_table.headers, row)) for row in tz_table.rows
-
-# make a dict keyed by TZ database name
-tz_db = {row"TZ database name": row for row in rows}
-
-from pprint import pprint
-
-pprint(tz_db"America/Chicago")

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/invRegex.py Deleted

@@ -1,310 +0,0 @@
-#
-# invRegex.py
-#
-# Copyright 2008, Paul McGuire
-#
-# pyparsing script to expand a regular expression into all possible matching strings
-# Supports:
-# - {n} and {m,n} repetition, but not unbounded + or * repetition
-# - ? optional elements
-# -  character ranges
-# - () grouping
-# - | alternation
-#
-__all__ = "count", "invert"
-
-from pyparsing import (
-    Literal,
-    oneOf,
-    printables,
-    ParserElement,
-    Combine,
-    SkipTo,
-    infixNotation,
-    ParseFatalException,
-    Word,
-    nums,
-    opAssoc,
-    Suppress,
-    ParseResults,
-    srange,
-)
-
-ParserElement.enablePackrat()
-
-
-class CharacterRangeEmitter:
-    def __init__(self, chars):
-        # remove duplicate chars in character range, but preserve original order
-        seen = set()
-        self.charset = "".join(seen.add(c) or c for c in chars if c not in seen)
-
-    def __str__(self):
-        return "" + self.charset + ""
-
-    def __repr__(self):
-        return "" + self.charset + ""
-
-    def makeGenerator(self):
-        def genChars():
-            yield from self.charset
-
-        return genChars
-
-
-class OptionalEmitter:
-    def __init__(self, expr):
-        self.expr = expr
-
-    def makeGenerator(self):
-        def optionalGen():
-            yield ""
-            yield from self.expr.makeGenerator()()
-
-        return optionalGen
-
-
-class DotEmitter:
-    def makeGenerator(self):
-        def dotGen():
-            yield from printables
-
-        return dotGen
-
-
-class GroupEmitter:
-    def __init__(self, exprs):
-        self.exprs = ParseResults(exprs)
-
-    def makeGenerator(self):
-        def groupGen():
-            def recurseList(elist):
-                if len(elist) == 1:
-                    yield from elist0.makeGenerator()()
-                else:
-                    for s in elist0.makeGenerator()():
-                        for s2 in recurseList(elist1:):
-                            yield s + s2
-
-            if self.exprs:
-                yield from recurseList(self.exprs)
-
-        return groupGen
-
-
-class AlternativeEmitter:
-    def __init__(self, exprs):
-        self.exprs = exprs
-
-    def makeGenerator(self):
-        def altGen():
-            for e in self.exprs:
-                yield from e.makeGenerator()()
-
-        return altGen
-
-
-class LiteralEmitter:
-    def __init__(self, lit):
-        self.lit = lit
-
-    def __str__(self):
-        return "Lit:" + self.lit
-
-    def __repr__(self):
-        return "Lit:" + self.lit
-
-    def makeGenerator(self):
-        def litGen():
-            yield self.lit
-
-        return litGen
-
-
-def handleRange(toks):
-    return CharacterRangeEmitter(srange(toks0))
-
-
-def handleRepetition(toks):
-    toks = toks0
-    if toks1 in "*+":
-        raise ParseFatalException("", 0, "unbounded repetition operators not supported")
-    if toks1 == "?":
-        return OptionalEmitter(toks0)
-    if "count" in toks:
-        return GroupEmitter(toks0 * int(toks.count))
-    if "minCount" in toks:
-        mincount = int(toks.minCount)
-        maxcount = int(toks.maxCount)
-        optcount = maxcount - mincount
-        if optcount:
-            opt = OptionalEmitter(toks0)
-            for i in range(1, optcount):
-                opt = OptionalEmitter(GroupEmitter(toks0, opt))
-            return GroupEmitter(toks0 * mincount + opt)
-        else:
-            return toks0 * mincount
-
-
-def handleLiteral(toks):
-    lit = ""
-    for t in toks:
-        if t0 == "\\":
-            if t1 == "t":
-                lit += "\t"
-            else:
-                lit += t1
-        else:
-            lit += t
-    return LiteralEmitter(lit)
-
-
-def handleMacro(toks):
-    macroChar = toks01
-    if macroChar == "d":
-        return CharacterRangeEmitter("0123456789")
-    elif macroChar == "w":
-        return CharacterRangeEmitter(srange("A-Za-z0-9_"))
-    elif macroChar == "s":
-        return LiteralEmitter(" ")
-    else:
-        raise ParseFatalException(
-            "", 0, "unsupported macro character (" + macroChar + ")"
-        )
-
-
-def handleSequence(toks):
-    return GroupEmitter(toks0)
-
-
-def handleDot():
-    return CharacterRangeEmitter(printables)
-
-
-def handleAlternative(toks):
-    return AlternativeEmitter(toks0)
-
-
-_parser = None
-
-
-def parser():
-    global _parser
-    if _parser is None:
-        ParserElement.setDefaultWhitespaceChars("")
-        lbrack, rbrack, lbrace, rbrace, lparen, rparen, colon, qmark = map(
-            Literal, "{}():?"
-        )
-
-        reMacro = Combine("\\" + oneOf(list("dws")))
-        escapedChar = ~reMacro + Combine("\\" + oneOf(list(printables)))
-        reLiteralChar = (
-            "".join(c for c in printables if c not in r"\{}().*?+|") + " \t"
-        )
-
-        reRange = Combine(lbrack + SkipTo(rbrack, ignore=escapedChar) + rbrack)
-        reLiteral = escapedChar | oneOf(list(reLiteralChar))
-        reNonCaptureGroup = Suppress("?:")
-        reDot = Literal(".")
-        repetition = (
-            (lbrace + Word(nums)("count") + rbrace)
-            | (lbrace + Word(nums)("minCount") + "," + Word(nums)("maxCount") + rbrace)
-            | oneOf(list("*+?"))
-        )
-
-        reRange.setParseAction(handleRange)
-        reLiteral.setParseAction(handleLiteral)
-        reMacro.setParseAction(handleMacro)
-        reDot.setParseAction(handleDot)
-
-        reTerm = reLiteral | reRange | reMacro | reDot | reNonCaptureGroup
-        reExpr = infixNotation(
-            reTerm,
-            
-                (repetition, 1, opAssoc.LEFT, handleRepetition),
-                (None, 2, opAssoc.LEFT, handleSequence),
-                (Suppress("|"), 2, opAssoc.LEFT, handleAlternative),
-            ,
-        )
-        _parser = reExpr
-
-    return _parser
-
-
-def count(gen):
-    """Simple function to count the number of elements returned by a generator."""
-    return sum(1 for _ in gen)
-
-
-def invert(regex):
-    r"""
-    Call this routine as a generator to return all the strings that
-    match the input regular expression.
-        for s in invert(r"A-Z{3}\d{3}"):
-            print s
-    """
-    invReGenerator = GroupEmitter(parser().parseString(regex)).makeGenerator()
-    return invReGenerator()
-
-
-def main():
-    tests = r"""
-    A-EA
-    A-D*
-    A-D{3}
-    XA-C{3}Y
-    XA-C{3}\(
-    X\d
-    foobar\d\d
-    foobar{2}
-    foobar{2,9}
-    foobarz{2}
-    (foobar){2}
-    (01\d)|(20-5)
-    (?:01\d)|(20-5)
-    (01\d\d)|(20-4\d)|(250-5)
-    A-C{1,2}
-    A-C{0,3}
-    A-C\sA-C\sA-C
-    A-C\s?A-CA-C
-    A-C\s(A-CA-C)
-    A-C\s(A-CA-C)?
-    A-C{2}\d{2}
-    @|TH12
-    @(@|TH12)?
-    @(@|TH12|AL12|SP123|TB(10-9?|20?|3-9))?
-    @(@|TH12|AL12|SP123|TB(10-9?|20?|3-9)|OH(10-9?|20-9?|30?|4-9))?
-    ((ECMP|HA|AK)SD|HS)T
-    A-CV{2}
-    Acglmrstu|Baehikr?|Cadeflmorsu?|Dbsy|Ersu|Femr?|Gade|Hefgos?|Inr?|Kr?|Lairu|Mdgnot|Nabdeiop?|Os?|Pabdmortu?|Rabefghnu|Sbcegimnr?|Tabcehilm|Uubhopqst|U|V|W|Xe|Yb?|Znr
-    (a|b)|(x|y)
-    (a|b) (x|y)
-    ABCDEFG(?:#|##|b|bb)?(?:maj|min|m|sus|aug|dim)?0-9?(?:/ABCDEFG(?:#|##|b|bb)?)?
-    (Fri|Mon|S(atur|un)|T(hur|ue)s|Wednes)day
-    A(pril|ugust)|((Dec|Nov|Sept)em|Octo)ber|(Febr|Jan)uary|Ju(ly|ne)|Ma(rch|y)
-    """.splitlines()
-
-    for t in tests:
-        t = t.strip()
-        if not t:
-            continue
-        print("-" * 50)
-        print(t)
-        try:
-            num = count(invert(t))
-            print(num)
-            maxprint = 30
-            for s in invert(t):
-                print(s)
-                maxprint -= 1
-                if not maxprint:
-                    break
-        except ParseFatalException as pfe:
-            print(pfe.msg)
-            print("")
-            continue
-        print("")
-
-
-if __name__ == "__main__":
-    main()

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/linenoExample.py Deleted

@@ -1,56 +0,0 @@
-#
-# linenoExample.py
-#
-# an example of using the location value returned by pyparsing to
-# extract the line and column number of the location of the matched text,
-# or to extract the entire line of text.
-#
-# Copyright (c) 2006, Paul McGuire
-#
-from pyparsing import *
-
-data = """Now is the time
-for all good men
-to come to the aid
-of their country."""
-
-# demonstrate use of lineno, line, and col in a parse action
-def reportLongWords(st, locn, toks):
-    word = toks0
-    if len(word) > 3:
-        print(
-            "Found '%s' on line %d at column %d"
-            % (word, lineno(locn, st), col(locn, st))
-        )
-        print("The full line of text was:")
-        print("'%s'" % line(locn, st))
-        print((" " * col(locn, st)) + " ^")
-        print()
-
-
-wd = Word(alphas).setParseAction(reportLongWords)
-OneOrMore(wd).parseString(data)
-
-
-# demonstrate returning an object from a parse action, containing more information
-# than just the matching token text
-class Token:
-    def __init__(self, st, locn, tokString):
-        self.tokenString = tokString
-        self.locn = locn
-        self.sourceLine = line(locn, st)
-        self.lineNo = lineno(locn, st)
-        self.col = col(locn, st)
-
-    def __str__(self):
-        return "%(tokenString)s (line: %(lineNo)d, col: %(col)d)" % self.__dict__
-
-
-def createTokenObject(st, locn, toks):
-    return Token(st, locn, toks0)
-
-
-wd = Word(alphas).setParseAction(createTokenObject)
-
-for tokenObj in OneOrMore(wd).parseString(data):
-    print(tokenObj)

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/macroExpander.py Deleted

@@ -1,61 +0,0 @@
-# macroExpander.py
-#
-# Example pyparsing program for performing macro expansion, similar to
-# the C pre-processor.  This program is not as fully-featured, simply
-# processing macros of the form:
-#     #def xxx yyyyy
-# and replacing xxx with yyyyy in the rest of the input string.  Macros
-# can also be composed using other macros, such as
-#     #def zzz xxx+1
-# Since xxx was previously defined as yyyyy, then zzz will be replaced
-# with yyyyy+1.
-#
-# Copyright 2007 by Paul McGuire
-#
-from pyparsing import *
-
-# define the structure of a macro definition (the empty term is used
-# to advance to the next non-whitespace character)
-identifier = Word(alphas + "_", alphanums + "_")
-macroDef = "#def" + identifier("macro") + empty + restOfLine("value")
-
-# define a placeholder for defined macros - initially nothing
-macroExpr = Forward()
-macroExpr << NoMatch()
-
-# global dictionary for macro definitions
-macros = {}
-
-# parse action for macro definitions
-def processMacroDefn(s, l, t):
-    macroVal = macroExpander.transformString(t.value)
-    macrost.macro = macroVal
-    macroExpr << MatchFirst(map(Keyword, macros.keys()))
-    return "#def " + t.macro + " " + macroVal
-
-
-# parse action to replace macro references with their respective definition
-def processMacroRef(s, l, t):
-    return macrost0
-
-
-# attach parse actions to expressions
-macroExpr.setParseAction(processMacroRef)
-macroDef.setParseAction(processMacroDefn)
-
-# define pattern for scanning through the input string
-macroExpander = macroExpr | macroDef
-
-
-# test macro substitution using transformString
-testString = """
-    #def A 100
-    #def ALEN A+1
-
-    char AstringALEN;
-    char AAA;
-    typedef charALEN Acharbuf;
-    """
-
-print(macroExpander.transformString(testString))
-print(macros)

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/parsePythonValue.py Deleted

@@ -1,71 +0,0 @@
-# parsePythonValue.py
-#
-# Copyright, 2006, by Paul McGuire
-#
-import pyparsing as pp
-
-
-cvtBool = lambda t: t0 == "True"
-cvtInt = lambda toks: int(toks0)
-cvtReal = lambda toks: float(toks0)
-cvtTuple = lambda toks: tuple(toks.asList())
-cvtDict = lambda toks: dict(toks.asList())
-cvtList = lambda toks: toks.asList()
-
-# define punctuation as suppressed literals
-lparen, rparen, lbrack, rbrack, lbrace, rbrace, colon, comma = map(
-    pp.Suppress, "(){}:,"
-)
-
-integer = pp.Regex(r"+-?\d+").setName("integer").setParseAction(cvtInt)
-real = pp.Regex(r"+-?\d+\.\d*(Ee+-?\d+)?").setName("real").setParseAction(cvtReal)
-tupleStr = pp.Forward()
-listStr = pp.Forward()
-dictStr = pp.Forward()
-
-unistr = pp.unicodeString().setParseAction(lambda t: t02:-1)
-quoted_str = pp.quotedString().setParseAction(lambda t: t01:-1)
-boolLiteral = pp.oneOf("True False", asKeyword=True).setParseAction(cvtBool)
-noneLiteral = pp.Keyword("None").setParseAction(pp.replaceWith(None))
-
-listItem = (
-    real
-    | integer
-    | quoted_str
-    | unistr
-    | boolLiteral
-    | noneLiteral
-    | pp.Group(listStr)
-    | tupleStr
-    | dictStr
-)
-
-tupleStr <<= (
-    lparen + pp.Optional(pp.delimitedList(listItem)) + pp.Optional(comma) + rparen
-)
-tupleStr.setParseAction(cvtTuple)
-
-listStr <<= (
-    lbrack + pp.Optional(pp.delimitedList(listItem) + pp.Optional(comma)) + rbrack
-)
-listStr.setParseAction(cvtList, lambda t: t0)
-
-dictEntry = pp.Group(listItem + colon + listItem)
-dictStr <<= (
-    lbrace + pp.Optional(pp.delimitedList(dictEntry) + pp.Optional(comma)) + rbrace
-)
-dictStr.setParseAction(cvtDict)
-
-if __name__ == "__main__":
-
-    tests = """'a', 100, ('A', 101,102), 3.14,  +2.718, 'xyzzy', -1.414 
-               {0: 2, 1: }, {0: , 1: , 2: }, {0: 1, 2}
-               { 'A':1, 'B':2, 'C': {'a': 1.2, 'b': 3.4} }
-               3.14159
-               42
-               6.02E23
-               6.02e+023
-               1.0e-7
-               'a quoted string'"""
-
-    listItem.runTests(tests)

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/parseResultsSumExample.py Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/pymicko.py Deleted

@@ -1,1738 +0,0 @@
-#!/usr/bin/python
-
-#    Python/pyparsing educational microC compiler v1.0
-#    Copyright (C) 2009  Zarko Zivanov
-#    (largely based on flex/bison microC compiler by Zorica Suvajdzin, used with her permission;
-#     current version can be found at http://www.acs.uns.ac.rs, under "Programski Prevodioci" Serbian site)
-#
-#    This program is free software: you can redistribute it and/or modify
-#    it under the terms of the GNU General Public License as published by
-#    the Free Software Foundation, either version 3 of the License, or
-#    (at your option) any later version.
-#
-#    This program is distributed in the hope that it will be useful,
-#    but WITHOUT ANY WARRANTY; without even the implied warranty of
-#    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-#    GNU General Public License for more details.
-#
-#    A copy of the GNU General Public License can be found at <https://www.gnu.org/licenses/>.
-
-from pyparsing import *
-from sys import stdin, argv, exit
-
-# defines debug level
-# 0 - no debug
-# 1 - print parsing results
-# 2 - print parsing results and symbol table
-# 3 - print parsing results only, without executing parse actions (grammar-only testing)
-DEBUG = 0
-
-##########################################################################################
-##########################################################################################
-
-#                               About microC language and microC compiler
-
-# microC language and microC compiler are educational tools, and their goal is to show some basic principles
-# of writing a C language compiler. Compiler represents one (relatively simple) solution, not necessarily the best one.
-# This Python/pyparsing version is made using Python 2.6.4 and pyparsing 1.5.2 (and it may contain errors :) )
-
-##########################################################################################
-##########################################################################################
-
-#                               Model of the used hypothetical processor
-
-# The reason behind using a hypothetical processor is to simplify code generation and to concentrate on the compiler itself.
-# This compiler can relatively easily be ported to x86, but one must know all the little details about which register
-# can be used for what, which registers are default for various operations, etc.
-
-# The hypothetical processor has 16 registers, called %0 to %15. Register %13 is used for the function return value (x86's eax),
-# %14 is the stack frame pointer (x86's ebp) and %15 is the stack pointer (x86's esp). All data-handling instructions can be
-# unsigned (suffix U), or signed (suffix S). These are ADD, SUB, MUL and DIV. These are three-address instructions,
-# the first two operands are input, the third one is output. Whether these operands are registers, memory or constant
-# is not relevant, all combinations are possible (except that output cannot be a constant). Constants are written with a $ prefix (10-base only).
-# Conditional jumps are handled by JXXY instructions, where XX is LT, GT, LE, GE, EQ, NE (less than, greater than, less than or equal, etc.)
-# and Y is U or S (unsigned or signed, except for JEQ i JNE). Unconditional jump is JMP. The move instruction is MOV.
-# Function handling is done using CALL, RET, PUSH and POP (C style function calls). Static data is defined using the WORD directive
-# (example: variable: WORD 1), whose only argument defines the number of locations that are reserved.
-
-##########################################################################################
-##########################################################################################
-
-#                               Grammar of The microC Programming Language
-# (small subset of C made for compiler course at Faculty of Technical Sciences, Chair for Applied Computer Sciences, Novi Sad, Serbia)
-
-# Patterns:
-
-# letter
-#  ->    "_" | "a" | "A" | "b" | "B" | "c" | "C" | "d" | "D" | "e" | "E" | "f"
-#      | "F" | "g" | "G" | "h" | "H" | "i" | "I" | "j" | "J" | "k" | "K" | "l"
-#      | "L" | "m" | "M" | "n" | "N" | "o" | "O" | "p" | "P" | "q" | "Q" | "r"
-#      | "R" | "s" | "S" | "t" | "T" | "u" | "U" | "v" | "V" | "w" | "W" | "x"
-#      | "X" | "y" | "Y" | "z" | "Z"
-
-# digit
-#  ->  "0" | "1" | "2" | "3" | "4" | "5" | "6" | "7" | "8" | "9"
-
-# identifier
-#  ->  letter ( letter | digit )*
-
-# int_constant
-#  ->  digit +
-
-# unsigned_constant
-#  ->  digit + ( "u" | "U" )
-
-# Productions:
-
-# program
-#  ->  variable_list function_list
-#  ->  function_list
-
-# variable_list
-#  ->  variable ";"
-#  ->  variable_list variable ";"
-
-# variable
-#  ->  type identifier
-
-# type
-#  ->  "int"
-#  ->  "unsigned"
-
-# function_list
-#  ->  function
-#  ->  function_list function
-
-# function
-#  ->  type identifier "(" parameters ")" body
-
-# parameters
-#  ->  <empty>
-#  ->  parameter_list
-
-# parameter_list
-#  ->  variable
-#  ->  parameter_list "," variable
-
-# body
-#  ->  "{" variable_list statement_list "}"
-#  ->  "{" statement_list "}"
-
-# statement_list
-#  ->  <empty>
-#  ->  statement_list statement
-
-# statement
-#  ->  assignement_statement
-#  ->  function_call_statement
-#  ->  if_statement
-#  ->  while_statement
-#  ->  return_statement
-#  ->  compound_statement
-
-# assignement_statement
-#  ->  identifier "=" num_exp ";"
-
-# num_exp
-#  ->  mul_exp
-#  ->  num_exp "+" mul_exp
-#  ->  num_exp "-" mul_exp
-
-# mul_exp
-#  ->  exp
-#  ->  mul_exp "*" exp
-#  ->  mul_exp "/" exp
-
-# exp
-#  ->  constant
-#  ->  identifier
-#  ->  function_call
-#  ->  "(" num_exp ")"
-#  ->  "+" exp
-#  ->  "-" exp
-
-# constant
-#  ->  int_constant
-#  ->  unsigned_constant
-
-# function_call
-#  ->  identifier "(" arguments ")"
-
-# arguments
-#  ->  <empty>
-#  ->  argument_list
-
-# argument_list
-#  ->  num_exp
-#  ->  argument_list "," num_exp
-
-# function_call_statement
-#  ->  function_call ";"
-
-# if_statement
-#  ->  "if" "(" log_exp ")" statement
-#  ->  "if" "(" log_exp ")" statement "else" statement
-#  ->   ->   ->   ->   ->   ->   -> ->   2
-
-# log_exp
-#  ->  and_exp
-#  ->  log_exp "||" and_exp
-
-# and_exp
-#  ->  rel_exp
-#  ->  and_exp "&&" rel_exp
-
-# rel_exp
-#  ->  num_exp  "<" num_exp
-#  ->  num_exp  ">" num_exp
-#  ->  num_exp  "<=" num_exp
-#  ->  num_exp  ">=" num_exp
-#  ->  num_exp  "==" num_exp
-#  ->  num_exp  "!=" num_exp
-
-# while_statement
-#  ->  "while" "(" log_exp ")" statement
-
-# return_statement
-#  ->  "return" num_exp ";"
-
-# compound_statement
-#  ->  "{" statement_list "}"
-
-# Comment: /* a comment */
-
-##########################################################################################
-##########################################################################################
-
-
-class Enumerate(dict):
-    """C enum emulation (original by Scott David Daniels)"""
-
-    def __init__(self, names):
-        for number, name in enumerate(names.split()):
-            setattr(self, name, number)
-            selfnumber = name
-
-
-class SharedData:
-    """Data used in all three main classes"""
-
-    # Possible kinds of symbol table entries
-    KINDS = Enumerate(
-        "NO_KIND WORKING_REGISTER GLOBAL_VAR FUNCTION PARAMETER LOCAL_VAR CONSTANT"
-    )
-    # Supported types of functions and variables
-    TYPES = Enumerate("NO_TYPE INT UNSIGNED")
-
-    # bit size of variables
-    TYPE_BIT_SIZE = 16
-    # min/max values of constants
-    MIN_INT = -(2 ** (TYPE_BIT_SIZE - 1))
-    MAX_INT = 2 ** (TYPE_BIT_SIZE - 1) - 1
-    MAX_UNSIGNED = 2 ** TYPE_BIT_SIZE - 1
-    # available working registers (the last one is the register for function's return value!)
-    REGISTERS = "%0 %1 %2 %3 %4 %5 %6 %7 %8 %9 %10 %11 %12 %13".split()
-    # register for function's return value
-    FUNCTION_REGISTER = len(REGISTERS) - 1
-    # the index of last working register
-    LAST_WORKING_REGISTER = len(REGISTERS) - 2
-    # list of relational operators
-    RELATIONAL_OPERATORS = "< > <= >= == !=".split()
-
-    def __init__(self):
-        # index of the currently parsed function
-        self.functon_index = 0
-        # name of the currently parsed function
-        self.functon_name = 0
-        # number of parameters of the currently parsed function
-        self.function_params = 0
-        # number of local variables of the currently parsed function
-        self.function_vars = 0
-
-
-##########################################################################################
-##########################################################################################
-
-
-class ExceptionSharedData:
-    """Class for exception handling data"""
-
-    def __init__(self):
-        # position in currently parsed text
-        self.location = 0
-        # currently parsed text
-        self.text = ""
-
-    def setpos(self, location, text):
-        """Helper function for setting currently parsed text and position"""
-        self.location = location
-        self.text = text
-
-
-exshared = ExceptionSharedData()
-
-
-class SemanticException(Exception):
-    """
-    Exception for semantic errors found during parsing, similar to ParseException.
-    Introduced because ParseException is used internally in pyparsing and custom
-    messages got lost and replaced by pyparsing's generic errors.
-    """
-
-    def __init__(self, message, print_location=True):
-        super().__init__()
-        self._message = message
-        self.location = exshared.location
-        self.print_location = print_location
-        if exshared.location != None:
-            self.line = lineno(exshared.location, exshared.text)
-            self.col = col(exshared.location, exshared.text)
-            self.text = line(exshared.location, exshared.text)
-        else:
-            self.line = self.col = self.text = None
-
-    def _get_message(self):
-        return self._message
-
-    def _set_message(self, message):
-        self._message = message
-
-    message = property(_get_message, _set_message)
-
-    def __str__(self):
-        """String representation of the semantic error"""
-        msg = "Error"
-        if self.print_location and (self.line != None):
-            msg += " at line %d, col %d" % (self.line, self.col)
-        msg += ": %s" % self.message
-        if self.print_location and (self.line != None):
-            msg += "\n%s" % self.text
-        return msg
-
-
-##########################################################################################
-##########################################################################################
-
-
-class SymbolTableEntry:
-    """Class which represents one symbol table entry."""
-
-    def __init__(self, sname="", skind=0, stype=0, sattr=None, sattr_name="None"):
-        """
-        Initialization of symbol table entry.
-        sname - symbol name
-        skind - symbol kind
-        stype - symbol type
-        sattr - symbol attribute
-        sattr_name - symbol attribute name (used only for table display)
-        """
-        self.name = sname
-        self.kind = skind
-        self.type = stype
-        self.attribute = sattr
-        self.attribute_name = sattr_name
-        self.param_types = 
-
-    def set_attribute(self, name, value):
-        """Sets attribute's name and value"""
-        self.attribute_name = name
-        self.attribute = value
-
-    def attribute_str(self):
-        """Returns attribute string (used only for table display)"""
-        return (
-            "{}={}".format(self.attribute_name, self.attribute)
-            if self.attribute != None
-            else "None"
-        )
-
-
-class SymbolTable:
-    """Class for symbol table of microC program"""
-
-    def __init__(self, shared):
-        """Initialization of the symbol table"""
-        self.table = 
-        self.lable_len = 0
-        # put working registers in the symbol table
-        for reg in range(SharedData.FUNCTION_REGISTER + 1):
-            self.insert_symbol(
-                SharedData.REGISTERSreg,
-                SharedData.KINDS.WORKING_REGISTER,
-                SharedData.TYPES.NO_TYPE,
-            )
-        # shared data
-        self.shared = shared
-
-    def error(self, text=""):
-        """
-        Symbol table error exception. It should happen only if index is out of range while accessing symbol table.
-        This exception is not handled by the compiler, so as to allow traceback printing
-        """
-        if text == "":
-            raise Exception("Symbol table index out of range")
-        else:
-            raise Exception("Symbol table error: %s" % text)
-
-    def display(self):
-        """Displays the symbol table content"""
-        # Finding the maximum length for each column
-        sym_name = "Symbol name"
-        sym_len = max(max(len(i.name) for i in self.table), len(sym_name))
-        kind_name = "Kind"
-        kind_len = max(
-            max(len(SharedData.KINDSi.kind) for i in self.table), len(kind_name)
-        )
-        type_name = "Type"
-        type_len = max(
-            max(len(SharedData.TYPESi.type) for i in self.table), len(type_name)
-        )
-        attr_name = "Attribute"
-        attr_len = max(max(len(i.attribute_str()) for i in self.table), len(attr_name))
-        # print table header
-        print(
-            "{0:3s} | {1:^{2}s} | {3:^{4}s} | {5:^{6}s} | {7:^{8}} | {9:s}".format(
-                " No",
-                sym_name,
-                sym_len,
-                kind_name,
-                kind_len,
-                type_name,
-                type_len,
-                attr_name,
-                attr_len,
-                "Parameters",
-            )
-        )
-        print(
-            "-----------------------------"
-            + "-" * (sym_len + kind_len + type_len + attr_len)
-        )
-        # print symbol table
-        for i, sym in enumerate(self.table):
-            parameters = ""
-            for p in sym.param_types:
-                if parameters == "":
-                    parameters = "{}".format(SharedData.TYPESp)
-                else:
-                    parameters += ", {}".format(SharedData.TYPESp)
-            print(
-                "{0:3d} | {1:^{2}s} | {3:^{4}s} | {5:^{6}s} | {7:^{8}} | ({9})".format(
-                    i,
-                    sym.name,
-                    sym_len,
-                    SharedData.KINDSsym.kind,
-                    kind_len,
-                    SharedData.TYPESsym.type,
-                    type_len,
-                    sym.attribute_str(),
-                    attr_len,
-                    parameters,
-                )
-            )
-
-    def insert_symbol(self, sname, skind, stype):
-        """
-        Inserts new symbol at the end of the symbol table.
-        Returns symbol index
-        sname - symbol name
-        skind - symbol kind
-        stype - symbol type
-        """
-        self.table.append(SymbolTableEntry(sname, skind, stype))
-        self.table_len = len(self.table)
-        return self.table_len - 1
-
-    def clear_symbols(self, index):
-        """Clears all symbols beginning with the index to the end of table"""
-        try:
-            del self.tableindex:
-        except Exception:
-            self.error()
-        self.table_len = len(self.table)
-
-    def lookup_symbol(
-        self,
-        sname,
-        skind=list(SharedData.KINDS.keys()),
-        stype=list(SharedData.TYPES.keys()),
-    ):
-        """
-        Searches for symbol, from the end to the beginning.
-        Returns symbol index or None
-        sname - symbol name
-        skind - symbol kind (one kind, list of kinds, or None) default: any kind
-        stype - symbol type (or None) default: any type
-        """
-        skind = skind if isinstance(skind, list) else skind
-        stype = stype if isinstance(stype, list) else stype
-        for i, sym in 
-            x, self.tablex
-            for x in range(len(self.table) - 1, SharedData.LAST_WORKING_REGISTER, -1)
-        :
-            if (sym.name == sname) and (sym.kind in skind) and (sym.type in stype):
-                return i
-        return None
-
-    def insert_id(self, sname, skind, skinds, stype):
-        """
-        Inserts a new identifier at the end of the symbol table, if possible.
-        Returns symbol index, or raises an exception if the symbol already exists
-        sname   - symbol name
-        skind   - symbol kind
-        skinds  - symbol kinds to check for
-        stype   - symbol type
-        """
-        index = self.lookup_symbol(sname, skinds)
-        if index == None:
-            index = self.insert_symbol(sname, skind, stype)
-            return index
-        else:
-            raise SemanticException("Redefinition of '%s'" % sname)
-
-    def insert_global_var(self, vname, vtype):
-        "Inserts a new global variable"
-        return self.insert_id(
-            vname,
-            SharedData.KINDS.GLOBAL_VAR,
-            SharedData.KINDS.GLOBAL_VAR, SharedData.KINDS.FUNCTION,
-            vtype,
-        )
-
-    def insert_local_var(self, vname, vtype, position):
-        "Inserts a new local variable"
-        index = self.insert_id(
-            vname,
-            SharedData.KINDS.LOCAL_VAR,
-            SharedData.KINDS.LOCAL_VAR, SharedData.KINDS.PARAMETER,
-            vtype,
-        )
-        self.tableindex.attribute = position
-
-    def insert_parameter(self, pname, ptype):
-        "Inserts a new parameter"
-        index = self.insert_id(
-            pname, SharedData.KINDS.PARAMETER, SharedData.KINDS.PARAMETER, ptype
-        )
-        # set parameter's attribute to it's ordinal number
-        self.tableindex.set_attribute("Index", self.shared.function_params)
-        # set parameter's type in param_types list of a function
-        self.tableself.shared.function_index.param_types.append(ptype)
-        return index
-
-    def insert_function(self, fname, ftype):
-        "Inserts a new function"
-        index = self.insert_id(
-            fname,
-            SharedData.KINDS.FUNCTION,
-            SharedData.KINDS.GLOBAL_VAR, SharedData.KINDS.FUNCTION,
-            ftype,
-        )
-        self.tableindex.set_attribute("Params", 0)
-        return index
-
-    def insert_constant(self, cname, ctype):
-        """
-        Inserts a constant (or returns index if the constant already exists)
-        Additionally, checks for range.
-        """
-        index = self.lookup_symbol(cname, stype=ctype)
-        if index == None:
-            num = int(cname)
-            if ctype == SharedData.TYPES.INT:
-                if (num < SharedData.MIN_INT) or (num > SharedData.MAX_INT):
-                    raise SemanticException(
-                        "Integer constant '%s' out of range" % cname
-                    )
-            elif ctype == SharedData.TYPES.UNSIGNED:
-                if (num < 0) or (num > SharedData.MAX_UNSIGNED):
-                    raise SemanticException(
-                        "Unsigned constant '%s' out of range" % cname
-                    )
-            index = self.insert_symbol(cname, SharedData.KINDS.CONSTANT, ctype)
-        return index
-
-    def same_types(self, index1, index2):
-        """Returns True if both symbol table elements are of the same type"""
-        try:
-            same = (
-                self.tableindex1.type
-                == self.tableindex2.type
-                != SharedData.TYPES.NO_TYPE
-            )
-        except Exception:
-            self.error()
-        return same
-
-    def same_type_as_argument(self, index, function_index, argument_number):
-        """
-        Returns True if index and function's argument are of the same type
-        index - index in symbol table
-        function_index - function's index in symbol table
-        argument_number - # of function's argument
-        """
-        try:
-            same = (
-                self.tablefunction_index.param_typesargument_number
-                == self.tableindex.type
-            )
-        except Exception:
-            self.error()
-        return same
-
-    def get_attribute(self, index):
-        try:
-            return self.tableindex.attribute
-        except Exception:
-            self.error()
-
-    def set_attribute(self, index, value):
-        try:
-            self.tableindex.attribute = value
-        except Exception:
-            self.error()
-
-    def get_name(self, index):
-        try:
-            return self.tableindex.name
-        except Exception:
-            self.error()
-
-    def get_kind(self, index):
-        try:
-            return self.tableindex.kind
-        except Exception:
-            self.error()
-
-    def get_type(self, index):
-        try:
-            return self.tableindex.type
-        except Exception:
-            self.error()
-
-    def set_type(self, index, stype):
-        try:
-            self.tableindex.type = stype
-        except Exception:
-            self.error()
-
-
-##########################################################################################
-##########################################################################################
-
-
-class CodeGenerator:
-    """Class for code generation methods."""
-
-    # dictionary of relational operators
-    RELATIONAL_DICT = {op: i for i, op in enumerate(SharedData.RELATIONAL_OPERATORS)}
-    # conditional jumps for relational operators
-    CONDITIONAL_JUMPS = 
-        "JLTS",
-        "JGTS",
-        "JLES",
-        "JGES",
-        "JEQ ",
-        "JNE ",
-        "JLTU",
-        "JGTU",
-        "JLEU",
-        "JGEU",
-        "JEQ ",
-        "JNE ",
-    
-    # opposite conditional jumps for relational operators
-    OPPOSITE_JUMPS = 
-        "JGES",
-        "JLES",
-        "JGTS",
-        "JLTS",
-        "JNE ",
-        "JEQ ",
-        "JGEU",
-        "JLEU",
-        "JGTU",
-        "JLTU",
-        "JNE ",
-        "JEQ ",
-    
-    # supported operations
-    OPERATIONS = {"+": "ADD", "-": "SUB", "*": "MUL", "/": "DIV"}
-    # suffixes for signed and unsigned operations (if no type is specified, unsigned will be assumed)
-    OPSIGNS = {
-        SharedData.TYPES.NO_TYPE: "U",
-        SharedData.TYPES.INT: "S",
-        SharedData.TYPES.UNSIGNED: "U",
-    }
-    # text at start of data segment
-    DATA_START_TEXT = "#DATA"
-    # text at start of code segment
-    CODE_START_TEXT = "#CODE"
-
-    def __init__(self, shared, symtab):
-        # generated code
-        self.code = ""
-        # prefix for internal labels
-        self.internal = "@"
-        # suffix for label definition
-        self.definition = ":"
-        # list of free working registers
-        self.free_registers = list(range(SharedData.FUNCTION_REGISTER, -1, -1))
-        # list of used working registers
-        self.used_registers = 
-        # list of used registers needed when function call is inside of a function call
-        self.used_registers_stack = 
-        # shared data
-        self.shared = shared
-        # symbol table
-        self.symtab = symtab
-
-    def error(self, text):
-        """
-        Compiler error exception. It should happen only if something is wrong with compiler.
-        This exception is not handled by the compiler, so as to allow traceback printing
-        """
-        raise Exception("Compiler error: %s" % text)
-
-    def take_register(self, rtype=SharedData.TYPES.NO_TYPE):
-        """Reserves one working register and sets its type"""
-        if len(self.free_registers) == 0:
-            self.error("no more free registers")
-        reg = self.free_registers.pop()
-        self.used_registers.append(reg)
-        self.symtab.set_type(reg, rtype)
-        return reg
-
-    def take_function_register(self, rtype=SharedData.TYPES.NO_TYPE):
-        """Reserves register for function return value and sets its type"""
-        reg = SharedData.FUNCTION_REGISTER
-        if reg not in self.free_registers:
-            self.error("function register already taken")
-        self.free_registers.remove(reg)
-        self.used_registers.append(reg)
-        self.symtab.set_type(reg, rtype)
-        return reg
-
-    def free_register(self, reg):
-        """Releases working register"""
-        if reg not in self.used_registers:
-            self.error("register %s is not taken" % self.REGISTERSreg)
-        self.used_registers.remove(reg)
-        self.free_registers.append(reg)
-        self.free_registers.sort(reverse=True)
-
-    def free_if_register(self, index):
-        """If index is a working register, free it, otherwise just return (helper function)"""
-        if (index < 0) or (index > SharedData.FUNCTION_REGISTER):
-            return
-        else:
-            self.free_register(index)
-
-    def label(self, name, internal=False, definition=False):
-        """
-        Generates label name (helper function)
-        name - label name
-        internal - boolean value, adds "@" prefix to label
-        definition - boolean value, adds ":" suffix to label
-        """
-        return "{}{}{}".format(
-            self.internal if internal else "",
-            name,
-            self.definition if definition else "",
-        )
-
-    def symbol(self, index):
-        """Generates symbol name from index"""
-        # if index is actually a string, just return it
-        if isinstance(index, str):
-            return index
-        elif (index < 0) or (index >= self.symtab.table_len):
-            self.error("symbol table index out of range")
-        sym = self.symtab.tableindex
-        # local variables are located at negative offset from frame pointer register
-        if sym.kind == SharedData.KINDS.LOCAL_VAR:
-            return "-{}(1:%14)".format(sym.attribute * 4 + 4)
-        # parameters are located at positive offset from frame pointer register
-        elif sym.kind == SharedData.KINDS.PARAMETER:
-            return "{}(1:%14)".format(8 + sym.attribute * 4)
-        elif sym.kind == SharedData.KINDS.CONSTANT:
-            return "${}".format(sym.name)
-        else:
-            return "{}".format(sym.name)
-
-    def save_used_registers(self):
-        """Pushes all used working registers before function call"""
-        used = self.used_registers:
-        del self.used_registers:
-        self.used_registers_stack.append(used:)
-        used.sort()
-        for reg in used:
-            self.newline_text("PUSH\t%s" % SharedData.REGISTERSreg, True)
-        self.free_registers.extend(used)
-        self.free_registers.sort(reverse=True)
-
-    def restore_used_registers(self):
-        """Pops all used working registers after function call"""
-        used = self.used_registers_stack.pop()
-        self.used_registers = used:
-        used.sort(reverse=True)
-        for reg in used:
-            self.newline_text("POP \t%s" % SharedData.REGISTERSreg, True)
-            self.free_registers.remove(reg)
-
-    def text(self, text):
-        """Inserts text into generated code"""
-        self.code += text
-
-    def prepare_data_segment(self):
-        """Inserts text at the start of data segment"""
-        self.text(self.DATA_START_TEXT)
-
-    def prepare_code_segment(self):
-        """Inserts text at the start of code segment"""
-        self.newline_text(self.CODE_START_TEXT)
-
-    def newline(self, indent=False):
-        """Inserts a newline, optionally with indentation."""
-        self.text("\n")
-        if indent:
-            self.text("\t\t\t")
-
-    def newline_text(self, text, indent=False):
-        """
-        Inserts a newline and text, optionally with indentation (helper function)
-        """
-        self.newline(indent)
-        self.text(text)
-
-    def newline_label(self, name, internal=False, definition=False):
-        """
-        Inserts a newline and a label (helper function)
-        name - label name
-        internal - boolean value, adds "@" prefix to label
-        definition - boolean value, adds ":" suffix to label
-        """
-        self.newline_text(
-            self.label(
-                "{}{}{}".format(
-                    "@" if internal else "", name, ":" if definition else ""
-                )
-            )
-        )
-
-    def global_var(self, name):
-        """Inserts a new static (global) variable definition"""
-        self.newline_label(name, False, True)
-        self.newline_text("WORD\t1", True)
-
-    def arithmetic_mnemonic(self, op_name, op_type):
-        """
-        Generates an arithmetic instruction mnemonic
-        """
-        return self.OPERATIONSop_name + self.OPSIGNSop_type
-
-    def arithmetic(self, operation, operand1, operand2, operand3=None):
-        """
-        Generates an arithmetic instruction
-        operation - one of supporetd operations
-        operandX - index in symbol table or text representation of operand
-        First two operands are input, third one is output
-        """
-        if isinstance(operand1, int):
-            output_type = self.symtab.get_type(operand1)
-            self.free_if_register(operand1)
-        else:
-            output_type = None
-        if isinstance(operand2, int):
-            output_type = (
-                self.symtab.get_type(operand2) if output_type == None else output_type
-            )
-            self.free_if_register(operand2)
-        else:
-            output_type = (
-                SharedData.TYPES.NO_TYPE if output_type == None else output_type
-            )
-        # if operand3 is not defined, reserve one free register for it
-        output = self.take_register(output_type) if operand3 == None else operand3
-        mnemonic = self.arithmetic_mnemonic(operation, output_type)
-        self.newline_text(
-            "{}\t{},{},{}".format(
-                mnemonic,
-                self.symbol(operand1),
-                self.symbol(operand2),
-                self.symbol(output),
-            ),
-            True,
-        )
-        return output
-
-    def relop_code(self, relop, operands_type):
-        """
-        Returns code for relational operator
-        relop - relational operator
-        operands_type - int or unsigned
-        """
-        code = self.RELATIONAL_DICTrelop
-        offset = (
-            0
-            if operands_type == SharedData.TYPES.INT
-            else len(SharedData.RELATIONAL_OPERATORS)
-        )
-        return code + offset
-
-    def jump(self, relcode, opposite, label):
-        """
-        Generates a jump instruction
-        relcode  - relational operator code
-        opposite - generate normal or opposite jump
-        label    - jump label
-        """
-        jump = (
-            self.OPPOSITE_JUMPSrelcode
-            if opposite
-            else self.CONDITIONAL_JUMPSrelcode
-        )
-        self.newline_text("{}\t{}".format(jump, label), True)
-
-    def unconditional_jump(self, label):
-        """
-        Generates an unconditional jump instruction
-        label    - jump label
-        """
-        self.newline_text("JMP \t{}".format(label), True)
-
-    def move(self, operand1, operand2):
-        """
-        Generates a move instruction
-        If the output operand (opernad2) is a working register, sets it's type
-        operandX - index in symbol table or text representation of operand
-        """
-        if isinstance(operand1, int):
-            output_type = self.symtab.get_type(operand1)
-            self.free_if_register(operand1)
-        else:
-            output_type = SharedData.TYPES.NO_TYPE
-        self.newline_text(
-            "MOV \t{},{}".format(self.symbol(operand1), self.symbol(operand2)), True
-        )
-        if isinstance(operand2, int):
-            if self.symtab.get_kind(operand2) == SharedData.KINDS.WORKING_REGISTER:
-                self.symtab.set_type(operand2, output_type)
-
-    def push(self, operand):
-        """Generates a push operation"""
-        self.newline_text("PUSH\t%s" % self.symbol(operand), True)
-
-    def pop(self, operand):
-        """Generates a pop instruction"""
-        self.newline_text("POP \t%s" % self.symbol(operand), True)
-
-    def compare(self, operand1, operand2):
-        """
-        Generates a compare instruction
-        operandX - index in symbol table
-        """
-        typ = self.symtab.get_type(operand1)
-        self.free_if_register(operand1)
-        self.free_if_register(operand2)
-        self.newline_text(
-            "CMP{}\t{},{}".format(
-                self.OPSIGNStyp, self.symbol(operand1), self.symbol(operand2)
-            ),
-            True,
-        )
-
-    def function_begin(self):
-        """Inserts function name label and function frame initialization"""
-        self.newline_label(self.shared.function_name, False, True)
-        self.push("%14")
-        self.move("%15", "%14")
-
-    def function_body(self):
-        """Inserts a local variable initialization and body label"""
-        if self.shared.function_vars > 0:
-            const = self.symtab.insert_constant(
-                "0{}".format(self.shared.function_vars * 4), SharedData.TYPES.UNSIGNED
-            )
-            self.arithmetic("-", "%15", const, "%15")
-        self.newline_label(self.shared.function_name + "_body", True, True)
-
-    def function_end(self):
-        """Inserts an exit label and function return instructions"""
-        self.newline_label(self.shared.function_name + "_exit", True, True)
-        self.move("%14", "%15")
-        self.pop("%14")
-        self.newline_text("RET", True)
-
-    def function_call(self, function, arguments):
-        """
-        Generates code for a function call
-        function - function index in symbol table
-        arguments - list of arguments (indexes in symbol table)
-        """
-        # push each argument to stack
-        for arg in arguments:
-            self.push(self.symbol(arg))
-            self.free_if_register(arg)
-        self.newline_text("CALL\t" + self.symtab.get_name(function), True)
-        args = self.symtab.get_attribute(function)
-        # generates stack cleanup if function has arguments
-        if args > 0:
-            args_space = self.symtab.insert_constant(
-                "{}".format(args * 4), SharedData.TYPES.UNSIGNED
-            )
-            self.arithmetic("+", "%15", args_space, "%15")
-
-
-##########################################################################################
-##########################################################################################
-
-
-class MicroC:
-    """Class for microC parser/compiler"""
-
-    def __init__(self):
-        # Definitions of terminal symbols for microC programming language
-        self.tId = Word(alphas + "_", alphanums + "_")
-        self.tInteger = Word(nums).setParseAction(
-            lambda x: x0, SharedData.TYPES.INT
-        )
-        self.tUnsigned = Regex(r"0-9+uU").setParseAction(
-            lambda x: x0:-1, SharedData.TYPES.UNSIGNED
-        )
-        self.tConstant = (self.tUnsigned | self.tInteger).setParseAction(
-            self.constant_action
-        )
-        self.tType = Keyword("int").setParseAction(
-            lambda x: SharedData.TYPES.INT
-        ) | Keyword("unsigned").setParseAction(lambda x: SharedData.TYPES.UNSIGNED)
-        self.tRelOp = oneOf(SharedData.RELATIONAL_OPERATORS)
-        self.tMulOp = oneOf("* /")
-        self.tAddOp = oneOf("+ -")
-
-        # Definitions of rules for global variables
-        self.rGlobalVariable = (
-            self.tType("type") + self.tId("name") + FollowedBy(";")
-        ).setParseAction(self.global_variable_action)
-        self.rGlobalVariableList = ZeroOrMore(self.rGlobalVariable + Suppress(";"))
-
-        # Definitions of rules for numeric expressions
-        self.rExp = Forward()
-        self.rMulExp = Forward()
-        self.rNumExp = Forward()
-        self.rArguments = delimitedList(
-            self.rNumExp("exp").setParseAction(self.argument_action)
-        )
-        self.rFunctionCall = (
-            (self.tId("name") + FollowedBy("(")).setParseAction(
-                self.function_call_prepare_action
-            )
-            + Suppress("(")
-            + Optional(self.rArguments)("args")
-            + Suppress(")")
-        ).setParseAction(self.function_call_action)
-        self.rExp << (
-            self.rFunctionCall
-            | self.tConstant
-            | self.tId("name").setParseAction(self.lookup_id_action)
-            | Group(Suppress("(") + self.rNumExp + Suppress(")"))
-            | Group("+" + self.rExp)
-            | Group("-" + self.rExp)
-        ).setParseAction(lambda x: x0)
-        self.rMulExp << (
-            self.rExp + ZeroOrMore(self.tMulOp + self.rExp)
-        ).setParseAction(self.mulexp_action)
-        self.rNumExp << (
-            self.rMulExp + ZeroOrMore(self.tAddOp + self.rMulExp)
-        ).setParseAction(self.numexp_action)
-
-        # Definitions of rules for logical expressions (these are without parenthesis support)
-        self.rAndExp = Forward()
-        self.rLogExp = Forward()
-        self.rRelExp = (self.rNumExp + self.tRelOp + self.rNumExp).setParseAction(
-            self.relexp_action
-        )
-        self.rAndExp << (
-            self.rRelExp("exp")
-            + ZeroOrMore(
-                Literal("&&").setParseAction(self.andexp_action) + self.rRelExp("exp")
-            ).setParseAction(lambda x: self.relexp_code)
-        )
-        self.rLogExp << (
-            self.rAndExp("exp")
-            + ZeroOrMore(
-                Literal("||").setParseAction(self.logexp_action) + self.rAndExp("exp")
-            ).setParseAction(lambda x: self.andexp_code)
-        )
-
-        # Definitions of rules for statements
-        self.rStatement = Forward()
-        self.rStatementList = Forward()
-        self.rReturnStatement = (
-            Keyword("return") + self.rNumExp("exp") + Suppress(";")
-        ).setParseAction(self.return_action)
-        self.rAssignmentStatement = (
-            self.tId("var") + Suppress("=") + self.rNumExp("exp") + Suppress(";")
-        ).setParseAction(self.assignment_action)
-        self.rFunctionCallStatement = self.rFunctionCall + Suppress(";")
-        self.rIfStatement = (
-            (Keyword("if") + FollowedBy("(")).setParseAction(self.if_begin_action)
-            + (Suppress("(") + self.rLogExp + Suppress(")")).setParseAction(
-                self.if_body_action
-            )
-            + (self.rStatement + Empty()).setParseAction(self.if_else_action)
-            + Optional(Keyword("else") + self.rStatement)
-        ).setParseAction(self.if_end_action)
-        self.rWhileStatement = (
-            (Keyword("while") + FollowedBy("(")).setParseAction(self.while_begin_action)
-            + (Suppress("(") + self.rLogExp + Suppress(")")).setParseAction(
-                self.while_body_action
-            )
-            + self.rStatement
-        ).setParseAction(self.while_end_action)
-        self.rCompoundStatement = Group(
-            Suppress("{") + self.rStatementList + Suppress("}")
-        )
-        self.rStatement << (
-            self.rReturnStatement
-            | self.rIfStatement
-            | self.rWhileStatement
-            | self.rFunctionCallStatement
-            | self.rAssignmentStatement
-            | self.rCompoundStatement
-        )
-        self.rStatementList << ZeroOrMore(self.rStatement)
-
-        self.rLocalVariable = (
-            self.tType("type") + self.tId("name") + FollowedBy(";")
-        ).setParseAction(self.local_variable_action)
-        self.rLocalVariableList = ZeroOrMore(self.rLocalVariable + Suppress(";"))
-        self.rFunctionBody = (
-            Suppress("{")
-            + Optional(self.rLocalVariableList).setParseAction(
-                self.function_body_action
-            )
-            + self.rStatementList
-            + Suppress("}")
-        )
-        self.rParameter = (self.tType("type") + self.tId("name")).setParseAction(
-            self.parameter_action
-        )
-        self.rParameterList = delimitedList(self.rParameter)
-        self.rFunction = (
-            (self.tType("type") + self.tId("name")).setParseAction(
-                self.function_begin_action
-            )
-            + Group(
-                Suppress("(")
-                + Optional(self.rParameterList)("params")
-                + Suppress(")")
-                + self.rFunctionBody
-            )
-        ).setParseAction(self.function_end_action)
-
-        self.rFunctionList = OneOrMore(self.rFunction)
-        self.rProgram = (
-            Empty().setParseAction(self.data_begin_action)
-            + self.rGlobalVariableList
-            + Empty().setParseAction(self.code_begin_action)
-            + self.rFunctionList
-        ).setParseAction(self.program_end_action)
-
-        # shared data
-        self.shared = SharedData()
-        # symbol table
-        self.symtab = SymbolTable(self.shared)
-        # code generator
-        self.codegen = CodeGenerator(self.shared, self.symtab)
-
-        # index of the current function call
-        self.function_call_index = -1
-        # stack for the nested function calls
-        self.function_call_stack = 
-        # arguments of the current function call
-        self.function_arguments = 
-        # stack for arguments of the nested function calls
-        self.function_arguments_stack = 
-        # number of arguments for the current function call
-        self.function_arguments_number = -1
-        # stack for the number of arguments for the nested function calls
-        self.function_arguments_number_stack = 
-
-        # last relational expression
-        self.relexp_code = None
-        # last and expression
-        self.andexp_code = None
-        # label number for "false" internal labels
-        self.false_label_number = -1
-        # label number for all other internal labels
-        self.label_number = None
-        # label stack for nested statements
-        self.label_stack = 
-
-    def warning(self, message, print_location=True):
-        """Displays warning message. Uses exshared for current location of parsing"""
-        msg = "Warning"
-        if print_location and (exshared.location != None):
-            wline = lineno(exshared.location, exshared.text)
-            wcol = col(exshared.location, exshared.text)
-            wtext = line(exshared.location, exshared.text)
-            msg += " at line %d, col %d" % (wline, wcol)
-        msg += ": %s" % message
-        if print_location and (exshared.location != None):
-            msg += "\n%s" % wtext
-        print(msg)
-
-    def data_begin_action(self):
-        """Inserts text at start of data segment"""
-        self.codegen.prepare_data_segment()
-
-    def code_begin_action(self):
-        """Inserts text at start of code segment"""
-        self.codegen.prepare_code_segment()
-
-    def global_variable_action(self, text, loc, var):
-        """Code executed after recognising a global variable"""
-        exshared.setpos(loc, text)
-        if DEBUG > 0:
-            print("GLOBAL_VAR:", var)
-            if DEBUG == 2:
-                self.symtab.display()
-            if DEBUG > 2:
-                return
-        index = self.symtab.insert_global_var(var.name, var.type)
-        self.codegen.global_var(var.name)
-        return index
-
-    def local_variable_action(self, text, loc, var):
-        """Code executed after recognising a local variable"""
-        exshared.setpos(loc, text)
-        if DEBUG > 0:
-            print("LOCAL_VAR:", var, var.name, var.type)
-            if DEBUG == 2:
-                self.symtab.display()
-            if DEBUG > 2:
-                return
-        index = self.symtab.insert_local_var(
-            var.name, var.type, self.shared.function_vars
-        )
-        self.shared.function_vars += 1
-        return index
-
-    def parameter_action(self, text, loc, par):
-        """Code executed after recognising a parameter"""
-        exshared.setpos(loc, text)
-        if DEBUG > 0:
-            print("PARAM:", par)
-            if DEBUG == 2:
-                self.symtab.display()
-            if DEBUG > 2:
-                return
-        index = self.symtab.insert_parameter(par.name, par.type)
-        self.shared.function_params += 1
-        return index
-
-    def constant_action(self, text, loc, const):
-        """Code executed after recognising a constant"""
-        exshared.setpos(loc, text)
-        if DEBUG > 0:
-            print("CONST:", const)
-            if DEBUG == 2:
-                self.symtab.display()
-            if DEBUG > 2:
-                return
-        return self.symtab.insert_constant(const0, const1)
-
-    def function_begin_action(self, text, loc, fun):
-        """Code executed after recognising a function definition (type and function name)"""
-        exshared.setpos(loc, text)
-        if DEBUG > 0:
-            print("FUN_BEGIN:", fun)
-            if DEBUG == 2:
-                self.symtab.display()
-            if DEBUG > 2:
-                return
-        self.shared.function_index = self.symtab.insert_function(fun.name, fun.type)
-        self.shared.function_name = fun.name
-        self.shared.function_params = 0
-        self.shared.function_vars = 0
-        self.codegen.function_begin()
-
-    def function_body_action(self, text, loc, fun):
-        """Code executed after recognising the beginning of function's body"""
-        exshared.setpos(loc, text)
-        if DEBUG > 0:
-            print("FUN_BODY:", fun)
-            if DEBUG == 2:
-                self.symtab.display()
-            if DEBUG > 2:
-                return
-        self.codegen.function_body()
-
-    def function_end_action(self, text, loc, fun):
-        """Code executed at the end of function definition"""
-        if DEBUG > 0:
-            print("FUN_END:", fun)
-            if DEBUG == 2:
-                self.symtab.display()
-            if DEBUG > 2:
-                return
-        # set function's attribute to number of function parameters
-        self.symtab.set_attribute(
-            self.shared.function_index, self.shared.function_params
-        )
-        # clear local function symbols (but leave function name)
-        self.symtab.clear_symbols(self.shared.function_index + 1)
-        self.codegen.function_end()
-
-    def return_action(self, text, loc, ret):
-        """Code executed after recognising a return statement"""
-        exshared.setpos(loc, text)
-        if DEBUG > 0:
-            print("RETURN:", ret)
-            if DEBUG == 2:
-                self.symtab.display()
-            if DEBUG > 2:
-                return
-        if not self.symtab.same_types(self.shared.function_index, ret.exp0):
-            raise SemanticException("Incompatible type in return")
-        # set register for function's return value to expression value
-        reg = self.codegen.take_function_register()
-        self.codegen.move(ret.exp0, reg)
-        # after return statement, register for function's return value is available again
-        self.codegen.free_register(reg)
-        # jump to function's exit
-        self.codegen.unconditional_jump(
-            self.codegen.label(self.shared.function_name + "_exit", True)
-        )
-
-    def lookup_id_action(self, text, loc, var):
-        """Code executed after recognising an identificator in expression"""
-        exshared.setpos(loc, text)
-        if DEBUG > 0:
-            print("EXP_VAR:", var)
-            if DEBUG == 2:
-                self.symtab.display()
-            if DEBUG > 2:
-                return
-        var_index = self.symtab.lookup_symbol(
-            var.name,
-            
-                SharedData.KINDS.GLOBAL_VAR,
-                SharedData.KINDS.PARAMETER,
-                SharedData.KINDS.LOCAL_VAR,
-            ,
-        )
-        if var_index == None:
-            raise SemanticException("'%s' undefined" % var.name)
-        return var_index
-
-    def assignment_action(self, text, loc, assign):
-        """Code executed after recognising an assignment statement"""
-        exshared.setpos(loc, text)
-        if DEBUG > 0:
-            print("ASSIGN:", assign)
-            if DEBUG == 2:
-                self.symtab.display()
-            if DEBUG > 2:
-                return
-        var_index = self.symtab.lookup_symbol(
-            assign.var,
-            
-                SharedData.KINDS.GLOBAL_VAR,
-                SharedData.KINDS.PARAMETER,
-                SharedData.KINDS.LOCAL_VAR,
-            ,
-        )
-        if var_index == None:
-            raise SemanticException("Undefined lvalue '%s' in assignment" % assign.var)
-        if not self.symtab.same_types(var_index, assign.exp0):
-            raise SemanticException("Incompatible types in assignment")
-        self.codegen.move(assign.exp0, var_index)
-
-    def mulexp_action(self, text, loc, mul):
-        """Code executed after recognising a mulexp expression (something *|/ something)"""
-        exshared.setpos(loc, text)
-        if DEBUG > 0:
-            print("MUL_EXP:", mul)
-            if DEBUG == 2:
-                self.symtab.display()
-            if DEBUG > 2:
-                return
-        # iterate through all multiplications/divisions
-        m = list(mul)
-        while len(m) > 1:
-            if not self.symtab.same_types(m0, m2):
-                raise SemanticException("Invalid opernads to binary '%s'" % m1)
-            reg = self.codegen.arithmetic(m1, m0, m2)
-            # replace first calculation with it's result
-            m0:3 = reg
-        return m0
-
-    def numexp_action(self, text, loc, num):
-        """Code executed after recognising a numexp expression (something +|- something)"""
-        exshared.setpos(loc, text)
-        if DEBUG > 0:
-            print("NUM_EXP:", num)
-            if DEBUG == 2:
-                self.symtab.display()
-            if DEBUG > 2:
-                return
-        # iterate through all additions/substractions
-        n = list(num)
-        while len(n) > 1:
-            if not self.symtab.same_types(n0, n2):
-                raise SemanticException("Invalid opernads to binary '%s'" % n1)
-            reg = self.codegen.arithmetic(n1, n0, n2)
-            # replace first calculation with it's result
-            n0:3 = reg
-        return n0
-
-    def function_call_prepare_action(self, text, loc, fun):
-        """Code executed after recognising a function call (type and function name)"""
-        exshared.setpos(loc, text)
-        if DEBUG > 0:
-            print("FUN_PREP:", fun)
-            if DEBUG == 2:
-                self.symtab.display()
-            if DEBUG > 2:
-                return
-        index = self.symtab.lookup_symbol(fun.name, SharedData.KINDS.FUNCTION)
-        if index == None:
-            raise SemanticException("'%s' is not a function" % fun.name)
-        # save any previous function call data (for nested function calls)
-        self.function_call_stack.append(self.function_call_index)
-        self.function_call_index = index
-        self.function_arguments_stack.append(self.function_arguments:)
-        del self.function_arguments:
-        self.codegen.save_used_registers()
-
-    def argument_action(self, text, loc, arg):
-        """Code executed after recognising each of function's arguments"""
-        exshared.setpos(loc, text)
-        if DEBUG > 0:
-            print("ARGUMENT:", arg.exp)
-            if DEBUG == 2:
-                self.symtab.display()
-            if DEBUG > 2:
-                return
-        arg_ordinal = len(self.function_arguments)
-        # check argument's type
-        if not self.symtab.same_type_as_argument(
-            arg.exp, self.function_call_index, arg_ordinal
-        ):
-            raise SemanticException(
-                "Incompatible type for argument %d in '%s'"
-                % (arg_ordinal + 1, self.symtab.get_name(self.function_call_index))
-            )
-        self.function_arguments.append(arg.exp)
-
-    def function_call_action(self, text, loc, fun):
-        """Code executed after recognising the whole function call"""
-        exshared.setpos(loc, text)
-        if DEBUG > 0:
-            print("FUN_CALL:", fun)
-            if DEBUG == 2:
-                self.symtab.display()
-            if DEBUG > 2:
-                return
-        # check number of arguments
-        if len(self.function_arguments) != self.symtab.get_attribute(
-            self.function_call_index
-        ):
-            raise SemanticException(
-                "Wrong number of arguments for function '%s'" % fun.name
-            )
-        # arguments should be pushed to stack in reverse order
-        self.function_arguments.reverse()
-        self.codegen.function_call(self.function_call_index, self.function_arguments)
-        self.codegen.restore_used_registers()
-        return_type = self.symtab.get_type(self.function_call_index)
-        # restore previous function call data
-        self.function_call_index = self.function_call_stack.pop()
-        self.function_arguments = self.function_arguments_stack.pop()
-        register = self.codegen.take_register(return_type)
-        # move result to a new free register, to allow the next function call
-        self.codegen.move(self.codegen.take_function_register(return_type), register)
-        return register
-
-    def relexp_action(self, text, loc, arg):
-        """Code executed after recognising a relexp expression (something relop something)"""
-        if DEBUG > 0:
-            print("REL_EXP:", arg)
-            if DEBUG == 2:
-                self.symtab.display()
-            if DEBUG > 2:
-                return
-        exshared.setpos(loc, text)
-        if not self.symtab.same_types(arg0, arg2):
-            raise SemanticException("Invalid operands for operator '{}'".format(arg1))
-        self.codegen.compare(arg0, arg2)
-        # return relational operator's code
-        self.relexp_code = self.codegen.relop_code(arg1, self.symtab.get_type(arg0))
-        return self.relexp_code
-
-    def andexp_action(self, text, loc, arg):
-        """Code executed after recognising a andexp expression (something and something)"""
-        exshared.setpos(loc, text)
-        if DEBUG > 0:
-            print("AND+EXP:", arg)
-            if DEBUG == 2:
-                self.symtab.display()
-            if DEBUG > 2:
-                return
-        label = self.codegen.label(
-            "false{}".format(self.false_label_number), True, False
-        )
-        self.codegen.jump(self.relexp_code, True, label)
-        self.andexp_code = self.relexp_code
-        return self.andexp_code
-
-    def logexp_action(self, text, loc, arg):
-        """Code executed after recognising logexp expression (something or something)"""
-        exshared.setpos(loc, text)
-        if DEBUG > 0:
-            print("LOG_EXP:", arg)
-            if DEBUG == 2:
-                self.symtab.display()
-            if DEBUG > 2:
-                return
-        label = self.codegen.label("true{}".format(self.label_number), True, False)
-        self.codegen.jump(self.relexp_code, False, label)
-        self.codegen.newline_label(
-            "false{}".format(self.false_label_number), True, True
-        )
-        self.false_label_number += 1
-
-    def if_begin_action(self, text, loc, arg):
-        """Code executed after recognising an if statement (if keyword)"""
-        exshared.setpos(loc, text)
-        if DEBUG > 0:
-            print("IF_BEGIN:", arg)
-            if DEBUG == 2:
-                self.symtab.display()
-            if DEBUG > 2:
-                return
-        self.false_label_number += 1
-        self.label_number = self.false_label_number
-        self.codegen.newline_label("if{}".format(self.label_number), True, True)
-
-    def if_body_action(self, text, loc, arg):
-        """Code executed after recognising if statement's body"""
-        exshared.setpos(loc, text)
-        if DEBUG > 0:
-            print("IF_BODY:", arg)
-            if DEBUG == 2:
-                self.symtab.display()
-            if DEBUG > 2:
-                return
-        # generate conditional jump (based on last compare)
-        label = self.codegen.label(
-            "false{}".format(self.false_label_number), True, False
-        )
-        self.codegen.jump(self.relexp_code, True, label)
-        # generate 'true' label (executes if condition is satisfied)
-        self.codegen.newline_label("true{}".format(self.label_number), True, True)
-        # save label numbers (needed for nested if/while statements)
-        self.label_stack.append(self.false_label_number)
-        self.label_stack.append(self.label_number)
-
-    def if_else_action(self, text, loc, arg):
-        """Code executed after recognising if statement's else body"""
-        exshared.setpos(loc, text)
-        if DEBUG > 0:
-            print("IF_ELSE:", arg)
-            if DEBUG == 2:
-                self.symtab.display()
-            if DEBUG > 2:
-                return
-        # jump to exit after all statements for true condition are executed
-        self.label_number = self.label_stack.pop()
-        label = self.codegen.label("exit{}".format(self.label_number), True, False)
-        self.codegen.unconditional_jump(label)
-        # generate final 'false' label (executes if condition isn't satisfied)
-        self.codegen.newline_label("false{}".format(self.label_stack.pop()), True, True)
-        self.label_stack.append(self.label_number)
-
-    def if_end_action(self, text, loc, arg):
-        """Code executed after recognising a whole if statement"""
-        exshared.setpos(loc, text)
-        if DEBUG > 0:
-            print("IF_END:", arg)
-            if DEBUG == 2:
-                self.symtab.display()
-            if DEBUG > 2:
-                return
-        self.codegen.newline_label("exit{}".format(self.label_stack.pop()), True, True)
-
-    def while_begin_action(self, text, loc, arg):
-        """Code executed after recognising a while statement (while keyword)"""
-        exshared.setpos(loc, text)
-        if DEBUG > 0:
-            print("WHILE_BEGIN:", arg)
-            if DEBUG == 2:
-                self.symtab.display()
-            if DEBUG > 2:
-                return
-        self.false_label_number += 1
-        self.label_number = self.false_label_number
-        self.codegen.newline_label("while{}".format(self.label_number), True, True)
-
-    def while_body_action(self, text, loc, arg):
-        """Code executed after recognising while statement's body"""
-        exshared.setpos(loc, text)
-        if DEBUG > 0:
-            print("WHILE_BODY:", arg)
-            if DEBUG == 2:
-                self.symtab.display()
-            if DEBUG > 2:
-                return
-        # generate conditional jump (based on last compare)
-        label = self.codegen.label(
-            "false{}".format(self.false_label_number), True, False
-        )
-        self.codegen.jump(self.relexp_code, True, label)
-        # generate 'true' label (executes if condition is satisfied)
-        self.codegen.newline_label("true{}".format(self.label_number), True, True)
-        self.label_stack.append(self.false_label_number)
-        self.label_stack.append(self.label_number)
-
-    def while_end_action(self, text, loc, arg):
-        """Code executed after recognising a whole while statement"""
-        exshared.setpos(loc, text)
-        if DEBUG > 0:
-            print("WHILE_END:", arg)
-            if DEBUG == 2:
-                self.symtab.display()
-            if DEBUG > 2:
-                return
-        # jump to condition checking after while statement body
-        self.label_number = self.label_stack.pop()
-        label = self.codegen.label("while{}".format(self.label_number), True, False)
-        self.codegen.unconditional_jump(label)
-        # generate final 'false' label and exit label
-        self.codegen.newline_label("false{}".format(self.label_stack.pop()), True, True)
-        self.codegen.newline_label("exit{}".format(self.label_number), True, True)
-
-    def program_end_action(self, text, loc, arg):
-        """Checks if there is a 'main' function and the type of 'main' function"""
-        exshared.setpos(loc, text)
-        if DEBUG > 0:
-            print("PROGRAM_END:", arg)
-            if DEBUG == 2:
-                self.symtab.display()
-            if DEBUG > 2:
-                return
-        index = self.symtab.lookup_symbol("main", SharedData.KINDS.FUNCTION)
-        if index == None:
-            raise SemanticException("Undefined reference to 'main'", False)
-        elif self.symtab.get_type(index) != SharedData.TYPES.INT:
-            self.warning("Return type of 'main' is not int", False)
-
-    def parse_text(self, text):
-        """Parse string (helper function)"""
-        try:
-            return self.rProgram.ignore(cStyleComment).parseString(text, parseAll=True)
-        except SemanticException as err:
-            print(err)
-            exit(3)
-        except ParseException as err:
-            print(err)
-            exit(3)
-
-    def parse_file(self, filename):
-        """Parse file (helper function)"""
-        try:
-            return self.rProgram.ignore(cStyleComment).parseFile(
-                filename, parseAll=True
-            )
-        except SemanticException as err:
-            print(err)
-            exit(3)
-        except ParseException as err:
-            print(err)
-            exit(3)
-
-
-##########################################################################################
-##########################################################################################
-if 0:
-    # main program
-    mc = MicroC()
-    output_file = "output.asm"
-
-    if len(argv) == 1:
-        input_file = stdin
-    elif len(argv) == 2:
-        input_file = argv1
-    elif len(argv) == 3:
-        input_file = argv1
-        output_file = argv2
-    else:
-        usage = """Usage: {} input_file output_file
-    If output file is omitted, output.asm is used
-    If input file is omitted, stdin is used""".format(
-            argv0
-        )
-        print(usage)
-        exit(1)
-    try:
-        parse = stdin if input_file == stdin else open(input_file, "r")
-    except Exception:
-        print("Input file '%s' open error" % input_file)
-        exit(2)
-    mc.parse_file(parse)
-    # if you want to see the final symbol table, uncomment next line
-    # mc.symtab.display()
-    try:
-        out = open(output_file, "w")
-        out.write(mc.codegen.code)
-        out.close
-    except Exception:
-        print("Output file '%s' open error" % output_file)
-        exit(2)
-
-##########################################################################################
-##########################################################################################
-
-if __name__ == "__main__":
-
-    test_program_example = """
-        int a;
-        int b;
-        int c;
-        unsigned d;
-
-        int fun1(int x, unsigned y) {
-            return 123;
-        }
-
-        int fun2(int a) {
-            return 1 + a * fun1(a, 456u);
-        }
-
-        int main(int x, int y) {
-            int w;
-            unsigned z;
-            if (9 > 8 && 2 < 3 || 6 != 5 && a <= b && c < x || w >= y) {
-                a = b + 1;
-                if (x == y)
-                    while (d < 4u)
-                        x = x * w;
-                else
-                    while (a + b < c - y && x > 3 || y < 2)
-                        if (z > d)
-                            a = a - 4;
-                        else
-                            b = a * b * c * x / y;
-            }
-            else
-                c = 4;
-            a = fun1(x,d) + fun2(fun1(fun2(w + 3 * 2) + 2 * c, 2u));
-            return 2;
-        }
-    """
-
-    mc = MicroC()
-    mc.parse_text(test_program_example)
-    print(mc.codegen.code)

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/rangeCheck.py Deleted

@@ -1,64 +0,0 @@
-# rangeCheck.py
-#
-#   A sample program showing how parse actions can convert parsed
-# strings into a data type or object, and to validate the parsed value.
-#
-# Updated to use new addCondition method and expr() copy.
-#
-# Copyright 2011,2015 Paul T. McGuire
-#
-
-from pyparsing import Word, nums, Suppress, Optional
-from datetime import datetime
-
-
-def ranged_value(expr, minval=None, maxval=None):
-    # have to specify at least one range boundary
-    if minval is None and maxval is None:
-        raise ValueError("minval or maxval must be specified")
-
-    # set range testing function and error message depending on
-    # whether either or both min and max values are given
-    inRangeCondition = {
-        (True, False): lambda s, l, t: t0 <= maxval,
-        (False, True): lambda s, l, t: minval <= t0,
-        (False, False): lambda s, l, t: minval <= t0 <= maxval,
-    }minval is None, maxval is None
-    outOfRangeMessage = {
-        (True, False): "value is greater than %s" % maxval,
-        (False, True): "value is less than %s" % minval,
-        (False, False): "value is not in the range ({} to {})".format(minval, maxval),
-    }minval is None, maxval is None
-
-    return expr().addCondition(inRangeCondition, message=outOfRangeMessage)
-
-
-# define the expressions for a date of the form YYYY/MM/DD or YYYY/MM (assumes YYYY/MM/01)
-integer = Word(nums).setName("integer")
-integer.setParseAction(lambda t: int(t0))
-
-month = ranged_value(integer, 1, 12)
-day = ranged_value(integer, 1, 31)
-year = ranged_value(integer, 2000, None)
-
-SLASH = Suppress("/")
-dateExpr = year("year") + SLASH + month("month") + Optional(SLASH + day("day"))
-dateExpr.setName("date")
-
-# convert date fields to datetime (also validates dates as truly valid dates)
-dateExpr.setParseAction(lambda t: datetime(t.year, t.month, t.day or 1).date())
-
-# add range checking on dates
-mindate = datetime(2002, 1, 1).date()
-maxdate = datetime.now().date()
-dateExpr = ranged_value(dateExpr, mindate, maxdate)
-
-
-dateExpr.runTests(
-    """
-    2011/5/8
-    2001/1/1
-    2004/2/29
-    2004/2
-    1999/12/31"""
-)

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/sparser.py Deleted

@@ -1,367 +0,0 @@
-#!/usr/bin/env python
-
-"""
-NAME:
-    sparser.py
-
-SYNOPSIS:
-    sparser.py options filename
-
-DESCRIPTION:
-    The sparser.py script is a Specified PARSER.  It is unique (as far as I can
-    tell) because it doesn't care about the delimiter(s).  The user specifies
-    what is expected, and the order, for each line of text.  All of the heavy
-    lifting is handled by pyparsing (http://pyparsing.sf.net).
-
-OPTIONS:
-    -h,--help        this message
-    -v,--version     version
-    -d,--debug       turn on debug messages
-
-EXAMPLES:
-    1. As standalone
-        sparser.py myfile
-    2. As library
-        import sparser
-        ...
-
-#Copyright (C) 2006  Tim Cera timcera@earthlink.net
-#
-#
-#    This program is free software; you can redistribute it and/or modify it
-#    under the terms of the GNU General Public License as published by the Free
-#    Software Foundation; either version 2 of the License, or (at your option)
-#    any later version.
-#
-#    This program is distributed in the hope that it will be useful, but
-#    WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-#    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-#    for more details.
-#
-#    You should have received a copy of the GNU General Public License along
-#    with this program; if not, write to the Free Software Foundation, Inc.,
-#    675 Mass Ave, Cambridge, MA 02139, USA.
-"""
-
-# ===imports======================
-import sys
-import os
-import getopt
-
-from pyparsing import *
-
-
-# ===globals======================
-modname = "sparser"
-__version__ = "0.1"
-
-
-# --option args--
-debug_p = 0
-# opt_b=None  #string arg, default is undefined
-
-
-# ---positional args, default is empty---
-pargs = 
-
-
-# ---other---
-
-
-# ===utilities====================
-def msg(txt):
-    """Send message to stdout."""
-    sys.stdout.write(txt)
-    sys.stdout.flush()
-
-
-def debug(ftn, txt):
-    """Used for debugging."""
-    if debug_p:
-        sys.stdout.write("{}.{}:{}\n".format(modname, ftn, txt))
-        sys.stdout.flush()
-
-
-def fatal(ftn, txt):
-    """If can't continue."""
-    msg = "{}.{}:FATAL:{}\n".format(modname, ftn, txt)
-    raise SystemExit(msg)
-
-
-def usage():
-    """Prints the docstring."""
-    print(__doc__)
-
-
-# ====================================
-class ToInteger(TokenConverter):
-    """Converter to make token into an integer."""
-
-    def postParse(self, instring, loc, tokenlist):
-        return int(tokenlist0)
-
-
-class ToFloat(TokenConverter):
-    """Converter to make token into a float."""
-
-    def postParse(self, instring, loc, tokenlist):
-        return float(tokenlist0)
-
-
-class ParseFileLineByLine:
-    """
-    Bring data from text files into a program, optionally parsing each line
-    according to specifications in a parse definition file.
-
-    ParseFileLineByLine instances can be used like normal file objects (i.e. by
-    calling readline(), readlines(), and write()), but can also be used as
-    sequences of lines in for-loops.
-
-    ParseFileLineByLine objects also handle compression transparently. i.e. it
-    is possible to read lines from a compressed text file as if it were not
-    compressed.  Compression is deduced from the file name suffixes '.Z'
-    (compress/uncompress), '.gz' (gzip/gunzip), and '.bz2' (bzip2).
-
-    The parse definition fi le name is developed based on the input file name.
-    If the input file name is 'basename.ext', then the definition file is
-    'basename_def.ext'.  If a definition file specific to the input file is not
-    found, then the program searches for the file 'sparse.def' which would be
-    the definition file for all files in that directory without a file specific
-    definition file.
-
-    Finally, ParseFileLineByLine objects accept file names that start with '~'
-    or '~user' to indicate a home directory, as well as URLs (for reading
-    only).
-
-    Constructor:
-    ParseFileLineByLine(|filename|, |mode|='"r"'), where |filename| is the name
-    of the file (or a URL) and |mode| is one of '"r"' (read), '"w"' (write) or
-    '"a"' (append, not supported for .Z files).
-    """
-
-    def __init__(self, filename, mode="r"):
-        """
-        Opens input file, and if available the definition file.  If the
-        definition file is available __init__ will then create some pyparsing
-        helper variables.
-        """
-        if mode not in "r", "w", "a":
-            raise OSError(0, "Illegal mode: " + repr(mode))
-
-        if string.find(filename, ":/") > 1:  # URL
-            if mode == "w":
-                raise OSError("can't write to a URL")
-            import urllib.request, urllib.parse, urllib.error
-
-            self.file = urllib.request.urlopen(filename)
-        else:
-            filename = os.path.expanduser(filename)
-            if mode == "r" or mode == "a":
-                if not os.path.exists(filename):
-                    raise OSError(2, "No such file or directory: " + filename)
-            filen, file_extension = os.path.splitext(filename)
-            command_dict = {
-                (".Z", "r"): "self.file = os.popen('uncompress -c ' + filename, mode)",
-                (".gz", "r"): "self.file = gzip.GzipFile(filename, 'rb')",
-                (".bz2", "r"): "self.file = os.popen('bzip2 -dc ' + filename, mode)",
-                (".Z", "w"): "self.file = os.popen('compress > ' + filename, mode)",
-                (".gz", "w"): "self.file = gzip.GzipFile(filename, 'wb')",
-                (".bz2", "w"): "self.file = os.popen('bzip2 > ' + filename, mode)",
-                (".Z", "a"): "raise IOError, (0, 'Can't append to .Z files')",
-                (".gz", "a"): "self.file = gzip.GzipFile(filename, 'ab')",
-                (".bz2", "a"): "raise IOError, (0, 'Can't append to .bz2 files')",
-            }
-
-            exec(
-                command_dict.get(
-                    (file_extension, mode), "self.file = open(filename, mode)"
-                )
-            )
-
-        self.grammar = None
-
-        # Try to find a parse ('*_def.ext') definition file.  First try to find
-        # a file specific parse definition file, then look for 'sparse.def'
-        # that would be the definition file for all files within the directory.
-
-        # The definition file is pure Python.  The one variable that needs to
-        # be specified is 'parse'.  The 'parse' variable is a list of tuples
-        # defining the name, type, and because it is a list, the order of
-        # variables on each line in the data file.  The variable name is a
-        # string, the type variable is defined as integer, real, and qString.
-
-        # parse = 
-        #          ('year', integer),
-        #          ('month', integer),
-        #          ('day', integer),
-        #          ('value', real),
-        #         
-
-        definition_file_one = filen + "_def" + file_extension
-        definition_file_two = os.path.dirname(filen) + os.sep + "sparse.def"
-        if os.path.exists(definition_file_one):
-            self.parsedef = definition_file_one
-        elif os.path.exists(definition_file_two):
-            self.parsedef = definition_file_two
-        else:
-            self.parsedef = None
-            return None
-
-        # Create some handy pyparsing constructs.  I kept 'decimal_sep' so that
-        # could easily change to parse if the decimal separator is a ",".
-        decimal_sep = "."
-        sign = oneOf("+ -")
-        # part of printables without decimal_sep, +, -
-        special_chars = string.replace(
-            "!\"#$%&'()*,./:;<=>?@\\^_`{|}~", decimal_sep, ""
-        )
-        integer = ToInteger(Combine(Optional(sign) + Word(nums))).setName("integer")
-        positive_integer = ToInteger(Combine(Optional("+") + Word(nums))).setName(
-            "integer"
-        )
-        negative_integer = ToInteger(Combine("-" + Word(nums))).setName("integer")
-        real = ToFloat(
-            Combine(
-                Optional(sign)
-                + Word(nums)
-                + decimal_sep
-                + Optional(Word(nums))
-                + Optional(oneOf("E e") + Word(nums))
-            )
-        ).setName("real")
-        positive_real = ToFloat(
-            Combine(
-                Optional("+")
-                + Word(nums)
-                + decimal_sep
-                + Optional(Word(nums))
-                + Optional(oneOf("E e") + Word(nums))
-            )
-        ).setName("real")
-        negative_real = ToFloat(
-            Combine(
-                "-"
-                + Word(nums)
-                + decimal_sep
-                + Optional(Word(nums))
-                + Optional(oneOf("E e") + Word(nums))
-            )
-        ).setName("real")
-        qString = (sglQuotedString | dblQuotedString).setName("qString")
-
-        # add other characters we should skip over between interesting fields
-        integer_junk = Optional(
-            Suppress(Word(alphas + special_chars + decimal_sep))
-        ).setName("integer_junk")
-        real_junk = Optional(Suppress(Word(alphas + special_chars))).setName(
-            "real_junk"
-        )
-        qString_junk = SkipTo(qString).setName("qString_junk")
-
-        # Now that 'integer', 'real', and 'qString' have been assigned I can
-        # execute the definition file.
-        exec(compile(open(self.parsedef).read(), self.parsedef, "exec"))
-
-        # Build the grammar, combination of the 'integer', 'real, 'qString',
-        # and '*_junk' variables assigned above in the order specified in the
-        # definition file.
-        grammar = 
-        for nam, expr in parse:
-            grammar.append(eval(expr.name + "_junk"))
-            grammar.append(expr.setResultsName(nam))
-        self.grammar = And(grammar1: + restOfLine)
-
-    def __del__(self):
-        """Delete (close) the file wrapper."""
-        self.close()
-
-    def __getitem__(self, item):
-        """Used in 'for line in fp:' idiom."""
-        line = self.readline()
-        if not line:
-            raise IndexError
-        return line
-
-    def readline(self):
-        """Reads (and optionally parses) a single line."""
-        line = self.file.readline()
-        if self.grammar and line:
-            try:
-                return self.grammar.parseString(line).asDict()
-            except ParseException:
-                return self.readline()
-        else:
-            return line
-
-    def readlines(self):
-        """Returns a list of all lines (optionally parsed) in the file."""
-        if self.grammar:
-            tot = 
-            # Used this way instead of a 'for' loop against
-            # self.file.readlines() so that there wasn't two copies of the file
-            # in memory.
-            while 1:
-                line = self.file.readline()
-                if not line:
-                    break
-                tot.append(line)
-            return tot
-        return self.file.readlines()
-
-    def write(self, data):
-        """Write to a file."""
-        self.file.write(data)
-
-    def writelines(self, list):
-        """Write a list to a file. Each item in the list is a line in the
-        file.
-        """
-        for line in list:
-            self.file.write(line)
-
-    def close(self):
-        """Close the file."""
-        self.file.close()
-
-    def flush(self):
-        """Flush in memory contents to file."""
-        self.file.flush()
-
-
-# =============================
-def main(pargs):
-    """This should only be used for testing. The primary mode of operation is
-    as an imported library.
-    """
-    input_file = sys.argv1
-    fp = ParseFileLineByLine(input_file)
-    for i in fp:
-        print(i)
-
-
-# -------------------------
-if __name__ == "__main__":
-    ftn = "main"
-    opts, pargs = getopt.getopt(
-        sys.argv1:, "hvd", "help", "version", "debug", "bb="
-    )
-    for opt in opts:
-        if opt0 == "-h" or opt0 == "--help":
-            print(modname + ": version=" + __version__)
-            usage()
-            sys.exit(0)
-        elif opt0 == "-v" or opt0 == "--version":
-            print(modname + ": version=" + __version__)
-            sys.exit(0)
-        elif opt0 == "-d" or opt0 == "--debug":
-            debug_p = 1
-        elif opt0 == "--bb":
-            opt_b = opt1
-
-    # ---make the object and run it---
-    main(pargs)
-
-# ===Revision Log===
-# Created by mkpythonproj:
-# 2006-02-06  Tim Cera
-#

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/Ctr3sr.v Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/INIT Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/RANDOM_GATE Deleted

@@ -1,106 +0,0 @@
-integer
-  delay_dev,
-
-  seed,
-  and_gate_seed,
-  addacc_conf_seed,
-  addacc_dro_seed,
-  addacc_t1ff_seed,
-  addacc1_dro_seed,
-  addacc1_t1ff_seed,
-  psr1_conf_seed,
-  psr1_dro_seed,
-  psr1_split_seed,
-  psr2_and_seed,
-  psr2_split_seed,
-  inv_cell_seed,
-  xor_gate_seed,
-  dro_cell_seed,
-  dro1_cell_seed,
-  tff_seed,
-
-  and_hs_dev,
-  addacc_dro_hs_dev,
-  addacc_t1ff_hs_dev,
-  addacc1_dro_hs_dev,
-  addacc1_t1ff_hs_dev,
-  psr1_dro_hs_dev,
-  psr2_and_hs_dev,
-  inv_hs_dev,
-  xor_hs_dev,
-  dro_hs_dev,
-  dro1_hs_dev;
-
-real
-  and_gate_variation,
-  addacc_conf_variation,
-  addacc_dro_variation,
-  addacc_t1ff_variation,
-  addacc1_dro_variation,
-  addacc1_t1ff_variation,
-  psr1_conf_variation,
-  psr1_dro_variation,
-  psr1_split_variation,
-  psr2_and_variation,
-  psr2_split_variation,
-  inv_cell_variation,
-  xor_gate_variation,
-  dro_cell_variation,
-  dro1_cell_variation,
-  tff_variation;
-
-initial
-
-  begin
-
-   	`include "SEED"
-
-  	and_gate_variation = 0.15;
-  	addacc_conf_variation = 0.2;
-  	addacc_dro_variation = 0.16;
-  	addacc_t1ff_variation = 0.2;
-  	addacc1_dro_variation = 0.16;
-  	addacc1_t1ff_variation = 0.2;
-  	psr1_conf_variation = 0.2;
-  	psr1_dro_variation = 0.16;
-  	psr1_split_variation = 0.2;
-  	psr2_and_variation = 0.15;
-  	psr2_split_variation = 0.2;
-  	inv_cell_variation = 0.14;
-  	xor_gate_variation = 0.17;
-  	dro_cell_variation = 0.16;
-  	dro1_cell_variation = 0.16;
-  	tff_variation = 0.2;
-
-	and_hs_dev = 3;
-  	addacc_dro_hs_dev = 2;
- 	addacc_t1ff_hs_dev = 3;
-  	addacc1_dro_hs_dev = 2;
- 	addacc1_t1ff_hs_dev = 3;
-	psr1_dro_hs_dev = 2;
-        psr2_and_hs_dev = 3;
-	inv_hs_dev = 2;
-	xor_hs_dev = 3;
-	dro_hs_dev = 2;
-	dro1_hs_dev = 2;
-
-
-	and_gate_seed = $random(seed);
-	addacc_conf_seed = $random(seed);
-	addacc_dro_seed = $random(seed);
-        addacc_t1ff_seed = $random(seed);
-	addacc1_dro_seed = $random(seed);
-        addacc1_t1ff_seed = $random(seed);
-        psr1_conf_seed = $random(seed);
-	psr1_dro_seed = $random(seed);
-        psr1_split_seed = $random(seed);
-	psr2_and_seed = $random(seed);
-        psr2_split_seed = $random(seed);
-        inv_cell_seed = $random(seed);
-        xor_gate_seed = $random(seed);        
-	dro_cell_seed = $random(seed);
-	dro1_cell_seed = $random(seed);
-	tff_seed = $random(seed);        
-
-  end
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/RANDOM_INTERCONNECT Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/SEED Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/TestCtr3sr.v Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/addacc.v Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/addacc1_dro.v Deleted

@@ -1,149 +0,0 @@
-// Verilog HDL for "RSFQ.lib", "dro_cell" "_functional"
-
-// Module DRO cell
-module addacc1_dro (d, clk, out);
-
-input
-	d, clk;
-
-output
-	out;
-reg 
-	out;
-
-parameter
-	t_hold	= -6,
-	t_setup	= 10,
-	delay	= 12,
-
-// multichannel description of a warning file
-	warning_file=2,  
-// multichannel description of a delay file
-	delay_file = warning_file<<1;
-
-reg
-	d_internal, clk_internal,
-	d_state,          	   // internal state at the input d
-	d_set;		   	   // signal determining the moment when
-				   // the state of the d input changes to "1"
-
-integer
-	data_delay,  // delay between d and d_internal
-	clk_delay,   // delay between clk and clk_internal
-	out_delay,   // delay between clk_internal and out
-	out_value,   // output value in a given clock cycle
-	last_clk_time,	// time when the last clock pulse appeared
-	vt_hold,	// variable hold
-	vt_setup,	// variable setup
-	vdelay;	     // variable delay
-
-`include "INIT"
-
-`ifdef RANDOM_DELAYS
-  `include "RANDOM_GATE"
-`endif
-
-initial 
-	begin
-		vt_hold = t_hold;
-		vt_setup = t_setup;
-		vdelay = delay;
-
-//`ifdef RANDOM_DELAYS
-		delay_dev = addacc1_dro_variation*delay;
-		vdelay = $dist_normal(addacc1_dro_seed, delay, delay_dev);
-		vt_hold = $dist_normal(addacc1_dro_seed, t_hold,
-                                        addacc1_dro_hs_dev);
-		vt_setup = t_setup + (t_hold - vt_hold);
-//`endif
-
-		#1 $fdisplay(delay_file, "module=%m, nom_delay=%0d, delay=%0d", delay, vdelay);
-		#1 $fdisplay(delay_file, "module=%m, nom_hold=%0d, hold=%0d", t_hold, vt_hold);
-		#1 $fdisplay(delay_file, "module=%m, nom_setup=%0d, setup=%0d", t_setup, vt_setup);
-
-
-// define delays between inputs & outputs and the corresponding
-//  internal auxiliary registers
-	  	if(vt_hold<0)
-		  begin
-	    	  	data_delay = -vt_hold;
-	    		clk_delay  = 0;
-			out_delay  = vdelay;
-		  end
-	  	else
-		  begin
-	   	  	data_delay = 0;
-	    		clk_delay  = vt_hold;
-		  	out_delay  = vdelay-vt_hold;
-		  end
-
-// clear internal registers and the output signal
-		d_internal = 0;
-		clk_internal = 0;
-		last_clk_time = 0;
-		d_state = 0;
-		d_set = 0;
-		out = 0;
-	end
-
-
-always @(posedge d) 	// Execute at positive edge of d
-	  d_internal <= #(data_delay) d;
-
-always @(posedge clk)  // Execute at positive edge of clk
-	  clk_internal <= #(clk_delay) clk;
-
-
-always @(posedge d_internal)
-	begin
-// setting the state of the d input
-                d_state <= d_state | 1'bx;
-		if (d_internal === 1)
-		  d_set <= #(vt_hold+vt_setup) 1;
-
-		d_internal <= 0;
-	end
-        
-
-always @(posedge d_set)
-	begin
-		if ($stime - last_clk_time >= vt_hold+vt_setup)
-			d_state = 1;
-		else
-		  begin
-			d_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input D pulse at %0d,",
-			 $stime-data_delay-vt_hold-vt_setup);
-			$fwrite(warning_file,
-			"\tClock pulse at %0d.\n", last_clk_time-clk_delay);
-		  end
-
-		d_set <= 0;
-	end
-
-
-always @(posedge clk_internal)	
-	begin
-// computing the output
-		if (clk_internal === 1'bx)
-		  out_value = 1'bx;
-		else
-		  out_value = d_state;
-
-// transfering the result to the output
-		out <= #(out_delay) out_value;
-		out <= #(out_delay+2) 0;
-
-// clearing the internal state of the DRO
-		d_state  <= 0;
-
-		clk_internal <= 0;
-		last_clk_time = $stime;
-	end
-
-endmodule

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/addacc1_t1ff.v Deleted

@@ -1,199 +0,0 @@
-// Verilog HDL for "RSFQ.lib", "t1ff" "_functional"
-
-// Module T1 flip-flop
-module addacc1_t1ff (t, wr0, out, rd1);
-
-input
-	t, wr0;
-
-output
-	out, rd1;
-reg 
-	out, rd1;
-
-parameter
-	t_separation 	=  8,
-	delay		= 35,
-	t_hold 		= -12,
-	t_setup 	= 32,
-	rd1_delay	= 17,
-
-// multichannel description of a warning file
-	warning_file=2,  
-// multichannel description of a delay file
-	delay_file = warning_file<<1;
-
-reg
-	t_internal, wr0_internal, // signals at inputs after i/o stage
-	t_state,  // internal state of T flip-flop
-	sep_clr,  // signal marking the end of the separation zone
-	hs_clr;	  // signal marking the end of the hold/setup zone
-
-
-integer
-	data_delay, 	// delay between t and t_internal
-	wr0_delay, 	// delay between rd and rd_internal
-	t_out_delay, 	// delay between t_internal and out
-	wr0_out_delay,  // delay between rd_internal and out
-	last_t_time,    // time when the last t pulse appeared
-	last_wr0_time,  // time when the last wr0 pulse appeared
-	in_hs,    // number of t pulses in hold/setup zone
-	in_sep,	 // number of pulses within an interval t_sep before 
-		 //  the last data pulse
-	out_value, // value at the output
-	vt_hold,	// variable hold
-	vt_setup,	// variable setup
-	vdelay;    // variable delay
-
-`include "INIT"
-
-`ifdef RANDOM_DELAYS
- `include "RANDOM_GATE"
-`endif
-
-initial 
-	begin
-		vt_hold = t_hold;
-		vt_setup = t_setup;
-		vdelay = delay;
-
-`ifdef RANDOM_DELAYS
-		delay_dev = addacc1_t1ff_variation*delay;
-		vdelay = $dist_normal(addacc1_t1ff_seed, delay, delay_dev);
-		vt_hold = $dist_normal(addacc1_t1ff_seed, t_hold, 
-                                           addacc1_t1ff_hs_dev);
-		vt_setup = t_setup + (t_hold - vt_hold);
-`endif
-
-		#1 $fdisplay(delay_file, "module=%m, nom_delay=%0d, delay=%0d", delay, vdelay);
-		#1 $fdisplay(delay_file, "module=%m, nom_hold=%0d, hold=%0d", t_hold, vt_hold);
-		#1 $fdisplay(delay_file, "module=%m, nom_setup=%0d, setup=%0d", t_setup, vt_setup);
-
-
-// define delays between inputs & outputs and the corresponding
-//  internal auxiliary registers
-	  	if(vt_hold<0)
-		  begin
-	    	  	data_delay = -vt_hold;
-	    		wr0_delay  = 0;
-		  end
-	  	else
-		  begin
-	   	  	data_delay = 0;
-	    		wr0_delay  = vt_hold;
-		  end
-		t_out_delay  = vdelay-data_delay;
-		wr0_out_delay = rd1_delay-wr0_delay;
-
-// clear internal registers and the output signal
-		t_internal = 0;
-		wr0_internal = 0;
-		t_state = 0;
-		in_hs = 0;
-		in_sep = 0;
-		sep_clr = 0;
-		hs_clr = 0;
-		out = 0;
-		rd1 = 0;
-	end
-
-
-always @(posedge t) 	// Execute at positive edge of t
-	  t_internal <= #(data_delay) t;
-
-always @(posedge wr0) 	// Execute at positive edge of t
-	  wr0_internal <= #(wr0_delay) wr0;
-
-
-always @(posedge t_internal)
-	begin
-	  if (in_sep>0)
-	    begin
-	      t_state = 1'bx;
-
-	    // generating a warning
-	      $fwrite(warning_file, 
-	       "Violation of separation time in module %m.\n");
-	      $fwrite(warning_file,
-	       "Input T pulses at %0d and at %0d.\n", last_t_time, 
-	       $stime-data_delay);
-            end
-	  last_t_time <= $stime-data_delay;
-
-	  out <= #t_out_delay t_state;
-	  out <= #(t_out_delay+2) 0;
-
-	  t_state = t_state ^ 1;
-	  if (t_internal === 1)
-	    begin
-	      in_sep = in_sep + 1;
-	      sep_clr <= #(t_separation) 1;
-	    end
-	  else
-	    t_state = 1'bx;
-
-// setting the state of the t input
-	  if (t_internal === 1)
-	    begin
-	      in_hs = in_hs+1;
-	      hs_clr <= #(vt_hold+vt_setup) 1;
-	    end
-	  else
-	    t_state = 1'bx;
-
-	  t_internal <= 0;
-	end
-
-
-always @(posedge hs_clr)
-	begin
-		if ($stime - last_wr0_time < vt_hold+vt_setup)
-		  begin
-			t_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input T pulse at %0d,",
-			 $stime-data_delay-vt_hold-vt_setup);
-			$fwrite(warning_file,
-			"\tInput WRITE0 pulse at %0d.\n",
-			 last_wr0_time-wr0_delay);
-		  end
-
-		in_hs = in_hs-1;
-		hs_clr <= 0;
-	end
-
-always @(posedge sep_clr)
-	begin
-	  	in_sep = in_sep - 1;
-		sep_clr <= 0;
-	end
-
-
-always @(posedge wr0_internal)	
-	begin
-// computing the output
-		if ((wr0_internal === 1'bx) || (in_hs>0))
-		  out_value = 1'bx;
-		else
-		  out_value = t_state;
-
-// transfering the result to the output
-		rd1 <= #(wr0_out_delay) out_value;
-		rd1 <= #(wr0_out_delay+2) 0;
-
-// clearing the internal state of T1 flip-flop
-		if(in_hs == 0)
-		  t_state  = 0;
-		else
-		  t_state = 1'bx;
-
-		wr0_internal <= 0;
-		last_wr0_time = $stime;
-	end
-
-
-endmodule

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/addacc_conf.v Deleted

@@ -1,116 +0,0 @@
-// Verilog HDL for "RSFQ.lib", "conf_buff" "_functional"
-
-// Module CONFLUENCE BUFFER
-module addacc_conf (in1, in2, out);
-
-input
-	in1, in2;
-
-output
-	out;
-reg 
-	out;
-
-parameter
-	t_separation = 10,
-	delay=20,
-
-// multichannel description of a warning file
-	warning_file=2,  
-// multichannel description of a delay file
-	delay_file = warning_file<<1;
-
-reg
-	sep_clr; // signal marking the end of the min separation zone
-		 //  for the last pulse
-
-integer
-	last_in_time,    // time when the last t pulse appeared
-	in_sep,	 // number of pulses within an interval t_sep before 
-		 //  the last data pulse;
-	vdelay;		 // variable delay
-
-
-`include "INIT"
-
-`ifdef RANDOM_DELAYS
- `include "RANDOM_GATE"
-`endif
-
-
-initial 
-	begin
-		vdelay = delay;
-
-`ifdef RANDOM_DELAYS
-		delay_dev = addacc_conf_variation*delay;
-		vdelay = $dist_normal(addacc_conf_seed, delay, delay_dev);
-`endif
-
-		#1 $fdisplay(delay_file, "module=%m, nom_delay=%0d, delay=%0d", delay, vdelay);
-
-// clear internal registers and the output signal
-		last_in_time = 0;
-		in_sep = 0;
-		sep_clr = 0;
-		out = 0;
-	end
-
-always @(posedge in1)
-	begin
-		out <= #vdelay ((in_sep > 0) || (in2 == 1)) ? 1'bx : 1;
-		out <= #(vdelay+2) 0;
-		
-		if((in_sep>0) || (in2 == 1))
-	          begin
-	        // generating a warning
-	            $fwrite(warning_file, 
-	            "Violation of separation time in module %m.\n");
-	            $fwrite(warning_file,
-	            "Input pulses at ");
-		    if(in_sep>0)
-			$fwrite(warning_file,
-			"%0d and at %0d.\n", last_in_time, $stime);
-		    else
-			$fwrite(warning_file,
-			"%0d and at %0d.\n", $stime, $stime);
-	    	  end
-	  	last_in_time <= $stime;
-
-		in_sep <= in_sep + 1;
-		sep_clr <= #(t_separation-1) 1;
-	end
-
-always @(posedge in2)
-	begin
-		out <= #vdelay ((in_sep > 0) || (in1 == 1)) ? 1'bx : 1;
-		out <= #(vdelay+2) 0;
-
-		if((in_sep>0) || (in1 == 1))
-	          begin
-	        // generating a warning
-	            $fwrite(warning_file, 
-	            "Violation of separation time in module %m.\n");
-	            $fwrite(warning_file,
-	            "Input pulses at ");
-		    if(in_sep>0)
-			$fwrite(warning_file,
-			"%0d and at %0d.\n", last_in_time, $stime);
-		    else
-			$fwrite(warning_file,
-			"%0d and at %0d.\n", $stime, $stime);
-	    	  end
-	  	last_in_time <= $stime;
-
-		in_sep <= in_sep + 1;
-		sep_clr <= #(t_separation-1) 1;
-	end
-
-always @(posedge sep_clr)
-	begin
-	  	in_sep <= in_sep - 1;
-		sep_clr <= 0;
-	end
-
-
-endmodule

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/addacc_dro.v Deleted

@@ -1,150 +0,0 @@
-// Verilog HDL for "RSFQ.lib", "dro_cell" "_functional"
-
-// Module DRO cell
-module addacc_dro (d, clk, out);
-
-input
-	d, clk;
-
-output
-	out;
-reg 
-	out;
-
-parameter
-	t_hold	= -3,
-	t_setup	= 8,
-	delay	= 13,
-
-// multichannel description of a warning file
-	warning_file=2,  
-// multichannel description of a delay file
-	delay_file = warning_file<<1;
-
-reg
-	d_internal, clk_internal,
-	d_state,          	   // internal state at the input d
-	d_set;		   	   // signal determining the moment when
-				   // the state of the d input changes to "1"
-
-integer
-	data_delay,  // delay between d and d_internal
-	clk_delay,   // delay between clk and clk_internal
-	out_delay,   // delay between clk_internal and out
-	out_value,   // output value in a given clock cycle
-	last_clk_time,	// time when the last clock pulse appeared
-	vt_hold,	// variable hold
-	vt_setup,	// variable setup
-	vdelay;		// variable delay
-
-`include "INIT"
-
-`ifdef RANDOM_DELAYS
- `include "RANDOM_GATE"
-`endif
-
-
-initial 
-	begin
-		vt_hold = t_hold;
-		vt_setup = t_setup;
-		vdelay = delay;
-
-`ifdef RANDOM_DELAYS
-		delay_dev = addacc_dro_variation*delay;
-		vdelay = $dist_normal(addacc_dro_seed, delay, delay_dev);
-		vt_hold = $dist_normal(addacc_dro_seed, t_hold,
-                                       addacc_dro_hs_dev);
-		vt_setup = t_setup + (t_hold - vt_hold);
-`endif
-
-		#1 $fdisplay(delay_file, "module=%m, nom_delay=%0d, delay=%0d", delay, vdelay);
-		#1 $fdisplay(delay_file, "module=%m, nom_hold=%0d, hold=%0d", t_hold, vt_hold);
-		#1 $fdisplay(delay_file, "module=%m, nom_setup=%0d, setup=%0d", t_setup, vt_setup);
-
-
-// define delays between inputs & outputs and the corresponding
-//  internal auxiliary registers
-	  	if(vt_hold<0)
-		  begin
-	    	  	data_delay = -vt_hold;
-	    		clk_delay  = 0;
-			out_delay  = vdelay;
-		  end
-	  	else
-		  begin
-	   	  	data_delay = 0;
-	    		clk_delay  = vt_hold;
-		  	out_delay  = vdelay-vt_hold;
-		  end
-
-// clear internal registers and the output signal
-		d_internal = 0;
-		clk_internal = 0;
-		last_clk_time = 0;
-		d_state = 0;
-		d_set = 0;
-		out = 0;
-	end
-
-
-
-always @(posedge d) 	// Execute at positive edge of d
-	  d_internal <= #(data_delay) d;
-
-always @(posedge clk)  // Execute at positive edge of clk
-	  clk_internal <= #(clk_delay) clk;
-
-
-always @(posedge d_internal)
-	begin
-// setting the state of the d input
-                d_state <= d_state | 1'bx;
-		if (d_internal === 1)
-		  d_set <= #(vt_hold+vt_setup) 1;
-
-		d_internal <= 0;
-	end
-
-always @(posedge d_set)
-	begin
-		if ($stime - last_clk_time >= vt_hold+vt_setup)
-			d_state = 1;
-		else
-		  begin
-			d_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input D pulse at %0d,",
-			 $stime-data_delay-vt_hold-vt_setup);
-			$fwrite(warning_file,
-			"\tClock pulse at %0d.\n", last_clk_time-clk_delay);
-		  end
-
-		d_set <= 0;
-	end
-
-
-always @(posedge clk_internal)	
-	begin
-// computing the output
-		if (clk_internal === 1'bx)
-		  out_value = 1'bx;
-		else
-		  out_value = d_state;
-
-// transfering the result to the output
-		out <= #(out_delay) out_value;
-		out <= #(out_delay+2) 0;
-
-// clearing the internal state of the DRO
-		d_state  <= 0;
-
-		clk_internal <= 0;
-		last_clk_time = $stime;
-	end
-
-endmodule

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/addacc_t1ff.v Deleted

@@ -1,200 +0,0 @@
-// Verilog HDL for "RSFQ.lib", "t1ff" "_functional"
-
-// Module T1 flip-flop
-module addacc_t1ff (t, wr0, out, rd1);
-
-input
-	t, wr0;
-
-output
-	out, rd1;
-reg 
-	out, rd1;
-
-parameter
-	t_separation 	=  8,
-	delay		= 20,
-	t_hold 		=  6,
-	t_setup 	= 15,
-	rd1_delay	= 17,
-
-// multichannel description of a warning file
-	warning_file=2,  
-// multichannel description of a delay file
-	delay_file = warning_file<<1;
-
-reg
-	t_internal, wr0_internal, // signals at inputs after i/o stage
-	t_state,  // internal state of T flip-flop
-	sep_clr,  // signal marking the end of the separation zone
-	hs_clr;	  // signal marking the end of the hold/setup zone
-
-
-integer
-	data_delay, 	// delay between t and t_internal
-	wr0_delay, 	// delay between rd and rd_internal
-	t_out_delay, 	// delay between t_internal and out
-	wr0_out_delay,  // delay between rd_internal and out
-	last_t_time,    // time when the last t pulse appeared
-	last_wr0_time,  // time when the last wr0 pulse appeared
-	in_hs,    // number of t pulses in hold/setup zone
-	in_sep,	 // number of pulses within an interval t_sep before 
-		 //  the last data pulse;
-	out_value, // value at the output
-	vt_hold,	// variable hold
-	vt_setup,	// variable setup
-	vdelay;		// variable delay
-
-`include "INIT"
-
-`ifdef RANDOM_DELAYS
- `include "RANDOM_GATE"
-`endif
-
-
-initial 
-	begin
-		vt_hold = t_hold;
-		vt_setup = t_setup;
-		vdelay = delay;
-
-`ifdef RANDOM_DELAYS
-		delay_dev = addacc_t1ff_variation*delay;
-		vdelay = $dist_normal(addacc_t1ff_seed, delay, delay_dev);
-		vt_hold = $dist_normal(addacc_t1ff_seed, t_hold,
-                                       addacc_t1ff_hs_dev);
-		vt_setup = t_setup + (t_hold - vt_hold);
-`endif
-
-		#1 $fdisplay(delay_file, "module=%m, nom_delay=%0d, delay=%0d", delay, vdelay);
-		#1 $fdisplay(delay_file, "module=%m, nom_hold=%0d, hold=%0d", t_hold, vt_hold);
-		#1 $fdisplay(delay_file, "module=%m, nom_setup=%0d, setup=%0d", t_setup, vt_setup);
-
-
-// define delays between inputs & outputs and the corresponding
-//  internal auxiliary registers
-	  	if(vt_hold<0)
-		  begin
-	    	  	data_delay = -vt_hold;
-	    		wr0_delay  = 0;
-		  end
-	  	else
-		  begin
-	   	  	data_delay = 0;
-	    		wr0_delay  = vt_hold;
-		  end
-		t_out_delay  = vdelay-data_delay;
-		wr0_out_delay = rd1_delay-wr0_delay;
-
-// clear internal registers and the output signal
-		t_internal = 0;
-		wr0_internal = 0;
-		t_state = 0;
-		in_hs = 0;
-		in_sep = 0;
-		sep_clr = 0;
-		hs_clr = 0;
-		out = 0;
-		rd1 = 0;
-	end
-
-
-always @(posedge t) 	// Execute at positive edge of t
-	  t_internal <= #(data_delay) t;
-
-always @(posedge wr0) 	// Execute at positive edge of t
-	  wr0_internal <= #(wr0_delay) wr0;
-
-
-always @(posedge t_internal)
-	begin
-	  if (in_sep>0)
-	    begin
-	      t_state = 1'bx;
-
-	    // generating a warning
-	      $fwrite(warning_file, 
-	       "Violation of separation time in module %m.\n");
-	      $fwrite(warning_file,
-	       "Input T pulses at %0d and at %0d.\n", last_t_time, 
-	       $stime-data_delay);
-	    end
-	  last_t_time <= $stime-data_delay;
-
-	  out <= #t_out_delay t_state;
-	  out <= #(t_out_delay+2) 0;
-
-	  t_state = t_state ^ 1;
-	  if (t_internal === 1)
-	    begin
-	      in_sep = in_sep + 1;
-	      sep_clr <= #(t_separation) 1;
-	    end
-	  else
-	    t_state = 1'bx;
-
-// setting the state of the t input
-	  if (t_internal === 1)
-	    begin
-	      in_hs = in_hs+1;
-	      hs_clr <= #(vt_hold+vt_setup) 1;
-	    end
-	  else
-	    t_state = 1'bx;
-
-	  t_internal <= 0;
-	end
-
-
-always @(posedge hs_clr)
-	begin
-		if ($stime - last_wr0_time < vt_hold+vt_setup)
-		  begin
-			t_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input T pulse at %0d,",
-			 $stime-data_delay-vt_hold-vt_setup);
-			$fwrite(warning_file,
-			"\tInput WRITE0 pulse at %0d.\n",
-			 last_wr0_time-wr0_delay);
-		  end
-
-		in_hs = in_hs-1;
-		hs_clr <= 0;
-	end
-
-always @(posedge sep_clr)
-	begin
-	  	in_sep = in_sep - 1;
-		sep_clr <= 0;
-	end
-
-
-always @(posedge wr0_internal)	
-	begin
-// computing the output
-		if ((wr0_internal === 1'bx) || (in_hs>0))
-		  out_value = 1'bx;
-		else
-		  out_value = t_state;
-
-// transfering the result to the output
-		rd1 <= #(wr0_out_delay) out_value;
-		rd1 <= #(wr0_out_delay+2) 0;
-
-// clearing the internal state of T1 flip-flop
-		if(in_hs == 0)
-		  t_state  = 0;
-		else
-		  t_state = 1'bx;
-
-		wr0_internal <= 0;
-		last_wr0_time = $stime;
-	end
-
-
-endmodule

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/allParseOutput.zip Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/and.v Deleted

@@ -1,153 +0,0 @@
-// Verilog HDL for "gates.lib", "and_gate" "_functional"
-// Module AND gate
-module and_gate (a, b, clk, out);
-
-input
-	a, b, clk;
-
-output
-	out;
-reg 
-	out;
-
-parameter
-	t_hold	= 12,
-	t_setup	=  1,
-	delay	= 25,
-
-	warning_file=3;  // multichannel description of a warning file
-
-reg
-	a_internal, b_internal, clk_internal,
-	a_state, b_state,          // internal state at inputs a and b
-	a_set, b_set;		   // signals determining the moment when
-				   // the state of the a,b inputs changes to "1"
-integer
-	data_delay, 	// delay between a (b) and a_internal (b_internal)
-	clk_delay, 	// delay between clk and clk_internal
-	out_delay, 	// delay between clk_internal and out
-	out_value,	// output value in a given clock cycle
-	last_clk_time;	// time when the last clock pulse appeared
-
-initial 
-	begin
-// define delays between inputs & outputs and the corresponding
-//  internal auxiliary registers
-	  	if(t_hold<0)
-		  begin
-	    		data_delay = -t_hold;
-	    	  	clk_delay = 0;
-		  	out_delay = delay;
-		  end
-	  	else
-		  begin
-	    	  	data_delay = 0;
-	    	  	clk_delay = t_hold;
-		  	out_delay=delay-t_hold;
-		  end
-
-// clear internal registers and the output signal
-		a_internal = 0;
-		b_internal = 0;
-		clk_internal = 0;
-		last_clk_time = 0;
-		a_state = 0;
-		b_state = 0;
-		a_set = 0;
-		b_set = 0;
-		out = 0;
-	end
-
-always @(posedge a) 	// Execute at positive edge of a
-	  a_internal <= #(data_delay) a;
-
-always @(posedge b) 	// Execute at positive edge of b
-	  b_internal <= #(data_delay) b;
-
-always @(posedge clk) 	// Execute at positive edge of clk
-	  clk_internal <= #(clk_delay) clk;
-
-always @(posedge a_internal)
-	begin
-// setting an internal state at the input a
-                a_state <= a_state | 1'bx;
-		if (a_internal === 1)
-		  a_set <= #(t_hold+t_setup) 1;
-
-		a_internal <= 0;
-	end
-
-always @(posedge b_internal)
-	begin
-// setting an internal state at the input a
-                b_state <= b_state | 1'bx;
-		if (b_internal === 1)
-		  b_set <= #(t_hold+t_setup) 1;
-
-		b_internal <= 0;
-	end
-
-always @(posedge a_set)
-	begin
-		if ($stime - last_clk_time >= t_hold+t_setup)
-			a_state = 1;
-		else
-		  begin
-			a_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input A pulse at %0d,",
-			 $stime-data_delay-t_hold-t_setup);
-			$fwrite(warning_file,
-			"\tClock pulse at %0d.\n", last_clk_time-clk_delay);
-		  end
-
-		a_set <= 0;
-	end
-
-always @(posedge b_set)
-	begin
-		if ($stime - last_clk_time >= t_hold+t_setup)
-			b_state = 1;
-		else
-		  begin
-			b_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input B pulse at %0d,",
-			 $stime-data_delay-t_hold-t_setup);
-			$fwrite(warning_file,
-			"\tClock pulse at %0d.\n", last_clk_time-clk_delay);
-		  end
-
-		b_set <= 0;
-	end
-
-
-always @(posedge clk_internal)	
-	begin
-// computing the output
-		if (clk_internal === 1'bx)
-		  out_value = 1'bx;
-		else
-		  out_value = a_state & b_state;
-
-// transfering the result to the output
-		out <= #(out_delay) out_value;
-		out <= #(out_delay+2) 0;
-
-// clearing the internal state of A and B inputs
-		a_state  <= 0;
-		b_state  <= 0;
-
-		clk_internal <= 0;
-		last_clk_time = $stime;
-	end
-
-endmodule

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/and_gate.v Deleted

@@ -1,185 +0,0 @@
-// Verilog HDL for "RSFQ.lib", "and_gate" "_functional"
-
-// Module AND gate
-module and_gate (a, b, clk, out);
-
-input
-	a, b, clk;
-
-output
-	out;
-reg 
-	out;
-
-parameter
-	t_hold	= 12,
-	t_setup	=  1,
-	delay	= 25,
-
-// multichannel description of a warning file
-	warning_file=2,  
-// multichannel description of a delay file
-	delay_file = warning_file<<1;
-
-reg
-	a_internal, b_internal, clk_internal,
-	a_state, b_state,          // internal state at inputs a and b
-	a_set, b_set;		   // signals determining the moment when
-				   // the state of the a,b inputs changes to "1"
-integer
-	data_delay, 	// delay between a (b) and a_internal (b_internal)
-	clk_delay, 	// delay between clk and clk_internal
-	out_delay, 	// delay between clk_internal and out
-	out_value,	// output value in a given clock cycle
-	last_clk_time,	// time when the last clock pulse appeared
-	vt_hold,	// variable hold
-	vt_setup,	// variable setup
-	vdelay;		// variable delay
-
-
-`include "INIT"
-
-`ifdef RANDOM_DELAYS
- `include "RANDOM_GATE"
-`endif
-
-
-initial 
-	begin
-		vt_hold = t_hold;
-		vt_setup = t_setup;
-		vdelay = delay;
-
-`ifdef RANDOM_DELAYS
-		delay_dev = and_gate_variation*delay;
-		vdelay = $dist_normal(and_gate_seed, delay, delay_dev);
-		vt_hold = $dist_normal(and_gate_seed, t_hold, and_hs_dev);
-		vt_setup = t_setup + (t_hold - vt_hold);
-`endif
-
-		#0 $fdisplay(delay_file, "module=%m, nom_delay=%0d, delay=%0d", delay, vdelay);
-		#0 $fdisplay(delay_file, "module=%m, nom_hold=%0d, hold=%0d", t_hold, vt_hold);
-		#0 $fdisplay(delay_file, "module=%m, nom_setup=%0d, setup=%0d", t_setup, vt_setup);
-
-
-// define delays between inputs & outputs and the corresponding
-//  internal auxiliary registers
-	  	if(vt_hold<0)
-		  begin
-	    		data_delay = -vt_hold;
-	    	  	clk_delay = 0;
-		  	out_delay = vdelay;
-		  end
-	  	else
-		  begin
-	    	  	data_delay = 0;
-	    	  	clk_delay = vt_hold;
-		  	out_delay=vdelay-vt_hold;
-		  end
-
-// clear internal registers and the output signal
-		a_internal = 0;
-		b_internal = 0;
-		clk_internal = 0;
-		last_clk_time = 0;
-		a_state = 0;
-		b_state = 0;
-		a_set = 0;
-		b_set = 0;
-		out = 0;
-	end
-
-always @(posedge a) 	// Execute at positive edge of a
-	  a_internal <= #(data_delay) a;
-
-always @(posedge b) 	// Execute at positive edge of b
-	  b_internal <= #(data_delay) b;
-
-always @(posedge clk) 	// Execute at positive edge of clk
-	  clk_internal <= #(clk_delay) clk;
-
-always @(posedge a_internal)
-	begin
-// setting an internal state at the input a
-                a_state <= a_state | 1'bx;
-		if (a_internal === 1)
-		  a_set <= #(vt_hold+vt_setup) 1;
-
-		a_internal <= 0;
-	end
-
-always @(posedge b_internal)
-	begin
-// setting an internal state at the input a
-                b_state <= b_state | 1'bx;
-		if (b_internal === 1)
-		  b_set <= #(vt_hold+vt_setup) 1;
-
-		b_internal <= 0;
-	end
-
-always @(posedge a_set)
-	begin
-		if ($stime - last_clk_time >= vt_hold+vt_setup)
-			a_state = 1;
-		else
-		  begin
-			a_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input A pulse at %0d,",
-			 $stime-data_delay-vt_hold-vt_setup);
-			$fwrite(warning_file,
-			"\tClock pulse at %0d.\n", last_clk_time-clk_delay);
-		  end
-
-		a_set <= 0;
-	end
-
-always @(posedge b_set)
-	begin
-		if ($stime - last_clk_time >= vt_hold+vt_setup)
-			b_state = 1;
-		else
-		  begin
-			b_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input B pulse at %0d,",
-			 $stime-data_delay-vt_hold-vt_setup);
-			$fwrite(warning_file,
-			"\tClock pulse at %0d.\n", last_clk_time-clk_delay);
-		  end
-
-		b_set <= 0;
-	end
-
-
-always @(posedge clk_internal)	
-	begin
-// computing the output
-		if (clk_internal === 1'bx)
-		  out_value = 1'bx;
-		else
-		  out_value = a_state & b_state;
-
-// transfering the result to the output
-		out <= #(out_delay) out_value;
-		out <= #(out_delay+2) 0;
-
-// clearing the internal state of A and B inputs
-		a_state  <= 0;
-		b_state  <= 0;
-
-		clk_internal <= 0;
-		last_clk_time = $stime;
-
-	end
-
-endmodule

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/conf.v Deleted

@@ -1,94 +0,0 @@
-// Verilog HDL for "gates.lib", "conf_buff" "_functional"
-// Module CONFLUENCE BUFFER
-module conf_buff (in1, in2, out);
-
-input
-	in1, in2;
-
-output
-	out;
-reg 
-	out;
-
-parameter
-	t_separation = 10,
-	delay=15,
-
-	warning_file=3;  // multichannel description of a warning file
-
-reg
-	sep_clr; // signal marking the end of the min separation zone
-		 //  for the last pulse
-
-integer
-	last_in_time,    // time when the last t pulse appeared
-	in_sep;	 // number of pulses within an interval t_sep before 
-		 //  the last data pulse;
-
-initial 
-	begin
-// clear internal registers and the output signal
-		last_in_time = 0;
-		in_sep = 0;
-		sep_clr = 0;
-		out = 0;
-	end
-
-always @(posedge in1)
-	begin
-		out <= #delay ((in_sep > 0) || (in2 == 1)) ? 1'bx : 1;
-		out <= #(delay+2) 0;
-		
-		if((in_sep>0) || (in2 == 1))
-	          begin
-	        // generating a warning
-	            $fwrite(warning_file, 
-	            "Violation of separation time in module %m.\n");
-	            $fwrite(warning_file,
-	            "Input pulses at ");
-		    if(in_sep>0)
-			$fwrite(warning_file,
-			"%0d and at %0d.\n", last_in_time, $stime);
-		    else
-			$fwrite(warning_file,
-			"%0d and at %0d.\n", $stime, $stime);
-	    	  end
-	  	last_in_time <= $stime;
-
-		in_sep <= in_sep + 1;
-		sep_clr <= #(t_separation-1) 1;
-	end
-
-always @(posedge in2)
-	begin
-		out <= #delay ((in_sep > 0) || (in1 == 1)) ? 1'bx : 1;
-		out <= #(delay+2) 0;
-
-		if((in_sep>0) || (in1 == 1))
-	          begin
-	        // generating a warning
-	            $fwrite(warning_file, 
-	            "Violation of separation time in module %m.\n");
-	            $fwrite(warning_file,
-	            "Input pulses at ");
-		    if(in_sep>0)
-			$fwrite(warning_file,
-			"%0d and at %0d.\n", last_in_time, $stime);
-		    else
-			$fwrite(warning_file,
-			"%0d and at %0d.\n", $stime, $stime);
-	    	  end
-	  	last_in_time <= $stime;
-
-		in_sep <= in_sep + 1;
-		sep_clr <= #(t_separation-1) 1;
-	end
-
-always @(posedge sep_clr)
-	begin
-	  	in_sep <= in_sep - 1;
-		sep_clr <= 0;
-	end
-
-
-endmodule

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/core_test.v Deleted

@@ -1,94 +0,0 @@
-`timescale 100ps/10ps
-/* Core Tester */
-// Author Andrew Laffely
-// Last modified: 12 Feb 03
-
-module core_test;
-
-reg gclock, reset, hold;
-wire 2:0 in_ready, out_ready;
-wire 31:0 data_in, data_out;
-reg 31:0  temp, temp2;
-reg 32:0 data_to_core;
-wire 32:0 data_from_core; 
-wire read, write;   
-wire 1:0 in_addr, out_addr;
-reg 1:0 to_addr, from_addr;
-reg valid_next;
-wire valid_back;
-reg start, start2;
-integer count, fp, fpin;
-
-/************************** INTERCONNECT ****************************/
-in_port IN_PORT_TILE1(gclock, reset, to_addr, data_to_core, in_addr, 
-			read, data_in, valid_back, in_ready);
-out_port OUT_PORT_TILE1(gclock, reset, from_addr, data_out, out_addr, 
-			write, valid_next, data_from_core, out_ready);
-/************************** END INTERCONNECT *************************/
-
-/***********************************CORE*****************************/
-adder_core CORE_TILE1(reset, hold, in_ready, out_ready, data_in, data_out, 
-			read, write, in_addr, out_addr);
-/*********************************END CORE***************************/
-
-/********************* TEST BENCH ******************************/
-initial
-begin
-	gclock = 1'b0;
-	forever #10 gclock = ~gclock;
-end
-initial
-begin
-	count=0;
-	start=0; start2=0;
-	fp=$fopen("results.dat");  //open a file pointer	
-	fpin=$fopen("inputs.dat");  //open a file pointer
-	reset = 1'b1;
-	hold = 1'b0;
-	data_to_core32=0;
-	temp=32'h00000000;
-	temp2=32'h00000000;
-	data_to_core31:0=32'h00000000;
-	valid_next=0;
-	to_addr=2'b00;
-	from_addr=2'b00;
-	#2 reset = 1'b0;
-	#26 start=1;
-	#4000 $fclose(fp);
-	$fclose(fpin);
-	$finish;
-end
-
-always @ (posedge gclock)
-  begin
-	count=count+1;
-	//Inputs
-	to_addr0 = ~to_addr0;
-	if((!valid_back)&&(start))
-	  begin
-		#1 if (!to_addr0)
-		  begin
-			data_to_core={1'b1,temp};
-			temp=temp+1;
-			$fdisplay(fpin, "Cycle=%d: InputA=%h",count,data_to_core);
-			start2=1;	
-		  end
-		else 
-		  begin
-		    if (start2)
-		      begin
-			data_to_core={1'b1,temp2};
-			temp2=temp2+256;
-			$fdisplay(fpin, "Cycle=%d: InputB=%h",count,data_to_core);	
-		      end
-		  end
-	  end
-	//Output
-	if (from_addr==2'b00)
-		from_addr=2'b11;
-	else
-		from_addr=2'b00;
-	if (data_from_core32)
-		$fdisplay(fp, "Cycle = %d: Output = %h",count,data_from_core);
-  end
-endmodule

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/count2bit.v Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/count_all_prims_test.v Deleted

@@ -1,49 +0,0 @@
-/**********************************************************************
- * $count_primitives example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $count_primitives PLI application 
- * on a 1-bit adder modeled using gate primitives.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-  reg  a, b, ci, clk;
-  wire sum, co, sum2;
-
-  addbit i1 (a, b, ci, sum, co);
-  buf (sum2, sum);
-
-  initial
-    begin
-      #1 $count_primitives;
-      #1 $finish;
-    end
-endmodule
-
-/*** A gate level 1 bit adder model ***/
-`timescale 1ns / 1ns
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci, sum, co,
-        n1, n2, n3;
-
-  xor    (n1, a, b);
-  xor #2 (sum, n1, ci);
-  and    (n2, a, b);
-  and    (n3, n1, ci);
-  or  #2 (co, n2, n3);
-  
-  specify
-    (a *> sum) = 5;
-    (b *> sum, co) = 5;
-  endspecify
-
-endmodule
-/*********************************************************************/

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/count_loads_test.v Deleted

@@ -1,148 +0,0 @@
-/**********************************************************************
- * $count_loads example -- Verilog test bench source code
- *
- * Verilog test bench to test the $count_loads PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-
-/**********************************************************************
- * Top-level test bench module for a 4-bit adder model.
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-  reg    3:0 a, b;
-  wire   3:0 sum;
-  reg          ci;
-  wire         co;
-
-  add4 i1 (a, b, ci, sum, co);
-
-  initial
-    begin
-      $display("loads on i1.a1.sum = %d\n", $count_loads(i1.a1.sum));
-      $display("loads on i1.a2.r1 = %d\n", $count_loads(i1.a2.r1));
-      #1 $finish;
-    end
-endmodule
-
-/**********************************************************************
- * 4-bit adder model, using a 1-bit adder model.
- *********************************************************************/
-`timescale 1ns / 1ns
-module add4 (a, b, ci, sum, co);
-  input  3:0 a, b;
-  input        ci;
-  output 3:0 sum;
-  output       co;
-
-  wire   3:0 a, b, sum;
-  wire         ci, co, co1, co2, co3;
-  wire         n1, n2, n3, n4, n5, n6, n7, n8, n9;
-
-  addbit  a1  (a0, b0, ci,  sum0, co1, n1);
-  addbit  a2  (a1, b1, co1, sum1, co2, n2);
-  addbit  a3  (a2, b2, co2, sum2, co3, n3);
-  addbit  a4  (a3, b3, co3, sum3, co , n4);
-
-  and2    a5  (n5, sum0, sum1);
-  xor2    a6  (n6, sum0, co);
-  or2     a7  (n7, n1, n2);
-  or2     a8  (n8, n3, n4);
-  and2    a9  (n9, n7, n8);
-endmodule
-
-/**********************************************************************
- * 1-bit adder model, using cells from a library.
- *********************************************************************/
-`timescale 1ns / 1ns
-module addbit (a, b, ci, sum, co, r1);
-  input  a, b, ci;
-  output sum, co;
-  output r1;
-  
-  wire  a, b, ci, sum, co, n1, n2, n3;
-  reg   r1;
-
-  xor2  u1  (n1, a, b);
-  xor2  u2  (sum, n1, ci);
-  and2  u3  (n2, a, b);
-  and2  u4  (n3, n1, ci);
-  or2   u5  (co, n2, n3);
-
-endmodule
-/**********************************************************************
-* Cell library
- *********************************************************************/
-`resetall
-`celldefine
-`timescale 1ns / 10ps
-module or2 (y, a, b);
-  output y;
-  input  a, b;
-  wire   y, a, b;  //wire data type for cmos
-  or    (y, a, b);
-  specify
-    (a *> y) = 1.0;
-    (b *> y) = 1.0;
-    specparam BaseDelay$   = 2.5;
-    specparam InputLoad$a  = 0.3;
-    specparam InputLoad$b  = 0.3;
-    specparam InputLoad$c  = 0.3;
-    specparam in_cap_pf$a  = 0.02;
-    specparam in_cap_pf$b  = 0.02;
-    specparam in_cap_pf$c  = 0.02;
-    specparam out_cap_pf$  = 0.05;
-  endspecify
-endmodule
-`endcelldefine
-/*********************************************************************/
-`resetall
-`celldefine
-`timescale 1ns / 10ps
-module xor2 (y, a, b);
-  output y;
-  input  a, b;
-  wire   y, a, b;  //wire data type for cmos
-  xor   (y, a, b);
-  specify
-    (a *> y) = 1.0;
-    (b *> y) = 1.0;
-    specparam BaseDelay$   = 2.5;
-    specparam InputLoad$a  = 0.3;
-    specparam InputLoad$b  = 0.3;
-    specparam InputLoad$c  = 0.3;
-    specparam in_cap_pf$a  = 0.02;
-    specparam in_cap_pf$b  = 0.02;
-    specparam in_cap_pf$c  = 0.02;
-    specparam out_cap_pf$  = 0.05;
-  endspecify
-endmodule
-`endcelldefine
-/*********************************************************************/
-`resetall
-`celldefine
-`timescale 1 ns / 10 ps
-module and2 (y, a, b);
-  output y;
-  input  a, b;
-  wire   y, a, b;  //wire data type for cmos
-  and   (y, a, b);
-  specify
-    (a *> y) = 1.0;
-    (b *> y) = 1.0;
-    specparam BaseDelay$   = 2.5;
-    specparam InputLoad$a  = 0.2;
-    specparam InputLoad$b  = 0.2;
-    specparam in_cap_pf$a  = 0.02;
-    specparam in_cap_pf$b  = 0.02;
-    specparam out_cap_pf$  = 0.05;
-  endspecify
-endmodule
-`endcelldefine
-/*********************************************************************/
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/dds.v Deleted

@@ -1,122 +0,0 @@
-//
-//
-// This is just a little demo of DDS.  It doesn't have any cool features
-// or anything..
-//
-module dds (
-   clk,
-   reset,
-   
-   din,
-   
-   dout
-);
-
-parameter	W = 12;
-
-input		clk;	// Primary clock.
-input		reset;	// Synchronous reset.
-input W-1:0	din;	// The "phase step".
-output W-1:0	dout;	// Output of the phase accumulator register.
-
-reg W-1:0	dout;
-
-reg W-1:0	accum;	// Phas Accumulator
-
-// Just output the accumulator...
-always @(accum)
-   dout <= accum;
-
-// Specify the accumulator..   
-always @(posedge clk) begin
-   if (reset) accum <= 0;
-   else begin
-      accum <= accum + din;
-   end
-end
-
-endmodule
-
-// synopsys translate_off
-module ddstest;
-
-reg		clk;
-reg		reset;
-reg 11:0	din;
-wire 11:0	dout;	
-reg 7:0	cosout;	
-
-// Instantiate the DDS with 12-bits.
-//
-dds #(12) dds1 (.clk(clk),  .reset(reset),  .din(din),  .dout(dout));
-
-// Here's our Cosine lookup table.
-//
-reg 7:0	costable0:4095;  // 4KBytes.
-
-// DDS Phase Accumulator output simply indexes into the Cos lookup table.
-//
-always @(dout)
-   cosout <= costabledout;
-
-// Main test thread.
-//   
-initial begin
-   $readmemh ("cos.hex", costable); // See the PERL program 'generate_cos_table.pl'
-
-   din = 12'h020; // Start at 16
-   #500000;
-   
-   din = 12'h0D0; // A little faster.. 
-   #500000;
-   
-   din = 12'h200; // Fairly fast.
-   #500000;
-   
-   $finish;
-end
-
-// Let's clock it at 1 MHz
-initial begin
-   clk = 0;
-   forever begin
-      #500 clk = 1;
-      #500 clk = 0;
-   end
-end
-
-// Reset
-initial begin
-   reset = 1;
-   #3500 reset = 0;
-end
-
-// Generate VCD file for viewing.
-initial begin
-   $dumpfile ("dds.vcd");
-   $dumpvars (0,ddstest);   
-end
-endmodule
-
-/*
-//***  Here's the Perl program for your reference...
-`ifdef WHEN_PERL_IS_A_SUBSET_OF_VERILOG
-      #!/tools2/perl/bin/perl
-      #
-      #  Generate a file of cos data for use by a DDS simulation.
-      #
-
-      $n      = 4096;	# Number of data points
-      $minval = 0;	# Smallest cos value.
-      $maxval = 255;	# Largest cos value.
-
-      $pi = 3.1415927;
-      $t = 0;
-      for ($i = 1; $i < $n; $i = $i + 1) {
-         $value = ($maxval - $minval)/2 + (($maxval - $minval)/2)*cos($t);
-         $value = int($value);
-         printf "%x\n", $value;
-         $t = $t + 2*$pi / $n;
-      }
-`endif
-*/
\ No newline at end of file

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/diff_udp.v Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/display_all_nets_test.v Deleted

@@ -1,55 +0,0 @@
-/**********************************************************************
- * $display_all_nets example -- Verilog test bench source code
- *
- * Verilog test bench to test the $display_all_nets PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module top;
-  reg  2:0 test;
-  reg        clock;
-  wire 1:0 results;
-
-  addbit i1 (test0, test1, test2, results0, results1);
-
-  always @(negedge clock)
-    $display_all_nets(i1);
-
-  initial
-    begin
-      clock = 1;
-      forever #5 clock = ~clock;
-    end
-
-  initial
-    begin
-      test = 3'b000;
-      @(posedge clock) test = 3'b001;
-      @(posedge clock) test = 3'b011;
-      @(posedge clock) $finish;
-    end
-endmodule
-
-/*** A gate level 1 bit adder model ***/
-`timescale 1ns / 1ns
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci, sum, co,
-        n1, n2, n3;
-
-  xor    (n1, a, b);
-  xor #2 (sum, n1, ci);
-  and    (n2, a, b);
-  and    (n3, n1, ci);
-  or  #2 (co, n2, n3);
-
-endmodule
-/*********************************************************************/
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/div16.v Deleted

@@ -1,242 +0,0 @@
-//
-// Integer Multicycle Divide circuit (divide a 16-bit number by a 16-bit number in 16 cycles).
-//
-// a / b = q with remainder r
-//
-// Where a is 16-bits,
-// Where b is 16 bits
-//
-// Module is actually parameterized if you want other widths.
-//
-// *** Test the ranges of values for which you'll use this.  For example, you
-//     can't divide FFFF by FF without underflow (overflow?).  Mess with
-//     the testbench.  You may need to widen some thing.  ***
-//
-// The answer is 16-bits and the remainder is also 16-bits.
-// After the start pulse, the module requires 16 cycles to complete.
-// The q/r outputs stay the same until next start pulse.
-// Start pulse should be a single cycle.
-// Division by zero results in a quotient equal to FFFF and remainder equal to 'a'.
-//
-// 
-// Written by tom coonan.
-//
-// Notes:
-//    - This ain't fancy.  I wanted something straight-forward quickly.  Go study
-//      more elaborate algorithms if you want to optimize area or speed.  If you
-//      have an isolated divide and can spare N cycles for N bits; this may meet your needs.
-//    - You might want to think more about the sizes of things.  I wanted a basic estimate
-//      of gates plus I specifically needed to divide 16-bits (not even full range)
-//      by 8-bits.
-//    - Handle divide by zero at higher level..
-//    - I needed a remainder so I could easily to truncate and rounding stuff,
-//      but remove this to save gates if you don't need a remainder.
-//    - This is about 800 asic gates (0.25um, Standard Cell, 27Mhz).  27Mhz
-//      is my system clock and NOT the maximum it can go..
-//    - I tried to keep everything parameterized by N, but I only worked through
-//      the N=16 case because that's what I needed...
-//
-module div16 (clk, resetb, start, a, b, q, r, done);
-
-parameter N = 16;	// a/b = q remainder r, where all operands are N wide.
-
-input		clk;
-input		resetb;	// Asynchronous, active low reset.
-input		start;	// Pulse this to start the division.
-input N-1:0	a;	// This is the number we are dividing (the dividend)
-input N-1:0	b;	// This is the 'divisor'
-output N-1:0	q;	// This is the 'quotient'
-output N-1:0	r;	// Here is the remainder.
-output		done;	// Will be asserted when q and r are available.
-
-// Registered q
-reg N-1:0	q;
-reg		done;
-
-// Power is the current 2^n bit we are considering.  Power is a shifting
-// '1' that starts at the highest power of 2 and goes all the way down
-// to ...00001  Shift this until it is zero at which point we stop.
-//
-reg N-1:0	power;
-
-// This is the accumulator.  We are start with the accumulator set to 'a' (the dividend).
-// For each (divisor*2^N) term, we see if we can subtract (divisor*2^N) from the accumulator.
-// We subtract these terms as long as adding in the term doesn't cause the accumulator
-// to exceed a.  When we are done, whatever is left in the accumulator is the remainder.
-//
-reg N-1:0	accum;
-
-// This is the divisor*2^N term.  Essentually, we are taking the divisor ('b'), initially
-// shifting it all the way to the left, and shifting it 1 bit at a time to the right.
-//
-reg (2*N-1):0	bpower;
-
-// Remainder will be whatever is left in the accumulator.
-assign r = accum;
-
-// Do this addition here for resource sharing.  
-// ** Note that 'accum' is N bits wide, but bpower is 2*N-1 bits wide **
-//
-wire 2*N-1:0 accum_minus_bpower = accum - bpower;
-
-always @(posedge clk or negedge resetb) begin
-   if (~resetb) begin
-      q <= 0;
-      accum <= 0;
-      power <= 0;
-      bpower <= 0;
-      done <= 0;
-   end
-   else begin
-      if (start) begin
-         // Reinitialize the divide circuit.
-         q      <= 0;
-         accum  <= a; // Accumulator initially gets the dividend.  
-         powerN-1 <= 1'b1; // We start with highest power of 2 (which is a '1' in MSB)
-         bpower <= b << N-1; // Start with highest bpower, which is (divisor * 2^(N-1))
-         done <= 0;
-      end
-      else begin
-         // Go until power is zero.
-         //
-         if (power != 0) begin
-            //
-            // Can we add this divisor*2^(power) to the accumulator without going negative?
-            // Just test the MSB of the subtraction.  If it is '1', then it must be negative.
-            //
-            if ( ~accum_minus_bpower2*N-1) begin
-               // Yes!  Set this power of 2 in the quotieny and
-               // then actually comitt to the subtraction from our accumulator.
-               //
-               q     <= q | power;
-               accum <= accum_minus_bpower;
-            end
-            // Regardless, always go to next lower power of 2.
-            //
-            power  <= power >> 1;
-            bpower <= bpower >> 1;
-         end
-         else begin
-            // We're done.  Set done flag.
-            done <= 1;
-         end
-      end
-   end
-end
-endmodule
-
-// synopsys translate_off
-module test_div16;
-reg		clk;
-reg		resetb;
-reg		start;
-reg 15:0	a;
-reg 15:0	b;
-wire 15:0	q;
-wire 15:0	r;
-wire		done;
-
-integer		num_errors;
-
-div16 div16 (
-   .clk(clk),
-   .resetb(resetb),
-   .start(start),
-   .a(a),
-   .b(b),
-   .q(q),
-   .r(r),
-   .done(done)
-);
-
-initial begin
-   num_errors = 0;
-   
-   start = 0;
-   
-   // Wait till reset is completely over.
-   #200;
-   
-   // Do some divisions where divisor is constrained to 8-bits and dividend is 16-bits
-   $display ("16-bit Dividend, 8-bit divisor");
-   repeat (25) begin
-      do_divide ($random, $random & 255);
-   end
-   
-   // Do some divisions where divisor is constrained to 12-bits and dividend is 16-bits
-   $display ("\n16-bit Dividend, 12-bit divisor");
-   repeat (25) begin
-      do_divide ($random, $random & 4095);
-   end
-   
-   // Do some divisions where both divisor and dividend is 16-bits
-   $display ("\n16-bit Dividend, 16-bit divisor");
-   repeat (25) begin
-      do_divide ($random, $random);
-   end
-   
-   // Special cases
-   $display ("\nSpecial Cases:");
-   do_divide (16'hFFFF,  16'hFFFF); // largest possible quotient
-   do_divide (312,  1); // divide by 1
-   do_divide (  0, 42); // divide 0 by something else
-   do_divide (312,  0); // divide by zero
-
-   // That's all.  Summarize the test.
-   if (num_errors === 0) begin
-      $display ("\n\nSUCCESS.  There were %0d Errors.", num_errors);
-   end
-   else begin
-      $display ("\n\nFAILURE!!  There were %0d Errors.", num_errors);
-   end
-   
-   $finish;
-end
-
-task do_divide;
-   input 15:0 arga;
-   input 15:0 argb;
-   
-   begin
-      a = arga;
-      b = argb;
-      @(posedge clk);
-      #1 start = 1;
-      @(posedge clk);
-      #1 start = 0;
-      while (~done) @(posedge clk);
-      #1;
-      
-      $display ("Circuit: %0d / %0d = %0d, rem = %0d \t\t......... Reality: %0d, rem = %0d", arga, argb, q, r, a/b, a%b);
-      if (b !== 0) begin
-         if (q !== a/b) begin
-            $display ("   Error!  Unexpected Quotient\n\n");
-            num_errors = num_errors + 1;
-         end
-         if (r !== a % b) begin
-            $display ("   Error!  Unexpected Remainder\n\n");
-            num_errors = num_errors + 1;
-         end
-      end
-   end
-endtask
-
-initial begin
-   clk = 0;
-   forever begin
-      #10 clk = 1;
-      #10 clk = 0;
-   end
-end
-
-initial begin
-   resetb = 0;
-   #133 resetb = 1;
-end
-
-initial begin
-   $dumpfile ("test_div16.vcd");
-   $dumpvars (0,test_div16);   
-end
-
-endmodule

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/dro.v Deleted

@@ -1,119 +0,0 @@
-// Verilog HDL for "gates.lib", "dro_cell" "_functional"
-// Module DRO cell
-module dro_cell (d, clk, out);
-
-input
-	d, clk;
-
-output
-	out;
-reg 
-	out;
-
-parameter
-	t_hold	= -3,
-	t_setup	= 8,
-	delay	= 9,
-
-	warning_file=3;  // multichannel description of a warning file
-
-reg
-	d_internal, clk_internal,
-	d_state,          	   // internal state at the input d
-	d_set;		   	   // signal determining the moment when
-				   // the state of the d input changes to "1"
-
-integer
-	data_delay,  // delay between d and d_internal
-	clk_delay,   // delay between clk and clk_internal
-	out_delay,   // delay between clk_internal and out
-	out_value,   // output value in a given clock cycle
-	last_clk_time;	// time when the last clock pulse appeared
-
-initial 
-	begin
-// define delays between inputs & outputs and the corresponding
-//  internal auxiliary registers
-	  	if(t_hold<0)
-		  begin
-	    	  	data_delay = -t_hold;
-	    		clk_delay  = 0;
-			out_delay  = delay;
-		  end
-	  	else
-		  begin
-	   	  	data_delay = 0;
-	    		clk_delay  = t_hold;
-		  	out_delay  = delay-t_hold;
-		  end
-
-// clear internal registers and the output signal
-		d_internal = 0;
-		clk_internal = 0;
-		last_clk_time = 0;
-		d_state = 0;
-		d_set = 0;
-		out = 0;
-	end
-
-
-
-always @(posedge d) 	// Execute at positive edge of d
-	  d_internal <= #(data_delay) d;
-
-always @(posedge clk)  // Execute at positive edge of clk
-	  clk_internal <= #(clk_delay) clk;
-
-
-always @(posedge d_internal)
-	begin
-// setting the state of the d input
-                d_state <= d_state | 1'bx;
-		if (d_internal === 1)
-		  d_set <= #(t_hold+t_setup) 1;
-
-		d_internal <= 0;
-	end
-
-always @(posedge d_set)
-	begin
-		if ($stime - last_clk_time >= t_hold+t_setup)
-			d_state = 1;
-		else
-		  begin
-			d_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input D pulse at %0d,",
-			 $stime-data_delay-t_hold-t_setup);
-			$fwrite(warning_file,
-			"\tClock pulse at %0d.\n", last_clk_time-clk_delay);
-		  end
-
-		d_set <= 0;
-	end
-
-
-always @(posedge clk_internal)	
-	begin
-// computing the output
-		if (clk_internal === 1'bx)
-		  out_value = 1'bx;
-		else
-		  out_value = d_state;
-
-// transfering the result to the output
-		out <= #(out_delay) out_value;
-		out <= #(out_delay+2) 0;
-
-// clearing the internal state of the DRO
-		d_state  <= 0;
-
-		clk_internal <= 0;
-		last_clk_time = $stime;
-	end
-
-endmodule

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/dro1_cell.v Deleted

@@ -1,149 +0,0 @@
-// Verilog HDL for "RSFQ.lib", "dro1_cell" "_functional"
-
-// Module DRO1 cell
-module dro1_cell (d, clk, out);
-
-input
-	d, clk;
-
-output
-	out;
-reg 
-	out;
-
-parameter
-	t_hold	= -6,
-	t_setup	= 11,
-	delay	=  6,
-
-// multichannel description of a warning file
-	warning_file=2,  
-// multichannel description of a delay file
-	delay_file = warning_file<<1;
-
-reg
-	d_internal, clk_internal,
-	d_state,          	   // internal state at the input d
-	d_set;		   	   // signal determining the moment when
-				   // the state of the d input changes to "1"
-
-integer
-	data_delay,  // delay between d and d_internal
-	clk_delay,   // delay between clk and clk_internal
-	out_delay,   // delay between clk_internal and out
-	out_value,   // output value in a given clock cycle
-	last_clk_time,	// time when the last clock pulse appeared
-	vt_hold,	// variable hold
-	vt_setup,	// variable setup
-	vdelay;		// variable delay
-
-`include "INIT"
-
-`ifdef RANDOM_DELAYS
- `include "RANDOM_GATE"
-`endif
-
-initial 
-	begin
-
-		vt_hold = t_hold;
-		vt_setup = t_setup;
-		vdelay = delay;
-
-`ifdef RANDOM_DELAYS
-		delay_dev = dro1_cell_variation*delay;
-		vdelay = $dist_normal(dro1_cell_seed, delay, delay_dev);
-		vt_hold = $dist_normal(dro1_cell_seed, t_hold, dro1_hs_dev);
-		vt_setup = t_setup + (t_hold - vt_hold);
-`endif
-
-		#1 $fdisplay(delay_file, "module=%m, nom_delay=%0d, delay=%0d", delay, vdelay);
-		#1 $fdisplay(delay_file, "module=%m, nom_hold=%0d, hold=%0d", t_hold, vt_hold);
-		#1 $fdisplay(delay_file, "module=%m, nom_setup=%0d, setup=%0d", t_setup, vt_setup);
-
-
-// define delays between inputs & outputs and the corresponding
-//  internal auxiliary registers
-	  	if(vt_hold<0)
-		  begin
-	    	  	data_delay = -vt_hold;
-	    		clk_delay  = 0;
-			out_delay  = vdelay;
-		  end
-	  	else
-		  begin
-	   	  	data_delay = 0;
-	    		clk_delay  = vt_hold;
-		  	out_delay  = vdelay-vt_hold;
-		  end
-
-// clear internal registers and the output signal
-		d_internal = 0;
-		clk_internal = 0;
-		last_clk_time = 0;
-		d_state = 0;
-		d_set = 0;
-		out = 0;
-	end
-
-
-
-always @(posedge d) 	// Execute at positive edge of d
-	  d_internal <= #(data_delay) d;
-
-always @(posedge clk)  // Execute at positive edge of clk
-	  clk_internal <= #(clk_delay) clk;
-
-
-always @(posedge d_internal)
-	begin
-// setting the state of the d input
-                d_state <= d_state | 1'bx;
-		if (d_internal === 1)
-		  d_set <= #(vt_hold+vt_setup) 1;
-
-		d_internal <= 0;
-	end
-
-always @(posedge d_set)
-	begin
-		if ($stime - last_clk_time >= vt_hold+vt_setup)
-			d_state = 1;
-		else
-		  begin
-			d_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input D pulse at %0d,",
-			 $stime-data_delay-vt_hold-vt_setup);
-			$fwrite(warning_file,
-			"\tClock pulse at %0d.\n", last_clk_time-clk_delay);
-		  end
-
-		d_set <= 0;
-	end
-
-
-always @(posedge clk_internal)	
-	begin
-// computing the output
-		if (clk_internal === 1'bx)
-		  out_value = 1'bx;
-		else
-		  out_value = d_state;
-
-// transfering the result to the output
-		out <= #(out_delay) out_value;
-		out <= #(out_delay+2) 0;
-
-// clearing the internal state of the DRO
-		d_state  <= 0;
-
-		clk_internal <= 0;
-		last_clk_time = $stime;
-	end
-
-endmodule

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/dro_cell.v Deleted

@@ -1,148 +0,0 @@
-// Verilog HDL for "RSFQ.lib", "dro_cell" "_functional"
-
-// Module DRO cell
-module dro_cell (d, clk, out);
-
-input
-	d, clk;
-
-output
-	out;
-reg 
-	out;
-
-parameter
-	t_hold	= -3,
-	t_setup	= 8,
-	delay	= 9,
-
-// multichannel description of a warning file
-	warning_file=2,  
-// multichannel description of a delay file
-	delay_file = warning_file<<1;
-
-reg
-	d_internal, clk_internal,
-	d_state,          	   // internal state at the input d
-	d_set;		   	   // signal determining the moment when
-				   // the state of the d input changes to "1"
-
-integer
-	data_delay,  // delay between d and d_internal
-	clk_delay,   // delay between clk and clk_internal
-	out_delay,   // delay between clk_internal and out
-	out_value,   // output value in a given clock cycle
-	last_clk_time,	// time when the last clock pulse appeared
-	vt_hold,	// variable hold
-	vt_setup,	// variable setup
-	vdelay;		// variable delay
-
-`include "INIT"
-
-`ifdef RANDOM_DELAYS
- `include "RANDOM_GATE"
-`endif
-
-initial 
-	begin
-		vt_hold = t_hold;
-		vt_setup = t_setup;
-		vdelay = delay;
-
-`ifdef RANDOM_DELAYS
-		delay_dev = dro_cell_variation*delay;
-		vdelay = $dist_normal(dro_cell_seed, delay, delay_dev);
-		vt_hold = $dist_normal(dro_cell_seed, t_hold, dro_hs_dev);
-		vt_setup = t_setup + (t_hold - vt_hold);
-`endif
-
-		#1 $fdisplay(delay_file, "module=%m, nom_delay=%0d, delay=%0d", delay, vdelay);
-		#1 $fdisplay(delay_file, "module=%m, nom_hold=%0d, hold=%0d", t_hold, vt_hold);
-		#1 $fdisplay(delay_file, "module=%m, nom_setup=%0d, setup=%0d", t_setup, vt_setup);
-
-
-// define delays between inputs & outputs and the corresponding
-//  internal auxiliary registers
-	  	if(vt_hold<0)
-		  begin
-	    	  	data_delay = -vt_hold;
-	    		clk_delay  = 0;
-			out_delay  = vdelay;
-		  end
-	  	else
-		  begin
-	   	  	data_delay = 0;
-	    		clk_delay  = vt_hold;
-		  	out_delay  = vdelay-vt_hold;
-		  end
-
-// clear internal registers and the output signal
-		d_internal = 0;
-		clk_internal = 0;
-		last_clk_time = 0;
-		d_state = 0;
-		d_set = 0;
-		out = 0;
-	end
-
-
-
-always @(posedge d) 	// Execute at positive edge of d
-	  d_internal <= #(data_delay) d;
-
-always @(posedge clk)  // Execute at positive edge of clk
-	  clk_internal <= #(clk_delay) clk;
-
-
-always @(posedge d_internal)
-	begin
-// setting the state of the d input
-                d_state <= d_state | 1'bx;
-		if (d_internal === 1)
-		  d_set <= #(vt_hold+vt_setup) 1;
-
-		d_internal <= 0;
-	end
-
-always @(posedge d_set)
-	begin
-		if ($stime - last_clk_time >= vt_hold+vt_setup)
-			d_state = 1;
-		else
-		  begin
-			d_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input D pulse at %0d,",
-			 $stime-data_delay-vt_hold-vt_setup);
-			$fwrite(warning_file,
-			"\tClock pulse at %0d.\n", last_clk_time-clk_delay);
-		  end
-
-		d_set <= 0;
-	end
-
-
-always @(posedge clk_internal)	
-	begin
-// computing the output
-		if (clk_internal === 1'bx)
-		  out_value = 1'bx;
-		else
-		  out_value = d_state;
-
-// transfering the result to the output
-		out <= #(out_delay) out_value;
-		out <= #(out_delay+2) 0;
-
-// clearing the internal state of the DRO
-		d_state  <= 0;
-
-		clk_internal <= 0;
-		last_clk_time = $stime;
-	end
-
-endmodule

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/dump_and_fill_mem_test.v Deleted

@@ -1,107 +0,0 @@
-/**********************************************************************
- * $dump_mem_hex and $fill_mem example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $dump_mem_hex, $dump_mem_ascii
- * and $fill_mem PLI applications.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns 
-module dump_mem_test;
-
-  parameter LEFT_BIT = 23, RIGHT_BIT = 00, FIRST_ADDR = 0, LAST_ADDR = 3;
-//  parameter LEFT_BIT = 00, RIGHT_BIT = 23, FIRST_ADDR = 0, LAST_ADDR = 3;
-//  parameter LEFT_BIT = 23, RIGHT_BIT = 00, FIRST_ADDR = 3, LAST_ADDR = 0;
-//  parameter LEFT_BIT = 00, RIGHT_BIT = 23, FIRST_ADDR = 3, LAST_ADDR = 0;
-//  parameter LEFT_BIT = 24, RIGHT_BIT = 01, FIRST_ADDR = 0, LAST_ADDR = 3;
-//  parameter LEFT_BIT = 01, RIGHT_BIT = 24, FIRST_ADDR = 0, LAST_ADDR = 3;
-//  parameter LEFT_BIT = 23, RIGHT_BIT = 00, FIRST_ADDR = 1, LAST_ADDR = 4;
-//  parameter LEFT_BIT = 23, RIGHT_BIT = 00, FIRST_ADDR = 4, LAST_ADDR = 1;
-
-  reg  LEFT_BIT:RIGHT_BIT RAM FIRST_ADDR:LAST_ADDR;
-
-  integer addr;
-  wire 23:0 vector1, vector2;
-
-  initial
-    begin
-      $display("Loading memory from Verilog HDL...\n");
-      fill_mem("Hello world!");
-      #1 dump_mem_hex;
-      #1 dump_mem_ascii;
-      $display("Accessing memory using $dump_mem...\n");
-      $dump_mem_hex(RAMFIRST_ADDR); /* address ignored by PLI */
-      $dump_mem_ascii(RAMFIRST_ADDR);
-
-      $display("\nModifying memory using $fill_mem...\n");
-      $fill_mem(RAMFIRST_ADDR, FIRST_ADDR);
-      #1 dump_mem_hex;
-      $dump_mem_hex(RAMFIRST_ADDR);
-      #10 $finish;
-    end
-
-  assign vector1 = RAMFIRST_ADDR;
-  always @(vector1)
-    $display("\nRAM%0d just changed to %h\n", FIRST_ADDR, RAMFIRST_ADDR);
-
-  assign vector2 = RAMLAST_ADDR;
-  always @(vector2)
-    $display("\nRAM%0d just changed to %h\n", LAST_ADDR, RAMLAST_ADDR);
-
-
-  task dump_mem_ascii;
-    begin
-      $write("Within Verilog:\n Memory contents in ASCII are:\n   ");
-      if (FIRST_ADDR < LAST_ADDR)
-        for (addr=FIRST_ADDR; addr<=LAST_ADDR; addr=addr+1)
-          $write("%s", RAMaddr);
-      else
-        for (addr=FIRST_ADDR; addr>=LAST_ADDR; addr=addr-1)
-          $write("%s", RAMaddr);
-      $display("\n");           //terminate dump string
-    end
-  endtask
-
-  task dump_mem_hex;
-    begin
-      $display("Within Verilog:\n Memory contents in hex are:");
-      if (FIRST_ADDR < LAST_ADDR)
-        for (addr=FIRST_ADDR; addr<=LAST_ADDR; addr=addr+1)
-          $display("   address %0d:\t %h", addr, RAMaddr);
-      else
-        for (addr=FIRST_ADDR; addr>=LAST_ADDR; addr=addr-1)
-          $display("   address %0d:\t %h", addr, RAMaddr);
-    end
-  endtask
-
-  task fill_mem; /* assumes at least 4 words, each word at least 24 bits wide */
-    input (20*8)-1:0 string; /* input for 20 ASCII characters */
-    begin
-      if (FIRST_ADDR < LAST_ADDR)
-        begin
-          if (   (LEFT_BIT - RIGHT_BIT) !== 23
-              && (RIGHT_BIT - LEFT_BIT) !== 23 )
-            disable fill_mem;  /* abort if word is not 24 bits wide */
-          RAMFIRST_ADDR+3 = string23: 0;
-          RAMFIRST_ADDR+2 = string47:24;
-          RAMFIRST_ADDR+1 = string71:48;
-          RAMFIRST_ADDR+0 = string95:72;
-        end
-      else
-        begin
-          if (   (LEFT_BIT - RIGHT_BIT) !== 23
-              && (RIGHT_BIT - LEFT_BIT) !== 23 )
-            disable fill_mem;  /* abort if word is not 24 bits wide */
-          RAMFIRST_ADDR-3 = string23: 0;
-          RAMFIRST_ADDR-2 = string47:24;
-          RAMFIRST_ADDR-1 = string71:48;
-          RAMFIRST_ADDR-0 = string95:72;
-        end
-    end
-  endtask
-
-endmodule

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/exprinfo_test.v Deleted

@@ -1,40 +0,0 @@
-/**********************************************************************
- * $exprinfo_test example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $exprinfo_test PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-  reg        reg1;
-  reg 31:0 reg2;
-  reg 0:51 reg3;
-  real       r1;
-
-  initial
-    begin
-      reg1 = 1'b0;
-      reg2 = 32'hF0F0F0F0;
-      reg3 = {13{4'b01zx}};
-      r1   = 3.1415;
-
-      #1 $exprinfo_test("Hello world");
-      #1 $exprinfo_test(r1);
-      #1 $exprinfo_test(reg1);
-      #1 $exprinfo_test(reg2);
-      #1 $exprinfo_test(reg3);
-      #1 $exprinfo_test(reg31);
-      #1 $exprinfo_test(reg34:48);
-
-      #1 $finish;
-    end
-
-endmodule
-
-/**********************************************************************/
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/fetch_values_test.v Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/ff.v Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/ff_test.v Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/fifo.v Deleted

@@ -1,327 +0,0 @@
-// Synchronous FIFO.  4 x 16 bit words.
-//
-module fifo (clk, rstp, din, writep, readp, dout, emptyp, fullp);
-input		clk;
-input		rstp;
-input 15:0	din;
-input		readp;
-input		writep;
-output 15:0	dout;
-output		emptyp;
-output		fullp;
-
-// Defines sizes in terms of bits.
-//
-parameter	DEPTH = 2,		// 2 bits, e.g. 4 words in the FIFO.
-		MAX_COUNT = 2'b11;	// topmost address in FIFO.
-
-reg 		emptyp;
-reg		fullp;
-
-// Registered output.
-reg 15:0	dout;
-
-// Define the FIFO pointers.  A FIFO is essentially a circular queue.
-//
-reg (DEPTH-1):0	tail;
-reg (DEPTH-1):0	head;
-
-// Define the FIFO counter.  Counts the number of entries in the FIFO which
-// is how we figure out things like Empty and Full.
-//
-reg (DEPTH-1):0	count;
-
-// Define our regsiter bank.  This is actually synthesizable!
-//
-reg 15:0 fifomem0:MAX_COUNT;
-
-// Dout is registered and gets the value that tail points to RIGHT NOW.
-//
-always @(posedge clk) begin
-   if (rstp == 1) begin
-      dout <= 16'h0000;
-   end
-   else begin
-      dout <= fifomemtail;
-   end
-end 
-     
-// Update FIFO memory.
-always @(posedge clk) begin
-   if (rstp == 1'b0 && writep == 1'b1 && fullp == 1'b0) begin
-      fifomemhead <= din;
-   end
-end
-                  
-// Update the head register.
-//
-always @(posedge clk) begin
-   if (rstp == 1'b1) begin
-      head <= 2'b00;
-   end
-   else begin
-      if (writep == 1'b1 && fullp == 1'b0) begin
-         // WRITE
-         head <= head + 1;
-      end
-   end
-end
-
-// Update the tail register.
-//
-always @(posedge clk) begin
-   if (rstp == 1'b1) begin
-      tail <= 2'b00;
-   end
-   else begin
-      if (readp == 1'b1 && emptyp == 1'b0) begin
-         // READ               
-         tail <= tail + 1;
-      end
-   end
-end
-
-// Update the count regsiter.
-//
-always @(posedge clk) begin
-   if (rstp == 1'b1) begin
-      count <= 2'b00;
-   end
-   else begin
-      case ({readp, writep})
-         2'b00: count <= count;
-         2'b01: 
-            // WRITE
-            if (count != MAX_COUNT) 
-               count <= count + 1;
-         2'b10: 
-            // READ
-            if (count != 2'b00)
-               count <= count - 1;
-         2'b11:
-            // Concurrent read and write.. no change in count
-            count <= count;
-      endcase
-   end
-end
-
-         
-// *** Update the flags
-//
-// First, update the empty flag.
-//
-always @(count) begin
-   if (count == 2'b00)
-      emptyp <= 1'b1;
-   else
-      emptyp <= 1'b0;
-end
-
-
-// Update the full flag
-//
-always @(count) begin
-   if (count == MAX_COUNT)
-      fullp <= 1'b1;
-   else
-      fullp <= 1'b0;
-end
-
-endmodule
-
-// synopsys translate_off
-
-`define TEST_FIFO
-// synopsys translate_off
-`ifdef TEST_FIFO
-module test_fifo;
-
-reg		clk;
-reg		rstp;
-reg 15:0	din;
-reg		readp;
-reg		writep;
-wire 15:0	dout;
-wire		emptyp;
-wire		fullp;
-
-reg 15:0	value;
-
-fifo U1 (
-   .clk		(clk),
-   .rstp	(rstp),
-   .din		(din),
-   .readp	(readp),
-   .writep	(writep),
-   .dout	(dout),
-   .emptyp	(emptyp),
-   .fullp	(fullp)
-);
-
-task read_word;
-begin
-   @(negedge clk);
-   readp = 1;
-   @(posedge clk) #5;
-   $display ("Read %0h from FIFO", dout);
-   readp = 0;
-end
-endtask
-   
-task write_word;
-input 15:0	value;
-begin
-   @(negedge clk);
-   din = value;
-   writep = 1;
-   @(posedge clk);
-   $display ("Write %0h to FIFO", din);
-   #5;
-   din = 16'hzzzz;
-   writep = 0;
-end
-endtask
-
-initial begin
-   clk = 0;
-   forever begin
-      #10 clk = 1;
-      #10 clk = 0;
-   end
-end
-
-initial begin
-   $shm_open ("./fifo.shm");
-   $shm_probe (test_fifo, "AS");
-   
-   //test1;
-   test2;
-   
-   $shm_close;
-   $finish;
-end
-
-task test1;
-begin
-   din = 16'hzzzz;
-   writep = 0;
-   readp = 0;
-
-   // Reset
-   rstp = 1;
-   #50;
-   rstp = 0;
-   #50;
-   
-   // ** Write 3 values.
-   write_word (16'h1111);
-   write_word (16'h2222);
-   write_word (16'h3333);
-   
-   // ** Read 2 values
-   read_word;
-   read_word;
-   
-   // ** Write one more
-   write_word (16'h4444);
-   
-   // ** Read a bunch of values
-   repeat (6) begin
-      read_word;
-   end
-   
-   // *** Write a bunch more values
-   write_word (16'h0001);
-   write_word (16'h0002);
-   write_word (16'h0003);
-   write_word (16'h0004);
-   write_word (16'h0005);
-   write_word (16'h0006);
-   write_word (16'h0007);
-   write_word (16'h0008);
-
-   // ** Read a bunch of values
-   repeat (6) begin
-      read_word;
-   end
-   
-   $display ("Done TEST1.");
-end
-endtask
-
-// TEST2
-//
-// This test will operate the FIFO in an orderly manner the way it normally works.
-// 2 threads are forked; a reader and a writer.  The writer writes a counter to
-// the FIFO and obeys the fullp flag and delays randomly.  The reader likewise
-// obeys the emptyp flag and reads at random intervals.  The result should be that
-// the reader reads the incrementing counter out of the FIFO.  The empty/full flags
-// should bounce around depending on the random delays.  The writer repeats some
-// fixed number of times and then terminates both threads and kills the sim.
-//
-task test2;
-reg 15:0 writer_counter;
-begin
-   writer_counter = 16'h0001;
-   din = 16'hzzzz;
-   writep = 0;
-   readp = 0;
-
-   // Reset
-   rstp = 1;
-   #50;
-   rstp = 0;
-   #50;
-   
-   fork
-      // Writer
-      begin
-         repeat (500) begin
-            @(negedge clk);
-            if (fullp == 1'b0) begin
-               write_word (writer_counter);
-               #5;
-               writer_counter = writer_counter + 1;
-            end
-            else begin
-               $display ("WRITER is waiting..");
-            end
-            // Delay a random amount of time between 0ns and 100ns
-            #(50 + ($random % 50));
-         end
-         $display ("Done with WRITER fork..");
-         $finish;
-      end
-      
-      // Reader
-      begin
-         forever begin
-            @(negedge clk);
-            if (emptyp == 1'b0) begin
-               read_word;
-            end  
-            else begin
-               $display ("READER is waiting..");
-            end
-            // Delay a random amount of time between 0ns and 100ns
-            #(50 + ($random % 50));
-         end
-      end
-   join
-end
-endtask
-
-always @(fullp)
-   $display ("fullp = %0b", fullp);
-   
-always @(emptyp)
-   $display ("emptyp = %0b", emptyp);
-
-always @(U1.head)
-   $display ("head = %0h", U1.head);
-
-always @(U1.tail)
-   $display ("tail = %0h", U1.tail);
-
-endmodule
-`endif

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/find_driver.tcl.gz Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/framer.v Deleted

@@ -1,323 +0,0 @@
-//
-// Simple example of a "framer".  In this case, an MPEG framer where
-// data is sent in 188-byte frames which begin with a special SYNC character
-// defined as 47 hex.  Framing must, of course, handle cases where 47s
-// happen to also be embedded in the data.  Framer must be able to find
-// the period SYNC characters while not be thrown off by spurious SYNCs.
-//
-// This circuit uses a modulo-188 counter that serves as a timestamp.
-// Every received SYNC character causes the current modulo-188 counter
-// to be pushed onto a little queue.  The idea is that the timestamps
-// should all be the same if the data was perfectly framed.  If spurious
-// false SYNC characters fall in the data, then some of the timestamps
-// will be different.  This is OK as long as there is a clear majority.
-//
-// This circuit is something I started to actually have to do, but then
-// I ended up not using it.  It is not tested, so use it only for ideas
-// and not as a proven circuit!!
-//
-// tom coonan, 12/1999
-//
-module framer (clk, resetb, din, dinstb, dout, doutsync, doutstb, locked);
-input		clk;
-input		resetb;
-input 7:0	din;
-input		dinstb;
-output 7:0	dout;
-output		doutsync;
-output		doutstb;
-output		locked;
-
-parameter SYNC = 8'h47;
-
-reg 7:0	dout;
-reg		doutsync;
-reg		doutstb;
-reg		locked;
-
-/* Internals */
-
-// Free-running Modulo-188 counter
-reg 7:0	cnt188;
-
-// Modulo-188 value when SYNCs are expected once locked.
-reg 7:0	syncindex;
-
-// 6 deep queue of timestamps of every time a SYNC character is received.
-// the timestamp is the value of the modulo-188 counter when a SYNC is received.
-//
-reg 7:0	t0;	// Oldest timestamp
-reg 7:0	t1;
-reg 7:0	t2;
-reg 7:0	t3;
-reg 7:0	t4;
-reg 7:0	t5;	// Newest timestamp
-
-// Modulo-188 free-running counter.
-//
-always @(posedge clk or negedge resetb) begin
-   if (~resetb) begin
-      cnt188 <= 0;
-   end
-   else begin
-      if (dinstb) begin
-         if (cnt188 == 187) begin
-            cnt188 <= 0;
-         end
-         else begin
-            cnt188 <= cnt188 + 1;
-         end
-      end
-   end
-end
-
-// Timestamp queue.
-//
-always @(posedge clk or negedge resetb) begin
-   if (~resetb) begin
-      t0 <= 8'hff;  // Let's use FF as an invalid indicator, otherwise
-      t1 <= 8'hff;  // we'd potentially get a premature lock..
-      t2 <= 8'hff;
-      t3 <= 8'hff;
-      t4 <= 8'hff;
-      t5 <= 8'hff;
-   end
-   else begin
-      if (dinstb && (din == SYNC)) begin
-         // Add new timestamp into our queue.
-         t0 <= t1;   
-         t1 <= t2;   
-         t2 <= t3;   
-         t3 <= t4;   
-         t4 <= t5;   
-         t5 <= cnt188;   
-      end
-   end
-end
-
-// Comparators.
-wire t0equal = (t0 == cnt188) && (t0 != 8'hFF);
-wire t1equal = (t1 == cnt188) && (t1 != 8'hFF);
-wire t2equal = (t2 == cnt188) && (t2 != 8'hFF);
-wire t3equal = (t3 == cnt188) && (t3 != 8'hFF);
-wire t4equal = (t4 == cnt188) && (t4 != 8'hFF);
-wire t5equal = (t5 == cnt188) && (t5 != 8'hFF);
-
-// Count number of matches in all the prior timestamps and current modulo-188 time.
-wire 3:0 numequal = t0equal + t1equal + t2equal + t3equal + t4equal + t5equal;
-
-// Main sequential process.
-//
-always @(posedge clk or negedge resetb) begin
-   if (~resetb) begin
-      locked   <= 0;
-      dout     <= 0;
-      doutstb  <= 0;
-      doutsync <= 0;
-      syncindex <= 0;
-   end
-   else begin
-      doutstb  <= 0;  // defaults..
-      doutsync <= 0;
-      if (dinstb) begin
-         dout    <= din;
-         doutstb <= 1;
-         if (locked) begin
-            if (cnt188 == syncindex) begin
-               // We expect the data input to be a SYNC.  If it is not, we will
-               // immediately drop lock.
-               //
-               if (din == SYNC) begin
-                  $display (".. Received expected SYNC ..");
-                  doutsync <= 1;
-               end
-               else begin
-                  locked   <= 0;
-                  $display (".. Did not receive expected SYNC, dropping lock! ");
-               end
-            end
-         end
-         else begin
-            // The following line is the criteria for declaring LOCK.  It
-            // says that when a SYNC is recieved we look at the current
-            // timestamp, and if this timestamp is present in at least
-            // 4 other times in the queue, than this SYNC is an actual SYNC.
-            //
-            if ((din == SYNC) && (numequal > 3)) begin
-               doutsync <= 1;
-               locked   <= 1;
-               syncindex <= cnt188;
-               $display (".. Received SYNC (cnt188=%0h) and declaring LOCK!", cnt188);
-            end
-         end
-      end
-   end
-end
-
-endmodule
-
-// synopsys translate_off
-module test;
-
-reg		clk;
-reg		resetb;
-reg 7:0	din;
-reg		dinstb;
-wire 7:0	dout;
-wire		doutsync;
-wire		doutstb;
-wire		locked;
-
-// Instantiate the framer
-framer framer (
-   .clk(clk),
-   .resetb(resetb),
-   .din(din),
-   .dinstb(dinstb),
-   .dout(dout),
-   .doutsync(doutsync),
-   .doutstb(doutstb),
-   .locked(locked)
-);
-
-initial begin
-   fork
-      monitor_cycles(100000); // just in case..
-      genreset;
-      genclock;
-      begin
-         gendata (20);
-         $display ("Done sending good framed data, now sending trash..");
-         genradomdata (188*3);  // 3 frames worth of trash.. should drop lock.
-         $display ("Done sending trash.  Killing simulation.");
-         $finish;
-      end
-      monitor_framer_output;
-   join
-end
-
-// Generate VCD file for viewing.
-initial begin
-   $dumpfile ("framer.vcd");
-   $dumpvars (0,test);   
-end
-
-// Just a generic task for watching total cycles.
-task monitor_cycles;
-   input	maxcycles;
-   integer	maxcycles;
-   integer	cycles;
-   begin
-      forever begin
-         @(posedge clk);
-         cycles = cycles + 1;
-         if (cycles > maxcycles) begin
-            $finish;
-         end
-      end
-   end
-endtask
-
-// Watch output of framer.  Expect to see the pattern 1,2,3,4 after each SYNC.
-// This is the pattern that will be injected into framer.
-//
-task monitor_framer_output;
-   integer	cnt;
-   integer	numerrors;
-   begin
-      numerrors = 0;
-      forever begin
-         @(posedge doutstb);
-         #1;
-         if (doutsync) begin
-            $display ("Framer says SYNC..");
-            cnt = 1;
-            repeat (4) begin
-               @(posedge doutstb);
-               #1
-               $display ("   and %h..", dout);
-               if (dout != cnt) begin
-                  numerrors = numerrors + 1;
-                  $display ("!! Unexpected data from framer !! (%0d errors)", numerrors);
-               end
-               cnt = cnt + 1;
-            end
-         end
-      end
-   end
-endtask
-
-task genreset;
-   begin
-      resetb = 0;
-      repeat (2) @(posedge clk);
-      @(negedge clk);
-      resetb = 1;
-   end
-endtask
-
-task genclock;
-   begin
-      clk = 0;
-      forever begin
-         #10 clk = ~clk;
-      end
-   end
-endtask
-
-// Input framed data into the framer.  First 4 bytes of each frame should be
-// a simple counting sequence that can then be checked at its output.
-//
-task gendata;
-   input	numframes;
-   
-   integer	numframes;
-   
-   integer	cnt;
-   begin
-      cnt = $random;  // Start randomly in the frame sequence..
-      repeat (numframes*188) begin
-         repeat (3) @(posedge clk);
-         if (cnt == 0) begin
-            din = 8'h47;
-            $display ("SYNC..");
-         end
-         else begin
-            if (cnt < 5) begin
-               din = cnt;
-            end
-            else begin
-               din = $random;
-               if (din == 8'h47) begin
-                  $display ("   .. Non-SYNC 0x47 embedded in frame data !");
-               end
-            end
-         end
-      
-         dinstb = 1;
-         @(posedge clk);
-         dinstb = 0;
-         cnt = (cnt + 1) % 188;
-      end
-   end
-endtask
-
-// This will inject trash (no good framing) into framer.  Use this to show
-// that it actually drops lock.
-//
-task genradomdata;
-   input	numbytes;
-   integer	numbytes;
-   begin
-      repeat (numbytes) begin
-         repeat (3) @(posedge clk);
-         din = $random;
-         dinstb = 1;
-         @(posedge clk);
-         dinstb = 0;
-      end
-   end
-endtask
-
-endmodule
-// synopsys translate_on

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/func_72bit_test.v Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/gen.v Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/gencrc.v Deleted

@@ -1,287 +0,0 @@
-//
-// Behavioral Verilog for CRC16 and CRC32 for use in a testbench.
-//
-// The specific polynomials and conventions regarding bit-ordering etc.
-// are specific to the Cable Modem DOCSIS protocol, but the general scheme
-// should be reusable for other types of CRCs with some fiddling.
-//
-// This CRC code works for a specific type of network protocol, and it
-// must do certain byte swappings, etc.  You may need to play with it 
-// for your protocol.  Also, make sure the polynomials are what you
-// really want.  This is obviously, not synthesizable - I just used this
-// in a testbench at one point.
-//
-// These tasks are crude and rely on some global parameters.  They should
-// also read from a file, yada yada yada.  It is probably better to do this 
-// with a PLI call, but here it is anyway..
-//
-// The test case includes a golden DOCSIS (Cable Modem) test message that 
-// was captured in a lab.
-//
-// tom coonan, 1999.
-//
-module test_gencrc;
-
-// *** Buffer for the Golden Message ***
-reg 7:0	test_packet0:54;  
-
-// *** Global parameter block for the CRC32 calculator.
-//
-parameter	CRC32_POLY = 32'h04C11DB7;
-reg  7:0	crc32_packet0:255;
-integer		crc32_length;
-reg 31:0	crc32_result;
-
-// *** Global parameter block for the CRC16 calculator.
-//
-parameter	CRC16_POLY = 16'h1020;
-reg  7:0	crc16_packet0:255;
-integer		crc16_length;
-reg 15:0	crc16_result;
-
-`define TEST_GENCRC
-`ifdef TEST_GENCRC
-// Call the main test task and then quit.
-//
-initial begin
-   main_test;
-   $finish;
-end
-`endif
-
-// ****************************************************************
-// *
-// *   GOLDEN MESSAGE
-// *
-// *   The golden message is a DOCSIS frame that was captured off
-// *   the Broadcom reference design.  It is a MAP message.  It
-// *   includes a HCS (crc 16) and a CRC32.
-// *
-// *
-// ****************************************************************
-//
-task initialize_test_packet;
-   begin
-      test_packet00 = 8'hC2;	// FC.   HCS coverage starts here.
-      test_packet01 = 8'h00;	// MACPARAM
-      test_packet02 = 8'h00;	// MAC LEN
-      test_packet03 = 8'h30;	// MAC LEN.  HCS Coverage includes this byte and ends here.
-      test_packet04 = 8'hF2;	// CRC16 (also known as HCS)
-      test_packet05 = 8'hCF;	// CRC16 cont..
-      test_packet06 = 8'h01;	// Start of the IEEE payload.  CRC32 covererage starts here.  This is the DA field
-      test_packet07 = 8'hE0;	// DA field cont..
-      test_packet08 = 8'h2F;	// DA field cont..
-      test_packet09 = 8'h00;	// DA field cont..
-      test_packet10 = 8'h00;	// DA field cont..
-      test_packet11 = 8'h01;	// DA field cont..
-      test_packet12 = 8'h00;	// SA field
-      test_packet13 = 8'h80;	// SA field cont..
-      test_packet14 = 8'h42;	// SA field cont..
-      test_packet15 = 8'h42;	// SA field cont..
-      test_packet16 = 8'h20;	// SA field cont..
-      test_packet17 = 8'h9E;	// SA field cont..
-      test_packet18 = 8'h00;	// IEEE LEN field
-      test_packet19 = 8'h1E;	// IEEE LEN field cont.
-      test_packet20 = 8'h00;	// LLC field.
-      test_packet21 = 8'h00;	// LLC field cont...
-      test_packet22 = 8'h03;	// LLC field cont...
-      test_packet23 = 8'h01;	// LLC field cont...
-      test_packet24 = 8'h03;	// LLC field cont...  This is also the TYPE, which indicates MAP.
-      test_packet25 = 8'h00;	// LLC field cont...
-      test_packet26 = 8'h01;	// Start of MAP message payload.
-      test_packet27 = 8'h01;	// MAP message payload..
-      test_packet28 = 8'h02;	// MAP message payload..
-      test_packet29 = 8'h00;	// MAP message payload..
-      test_packet30 = 8'h00;	// MAP message payload..
-      test_packet31 = 8'h18;	// MAP message payload..
-      test_packet32 = 8'hAA;	// MAP message payload..
-      test_packet33 = 8'h58;	// MAP message payload..
-      test_packet34 = 8'h00;	// MAP message payload..
-      test_packet35 = 8'h18;	// MAP message payload..
-      test_packet36 = 8'hA8;	// MAP message payload..
-      test_packet37 = 8'hA0;	// MAP message payload..
-      test_packet38 = 8'h02;	// MAP message payload..
-      test_packet39 = 8'h03;	// MAP message payload..
-      test_packet40 = 8'h03;	// MAP message payload..
-      test_packet41 = 8'h08;	// MAP message payload..
-      test_packet42 = 8'hFF;	// MAP message payload..
-      test_packet43 = 8'hFC;	// MAP message payload..
-      test_packet44 = 8'h40;	// MAP message payload..
-      test_packet45 = 8'h00;	// MAP message payload..
-      test_packet46 = 8'h00;	// MAP message payload..
-      test_packet47 = 8'h01;	// MAP message payload..
-      test_packet48 = 8'hC0;	// MAP message payload..
-      test_packet49 = 8'h14;	// Last byte of MAP payload, last byte covered by CRC32.
-      test_packet50 = 8'hDD;	// CRC32 Starts here
-      test_packet51 = 8'hBF;	// CRC32 cont..
-      test_packet52 = 8'hC1;	// CRC32 cont..
-      test_packet53 = 8'h2E;	// Last byte of CRC32, last byte of DOCSIS.
-   end
-endtask
-
-// *************************************************************************
-// *
-// *   Main test task.
-// *
-// *   Use our primary "golden packet".  Copy into the generic global
-// *   variables that the low-level 'gencrc16' and 'gencrc32' tasks use.
-// *   Comare against the expected values and report SUCCESS or FAILURE.
-// *
-// *************************************************************************
-//
-task main_test;
-   integer	i, j;
-   integer	num_errors;
-   reg 15:0	crc16_expected;
-   reg 31:0	crc32_expected;
-   begin
-   
-   num_errors = 0;
-   
-   // Initialize the Golden Message!
-   //
-   initialize_test_packet;
-   
-   // **** TEST CRC16
-   //
-   $display ("Testing CRC16:");
-   //
-   // Copy golden test_packet into the main crc16 buffer..
-   for (i=0; i<4; i=i+1) begin
-      crc16_packeti = test_packeti;
-   end
-   crc16_expected = {test_packet4, test_packet5};
-   crc16_length = 4;  // Must tell test function the length
-   gencrc16;  // Call main test function
-   $display ("   Actual crc16_result = %h, Expected = %h", crc16_result, crc16_expected);
-   if (crc16_result == crc16_expected) begin
-      $display ("   Success.");
-   end
-   else begin
-      $display ("   ERROR!!!");
-      num_errors = num_errors + 1;
-   end
-
-   // **** TEST CRC16
-   //
-   $display ("Testing CRC32:");
-   j = 0;
-   for (i=6; i<50; i=i+1) begin
-      crc32_packetj = test_packeti;
-      j = j + 1;
-   end
-   crc32_expected = {test_packet50, test_packet51, test_packet52, test_packet53};
-   crc32_length = 44;
-   gencrc32;
-   $display ("   Actual crc32_result = %h, Expected = %h", crc32_result, crc32_expected);
-   if (crc32_result == crc32_expected) begin
-      $display ("   Success.");
-   end
-   else begin
-      $display ("   ERROR!!!");
-      num_errors = num_errors + 1;
-   end
-   
-   $display ("\nDone.  %0d Errors.", num_errors);
-   $display ("\n");
-   end
-endtask
-
-
-// ****************************************************************
-// *
-// *   Main working CRC tasks are: gencrc16, gencrc32.
-// *
-// *   These tasks rely on some globals (see front of program).
-// *
-// ****************************************************************
-
-
-// Generate a (DOCSIS) CRC16.
-//
-// Uses the GLOBAL variables:
-//
-//    Globals referenced:
-//       parameter	CRC16_POLY = 16'h1020;
-//       reg  7:0	crc16_packet0:255;
-//       integer	crc16_length;
-//
-//    Globals modified:
-//       reg 15:0	crc16_result;
-//
-task gencrc16;
-   integer	byte, bit;
-   reg		msb;
-   reg 7:0	current_byte;
-   reg 15:0	temp;
-   begin
-      crc16_result = 16'hffff;
-      for (byte = 0; byte < crc16_length; byte = byte + 1) begin
-         current_byte = crc16_packetbyte;
-         for (bit = 0; bit < 8; bit = bit + 1) begin
-            msb = crc16_result15;
-            crc16_result = crc16_result << 1;
-            if (msb != current_bytebit) begin
-               crc16_result = crc16_result ^ CRC16_POLY;
-               crc16_result0 = 1;
-            end
-         end
-      end
-      
-      // Last step is to "mirror" every bit, swap the 2 bytes, and then complement each bit.
-      //
-      // Mirror:
-      for (bit = 0; bit < 16; bit = bit + 1)
-         temp15-bit = crc16_resultbit;
-         
-      // Swap and Complement:
-      crc16_result = ~{temp7:0, temp15:8};
-   end
-endtask
-
-
-// Generate a (DOCSIS) CRC32.
-//
-// Uses the GLOBAL variables:
-//
-//    Globals referenced:
-//       parameter	CRC32_POLY = 32'h04C11DB7;
-//       reg  7:0	crc32_packet0:255;
-//       integer	crc32_length;
-//
-//    Globals modified:
-//       reg 31:0	crc32_result;
-//
-
-task gencrc32;
-   integer	byte, bit;
-   reg		msb;
-   reg 7:0	current_byte;
-   reg 31:0	temp;
-   begin
-      crc32_result = 32'hffffffff;
-      for (byte = 0; byte < crc32_length; byte = byte + 1) begin
-         current_byte = crc32_packetbyte;
-         for (bit = 0; bit < 8; bit = bit + 1) begin
-            msb = crc32_result31;
-            crc32_result = crc32_result << 1;
-            if (msb != current_bytebit) begin
-               crc32_result = crc32_result ^ CRC32_POLY;
-               crc32_result0 = 1;
-            end
-         end
-      end
-      
-      // Last step is to "mirror" every bit, swap the 4 bytes, and then complement each bit.
-      //
-      // Mirror:
-      for (bit = 0; bit < 32; bit = bit + 1)
-         temp31-bit = crc32_resultbit;
-         
-      // Swap and Complement:
-      crc32_result = ~{temp7:0, temp15:8, temp23:16, temp31:24};
-   end
-endtask
-
-endmodule
-

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_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/hadd.v Deleted

@@ -1,216 +0,0 @@
-// Verilog HDL for "LIB", "hadd" "_functional"
-
-module hadd (clock, A_in, B_in, carry, sum);
-
-// Default values for the timing parameters
-parameter
-	delay_carry = 33,
-	delay_sum = 37,
-	t_hold = 1,
-	t_setup = 31,
-	t_sep = 11,
-	warning_file = 2;
-
-// Declaration of data types
-input
-	clock,
-	A_in,
-	B_in;
-
-output
-	carry,
-	sum;
-
-reg
-	trig,
-	carry,
-	sum,
-	data_A,
-	data_B,
-	extra_A,
-	extra_B;	// Multi-pulse indicators
-
-integer
-	current_time,
-	holdtime,
-	sep_time,
-	left_bound,
-	right_bound,
-	time_A,
-	time_B;
-
-initial
-  begin		// Initialization
-	trig = 0;
-	left_bound = 0;
-	{data_A, data_B} = 0;
-	{carry, sum} = 0;
-	#0 holdtime = (t_hold < 0) ? 0 : t_hold;
-  end	// initial
-
-always @(posedge A_in)
-  begin
-    // Store the time position of the data (center of the pulse)
-    time_A = $time + 1;
-    // Store the value of the data input
-    data_A = A_in;
-
-    // Display warning if more than 1 data pulse comes in 1 clock cycle
-    if (extra_A == 'b1)
-      $fdisplay(warning_file, "Extra pulse detected in module %m at input A at %0d ps.\n", time_A);
-
-    extra_A = 1;	// Set after 1 data pulse comes
-  end	// always
-
-always @(posedge B_in)
-  begin
-    // Store the time position of the data (center of the pulse)
-    time_B = $time + 1;
-    // Store the value of the data input
-    data_B = B_in;
-
-    // Display warning if more than 1 data pulse comes in 1 clock cycle
-    if (extra_B == 'b1)
-      $fdisplay(warning_file, "Extra pulse detected in module %m at input B at %0d ps.\n", time_B);
-
-    extra_B = 1;	// Set after 1 data pulse comes
-  end	// always
-
-always @(posedge clock)
-// Trigger after clock+holdtime
-  trig <= #(holdtime-1) 1;
-
-always @(posedge trig)
-  begin
-    current_time = $time+1-(holdtime-1);	// Present time of clock
-// Delay = 0.5 so that clock cycles do not overlap
-    #0.5 trig = 0;
-
-    // Generate output only if there are input pulses
-    if ((data_A !== 'b0) | (data_B !== 'b0))
-      begin
-	// Reset to receive data input in a new clock cycle
-	extra_A = 0;
-	extra_B = 0;
-	// Determine the right boundary of the time range in which there is no timing violation
-	right_bound = current_time - t_setup;
-
-	casex ({(data_A !== 'b0), (data_B !== 'b0), ((time_A >= left_bound) & (time_A <= right_bound)), ((time_B >= left_bound) & (time_B <= right_bound))})
-
-	// Two data inputs and no timing violation
-	  4'b1111:
-	    begin
-	      sep_time = time_A - time_B;
-	      sep_time = (sep_time < 0) ? -sep_time : sep_time;
-	      // Separation time violation?
-	      if (sep_time < t_sep)
-		begin
-		  carry <= #(delay_carry - holdtime) 'bx;
-		  sum <= #(delay_sum - holdtime) 'bx;
-		  $fdisplay(warning_file, "Violation of separation time in module %m.\nInput A at %0d ps, input B at %0d ps.\n", time_A, time_B);
-		end
-	      else
-		carry <= #(delay_carry - holdtime) (data_A & data_B);
-	      // Reset to receive new data values in a new clock cycle
-	      {data_A, data_B} = 0;
-	    end
-
-	// One data input and no timing violation
-	  4'b101x:
-	    begin
-	      sum <= #(delay_sum - holdtime) data_A;
-	      data_A = 0;
-	    end
-
-	// One data input and no timing violation
-	  4'b01x1:
-	    begin
-	      sum <= #(delay_sum - holdtime) data_B;
-	      data_B = 0;
-	    end
-
-	// Two data inputs and there is timing violation
-	  4'b1100:
-	    begin
-	      carry <= #(delay_carry - holdtime) 'bx;
-	      sum <= #(delay_sum - holdtime) 'bx;
-	      // Issue a warning
-	      if ((time_A > right_bound) & (time_B > right_bound))
-		$fdisplay(warning_file, "Violation of hold/setup time in module %m. \nInput A at %0d ps, input B at %0d ps, clock at %0d ps.\n", time_A, time_B, current_time);
-	      else if (time_A > right_bound)
-		begin
-		  $fdisplay(warning_file, "Violation of hold/setup time in module %m. \nInput A at %0d ps, clock at %0d ps.\n", time_A, current_time);
-		  data_B = 0;
-		end
-	      else if (time_B > right_bound)
-		begin
-		  $fdisplay(warning_file, "Violation of hold/setup time in module %m. \nInput B at %0d ps, clock at %0d ps.\n", time_B, current_time);
-		  data_A = 0;
-		end
-	      // If a warning has been issued before
-	      else
-		{data_A, data_B} = 0;
-	    end
-
-	// One data input and there is timing violation
-	  4'b100x:
-	    begin
-	      sum <= #(delay_sum - holdtime) 'bx;
-	      // Issue a warning
-	      if (time_A > right_bound)
-		$fdisplay(warning_file, "Violation of hold/setup time in module %m. \nInput A at %0d ps, clock at %0d ps.\n", time_A, current_time);
-	      // If a warning has been issued before
-	      else
-		data_A = 0;
-	    end
-
-	// One data input and there is timing violation
-	  4'b01x0:
-	    begin
-	      sum <= #(delay_sum - holdtime) 'bx;
-	      // Issue a warning
-	      if (time_B > right_bound)
-		$fdisplay(warning_file, "Violation of hold/setup time in module %m. \nInput B at %0d ps, clock at %0d ps.\n", time_B, current_time);
-	      // If a warning has been issued before
-	      else
-		data_B = 0;
-	    end
-
-	// Two data inputs and there is timing violation
-	  4'b1110:
-	    begin
-	      carry <= #(delay_carry - holdtime) 'bx;
-	      sum <= #(delay_sum - holdtime) 'bx;
-	      // Issue a warning
-	      if (time_A > right_bound)
-		$fdisplay(warning_file, "Violation of hold/setup time in module %m. \nInput A at %0d ps, clock at %0d ps.\n", time_A, current_time);
-	      // If a warning has been issued before
-	      else
-		data_A = 0;
-	    end
-
-	// Two data inputs and there is timing violation
-	  4'b1101:
-	    begin
-	      carry <= #(delay_carry - holdtime) 'bx;
-	      sum <= #(delay_sum - holdtime) 'bx;
-	      // Issue a warning
-	      if (time_B > right_bound)
-		$fdisplay(warning_file, "Violation of hold/setup time in module %m. \nInput B at %0d ps, clock at %0d ps.\n", time_B, current_time);
-	      // If a warning has been issued before
-	      else
-		data_B = 0;
-	    end
-
-	endcase
-
-	// Reset the outputs after 2ps
-	carry <= #(delay_carry - holdtime + 2) 0;
-	sum <= #(delay_sum - holdtime + 2) 0;
-      end	// if
-
-     // Determine the left boundary of the time range in which there is no timing violation
-    left_bound = current_time + t_hold;
-  end	// always
-			
-endmodule

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/hasCompilerDirectives/pl.v Deleted

@@ -1,434 +0,0 @@
-/////////////////////////////////////////////////////////////////////
-////                                                             ////
-////  Protocol Layer                                             ////
-////  This block is typically referred to as the SEI in USB      ////
-////  Specification. It encapsulates the Packet Assembler,       ////
-////  disassembler, protocol engine and internal DMA             ////
-////                                                             ////
-////  Author: Rudolf Usselmann                                   ////
-////          rudi@asics.ws                                      ////
-////                                                             ////
-////                                                             ////
-////  Downloaded from: http://www.opencores.org/cores/usb/       ////
-////                                                             ////
-/////////////////////////////////////////////////////////////////////
-////                                                             ////
-//// Copyright (C) 2000 Rudolf Usselmann                         ////
-////                    rudi@asics.ws                            ////
-////                                                             ////
-//// This source file may be used and distributed without        ////
-//// restriction provided that this copyright statement is not   ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer.////
-////                                                             ////
-////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
-//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
-//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
-//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
-//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
-//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
-//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
-//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
-//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
-//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
-//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
-//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
-//// POSSIBILITY OF SUCH DAMAGE.                                 ////
-////                                                             ////
-/////////////////////////////////////////////////////////////////////
-
-//  CVS Log
-//
-//  $Id: pl.v,v 1.0 2001/03/07 09:17:12 rudi Exp $
-//
-//  $Date: 2001/03/07 09:17:12 $
-//  $Revision: 1.0 $
-//  $Author: rudi $
-//  $Locker:  $
-//  $State: Exp $
-//
-// Change History:
-//               $Log: pl.v,v $
-//               Revision 1.0  2001/03/07 09:17:12  rudi
-//
-//
-//               Changed all revisions to revision 1.0. This is because OpenCores CVS
-//               interface could not handle the original '0.1' revision ....
-//
-//               Revision 0.1.0.1  2001/02/28 08:11:11  rudi
-//               Initial Release
-//
-//
-
-`include "usb_defines.v"
-
-module pl(  clk, rst,
-
-        // UTMI Interface
-        rx_data, rx_valid, rx_active, rx_err,
-        tx_data, tx_valid, tx_valid_last, tx_ready,
-        tx_first, tx_valid_out,
-        mode_hs, usb_reset, usb_suspend, usb_attached,
-
-        // memory interface
-        madr, mdout, mdin, mwe, mreq, mack,
-
-        // Register File Interface
-        fa, idin,
-        ep_sel, match,
-        dma_in_buf_sz1, dma_out_buf_avail,
-        buf0_rl, buf0_set, buf1_set,
-        uc_bsel_set, uc_dpd_set,
-
-        int_buf1_set, int_buf0_set, int_upid_set,
-        int_crc16_set, int_to_set, int_seqerr_set,
-
-        csr, buf0, buf1,
-
-        // Misc
-        frm_nat,
-        pid_cs_err, nse_err,
-        crc5_err
-
-        );
-
-// UTMI Interface
-input       clk, rst;
-input   7:0   rx_data;
-input       rx_valid, rx_active, rx_err;
-output  7:0   tx_data;
-output      tx_valid;
-output      tx_valid_last;
-input       tx_ready;
-output      tx_first;
-input       tx_valid_out;
-input       mode_hs;    // High Speed Mode
-input       usb_reset;  // USB Reset
-input       usb_suspend;    // USB Suspend
-input       usb_attached;   // Attached to USB
-
-
-// Memory Arbiter Interface
-output  14:0  madr;       // word address
-output  31:0  mdout;
-input   31:0  mdin;
-output      mwe;
-output      mreq;
-input       mack;
-
-
-// Register File interface
-input   6:0   fa;     // Function Address (as set by the controller)
-output  31:0  idin;       // Data Input
-output  3:0   ep_sel;     // Endpoint Number Input
-input       match;      // Endpoint Matched
-input       dma_in_buf_sz1;
-input       dma_out_buf_avail;
-output      nse_err;    // no such endpoint error
-
-output      buf0_rl;    // Reload Buf 0 with original values
-output      buf0_set;   // Write to buf 0
-output      buf1_set;   // Write to buf 1
-output      uc_bsel_set;    // Write to the uc_bsel field
-output      uc_dpd_set; // Write to the uc_dpd field
-output      int_buf1_set;   // Set buf1 full/empty interrupt
-output      int_buf0_set;   // Set buf0 full/empty interrupt
-output      int_upid_set;   // Set unsupported PID interrupt
-output      int_crc16_set;  // Set CRC16 error interrupt
-output      int_to_set; // Set time out interrupt
-output      int_seqerr_set; // Set PID sequence error interrupt
-
-input   31:0  csr;        // Internal CSR Output
-input   31:0  buf0;       // Internal Buf 0 Output
-input   31:0  buf1;       // Internal Buf 1 Output
-
-// Misc
-output      pid_cs_err; // pid checksum error
-output      crc5_err;   // crc5 error
-output  31:0  frm_nat;
-
-
-///////////////////////////////////////////////////////////////////
-//
-// Local Wires and Registers
-//
-
-// Packet Disassembler Interface
-wire        clk, rst;
-wire    7:0   rx_data;
-wire        rx_valid, rx_active, rx_err;
-wire        pid_OUT, pid_IN, pid_SOF, pid_SETUP;
-wire        pid_DATA0, pid_DATA1, pid_DATA2, pid_MDATA;
-wire        pid_ACK, pid_NACK, pid_STALL, pid_NYET;
-wire        pid_PRE, pid_ERR, pid_SPLIT, pid_PING;
-wire    6:0   token_fadr;
-wire        token_valid;
-wire        crc5_err;
-wire    11:0  frame_no;
-wire    7:0   rx_data_st;
-wire        rx_data_valid;
-wire        rx_data_done;
-wire        crc16_err;
-wire        rx_seq_err;
-
-// Packet Assembler Interface
-wire        send_token;
-wire    1:0   token_pid_sel;
-wire        send_data;
-wire    1:0   data_pid_sel;
-wire    7:0   tx_data_st;
-wire        rd_next;
-
-// IDMA Interface
-wire        rx_dma_en;  // Allows the data to be stored
-wire        tx_dma_en;  // Allows for data to be retrieved
-wire        abort;      // Abort Transfer (time_out, crc_err or rx_error)
-wire        idma_done;  // DMA is done
-wire    16:0  adr;        // Byte Address
-wire    13:0  size;       // Size in bytes
-wire    10:0  sizu_c;     // Up and Down counting size registers, used
-                // to update
-wire    13:0  buf_size;   // Actual buffer size
-wire        dma_en;     // external dma enabled
-
-// Memory Arbiter Interface
-wire    14:0  madr;       // word address
-wire    31:0  mdout;
-wire    31:0  mdin;
-wire        mwe;
-wire        mreq;
-wire        mack;
-
-// Local signals
-wire        pid_bad, pid_bad1, pid_bad2;
-
-reg     hms_clk;    // 0.5 Micro Second Clock
-reg 4:0   hms_cnt;
-
-reg 11:0  frame_no_r; // Current Frame Number register
-wire        frame_no_we;
-reg     frame_no_same;  // Indicates current and prev. frame numbers
-                // are equal
-reg 3:0   mfm_cnt;    // Micro Frame Counter
-reg 11:0  sof_time;   // Time since last sof
-reg     clr_sof_time;
-
-wire        fsel;       // This Function is selected
-
-wire        match_o;
-
-///////////////////////////////////////////////////////////////////
-//
-// Misc Logic
-//
-
-
-// PIDs we should never receive
-assign pid_bad1 = pid_ACK | pid_NACK | pid_STALL | pid_NYET | pid_PRE |
-            pid_ERR | pid_SPLIT;
-
-// PIDs we should never get in full speed mode (high speed mode only)
-assign pid_bad2 = !mode_hs & pid_PING;
-
-// All bad pids
-assign pid_bad = pid_bad1 | pid_bad2;
-
-assign match_o = !pid_bad & match & token_valid & !crc5_err;
-
-// Frame Number (from SOF token)
-reg frame_no_we_r;
-
-assign frame_no_we = token_valid & !crc5_err & pid_SOF;
-
-always @(posedge clk)
-    frame_no_we_r <= #1 frame_no_we;
-
-always @(posedge clk)
-    if(!rst)    frame_no_r <= #1 0;
-    else
-    if(frame_no_we) frame_no_r <= #1 frame_no;
-
-// Micro Frame Counter
-always @(posedge clk)
-    frame_no_same <= #1 frame_no_we & (frame_no_r == frame_no);
-
-always @(posedge clk)
-    if(!rst)        mfm_cnt <= #1 0;
-    else
-    if(frame_no_we & !frame_no_same)
-                mfm_cnt <= #1 0;
-    else
-    if(frame_no_same)   mfm_cnt <= #1 mfm_cnt + 1;
-
-//SOF delay counter
-always @(posedge clk)
-    clr_sof_time <= #1 frame_no_we;
-
-always @(posedge clk)
-    if(clr_sof_time)    sof_time <= #1 0;
-    else
-    if(hms_clk)     sof_time <= #1 sof_time + 1;
-
-assign frm_nat = {mfm_cnt, frame_no_r, 4'h0, sof_time};
-
-
-// 0.5 Micro Seconds Clock Generator
-always @(posedge clk)
-    if(!rst | hms_clk | frame_no_we)    hms_cnt <= #1 0;
-    else                    hms_cnt <= #1 hms_cnt + 1;
-
-always @(posedge clk)
-    hms_clk <= #1 (hms_cnt == `HMS_DEL);
-
-///////////////////////////////////////////////////////////////////
-
-// This function is addressed
-assign fsel = (token_fadr == fa);
-
-///////////////////////////////////////////////////////////////////
-//
-// Module Instantiations
-//
-
-//Packet Decoder
-pd  u0( .clk(       clk     ),
-        .rst(       rst     ),
-        .rx_data(   rx_data     ),
-        .rx_valid(  rx_valid    ),
-        .rx_active( rx_active   ),
-        .rx_err(    rx_err      ),
-        .pid_OUT(   pid_OUT     ),
-        .pid_IN(    pid_IN      ),
-        .pid_SOF(   pid_SOF     ),
-        .pid_SETUP( pid_SETUP   ),
-        .pid_DATA0( pid_DATA0   ),
-        .pid_DATA1( pid_DATA1   ),
-        .pid_DATA2( pid_DATA2   ),
-        .pid_MDATA( pid_MDATA   ),
-        .pid_ACK(   pid_ACK     ),
-        .pid_NACK(  pid_NACK    ),
-        .pid_STALL( pid_STALL   ),
-        .pid_NYET(  pid_NYET    ),
-        .pid_PRE(   pid_PRE     ),
-        .pid_ERR(   pid_ERR     ),
-        .pid_SPLIT( pid_SPLIT   ),
-        .pid_PING(  pid_PING    ),
-        .pid_cks_err(   pid_cs_err  ),
-        .token_fadr(    token_fadr  ),
-        .token_endp(    ep_sel      ),
-        .token_valid(   token_valid ),
-        .crc5_err(  crc5_err    ),
-        .frame_no(  frame_no    ),
-        .rx_data_st(    rx_data_st  ),
-        .rx_data_valid( rx_data_valid   ),
-        .rx_data_done(  rx_data_done    ),
-        .crc16_err( crc16_err   ),
-        .seq_err(   rx_seq_err  )
-        );
-
-// Packet Assembler
-pa  u1( .clk(       clk     ),
-        .rst(       rst     ),
-        .tx_data(   tx_data     ),
-        .tx_valid(  tx_valid    ),
-        .tx_valid_last( tx_valid_last   ),
-        .tx_ready(  tx_ready    ),
-        .tx_first(  tx_first    ),
-        .send_token(    send_token  ),
-        .token_pid_sel( token_pid_sel   ),
-        .send_data( send_data   ),
-        .data_pid_sel(  data_pid_sel    ),
-        .tx_data_st(    tx_data_st  ),
-        .rd_next(   rd_next     )
-        );
-
-// Internal DMA / Memory Arbiter Interface
-idma    u2( .clk(       clk     ),
-        .rst(       rst     ),
-        .rx_data_st(    rx_data_st  ),
-        .rx_data_valid( rx_data_valid   ),
-        .rx_data_done(  rx_data_done    ),
-        .send_data( send_data   ),
-        .tx_data_st(    tx_data_st  ),
-        .rd_next(   rd_next     ),
-        .rx_dma_en( rx_dma_en   ),
-        .tx_dma_en( tx_dma_en   ),
-        .abort(     abort       ),
-        .idma_done( idma_done   ),
-        .adr(       adr     ),
-        .size(      size        ),
-        .buf_size(  buf_size    ),
-        .dma_en(    dma_en      ),
-        .madr(      madr        ),
-        .sizu_c(    sizu_c      ),
-        .mdout(     mdout       ),
-        .mdin(      mdin        ),
-        .mwe(       mwe     ),
-        .mreq(      mreq        ),
-        .mack(      mack        )
-        );
-
-// Protocol Engine
-pe  u3( .clk(           clk         ),
-        .rst(           rst         ),
-        .tx_valid(      tx_valid_out        ),
-        .rx_active(     rx_active       ),
-        .pid_OUT(       pid_OUT         ),
-        .pid_IN(        pid_IN          ),
-        .pid_SOF(       pid_SOF         ),
-        .pid_SETUP(     pid_SETUP       ),
-        .pid_DATA0(     pid_DATA0       ),
-        .pid_DATA1(     pid_DATA1       ),
-        .pid_DATA2(     pid_DATA2       ),
-        .pid_MDATA(     pid_MDATA       ),
-        .pid_ACK(       pid_ACK         ),
-        .pid_NACK(      pid_NACK        ),
-        .pid_STALL(     pid_STALL       ),
-        .pid_NYET(      pid_NYET        ),
-        .pid_PRE(       pid_PRE         ),
-        .pid_ERR(       pid_ERR         ),
-        .pid_SPLIT(     pid_SPLIT       ),
-        .pid_PING(      pid_PING        ),
-        .mode_hs(       mode_hs         ),
-        .token_valid(       token_valid     ),
-        .crc5_err(      crc5_err        ),
-        .rx_data_valid(     rx_data_valid       ),
-        .rx_data_done(      rx_data_done        ),
-        .crc16_err(     crc16_err       ),
-        .send_token(        send_token      ),
-        .token_pid_sel(     token_pid_sel       ),
-        .data_pid_sel(      data_pid_sel        ),
-        .rx_dma_en(     rx_dma_en       ),
-        .tx_dma_en(     tx_dma_en       ),
-        .abort(         abort           ),
-        .idma_done(     idma_done       ),
-        .adr(           adr         ),
-        .size(          size            ),
-        .buf_size(      buf_size        ),
-        .sizu_c(        sizu_c          ),
-        .dma_en(        dma_en          ),
-        .fsel(          fsel            ),
-        .idin(          idin            ),
-        .ep_sel(        ep_sel          ),
-        .match(         match_o         ),
-        .dma_in_buf_sz1(    dma_in_buf_sz1      ),
-        .dma_out_buf_avail( dma_out_buf_avail   ),
-        .nse_err(       nse_err         ),
-        .buf0_rl(       buf0_rl         ),
-        .buf0_set(      buf0_set        ),
-        .buf1_set(      buf1_set        ),
-        .uc_bsel_set(       uc_bsel_set     ),
-        .uc_dpd_set(        uc_dpd_set      ),
-        .int_buf1_set(      int_buf1_set        ),
-        .int_buf0_set(      int_buf0_set        ),
-        .int_upid_set(      int_upid_set        ),
-        .int_crc16_set(     int_crc16_set       ),
-        .int_to_set(        int_to_set      ),
-        .int_seqerr_set(    int_seqerr_set      ),
-        .csr(           csr         ),
-        .buf0(          buf0            ),
-        .buf1(          buf1            )
-        );
-
-endmodule
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/hello_test.v Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/in_port.v Deleted

@@ -1,115 +0,0 @@
-/* Input port */
-// Author Andrew Laffely
-// Last modified: 12 Feb 03
-//!!!!!!!!!!!!!!!! DO NOT CHANGE THIS FILE !!!!!!!!!!!!!!!!!!!!!
-module in_port (gclock, reset, i_addr, data_in, c_addr, c_read, c_data, valid_back, ready);
-
-input gclock, reset;
-input 1:0 i_addr;      // buffer address requested by ccm
-input 1:0 c_addr;      // buffer address requested by core
-input 32:0 data_in;    // the data to be buffered from interface
-input c_read;	         // read singal from core
-
-output valid_back;       // flow control bit sent upstream to block data
-output 31:0 c_data;    // the data sent to the core
-output 2:0 ready;      // flow control, port "ready" signal, sent to core
-reg valid_back;
-reg 31:0 c_data;
-reg 2:0 ready;   
-
-reg 5:0 valid;         // contains the valid bits of the data in the port
-reg 31:0 data 5:0;   // the data in the cdm
-reg 2:0 i_addr_hold;   // hold the buf addr while evaluating
-reg 2:0 c_addr_hold;   // hold the buf addr while evaluating
-reg 2:0 i_buf_state, c_buf_state; // first or second buf in each port
-
-reg faketiming;  // Makes level sensitive transitions work properly
-initial
-begin
-	faketiming = 1'b0;
-	forever #1 faketiming = ~faketiming;
-end
-
-// *********************** INTERCONNECT *********************** //
-always @ (posedge gclock)  //interconnect side
-begin
-  if(!reset)
-    begin
-      //update valid from last transfer
-      if(!(i_addr_hold2:1 == 2'b11))  
-	begin
-	  if(!valid_back)
-	    begin
-		validi_addr_hold=data_in32;  //glitch set
-		if (data_in32)
-		   i_buf_statei_addr_hold2:1=~i_buf_statei_addr_hold2:1;
-	    end
-	end
-	#1 i_addr_hold = {i_addr,i_buf_statei_addr};
-
-	//Send data
-	if(i_addr == 2'b11)  //default no data
-	  begin
-		#1 valid_back = 0;//upstream flow control
-	  end
-	else
-	  begin
-	 	#1 valid_back = validi_addr_hold;
-		 //upstream flow control
-	  end
-    end
-end
-// ******************** END INTERCONNECT *********************** //
-
-// *************************** CORE **************************** //
-always @ (posedge c_read)
-begin
-	c_addr_hold = {c_addr, c_buf_statec_addr};
-end
-always @ (negedge c_read) //Core
-  begin
-    if(!reset)
-      begin
-	validc_addr_hold=0;  //glitch reset
-	c_buf_statec_addr_hold2:1=~c_buf_statec_addr_hold2:1;
-      end
-end
-// ************************** END CORE ************************* //
-
-always @ (faketiming)
-  begin
-    if (reset)
-      begin
-	valid = 4'b0000;
-	valid_back = 1'b0;
-	i_addr_hold = 3'b111;
-	i_buf_state=3'b000;
-	c_buf_state=3'b000;
-      end
-    else
-      begin
-	ready0=validc_buf_state0;
-	ready1=validc_buf_state1;
-	ready2=validc_buf_state2;
-
-	// ********************* Interconnect side **************** //
-	if (!gclock)
-	  begin
-		//if valid port # and not blocked store new data in port
-		if(!(i_addr_hold2:1 == 2'b11)&&(!valid_back)) 
-		  begin
-			datai_addr_hold = data_in31:0;
-		  end
-	  end
-	// ****************** End Interconnect side **************** //
-
-	// *************************** CORE ************************ //
-	if (c_read)
-	  begin
-		c_data = datac_addr_hold;
-	  end
-        // ************************ END CORE ********************** //
-  end
-end
-
-endmodule

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/inv.v Deleted

@@ -1,119 +0,0 @@
-// Verilog HDL for "gates.lib", "inv_cell" "_functional"
-// Module INV cell
-module inv_cell (d, clk, out);
-
-input
-	d, clk;
-
-output
-	out;
-reg 
-	out;
-
-parameter
-	t_hold=5,
-	t_setup=10,
-	delay=15,
-
-	warning_file=3;  // multichannel description of a warning file
-
-reg
-	d_internal, clk_internal,
-	d_state,          	   // internal state at the input d
-	d_set;		   	   // signal determining the moment when
-				   // the state of the d input changes to "1"
-
-integer
-	data_delay,  // delay between d and d_internal
-	clk_delay,   // delay between clk and clk_internal
-	out_delay,   // delay between clk_internal and out
-	out_value,   // output value in a given clock cycle
-	last_clk_time;	// time when the last clock pulse appeared
-
-initial 
-	begin
-// define delays between inputs & outputs and the corresponding
-//  internal auxiliary registers
-	  	if(t_hold<0)
-		  begin
-	    	  	data_delay = -t_hold;
-	    		clk_delay  = 0;
-			out_delay  = delay;
-		  end
-	  	else
-		  begin
-	   	  	data_delay = 0;
-	    		clk_delay  = t_hold;
-		  	out_delay  = delay-t_hold;
-		  end
-
-// clear internal registers and the output signal
-		d_internal = 0;
-		clk_internal = 0;
-		last_clk_time = 0;
-		d_state = 0;
-		d_set = 0;
-		out = 0;
-	end
-
-
-
-always @(posedge d) 	// Execute at positive edge of d
-	  d_internal <= #(data_delay) d;
-
-always @(posedge clk)  // Execute at positive edge of clk
-	  clk_internal <= #(clk_delay) clk;
-
-
-always @(posedge d_internal)
-	begin
-// setting the state of the d input
-                d_state <= d_state | 1'bx;
-		if (d_internal === 1)
-		  d_set <= #(t_hold+t_setup) 1;
-
-		d_internal <= 0;
-	end
-
-always @(posedge d_set)
-	begin
-		if ($stime - last_clk_time >= t_hold+t_setup)
-			d_state = 1;
-		else
-		  begin
-			d_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input D pulse at %0d,",
-			 $stime-data_delay-t_hold-t_setup);
-			$fwrite(warning_file,
-			"\tClock pulse at %0d.\n", last_clk_time-clk_delay);
-		  end
-
-		d_set <= 0;
-	end
-
-
-always @(posedge clk_internal)	
-	begin
-// computing the output
-		if (clk_internal === 1'bx)
-		  out_value = 1'bx;
-		else
-		  out_value = ~d_state;
-
-// transfering the result to the output
-		out <= #(out_delay) out_value;
-		out <= #(out_delay+2) 0;
-
-// clearing the internal state of the DRO
-		d_state  <= 0;
-
-		clk_internal <= 0;
-		last_clk_time = $stime;
-	end
-
-endmodule

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/inv_cell.v Deleted

@@ -1,150 +0,0 @@
-// Verilog HDL for "RSFQ.lib", "inv_cell" "_functional"
-
-// Module INV cell
-module inv_cell (d, clk, out);
-
-input
-	d, clk;
-
-output
-	out;
-reg 
-	out;
-
-parameter
-	t_hold=5,
-	t_setup=10,
-	delay=15,
-
-// multichannel description of a warning file
-	warning_file=2,  
-// multichannel description of a delay file
-	delay_file = warning_file<<1;
-
-reg
-	d_internal, clk_internal,
-	d_state,          	   // internal state at the input d
-	d_set;		   	   // signal determining the moment when
-				   // the state of the d input changes to "1"
-
-integer
-	data_delay,  // delay between d and d_internal
-	clk_delay,   // delay between clk and clk_internal
-	out_delay,   // delay between clk_internal and out
-	out_value,   // output value in a given clock cycle
-	last_clk_time,	// time when the last clock pulse appeared
-	vt_hold,	// variable hold
-	vt_setup,	// variable setup
-	vdelay;		// variable delay
-
-`include "INIT"
-
-`ifdef RANDOM_DELAYS
- `include "RANDOM_GATE"
-`endif
-
-
-initial 
-	begin
-
-		vt_hold = t_hold;
-		vt_setup = t_setup;
-		vdelay = delay;
-
-`ifdef RANDOM_DELAYS
-		delay_dev = inv_cell_variation*delay;
-		vdelay = $dist_normal(inv_cell_seed, delay, delay_dev);
-		vt_hold = $dist_normal(inv_cell_seed, t_hold, inv_hs_dev);
-		vt_setup = t_setup + (t_hold - vt_hold);
-`endif
-
-		#1 $fdisplay(delay_file, "module=%m, nom_delay=%0d, delay=%0d", delay, vdelay);
-		#1 $fdisplay(delay_file, "module=%m, nom_hold=%0d, hold=%0d", t_hold, vt_hold);
-		#1 $fdisplay(delay_file, "module=%m, nom_setup=%0d, setup=%0d", t_setup, vt_setup);
-
-
-// define delays between inputs & outputs and the corresponding
-//  internal auxiliary registers
-	  	if(vt_hold<0)
-		  begin
-	    	  	data_delay = -vt_hold;
-	    		clk_delay  = 0;
-			out_delay  = vdelay;
-		  end
-	  	else
-		  begin
-	   	  	data_delay = 0;
-	    		clk_delay  = vt_hold;
-		  	out_delay  = vdelay-vt_hold;
-		  end
-
-// clear internal registers and the output signal
-		d_internal = 0;
-		clk_internal = 0;
-		last_clk_time = 0;
-		d_state = 0;
-		d_set = 0;
-		out = 0;
-	end
-
-
-
-always @(posedge d) 	// Execute at positive edge of d
-	  d_internal <= #(data_delay) d;
-
-always @(posedge clk)  // Execute at positive edge of clk
-	  clk_internal <= #(clk_delay) clk;
-
-
-always @(posedge d_internal)
-	begin
-// setting the state of the d input
-                d_state <= d_state | 1'bx;
-		if (d_internal === 1)
-		  d_set <= #(vt_hold+vt_setup) 1;
-
-		d_internal <= 0;
-	end
-
-always @(posedge d_set)
-	begin
-		if ($stime - last_clk_time >= vt_hold+vt_setup)
-			d_state = 1;
-		else
-		  begin
-			d_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input D pulse at %0d,",
-			 $stime-data_delay-vt_hold-vt_setup);
-			$fwrite(warning_file,
-			"\tClock pulse at %0d.\n", last_clk_time-clk_delay);
-		  end
-
-		d_set <= 0;
-	end
-
-
-always @(posedge clk_internal)	
-	begin
-// computing the output
-		if (clk_internal === 1'bx)
-		  out_value = 1'bx;
-		else
-		  out_value = ~d_state;
-
-// transfering the result to the output
-		out <= #(out_delay) out_value;
-		out <= #(out_delay+2) 0;
-
-// clearing the internal state of the DRO
-		d_state  <= 0;
-
-		clk_internal <= 0;
-		last_clk_time = $stime;
-	end
-
-endmodule

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/invoke_commands_test.v Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/invoke_options_test.v Deleted

@@ -1,36 +0,0 @@
-/**************************************************************************
- * $test_invoke_options example -- Verilog test bench source code
- *
- * Verilog test bench to test the $test_invoke_options PLI application.
- *
- * NOTE: This test uses two supplemental files: invoke_options_test1.f and
- * invoke_options_test1.f.  This test is designed to be invoked as follows:
- *
- *   <simulator_name> +a +b -f invoke_options_test1.f +c
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *************************************************************************/
-`timescale 1ns / 1ns
-module test;
-  reg option_exists;
-  initial
-    begin
-      option_exists = $test_invoke_options("+test1");
-      if (option_exists)
-        $display("\nSimulation WAS invoked with a +test1 option\n");
-      else
-        $display("\nSimulation was NOT invoked with a +test1 option\n");
-
-      if ($test_invoke_options("+test2"))
-        $display("\nSimulation WAS invoked with a +test2 option\n");
-      else
-        $display("\nSimulation was NOT invoked with a +test2 option\n");
-
-      #1 $finish;
-    end
-
-endmodule

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/jtl2.v Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/jutzi Deleted

@@ -1,116 +0,0 @@
-Vic, Darren, Quentin,
-
-Prof. Jutzi from Germany has asked us for support
-in adapting their Cadence DF II to design of RSFQ circuits.
-Below are my answers to his questions.
-Could you please review my letter, and let me know
-if I omitted anything or put something wrong.
-
-Thanks a lot,
-
-Kris
-
-
-Dear Prof. Jutzi,
-
-I am very sorry for the delay in my response.
-Below are my answers to your questions.
-
-> Having in mind your recommendations during my visit in Rochester 
-> on Sept. 6, 1996 I tried to apply Cadence for superconducting 
-> circuits after my co-workers got limited access to one of the
-> Sun Sparc workstations inside the university.
-> Tentative Cadence simulations with semiconductor devices work, 
-> also in connection with Berkeley SPICE. 
-> Josephson junction models for SPICE are in operation, for
-> Cadence not yet.
-> There are still difficulties to define a Cadence symbol for Josephson
-> junctions that is understood
-> by SPICE.
-
-We do not use Cadence for simulation of digital circuits
-at the junction (circuit) level in our group.
-Simulation at this level is performed
-outside of the Cadence environment using JSPICE.
-JSPICE is a version of SPICE extended with a model 
-of Josephson junction by Steve Whiteley. 
-The version of JSPICE we use cost $1500,
-but there exists an older version which is available
-in public domain and has almost the same functionality.
-If you are interested in acquiring any of these versions
-I would be happy to provide you with the address of the
-appropriate ftp site or the contact to Steve Whiteley.
-
-Even though we perform circuit level simulations outside of 
-the Cadence environment, we still use Cadence Schematic Editor 
-to draw the schematic of the circuit.
-Creating a symbol of a Josephson junction within this editor is
-straightforward. 
-When the schematic of the circuit is ready, its netlist is generated
-using commands of the schematic editor.
-By default, the generated netlist is in the format different from the
-format accepted by JSPICE.
-We wrote a special Pearl script to translate a netlist 
-in this default Cadence notation to the JSPICE netlist.
-
-> Perhaps there is a chance to get your support to adapt Cadence DF II to
-> RSFQ-circuits.
-
-The true value of Cadence becomes appearant at other levels
-of the design process:
-
-1. Cadence is used to create the layout of the circuit.
-   Cadence Layout Editor seems to be the most convenient
-   and robust out of all layout editors we are aware off.
-
-2. Cadence is used to check the layout for violations of the 
-   design rules in the circuit.
-   To make it possible, we wrote a special technology file
-   that describes the design rules required by Hypres, Inc.
-   fabrication process. 
-   We would be happy to provide you with this file.
-
-3. Cadence is used for extracting circuit components and their values
-   from the layout and for comparing the 
-   extracted circuit schematic with the original circuit 
-   schematic (LVS - layout vs. schematic verification).
-   This process has required a special technology file to be written.
-   This file is technology-dependent (similarly as the DRC technology file).
-   We can provide you with its version corresponding to the 
-   Hypres, Inc. fabrication process.
-
-4. We use Cadence for simulation of RSFQ circuits at the gate level.
-   This is performed using Verilog-XL simulator which is a part
-   of the Cadence environment.
-   To make this simulation possible, functional models of elementary 
-   RSFQ gates (DRO, AND, XOR, adder-accumulator, etc.) were first written 
-   in Verilog HDL.
-   This models are then associated within Cadence
-   with symbols of basic gates (a symbol view and a functional view
-   are just different views of the same gate).
-   After models of basic gates are ready, simulation of large digital 
-   circuits is possible without the need for any further calibration.
-   The speed of gate level simulation is approximately
-   two orders of magnitude greater than the speed of the junction 
-   level simulation. The accuracy of modeling is sufficient
-   to verify timing violations in the circuit.
-
-In summary:
-We would be happy to help you to adapt Cadence to the design of RSFQ circuits
-by providing you with:
-1. Pearl scripts for converting regular Cadence netlist to JSPICE notation.
-2. Technology files for Design Rule Checking, Component Extraction &
-   Layout vs. Schematic Verification.
-3. Verilog models of basic RSFQ gates.
-
-How much changes you would need to introduce to technology files (2.)
-to make your Cadence environment operational depends mainly on how 
-different the process you use is from the Hypres, Inc. fabrication 
-process.
-   
-I hope this information will be helpful in determining your
-further calibration steps.
-
-With best regards,
-
-Kris Gaj

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/list_cells_test.v Deleted

@@ -1,140 +0,0 @@
-/**********************************************************************
- * $list_cells example -- Verilog test bench source code
- *
- * Verilog test bench to test the $list_cells PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-
-/**********************************************************************
- * Top-level test bench module for a 4-bit adder model.
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-  reg    3:0 a, b;
-  wire   3:0 sum;
-  reg          ci;
-  wire         co;
-
-  add4 i1 (a, b, ci, sum, co);
-
-  initial
-    begin
-      #1 $list_cells(i1);
-      #1 $finish;
-    end
-endmodule
-
-/**********************************************************************
- * 4-bit adder model, using a 1-bit adder model.
- *********************************************************************/
-`timescale 1ns / 1ns
-module add4 (a, b, ci, sum, co);
-  input  3:0 a, b;
-  input        ci;
-  output 3:0 sum;
-  output       co;
-
-  wire   3:0 a, b, sum;
-  wire         ci, co, co1, co2, co3;
-
-  addbit  a1  (a0, b0, ci,  sum0, co1);
-  addbit  a2  (a1, b1, co1, sum1, co2);
-  addbit  a3  (a2, b2, co2, sum2, co3);
-  addbit  a4  (a3, b3, co3, sum3, co );
-
-endmodule
-
-/**********************************************************************
- * 1-bit adder model, using cells from a library.
- *********************************************************************/
-`timescale 1ns / 1ns
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci, sum, co,
-        n1, n2, n3;
-
-  xor2  u1  (n1, a, b);
-  xor2  u2  (sum, n1, ci);
-  and2  u3  (n2, a, b);
-  and2  u4  (n3, n1, ci);
-  or2   u5  (co, n2, n3);
-
-endmodule
-/**********************************************************************
-* Cell library
- *********************************************************************/
-`resetall
-`celldefine
-`timescale 1ns / 10ps
-module or2 (y, a, b);
-  output y;
-  input  a, b;
-  wire   y, a, b;  //wire data type for cmos
-  or    (y, a, b);
-  specify
-    (a *> y) = 1.0;
-    (b *> y) = 1.0;
-    specparam BaseDelay$   = 2.5;
-    specparam InputLoad$a  = 0.3;
-    specparam InputLoad$b  = 0.3;
-    specparam InputLoad$c  = 0.3;
-    specparam in_cap_pf$a  = 0.02;
-    specparam in_cap_pf$b  = 0.02;
-    specparam in_cap_pf$c  = 0.02;
-    specparam out_cap_pf$  = 0.05;
-  endspecify
-endmodule
-`endcelldefine
-/*********************************************************************/
-`resetall
-`celldefine
-`timescale 1ns / 10ps
-module xor2 (y, a, b);
-  output y;
-  input  a, b;
-  wire   y, a, b;  //wire data type for cmos
-  xor   (y, a, b);
-  specify
-    (a *> y) = 1.0;
-    (b *> y) = 1.0;
-    specparam BaseDelay$   = 2.5;
-    specparam InputLoad$a  = 0.3;
-    specparam InputLoad$b  = 0.3;
-    specparam InputLoad$c  = 0.3;
-    specparam in_cap_pf$a  = 0.02;
-    specparam in_cap_pf$b  = 0.02;
-    specparam in_cap_pf$c  = 0.02;
-    specparam out_cap_pf$  = 0.05;
-  endspecify
-endmodule
-`endcelldefine
-/*********************************************************************/
-`resetall
-`celldefine
-`timescale 1 ns / 10 ps
-module and2 (y, a, b);
-  output y;
-  input  a, b;
-  wire   y, a, b;  //wire data type for cmos
-  and   (y, a, b);
-  specify
-    (a *> y) = 1.0;
-    (b *> y) = 1.0;
-    specparam BaseDelay$   = 2.5;
-    specparam InputLoad$a  = 0.2;
-    specparam InputLoad$b  = 0.2;
-    specparam in_cap_pf$a  = 0.02;
-    specparam in_cap_pf$b  = 0.02;
-    specparam out_cap_pf$  = 0.05;
-  endspecify
-endmodule
-`endcelldefine
-/*********************************************************************/
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/list_nets_test.v Deleted

@@ -1,48 +0,0 @@
-/**********************************************************************
- * $list_nets example -- Verilog test bench source code
- *
- * Verilog test bench to test the $list_nets PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module top;
-  reg  2:0 test;
-  wire 2:0 results;
-
-  addbit i1 (test0, test1, test2, results0, results1);
-
-  initial
-    begin
-      test = 3'b000;
-      #10 test = 3'b001;
-
-      #10 $list_nets(top);
-      #10 $list_nets(i1);
-
-      #10 $finish;
-    end
-endmodule
-
-/*** A gate level 1 bit adder model ***/
-`timescale 1ns / 1ns
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci, sum, co, n1, n2, n3;
-  wire  3:0 foo = 4'bXZ10;
-
-  xor    (n1, a, b);
-  xor #2 (sum, n1, ci);
-  and    (n2, a, b);
-  and    (n3, n1, ci);
-  or  #2 (co, n2, n3);
-
-endmodule
-/*********************************************************************/
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/list_parameters_test.v Deleted

@@ -1,48 +0,0 @@
-/**********************************************************************
- * $list_parameters example -- Verilog test bench source code
- *
- * Verilog test bench to test the $list_parameters PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module top;
-  reg  2:0 test;
-  wire 1:0 results;
-
-  addbit i1 (test0, test1, test2, results0, results1);
-
-  initial
-    begin
-      #1 $list_parameters(i1);
-      #1 $finish;
-    end
-endmodule
-
-/*** A gate level 1 bit adder model ***/
-`timescale 1ns / 10ps
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  parameter int_param = 1;
-  parameter real_param = 2.0;
-  parameter string_param = "3.0";
-  parameter 3:0 vector_param = 4'b01zx;
-  
-  wire  a, b, ci, sum, co, n1, n2, n3, n4;
-  wire  3:0 foo = 4'bXZ10;
-
-  xor #1.87       p1 (n1, a, b);    // all transitions have same delay
-  xor #(1.8, 2.2) p2 (sum, n1, ci); //rise, fall delays
-  and             p3 (n2, a, b);
-  and             p4 (n3, n1, ci);
-  or  #4          p5 (co, n2, n3);  //integer delay
-
-endmodule
-/*********************************************************************/
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/list_path_delays_test.v Deleted

@@ -1,50 +0,0 @@
-/**********************************************************************
- * $list_path_delays example -- Verilog test bench source code
- *
- * Verilog test bench to test the $list_path_delays PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module top;
-  reg  2:0 test;
-  wire 1:0 results;
-
-  addbit i1 (test0, test1, test2, results0, results1);
-
-  initial
-    begin
-      #1 $list_path_delays(i1);
-      #1 $finish;
-    end
-endmodule
-
-/*** A gate level 1 bit adder model ***/
-`timescale 1ns / 10ps
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci, sum, co, n1, n2, n3, n4;
-  wire  3:0 foo = 4'bXZ10;
-
-  xor    p1 (n1, a, b);    // all transitions have same delay
-  xor    p2 (sum, n1, ci); //rise, fall delays
-  and    p3 (n2, a, b);
-  and    p4 (n3, n1, ci);
-//  or     p5 (co, n2, n3);  //integer delay
-  bufif1 p6 (co, n2, 1'b0); //all delay values
-
-  specify
-    (a *> sum) = 3.1415;
-    (b *> sum) = (1:2:3, 4:5:6, 7:8:9);
-    (ci *> sum, co) = (1, 2, 3, 4, 5, 6);
-  endspecify
-
-endmodule
-/*********************************************************************/
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/list_pathout_ports_test.v Deleted

@@ -1,58 +0,0 @@
-/**********************************************************************
- * $list_pathout_ports example -- Verilog test bench source code
- *
- * Verilog test bench to test the $list_pathout_ports PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-  reg  a, b, ci, clk;
-  wire sum, co, foo;
-
-  addbit i1 (a, b, ci, sum, co, foo);
-
-  initial
-    begin
-      $monitor("At %0d: \t a=%b  b=%b  ci=%b  sum=%b  co=%b",
-               $time, a, b, ci, sum, co);
-      clk = 0;
-      a = 0;
-      b = 0;
-      ci = 0;
-      #10 a = 1;
-      #10 b = 1;
-
-      #10 $list_pathout_ports(i1);
-
-      #10 $finish;
-    end
-endmodule
-
-/*** A gate level 1 bit adder model ***/
-`timescale 1ns / 1ns
-module addbit (a, b, ci, sum, co, foo);
-  input  a, b, ci;
-  output sum, co, foo;
-
-  wire  a, b, ci, sum, co, foo,
-        n1, n2, n3;
-
-  xor    (n1, a, b);
-  xor    (sum, n1, ci);
-  and    (n2, a, b);
-  and    (n3, n1, ci);
-  or     (co, n2, n3);
-
-  specify
-    (a,b,ci => sum) = 2;
-    (a,b,ci => co)  = 3;
-  endspecify
-
-endmodule
-/*********************************************************************/
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/list_prim_delays_test.v Deleted

@@ -1,45 +0,0 @@
-/**********************************************************************
- * $list_prim_delays example -- Verilog test bench source code
- *
- * Verilog test bench to test the $list_prim_delays PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module top;
-  reg  2:0 test;
-  wire 1:0 results;
-
-  addbit i1 (test0, test1, test2, results0, results1);
-
-  initial
-    begin
-      #1 $list_prim_delays(i1);
-      #1 $finish;
-    end
-endmodule
-
-/*** A gate level 1 bit adder model ***/
-`timescale 1ns / 10ps
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci, sum, co, n1, n2, n3, n4;
-  wire  3:0 foo = 4'bXZ10;
-
-  xor #1.87       p1 (n1, a, b);    // all transitions have same delay
-  xor #(1.8, 2.2) p2 (sum, n1, ci); //rise, fall delays
-  and             p3 (n2, a, b);
-  and             p4 (n3, n1, ci);
-  or  #4          p5 (co, n2, n3);  //integer delay
-  
-  bufif1 #(1:2:3, 4:5:6, 7:8:9) p6 (n4, n2, n3); //all delay values
-
-endmodule
-/*********************************************************************/
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/load_in.v Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/load_out.v Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/mem_arb.v Deleted

@@ -1,179 +0,0 @@
-/////////////////////////////////////////////////////////////////////
-////                                                             ////
-////  Memory Buffer Arbiter                                      ////
-////  Arbitrates between the internal DMA and external bus       ////
-////  interface for the internal buffer memory                   ////
-////                                                             ////
-////  Author: Rudolf Usselmann                                   ////
-////          rudi@asics.ws                                      ////
-////                                                             ////
-////                                                             ////
-////  Downloaded from: http://www.opencores.org/cores/usb/       ////
-////                                                             ////
-/////////////////////////////////////////////////////////////////////
-////                                                             ////
-//// Copyright (C) 2000 Rudolf Usselmann                         ////
-////                    rudi@asics.ws                            ////
-////                                                             ////
-//// This source file may be used and distributed without        ////
-//// restriction provided that this copyright statement is not   ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer.////
-////                                                             ////
-////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
-//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
-//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
-//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
-//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
-//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
-//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
-//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
-//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
-//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
-//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
-//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
-//// POSSIBILITY OF SUCH DAMAGE.                                 ////
-////                                                             ////
-/////////////////////////////////////////////////////////////////////
-
-//  CVS Log
-//
-//  $Id: mem_arb.v,v 1.0 2001/03/07 09:17:12 rudi Exp $
-//
-//  $Date: 2001/03/07 09:17:12 $
-//  $Revision: 1.0 $
-//  $Author: rudi $
-//  $Locker:  $
-//  $State: Exp $
-//
-// Change History:
-//               $Log: mem_arb.v,v $
-//               Revision 1.0  2001/03/07 09:17:12  rudi
-//
-//
-//               Changed all revisions to revision 1.0. This is because OpenCores CVS
-//               interface could not handle the original '0.1' revision ....
-//
-//               Revision 0.1.0.1  2001/02/28 08:10:52  rudi
-//               Initial Release
-//
-//
-
-`include "usb_defines.v"
-
-module mem_arb(	phy_clk, wclk, rst,
-
-		// SSRAM Interface
-		radr, rdin, rdout, rre, rwe,
-
-		// IDMA Memory Interface
-		madr, mdout, mdin, mwe, mreq, mack,
-
-		// WISHBONE Memory Interface
-		wadr, wdout, wdin, wwe, wreq, wack
-
-		);
-
-input		phy_clk, wclk, rst;
-
-output	14:0	radr;
-input	31:0	rdin;
-output	31:0	rdout;
-output		rre, rwe;
-
-input	14:0	madr;
-output	31:0	mdout;
-input	31:0	mdin;
-input		mwe;
-input		mreq;
-output		mack;
-
-input	14:0	wadr;
-output	31:0	wdout;
-input	31:0	wdin;
-input		wwe;
-input		wreq;
-output		wack;
-
-///////////////////////////////////////////////////////////////////
-//
-// Local Wires and Registers
-//
-
-wire		wsel;
-reg	14:0	radr;
-reg	31:0	rdout;
-reg		rwe;
-reg		mack;
-reg		mack_r;
-wire		mcyc;
-reg		wack;
-wire		wcyc;
-reg		wwe_r;
-
-///////////////////////////////////////////////////////////////////
-//
-// Memory Arbiter Logic
-//
-
-// IDMA has always first priority
-
-// -----------------------------------------
-// Ctrl Signals
-
-assign wsel = (wreq | wcyc) & !mreq;
-
-// -----------------------------------------
-// SSRAM Specific
-// Data Path
-always @(wsel or wdin or mdin)
-	if(wsel)	rdout = wdin;
-	else		rdout = mdin;
-
-// Address Path
-always @(wsel or wadr or madr)
-	if(wsel)	radr = wadr;
-	else		radr = madr;
-
-// Write Enable Path
-always @(wsel or wwe_r or mwe or mcyc or wcyc)
-	if(wsel)	rwe = wwe_r & wcyc;
-	else		rwe = mwe & mcyc;
-
-assign rre = 1;
-
-// -----------------------------------------
-// IDMA specific
-assign mdout = rdin;
-
-always @(mreq)
-	mack = mreq;
-
-always @(posedge phy_clk)
-	mack_r <= #1 mack;
-
-assign mcyc = mack;	// Qualifier for writes
-
-// -----------------------------------------
-// WISHBONE specific
-assign wdout = rdin;
-
-reg	wack_d, wack_r;
-
-always @(wack_d or mreq)
-	wack = wack_d & !mreq;
-
-always @(posedge phy_clk)
-	wack_r <= #1 wack_d;
-
-always @(wreq or mreq)
-	if(!mreq)	wack_d = wreq;
-	else		wack_d = 0;
-
-always @(posedge phy_clk)
-	wwe_r <= #1 wwe;
-
-assign wcyc = wack_d | wack_r;	// Qualifier for writes
-
-endmodule
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/mipd_delays_test.v Deleted

@@ -1,42 +0,0 @@
-/**********************************************************************
- * $append_gate_delays example -- Verilog test bench source code
- *
- * Verilog test bench to test the $append_gate_delays PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 100ps
-module top;
-  reg  2:0 test;
-  wire 1:0 results;
-
-  addbit i1 (test0, test1, test2, results0, results1);
-
-  initial
-    begin
-      $mipd_delays(i1.ci, 1.4, 1.6, 1.9, 1.1, 1.3, 1.5, 0.6, 0.8, 0.9);
-      #1 $finish;
-    end
-endmodule
-
-/*** A gate level 1 bit adder model ***/
-`timescale 1ns / 10ps
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci, sum, co, n1, n2, n3, n4;
-
-  xor #1.87       p1 (n1, a, b);    // all transitions have same delay
-  xor #(1.8, 2.2) p2 (sum, n1, ci); //rise, fall delays
-  and             p3 (n2, a, b);
-  and             p4 (n3, n1, ci);
-  or  #4          p5 (co, n2, n3);  //integer delay
-  
-endmodule
-/*********************************************************************/
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/mult16.v Deleted

@@ -1,147 +0,0 @@
-// **** Here's a simple, sequential multiplier.  Very simple, unsigned..
-// Not very well tested, play with testbench, use at your own risk, blah blah blah..
-//
-
-//
-// Unsigned 16-bit multiply (multiply two 16-bit inputs to get a 32-bit output)
-//
-// Present data and assert start synchronous with clk.
-// Assert start for ONLY one cycle.
-// Wait N cycles for answer (at most).  Answer will remain stable until next start.
-// You may use DONE signal as handshake.
-//
-// Written by tom coonan
-//
-module mult16 (clk, resetb, start, done, ain, bin, yout);
-parameter N = 16;
-input			clk;
-input			resetb;
-input			start; // Register the ain and bin inputs (they can change afterwards)
-input N-1:0		ain;
-input N-1:0		bin;
-output 2*N-1:0	yout;
-output			done;
-
-reg 2*N-1:0		a;
-reg N-1:0		b;
-reg 2*N-1:0		yout;
-
-reg		done;
-
-always @(posedge clk or negedge resetb) begin
-   if (~resetb) begin
-      a <= 0;
-      b <= 0;
-      yout <= 0;
-      done <= 1'b1;
-   end
-   else begin
-      // Load will register the input and clear the counter.
-      if (start) begin
-         a    <= ain;
-         b    <= bin;
-         yout <= 0;
-         done <= 0;
-      end
-      else begin
-         // Go until b is zero
-         if (~done) begin
-            if (b != 0) begin
-               // If '1' then add a to sum
-               if (b0) begin
-                  yout <= yout + a;
-               end
-               b <= b >> 1;
-               a <= a << 1;
-               //$display ("a = %b, b = %b, yout = %b", a,b,yout);
-            end
-            else begin
-               done <= 1'b1;
-            end
-         end
-      end
-   end
-end
-endmodule
-
-// synopsys translate_off
-//`define TESTMULT16
-`ifdef TESTMULT16
-
-module testmult16;
-reg clk, resetb, start;
-reg 15:0 a;
-reg 15:0 b;
-wire 31:0 y;
-wire done;
-
-mult16 mult16inst (clk, resetb, start, done, a, b, y);
-
-initial begin
-   clk = 0;
-   forever begin
-      #10 clk = ~clk;
-   end
-end
-
-initial begin
-   resetb = 0;
-   #30 resetb = 1;
-end
-
-integer num_errors;
-parameter MAX_TRIALS = 1000;
-
-initial begin
-   $dumpfile ("multdiv.vcd");
-   $dumpvars (0,testmult16);   
-   num_errors = 0;
-
-   #100;
-
-   // Do a bunch of random multiplies
-   repeat (MAX_TRIALS) begin
-      test_multiply ($random, $random);
-   end
-   
-   // Special cases
-   test_multiply ($random, 1);
-   test_multiply (1, $random);
-   test_multiply ($random, 0);
-   test_multiply (0, $random);
-   
-   $display ("Done.  %0d Errors", num_errors);
-   #800;
-   $finish;
-end
-
-task test_multiply;
-   input 15:0 aarg;
-   input 15:0 barg;
-   
-   integer expected_answer;
-   
-   begin
-      if (~done) begin
-         $display ("Multiplier is Busy!!");
-      end
-      else begin
-         @(negedge clk);
-         start = 1;
-         a = aarg;
-         b = barg;
-         @(negedge clk) start = 0;
-         @(posedge done); 
-         expected_answer = a*b;
-         $display ("%0d * %0d = %0h, Reality = %0h", a, b, y, expected_answer);
-         if (y !== expected_answer) begin
-            $display ("   FAILURE!");
-            num_errors = num_errors + 1;
-         end
-      end
-   end
-endtask
-
-endmodule
-`endif
-     
\ No newline at end of file

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/multi21_udp.v Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/my_monitor1_test.v Deleted

@@ -1,38 +0,0 @@
-/**********************************************************************
- * $my_monitor1 example -- Verilog test bench source code
- *
- * Verilog test bench to test the $my_monitor1 PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-
-  reg 3:0 q, d;
-  reg clock;
-  
-  initial
-    $my_monitor1(clock, q, d);
-    
-  always @(posedge clock)
-    q <= #1 d;
-    
-  initial
-    begin
-      clock = 0;
-      forever #5 clock = ~ clock;
-    end
-  
-  initial
-    begin
-      d = 4'h0;
-      @(negedge clock) d = 4'h1;
-      @(negedge clock) d = 4'hF;
-      @(negedge clock) $finish;
-    end
-endmodule
-      
\ No newline at end of file

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/my_monitor2_test.v Deleted

@@ -1,38 +0,0 @@
-/**********************************************************************
- * $my_monitor2 example -- Verilog test bench source code
- *
- * Verilog test bench to test the $my_monitor1 PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-
-  reg 3:0 q, d;
-  reg clock;
-  
-  initial
-    $my_monitor2(clock, q, d);
-    
-  always @(posedge clock)
-    q <= #1 d;
-    
-  initial
-    begin
-      clock = 0;
-      forever #5 clock = ~ clock;
-    end
-  
-  initial
-    begin
-      d = 4'h0;
-      @(negedge clock) d = 4'h1;
-      @(negedge clock) d = 4'hF;
-      @(negedge clock) $finish;
-    end
-endmodule
-      
\ No newline at end of file

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/my_monitor_test.v Deleted

@@ -1,45 +0,0 @@
-/**********************************************************************
- * $my_monitor example -- Verilog test bench source code
- *
- * Verilog test bench to test the $my_monitor PLI application on
- * a 1-bit adder modeled using RTL code.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module top;
-  integer    test;
-  tri  1:0 results;
-
-  addbit i1 (test0, test1, test2, results0, results1);
-
-  initial
-    begin
-      $my_monitor(results0);
-      $my_monitor(i1.sum, i1.co);
-      test = 3'b000;
-      #10 test = 3'b001;
-      #10 test = 3'b011;
-      #10 $finish;
-    end
-endmodule
-
-/*** An RTL level 1 bit adder model ***/
-`timescale 1ns / 1ns
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci;
-  reg   sum, co;
-
-  always @(a or b or ci)
-    {co, sum} = a + b + ci;
-
-endmodule
-/*********************************************************************/
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/my_strobe_test.v Deleted

@@ -1,75 +0,0 @@
-/**********************************************************************
- * $my_strobe example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $my_strobe PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-  reg  a, b, ci, clk;
-  reg  sum, co;
-
-  always @(a or b or ci)
-    {co,sum} = a + b + ci;
-
-  initial
-    begin
-      $strobe ("$strobe   : At %0d: \t %m.sum = %d",$time, sum);
-      $display("$display  : At %0d: \t %m.sum = %d",$time, sum);
-      $my_strobe(sum);
-      a = 0; b = 0; ci = 0;
-
-      #10 $display("");
-      a = 1;
-      $my_strobe(sum);
-      $strobe ("$strobe   : At %0d: \t %m.sum = %d",$time, sum);
-      $display("$display  : At %0d: \t %m.sum = %d",$time, sum);
-      
-      #10 $display("");
-      a = 0;
-      $my_strobe(sum);
-      $display("$display  : At %0d: \t %m.sum = %d",$time, sum);
-      $strobe ("$strobe   : At %0d: \t %m.sum = %d",$time, sum);
-
-      #10 $display("");
-      b = 1;
-      $strobe ("$strobe   : At %0d: \t %m.sum = %d",$time, sum);
-      $my_strobe(sum);
-      $display("$display  : At %0d: \t %m.sum = %d",$time, sum);
-      a = 1;
-      $my_strobe(sum);
-      $strobe ("$strobe   : At %0d: \t %m.sum = %d",$time, sum);
-      $display("$display  : At %0d: \t %m.sum = %d",$time, sum);
-
-      #10 $display("");
-      $finish;
-    end
-
-  initial
-      $monitor("$monitor  : At %0d: \t %m.sum = %d",$time, sum);
-  
-endmodule
-
-/*** A gate level 1 bit adder model ***/
-`timescale 1ns / 1ns
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci, sum, co,
-        n1, n2, n3;
-
-  xor    (n1, a, b);
-  xor    (sum, n1, ci);
-  and    (n2, a, b);
-  and    (n3, n1, ci);
-  or     (co, n2, n3);
-
-endmodule
-/*********************************************************************/
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/myram64x16.v Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/nco.v Deleted

@@ -1,244 +0,0 @@
-//
-// NCO Demo (Numerically controlled Oscillator).
-//
-// One type of NCO is based on the idea of a continuously wrapping modulo
-// counter.  The NCO is a programmable modulo counter.  For example, if
-// the MOD input is set to 10, then it'll count 0,1,2,3,4,5,6,7,8,9,0,1,2 etc.
-// The STEP input is continuously added to the modulo counter.  What's important
-// is not the counter value itself, but the number of times it "wraps".  If
-// you do the math, the counter will wrap at a rate of F*S/M (F is the system
-// clock frequency, S is the step input, and M is the modulo).  Every wrap
-// occurance is a little pulse.  The pulse output could be used as the clock itself
-// except that it may have a very small duty cycle.  Instead, take the WRAP
-// pulse signal and use it to increment a TICKS counter.  The TICKS counter will
-// then count at the programmed frequency.
-//
-// The TICK counter could be used in itself for, say, a TDMA slot counter.  Any
-// number of TICKS LSB bits can be thrown away to "reduce jitter" but also
-// reduce the rate.  This NCO has a little MASK input and an internal OR gate
-// so you can pick off whichever TICKS bits you wish for your final FOUT output.
-//
-// In an open-loop mode, you program your Modulo and Step inputs and you are done.
-// If you are tracking some other reference (e.g. like in a PLL style circuit) you
-// would somehow control STEP via some sort of "phase detector" and loop filter.
-// None of this is shown here.
-//
-// Anyway, this is just the guts of the NCO, which can be applied in many, many
-// ways.
-//
-// Oh.. And this NCO seems to be off by a small percentage..?!..  I'm not sure
-// why.  It may be the circuit or the testbench.  Let me know if you play with it
-// and find out.  My application is closed-loop, so, I'm not highly motivated
-// to figure it out.
-//
-// Written by tom coonan
-//
-module nco (
-   clk,
-   resetb,
-   step,	// Step input is continuously added to the modulo counter
-   mod,		// modulo
-   mask,	// Mask is ANDed with ticks and gen ORed to produce fout
-   ticks,	// Tick counter output
-   fout		// Output.
-);
-
-parameter W_ACCUM = 24; // Width of the Accumulator
-parameter W_TICK  = 8; // Width of the Tick counter.
-parameter W_STEP  = 24;
-parameter W_MOD   = 24;
-
-input			clk;
-input			resetb;
-input W_STEP-1:0	step;
-input W_MOD-1:0	mod;
-input W_TICK-1:0	mask;
-output W_TICK-1:0	ticks;
-output			fout;
-
-// Registered outputs
-
-// Internals
-reg W_ACCUM-1:0	accum, accum_in;
-reg W_TICK-1:0	ticks;
-
-// *** Modulo Counter ***
-// Registered outputs
-reg		wrap;
-
-wire W_ACCUM-1:0	sum = accum + step;
-wire W_ACCUM-1:0	rem = sum - mod;
-wire			over = (sum >= mod);
-
-always @(posedge clk or negedge resetb)
-   if (~resetb) accum <= 0;
-   else         accum <= accum_in;
-   
-always @(over or rem or sum) begin
-   if (over) begin
-      // Wrap!
-      accum_in <= rem; // load remainder instead of sum
-      wrap <= 1;
-   end
-   else begin
-      // No wrap, just add
-      accum_in <= sum;
-      wrap <= 0;
-   end
-end
-
-// *** Tick Counter ***
-//
-always @(posedge clk) begin
-   if (~resetb) ticks <= 0;
-   else begin
-      // Whenever Modulo counter wraps, increment the tick counter.
-      if (wrap) 
-         ticks <= ticks + 1;
-   end
-end
-
-// *** Masks and final output *** //
-
-assign fout = |(ticks & mask);
-
-endmodule
-
-module ncotest;
-
-reg		clk;
-reg		resetb;
-reg 23:0	step;
-reg 23:0	mod;
-reg 7:0	mask;
-wire		fout;
-wire 7:0	ticks;	
-
-parameter W_ACCUM = 24; // Width of the Accumulator
-parameter W_TICK  = 8; // Width of the Tick counter.
-parameter W_STEP  = 24;
-parameter W_MOD   = 24;
-
-nco nco1 (
-   .clk(clk),
-   .resetb(resetb),
-   .step(step),
-   .mod(mod),
-   .mask(mask),
-   .fout(fout),
-   .ticks(ticks)
-);
-
-parameter PERIOD_NS = 36;
-parameter DUMP_ON = 1;
-
-real	sys_freq;
-
-initial begin
-   step = 0;
-   mod = 0;
-   mask = 8'b00000001; // Final Divider for FOUT
-   
-   sys_freq = 1000000000.0/(PERIOD_NS);
-   
-   #300;
-
-   // Display the basic such as system clock frequency, etc.
-   //
-   $display ("NCO Test.  NCO Accumulator width is %0d bits, system clock period is %0d ns (%fMHz).",
-      W_ACCUM,
-      PERIOD_NS,
-      sys_freq
-   );
-   
-   // Program Modulo and Step for desired frequency.  Modulo and Step values should
-   // not be divisible by each other (I'm not mathematically strong enough to
-   // justify this...).  Find the ratio of S/M, integerize it, and reduce to lowest
-   // common divisors.  Then, multiply up by a big power of 2 so we can get some
-   // resolution on the NCO.
-   // 
-   
-   // Let's generate 1Mhz, Fsys*(Step/Mod)/2 = 27777777.777*(S/M)/2 = 1000000
-   //    S/M = 0.072 = 72/1000 = 9/125 (9 * 2^12) / (125 * 2^12)
-   //
-   mod  = 125 << 12; // Shift up so we get resolution..
-   step =   9 << 12; // Shift up so we get resolution..
-   nco_test (mod, step, 1000000); // Run test for specified interval (units are NS)
-   
-   // Generate 10.24MHz: Fsys*(Step/Mod)/2 = 27777777.777*(S/M)/2 = 10240000
-   //    S/M = 0.73728 = 73728/100000 = 9216/12500 = 4608/6250 = 2304/3125
-   //
-   mod  = 3125 << 10; // Shift up so we get resolution..
-   step = 2304 << 10; // Shift up so we get resolution..
-   nco_test (mod, step, 1000000); // Run test for specified interval (units are NS)
-   
-   // Generate 32.768 KHz using TICKS MSB (divide by 8): 
-   //    Fsys*(Step/Mod) = 27777777.777*(S/M) = 32768*256
-   //    S/M = 0.301989888 =~ 0.302 = 302/1000 = 151/500
-   //
-   mask = 8'b10000000; // Divide by 256
-   mod  = 500 << 12;
-   step = (151 << 12) - 9566;  // Manually Tweaked this to get the right number..
-                               // this is expected since didn't have a good integer
-                               // ratio above..
-   nco_test (mod, step, 1000000); // Run test for specified interval (units are NS)
-      
-   $display ("Done.");
-   
-   $finish;
-end
-
-// Run a single trial of the NCO test.
-//   
-task nco_test;
-   input 23:0 mod_arg;
-   input 23:0 step_arg;
-   input	interval;
-   
-   integer	interval;   // Use $time..  Make sure timescale is correct!
-   integer	start_time;
-   integer	fout_edges;
-   
-   begin
-      step = step_arg; // Configure NCO
-      mod  = mod_arg;
-      
-      // Count rising edges on FOUT which is the output frequency
-      fout_edges = 0;
-      start_time = $time; // Note our starting time
-      // Loop for at least the specified amount of time
-      while ( ($time - start_time) < interval) begin
-         @(posedge fout); // Wait for an edge on FOUT
-         fout_edges = fout_edges + 1;
-      end
-      
-      // Done.  Display results and expected results.
-      $display ("For Mod=%0d(0x%h), Step=%0d(0x%h), Frequency of fout = %f Hz, Expected fout is %f Hz.",
-         mod, mod,
-         step, step,
-         ((fout_edges*1.0)/($time - start_time))*1000000000.0, // measured..
-         ((step*1.0)/(mod*1.0))*(sys_freq)/(mask*2.0)   // expected..
-      );
-   end
-endtask
-
-// Let's clock it at about 27 MHz
-initial begin
-   clk = 0;
-   forever begin
-      #(PERIOD_NS/2) clk = ~clk;
-   end
-end
-
-initial begin
-   resetb = 0;
-   #200 resetb = 1;
-end
-
-initial begin
-   if (DUMP_ON) begin
-      $dumpfile ("nco.vcd");
-      $dumpvars (0,ncotest);   
-   end
-end
-endmodule

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/ndro.v Deleted

@@ -1,149 +0,0 @@
-// Verilog HDL for "RSFQ.lib", "ndro_cell" "_functional"
-// Module NDRO cell
-
-module ndro_cell (on, off, sig, out, dout);
-
-input
-	on, off, sig;
-
-output
-	out, dout;
-reg 
-	out, dout;
-
-parameter
-	off_sig_hold	= -3,
-	off_sig_setup	= 8,
-	on_sig_hold	= 10,
-	on_sig_setup	= 7,
-	on_off_hold	= 6,
-	on_off_setup	= 10,
-	sig_out_delay	= 12,
-	off_dout_delay  = 10,
-
-	warning_file=3;  // multichannel description of a warning file
-
-reg
-	on_internal, off_internal, sig_internal,
-	ndro_state,          	   // internal state
-	d_set;		   	   // signal determining the moment when
-				   // the state of the d input changes to "1"
-
-integer
-	data_delay,  // delay between d and d_internal
-	clk_delay,   // delay between clk and clk_internal
-	out_delay,   // delay between clk_internal and out
-	out_value,   // output value in a given clock cycle
-	last_clk_time;	// time when the last clock pulse appeared
-
-initial 
-	begin
-// define delays between inputs & outputs and the corresponding
-//  internal auxiliary registers
-	  	if(t_hold<0)
-		  begin
-	    	  	data_delay = -t_hold;
-	    		clk_delay  = 0;
-			out_delay  = delay;
-		  end
-	  	else
-		  begin
-	   	  	data_delay = 0;
-	    		clk_delay  = t_hold;
-		  	out_delay  = delay-t_hold;
-		  end
-
-// clear internal registers and the output signal
-		d_internal = 0;
-		clk_internal = 0;
-		last_clk_time = 0;
-		d_state = 0;
-		d_set = 0;
-		out = 0;
-	end
-
-
-
-always @(posedge on) 	// Execute at positive edge of on
-	  on_internal <= #(data_delay) on;
-
-always @(posedge off)  // Execute at positive edge of off
-	  off_internal <= #(clk_delay) off;
-
-always @(posedge sig)  // Execute at positive edge of sig
-	  sig_internal <= #(clk_delay) sig;
-
-
-always @(posedge on_internal)
-	begin
-                ndro_state <= ndro_state | 1'bx;
-		if (on_internal === 1)
-		  on_sig_set <= #(on_sig_hold+on_sig_setup) 1;
-
-		on_internal <= 0;
-	end
-
-always @(posedge on_set)
-	begin
-		if ($stime - last_sig_time >= on_sig_hold+on_sig_setup)
-			ndro_state = 1;
-		else
-		  begin
-			ndro_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input ON pulse at %0d,",
-			 $stime-data_delay-t_hold-t_setup);
-			$fwrite(warning_file,
-			"\tSIG pulse at %0d.\n", last_clk_time-clk_delay);
-		  end
-
-		on_set <= 0;
-	end
-
-
-always @(posedge sig_internal)	
-	begin
-// computing the output
-		if (sig_internal === 1'bx)
-		  out_value = 1'bx;
-		else
-		  out_value = ndro_state;
-
-// transfering the result to the output
-		out <= #(out_delay) out_value;
-		out <= #(out_delay+2) 0;
-
-                ndro_state <= ndro_state | 1'bx;
-		if (sig_internal === 1)
-		  sig_off_set <= #(sig_off_hold+sig_off_setup) 1;
-
-		sig_internal <= 0;
-		last_sig_time = $stime;
-	end
-
-
-always @(posedge off_internal)	
-	begin
-// computing the output
-		if (off_internal === 1'bx)
-		  out_value = 1'bx;
-		else
-		  out_value = ndro_state;
-
-// transfering the result to the output
-		out <= #(out_delay) out_value;
-		out <= #(out_delay+2) 0;
-
-// clearing the internal state of the NDRO
-		ndro_state  <= 0;
-
-		off_internal <= 0;
-		last_off_time = $stime;
-	end
-
-
-endmodule

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/new/count_bits.v Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/new/count_bits8.v Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/new/exampleresults.txt Deleted

@@ -1,112 +0,0 @@
-
-    
-        'module', 'test', '(', 
-            
-                'a', 'b', 'd'
-            , ')', ';'
-        , 
-        
-            'input', '', '4', ':', '0', '', 'a', ';', 
-            'input', '', '20', ':', '0', '', 'b', ';', 
-            'output', 'd', ';', 
-            'always', 
-                '@', '(', 
-                    
-                        'a', 
-                        'b'
-                    , ')'
-                , 
-                'begin', 
-                    'if', '(', 
-                        'a', 
-                        '==', 
-                        "5'b00000", 
-                        ')', 
-                        'begin', 
-                            
-                                
-                                    'd', 
-                                    '=', 
-                                    'b', '', '2', '0', ''
-                                , 
-                            ';'
-                            , 
-                        'end'
-                        ,
-                        'else', 
-                        'if', '(', 
-                            'a', 
-                            '==', 
-                            "5'b00001", 
-                            ')', 
-                                'begin', 
-                                    
-                                        
-                                            'd', 
-                                            '=', 
-                                            'b', '', '5', '3', ''
-                                        , 
-                                        ';'
-                                    , 'end', 
-                        'else', 'if', '(', 'a', '==', "5'b00010", ')', 
-                                'begin', 'd', '=', 'b', '', '8', '6', '', ';', 'end', 
-                        'else', 'if', '(', 'a', '==', "5'b00011", ')', 
-                                'begin', 'd', '=', 'b', '', '11', '9', '', ';', 'end', 
-                        'else', 'if', '(', 'a', '==', "5'b00100", ')', 
-                                'begin', 'd', '=', 'b', '', '14', '12', '', ';', 'end', 
-                        'else', 'if', '(', 'a', '==', "5'b00101", ')', 
-                                'begin', 'd', '=', 'b', '', '17', '15', '', ';', 'end', 
-                        'else', 'if', '(', 'a', '==', "5'b00110", ')', 
-                                'begin', 'd', '=', 'b', '', '20', '18', '', ';', 'end', 
-                        'else', 'if', '(', 'a', '==', "5'b00111", ')', 
-                                'begin', 'd', '=', 'b', '', '2', '0', '', ';', 'end', 
-                        'else', 'if', '(', 'a', '==', "5'b01000", ')', 
-                                'begin', 'd', '=', 'b', '', '5', '3', '', ';', 'end', 
-                        'else', 'if', '(', 'a', '==', "5'b01001", ')', 
-                                'begin', 'd', '=', 'b', '', '8', '6', '', ';', 'end', 
-                        'else', 'if', '(', 'a', '==', "5'b01010", ')', 
-                                'begin', 'd', '=', 'b', '', '11', '9', '', ';', 'end', 
-                        'else', 'if', '(', 'a', '==', "5'b01011", ')', 
-                                'begin', 'd', '=', 'b', '', '14', '12', '', ';', 'end', 
-                        'else', 'if', '(', 'a', '==', "5'b01100", ')', 
-                                'begin', 'd', '=', 'b', '', '17', '15', '', ';', 'end', 
-                        'else', 'if', '(', 'a', '==', "5'b01101", ')', 
-                                'begin', 'd', '=', 'b', '', '20', '18', '', ';', 'end', 
-                        'else', 'if', '(', 'a', '==', "5'b01110", ')', 
-                                'begin', 'd', '=', 'b', '', '2', '0', '', ';', 'end', 
-                        'else', 'if', '(', 'a', '==', "5'b01111", ')', 
-                                'begin', 'd', '=', 'b', '', '5', '3', '', ';', 'end', 
-                        'else', 'if', '(', 'a', '==', "5'b10000", ')', 
-                                'begin', 'd', '=', 'b', '', '8', '6', '', ';', 'end', 
-                        'else', 'if', '(', 'a', '==', "5'b10001", ')', 
-                                'begin', 'd', '=', 'b', '', '11', '9', '', ';', 'end', 
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-                                'begin', 'd', '=', 'b', '', '14', '12', '', ';', 'end', 
-                        'else', 'if', '(', 'a', '==', "5'b10011", ')', 
-                                'begin', 'd', '=', 'b', '', '17', '15', '', ';', 'end', 
-                        'else', 'if', '(', 'a', '==', "5'b10100", ')', 
-                                'begin', 'd', '=', 'b', '', '20', '18', '', ';', 'end', 
-                        'else', 'if', '(', 'a', '==', "5'b10101", ')', 
-                                'begin', 'd', '=', 'b', '', '2', '0', '', ';', 'end', 
-                        'else', 'if', '(', 'a', '==', "5'b10110", ')', 
-                        'begin', 'd', '=', 'b', '', '5', '3', '', ';', 'end', 
-                        'else', 'if', '(', 'a', '==', "5'b10111", ')', 
-                        'begin', 'd', '=', 'b', '', '8', '6', '', ';', 'end', 
-                        'else', 'if', '(', 'a', '==', "5'b11000", ')', 
-                        'begin', 'd', '=', 'b', '', '11', '9', '', ';', 'end', 
-                        'else', 'if', '(', 'a', '==', "5'b11001", ')', 
-                        'begin', 'd', '=', 'b', '', '14', '12', '', ';', 'end', 
-                        'else', 'if', '(', 'a', '==', "5'b11010", ')', 
-                        'begin', 'd', '=', 'b', '', '17', '15', '', ';', 'end', 
-                        'else', 'if', '(', 'a', '==', "5'b11011", ')', 
-                        'begin', 'd', '=', 'b', '', '20', '18', '', ';', 'end', 
-                        'else', 'if', '(', 'a', '==', "5'b11111", ')', 
-                        'begin', 'd', '=', "3'b0", ';', 'end', 'else', 
-                        'begin', 'd', '=', '{', '3', '{', "1'b0", '}', '}', ';', 'end'
-                        , 
-                        'end'
-                    
-                , 
-                'endmodule'
-            
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/new2/bar.v Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/new2/foo.v Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/new2/fubar.v Deleted

@@ -1,92 +0,0 @@
-module fubar
-  (/*AUTOARG*/
-  // Outputs
-  ThisIsAnotherLongName, THIS_IS_ANOTHER_LONG_NAME_OUT,
-  // Inputs
-  MY_ADDR_IN
-  );
-
-  input 1:0 MY_ADDR_IN;
-  output      THIS_IS_ANOTHER_LONG_NAME_OUT;
-
-  //------------------------------------------------------------------
-
-
-  /*AUTOREGINPUT*/
-
-  /*AUTOREG*/
-
-  /*AUTOWIRE*/
-  // Beginning of automatic wires (for undeclared instantiated-module outputs)
-  wire                  Ack;                    // From foo of foo.v
-  wire                  Req;                    // From bar of bar.v
-  wire                  ThisIsLongerName;       // From foo of foo.v
-  wire                  ThisNameLonger;         // From bar of bar.v
-  // End of automatics
-
-  //
-  // inputs sort of work
-  //
-
-  /*AUTOUNUSED*/
-
-  /*AUTOINPUT*/
-
-  wire                  MyAddr;
-  assign                MyAddr = MY_ADDR_IN;
-
-  //
-  // outputs dont work
-  //
-
-  /*AUTOOUTPUT*/
-  // Beginning of automatic outputs (from unused autoinst outputs)
-  output                ThisIsAnotherLongName;  // From foo of foo.v
-  // End of automatics
-
-  wire                  THIS_IS_ANOTHER_LONG_NAME_OUT;
-  assign                THIS_IS_ANOTHER_LONG_NAME_OUT = ThisIsAnotherLongName;
-
-  //------------------------------------------------------------------
-
-  /*AUTO_LISP(defun underscore_to_camelcase (s)
-               "Convert NAMES_LIKE_THIS to NamesLikeThis"
-               (setq r "")
-               (setq l (split-string s "_"))
-               (while l
-                 (setq r (concat r (upcase-initials (downcase (car l)))))
-                 (setq l (cdr l)))
-               r)*/
-
-  /* foo AUTO_TEMPLATE (
-   .$.+$_$IN\|OUT$ (@"(underscore_to_camelcase \\"\1\\")"),
-   ); */
-
-  foo foo
-    (/*AUTOINST*/
-     // Outputs
-     .ACK_OUT                           (Ack),                   // Templated
-     .THIS_IS_LONGER_NAME_OUT           (ThisIsLongerName),      // Templated
-     .THIS_IS_ANOTHER_LONG_NAME_OUT     (ThisIsAnotherLongName), // Templated
-     // Inputs
-     .MY_ADDR_IN                        (MyAddr),                // Templated
-     .REQ_IN                            (Req),                   // Templated
-     .THIS_NAME_LONGER_IN               (ThisNameLonger));        // Templated
-
-  /* bar AUTO_TEMPLATE (
-   .$.+$_$IN\|OUT$ (@"(underscore_to_camelcase \\"\1\\")"),
-   ); */
-
-  bar bar
-    (/*AUTOINST*/
-     // Outputs
-     .REQ_OUT                           (Req),                   // Templated
-     .THIS_NAME_LONGER_OUT              (ThisNameLonger),        // Templated
-     // Inputs
-     .MY_ADDR_IN                        (MyAddr),                // Templated
-     .ACK_IN                            (Ack),                   // Templated
-     .THIS_IS_LONGER_NAME_IN            (ThisIsLongerName));      // Templated
-
-  //------------------------------------------------------------------
-
-endmodule

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/new3/b06.v Deleted

@@ -1,151 +0,0 @@
-//
-//  ITC99 Benchmark
-//  Downloaded from http://www.cad.polito.it/tools/itc99.html
-//  
-//  ----------------------------------------------------------------------
-//  
-//  This netlist was generated with Cadence RTL Compiler in a quick 
-//  synthesis run.
-//  
-//  ----------------------------------------------------------------------
-//  
-//  Copyright (C) 1999
-//  Fulvio Corno, Matteo Sonze Reorda, Giovanni Squillero
-//  Politecnico di Torino
-//  
-//  This source file may be used and distributed without restriction
-//  provided that this copyright statement is not removed from the
-//  file and that any derivative work contains the original copyright
-//  notice and the associated disclaimer.
-//  
-//  This source file is free software; you can redistribute it and/or
-//  modify it under the terms of the GNU General Public License as
-//  published by the Free Software Foundation.
-//  
-//  This source is distributed in the hope that it will be useful,
-//  but WITHOUT ANY WARRANTY; without even the implied warranty of
-//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-//  General Public License for more details.
-//  
-//  You should have received a copy of the GNU General Public License
-//  along with this source; if not, download it from
-//  http://www.gnu.org/copyleft/gpl.html
-//  
-
-// Generated by Cadence RTL Compiler (RC) v05.10-b006_1
-
-module b06(cc_mux, eql, uscite, clock, enable_count, ackout, reset,
-     cont_eql);
-  input eql, clock, reset, cont_eql;
-  output 2:1 cc_mux, uscite;
-  output enable_count, ackout;
-  wire eql, clock, reset, cont_eql;
-  wire 2:1 cc_mux, uscite;
-  wire enable_count, ackout;
-  wire n_0, n_1, n_2, n_3, n_4, n_5, n_6, n_7;
-  wire n_9, n_10, n_11, n_12, n_13, n_14, n_15, n_16;
-  wire n_17, n_19, n_20, n_22, n_23, n_24, n_25, n_26;
-  wire n_27, n_28, n_30, n_31, n_32, n_33, n_34, n_36;
-  wire n_37, n_38, n_39, n_41, n_42, n_43, n_44, n_45;
-  wire n_46, n_47, n_48, n_49, n_50, n_51, n_52, n_53;
-  wire n_54, n_55, n_56, n_57, n_58, n_59, n_60, n_61;
-  wire n_62, n_63, n_64, n_65, n_66, n_67, n_68, n_69;
-  wire n_70, n_71, n_72, n_73, n_74, n_75, n_76, n_77;
-  wire n_78, n_79, n_80, n_83, n_84, state, state_7, state_8;
-  DFFSRX1 \cc_mux_reg1 (.RN (n_80), .SN (1'b1), .CK (clock), .D
-       (n_78), .Q (cc_mux1), .QN ());
-  DFFSRX1 enable_count_reg(.RN (n_80), .SN (1'b1), .CK (clock), .D
-       (n_79), .Q (enable_count), .QN ());
-  DFFSRX1 ackout_reg(.RN (n_80), .SN (1'b1), .CK (clock), .D (n_79), .Q
-       (ackout), .QN ());
-  DFFSRX1 \cc_mux_reg2 (.RN (n_80), .SN (1'b1), .CK (clock), .D
-       (n_77), .Q (cc_mux2), .QN ());
-  DFFSRX1 \state_reg1 (.RN (n_80), .SN (1'b1), .CK (clock), .D
-       (n_76), .Q (state_7), .QN ());
-  NAND2X2 g212(.A (n_74), .B (n_61), .Y (n_78));
-  DFFSRX1 \state_reg0 (.RN (n_80), .SN (1'b1), .CK (clock), .D
-       (n_75), .Q (state), .QN ());
-  DFFSRX1 \state_reg2 (.RN (n_80), .SN (1'b1), .CK (clock), .D
-       (n_73), .Q (state_8), .QN ());
-  DFFSRX1 \uscite_reg1 (.RN (n_80), .SN (1'b1), .CK (clock), .D
-       (n_72), .Q (uscite1), .QN ());
-  NAND2X2 g213(.A (n_69), .B (n_66), .Y (n_79));
-  NAND2X2 g218(.A (n_67), .B (n_58), .Y (n_77));
-  NAND2X2 g220(.A (n_71), .B (n_57), .Y (n_76));
-  NAND3X1 g219(.A (n_62), .B (n_49), .C (n_31), .Y (n_75));
-  INVX2 g215(.A (n_68), .Y (n_74));
-  NAND3X1 g223(.A (n_64), .B (n_43), .C (n_31), .Y (n_73));
-  NAND4X1 g211(.A (n_51), .B (n_37), .C (n_54), .D (n_46), .Y (n_72));
-  NOR2X1 g225(.A (n_42), .B (n_70), .Y (n_71));
-  DFFSRX1 \uscite_reg2 (.RN (n_80), .SN (1'b1), .CK (clock), .D
-       (n_70), .Q (uscite2), .QN ());
-  NAND2X1 g222(.A (n_56), .B (n_65), .Y (n_69));
-  NAND4X1 g216(.A (n_39), .B (n_41), .C (n_52), .D (n_45), .Y (n_68));
-  NOR2X1 g224(.A (n_63), .B (n_44), .Y (n_67));
-  AOI21X1 g217(.A0 (n_38), .A1 (n_65), .B0 (n_50), .Y (n_66));
-  INVX1 g231(.A (n_63), .Y (n_64));
-  NOR2X1 g234(.A (n_60), .B (n_53), .Y (n_62));
-  NAND2X2 g227(.A (n_84), .B (n_59), .Y (n_70));
-  NOR2X1 g230(.A (n_13), .B (n_60), .Y (n_61));
-  NAND2X1 g232(.A (n_55), .B (n_59), .Y (n_63));
-  AND2X1 g236(.A (n_47), .B (n_24), .Y (n_58));
-  AOI21X1 g237(.A0 (n_36), .A1 (eql), .B0 (n_26), .Y (n_57));
-  NAND4X1 g238(.A (n_55), .B (n_20), .C (n_33), .D (n_25), .Y (n_56));
-  NOR2X1 g228(.A (n_48), .B (n_34), .Y (n_54));
-  INVX1 g254(.A (n_52), .Y (n_53));
-  NOR2X1 g229(.A (n_23), .B (n_50), .Y (n_51));
-  NOR2X1 g235(.A (n_48), .B (n_50), .Y (n_49));
-  NAND2X1 g244(.A (n_26), .B (eql), .Y (n_47));
-  NOR2X1 g226(.A (n_19), .B (n_30), .Y (n_46));
-  NAND2X1 g248(.A (n_27), .B (eql), .Y (n_45));
-  INVX1 g249(.A (n_43), .Y (n_44));
-  INVX1 g252(.A (n_41), .Y (n_42));
-  NAND2X2 g255(.A (n_19), .B (n_1), .Y (n_52));
-  NAND3X1 g233(.A (n_28), .B (n_24), .C (n_32), .Y (n_38));
-  INVX1 g265(.A (n_36), .Y (n_37));
-  NAND4X1 g239(.A (n_83), .B (n_16), .C (n_3), .D (eql), .Y (n_59));
-  INVX1 g240(.A (n_34), .Y (n_84));
-  NAND2X1 g242(.A (n_33), .B (n_32), .Y (n_60));
-  INVX1 g245(.A (n_30), .Y (n_31));
-  NAND2X1 g250(.A (n_14), .B (eql), .Y (n_43));
-  NOR2X1 g251(.A (n_28), .B (eql), .Y (n_50));
-  NAND2X1 g253(.A (n_17), .B (eql), .Y (n_41));
-  INVX2 g258(.A (n_27), .Y (n_55));
-  INVX1 g262(.A (n_26), .Y (n_39));
-  INVX1 g266(.A (n_33), .Y (n_36));
-  NOR2X1 g241(.A (n_22), .B (eql), .Y (n_34));
-  NOR2X1 g243(.A (n_25), .B (eql), .Y (n_48));
-  NOR2X1 g247(.A (n_24), .B (eql), .Y (n_30));
-  INVX1 g256(.A (n_32), .Y (n_23));
-  INVX2 g259(.A (n_22), .Y (n_27));
-  INVX1 g263(.A (n_28), .Y (n_26));
-  INVX2 g272(.A (n_20), .Y (n_19));
-  NAND3X1 g267(.A (n_7), .B (n_16), .C (n_15), .Y (n_33));
-  NAND3X1 g264(.A (n_16), .B (n_9), .C (n_15), .Y (n_28));
-  NAND3X1 g260(.A (n_12), .B (n_10), .C (n_11), .Y (n_22));
-  INVX1 g269(.A (n_25), .Y (n_14));
-  INVX1 g268(.A (n_25), .Y (n_13));
-  NAND3X1 g273(.A (n_12), .B (n_16), .C (n_11), .Y (n_20));
-  NAND3X1 g257(.A (n_9), .B (n_10), .C (n_15), .Y (n_32));
-  INVX1 g275(.A (n_24), .Y (n_17));
-  NAND2X2 g270(.A (n_5), .B (n_10), .Y (n_25));
-  NAND3X1 g276(.A (n_0), .B (n_6), .C (n_15), .Y (n_24));
-  INVX1 g286(.A (n_7), .Y (n_83));
-  INVX2 g287(.A (n_9), .Y (n_7));
-  INVX2 g285(.A (n_6), .Y (n_12));
-  NOR2X1 g277(.A (n_2), .B (n_4), .Y (n_5));
-  INVX2 g288(.A (n_6), .Y (n_9));
-  INVX1 g283(.A (n_4), .Y (n_11));
-  INVX1 g281(.A (n_15), .Y (n_3));
-  INVX4 g289(.A (n_2), .Y (n_6));
-  INVX1 g278(.A (reset), .Y (n_80));
-  INVX1 g279(.A (eql), .Y (n_1));
-  INVX1 g292(.A (state_7), .Y (n_0));
-  INVX1 g284(.A (state_8), .Y (n_4));
-  INVX1 g291(.A (state_7), .Y (n_10));
-  INVX1 g282(.A (state_8), .Y (n_15));
-  INVX2 g290(.A (state), .Y (n_2));
-  INVX1 g280(.A (cont_eql), .Y (n_65));
-  CLKBUFX1 g293(.A (state_7), .Y (n_16));
-endmodule
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/new3/b10.v Deleted

@@ -1,438 +0,0 @@
-//
-//  ITC99 Benchmark
-//  Downloaded from http://www.cad.polito.it/tools/itc99.html
-//  
-//  ----------------------------------------------------------------------
-//  
-//  This netlist was generated with Cadence RTL Compiler in a quick 
-//  synthesis run.
-//  
-//  ----------------------------------------------------------------------
-//  
-//  Copyright (C) 1999
-//  Fulvio Corno, Matteo Sonze Reorda, Giovanni Squillero
-//  Politecnico di Torino
-//  
-//  This source file may be used and distributed without restriction
-//  provided that this copyright statement is not removed from the
-//  file and that any derivative work contains the original copyright
-//  notice and the associated disclaimer.
-//  
-//  This source file is free software; you can redistribute it and/or
-//  modify it under the terms of the GNU General Public License as
-//  published by the Free Software Foundation.
-//  
-//  This source is distributed in the hope that it will be useful,
-//  but WITHOUT ANY WARRANTY; without even the implied warranty of
-//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-//  General Public License for more details.
-//  
-//  You should have received a copy of the GNU General Public License
-//  along with this source; if not, download it from
-//  http://www.gnu.org/copyleft/gpl.html
-//  
-
-// Generated by Cadence RTL Compiler (RC) v05.10-b006_1
-
-module b10(r_button, g_button, key, start, reset, test, cts, ctr, rts,
-     rtr, clock, v_in, v_out);
-  input r_button, g_button, key, start, reset, test, rts, rtr, clock;
-  input 3:0 v_in;
-  output cts, ctr;
-  output 3:0 v_out;
-  wire r_button, g_button, key, start, reset, test, rts, rtr, clock;
-  wire 3:0 v_in;
-  wire cts, ctr;
-  wire 3:0 v_out;
-  wire n_1, n_2, n_4, n_5, n_6, n_7, n_8, n_9;
-  wire n_12, n_13, n_15, n_16, n_17, n_18, n_20, n_21;
-  wire n_22, n_24, n_27, n_29, n_30, n_31, n_33, n_34;
-  wire n_35, n_36, n_37, n_38, n_39, n_45, n_46, n_47;
-  wire n_49, n_57, n_59, n_60, n_61, n_63, n_67, n_72;
-  wire n_73, n_74, n_75, n_77, n_78, n_79, n_80, n_85;
-  wire n_86, n_87, n_89, n_90, n_91, n_92, n_94, n_95;
-  wire n_96, n_97, n_98, n_99, n_103, n_104, n_110, n_111;
-  wire n_112, n_113, n_115, n_120, n_121, n_122, n_123, n_124;
-  wire n_125, n_126, n_127, n_128, n_131, n_132, n_133, n_135;
-  wire n_137, n_138, n_140, n_141, n_142, n_145, n_148, n_149;
-  wire n_150, n_151, n_152, n_153, n_154, n_155, n_156, n_161;
-  wire n_162, n_163, n_165, n_166, n_167, n_168, n_169, n_171;
-  wire n_174, n_175, n_176, n_178, n_179, n_180, n_181, n_182;
-  wire n_183, n_184, n_186, n_188, n_189, n_190, n_191, n_192;
-  wire n_194, n_195, n_196, n_197, n_199, n_200, n_201, n_203;
-  wire n_204, n_205, n_206, n_207, n_208, n_209, n_210, n_211;
-  wire n_212, n_213, n_214, n_215, n_218, n_219, n_220, n_221;
-  wire n_222, n_223, n_224, n_225, n_226, n_227, n_228, n_229;
-  wire n_230, n_231, n_233, n_235, n_238, n_241, n_243, n_244;
-  wire n_245, n_246, n_247, n_248, n_249, n_250, n_251, n_252;
-  wire n_254, n_255, n_256, n_257, n_258, n_259, n_260, n_261;
-  wire n_262, n_263, n_264, n_265, n_266, n_267, n_268, n_269;
-  wire n_270, n_271, n_274, n_276, n_277, n_279, n_280, n_281;
-  wire n_282, n_284, n_285, n_286, n_287, n_288, n_289, n_292;
-  wire n_293, n_294, n_295, n_297, n_300, n_301, n_302, n_303;
-  wire n_304, n_305, n_307, n_309, n_310, n_311, n_312, n_313;
-  wire n_314, n_315, n_316, n_317, n_318, n_319, n_320, n_322;
-  wire n_323, n_324, n_325, n_328, n_329, n_330, n_331, n_332;
-  wire n_333, n_335, n_336, n_337, n_338, n_339, n_340, n_348;
-  wire n_350, n_351, n_352, n_358, n_377, n_381, n_388, n_389;
-  wire n_391, n_392, n_397, n_398, n_399, n_400, n_401, n_402;
-  wire n_403, n_404, n_405, n_406, n_407, n_408, n_409, n_411;
-  wire n_412, n_413, n_414, n_415, n_416, n_430, n_431, n_432;
-  wire n_433, n_441, n_442, n_443, n_444, n_445, n_446, n_447;
-  wire n_449, n_451, n_453, n_454, n_455, n_456, n_457, n_458;
-  wire n_459, n_460, n_461, n_462, n_463, n_464, n_465, n_466;
-  wire n_467, n_468, n_469, n_470, stato, stato_5, stato_6, stato_7;
-  wire voto2;
-  DFFSRX1 \stato_reg2 (.RN (n_340), .SN (1'b1), .CK (clock), .D
-       (n_339), .Q (stato_6), .QN ());
-  DFFSRX1 \stato_reg0 (.RN (n_340), .SN (1'b1), .CK (clock), .D
-       (n_446), .Q (stato), .QN ());
-  DFFSRX1 voto1_reg(.RN (n_340), .SN (1'b1), .CK (clock), .D (n_336),
-       .Q (n_178), .QN ());
-  DFFSRX1 \stato_reg1 (.RN (n_340), .SN (1'b1), .CK (clock), .D
-       (n_333), .Q (stato_5), .QN ());
-  DFFSRX1 \v_out_reg2 (.RN (n_340), .SN (1'b1), .CK (clock), .D
-       (n_337), .Q (v_out2), .QN ());
-  DFFSRX1 \v_out_reg3 (.RN (n_340), .SN (1'b1), .CK (clock), .D
-       (n_332), .Q (v_out3), .QN ());
-  DFFSRX1 cts_reg(.RN (n_340), .SN (1'b1), .CK (clock), .D (n_335), .Q
-       (cts), .QN ());
-  DFFSRX1 \v_out_reg0 (.RN (n_340), .SN (1'b1), .CK (clock), .D
-       (n_331), .Q (v_out0), .QN ());
-  DFFSRX1 \v_out_reg1 (.RN (n_340), .SN (1'b1), .CK (clock), .D
-       (n_338), .Q (v_out1), .QN ());
-  OR4X1 g1181(.A (n_189), .B (n_238), .C (n_195), .D (n_324), .Y
-       (n_339));
-  DFFSRX1 last_g_reg(.RN (n_340), .SN (1'b1), .CK (clock), .D (n_330),
-       .Q (n_300), .QN ());
-  DFFSRX1 last_r_reg(.RN (n_340), .SN (1'b1), .CK (clock), .D (n_329),
-       .Q (n_38), .QN ());
-  DFFSRX1 \sign_reg3 (.RN (n_340), .SN (1'b1), .CK (clock), .D
-       (n_328), .Q (n_286), .QN ());
-  DFFSRX1 ctr_reg(.RN (n_340), .SN (1'b1), .CK (clock), .D (n_416), .Q
-       (ctr), .QN ());
-  NAND2X2 g1210(.A (n_316), .B (n_260), .Y (n_338));
-  NAND2X2 g1211(.A (n_315), .B (n_264), .Y (n_337));
-  DFFSRX1 voto2_reg(.RN (n_340), .SN (1'b1), .CK (clock), .D (n_325),
-       .Q (voto2), .QN ());
-  DFFSRX1 \stato_reg3 (.RN (n_340), .SN (1'b1), .CK (clock), .D
-       (n_323), .Q (stato_7), .QN ());
-  NAND2X1 g1199(.A (n_467), .B (n_468), .Y (n_336));
-  NAND3X1 g1216(.A (n_313), .B (n_254), .C (n_271), .Y (n_335));
-  NAND3X1 g1202(.A (n_322), .B (n_305), .C (n_209), .Y (n_333));
-  NAND2X2 g1205(.A (n_320), .B (n_263), .Y (n_332));
-  NAND2X2 g1209(.A (n_319), .B (n_261), .Y (n_331));
-  DFFSRX1 voto3_reg(.RN (n_340), .SN (1'b1), .CK (clock), .D (n_309),
-       .Q (n_27), .QN ());
-  NAND3X1 g1217(.A (n_312), .B (n_301), .C (n_225), .Y (n_330));
-  NAND3X1 g1218(.A (n_311), .B (n_279), .C (n_222), .Y (n_329));
-  NAND2X1 g1208(.A (n_351), .B (n_352), .Y (n_328));
-  DFFSRX1 voto0_reg(.RN (n_340), .SN (1'b1), .CK (clock), .D (n_302),
-       .Q (n_47), .QN ());
-  NAND4X1 g1200(.A (n_274), .B (n_250), .C (n_281), .D (n_282), .Y
-       (n_325));
-  OAI21X1 g1214(.A0 (n_196), .A1 (n_74), .B0 (n_297), .Y (n_324));
-  NAND4X1 g1201(.A (n_247), .B (n_205), .C (n_303), .D (n_265), .Y
-       (n_323));
-  AOI21X1 g1221(.A0 (n_86), .A1 (n_175), .B0 (n_304), .Y (n_322));
-  INVX1 g1203(.A (n_307), .Y (n_467));
-  AOI22X1 g1231(.A0 (n_318), .A1 (v_out3), .B0 (n_317), .B1
-       (v_out3), .Y (n_320));
-  AOI22X1 g1232(.A0 (n_318), .A1 (v_out0), .B0 (n_317), .B1
-       (v_out0), .Y (n_319));
-  AOI22X1 g1233(.A0 (n_314), .A1 (v_out1), .B0 (n_317), .B1
-       (v_out1), .Y (n_316));
-  AOI22X1 g1234(.A0 (n_314), .A1 (v_out2), .B0 (n_317), .B1
-       (v_out2), .Y (n_315));
-  AOI22X1 g1235(.A0 (n_433), .A1 (cts), .B0 (n_169), .B1 (cts), .Y
-       (n_313));
-  OAI21X1 g1237(.A0 (n_258), .A1 (n_310), .B0 (n_300), .Y (n_312));
-  OAI21X1 g1238(.A0 (n_257), .A1 (n_310), .B0 (n_38), .Y (n_311));
-  NAND3X1 g1212(.A (n_289), .B (n_268), .C (n_267), .Y (n_309));
-  AOI22X1 g1247(.A0 (n_255), .A1 (n_286), .B0 (n_358), .B1 (n_286), .Y
-       (n_352));
-  NAND4X1 g1204(.A (n_252), .B (n_284), .C (n_231), .D (n_245), .Y
-       (n_307));
-  NOR2X1 g1227(.A (n_288), .B (n_285), .Y (n_351));
-  AOI21X1 g1230(.A0 (n_407), .A1 (n_269), .B0 (n_295), .Y (n_305));
-  NAND2X1 g1245(.A (n_270), .B (n_303), .Y (n_304));
-  NAND4X1 g1219(.A (n_277), .B (n_201), .C (n_233), .D (n_211), .Y
-       (n_302));
-  NAND2X1 g1264(.A (n_259), .B (n_300), .Y (n_301));
-  NOR2X1 g1226(.A (n_243), .B (n_280), .Y (n_297));
-  NAND3X1 g1236(.A (n_469), .B (n_194), .C (n_294), .Y (n_295));
-  NAND2X1 g1257(.A (n_293), .B (n_292), .Y (n_318));
-  NAND2X1 g1259(.A (n_293), .B (n_292), .Y (n_314));
-  AOI22X1 g1229(.A0 (n_276), .A1 (n_27), .B0 (n_112), .B1 (n_251), .Y
-       (n_289));
-  AND2X1 g1294(.A (n_287), .B (n_286), .Y (n_288));
-  OAI21X1 g1240(.A0 (n_181), .A1 (n_18), .B0 (n_149), .Y (n_285));
-  INVX1 g1241(.A (n_248), .Y (n_284));
-  AOI21X1 g1243(.A0 (n_59), .A1 (n_407), .B0 (n_213), .Y (n_282));
-  AOI21X1 g1244(.A0 (n_266), .A1 (voto2), .B0 (n_208), .Y (n_281));
-  NAND4X1 g1246(.A (n_165), .B (n_294), .C (n_162), .D (n_152), .Y
-       (n_280));
-  OAI21X1 g1250(.A0 (n_226), .A1 (n_453), .B0 (n_38), .Y (n_279));
-  NAND2X1 g1251(.A (n_276), .B (n_47), .Y (n_277));
-  NAND2X1 g1253(.A (n_276), .B (n_244), .Y (n_468));
-  NAND2X1 g1255(.A (n_276), .B (voto2), .Y (n_274));
-  OAI21X1 g1262(.A0 (n_317), .A1 (n_407), .B0 (cts), .Y (n_271));
-  NAND2X1 g1265(.A (n_203), .B (n_269), .Y (n_270));
-  AOI21X1 g1266(.A0 (n_89), .A1 (n_249), .B0 (n_408), .Y (n_268));
-  AOI21X1 g1268(.A0 (n_266), .A1 (n_27), .B0 (n_229), .Y (n_267));
-  AOI21X1 g1269(.A0 (n_230), .A1 (n_154), .B0 (n_235), .Y (n_265));
-  AOI21X1 g1271(.A0 (n_262), .A1 (v_out2), .B0 (n_228), .Y (n_264));
-  AOI21X1 g1272(.A0 (n_262), .A1 (v_out3), .B0 (n_224), .Y (n_263));
-  AOI21X1 g1273(.A0 (n_262), .A1 (v_out0), .B0 (n_220), .Y (n_261));
-  AOI21X1 g1274(.A0 (n_262), .A1 (v_out1), .B0 (n_219), .Y (n_260));
-  NAND2X1 g1277(.A (n_292), .B (n_392), .Y (n_259));
-  NAND2X1 g1285(.A (n_227), .B (n_256), .Y (n_258));
-  NAND2X1 g1290(.A (n_292), .B (n_256), .Y (n_257));
-  NAND2X1 g1293(.A (n_207), .B (n_292), .Y (n_255));
-  AOI21X1 g1300(.A0 (rtr), .A1 (n_175), .B0 (n_192), .Y (n_254));
-  AOI22X1 g1303(.A0 (n_249), .A1 (n_90), .B0 (n_251), .B1 (n_178), .Y
-       (n_252));
-  AOI22X1 g1304(.A0 (n_249), .A1 (n_80), .B0 (n_251), .B1 (voto2), .Y
-       (n_250));
-  OAI21X1 g1242(.A0 (n_212), .A1 (n_127), .B0 (n_167), .Y (n_248));
-  AOI21X1 g1215(.A0 (n_171), .A1 (n_246), .B0 (n_184), .Y (n_247));
-  NAND2X1 g1329(.A (n_389), .B (n_191), .Y (n_287));
-  NAND2X1 g1254(.A (n_183), .B (n_244), .Y (n_245));
-  NAND2X1 g1352(.A (n_389), .B (n_432), .Y (n_243));
-  INVX1 g1224(.A (n_210), .Y (n_241));
-  INVX1 g1288(.A (n_206), .Y (n_238));
-  NOR2X1 g1292(.A (n_453), .B (n_358), .Y (n_293));
-  OAI21X1 g1298(.A0 (n_256), .A1 (test), .B0 (n_168), .Y (n_235));
-  NAND2X1 g1299(.A (n_166), .B (n_269), .Y (n_469));
-  AOI22X1 g1301(.A0 (n_249), .A1 (n_94), .B0 (n_47), .B1 (n_460), .Y
-       (n_233));
-  AOI21X1 g1302(.A0 (n_230), .A1 (v_in1), .B0 (n_179), .Y (n_231));
-  OAI21X1 g1306(.A0 (n_215), .A1 (n_6), .B0 (n_176), .Y (n_229));
-  NOR2X1 g1312(.A (n_78), .B (n_223), .Y (n_228));
-  OR2X1 g1319(.A (n_186), .B (n_175), .Y (n_310));
-  INVX1 g1322(.A (n_226), .Y (n_227));
-  INVX4 g1324(.A (n_199), .Y (n_292));
-  AOI22X1 g1248(.A0 (n_121), .A1 (n_407), .B0 (n_300), .B1 (n_221), .Y
-       (n_225));
-  NOR2X1 g1332(.A (n_95), .B (n_223), .Y (n_224));
-  AOI22X1 g1249(.A0 (n_120), .A1 (n_407), .B0 (n_38), .B1 (n_221), .Y
-       (n_222));
-  NOR2X1 g1341(.A (n_96), .B (n_223), .Y (n_220));
-  NOR2X1 g1344(.A (n_92), .B (n_223), .Y (n_219));
-  NAND2X1 g1256(.A (n_156), .B (n_72), .Y (n_218));
-  AOI21X1 g1220(.A0 (n_111), .A1 (n_188), .B0 (n_223), .Y (n_214));
-  NOR2X1 g1263(.A (n_124), .B (n_212), .Y (n_213));
-  AOI22X1 g1270(.A0 (n_153), .A1 (n_47), .B0 (n_18), .B1 (n_221), .Y
-       (n_211));
-  NAND4X1 g1225(.A (n_209), .B (n_138), .C (n_131), .D (n_126), .Y
-       (n_210));
-  OAI21X1 g1275(.A0 (n_182), .A1 (n_79), .B0 (n_180), .Y (n_208));
-  NAND2X2 g1279(.A (n_207), .B (n_191), .Y (n_276));
-  NAND3X1 g1289(.A (rtr), .B (n_204), .C (n_163), .Y (n_206));
-  NAND3X1 g1291(.A (rtr), .B (n_204), .C (n_154), .Y (n_205));
-  NAND2X1 g1296(.A (n_215), .B (n_377), .Y (n_203));
-  AOI22X1 g1305(.A0 (n_230), .A1 (v_in0), .B0 (n_91), .B1 (n_409), .Y
-       (n_201));
-  NAND2X1 g1310(.A (n_407), .B (n_72), .Y (n_200));
-  NAND2X1 g1318(.A (n_256), .B (n_432), .Y (n_262));
-  NAND2X1 g1323(.A (n_123), .B (n_190), .Y (n_226));
-  NAND2X2 g1325(.A (n_148), .B (n_145), .Y (n_199));
-  NAND2X1 g1334(.A (n_432), .B (n_457), .Y (n_266));
-  NAND2X1 g1335(.A (n_161), .B (n_196), .Y (n_197));
-  INVX1 g1338(.A (n_194), .Y (n_195));
-  NAND2X1 g1342(.A (n_141), .B (n_133), .Y (n_358));
-  NOR2X1 g1347(.A (n_20), .B (n_191), .Y (n_192));
-  NAND2X1 g1349(.A (n_388), .B (n_190), .Y (n_317));
-  AOI21X1 g1222(.A0 (n_75), .A1 (n_188), .B0 (n_191), .Y (n_189));
-  NOR2X1 g1223(.A (n_155), .B (n_191), .Y (n_184));
-  NAND2X1 g1281(.A (n_182), .B (n_432), .Y (n_183));
-  AOI21X1 g1295(.A0 (test), .A1 (n_132), .B0 (n_221), .Y (n_181));
-  NAND2X1 g1309(.A (n_230), .B (v_in2), .Y (n_180));
-  NAND3X1 g1311(.A (start), .B (n_122), .C (n_140), .Y (n_212));
-  AND2X1 g1313(.A (n_178), .B (n_460), .Y (n_179));
-  NAND2X1 g1314(.A (n_175), .B (n_398), .Y (n_176));
-  NOR2X1 g1315(.A (n_196), .B (n_99), .Y (n_174));
-  NAND2X1 g1320(.A (n_406), .B (n_1), .Y (n_209));
-  NAND2X1 g1326(.A (n_230), .B (n_103), .Y (n_303));
-  NOR2X1 g1336(.A (n_470), .B (n_196), .Y (n_171));
-  NAND2X1 g1340(.A (n_150), .B (n_128), .Y (n_194));
-  NAND2X1 g1343(.A (rtr), .B (n_460), .Y (n_377));
-  AND2X1 g1345(.A (n_190), .B (n_381), .Y (n_207));
-  NAND2X1 g1346(.A (n_148), .B (n_215), .Y (n_169));
-  NAND3X1 g1348(.A (n_409), .B (start), .C (n_154), .Y (n_168));
-  NAND3X1 g1350(.A (n_406), .B (n_178), .C (n_1), .Y (n_167));
-  NAND2X1 g1351(.A (n_148), .B (n_190), .Y (n_166));
-  NAND3X1 g1353(.A (n_406), .B (start), .C (n_163), .Y (n_165));
-  NAND2X1 g1355(.A (n_85), .B (n_460), .Y (n_162));
-  CLKBUFX3 g1385(.A (n_191), .Y (n_223));
-  INVX2 g1399(.A (n_388), .Y (n_251));
-  INVX1 g1402(.A (n_389), .Y (n_186));
-  NAND2X1 g1287(.A (n_182), .B (n_148), .Y (n_156));
-  OAI21X1 g1239(.A0 (rtr), .A1 (n_154), .B0 (n_188), .Y (n_155));
-  INVX1 g1330(.A (n_182), .Y (n_153));
-  NAND2X1 g1333(.A (n_135), .B (n_163), .Y (n_152));
-  NAND2X1 g1337(.A (n_135), .B (n_150), .Y (n_151));
-  INVX1 g1362(.A (n_230), .Y (n_149));
-  INVX1 g1367(.A (n_175), .Y (n_161));
-  INVX2 g1374(.A (n_148), .Y (n_249));
-  INVX1 g1380(.A (n_460), .Y (n_145));
-  INVX4 g1388(.A (n_142), .Y (n_191));
-  INVX1 g1392(.A (n_381), .Y (n_204));
-  INVX1 g1396(.A (n_406), .Y (n_141));
-  CLKBUFX3 g1405(.A (n_431), .Y (n_221));
-  NAND4X1 g1282(.A (rtr), .B (n_72), .C (n_137), .D (n_348), .Y
-       (n_138));
-  NAND3X1 g1331(.A (n_1), .B (n_137), .C (n_125), .Y (n_182));
-  INVX2 g1368(.A (n_133), .Y (n_175));
-  INVX2 g1358(.A (n_132), .Y (n_256));
-  INVX1 g1359(.A (n_132), .Y (n_131));
-  INVX2 g1363(.A (n_449), .Y (n_230));
-  CLKBUFX3 g1364(.A (n_449), .Y (n_215));
-  INVX2 g1376(.A (n_135), .Y (n_148));
-  INVX2 g1389(.A (n_123), .Y (n_142));
-  CLKBUFX3 g1407(.A (n_190), .Y (n_196));
-  INVX1 g1408(.A (n_190), .Y (n_128));
-  NAND2X1 g1283(.A (n_87), .B (key), .Y (n_127));
-  NAND3X1 g1284(.A (n_104), .B (n_391), .C (n_125), .Y (n_126));
-  NAND2X1 g1286(.A (n_98), .B (key), .Y (n_124));
-  NAND2X2 g1390(.A (n_122), .B (n_113), .Y (n_123));
-  MX2X1 g1307(.A (n_300), .B (n_60), .S0 (start), .Y (n_121));
-  MX2X1 g1308(.A (n_38), .B (n_67), .S0 (start), .Y (n_120));
-  NAND3X1 g1316(.A (rts), .B (n_122), .C (n_348), .Y (n_294));
-  NAND2X1 g1252(.A (n_77), .B (rtr), .Y (n_188));
-  NAND2X1 g1369(.A (n_137), .B (n_125), .Y (n_133));
-  INVX2 g1377(.A (n_115), .Y (n_135));
-  INVX1 g1360(.A (n_97), .Y (n_132));
-  NAND2X2 g1409(.A (n_137), .B (n_113), .Y (n_190));
-  XOR2X1 g1276(.A (n_47), .B (n_63), .Y (n_112));
-  OR2X1 g1424(.A (rtr), .B (n_99), .Y (n_111));
-  INVX2 g1425(.A (n_110), .Y (n_140));
-  NAND2X1 g1378(.A (n_404), .B (n_456), .Y (n_115));
-  NOR2X1 g1321(.A (n_103), .B (n_73), .Y (n_104));
-  XOR2X1 g1357(.A (n_79), .B (n_34), .Y (n_98));
-  NAND2X1 g1361(.A (n_122), .B (n_125), .Y (n_97));
-  MX2X1 g1412(.A (n_4), .B (n_15), .S0 (rtr), .Y (n_96));
-  MX2X1 g1413(.A (n_2), .B (n_31), .S0 (rtr), .Y (n_95));
-  OAI21X1 g1414(.A0 (rts), .A1 (n_15), .B0 (n_16), .Y (n_94));
-  MX2X1 g1415(.A (n_5), .B (n_61), .S0 (rtr), .Y (n_92));
-  OAI21X1 g1416(.A0 (n_15), .A1 (start), .B0 (n_29), .Y (n_91));
-  OAI21X1 g1418(.A0 (rts), .A1 (n_61), .B0 (n_13), .Y (n_90));
-  OAI21X1 g1419(.A0 (n_246), .A1 (n_31), .B0 (n_8), .Y (n_89));
-  INVX2 g1426(.A (n_402), .Y (n_110));
-  XOR2X1 g1356(.A (n_61), .B (n_36), .Y (n_87));
-  NAND2X1 g1455(.A (n_1), .B (n_49), .Y (n_86));
-  NAND2X1 g1431(.A (rtr), .B (n_74), .Y (n_85));
-  OAI21X1 g1411(.A0 (rts), .A1 (n_79), .B0 (n_22), .Y (n_80));
-  MX2X1 g1420(.A (n_7), .B (n_79), .S0 (rtr), .Y (n_78));
-  NAND3X1 g1280(.A (n_30), .B (n_15), .C (n_31), .Y (n_77));
-  INVX2 g1432(.A (n_454), .Y (n_137));
-  INVX2 g1435(.A (n_57), .Y (n_113));
-  OR2X1 g1439(.A (rtr), .B (n_74), .Y (n_75));
-  INVX1 g1473(.A (n_72), .Y (n_99));
-  NOR2X1 g1410(.A (n_24), .B (n_21), .Y (n_103));
-  INVX1 g1527(.A (n_61), .Y (n_244));
-  OAI21X1 g1417(.A0 (n_33), .A1 (key), .B0 (n_17), .Y (n_67));
-  INVX1 g1474(.A (n_73), .Y (n_72));
-  INVX1 g1509(.A (n_74), .Y (n_163));
-  XOR2X1 g1422(.A (n_79), .B (n_61), .Y (n_63));
-  OAI21X1 g1421(.A0 (n_35), .A1 (key), .B0 (n_12), .Y (n_60));
-  NOR2X1 g1423(.A (n_79), .B (start), .Y (n_59));
-  INVX1 g1457(.A (n_403), .Y (n_122));
-  NAND2X2 g1436(.A (n_39), .B (n_37), .Y (n_57));
-  INVX2 g1450(.A (n_447), .Y (n_125));
-  INVX1 g1496(.A (n_154), .Y (n_470));
-  INVX1 g1513(.A (n_269), .Y (n_49));
-  INVX1 g1475(.A (n_465), .Y (n_73));
-  INVX1 g1498(.A (n_462), .Y (n_350));
-  INVX1 g1514(.A (n_39), .Y (n_269));
-  INVX1 g1510(.A (n_37), .Y (n_74));
-  NAND2X1 g1438(.A (n_35), .B (g_button), .Y (n_36));
-  NAND2X1 g1437(.A (n_33), .B (r_button), .Y (n_34));
-  NOR2X1 g1453(.A (n_79), .B (n_61), .Y (n_30));
-  NAND2X1 g1454(.A (key), .B (start), .Y (n_29));
-  CLKBUFX1 g1497(.A (n_462), .Y (n_154));
-  NAND2X1 g1460(.A (v_in0), .B (v_in1), .Y (n_24));
-  INVX1 g1518(.A (n_150), .Y (n_246));
-  NAND2X1 g1443(.A (v_in2), .B (rts), .Y (n_22));
-  NAND2X1 g1445(.A (v_in2), .B (v_in3), .Y (n_21));
-  NOR2X1 g1461(.A (rtr), .B (cts), .Y (n_20));
-  INVX1 g1511(.A (n_46), .Y (n_37));
-  NAND2X1 g1456(.A (r_button), .B (key), .Y (n_17));
-  NAND2X1 g1449(.A (v_in0), .B (rts), .Y (n_16));
-  NAND2X1 g1442(.A (v_in1), .B (rts), .Y (n_13));
-  NAND2X1 g1447(.A (g_button), .B (key), .Y (n_12));
-  INVX2 g1516(.A (n_45), .Y (n_9));
-  NAND2X1 g1446(.A (rts), .B (v_in3), .Y (n_8));
-  CLKBUFX2 g1515(.A (n_45), .Y (n_39));
-  INVX1 g1526(.A (n_47), .Y (n_15));
-  INVX1 g1485(.A (v_out2), .Y (n_7));
-  INVX1 g1502(.A (n_300), .Y (n_35));
-  INVX4 g1512(.A (stato_6), .Y (n_46));
-  INVX1 g1520(.A (rts), .Y (n_150));
-  INVX1 g1482(.A (v_in3), .Y (n_6));
-  INVX1 g1521(.A (reset), .Y (n_340));
-  INVX1 g1484(.A (v_out1), .Y (n_5));
-  INVX1 g1478(.A (v_out0), .Y (n_4));
-  INVX1 g1467(.A (n_27), .Y (n_31));
-  INVX2 g1517(.A (stato_5), .Y (n_45));
-  INVX1 g1483(.A (v_out3), .Y (n_2));
-  INVX1 g1531(.A (n_178), .Y (n_61));
-  INVX1 g1491(.A (start), .Y (n_1));
-  INVX1 g1506(.A (n_286), .Y (n_18));
-  INVX1 g1481(.A (n_38), .Y (n_33));
-  INVX2 g1535(.A (voto2), .Y (n_79));
-  CLKBUFX1 g1554(.A (n_456), .Y (n_348));
-  NAND2X1 g1393_dup(.A (n_451), .B (n_125), .Y (n_381));
-  NAND2X2 g1574(.A (n_140), .B (n_137), .Y (n_388));
-  NAND2X2 g1403_dup(.A (n_140), .B (n_137), .Y (n_389));
-  NOR2X1 g1575(.A (n_350), .B (n_73), .Y (n_466));
-  NOR2X1 g1448_dup(.A (n_350), .B (n_73), .Y (n_391));
-  INVX1 g1576(.A (n_453), .Y (n_392));
-  AND2X1 g41(.A (n_400), .B (n_407), .Y (n_408));
-  NAND2X1 g42(.A (n_397), .B (n_399), .Y (n_400));
-  NAND3X1 g43(.A (n_27), .B (start), .C (key), .Y (n_397));
-  INVX1 g47(.A (n_398), .Y (n_399));
-  NOR2X1 g48(.A (start), .B (n_31), .Y (n_398));
-  CLKBUFX3 g53(.A (n_406), .Y (n_407));
-  INVX2 g54(.A (n_405), .Y (n_406));
-  NAND2X1 g46(.A (n_402), .B (n_404), .Y (n_405));
-  INVX2 g51(.A (n_401), .Y (n_402));
-  NAND2X2 g52(.A (n_9), .B (n_46), .Y (n_401));
-  INVX1 g49(.A (n_403), .Y (n_404));
-  NAND2X1 g50(.A (n_461), .B (n_463), .Y (n_403));
-  CLKBUFX2 g1(.A (n_406), .Y (n_409));
-  NAND4X1 g1579(.A (n_411), .B (n_412), .C (n_413), .D (n_415), .Y
-       (n_416));
-  AOI21X1 g44(.A0 (ctr), .A1 (n_459), .B0 (n_195), .Y (n_411));
-  OAI21X1 g45(.A0 (n_287), .A1 (n_407), .B0 (ctr), .Y (n_412));
-  NAND2X1 g1581(.A (n_197), .B (ctr), .Y (n_413));
-  NAND2X1 g1582(.A (n_414), .B (ctr), .Y (n_415));
-  NAND3X1 g1583(.A (n_151), .B (n_215), .C (n_432), .Y (n_414));
-  NAND2X1 g17(.A (n_430), .B (n_432), .Y (n_433));
-  NAND2X1 g18(.A (rtr), .B (n_459), .Y (n_430));
-  INVX2 g19(.A (n_431), .Y (n_432));
-  NOR2X1 g20(.A (n_464), .B (n_110), .Y (n_431));
-  NAND2X2 g36(.A (n_444), .B (n_445), .Y (n_446));
-  NOR2X1 g37(.A (n_442), .B (n_443), .Y (n_444));
-  OAI21X1 g38(.A0 (n_441), .A1 (n_381), .B0 (n_200), .Y (n_442));
-  AND2X1 g1596(.A (n_99), .B (rtr), .Y (n_441));
-  NAND3X1 g39(.A (n_241), .B (n_218), .C (n_294), .Y (n_443));
-  AOI21X1 g40(.A0 (n_174), .A1 (n_246), .B0 (n_214), .Y (n_445));
-  NAND2X1 g1597(.A (n_449), .B (n_458), .Y (n_453));
-  NAND2X2 g1598(.A (n_125), .B (n_466), .Y (n_449));
-  NAND2X1 g26(.A (n_46), .B (n_45), .Y (n_447));
-  INVX1 g1599(.A (n_464), .Y (n_451));
-  NAND2X1 g1601(.A (n_457), .B (n_458), .Y (n_459));
-  NAND2X2 g1602(.A (n_455), .B (n_456), .Y (n_457));
-  INVX1 g28(.A (n_454), .Y (n_455));
-  NAND2X2 g29(.A (n_465), .B (n_461), .Y (n_454));
-  NOR2X1 g30(.A (n_45), .B (n_46), .Y (n_456));
-  NAND2X1 g27(.A (n_451), .B (n_125), .Y (n_458));
-  INVX2 g1603(.A (n_457), .Y (n_460));
-  NAND2X1 g11(.A (n_462), .B (n_463), .Y (n_464));
-  INVX1 g14(.A (n_461), .Y (n_462));
-  INVX2 g15(.A (stato_7), .Y (n_461));
-  INVX2 g13(.A (stato), .Y (n_463));
-  INVX2 g12(.A (n_463), .Y (n_465));
-endmodule
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/new3/ca_prng.v Deleted

@@ -1,1311 +0,0 @@
-//========================================================================
-//
-// ca_prng.v
-// ---------
-// Cellular Automata (CA) PRNG. This version produces PRNG words
-// with 32 bits.
-// 
-// Version: v1.1, 2009-03-20
-// Generated by: gen_ca_prng_rtl.py v2.0, 2009-03-20
-// 
-// 
-// Author: Joachim Strombergson
-// Copyright (c) 2008, InformAsic AB
-// All rights reserved.
-// 
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-// 
-//     * Redistributions in binary form must reproduce the above
-//       copyright notice, this list of conditions and the following
-//       disclaimer in the documentation and/or other materials
-//       provided with the distribution.
-// 
-// THIS SOFTWARE IS PROVIDED BY InformAsic AB ''AS IS'' AND ANY EXPRESS
-// OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL InformAsic AB BE LIABLE FOR ANY
-// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// 
-//========================================================================
-
-module ca_prng(
-               input wire           clk,
-               input wire           reset_n,
-
-               input wire 31 : 0  init_pattern_data,
-               input wire           load_init_pattern,
-               input wire           next_pattern,
-
-               input wire 7 : 0   update_rule,
-               input wire           load_update_rule,
-
-               output wire 31 : 0 prng_data
-              );
-
-
-  //--------------------------------------------------------------------
-  // Constant declarations.
-  //--------------------------------------------------------------------
-  // DEFAULT_RULE
-  // The Default update rule - rule 30.
-  parameter 7 : 0 DEFAULT_RULE = 8'b00011110;
-
-
-  //--------------------------------------------------------------------
-  // Register declarations.
-  //--------------------------------------------------------------------
-  // ca_state_reg
-  // State register for the CA cells, one bit for each cell.
-  reg 31 : 0 ca_state_reg;
-  reg 31 : 0 ca_state_new;
-  reg          ca_state_we;
-
-  // update_rule_reg
-  // Register for the update rule.
-  reg 7 : 0 update_rule_reg;
-
-
-  //--------------------------------------------------------------------
-  // Wire declarations.
-  //--------------------------------------------------------------------
-  // tmp_ca_state_new
-  // temporary update vector. Is muxed to the real update vector
-  // if the load_init_pattern control signal is not set.
-  reg 31 : 0 tmp_ca_state_new;
-
-
-  //--------------------------------------------------------------------
-  // Assignments.
-  //--------------------------------------------------------------------
-  // Connect the PRNG output port to the CA state registers.
-  assign prng_data = ca_state_reg;
-
-
-  //--------------------------------------------------------------------
-  // reg_update
-  //
-  // This clocked process impement all register updates including
-  // synchronous, active low reset.
-  //--------------------------------------------------------------------
-  always @ (posedge clk)
-    begin : reg_update
-      if (!reset_n)
-        begin
-          // Register reset.
-          update_rule_reg <= DEFAULT_RULE;
-          ca_state_reg    <= 32'b00000000000000000000000000000000;
-        end
-      else
-        begin
-          // Normal register update.
-
-          if (load_update_rule)
-            begin
-              update_rule_reg <= update_rule;
-           end
-
-          if (ca_state_we)
-            begin
-              ca_state_reg <= ca_state_new;
-           end
-         end
-    end // reg_update
-
-
-  //--------------------------------------------------------------------
-  // ca_state_update
-  //
-  // State update logic for the CA cells. This is where we implement
-  // the Rule 30-logic as well as init pattern assignment.
-  //--------------------------------------------------------------------
-  always @*
-    begin : ca_state_update
-      // Update for ca_state_reg bit 0.
-      case({ca_state_reg31, ca_state_reg0, ca_state_reg1})
-        0:
-        begin
-          tmp_ca_state_new0 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new0 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new0 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new0 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new0 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new0 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new0 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new0 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new0
-
-      // Update for ca_state_reg bit 1.
-      case({ca_state_reg0, ca_state_reg1, ca_state_reg2})
-        0:
-        begin
-          tmp_ca_state_new1 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new1 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new1 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new1 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new1 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new1 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new1 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new1 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new1
-
-      // Update for ca_state_reg bit 2.
-      case({ca_state_reg1, ca_state_reg2, ca_state_reg3})
-        0:
-        begin
-          tmp_ca_state_new2 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new2 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new2 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new2 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new2 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new2 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new2 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new2 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new2
-
-      // Update for ca_state_reg bit 3.
-      case({ca_state_reg2, ca_state_reg3, ca_state_reg4})
-        0:
-        begin
-          tmp_ca_state_new3 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new3 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new3 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new3 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new3 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new3 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new3 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new3 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new3
-
-      // Update for ca_state_reg bit 4.
-      case({ca_state_reg3, ca_state_reg4, ca_state_reg5})
-        0:
-        begin
-          tmp_ca_state_new4 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new4 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new4 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new4 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new4 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new4 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new4 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new4 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new4
-
-      // Update for ca_state_reg bit 5.
-      case({ca_state_reg4, ca_state_reg5, ca_state_reg6})
-        0:
-        begin
-          tmp_ca_state_new5 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new5 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new5 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new5 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new5 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new5 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new5 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new5 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new5
-
-      // Update for ca_state_reg bit 6.
-      case({ca_state_reg5, ca_state_reg6, ca_state_reg7})
-        0:
-        begin
-          tmp_ca_state_new6 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new6 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new6 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new6 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new6 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new6 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new6 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new6 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new6
-
-      // Update for ca_state_reg bit 7.
-      case({ca_state_reg6, ca_state_reg7, ca_state_reg8})
-        0:
-        begin
-          tmp_ca_state_new7 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new7 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new7 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new7 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new7 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new7 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new7 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new7 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new7
-
-      // Update for ca_state_reg bit 8.
-      case({ca_state_reg7, ca_state_reg8, ca_state_reg9})
-        0:
-        begin
-          tmp_ca_state_new8 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new8 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new8 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new8 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new8 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new8 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new8 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new8 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new8
-
-      // Update for ca_state_reg bit 9.
-      case({ca_state_reg8, ca_state_reg9, ca_state_reg10})
-        0:
-        begin
-          tmp_ca_state_new9 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new9 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new9 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new9 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new9 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new9 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new9 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new9 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new9
-
-      // Update for ca_state_reg bit 10.
-      case({ca_state_reg9, ca_state_reg10, ca_state_reg11})
-        0:
-        begin
-          tmp_ca_state_new10 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new10 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new10 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new10 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new10 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new10 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new10 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new10 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new10
-
-      // Update for ca_state_reg bit 11.
-      case({ca_state_reg10, ca_state_reg11, ca_state_reg12})
-        0:
-        begin
-          tmp_ca_state_new11 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new11 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new11 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new11 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new11 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new11 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new11 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new11 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new11
-
-      // Update for ca_state_reg bit 12.
-      case({ca_state_reg11, ca_state_reg12, ca_state_reg13})
-        0:
-        begin
-          tmp_ca_state_new12 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new12 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new12 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new12 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new12 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new12 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new12 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new12 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new12
-
-      // Update for ca_state_reg bit 13.
-      case({ca_state_reg12, ca_state_reg13, ca_state_reg14})
-        0:
-        begin
-          tmp_ca_state_new13 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new13 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new13 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new13 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new13 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new13 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new13 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new13 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new13
-
-      // Update for ca_state_reg bit 14.
-      case({ca_state_reg13, ca_state_reg14, ca_state_reg15})
-        0:
-        begin
-          tmp_ca_state_new14 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new14 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new14 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new14 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new14 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new14 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new14 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new14 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new14
-
-      // Update for ca_state_reg bit 15.
-      case({ca_state_reg14, ca_state_reg15, ca_state_reg16})
-        0:
-        begin
-          tmp_ca_state_new15 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new15 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new15 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new15 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new15 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new15 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new15 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new15 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new15
-
-      // Update for ca_state_reg bit 16.
-      case({ca_state_reg15, ca_state_reg16, ca_state_reg17})
-        0:
-        begin
-          tmp_ca_state_new16 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new16 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new16 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new16 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new16 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new16 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new16 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new16 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new16
-
-      // Update for ca_state_reg bit 17.
-      case({ca_state_reg16, ca_state_reg17, ca_state_reg18})
-        0:
-        begin
-          tmp_ca_state_new17 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new17 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new17 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new17 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new17 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new17 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new17 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new17 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new17
-
-      // Update for ca_state_reg bit 18.
-      case({ca_state_reg17, ca_state_reg18, ca_state_reg19})
-        0:
-        begin
-          tmp_ca_state_new18 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new18 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new18 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new18 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new18 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new18 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new18 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new18 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new18
-
-      // Update for ca_state_reg bit 19.
-      case({ca_state_reg18, ca_state_reg19, ca_state_reg20})
-        0:
-        begin
-          tmp_ca_state_new19 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new19 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new19 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new19 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new19 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new19 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new19 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new19 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new19
-
-      // Update for ca_state_reg bit 20.
-      case({ca_state_reg19, ca_state_reg20, ca_state_reg21})
-        0:
-        begin
-          tmp_ca_state_new20 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new20 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new20 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new20 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new20 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new20 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new20 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new20 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new20
-
-      // Update for ca_state_reg bit 21.
-      case({ca_state_reg20, ca_state_reg21, ca_state_reg22})
-        0:
-        begin
-          tmp_ca_state_new21 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new21 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new21 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new21 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new21 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new21 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new21 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new21 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new21
-
-      // Update for ca_state_reg bit 22.
-      case({ca_state_reg21, ca_state_reg22, ca_state_reg23})
-        0:
-        begin
-          tmp_ca_state_new22 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new22 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new22 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new22 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new22 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new22 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new22 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new22 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new22
-
-      // Update for ca_state_reg bit 23.
-      case({ca_state_reg22, ca_state_reg23, ca_state_reg24})
-        0:
-        begin
-          tmp_ca_state_new23 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new23 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new23 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new23 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new23 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new23 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new23 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new23 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new23
-
-      // Update for ca_state_reg bit 24.
-      case({ca_state_reg23, ca_state_reg24, ca_state_reg25})
-        0:
-        begin
-          tmp_ca_state_new24 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new24 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new24 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new24 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new24 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new24 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new24 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new24 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new24
-
-      // Update for ca_state_reg bit 25.
-      case({ca_state_reg24, ca_state_reg25, ca_state_reg26})
-        0:
-        begin
-          tmp_ca_state_new25 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new25 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new25 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new25 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new25 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new25 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new25 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new25 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new25
-
-      // Update for ca_state_reg bit 26.
-      case({ca_state_reg25, ca_state_reg26, ca_state_reg27})
-        0:
-        begin
-          tmp_ca_state_new26 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new26 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new26 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new26 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new26 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new26 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new26 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new26 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new26
-
-      // Update for ca_state_reg bit 27.
-      case({ca_state_reg26, ca_state_reg27, ca_state_reg28})
-        0:
-        begin
-          tmp_ca_state_new27 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new27 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new27 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new27 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new27 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new27 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new27 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new27 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new27
-
-      // Update for ca_state_reg bit 28.
-      case({ca_state_reg27, ca_state_reg28, ca_state_reg29})
-        0:
-        begin
-          tmp_ca_state_new28 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new28 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new28 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new28 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new28 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new28 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new28 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new28 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new28
-
-      // Update for ca_state_reg bit 29.
-      case({ca_state_reg28, ca_state_reg29, ca_state_reg30})
-        0:
-        begin
-          tmp_ca_state_new29 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new29 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new29 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new29 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new29 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new29 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new29 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new29 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new29
-
-      // Update for ca_state_reg bit 30.
-      case({ca_state_reg29, ca_state_reg30, ca_state_reg31})
-        0:
-        begin
-          tmp_ca_state_new30 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new30 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new30 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new30 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new30 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new30 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new30 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new30 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new30
-
-      // Update for ca_state_reg bit 31.
-      case({ca_state_reg30, ca_state_reg31, ca_state_reg0})
-        0:
-        begin
-          tmp_ca_state_new31 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new31 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new31 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new31 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new31 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new31 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new31 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new31 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new31
-
-
-      if (load_init_pattern)
-        begin
-          ca_state_new = init_pattern_data;
-        end
-      else
-        begin
-          ca_state_new = tmp_ca_state_new;
-        end
-
-      // Should an init pattern or the next pattern be stored in
-      // the CA array?
-      if (load_init_pattern || next_pattern)
-        begin
-          ca_state_we = 1;
-        end
-      else
-        begin
-          ca_state_we = 0;
-        end
-    end // ca_state_update
-
-
-endmodule // ca_prng
-//========================================================================
-// EOF ca_prng.v
-//========================================================================

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/new3/parseOutput/b06.v.parsed.txt Deleted

@@ -1,898 +0,0 @@
-//
-//  ITC99 Benchmark
-//  Downloaded from http://www.cad.polito.it/tools/itc99.html
-//  
-//  ----------------------------------------------------------------------
-//  
-//  This netlist was generated with Cadence RTL Compiler in a quick 
-//  synthesis run.
-//  
-//  ----------------------------------------------------------------------
-//  
-//  Copyright (C) 1999
-//  Fulvio Corno, Matteo Sonze Reorda, Giovanni Squillero
-//  Politecnico di Torino
-//  
-//  This source file may be used and distributed without restriction
-//  provided that this copyright statement is not removed from the
-//  file and that any derivative work contains the original copyright
-//  notice and the associated disclaimer.
-//  
-//  This source file is free software; you can redistribute it and/or
-//  modify it under the terms of the GNU General Public License as
-//  published by the Free Software Foundation.
-//  
-//  This source is distributed in the hope that it will be useful,
-//  but WITHOUT ANY WARRANTY; without even the implied warranty of
-//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-//  General Public License for more details.
-//  
-//  You should have received a copy of the GNU General Public License
-//  along with this source; if not, download it from
-//  http://www.gnu.org/copyleft/gpl.html
-//  
-
-// Generated by Cadence RTL Compiler (RC) v05.10-b006_1
-
-module b06(cc_mux, eql, uscite, clock, enable_count, ackout, reset,
-     cont_eql);
-  input eql, clock, reset, cont_eql;
-  output 2:1 cc_mux, uscite;
-  output enable_count, ackout;
-  wire eql, clock, reset, cont_eql;
-  wire 2:1 cc_mux, uscite;
-  wire enable_count, ackout;
-  wire n_0, n_1, n_2, n_3, n_4, n_5, n_6, n_7;
-  wire n_9, n_10, n_11, n_12, n_13, n_14, n_15, n_16;
-  wire n_17, n_19, n_20, n_22, n_23, n_24, n_25, n_26;
-  wire n_27, n_28, n_30, n_31, n_32, n_33, n_34, n_36;
-  wire n_37, n_38, n_39, n_41, n_42, n_43, n_44, n_45;
-  wire n_46, n_47, n_48, n_49, n_50, n_51, n_52, n_53;
-  wire n_54, n_55, n_56, n_57, n_58, n_59, n_60, n_61;
-  wire n_62, n_63, n_64, n_65, n_66, n_67, n_68, n_69;
-  wire n_70, n_71, n_72, n_73, n_74, n_75, n_76, n_77;
-  wire n_78, n_79, n_80, n_83, n_84, state, state_7, state_8;
-  DFFSRX1 \cc_mux_reg1 (.RN (n_80), .SN (1'b1), .CK (clock), .D
-       (n_78), .Q (cc_mux1), .QN ());
-  DFFSRX1 enable_count_reg(.RN (n_80), .SN (1'b1), .CK (clock), .D
-       (n_79), .Q (enable_count), .QN ());
-  DFFSRX1 ackout_reg(.RN (n_80), .SN (1'b1), .CK (clock), .D (n_79), .Q
-       (ackout), .QN ());
-  DFFSRX1 \cc_mux_reg2 (.RN (n_80), .SN (1'b1), .CK (clock), .D
-       (n_77), .Q (cc_mux2), .QN ());
-  DFFSRX1 \state_reg1 (.RN (n_80), .SN (1'b1), .CK (clock), .D
-       (n_76), .Q (state_7), .QN ());
-  NAND2X2 g212(.A (n_74), .B (n_61), .Y (n_78));
-  DFFSRX1 \state_reg0 (.RN (n_80), .SN (1'b1), .CK (clock), .D
-       (n_75), .Q (state), .QN ());
-  DFFSRX1 \state_reg2 (.RN (n_80), .SN (1'b1), .CK (clock), .D
-       (n_73), .Q (state_8), .QN ());
-  DFFSRX1 \uscite_reg1 (.RN (n_80), .SN (1'b1), .CK (clock), .D
-       (n_72), .Q (uscite1), .QN ());
-  NAND2X2 g213(.A (n_69), .B (n_66), .Y (n_79));
-  NAND2X2 g218(.A (n_67), .B (n_58), .Y (n_77));
-  NAND2X2 g220(.A (n_71), .B (n_57), .Y (n_76));
-  NAND3X1 g219(.A (n_62), .B (n_49), .C (n_31), .Y (n_75));
-  INVX2 g215(.A (n_68), .Y (n_74));
-  NAND3X1 g223(.A (n_64), .B (n_43), .C (n_31), .Y (n_73));
-  NAND4X1 g211(.A (n_51), .B (n_37), .C (n_54), .D (n_46), .Y (n_72));
-  NOR2X1 g225(.A (n_42), .B (n_70), .Y (n_71));
-  DFFSRX1 \uscite_reg2 (.RN (n_80), .SN (1'b1), .CK (clock), .D
-       (n_70), .Q (uscite2), .QN ());
-  NAND2X1 g222(.A (n_56), .B (n_65), .Y (n_69));
-  NAND4X1 g216(.A (n_39), .B (n_41), .C (n_52), .D (n_45), .Y (n_68));
-  NOR2X1 g224(.A (n_63), .B (n_44), .Y (n_67));
-  AOI21X1 g217(.A0 (n_38), .A1 (n_65), .B0 (n_50), .Y (n_66));
-  INVX1 g231(.A (n_63), .Y (n_64));
-  NOR2X1 g234(.A (n_60), .B (n_53), .Y (n_62));
-  NAND2X2 g227(.A (n_84), .B (n_59), .Y (n_70));
-  NOR2X1 g230(.A (n_13), .B (n_60), .Y (n_61));
-  NAND2X1 g232(.A (n_55), .B (n_59), .Y (n_63));
-  AND2X1 g236(.A (n_47), .B (n_24), .Y (n_58));
-  AOI21X1 g237(.A0 (n_36), .A1 (eql), .B0 (n_26), .Y (n_57));
-  NAND4X1 g238(.A (n_55), .B (n_20), .C (n_33), .D (n_25), .Y (n_56));
-  NOR2X1 g228(.A (n_48), .B (n_34), .Y (n_54));
-  INVX1 g254(.A (n_52), .Y (n_53));
-  NOR2X1 g229(.A (n_23), .B (n_50), .Y (n_51));
-  NOR2X1 g235(.A (n_48), .B (n_50), .Y (n_49));
-  NAND2X1 g244(.A (n_26), .B (eql), .Y (n_47));
-  NOR2X1 g226(.A (n_19), .B (n_30), .Y (n_46));
-  NAND2X1 g248(.A (n_27), .B (eql), .Y (n_45));
-  INVX1 g249(.A (n_43), .Y (n_44));
-  INVX1 g252(.A (n_41), .Y (n_42));
-  NAND2X2 g255(.A (n_19), .B (n_1), .Y (n_52));
-  NAND3X1 g233(.A (n_28), .B (n_24), .C (n_32), .Y (n_38));
-  INVX1 g265(.A (n_36), .Y (n_37));
-  NAND4X1 g239(.A (n_83), .B (n_16), .C (n_3), .D (eql), .Y (n_59));
-  INVX1 g240(.A (n_34), .Y (n_84));
-  NAND2X1 g242(.A (n_33), .B (n_32), .Y (n_60));
-  INVX1 g245(.A (n_30), .Y (n_31));
-  NAND2X1 g250(.A (n_14), .B (eql), .Y (n_43));
-  NOR2X1 g251(.A (n_28), .B (eql), .Y (n_50));
-  NAND2X1 g253(.A (n_17), .B (eql), .Y (n_41));
-  INVX2 g258(.A (n_27), .Y (n_55));
-  INVX1 g262(.A (n_26), .Y (n_39));
-  INVX1 g266(.A (n_33), .Y (n_36));
-  NOR2X1 g241(.A (n_22), .B (eql), .Y (n_34));
-  NOR2X1 g243(.A (n_25), .B (eql), .Y (n_48));
-  NOR2X1 g247(.A (n_24), .B (eql), .Y (n_30));
-  INVX1 g256(.A (n_32), .Y (n_23));
-  INVX2 g259(.A (n_22), .Y (n_27));
-  INVX1 g263(.A (n_28), .Y (n_26));
-  INVX2 g272(.A (n_20), .Y (n_19));
-  NAND3X1 g267(.A (n_7), .B (n_16), .C (n_15), .Y (n_33));
-  NAND3X1 g264(.A (n_16), .B (n_9), .C (n_15), .Y (n_28));
-  NAND3X1 g260(.A (n_12), .B (n_10), .C (n_11), .Y (n_22));
-  INVX1 g269(.A (n_25), .Y (n_14));
-  INVX1 g268(.A (n_25), .Y (n_13));
-  NAND3X1 g273(.A (n_12), .B (n_16), .C (n_11), .Y (n_20));
-  NAND3X1 g257(.A (n_9), .B (n_10), .C (n_15), .Y (n_32));
-  INVX1 g275(.A (n_24), .Y (n_17));
-  NAND2X2 g270(.A (n_5), .B (n_10), .Y (n_25));
-  NAND3X1 g276(.A (n_0), .B (n_6), .C (n_15), .Y (n_24));
-  INVX1 g286(.A (n_7), .Y (n_83));
-  INVX2 g287(.A (n_9), .Y (n_7));
-  INVX2 g285(.A (n_6), .Y (n_12));
-  NOR2X1 g277(.A (n_2), .B (n_4), .Y (n_5));
-  INVX2 g288(.A (n_6), .Y (n_9));
-  INVX1 g283(.A (n_4), .Y (n_11));
-  INVX1 g281(.A (n_15), .Y (n_3));
-  INVX4 g289(.A (n_2), .Y (n_6));
-  INVX1 g278(.A (reset), .Y (n_80));
-  INVX1 g279(.A (eql), .Y (n_1));
-  INVX1 g292(.A (state_7), .Y (n_0));
-  INVX1 g284(.A (state_8), .Y (n_4));
-  INVX1 g291(.A (state_7), .Y (n_10));
-  INVX1 g282(.A (state_8), .Y (n_15));
-  INVX2 g290(.A (state), .Y (n_2));
-  INVX1 g280(.A (cont_eql), .Y (n_65));
-  CLKBUFX1 g293(.A (state_7), .Y (n_16));
-endmodule
-
-
-
-   'module',
-      'b06',
-      '(',
-       'cc_mux',
-        'eql',
-        'uscite',
-        'clock',
-        'enable_count',
-        'ackout',
-        'reset',
-        'cont_eql',
-      ')',
-      ';',
-     'input', 'eql', 'clock', 'reset', 'cont_eql', ';',
-      'output', '', '2', ':', '1', '', 'cc_mux', 'uscite', ';',
-      'output', 'enable_count', 'ackout', ';',
-      'wire', 'eql', 'clock', 'reset', 'cont_eql', ';',
-      'wire', '', '2', ':', '1', '', 'cc_mux', 'uscite', ';',
-      'wire', 'enable_count', 'ackout', ';',
-       'wire',
-        'n_0', 'n_1', 'n_2', 'n_3', 'n_4', 'n_5', 'n_6', 'n_7',
-        ';',
-       'wire',
-        'n_9', 'n_10', 'n_11', 'n_12', 'n_13', 'n_14', 'n_15', 'n_16',
-        ';',
-       'wire',
-        'n_17', 'n_19', 'n_20', 'n_22', 'n_23', 'n_24', 'n_25', 'n_26',
-        ';',
-       'wire',
-        'n_27', 'n_28', 'n_30', 'n_31', 'n_32', 'n_33', 'n_34', 'n_36',
-        ';',
-       'wire',
-        'n_37', 'n_38', 'n_39', 'n_41', 'n_42', 'n_43', 'n_44', 'n_45',
-        ';',
-       'wire',
-        'n_46', 'n_47', 'n_48', 'n_49', 'n_50', 'n_51', 'n_52', 'n_53',
-        ';',
-       'wire',
-        'n_54', 'n_55', 'n_56', 'n_57', 'n_58', 'n_59', 'n_60', 'n_61',
-        ';',
-       'wire',
-        'n_62', 'n_63', 'n_64', 'n_65', 'n_66', 'n_67', 'n_68', 'n_69',
-        ';',
-       'wire',
-        'n_70', 'n_71', 'n_72', 'n_73', 'n_74', 'n_75', 'n_76', 'n_77',
-        ';',
-       'wire',
-         'n_78',
-          'n_79',
-          'n_80',
-          'n_83',
-          'n_84',
-          'state',
-          'state_7',
-          'state_8',
-        ';',
-       'DFFSRX1',
-         'cc_mux_reg1',
-           '(',
-            '.RN', '(', 'n_80', ')',
-            '.SN', '(', "1 'b 1", ')',
-            '.CK', '(', 'clock', ')',
-            '.D', '(', 'n_78', ')',
-            '.Q', '(', 'cc_mux', '', '1', '', ')',
-            '.QN', '(', ')',
-            ')',
-        ';',
-       'DFFSRX1',
-         'enable_count_reg',
-           '(',
-            '.RN', '(', 'n_80', ')',
-            '.SN', '(', "1 'b 1", ')',
-            '.CK', '(', 'clock', ')',
-            '.D', '(', 'n_79', ')',
-            '.Q', '(', 'enable_count', ')',
-            '.QN', '(', ')',
-            ')',
-        ';',
-       'DFFSRX1',
-         'ackout_reg',
-           '(',
-            '.RN', '(', 'n_80', ')',
-            '.SN', '(', "1 'b 1", ')',
-            '.CK', '(', 'clock', ')',
-            '.D', '(', 'n_79', ')',
-            '.Q', '(', 'ackout', ')',
-            '.QN', '(', ')',
-            ')',
-        ';',
-       'DFFSRX1',
-         'cc_mux_reg2',
-           '(',
-            '.RN', '(', 'n_80', ')',
-            '.SN', '(', "1 'b 1", ')',
-            '.CK', '(', 'clock', ')',
-            '.D', '(', 'n_77', ')',
-            '.Q', '(', 'cc_mux', '', '2', '', ')',
-            '.QN', '(', ')',
-            ')',
-        ';',
-       'DFFSRX1',
-         'state_reg1',
-           '(',
-            '.RN', '(', 'n_80', ')',
-            '.SN', '(', "1 'b 1", ')',
-            '.CK', '(', 'clock', ')',
-            '.D', '(', 'n_76', ')',
-            '.Q', '(', 'state_7', ')',
-            '.QN', '(', ')',
-            ')',
-        ';',
-       'NAND2X2',
-         'g212',
-           '(',
-            '.A', '(', 'n_74', ')',
-            '.B', '(', 'n_61', ')',
-            '.Y', '(', 'n_78', ')',
-            ')',
-        ';',
-       'DFFSRX1',
-         'state_reg0',
-           '(',
-            '.RN', '(', 'n_80', ')',
-            '.SN', '(', "1 'b 1", ')',
-            '.CK', '(', 'clock', ')',
-            '.D', '(', 'n_75', ')',
-            '.Q', '(', 'state', ')',
-            '.QN', '(', ')',
-            ')',
-        ';',
-       'DFFSRX1',
-         'state_reg2',
-           '(',
-            '.RN', '(', 'n_80', ')',
-            '.SN', '(', "1 'b 1", ')',
-            '.CK', '(', 'clock', ')',
-            '.D', '(', 'n_73', ')',
-            '.Q', '(', 'state_8', ')',
-            '.QN', '(', ')',
-            ')',
-        ';',
-       'DFFSRX1',
-         'uscite_reg1',
-           '(',
-            '.RN', '(', 'n_80', ')',
-            '.SN', '(', "1 'b 1", ')',
-            '.CK', '(', 'clock', ')',
-            '.D', '(', 'n_72', ')',
-            '.Q', '(', 'uscite', '', '1', '', ')',
-            '.QN', '(', ')',
-            ')',
-        ';',
-       'NAND2X2',
-         'g213',
-           '(',
-            '.A', '(', 'n_69', ')',
-            '.B', '(', 'n_66', ')',
-            '.Y', '(', 'n_79', ')',
-            ')',
-        ';',
-       'NAND2X2',
-         'g218',
-           '(',
-            '.A', '(', 'n_67', ')',
-            '.B', '(', 'n_58', ')',
-            '.Y', '(', 'n_77', ')',
-            ')',
-        ';',
-       'NAND2X2',
-         'g220',
-           '(',
-            '.A', '(', 'n_71', ')',
-            '.B', '(', 'n_57', ')',
-            '.Y', '(', 'n_76', ')',
-            ')',
-        ';',
-       'NAND3X1',
-         'g219',
-           '(',
-            '.A', '(', 'n_62', ')',
-            '.B', '(', 'n_49', ')',
-            '.C', '(', 'n_31', ')',
-            '.Y', '(', 'n_75', ')',
-            ')',
-        ';',
-       'INVX2',
-         'g215',
-           '(',
-            '.A', '(', 'n_68', ')',
-            '.Y', '(', 'n_74', ')',
-            ')',
-        ';',
-       'NAND3X1',
-         'g223',
-           '(',
-            '.A', '(', 'n_64', ')',
-            '.B', '(', 'n_43', ')',
-            '.C', '(', 'n_31', ')',
-            '.Y', '(', 'n_73', ')',
-            ')',
-        ';',
-       'NAND4X1',
-         'g211',
-           '(',
-            '.A', '(', 'n_51', ')',
-            '.B', '(', 'n_37', ')',
-            '.C', '(', 'n_54', ')',
-            '.D', '(', 'n_46', ')',
-            '.Y', '(', 'n_72', ')',
-            ')',
-        ';',
-       'NOR2X1',
-         'g225',
-           '(',
-            '.A', '(', 'n_42', ')',
-            '.B', '(', 'n_70', ')',
-            '.Y', '(', 'n_71', ')',
-            ')',
-        ';',
-       'DFFSRX1',
-         'uscite_reg2',
-           '(',
-            '.RN', '(', 'n_80', ')',
-            '.SN', '(', "1 'b 1", ')',
-            '.CK', '(', 'clock', ')',
-            '.D', '(', 'n_70', ')',
-            '.Q', '(', 'uscite', '', '2', '', ')',
-            '.QN', '(', ')',
-            ')',
-        ';',
-       'NAND2X1',
-         'g222',
-           '(',
-            '.A', '(', 'n_56', ')',
-            '.B', '(', 'n_65', ')',
-            '.Y', '(', 'n_69', ')',
-            ')',
-        ';',
-       'NAND4X1',
-         'g216',
-           '(',
-            '.A', '(', 'n_39', ')',
-            '.B', '(', 'n_41', ')',
-            '.C', '(', 'n_52', ')',
-            '.D', '(', 'n_45', ')',
-            '.Y', '(', 'n_68', ')',
-            ')',
-        ';',
-       'NOR2X1',
-         'g224',
-           '(',
-            '.A', '(', 'n_63', ')',
-            '.B', '(', 'n_44', ')',
-            '.Y', '(', 'n_67', ')',
-            ')',
-        ';',
-       'AOI21X1',
-         'g217',
-           '(',
-            '.A0', '(', 'n_38', ')',
-            '.A1', '(', 'n_65', ')',
-            '.B0', '(', 'n_50', ')',
-            '.Y', '(', 'n_66', ')',
-            ')',
-        ';',
-       'INVX1',
-         'g231',
-           '(',
-            '.A', '(', 'n_63', ')',
-            '.Y', '(', 'n_64', ')',
-            ')',
-        ';',
-       'NOR2X1',
-         'g234',
-           '(',
-            '.A', '(', 'n_60', ')',
-            '.B', '(', 'n_53', ')',
-            '.Y', '(', 'n_62', ')',
-            ')',
-        ';',
-       'NAND2X2',
-         'g227',
-           '(',
-            '.A', '(', 'n_84', ')',
-            '.B', '(', 'n_59', ')',
-            '.Y', '(', 'n_70', ')',
-            ')',
-        ';',
-       'NOR2X1',
-         'g230',
-           '(',
-            '.A', '(', 'n_13', ')',
-            '.B', '(', 'n_60', ')',
-            '.Y', '(', 'n_61', ')',
-            ')',
-        ';',
-       'NAND2X1',
-         'g232',
-           '(',
-            '.A', '(', 'n_55', ')',
-            '.B', '(', 'n_59', ')',
-            '.Y', '(', 'n_63', ')',
-            ')',
-        ';',
-       'AND2X1',
-         'g236',
-           '(',
-            '.A', '(', 'n_47', ')',
-            '.B', '(', 'n_24', ')',
-            '.Y', '(', 'n_58', ')',
-            ')',
-        ';',
-       'AOI21X1',
-         'g237',
-           '(',
-            '.A0', '(', 'n_36', ')',
-            '.A1', '(', 'eql', ')',
-            '.B0', '(', 'n_26', ')',
-            '.Y', '(', 'n_57', ')',
-            ')',
-        ';',
-       'NAND4X1',
-         'g238',
-           '(',
-            '.A', '(', 'n_55', ')',
-            '.B', '(', 'n_20', ')',
-            '.C', '(', 'n_33', ')',
-            '.D', '(', 'n_25', ')',
-            '.Y', '(', 'n_56', ')',
-            ')',
-        ';',
-       'NOR2X1',
-         'g228',
-           '(',
-            '.A', '(', 'n_48', ')',
-            '.B', '(', 'n_34', ')',
-            '.Y', '(', 'n_54', ')',
-            ')',
-        ';',
-       'INVX1',
-         'g254',
-           '(',
-            '.A', '(', 'n_52', ')',
-            '.Y', '(', 'n_53', ')',
-            ')',
-        ';',
-       'NOR2X1',
-         'g229',
-           '(',
-            '.A', '(', 'n_23', ')',
-            '.B', '(', 'n_50', ')',
-            '.Y', '(', 'n_51', ')',
-            ')',
-        ';',
-       'NOR2X1',
-         'g235',
-           '(',
-            '.A', '(', 'n_48', ')',
-            '.B', '(', 'n_50', ')',
-            '.Y', '(', 'n_49', ')',
-            ')',
-        ';',
-       'NAND2X1',
-         'g244',
-           '(',
-            '.A', '(', 'n_26', ')',
-            '.B', '(', 'eql', ')',
-            '.Y', '(', 'n_47', ')',
-            ')',
-        ';',
-       'NOR2X1',
-         'g226',
-           '(',
-            '.A', '(', 'n_19', ')',
-            '.B', '(', 'n_30', ')',
-            '.Y', '(', 'n_46', ')',
-            ')',
-        ';',
-       'NAND2X1',
-         'g248',
-           '(',
-            '.A', '(', 'n_27', ')',
-            '.B', '(', 'eql', ')',
-            '.Y', '(', 'n_45', ')',
-            ')',
-        ';',
-       'INVX1',
-         'g249',
-           '(',
-            '.A', '(', 'n_43', ')',
-            '.Y', '(', 'n_44', ')',
-            ')',
-        ';',
-       'INVX1',
-         'g252',
-           '(',
-            '.A', '(', 'n_41', ')',
-            '.Y', '(', 'n_42', ')',
-            ')',
-        ';',
-       'NAND2X2',
-         'g255',
-           '(',
-            '.A', '(', 'n_19', ')',
-            '.B', '(', 'n_1', ')',
-            '.Y', '(', 'n_52', ')',
-            ')',
-        ';',
-       'NAND3X1',
-         'g233',
-           '(',
-            '.A', '(', 'n_28', ')',
-            '.B', '(', 'n_24', ')',
-            '.C', '(', 'n_32', ')',
-            '.Y', '(', 'n_38', ')',
-            ')',
-        ';',
-       'INVX1',
-         'g265',
-           '(',
-            '.A', '(', 'n_36', ')',
-            '.Y', '(', 'n_37', ')',
-            ')',
-        ';',
-       'NAND4X1',
-         'g239',
-           '(',
-            '.A', '(', 'n_83', ')',
-            '.B', '(', 'n_16', ')',
-            '.C', '(', 'n_3', ')',
-            '.D', '(', 'eql', ')',
-            '.Y', '(', 'n_59', ')',
-            ')',
-        ';',
-       'INVX1',
-         'g240',
-           '(',
-            '.A', '(', 'n_34', ')',
-            '.Y', '(', 'n_84', ')',
-            ')',
-        ';',
-       'NAND2X1',
-         'g242',
-           '(',
-            '.A', '(', 'n_33', ')',
-            '.B', '(', 'n_32', ')',
-            '.Y', '(', 'n_60', ')',
-            ')',
-        ';',
-       'INVX1',
-         'g245',
-           '(',
-            '.A', '(', 'n_30', ')',
-            '.Y', '(', 'n_31', ')',
-            ')',
-        ';',
-       'NAND2X1',
-         'g250',
-           '(',
-            '.A', '(', 'n_14', ')',
-            '.B', '(', 'eql', ')',
-            '.Y', '(', 'n_43', ')',
-            ')',
-        ';',
-       'NOR2X1',
-         'g251',
-           '(',
-            '.A', '(', 'n_28', ')',
-            '.B', '(', 'eql', ')',
-            '.Y', '(', 'n_50', ')',
-            ')',
-        ';',
-       'NAND2X1',
-         'g253',
-           '(',
-            '.A', '(', 'n_17', ')',
-            '.B', '(', 'eql', ')',
-            '.Y', '(', 'n_41', ')',
-            ')',
-        ';',
-       'INVX2',
-         'g258',
-           '(',
-            '.A', '(', 'n_27', ')',
-            '.Y', '(', 'n_55', ')',
-            ')',
-        ';',
-       'INVX1',
-         'g262',
-           '(',
-            '.A', '(', 'n_26', ')',
-            '.Y', '(', 'n_39', ')',
-            ')',
-        ';',
-       'INVX1',
-         'g266',
-           '(',
-            '.A', '(', 'n_33', ')',
-            '.Y', '(', 'n_36', ')',
-            ')',
-        ';',
-       'NOR2X1',
-         'g241',
-           '(',
-            '.A', '(', 'n_22', ')',
-            '.B', '(', 'eql', ')',
-            '.Y', '(', 'n_34', ')',
-            ')',
-        ';',
-       'NOR2X1',
-         'g243',
-           '(',
-            '.A', '(', 'n_25', ')',
-            '.B', '(', 'eql', ')',
-            '.Y', '(', 'n_48', ')',
-            ')',
-        ';',
-       'NOR2X1',
-         'g247',
-           '(',
-            '.A', '(', 'n_24', ')',
-            '.B', '(', 'eql', ')',
-            '.Y', '(', 'n_30', ')',
-            ')',
-        ';',
-       'INVX1',
-         'g256',
-           '(',
-            '.A', '(', 'n_32', ')',
-            '.Y', '(', 'n_23', ')',
-            ')',
-        ';',
-       'INVX2',
-         'g259',
-           '(',
-            '.A', '(', 'n_22', ')',
-            '.Y', '(', 'n_27', ')',
-            ')',
-        ';',
-       'INVX1',
-         'g263',
-           '(',
-            '.A', '(', 'n_28', ')',
-            '.Y', '(', 'n_26', ')',
-            ')',
-        ';',
-       'INVX2',
-         'g272',
-           '(',
-            '.A', '(', 'n_20', ')',
-            '.Y', '(', 'n_19', ')',
-            ')',
-        ';',
-       'NAND3X1',
-         'g267',
-           '(',
-            '.A', '(', 'n_7', ')',
-            '.B', '(', 'n_16', ')',
-            '.C', '(', 'n_15', ')',
-            '.Y', '(', 'n_33', ')',
-            ')',
-        ';',
-       'NAND3X1',
-         'g264',
-           '(',
-            '.A', '(', 'n_16', ')',
-            '.B', '(', 'n_9', ')',
-            '.C', '(', 'n_15', ')',
-            '.Y', '(', 'n_28', ')',
-            ')',
-        ';',
-       'NAND3X1',
-         'g260',
-           '(',
-            '.A', '(', 'n_12', ')',
-            '.B', '(', 'n_10', ')',
-            '.C', '(', 'n_11', ')',
-            '.Y', '(', 'n_22', ')',
-            ')',
-        ';',
-       'INVX1',
-         'g269',
-           '(',
-            '.A', '(', 'n_25', ')',
-            '.Y', '(', 'n_14', ')',
-            ')',
-        ';',
-       'INVX1',
-         'g268',
-           '(',
-            '.A', '(', 'n_25', ')',
-            '.Y', '(', 'n_13', ')',
-            ')',
-        ';',
-       'NAND3X1',
-         'g273',
-           '(',
-            '.A', '(', 'n_12', ')',
-            '.B', '(', 'n_16', ')',
-            '.C', '(', 'n_11', ')',
-            '.Y', '(', 'n_20', ')',
-            ')',
-        ';',
-       'NAND3X1',
-         'g257',
-           '(',
-            '.A', '(', 'n_9', ')',
-            '.B', '(', 'n_10', ')',
-            '.C', '(', 'n_15', ')',
-            '.Y', '(', 'n_32', ')',
-            ')',
-        ';',
-       'INVX1',
-         'g275',
-           '(',
-            '.A', '(', 'n_24', ')',
-            '.Y', '(', 'n_17', ')',
-            ')',
-        ';',
-       'NAND2X2',
-         'g270',
-           '(',
-            '.A', '(', 'n_5', ')',
-            '.B', '(', 'n_10', ')',
-            '.Y', '(', 'n_25', ')',
-            ')',
-        ';',
-       'NAND3X1',
-         'g276',
-           '(',
-            '.A', '(', 'n_0', ')',
-            '.B', '(', 'n_6', ')',
-            '.C', '(', 'n_15', ')',
-            '.Y', '(', 'n_24', ')',
-            ')',
-        ';',
-       'INVX1',
-         'g286',
-           '(',
-            '.A', '(', 'n_7', ')',
-            '.Y', '(', 'n_83', ')',
-            ')',
-        ';',
-       'INVX2',
-         'g287',
-          '(', '.A', '(', 'n_9', ')', '.Y', '(', 'n_7', ')', ')',
-        ';',
-       'INVX2',
-         'g285',
-           '(',
-            '.A', '(', 'n_6', ')',
-            '.Y', '(', 'n_12', ')',
-            ')',
-        ';',
-       'NOR2X1',
-         'g277',
-           '(',
-            '.A', '(', 'n_2', ')',
-            '.B', '(', 'n_4', ')',
-            '.Y', '(', 'n_5', ')',
-            ')',
-        ';',
-       'INVX2',
-         'g288',
-          '(', '.A', '(', 'n_6', ')', '.Y', '(', 'n_9', ')', ')',
-        ';',
-       'INVX1',
-         'g283',
-           '(',
-            '.A', '(', 'n_4', ')',
-            '.Y', '(', 'n_11', ')',
-            ')',
-        ';',
-       'INVX1',
-         'g281',
-           '(',
-            '.A', '(', 'n_15', ')',
-            '.Y', '(', 'n_3', ')',
-            ')',
-        ';',
-       'INVX4',
-         'g289',
-          '(', '.A', '(', 'n_2', ')', '.Y', '(', 'n_6', ')', ')',
-        ';',
-       'INVX1',
-         'g278',
-           '(',
-            '.A', '(', 'reset', ')',
-            '.Y', '(', 'n_80', ')',
-            ')',
-        ';',
-       'INVX1',
-         'g279',
-          '(', '.A', '(', 'eql', ')', '.Y', '(', 'n_1', ')', ')',
-        ';',
-       'INVX1',
-         'g292',
-           '(',
-            '.A', '(', 'state_7', ')',
-            '.Y', '(', 'n_0', ')',
-            ')',
-        ';',
-       'INVX1',
-         'g284',
-           '(',
-            '.A', '(', 'state_8', ')',
-            '.Y', '(', 'n_4', ')',
-            ')',
-        ';',
-       'INVX1',
-         'g291',
-           '(',
-            '.A', '(', 'state_7', ')',
-            '.Y', '(', 'n_10', ')',
-            ')',
-        ';',
-       'INVX1',
-         'g282',
-           '(',
-            '.A', '(', 'state_8', ')',
-            '.Y', '(', 'n_15', ')',
-            ')',
-        ';',
-       'INVX2',
-         'g290',
-           '(',
-            '.A', '(', 'state', ')',
-            '.Y', '(', 'n_2', ')',
-            ')',
-        ';',
-       'INVX1',
-         'g280',
-           '(',
-            '.A', '(', 'cont_eql', ')',
-            '.Y', '(', 'n_65', ')',
-            ')',
-        ';',
-       'CLKBUFX1',
-         'g293',
-           '(',
-            '.A', '(', 'state_7', ')',
-            '.Y', '(', 'n_16', ')',
-            ')',
-        ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/new3/parseOutput/b10.v.parsed.txt Deleted

@@ -1,3384 +0,0 @@
-//
-//  ITC99 Benchmark
-//  Downloaded from http://www.cad.polito.it/tools/itc99.html
-//  
-//  ----------------------------------------------------------------------
-//  
-//  This netlist was generated with Cadence RTL Compiler in a quick 
-//  synthesis run.
-//  
-//  ----------------------------------------------------------------------
-//  
-//  Copyright (C) 1999
-//  Fulvio Corno, Matteo Sonze Reorda, Giovanni Squillero
-//  Politecnico di Torino
-//  
-//  This source file may be used and distributed without restriction
-//  provided that this copyright statement is not removed from the
-//  file and that any derivative work contains the original copyright
-//  notice and the associated disclaimer.
-//  
-//  This source file is free software; you can redistribute it and/or
-//  modify it under the terms of the GNU General Public License as
-//  published by the Free Software Foundation.
-//  
-//  This source is distributed in the hope that it will be useful,
-//  but WITHOUT ANY WARRANTY; without even the implied warranty of
-//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-//  General Public License for more details.
-//  
-//  You should have received a copy of the GNU General Public License
-//  along with this source; if not, download it from
-//  http://www.gnu.org/copyleft/gpl.html
-//  
-
-// Generated by Cadence RTL Compiler (RC) v05.10-b006_1
-
-module b10(r_button, g_button, key, start, reset, test, cts, ctr, rts,
-     rtr, clock, v_in, v_out);
-  input r_button, g_button, key, start, reset, test, rts, rtr, clock;
-  input 3:0 v_in;
-  output cts, ctr;
-  output 3:0 v_out;
-  wire r_button, g_button, key, start, reset, test, rts, rtr, clock;
-  wire 3:0 v_in;
-  wire cts, ctr;
-  wire 3:0 v_out;
-  wire n_1, n_2, n_4, n_5, n_6, n_7, n_8, n_9;
-  wire n_12, n_13, n_15, n_16, n_17, n_18, n_20, n_21;
-  wire n_22, n_24, n_27, n_29, n_30, n_31, n_33, n_34;
-  wire n_35, n_36, n_37, n_38, n_39, n_45, n_46, n_47;
-  wire n_49, n_57, n_59, n_60, n_61, n_63, n_67, n_72;
-  wire n_73, n_74, n_75, n_77, n_78, n_79, n_80, n_85;
-  wire n_86, n_87, n_89, n_90, n_91, n_92, n_94, n_95;
-  wire n_96, n_97, n_98, n_99, n_103, n_104, n_110, n_111;
-  wire n_112, n_113, n_115, n_120, n_121, n_122, n_123, n_124;
-  wire n_125, n_126, n_127, n_128, n_131, n_132, n_133, n_135;
-  wire n_137, n_138, n_140, n_141, n_142, n_145, n_148, n_149;
-  wire n_150, n_151, n_152, n_153, n_154, n_155, n_156, n_161;
-  wire n_162, n_163, n_165, n_166, n_167, n_168, n_169, n_171;
-  wire n_174, n_175, n_176, n_178, n_179, n_180, n_181, n_182;
-  wire n_183, n_184, n_186, n_188, n_189, n_190, n_191, n_192;
-  wire n_194, n_195, n_196, n_197, n_199, n_200, n_201, n_203;
-  wire n_204, n_205, n_206, n_207, n_208, n_209, n_210, n_211;
-  wire n_212, n_213, n_214, n_215, n_218, n_219, n_220, n_221;
-  wire n_222, n_223, n_224, n_225, n_226, n_227, n_228, n_229;
-  wire n_230, n_231, n_233, n_235, n_238, n_241, n_243, n_244;
-  wire n_245, n_246, n_247, n_248, n_249, n_250, n_251, n_252;
-  wire n_254, n_255, n_256, n_257, n_258, n_259, n_260, n_261;
-  wire n_262, n_263, n_264, n_265, n_266, n_267, n_268, n_269;
-  wire n_270, n_271, n_274, n_276, n_277, n_279, n_280, n_281;
-  wire n_282, n_284, n_285, n_286, n_287, n_288, n_289, n_292;
-  wire n_293, n_294, n_295, n_297, n_300, n_301, n_302, n_303;
-  wire n_304, n_305, n_307, n_309, n_310, n_311, n_312, n_313;
-  wire n_314, n_315, n_316, n_317, n_318, n_319, n_320, n_322;
-  wire n_323, n_324, n_325, n_328, n_329, n_330, n_331, n_332;
-  wire n_333, n_335, n_336, n_337, n_338, n_339, n_340, n_348;
-  wire n_350, n_351, n_352, n_358, n_377, n_381, n_388, n_389;
-  wire n_391, n_392, n_397, n_398, n_399, n_400, n_401, n_402;
-  wire n_403, n_404, n_405, n_406, n_407, n_408, n_409, n_411;
-  wire n_412, n_413, n_414, n_415, n_416, n_430, n_431, n_432;
-  wire n_433, n_441, n_442, n_443, n_444, n_445, n_446, n_447;
-  wire n_449, n_451, n_453, n_454, n_455, n_456, n_457, n_458;
-  wire n_459, n_460, n_461, n_462, n_463, n_464, n_465, n_466;
-  wire n_467, n_468, n_469, n_470, stato, stato_5, stato_6, stato_7;
-  wire voto2;
-  DFFSRX1 \stato_reg2 (.RN (n_340), .SN (1'b1), .CK (clock), .D
-       (n_339), .Q (stato_6), .QN ());
-  DFFSRX1 \stato_reg0 (.RN (n_340), .SN (1'b1), .CK (clock), .D
-       (n_446), .Q (stato), .QN ());
-  DFFSRX1 voto1_reg(.RN (n_340), .SN (1'b1), .CK (clock), .D (n_336),
-       .Q (n_178), .QN ());
-  DFFSRX1 \stato_reg1 (.RN (n_340), .SN (1'b1), .CK (clock), .D
-       (n_333), .Q (stato_5), .QN ());
-  DFFSRX1 \v_out_reg2 (.RN (n_340), .SN (1'b1), .CK (clock), .D
-       (n_337), .Q (v_out2), .QN ());
-  DFFSRX1 \v_out_reg3 (.RN (n_340), .SN (1'b1), .CK (clock), .D
-       (n_332), .Q (v_out3), .QN ());
-  DFFSRX1 cts_reg(.RN (n_340), .SN (1'b1), .CK (clock), .D (n_335), .Q
-       (cts), .QN ());
-  DFFSRX1 \v_out_reg0 (.RN (n_340), .SN (1'b1), .CK (clock), .D
-       (n_331), .Q (v_out0), .QN ());
-  DFFSRX1 \v_out_reg1 (.RN (n_340), .SN (1'b1), .CK (clock), .D
-       (n_338), .Q (v_out1), .QN ());
-  OR4X1 g1181(.A (n_189), .B (n_238), .C (n_195), .D (n_324), .Y
-       (n_339));
-  DFFSRX1 last_g_reg(.RN (n_340), .SN (1'b1), .CK (clock), .D (n_330),
-       .Q (n_300), .QN ());
-  DFFSRX1 last_r_reg(.RN (n_340), .SN (1'b1), .CK (clock), .D (n_329),
-       .Q (n_38), .QN ());
-  DFFSRX1 \sign_reg3 (.RN (n_340), .SN (1'b1), .CK (clock), .D
-       (n_328), .Q (n_286), .QN ());
-  DFFSRX1 ctr_reg(.RN (n_340), .SN (1'b1), .CK (clock), .D (n_416), .Q
-       (ctr), .QN ());
-  NAND2X2 g1210(.A (n_316), .B (n_260), .Y (n_338));
-  NAND2X2 g1211(.A (n_315), .B (n_264), .Y (n_337));
-  DFFSRX1 voto2_reg(.RN (n_340), .SN (1'b1), .CK (clock), .D (n_325),
-       .Q (voto2), .QN ());
-  DFFSRX1 \stato_reg3 (.RN (n_340), .SN (1'b1), .CK (clock), .D
-       (n_323), .Q (stato_7), .QN ());
-  NAND2X1 g1199(.A (n_467), .B (n_468), .Y (n_336));
-  NAND3X1 g1216(.A (n_313), .B (n_254), .C (n_271), .Y (n_335));
-  NAND3X1 g1202(.A (n_322), .B (n_305), .C (n_209), .Y (n_333));
-  NAND2X2 g1205(.A (n_320), .B (n_263), .Y (n_332));
-  NAND2X2 g1209(.A (n_319), .B (n_261), .Y (n_331));
-  DFFSRX1 voto3_reg(.RN (n_340), .SN (1'b1), .CK (clock), .D (n_309),
-       .Q (n_27), .QN ());
-  NAND3X1 g1217(.A (n_312), .B (n_301), .C (n_225), .Y (n_330));
-  NAND3X1 g1218(.A (n_311), .B (n_279), .C (n_222), .Y (n_329));
-  NAND2X1 g1208(.A (n_351), .B (n_352), .Y (n_328));
-  DFFSRX1 voto0_reg(.RN (n_340), .SN (1'b1), .CK (clock), .D (n_302),
-       .Q (n_47), .QN ());
-  NAND4X1 g1200(.A (n_274), .B (n_250), .C (n_281), .D (n_282), .Y
-       (n_325));
-  OAI21X1 g1214(.A0 (n_196), .A1 (n_74), .B0 (n_297), .Y (n_324));
-  NAND4X1 g1201(.A (n_247), .B (n_205), .C (n_303), .D (n_265), .Y
-       (n_323));
-  AOI21X1 g1221(.A0 (n_86), .A1 (n_175), .B0 (n_304), .Y (n_322));
-  INVX1 g1203(.A (n_307), .Y (n_467));
-  AOI22X1 g1231(.A0 (n_318), .A1 (v_out3), .B0 (n_317), .B1
-       (v_out3), .Y (n_320));
-  AOI22X1 g1232(.A0 (n_318), .A1 (v_out0), .B0 (n_317), .B1
-       (v_out0), .Y (n_319));
-  AOI22X1 g1233(.A0 (n_314), .A1 (v_out1), .B0 (n_317), .B1
-       (v_out1), .Y (n_316));
-  AOI22X1 g1234(.A0 (n_314), .A1 (v_out2), .B0 (n_317), .B1
-       (v_out2), .Y (n_315));
-  AOI22X1 g1235(.A0 (n_433), .A1 (cts), .B0 (n_169), .B1 (cts), .Y
-       (n_313));
-  OAI21X1 g1237(.A0 (n_258), .A1 (n_310), .B0 (n_300), .Y (n_312));
-  OAI21X1 g1238(.A0 (n_257), .A1 (n_310), .B0 (n_38), .Y (n_311));
-  NAND3X1 g1212(.A (n_289), .B (n_268), .C (n_267), .Y (n_309));
-  AOI22X1 g1247(.A0 (n_255), .A1 (n_286), .B0 (n_358), .B1 (n_286), .Y
-       (n_352));
-  NAND4X1 g1204(.A (n_252), .B (n_284), .C (n_231), .D (n_245), .Y
-       (n_307));
-  NOR2X1 g1227(.A (n_288), .B (n_285), .Y (n_351));
-  AOI21X1 g1230(.A0 (n_407), .A1 (n_269), .B0 (n_295), .Y (n_305));
-  NAND2X1 g1245(.A (n_270), .B (n_303), .Y (n_304));
-  NAND4X1 g1219(.A (n_277), .B (n_201), .C (n_233), .D (n_211), .Y
-       (n_302));
-  NAND2X1 g1264(.A (n_259), .B (n_300), .Y (n_301));
-  NOR2X1 g1226(.A (n_243), .B (n_280), .Y (n_297));
-  NAND3X1 g1236(.A (n_469), .B (n_194), .C (n_294), .Y (n_295));
-  NAND2X1 g1257(.A (n_293), .B (n_292), .Y (n_318));
-  NAND2X1 g1259(.A (n_293), .B (n_292), .Y (n_314));
-  AOI22X1 g1229(.A0 (n_276), .A1 (n_27), .B0 (n_112), .B1 (n_251), .Y
-       (n_289));
-  AND2X1 g1294(.A (n_287), .B (n_286), .Y (n_288));
-  OAI21X1 g1240(.A0 (n_181), .A1 (n_18), .B0 (n_149), .Y (n_285));
-  INVX1 g1241(.A (n_248), .Y (n_284));
-  AOI21X1 g1243(.A0 (n_59), .A1 (n_407), .B0 (n_213), .Y (n_282));
-  AOI21X1 g1244(.A0 (n_266), .A1 (voto2), .B0 (n_208), .Y (n_281));
-  NAND4X1 g1246(.A (n_165), .B (n_294), .C (n_162), .D (n_152), .Y
-       (n_280));
-  OAI21X1 g1250(.A0 (n_226), .A1 (n_453), .B0 (n_38), .Y (n_279));
-  NAND2X1 g1251(.A (n_276), .B (n_47), .Y (n_277));
-  NAND2X1 g1253(.A (n_276), .B (n_244), .Y (n_468));
-  NAND2X1 g1255(.A (n_276), .B (voto2), .Y (n_274));
-  OAI21X1 g1262(.A0 (n_317), .A1 (n_407), .B0 (cts), .Y (n_271));
-  NAND2X1 g1265(.A (n_203), .B (n_269), .Y (n_270));
-  AOI21X1 g1266(.A0 (n_89), .A1 (n_249), .B0 (n_408), .Y (n_268));
-  AOI21X1 g1268(.A0 (n_266), .A1 (n_27), .B0 (n_229), .Y (n_267));
-  AOI21X1 g1269(.A0 (n_230), .A1 (n_154), .B0 (n_235), .Y (n_265));
-  AOI21X1 g1271(.A0 (n_262), .A1 (v_out2), .B0 (n_228), .Y (n_264));
-  AOI21X1 g1272(.A0 (n_262), .A1 (v_out3), .B0 (n_224), .Y (n_263));
-  AOI21X1 g1273(.A0 (n_262), .A1 (v_out0), .B0 (n_220), .Y (n_261));
-  AOI21X1 g1274(.A0 (n_262), .A1 (v_out1), .B0 (n_219), .Y (n_260));
-  NAND2X1 g1277(.A (n_292), .B (n_392), .Y (n_259));
-  NAND2X1 g1285(.A (n_227), .B (n_256), .Y (n_258));
-  NAND2X1 g1290(.A (n_292), .B (n_256), .Y (n_257));
-  NAND2X1 g1293(.A (n_207), .B (n_292), .Y (n_255));
-  AOI21X1 g1300(.A0 (rtr), .A1 (n_175), .B0 (n_192), .Y (n_254));
-  AOI22X1 g1303(.A0 (n_249), .A1 (n_90), .B0 (n_251), .B1 (n_178), .Y
-       (n_252));
-  AOI22X1 g1304(.A0 (n_249), .A1 (n_80), .B0 (n_251), .B1 (voto2), .Y
-       (n_250));
-  OAI21X1 g1242(.A0 (n_212), .A1 (n_127), .B0 (n_167), .Y (n_248));
-  AOI21X1 g1215(.A0 (n_171), .A1 (n_246), .B0 (n_184), .Y (n_247));
-  NAND2X1 g1329(.A (n_389), .B (n_191), .Y (n_287));
-  NAND2X1 g1254(.A (n_183), .B (n_244), .Y (n_245));
-  NAND2X1 g1352(.A (n_389), .B (n_432), .Y (n_243));
-  INVX1 g1224(.A (n_210), .Y (n_241));
-  INVX1 g1288(.A (n_206), .Y (n_238));
-  NOR2X1 g1292(.A (n_453), .B (n_358), .Y (n_293));
-  OAI21X1 g1298(.A0 (n_256), .A1 (test), .B0 (n_168), .Y (n_235));
-  NAND2X1 g1299(.A (n_166), .B (n_269), .Y (n_469));
-  AOI22X1 g1301(.A0 (n_249), .A1 (n_94), .B0 (n_47), .B1 (n_460), .Y
-       (n_233));
-  AOI21X1 g1302(.A0 (n_230), .A1 (v_in1), .B0 (n_179), .Y (n_231));
-  OAI21X1 g1306(.A0 (n_215), .A1 (n_6), .B0 (n_176), .Y (n_229));
-  NOR2X1 g1312(.A (n_78), .B (n_223), .Y (n_228));
-  OR2X1 g1319(.A (n_186), .B (n_175), .Y (n_310));
-  INVX1 g1322(.A (n_226), .Y (n_227));
-  INVX4 g1324(.A (n_199), .Y (n_292));
-  AOI22X1 g1248(.A0 (n_121), .A1 (n_407), .B0 (n_300), .B1 (n_221), .Y
-       (n_225));
-  NOR2X1 g1332(.A (n_95), .B (n_223), .Y (n_224));
-  AOI22X1 g1249(.A0 (n_120), .A1 (n_407), .B0 (n_38), .B1 (n_221), .Y
-       (n_222));
-  NOR2X1 g1341(.A (n_96), .B (n_223), .Y (n_220));
-  NOR2X1 g1344(.A (n_92), .B (n_223), .Y (n_219));
-  NAND2X1 g1256(.A (n_156), .B (n_72), .Y (n_218));
-  AOI21X1 g1220(.A0 (n_111), .A1 (n_188), .B0 (n_223), .Y (n_214));
-  NOR2X1 g1263(.A (n_124), .B (n_212), .Y (n_213));
-  AOI22X1 g1270(.A0 (n_153), .A1 (n_47), .B0 (n_18), .B1 (n_221), .Y
-       (n_211));
-  NAND4X1 g1225(.A (n_209), .B (n_138), .C (n_131), .D (n_126), .Y
-       (n_210));
-  OAI21X1 g1275(.A0 (n_182), .A1 (n_79), .B0 (n_180), .Y (n_208));
-  NAND2X2 g1279(.A (n_207), .B (n_191), .Y (n_276));
-  NAND3X1 g1289(.A (rtr), .B (n_204), .C (n_163), .Y (n_206));
-  NAND3X1 g1291(.A (rtr), .B (n_204), .C (n_154), .Y (n_205));
-  NAND2X1 g1296(.A (n_215), .B (n_377), .Y (n_203));
-  AOI22X1 g1305(.A0 (n_230), .A1 (v_in0), .B0 (n_91), .B1 (n_409), .Y
-       (n_201));
-  NAND2X1 g1310(.A (n_407), .B (n_72), .Y (n_200));
-  NAND2X1 g1318(.A (n_256), .B (n_432), .Y (n_262));
-  NAND2X1 g1323(.A (n_123), .B (n_190), .Y (n_226));
-  NAND2X2 g1325(.A (n_148), .B (n_145), .Y (n_199));
-  NAND2X1 g1334(.A (n_432), .B (n_457), .Y (n_266));
-  NAND2X1 g1335(.A (n_161), .B (n_196), .Y (n_197));
-  INVX1 g1338(.A (n_194), .Y (n_195));
-  NAND2X1 g1342(.A (n_141), .B (n_133), .Y (n_358));
-  NOR2X1 g1347(.A (n_20), .B (n_191), .Y (n_192));
-  NAND2X1 g1349(.A (n_388), .B (n_190), .Y (n_317));
-  AOI21X1 g1222(.A0 (n_75), .A1 (n_188), .B0 (n_191), .Y (n_189));
-  NOR2X1 g1223(.A (n_155), .B (n_191), .Y (n_184));
-  NAND2X1 g1281(.A (n_182), .B (n_432), .Y (n_183));
-  AOI21X1 g1295(.A0 (test), .A1 (n_132), .B0 (n_221), .Y (n_181));
-  NAND2X1 g1309(.A (n_230), .B (v_in2), .Y (n_180));
-  NAND3X1 g1311(.A (start), .B (n_122), .C (n_140), .Y (n_212));
-  AND2X1 g1313(.A (n_178), .B (n_460), .Y (n_179));
-  NAND2X1 g1314(.A (n_175), .B (n_398), .Y (n_176));
-  NOR2X1 g1315(.A (n_196), .B (n_99), .Y (n_174));
-  NAND2X1 g1320(.A (n_406), .B (n_1), .Y (n_209));
-  NAND2X1 g1326(.A (n_230), .B (n_103), .Y (n_303));
-  NOR2X1 g1336(.A (n_470), .B (n_196), .Y (n_171));
-  NAND2X1 g1340(.A (n_150), .B (n_128), .Y (n_194));
-  NAND2X1 g1343(.A (rtr), .B (n_460), .Y (n_377));
-  AND2X1 g1345(.A (n_190), .B (n_381), .Y (n_207));
-  NAND2X1 g1346(.A (n_148), .B (n_215), .Y (n_169));
-  NAND3X1 g1348(.A (n_409), .B (start), .C (n_154), .Y (n_168));
-  NAND3X1 g1350(.A (n_406), .B (n_178), .C (n_1), .Y (n_167));
-  NAND2X1 g1351(.A (n_148), .B (n_190), .Y (n_166));
-  NAND3X1 g1353(.A (n_406), .B (start), .C (n_163), .Y (n_165));
-  NAND2X1 g1355(.A (n_85), .B (n_460), .Y (n_162));
-  CLKBUFX3 g1385(.A (n_191), .Y (n_223));
-  INVX2 g1399(.A (n_388), .Y (n_251));
-  INVX1 g1402(.A (n_389), .Y (n_186));
-  NAND2X1 g1287(.A (n_182), .B (n_148), .Y (n_156));
-  OAI21X1 g1239(.A0 (rtr), .A1 (n_154), .B0 (n_188), .Y (n_155));
-  INVX1 g1330(.A (n_182), .Y (n_153));
-  NAND2X1 g1333(.A (n_135), .B (n_163), .Y (n_152));
-  NAND2X1 g1337(.A (n_135), .B (n_150), .Y (n_151));
-  INVX1 g1362(.A (n_230), .Y (n_149));
-  INVX1 g1367(.A (n_175), .Y (n_161));
-  INVX2 g1374(.A (n_148), .Y (n_249));
-  INVX1 g1380(.A (n_460), .Y (n_145));
-  INVX4 g1388(.A (n_142), .Y (n_191));
-  INVX1 g1392(.A (n_381), .Y (n_204));
-  INVX1 g1396(.A (n_406), .Y (n_141));
-  CLKBUFX3 g1405(.A (n_431), .Y (n_221));
-  NAND4X1 g1282(.A (rtr), .B (n_72), .C (n_137), .D (n_348), .Y
-       (n_138));
-  NAND3X1 g1331(.A (n_1), .B (n_137), .C (n_125), .Y (n_182));
-  INVX2 g1368(.A (n_133), .Y (n_175));
-  INVX2 g1358(.A (n_132), .Y (n_256));
-  INVX1 g1359(.A (n_132), .Y (n_131));
-  INVX2 g1363(.A (n_449), .Y (n_230));
-  CLKBUFX3 g1364(.A (n_449), .Y (n_215));
-  INVX2 g1376(.A (n_135), .Y (n_148));
-  INVX2 g1389(.A (n_123), .Y (n_142));
-  CLKBUFX3 g1407(.A (n_190), .Y (n_196));
-  INVX1 g1408(.A (n_190), .Y (n_128));
-  NAND2X1 g1283(.A (n_87), .B (key), .Y (n_127));
-  NAND3X1 g1284(.A (n_104), .B (n_391), .C (n_125), .Y (n_126));
-  NAND2X1 g1286(.A (n_98), .B (key), .Y (n_124));
-  NAND2X2 g1390(.A (n_122), .B (n_113), .Y (n_123));
-  MX2X1 g1307(.A (n_300), .B (n_60), .S0 (start), .Y (n_121));
-  MX2X1 g1308(.A (n_38), .B (n_67), .S0 (start), .Y (n_120));
-  NAND3X1 g1316(.A (rts), .B (n_122), .C (n_348), .Y (n_294));
-  NAND2X1 g1252(.A (n_77), .B (rtr), .Y (n_188));
-  NAND2X1 g1369(.A (n_137), .B (n_125), .Y (n_133));
-  INVX2 g1377(.A (n_115), .Y (n_135));
-  INVX1 g1360(.A (n_97), .Y (n_132));
-  NAND2X2 g1409(.A (n_137), .B (n_113), .Y (n_190));
-  XOR2X1 g1276(.A (n_47), .B (n_63), .Y (n_112));
-  OR2X1 g1424(.A (rtr), .B (n_99), .Y (n_111));
-  INVX2 g1425(.A (n_110), .Y (n_140));
-  NAND2X1 g1378(.A (n_404), .B (n_456), .Y (n_115));
-  NOR2X1 g1321(.A (n_103), .B (n_73), .Y (n_104));
-  XOR2X1 g1357(.A (n_79), .B (n_34), .Y (n_98));
-  NAND2X1 g1361(.A (n_122), .B (n_125), .Y (n_97));
-  MX2X1 g1412(.A (n_4), .B (n_15), .S0 (rtr), .Y (n_96));
-  MX2X1 g1413(.A (n_2), .B (n_31), .S0 (rtr), .Y (n_95));
-  OAI21X1 g1414(.A0 (rts), .A1 (n_15), .B0 (n_16), .Y (n_94));
-  MX2X1 g1415(.A (n_5), .B (n_61), .S0 (rtr), .Y (n_92));
-  OAI21X1 g1416(.A0 (n_15), .A1 (start), .B0 (n_29), .Y (n_91));
-  OAI21X1 g1418(.A0 (rts), .A1 (n_61), .B0 (n_13), .Y (n_90));
-  OAI21X1 g1419(.A0 (n_246), .A1 (n_31), .B0 (n_8), .Y (n_89));
-  INVX2 g1426(.A (n_402), .Y (n_110));
-  XOR2X1 g1356(.A (n_61), .B (n_36), .Y (n_87));
-  NAND2X1 g1455(.A (n_1), .B (n_49), .Y (n_86));
-  NAND2X1 g1431(.A (rtr), .B (n_74), .Y (n_85));
-  OAI21X1 g1411(.A0 (rts), .A1 (n_79), .B0 (n_22), .Y (n_80));
-  MX2X1 g1420(.A (n_7), .B (n_79), .S0 (rtr), .Y (n_78));
-  NAND3X1 g1280(.A (n_30), .B (n_15), .C (n_31), .Y (n_77));
-  INVX2 g1432(.A (n_454), .Y (n_137));
-  INVX2 g1435(.A (n_57), .Y (n_113));
-  OR2X1 g1439(.A (rtr), .B (n_74), .Y (n_75));
-  INVX1 g1473(.A (n_72), .Y (n_99));
-  NOR2X1 g1410(.A (n_24), .B (n_21), .Y (n_103));
-  INVX1 g1527(.A (n_61), .Y (n_244));
-  OAI21X1 g1417(.A0 (n_33), .A1 (key), .B0 (n_17), .Y (n_67));
-  INVX1 g1474(.A (n_73), .Y (n_72));
-  INVX1 g1509(.A (n_74), .Y (n_163));
-  XOR2X1 g1422(.A (n_79), .B (n_61), .Y (n_63));
-  OAI21X1 g1421(.A0 (n_35), .A1 (key), .B0 (n_12), .Y (n_60));
-  NOR2X1 g1423(.A (n_79), .B (start), .Y (n_59));
-  INVX1 g1457(.A (n_403), .Y (n_122));
-  NAND2X2 g1436(.A (n_39), .B (n_37), .Y (n_57));
-  INVX2 g1450(.A (n_447), .Y (n_125));
-  INVX1 g1496(.A (n_154), .Y (n_470));
-  INVX1 g1513(.A (n_269), .Y (n_49));
-  INVX1 g1475(.A (n_465), .Y (n_73));
-  INVX1 g1498(.A (n_462), .Y (n_350));
-  INVX1 g1514(.A (n_39), .Y (n_269));
-  INVX1 g1510(.A (n_37), .Y (n_74));
-  NAND2X1 g1438(.A (n_35), .B (g_button), .Y (n_36));
-  NAND2X1 g1437(.A (n_33), .B (r_button), .Y (n_34));
-  NOR2X1 g1453(.A (n_79), .B (n_61), .Y (n_30));
-  NAND2X1 g1454(.A (key), .B (start), .Y (n_29));
-  CLKBUFX1 g1497(.A (n_462), .Y (n_154));
-  NAND2X1 g1460(.A (v_in0), .B (v_in1), .Y (n_24));
-  INVX1 g1518(.A (n_150), .Y (n_246));
-  NAND2X1 g1443(.A (v_in2), .B (rts), .Y (n_22));
-  NAND2X1 g1445(.A (v_in2), .B (v_in3), .Y (n_21));
-  NOR2X1 g1461(.A (rtr), .B (cts), .Y (n_20));
-  INVX1 g1511(.A (n_46), .Y (n_37));
-  NAND2X1 g1456(.A (r_button), .B (key), .Y (n_17));
-  NAND2X1 g1449(.A (v_in0), .B (rts), .Y (n_16));
-  NAND2X1 g1442(.A (v_in1), .B (rts), .Y (n_13));
-  NAND2X1 g1447(.A (g_button), .B (key), .Y (n_12));
-  INVX2 g1516(.A (n_45), .Y (n_9));
-  NAND2X1 g1446(.A (rts), .B (v_in3), .Y (n_8));
-  CLKBUFX2 g1515(.A (n_45), .Y (n_39));
-  INVX1 g1526(.A (n_47), .Y (n_15));
-  INVX1 g1485(.A (v_out2), .Y (n_7));
-  INVX1 g1502(.A (n_300), .Y (n_35));
-  INVX4 g1512(.A (stato_6), .Y (n_46));
-  INVX1 g1520(.A (rts), .Y (n_150));
-  INVX1 g1482(.A (v_in3), .Y (n_6));
-  INVX1 g1521(.A (reset), .Y (n_340));
-  INVX1 g1484(.A (v_out1), .Y (n_5));
-  INVX1 g1478(.A (v_out0), .Y (n_4));
-  INVX1 g1467(.A (n_27), .Y (n_31));
-  INVX2 g1517(.A (stato_5), .Y (n_45));
-  INVX1 g1483(.A (v_out3), .Y (n_2));
-  INVX1 g1531(.A (n_178), .Y (n_61));
-  INVX1 g1491(.A (start), .Y (n_1));
-  INVX1 g1506(.A (n_286), .Y (n_18));
-  INVX1 g1481(.A (n_38), .Y (n_33));
-  INVX2 g1535(.A (voto2), .Y (n_79));
-  CLKBUFX1 g1554(.A (n_456), .Y (n_348));
-  NAND2X1 g1393_dup(.A (n_451), .B (n_125), .Y (n_381));
-  NAND2X2 g1574(.A (n_140), .B (n_137), .Y (n_388));
-  NAND2X2 g1403_dup(.A (n_140), .B (n_137), .Y (n_389));
-  NOR2X1 g1575(.A (n_350), .B (n_73), .Y (n_466));
-  NOR2X1 g1448_dup(.A (n_350), .B (n_73), .Y (n_391));
-  INVX1 g1576(.A (n_453), .Y (n_392));
-  AND2X1 g41(.A (n_400), .B (n_407), .Y (n_408));
-  NAND2X1 g42(.A (n_397), .B (n_399), .Y (n_400));
-  NAND3X1 g43(.A (n_27), .B (start), .C (key), .Y (n_397));
-  INVX1 g47(.A (n_398), .Y (n_399));
-  NOR2X1 g48(.A (start), .B (n_31), .Y (n_398));
-  CLKBUFX3 g53(.A (n_406), .Y (n_407));
-  INVX2 g54(.A (n_405), .Y (n_406));
-  NAND2X1 g46(.A (n_402), .B (n_404), .Y (n_405));
-  INVX2 g51(.A (n_401), .Y (n_402));
-  NAND2X2 g52(.A (n_9), .B (n_46), .Y (n_401));
-  INVX1 g49(.A (n_403), .Y (n_404));
-  NAND2X1 g50(.A (n_461), .B (n_463), .Y (n_403));
-  CLKBUFX2 g1(.A (n_406), .Y (n_409));
-  NAND4X1 g1579(.A (n_411), .B (n_412), .C (n_413), .D (n_415), .Y
-       (n_416));
-  AOI21X1 g44(.A0 (ctr), .A1 (n_459), .B0 (n_195), .Y (n_411));
-  OAI21X1 g45(.A0 (n_287), .A1 (n_407), .B0 (ctr), .Y (n_412));
-  NAND2X1 g1581(.A (n_197), .B (ctr), .Y (n_413));
-  NAND2X1 g1582(.A (n_414), .B (ctr), .Y (n_415));
-  NAND3X1 g1583(.A (n_151), .B (n_215), .C (n_432), .Y (n_414));
-  NAND2X1 g17(.A (n_430), .B (n_432), .Y (n_433));
-  NAND2X1 g18(.A (rtr), .B (n_459), .Y (n_430));
-  INVX2 g19(.A (n_431), .Y (n_432));
-  NOR2X1 g20(.A (n_464), .B (n_110), .Y (n_431));
-  NAND2X2 g36(.A (n_444), .B (n_445), .Y (n_446));
-  NOR2X1 g37(.A (n_442), .B (n_443), .Y (n_444));
-  OAI21X1 g38(.A0 (n_441), .A1 (n_381), .B0 (n_200), .Y (n_442));
-  AND2X1 g1596(.A (n_99), .B (rtr), .Y (n_441));
-  NAND3X1 g39(.A (n_241), .B (n_218), .C (n_294), .Y (n_443));
-  AOI21X1 g40(.A0 (n_174), .A1 (n_246), .B0 (n_214), .Y (n_445));
-  NAND2X1 g1597(.A (n_449), .B (n_458), .Y (n_453));
-  NAND2X2 g1598(.A (n_125), .B (n_466), .Y (n_449));
-  NAND2X1 g26(.A (n_46), .B (n_45), .Y (n_447));
-  INVX1 g1599(.A (n_464), .Y (n_451));
-  NAND2X1 g1601(.A (n_457), .B (n_458), .Y (n_459));
-  NAND2X2 g1602(.A (n_455), .B (n_456), .Y (n_457));
-  INVX1 g28(.A (n_454), .Y (n_455));
-  NAND2X2 g29(.A (n_465), .B (n_461), .Y (n_454));
-  NOR2X1 g30(.A (n_45), .B (n_46), .Y (n_456));
-  NAND2X1 g27(.A (n_451), .B (n_125), .Y (n_458));
-  INVX2 g1603(.A (n_457), .Y (n_460));
-  NAND2X1 g11(.A (n_462), .B (n_463), .Y (n_464));
-  INVX1 g14(.A (n_461), .Y (n_462));
-  INVX2 g15(.A (stato_7), .Y (n_461));
-  INVX2 g13(.A (stato), .Y (n_463));
-  INVX2 g12(.A (n_463), .Y (n_465));
-endmodule
-
-
-
-   'module',
-      'b10',
-      '(',
-       'r_button',
-        'g_button',
-        'key',
-        'start',
-        'reset',
-        'test',
-        'cts',
-        'ctr',
-        'rts',
-        'rtr',
-        'clock',
-        'v_in',
-        'v_out',
-      ')',
-      ';',
-      'input',
-        'r_button',
-        'g_button',
-        'key',
-        'start',
-        'reset',
-        'test',
-        'rts',
-        'rtr',
-        'clock',
-        ';',
-      'input', '', '3', ':', '0', '', 'v_in', ';',
-      'output', 'cts', 'ctr', ';',
-      'output', '', '3', ':', '0', '', 'v_out', ';',
-       'wire',
-         'r_button',
-          'g_button',
-          'key',
-          'start',
-          'reset',
-          'test',
-          'rts',
-          'rtr',
-          'clock',
-        ';',
-      'wire', '', '3', ':', '0', '', 'v_in', ';',
-      'wire', 'cts', 'ctr', ';',
-      'wire', '', '3', ':', '0', '', 'v_out', ';',
-       'wire',
-        'n_1', 'n_2', 'n_4', 'n_5', 'n_6', 'n_7', 'n_8', 'n_9',
-        ';',
-       'wire',
-        'n_12', 'n_13', 'n_15', 'n_16', 'n_17', 'n_18', 'n_20', 'n_21',
-        ';',
-       'wire',
-        'n_22', 'n_24', 'n_27', 'n_29', 'n_30', 'n_31', 'n_33', 'n_34',
-        ';',
-       'wire',
-        'n_35', 'n_36', 'n_37', 'n_38', 'n_39', 'n_45', 'n_46', 'n_47',
-        ';',
-       'wire',
-        'n_49', 'n_57', 'n_59', 'n_60', 'n_61', 'n_63', 'n_67', 'n_72',
-        ';',
-       'wire',
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-            '.B', '(', 'key', ')',
-            '.Y', '(', 'n_17', ')',
-            ')',
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-       'NAND2X1',
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-            '.B', '(', 'rts', ')',
-            '.Y', '(', 'n_16', ')',
-            ')',
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-            '.B', '(', 'key', ')',
-            '.Y', '(', 'n_12', ')',
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-            '.Y', '(', 'n_9', ')',
-            ')',
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-            '.Y', '(', 'n_340', ')',
-            ')',
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-            '.Y', '(', 'n_5', ')',
-            ')',
-        ';',
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-        ';',
-       'NAND2X2',
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-        ';',
-       'NAND2X1',
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-        ';',
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-            '.C', '(', 'n_413', ')',
-            '.D', '(', 'n_415', ')',
-            '.Y', '(', 'n_416', ')',
-            ')',
-        ';',
-       'AOI21X1',
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-       'NAND2X1',
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-            '.B', '(', 'ctr', ')',
-            '.Y', '(', 'n_413', ')',
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-        ';',
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-            '.Y', '(', 'n_457', ')',
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-            '.Y', '(', 'n_455', ')',
-            ')',
-        ';',
-       'NAND2X2',
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-            '.Y', '(', 'n_454', ')',
-            ')',
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-            '.Y', '(', 'n_456', ')',
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-            '.Y', '(', 'n_458', ')',
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-            '.A', '(', 'n_457', ')',
-            '.Y', '(', 'n_460', ')',
-            ')',
-        ';',
-       'NAND2X1',
-         'g11',
-           '(',
-            '.A', '(', 'n_462', ')',
-            '.B', '(', 'n_463', ')',
-            '.Y', '(', 'n_464', ')',
-            ')',
-        ';',
-       'INVX1',
-         'g14',
-           '(',
-            '.A', '(', 'n_461', ')',
-            '.Y', '(', 'n_462', ')',
-            ')',
-        ';',
-       'INVX2',
-         'g15',
-           '(',
-            '.A', '(', 'stato_7', ')',
-            '.Y', '(', 'n_461', ')',
-            ')',
-        ';',
-       'INVX2',
-         'g13',
-           '(',
-            '.A', '(', 'stato', ')',
-            '.Y', '(', 'n_463', ')',
-            ')',
-        ';',
-       'INVX2',
-         'g12',
-           '(',
-            '.A', '(', 'n_463', ')',
-            '.Y', '(', 'n_465', ')',
-            ')',
-        ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/new3/parseOutput/ca_prng.v.parsed.txt Deleted

@@ -1,3729 +0,0 @@
-//========================================================================
-//
-// ca_prng.v
-// ---------
-// Cellular Automata (CA) PRNG. This version produces PRNG words
-// with 32 bits.
-// 
-// Version: v1.1, 2009-03-20
-// Generated by: gen_ca_prng_rtl.py v2.0, 2009-03-20
-// 
-// 
-// Author: Joachim Strombergson
-// Copyright (c) 2008, InformAsic AB
-// All rights reserved.
-// 
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-// 
-//     * Redistributions in binary form must reproduce the above
-//       copyright notice, this list of conditions and the following
-//       disclaimer in the documentation and/or other materials
-//       provided with the distribution.
-// 
-// THIS SOFTWARE IS PROVIDED BY InformAsic AB ''AS IS'' AND ANY EXPRESS
-// OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL InformAsic AB BE LIABLE FOR ANY
-// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// 
-//========================================================================
-
-module ca_prng(
-               input wire           clk,
-               input wire           reset_n,
-
-               input wire 31 : 0  init_pattern_data,
-               input wire           load_init_pattern,
-               input wire           next_pattern,
-
-               input wire 7 : 0   update_rule,
-               input wire           load_update_rule,
-
-               output wire 31 : 0 prng_data
-              );
-
-
-  //--------------------------------------------------------------------
-  // Constant declarations.
-  //--------------------------------------------------------------------
-  // DEFAULT_RULE
-  // The Default update rule - rule 30.
-  parameter 7 : 0 DEFAULT_RULE = 8'b00011110;
-
-
-  //--------------------------------------------------------------------
-  // Register declarations.
-  //--------------------------------------------------------------------
-  // ca_state_reg
-  // State register for the CA cells, one bit for each cell.
-  reg 31 : 0 ca_state_reg;
-  reg 31 : 0 ca_state_new;
-  reg          ca_state_we;
-
-  // update_rule_reg
-  // Register for the update rule.
-  reg 7 : 0 update_rule_reg;
-
-
-  //--------------------------------------------------------------------
-  // Wire declarations.
-  //--------------------------------------------------------------------
-  // tmp_ca_state_new
-  // temporary update vector. Is muxed to the real update vector
-  // if the load_init_pattern control signal is not set.
-  reg 31 : 0 tmp_ca_state_new;
-
-
-  //--------------------------------------------------------------------
-  // Assignments.
-  //--------------------------------------------------------------------
-  // Connect the PRNG output port to the CA state registers.
-  assign prng_data = ca_state_reg;
-
-
-  //--------------------------------------------------------------------
-  // reg_update
-  //
-  // This clocked process impement all register updates including
-  // synchronous, active low reset.
-  //--------------------------------------------------------------------
-  always @ (posedge clk)
-    begin : reg_update
-      if (!reset_n)
-        begin
-          // Register reset.
-          update_rule_reg <= DEFAULT_RULE;
-          ca_state_reg    <= 32'b00000000000000000000000000000000;
-        end
-      else
-        begin
-          // Normal register update.
-
-          if (load_update_rule)
-            begin
-              update_rule_reg <= update_rule;
-           end
-
-          if (ca_state_we)
-            begin
-              ca_state_reg <= ca_state_new;
-           end
-         end
-    end // reg_update
-
-
-  //--------------------------------------------------------------------
-  // ca_state_update
-  //
-  // State update logic for the CA cells. This is where we implement
-  // the Rule 30-logic as well as init pattern assignment.
-  //--------------------------------------------------------------------
-  always @*
-    begin : ca_state_update
-      // Update for ca_state_reg bit 0.
-      case({ca_state_reg31, ca_state_reg0, ca_state_reg1})
-        0:
-        begin
-          tmp_ca_state_new0 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new0 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new0 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new0 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new0 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new0 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new0 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new0 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new0
-
-      // Update for ca_state_reg bit 1.
-      case({ca_state_reg0, ca_state_reg1, ca_state_reg2})
-        0:
-        begin
-          tmp_ca_state_new1 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new1 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new1 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new1 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new1 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new1 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new1 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new1 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new1
-
-      // Update for ca_state_reg bit 2.
-      case({ca_state_reg1, ca_state_reg2, ca_state_reg3})
-        0:
-        begin
-          tmp_ca_state_new2 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new2 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new2 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new2 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new2 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new2 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new2 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new2 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new2
-
-      // Update for ca_state_reg bit 3.
-      case({ca_state_reg2, ca_state_reg3, ca_state_reg4})
-        0:
-        begin
-          tmp_ca_state_new3 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new3 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new3 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new3 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new3 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new3 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new3 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new3 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new3
-
-      // Update for ca_state_reg bit 4.
-      case({ca_state_reg3, ca_state_reg4, ca_state_reg5})
-        0:
-        begin
-          tmp_ca_state_new4 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new4 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new4 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new4 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new4 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new4 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new4 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new4 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new4
-
-      // Update for ca_state_reg bit 5.
-      case({ca_state_reg4, ca_state_reg5, ca_state_reg6})
-        0:
-        begin
-          tmp_ca_state_new5 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new5 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new5 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new5 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new5 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new5 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new5 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new5 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new5
-
-      // Update for ca_state_reg bit 6.
-      case({ca_state_reg5, ca_state_reg6, ca_state_reg7})
-        0:
-        begin
-          tmp_ca_state_new6 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new6 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new6 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new6 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new6 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new6 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new6 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new6 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new6
-
-      // Update for ca_state_reg bit 7.
-      case({ca_state_reg6, ca_state_reg7, ca_state_reg8})
-        0:
-        begin
-          tmp_ca_state_new7 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new7 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new7 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new7 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new7 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new7 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new7 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new7 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new7
-
-      // Update for ca_state_reg bit 8.
-      case({ca_state_reg7, ca_state_reg8, ca_state_reg9})
-        0:
-        begin
-          tmp_ca_state_new8 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new8 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new8 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new8 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new8 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new8 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new8 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new8 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new8
-
-      // Update for ca_state_reg bit 9.
-      case({ca_state_reg8, ca_state_reg9, ca_state_reg10})
-        0:
-        begin
-          tmp_ca_state_new9 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new9 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new9 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new9 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new9 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new9 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new9 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new9 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new9
-
-      // Update for ca_state_reg bit 10.
-      case({ca_state_reg9, ca_state_reg10, ca_state_reg11})
-        0:
-        begin
-          tmp_ca_state_new10 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new10 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new10 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new10 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new10 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new10 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new10 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new10 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new10
-
-      // Update for ca_state_reg bit 11.
-      case({ca_state_reg10, ca_state_reg11, ca_state_reg12})
-        0:
-        begin
-          tmp_ca_state_new11 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new11 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new11 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new11 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new11 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new11 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new11 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new11 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new11
-
-      // Update for ca_state_reg bit 12.
-      case({ca_state_reg11, ca_state_reg12, ca_state_reg13})
-        0:
-        begin
-          tmp_ca_state_new12 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new12 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new12 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new12 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new12 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new12 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new12 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new12 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new12
-
-      // Update for ca_state_reg bit 13.
-      case({ca_state_reg12, ca_state_reg13, ca_state_reg14})
-        0:
-        begin
-          tmp_ca_state_new13 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new13 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new13 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new13 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new13 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new13 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new13 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new13 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new13
-
-      // Update for ca_state_reg bit 14.
-      case({ca_state_reg13, ca_state_reg14, ca_state_reg15})
-        0:
-        begin
-          tmp_ca_state_new14 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new14 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new14 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new14 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new14 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new14 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new14 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new14 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new14
-
-      // Update for ca_state_reg bit 15.
-      case({ca_state_reg14, ca_state_reg15, ca_state_reg16})
-        0:
-        begin
-          tmp_ca_state_new15 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new15 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new15 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new15 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new15 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new15 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new15 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new15 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new15
-
-      // Update for ca_state_reg bit 16.
-      case({ca_state_reg15, ca_state_reg16, ca_state_reg17})
-        0:
-        begin
-          tmp_ca_state_new16 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new16 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new16 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new16 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new16 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new16 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new16 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new16 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new16
-
-      // Update for ca_state_reg bit 17.
-      case({ca_state_reg16, ca_state_reg17, ca_state_reg18})
-        0:
-        begin
-          tmp_ca_state_new17 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new17 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new17 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new17 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new17 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new17 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new17 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new17 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new17
-
-      // Update for ca_state_reg bit 18.
-      case({ca_state_reg17, ca_state_reg18, ca_state_reg19})
-        0:
-        begin
-          tmp_ca_state_new18 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new18 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new18 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new18 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new18 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new18 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new18 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new18 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new18
-
-      // Update for ca_state_reg bit 19.
-      case({ca_state_reg18, ca_state_reg19, ca_state_reg20})
-        0:
-        begin
-          tmp_ca_state_new19 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new19 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new19 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new19 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new19 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new19 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new19 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new19 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new19
-
-      // Update for ca_state_reg bit 20.
-      case({ca_state_reg19, ca_state_reg20, ca_state_reg21})
-        0:
-        begin
-          tmp_ca_state_new20 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new20 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new20 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new20 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new20 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new20 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new20 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new20 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new20
-
-      // Update for ca_state_reg bit 21.
-      case({ca_state_reg20, ca_state_reg21, ca_state_reg22})
-        0:
-        begin
-          tmp_ca_state_new21 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new21 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new21 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new21 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new21 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new21 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new21 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new21 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new21
-
-      // Update for ca_state_reg bit 22.
-      case({ca_state_reg21, ca_state_reg22, ca_state_reg23})
-        0:
-        begin
-          tmp_ca_state_new22 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new22 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new22 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new22 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new22 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new22 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new22 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new22 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new22
-
-      // Update for ca_state_reg bit 23.
-      case({ca_state_reg22, ca_state_reg23, ca_state_reg24})
-        0:
-        begin
-          tmp_ca_state_new23 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new23 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new23 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new23 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new23 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new23 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new23 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new23 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new23
-
-      // Update for ca_state_reg bit 24.
-      case({ca_state_reg23, ca_state_reg24, ca_state_reg25})
-        0:
-        begin
-          tmp_ca_state_new24 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new24 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new24 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new24 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new24 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new24 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new24 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new24 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new24
-
-      // Update for ca_state_reg bit 25.
-      case({ca_state_reg24, ca_state_reg25, ca_state_reg26})
-        0:
-        begin
-          tmp_ca_state_new25 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new25 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new25 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new25 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new25 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new25 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new25 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new25 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new25
-
-      // Update for ca_state_reg bit 26.
-      case({ca_state_reg25, ca_state_reg26, ca_state_reg27})
-        0:
-        begin
-          tmp_ca_state_new26 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new26 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new26 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new26 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new26 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new26 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new26 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new26 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new26
-
-      // Update for ca_state_reg bit 27.
-      case({ca_state_reg26, ca_state_reg27, ca_state_reg28})
-        0:
-        begin
-          tmp_ca_state_new27 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new27 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new27 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new27 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new27 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new27 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new27 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new27 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new27
-
-      // Update for ca_state_reg bit 28.
-      case({ca_state_reg27, ca_state_reg28, ca_state_reg29})
-        0:
-        begin
-          tmp_ca_state_new28 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new28 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new28 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new28 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new28 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new28 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new28 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new28 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new28
-
-      // Update for ca_state_reg bit 29.
-      case({ca_state_reg28, ca_state_reg29, ca_state_reg30})
-        0:
-        begin
-          tmp_ca_state_new29 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new29 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new29 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new29 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new29 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new29 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new29 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new29 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new29
-
-      // Update for ca_state_reg bit 30.
-      case({ca_state_reg29, ca_state_reg30, ca_state_reg31})
-        0:
-        begin
-          tmp_ca_state_new30 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new30 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new30 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new30 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new30 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new30 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new30 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new30 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new30
-
-      // Update for ca_state_reg bit 31.
-      case({ca_state_reg30, ca_state_reg31, ca_state_reg0})
-        0:
-        begin
-          tmp_ca_state_new31 = update_rule_reg0;
-        end
-        1:
-        begin
-          tmp_ca_state_new31 = update_rule_reg1;
-        end
-        2:
-        begin
-          tmp_ca_state_new31 = update_rule_reg2;
-        end
-        3:
-        begin
-          tmp_ca_state_new31 = update_rule_reg3;
-        end
-        4:
-        begin
-          tmp_ca_state_new31 = update_rule_reg4;
-        end
-        5:
-        begin
-          tmp_ca_state_new31 = update_rule_reg5;
-        end
-        6:
-        begin
-          tmp_ca_state_new31 = update_rule_reg6;
-        end
-        7:
-        begin
-          tmp_ca_state_new31 = update_rule_reg7;
-        end
-      endcase // tmp_ca_state_new31
-
-
-      if (load_init_pattern)
-        begin
-          ca_state_new = init_pattern_data;
-        end
-      else
-        begin
-          ca_state_new = tmp_ca_state_new;
-        end
-
-      // Should an init pattern or the next pattern be stored in
-      // the CA array?
-      if (load_init_pattern || next_pattern)
-        begin
-          ca_state_we = 1;
-        end
-      else
-        begin
-          ca_state_we = 0;
-        end
-    end // ca_state_update
-
-
-endmodule // ca_prng
-//========================================================================
-// EOF ca_prng.v
-//========================================================================
-
-
-   'module',
-      'ca_prng',
-      '(',
-       'input', 'wire', 'clk',
-        'input', 'wire', 'reset_n',
-        'input', 'wire', '', '31', ':', '0', '', 'init_pattern_data',
-        'input', 'wire', 'load_init_pattern',
-        'input', 'wire', 'next_pattern',
-        'input', 'wire', '', '7', ':', '0', '', 'update_rule',
-        'input', 'wire', 'load_update_rule',
-        'output', 'wire', '', '31', ':', '0', '', 'prng_data',
-      ')',
-      ';',
-      'parameter',
-        '',
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-        ':',
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-        'DEFAULT_RULE', '=', "8 'b 00011110",
-        ';',
-      'reg', '', '31', ':', '0', '', 'ca_state_reg', ';',
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-      'reg', '', '31', ':', '0', '', 'tmp_ca_state_new', ';',
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-       'always',
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-         'begin',
-          ':',
-          'reg_update',
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-             'begin',
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-                  ';',
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-              '}',
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-              'ca_state_reg', '', '2', '',
-              '}',
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-                    '=',
-                    'update_rule_reg', '', '6', '',
-                  ';',
-              'end',
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-            ':',
-             'begin',
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-                    '=',
-                    'update_rule_reg', '', '7', '',
-                  ';',
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-           'case',
-            '(',
-             '{',
-              'ca_state_reg', '', '29', '',
-              'ca_state_reg', '', '30', '',
-              'ca_state_reg', '', '31', '',
-              '}',
-            ')',
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-             'begin',
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-            ':',
-             'begin',
-                 'tmp_ca_state_new', '', '30', '',
-                    '=',
-                    'update_rule_reg', '', '2', '',
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-             'begin',
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-                  ';',
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-            '4',
-            ':',
-             'begin',
-                 'tmp_ca_state_new', '', '30', '',
-                    '=',
-                    'update_rule_reg', '', '4', '',
-                  ';',
-              'end',
-            '5',
-            ':',
-             'begin',
-                 'tmp_ca_state_new', '', '30', '',
-                    '=',
-                    'update_rule_reg', '', '5', '',
-                  ';',
-              'end',
-            '6',
-            ':',
-             'begin',
-                 'tmp_ca_state_new', '', '30', '',
-                    '=',
-                    'update_rule_reg', '', '6', '',
-                  ';',
-              'end',
-            '7',
-            ':',
-             'begin',
-                 'tmp_ca_state_new', '', '30', '',
-                    '=',
-                    'update_rule_reg', '', '7', '',
-                  ';',
-              'end',
-            'endcase',
-           'case',
-            '(',
-             '{',
-              'ca_state_reg', '', '30', '',
-              'ca_state_reg', '', '31', '',
-              'ca_state_reg', '', '0', '',
-              '}',
-            ')',
-            '0',
-            ':',
-             'begin',
-                 'tmp_ca_state_new', '', '31', '',
-                    '=',
-                    'update_rule_reg', '', '0', '',
-                  ';',
-              'end',
-            '1',
-            ':',
-             'begin',
-                 'tmp_ca_state_new', '', '31', '',
-                    '=',
-                    'update_rule_reg', '', '1', '',
-                  ';',
-              'end',
-            '2',
-            ':',
-             'begin',
-                 'tmp_ca_state_new', '', '31', '',
-                    '=',
-                    'update_rule_reg', '', '2', '',
-                  ';',
-              'end',
-            '3',
-            ':',
-             'begin',
-                 'tmp_ca_state_new', '', '31', '',
-                    '=',
-                    'update_rule_reg', '', '3', '',
-                  ';',
-              'end',
-            '4',
-            ':',
-             'begin',
-                 'tmp_ca_state_new', '', '31', '',
-                    '=',
-                    'update_rule_reg', '', '4', '',
-                  ';',
-              'end',
-            '5',
-            ':',
-             'begin',
-                 'tmp_ca_state_new', '', '31', '',
-                    '=',
-                    'update_rule_reg', '', '5', '',
-                  ';',
-              'end',
-            '6',
-            ':',
-             'begin',
-                 'tmp_ca_state_new', '', '31', '',
-                    '=',
-                    'update_rule_reg', '', '6', '',
-                  ';',
-              'end',
-            '7',
-            ':',
-             'begin',
-                 'tmp_ca_state_new', '', '31', '',
-                    '=',
-                    'update_rule_reg', '', '7', '',
-                  ';',
-              'end',
-            'endcase',
-           'if',
-            '(', 'load_init_pattern', ')',
-             'begin',
-              'ca_state_new', '=', 'init_pattern_data', ';',
-              'end',
-            'else',
-             'begin',
-              'ca_state_new', '=', 'tmp_ca_state_new', ';',
-              'end',
-           'if',
-            '(', 'load_init_pattern', '||', 'next_pattern', ')',
-            'begin', 'ca_state_we', '=', '1', ';', 'end',
-            'else',
-            'begin', 'ca_state_we', '=', '0', ';', 'end',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/nodeinfo_test.v Deleted

@@ -1,66 +0,0 @@
-/**********************************************************************
- * $nodeinfo_test example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $nodeinfo_test PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-  reg     reg1;
-  reg 39:0 reg2;
-  integer int1;
-  time    time1;
-  real    real1;
-  wire (strong0, weak1) w1 = reg1;
-  wire 0:39 w2 = reg2;
-  parameter param1 = 1;
-  parameter 7:0 param2 = 2;
-  parameter 47:0 param3 = 3;
-  parameter param4 = 4.1;
-
-  reg 23:0 RAM 0:3;
-  integer ARRAY 1:0;
-
-  initial
-    begin
-      reg1 = 1'bx;
-      reg2 = {10{4'b01ZX}};
-      int1 = "ABCD";
-      time1 = 'h25;
-      real1 = 3.1415;
-      RAM0 = "EFG";
-
-      #1 $nodeinfo_test(reg1);
-      #1 $nodeinfo_test(reg2);
-      #1 $nodeinfo_test(reg229:20);
-      #1 $nodeinfo_test(int19:2);
-      #1 $nodeinfo_test(time13);
-      #1 $nodeinfo_test(real1);
-      #1 $nodeinfo_test(w1);
-      #1 $nodeinfo_test(w2);
-      #1 $nodeinfo_test(param1);
-      #1 $nodeinfo_test(param2);
-      #1 $nodeinfo_test(param3);
-      #1 $nodeinfo_test(param4);
-      #1 $nodeinfo_test(RAM0);
-      #1 $nodeinfo_test(ARRAY0);
-
-      //unsupported expressions
-      #1 $nodeinfo_test(w239);
-      #1 $nodeinfo_test(w236:39);
-      #1 $nodeinfo_test();
-      #1 $nodeinfo_test(5);
-      #1 $nodeinfo_test("foobar");
-
-      #1 $finish;
-    end
-
-endmodule
-
-/**********************************************************************/
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/onehot.v Deleted

@@ -1,220 +0,0 @@
-// 
-// Just a little demo of some FSM techniques, including One-Hot and
-// using 'default' settings and the case statements to selectively
-// update registers (sort of like J-K flip-flops).
-//
-// tom coonan, 12/98.
-//
-module onehot (clk, resetb, a, b, x, y);
-
-input clk;
-input resetb;
-input 7:0 a;
-input 7:0 b;
-output 7:0 x;
-output 7:0 y;
-
-// Use One-Hot encoding.  There will be 16 states.
-//
-reg 15:0 state, next_state;
-
-// These are working registers.  Declare the register itself (e.g. 'x') and then
-// the input bus used to load in a new value (e.g. 'x_in').  The 'x_in' bus will
-// physically be a wire bus and 'x' will be the flip-flop register ('x_in' must
-// be declared 'reg' because it's used in an always block.
-//
-reg 7:0 x, x_in;
-reg 7:0 y, y_in;
-
-// Update state.  'state' is the actual flip-flop register and next_state is the combinatorial
-// bus used to update 'state''s value.  Check for the ZERO state which means an unexpected
-// next state was computed.  If this occurs, jump to our initialization state; state0.
-// 
-// It is considered good practice by many designers to seperate the combinatorial
-// and sequential aspects of state registers, and often registers in general.
-//
-always @(posedge clk or negedge resetb) begin
-   if (~resetb) state <= 0;
-   else begin
-      if (next_state == 0) begin
-         state <= 16'h0001;
-      end
-      else begin
-         state <= next_state;
-      end
-   end
-end
-
-// Implement the X flip-flop register.  Always load the input bus into the register.
-// Reset to zero.
-//
-always @(posedge clk or negedge resetb) begin
-   if (~resetb) x <= 0;
-   else         x <= x_in;
-end
-
-// Implement the Y flip-flop register.  Always load the input bus into the register.
-// Reset to zero.
-//
-always @(posedge clk or negedge resetb) begin
-   if (~resetb) y <= 0;
-   else         y <= y_in;
-end
-
-// Generate the next_state function.  Also, based on the current state, generate
-// any new values for X and Y.
-//
-always @(state or a or b or x or y) begin
-   // *** Establish defaults.
-   
-   // Working registers by default retain their current value.  If any particular
-   // state does NOT need to change a register, then it doesn't have to reference
-   // the register at all.  In these cases, the default below takes affect.  This
-   // turns out to be a pretty succinct way to control stuff from the FSM.
-   //
-   x_in <= x;
-   y_in <= y;
-   
-   // State by default will be cleared.  If we somehow ever got into an unknown
-   // state, then the default would throw state machine back to zero.  Look
-   // at the sequential 'always' block for state to see how this is handled.
-   //
-   next_state <= 0;
-   
-   // One-Hot State Machine Encoding.
-   //
-   // *** Using a 1'b1 in the case statement is the trick to doing One-Hot...
-   //     DON'T include a 'default' clause within the case because we want to
-   //     establish the defaults above. ***
-   //
-   case (1'b1) // synopsys parallel_case
-   
-      // Initialization state.  Set X and Y register to some interesting starting values.
-      //
-      state0:
-         begin
-            x_in <= 8'd20;
-            y_in <= 8'd100;
-            next_state1 <= 1'b1;
-         end
-      
-      // Just for fun.. Jump through states..  
-      state1: next_state2 <= 1'b1;
-      state2: next_state3 <= 1'b1;
-      state3: next_state4 <= 1'b1;
-      state4: next_state5 <= 1'b1;
-      state5: next_state6 <= 1'b1;
-      state6: next_state7 <= 1'b1;
-      
-      // Conditionally decrement Y register.
-      state7:
-         begin
-            if (a == 1) begin
-               y_in <= y - 1;
-               next_state1 <= 1'b1;
-            end
-            else begin
-               next_state8 <= 1'b1;
-            end
-         end
-        
-      // Just for fun.. Jump through states..  
-      state8: next_state9   <= 1'b1;
-      state9: next_state10  <= 1'b1;
-      state10: next_state11 <= 1'b1;
-
-      // Conditionally increment X register.
-      state11:
-         begin
-            if (b == 1) begin
-               x_in <= x + 1;
-               next_state1 <= 1'b1;
-            end
-            else begin
-               next_state12 <= 1'b1;
-            end
-         end
-
-      // Just for fun.. Jump through states..  
-      state12: next_state13 <= 1'b1;
-      state13: next_state14 <= 1'b1;
-      state14: next_state15 <= 1'b1;
-      state15: next_state1  <= 1'b1; // Don't go back to our initialization state, but state following that one.
-    endcase
-end
-endmodule
-
-// synopsys translate_off
-module test_onehot;
-reg clk, resetb;
-reg 7:0 a;
-reg 7:0 b;
-wire 7:0 x;
-wire 7:0 y;
-
-// Instantiate module.
-//
-onehot onehot (
-   .clk(clk),
-   .resetb(resetb),
-   .a(a),
-   .b(b),
-   .x(x),
-   .y(y)
-);
-
-// Generate clock.
-//
-initial begin
-   clk = 0;
-   forever begin
-      #10 clk = ~clk;
-   end
-end
-
-// Reset..
-//
-initial begin
-   resetb = 0;
-   #33 resetb = 1;
-end
-
-// Here's the test.
-//
-// Should see X and Y get initially loaded with their starting values.
-// As long as a and b are zero, nothing should change.
-// When a is asserted, Y should slowly decrement.  When b is asserted, X should
-// slowly increment.  That's it.
-//
-initial begin 
-   a = 0;
-   b = 0;
-   repeat (64) @(posedge clk);
-   #1
-   
-   // Y should be decremented..
-   a = 1;
-   b = 0;
-   repeat (256) @(posedge clk);
-   #1
-   
-   // X should be incremented..
-   a = 0;
-   b = 1;
-   repeat (256) @(posedge clk);
-   
-   $finish;
-end
-
-// Monitor the module.
-//
-initial begin
-   forever begin
-      @(posedge clk);
-      #1;
-      $display ("a = %b, b = %b, x = %0d, y = %0d", a,b,x,y);
-   end
-end
-      
-endmodule
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/or.v Deleted

@@ -1,153 +0,0 @@
-// Verilog HDL for "gates.lib", "or_gate" "_functional"
-// Module OR gate
-module or_gate (a, b, clk, out);
-
-input
-	a, b, clk;
-
-output
-	out;
-reg 
-	out;
-
-parameter
-	t_hold=5,
-	t_setup=10,
-	delay=15,
-
-	warning_file=3;  // multichannel description of a warning file
-
-reg
-	a_internal, b_internal, clk_internal,
-	a_state, b_state,          // internal state at inputs a and b
-	a_set, b_set;		   // signals determining the moment when
-				   // the state of the a,b inputs changes to "1"
-integer
-	data_delay, 	// delay between a (b) and a_internal (b_internal)
-	clk_delay, 	// delay between clk and clk_internal
-	out_delay, 	// delay between clk_internal and out
-	out_value,	// output value in a given clock cycle
-	last_clk_time;	// time when the last clock pulse appeared
-
-initial 
-	begin
-// define delays between inputs & outputs and the corresponding
-//  internal auxiliary registers
-	  	if(t_hold<0)
-		  begin
-	    		data_delay = -t_hold;
-	    	  	clk_delay = 0;
-		  	out_delay = delay;
-		  end
-	  	else
-		  begin
-	    	  	data_delay = 0;
-	    	  	clk_delay = t_hold;
-		  	out_delay=delay-t_hold;
-		  end
-
-// clear internal registers and the output signal
-		a_internal = 0;
-		b_internal = 0;
-		clk_internal = 0;
-		last_clk_time = 0;
-		a_state = 0;
-		b_state = 0;
-		a_set = 0;
-		b_set = 0;
-		out = 0;
-	end
-
-always @(posedge a) 	// Execute at positive edge of a
-	  a_internal <= #(data_delay) a;
-
-always @(posedge b) 	// Execute at positive edge of b
-	  b_internal <= #(data_delay) b;
-
-always @(posedge clk) 	// Execute at positive edge of clk
-	  clk_internal <= #(clk_delay) clk;
-
-always @(posedge a_internal)
-	begin
-// setting an internal state at the input a
-                a_state <= a_state | 1'bx;
-		if (a_internal === 1)
-		  a_set <= #(t_hold+t_setup) 1;
-
-		a_internal <= 0;
-	end
-
-always @(posedge b_internal)
-	begin
-// setting an internal state at the input a
-                b_state <= b_state | 1'bx;
-		if (b_internal === 1)
-		  b_set <= #(t_hold+t_setup) 1;
-
-		b_internal <= 0;
-	end
-
-always @(posedge a_set)
-	begin
-		if ($stime - last_clk_time >= t_hold+t_setup)
-			a_state = 1;
-		else
-		  begin
-			a_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input A pulse at %0d,",
-			 $stime-data_delay-t_hold-t_setup);
-			$fwrite(warning_file,
-			"\tClock pulse at %0d.\n", last_clk_time-clk_delay);
-		  end
-
-		a_set <= 0;
-	end
-
-always @(posedge b_set)
-	begin
-		if ($stime - last_clk_time >= t_hold+t_setup)
-			b_state = 1;
-		else
-		  begin
-			b_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input B pulse at %0d,",
-			 $stime-data_delay-t_hold-t_setup);
-			$fwrite(warning_file,
-			"\tClock pulse at %0d.\n", last_clk_time-clk_delay);
-		  end
-
-		b_set <= 0;
-	end
-
-
-always @(posedge clk_internal)	
-	begin
-// computing the output
-		if (clk_internal === 1'bx)
-		  out_value = 1'bx;
-		else
-		  out_value = a_state | b_state;
-
-// transfering the result to the output
-		out <= #(out_delay) out_value;
-		out <= #(out_delay+2) 0;
-
-// clearing the internal state of A and B inputs
-		a_state  <= 0;
-		b_state  <= 0;
-
-		clk_internal <= 0;
-		last_clk_time = $stime;
-	end
-
-endmodule

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/out_port.v Deleted

@@ -1,98 +0,0 @@
-/* Output port */
-// Author Andrew Laffely
-// Last modified: 12 Feb 03
-// !!!!!!!!!!!!!!! DO NOT CHANGE THIS FILE !!!!!!!!!!!!!!!!!!!!!!!!!
-module out_port (gclock, reset, i_addr, c_data, c_addr, c_write, valid_next, data_out, ready);
-
-input gclock, reset;
-input 1:0 i_addr;     // buffer address requested by ccm
-input 1:0 c_addr;     // buffer address requested by core
-input 31:0 c_data;    // the data sent from the core
-input valid_next;       // flow control bit sent from upstream block
-input c_write;	        // write singal from core
-
-output 32:0 data_out; // the data to be sent to interface
-output 2:0 ready;     // flow control, port "ready" signal, sent to core
-reg 32:0 data_out;
-reg 2:0 ready;        // Port ready signal
-
-reg 6:0 valid;        // contains the valid bits of the data in the port
-reg 31:0 data 6:0;  // the data in the cdm
-reg 2:0 i_addr_hold;  // hold the buf addr while evaluating  
-reg 2:0 c_addr_hold;  // hold the buf addr while evaluating
-reg 2:0 i_buf_state, c_buf_state; // first or second buf in each port
-
-reg faketiming;         // Makes level sensitive transitions work properly
-initial
-begin
-	faketiming = 1'b0;
-	forever #1 faketiming = ~faketiming;
-end
-
-// *********************** INTERCONNECT *********************** //
-always @ (posedge gclock)  //interconnect side
-  begin
-    if(!reset)
-      begin
-	//update valid from last transfer
-	if(!(i_addr_hold2:1 == 2'b11))  
-	  begin
-	    if(!(valid_next)&&data_out32)
-	      begin
-		i_buf_statei_addr_hold2:1=~i_buf_statei_addr_hold2:1;
-		validi_addr_hold=0;
-	      end
-	  end
-
-	#1 i_addr_hold = {i_addr,i_buf_statei_addr};
-
-	//send data
-	if(!(i_addr == 2'b11))  //default no data
-		#1 data_out={validi_addr_hold, datai_addr_hold};
-	else
-		#1 data_out32=0;
-	end
-end
-// ******************** END INTERCONNECT *********************** //
-
-// *************************** CORE **************************** //
-always @ (posedge c_write)
-  begin
-	c_addr_hold = {c_addr, c_buf_statec_addr};
-  end
-
-always @ (negedge c_write) //Core
-  begin
-	if(!reset)
-	  begin
-		c_buf_statec_addr_hold2:1=~c_buf_statec_addr_hold2:1;
-		validc_addr_hold=1;  //glitch reset
-	  end
-  end
-// ************************** END CORE ************************* //
-
-always @ (faketiming)
-  begin
-    if (reset)
-      begin
-	valid = 4'b0000;
-	i_addr_hold = 3'b111;
-	i_buf_state=3'b000;
-	c_buf_state=3'b000;
-      end
-   else
-      begin
-	ready0=~validc_buf_state0;
-	ready1=~validc_buf_state1;
-	ready2=~validc_buf_state2;
-
-	// *************************** CORE ************************ //
-	if (c_write)
-	  begin
-		datac_addr_hold=c_data31:0;
-	  end
-	// ************************ END CORE ********************** //
-  end
-end
-endmodule
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/Ctr3sr.v.parsed.txt Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/TestCtr3sr.v.parsed.txt Deleted

@@ -1,53 +0,0 @@
-module TestCtr3sr;
-
-reg Clk;		// Clock: rising edge
-reg Reset;		// synchronous reset
-wire 1:0 Out;		// output
-
-	Ctr3sr c(Clk, Reset, Out); // design for test
-	initial 
-	begin
-		$dumpfile("TestCtr3sr.vcd"); // command to generate a dumpfile
-		$dumpvars(0); 		     // put all variables in the dumpfile
-			Reset = 0;	
-			#50 Reset = 1;	// reset not activ
-			#20 Reset = 0;	// reset activ
-			#200 Reset = 1; // after 1 periode reset not activ
-			#20 Reset = 0; 	// after a while again
-		$finish;
-	end
-	initial // generate clock
-	begin
-		Clk = 0; 
-		while (1)
-			#10 Clk = !Clk;
-	end
-endmodule
-
-
-  'module', 'TestCtr3sr', ';',
-     'reg', 'Clk', ';',
-      'reg', 'Reset', ';',
-      'wire', '', '1', ':', '0', '', 'Out', ';',
-      'Ctr3sr', 'c', '(', 'Clk', 'Reset', 'Out', ')', ';',
-       'initial',
-         'begin',
-           '$dumpfile', '(', '"TestCtr3sr.vcd"', ')', ';',
-            '$dumpvars', '(', '0', ')', ';',
-            'Reset', '=', '0', ';',
-            '#', '50', 'Reset', '=', '1', ';',
-            '#', '20', 'Reset', '=', '0', ';',
-            '#', '200', 'Reset', '=', '1', ';',
-            '#', '20', 'Reset', '=', '0', ';',
-            '$finish', ';',
-          'end',
-       'initial',
-         'begin',
-           'Clk', '=', '0', ';',
-             'while',
-              '(',
-              '1',
-              ')',
-              '#', '10', 'Clk', '=', '!', 'Clk', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/addacc.v.parsed.txt Deleted

@@ -1,90 +0,0 @@
-// Verilog HDL for "gates.lib", "addacc" "_functional"
-// Module Adder Accumulator
-// 
-//
-module addacc (a, b, clk, rd, cout, sout);
-
-input
-	a, b, clk, rd;
-
-output
-	cout, sout;
-wire
-	cout, sout;
-
-parameter
-	t_hold	= -43,
-	t_setup	= 48,
-	delay	= 12,
-	rd_hold = -14,
-	rd_setup = 35,
-	rd_delay = 17,
-	t_separation = 10;
-
-defparam
-	  aacdro.delay = delay,
-	  aact1ff.rd1_delay = rd_delay,
-	  aacconf.t_separation = t_separation,
-
-	  aact1ff.t_separation = t_separation - 2,
-
-	  aacconf.delay = 20,
-	  aact1ff.delay = 20,
-	  
-	  aact1ff.t_hold  = rd_hold  + 20,
-	  aact1ff.t_setup = rd_setup - 20,
-	  aacdro.t_hold  = t_hold + 40,
-	  aacdro.t_setup = t_setup - 40;
-
-wire
-	t_in, t_out;
-
-
-conf_buff  aacconf(a, b, t_in);
-t1ff       aact1ff(t_in, rd, t_out, sout);
-dro_cell   aacdro(t_out, clk, cout);
-
-
-endmodule
-	
-
-
-   'module',
-      'addacc',
-      '(',
-      'a', 'b', 'clk', 'rd', 'cout', 'sout',
-      ')',
-      ';',
-     'input', 'a', 'b', 'clk', 'rd', ';',
-      'output', 'cout', 'sout', ';',
-      'wire', 'cout', 'sout', ';',
-       'parameter',
-        't_hold', '=', '-', '43',
-        't_setup', '=', '48',
-        'delay', '=', '12',
-        'rd_hold', '=', '-', '14',
-        'rd_setup', '=', '35',
-        'rd_delay', '=', '17',
-        't_separation', '=', '10',
-        ';',
-       'defparam',
-        'aacdro.delay', '=', 'delay',
-        'aact1ff.rd1_delay', '=', 'rd_delay',
-        'aacconf.t_separation', '=', 't_separation',
-        'aact1ff.t_separation', '=', 't_separation', '-', '2',
-        'aacconf.delay', '=', '20',
-        'aact1ff.delay', '=', '20',
-        'aact1ff.t_hold', '=', 'rd_hold', '+', '20',
-        'aact1ff.t_setup', '=', 'rd_setup', '-', '20',
-        'aacdro.t_hold', '=', 't_hold', '+', '40',
-        'aacdro.t_setup', '=', 't_setup', '-', '40',
-        ';',
-      'wire', 't_in', 't_out', ';',
-      'conf_buff', 'aacconf', '(', 'a', 'b', 't_in', ')', ';',
-       't1ff',
-        'aact1ff', '(', 't_in', 'rd', 't_out', 'sout', ')',
-        ';',
-       'dro_cell',
-        'aacdro', '(', 't_out', 'clk', 'cout', ')',
-        ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/addacc1_dro.v.parsed.txt Deleted

@@ -1,339 +0,0 @@
-// Verilog HDL for "RSFQ.lib", "dro_cell" "_functional"
-
-// Module DRO cell
-module addacc1_dro (d, clk, out);
-
-input
-	d, clk;
-
-output
-	out;
-reg 
-	out;
-
-parameter
-	t_hold	= -6,
-	t_setup	= 10,
-	delay	= 12,
-
-// multichannel description of a warning file
-	warning_file=2,  
-// multichannel description of a delay file
-	delay_file = warning_file<<1;
-
-reg
-	d_internal, clk_internal,
-	d_state,          	   // internal state at the input d
-	d_set;		   	   // signal determining the moment when
-				   // the state of the d input changes to "1"
-
-integer
-	data_delay,  // delay between d and d_internal
-	clk_delay,   // delay between clk and clk_internal
-	out_delay,   // delay between clk_internal and out
-	out_value,   // output value in a given clock cycle
-	last_clk_time,	// time when the last clock pulse appeared
-	vt_hold,	// variable hold
-	vt_setup,	// variable setup
-	vdelay;	     // variable delay
-
-`include "INIT"
-
-`ifdef RANDOM_DELAYS
-  `include "RANDOM_GATE"
-`endif
-
-initial 
-	begin
-		vt_hold = t_hold;
-		vt_setup = t_setup;
-		vdelay = delay;
-
-//`ifdef RANDOM_DELAYS
-		delay_dev = addacc1_dro_variation*delay;
-		vdelay = $dist_normal(addacc1_dro_seed, delay, delay_dev);
-		vt_hold = $dist_normal(addacc1_dro_seed, t_hold,
-                                        addacc1_dro_hs_dev);
-		vt_setup = t_setup + (t_hold - vt_hold);
-//`endif
-
-		#1 $fdisplay(delay_file, "module=%m, nom_delay=%0d, delay=%0d", delay, vdelay);
-		#1 $fdisplay(delay_file, "module=%m, nom_hold=%0d, hold=%0d", t_hold, vt_hold);
-		#1 $fdisplay(delay_file, "module=%m, nom_setup=%0d, setup=%0d", t_setup, vt_setup);
-
-
-// define delays between inputs & outputs and the corresponding
-//  internal auxiliary registers
-	  	if(vt_hold<0)
-		  begin
-	    	  	data_delay = -vt_hold;
-	    		clk_delay  = 0;
-			out_delay  = vdelay;
-		  end
-	  	else
-		  begin
-	   	  	data_delay = 0;
-	    		clk_delay  = vt_hold;
-		  	out_delay  = vdelay-vt_hold;
-		  end
-
-// clear internal registers and the output signal
-		d_internal = 0;
-		clk_internal = 0;
-		last_clk_time = 0;
-		d_state = 0;
-		d_set = 0;
-		out = 0;
-	end
-
-
-always @(posedge d) 	// Execute at positive edge of d
-	  d_internal <= #(data_delay) d;
-
-always @(posedge clk)  // Execute at positive edge of clk
-	  clk_internal <= #(clk_delay) clk;
-
-
-always @(posedge d_internal)
-	begin
-// setting the state of the d input
-                d_state <= d_state | 1'bx;
-		if (d_internal === 1)
-		  d_set <= #(vt_hold+vt_setup) 1;
-
-		d_internal <= 0;
-	end
-        
-
-always @(posedge d_set)
-	begin
-		if ($stime - last_clk_time >= vt_hold+vt_setup)
-			d_state = 1;
-		else
-		  begin
-			d_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input D pulse at %0d,",
-			 $stime-data_delay-vt_hold-vt_setup);
-			$fwrite(warning_file,
-			"\tClock pulse at %0d.\n", last_clk_time-clk_delay);
-		  end
-
-		d_set <= 0;
-	end
-
-
-always @(posedge clk_internal)	
-	begin
-// computing the output
-		if (clk_internal === 1'bx)
-		  out_value = 1'bx;
-		else
-		  out_value = d_state;
-
-// transfering the result to the output
-		out <= #(out_delay) out_value;
-		out <= #(out_delay+2) 0;
-
-// clearing the internal state of the DRO
-		d_state  <= 0;
-
-		clk_internal <= 0;
-		last_clk_time = $stime;
-	end
-
-endmodule
-
-
-  'module', 'addacc1_dro', '(', 'd', 'clk', 'out', ')', ';',
-     'input', 'd', 'clk', ';',
-      'output', 'out', ';',
-      'reg', 'out', ';',
-       'parameter',
-        't_hold', '=', '-', '6',
-        't_setup', '=', '10',
-        'delay', '=', '12',
-        'warning_file', '=', '2',
-        'delay_file', '=', 'warning_file', '<<', '1',
-        ';',
-      'reg', 'd_internal', 'clk_internal', 'd_state', 'd_set', ';',
-       'integer',
-        'data_delay',
-        'clk_delay',
-        'out_delay',
-        'out_value',
-        'last_clk_time',
-        'vt_hold',
-        'vt_setup',
-        'vdelay',
-        ';',
-       'initial',
-         'begin',
-           'vt_hold', '=', 't_hold', ';',
-            'vt_setup', '=', 't_setup', ';',
-            'vdelay', '=', 'delay', ';',
-             'delay_dev', '=', 'addacc1_dro_variation', '*', 'delay',
-              ';',
-              'vdelay',
-                '=',
-                 '$dist_normal',
-                  '(',
-                  'addacc1_dro_seed',
-                  'delay',
-                  'delay_dev',
-                  ')',
-              ';',
-              'vt_hold',
-                '=',
-                 '$dist_normal',
-                  '(',
-                  'addacc1_dro_seed',
-                  't_hold',
-                  'addacc1_dro_hs_dev',
-                  ')',
-              ';',
-              'vt_setup',
-                '=',
-                't_setup',
-                '+',
-                '(',
-                't_hold', '-', 'vt_hold',
-                ')',
-              ';',
-             '#', '1',
-               '$fdisplay',
-                '(',
-                'delay_file',
-                '"module=%m, nom_delay=%0d, delay=%0d"',
-                'delay',
-                'vdelay',
-                ')',
-                ';',
-             '#', '1',
-               '$fdisplay',
-                '(',
-                'delay_file',
-                '"module=%m, nom_hold=%0d, hold=%0d"',
-                't_hold',
-                'vt_hold',
-                ')',
-                ';',
-             '#', '1',
-               '$fdisplay',
-                '(',
-                'delay_file',
-                '"module=%m, nom_setup=%0d, setup=%0d"',
-                't_setup',
-                'vt_setup',
-                ')',
-                ';',
-             'if',
-              '(', 'vt_hold', '<', '0', ')',
-               'begin',
-                 'data_delay', '=', '-', 'vt_hold', ';',
-                  'clk_delay', '=', '0', ';',
-                  'out_delay', '=', 'vdelay', ';',
-                'end',
-              'else',
-               'begin',
-                 'data_delay', '=', '0', ';',
-                  'clk_delay', '=', 'vt_hold', ';',
-                  'out_delay', '=', 'vdelay', '-', 'vt_hold', ';',
-                'end',
-            'd_internal', '=', '0', ';',
-            'clk_internal', '=', '0', ';',
-            'last_clk_time', '=', '0', ';',
-            'd_state', '=', '0', ';',
-            'd_set', '=', '0', ';',
-            'out', '=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'd', ')',
-         'd_internal', '<=', '#', '(', 'data_delay', ')', 'd',
-          ';',
-       'always',
-        '@', '(', 'posedge', 'clk', ')',
-         'clk_internal', '<=', '#', '(', 'clk_delay', ')', 'clk',
-          ';',
-       'always',
-        '@', '(', 'posedge', 'd_internal', ')',
-         'begin',
-           'd_state', '<=', 'd_state', '|', "1 'b x", ';',
-             'if',
-              '(', 'd_internal', '===', '1', ')',
-                'd_set',
-                  '<=',
-                  '#', '(', 'vt_hold', '+', 'vt_setup', ')',
-                  '1',
-                ';',
-            'd_internal', '<=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'd_set', ')',
-         'begin',
-            'if',
-               '(',
-                '$stime',
-                '-',
-                'last_clk_time',
-                '>=',
-                'vt_hold',
-                '+',
-                'vt_setup',
-                ')',
-              'd_state', '=', '1', ';',
-              'else',
-               'begin',
-                 'd_state', '=', "1 'b x", ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Violation of hold/setup time in module %m.\\n"',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Input D pulse at %0d,"',
-                    '$stime',
-                    '-',
-                    'data_delay',
-                    '-',
-                    'vt_hold',
-                    '-',
-                    'vt_setup',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"\\tClock pulse at %0d.\\n"',
-                    'last_clk_time',
-                    '-',
-                    'clk_delay',
-                    ')',
-                    ';',
-                'end',
-            'd_set', '<=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'clk_internal', ')',
-         'begin',
-            'if',
-              '(', 'clk_internal', '===', "1 'b x", ')',
-              'out_value', '=', "1 'b x", ';',
-              'else',
-              'out_value', '=', 'd_state', ';',
-             'out', '<=', '#', '(', 'out_delay', ')', 'out_value',
-              ';',
-             'out', '<=', '#', '(', 'out_delay', '+', '2', ')', '0',
-              ';',
-            'd_state', '<=', '0', ';',
-            'clk_internal', '<=', '0', ';',
-            'last_clk_time', '=', '$stime', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/addacc1_t1ff.v.parsed.txt Deleted

@@ -1,477 +0,0 @@
-// Verilog HDL for "RSFQ.lib", "t1ff" "_functional"
-
-// Module T1 flip-flop
-module addacc1_t1ff (t, wr0, out, rd1);
-
-input
-	t, wr0;
-
-output
-	out, rd1;
-reg 
-	out, rd1;
-
-parameter
-	t_separation 	=  8,
-	delay		= 35,
-	t_hold 		= -12,
-	t_setup 	= 32,
-	rd1_delay	= 17,
-
-// multichannel description of a warning file
-	warning_file=2,  
-// multichannel description of a delay file
-	delay_file = warning_file<<1;
-
-reg
-	t_internal, wr0_internal, // signals at inputs after i/o stage
-	t_state,  // internal state of T flip-flop
-	sep_clr,  // signal marking the end of the separation zone
-	hs_clr;	  // signal marking the end of the hold/setup zone
-
-
-integer
-	data_delay, 	// delay between t and t_internal
-	wr0_delay, 	// delay between rd and rd_internal
-	t_out_delay, 	// delay between t_internal and out
-	wr0_out_delay,  // delay between rd_internal and out
-	last_t_time,    // time when the last t pulse appeared
-	last_wr0_time,  // time when the last wr0 pulse appeared
-	in_hs,    // number of t pulses in hold/setup zone
-	in_sep,	 // number of pulses within an interval t_sep before 
-		 //  the last data pulse
-	out_value, // value at the output
-	vt_hold,	// variable hold
-	vt_setup,	// variable setup
-	vdelay;    // variable delay
-
-`include "INIT"
-
-`ifdef RANDOM_DELAYS
- `include "RANDOM_GATE"
-`endif
-
-initial 
-	begin
-		vt_hold = t_hold;
-		vt_setup = t_setup;
-		vdelay = delay;
-
-`ifdef RANDOM_DELAYS
-		delay_dev = addacc1_t1ff_variation*delay;
-		vdelay = $dist_normal(addacc1_t1ff_seed, delay, delay_dev);
-		vt_hold = $dist_normal(addacc1_t1ff_seed, t_hold, 
-                                           addacc1_t1ff_hs_dev);
-		vt_setup = t_setup + (t_hold - vt_hold);
-`endif
-
-		#1 $fdisplay(delay_file, "module=%m, nom_delay=%0d, delay=%0d", delay, vdelay);
-		#1 $fdisplay(delay_file, "module=%m, nom_hold=%0d, hold=%0d", t_hold, vt_hold);
-		#1 $fdisplay(delay_file, "module=%m, nom_setup=%0d, setup=%0d", t_setup, vt_setup);
-
-
-// define delays between inputs & outputs and the corresponding
-//  internal auxiliary registers
-	  	if(vt_hold<0)
-		  begin
-	    	  	data_delay = -vt_hold;
-	    		wr0_delay  = 0;
-		  end
-	  	else
-		  begin
-	   	  	data_delay = 0;
-	    		wr0_delay  = vt_hold;
-		  end
-		t_out_delay  = vdelay-data_delay;
-		wr0_out_delay = rd1_delay-wr0_delay;
-
-// clear internal registers and the output signal
-		t_internal = 0;
-		wr0_internal = 0;
-		t_state = 0;
-		in_hs = 0;
-		in_sep = 0;
-		sep_clr = 0;
-		hs_clr = 0;
-		out = 0;
-		rd1 = 0;
-	end
-
-
-always @(posedge t) 	// Execute at positive edge of t
-	  t_internal <= #(data_delay) t;
-
-always @(posedge wr0) 	// Execute at positive edge of t
-	  wr0_internal <= #(wr0_delay) wr0;
-
-
-always @(posedge t_internal)
-	begin
-	  if (in_sep>0)
-	    begin
-	      t_state = 1'bx;
-
-	    // generating a warning
-	      $fwrite(warning_file, 
-	       "Violation of separation time in module %m.\n");
-	      $fwrite(warning_file,
-	       "Input T pulses at %0d and at %0d.\n", last_t_time, 
-	       $stime-data_delay);
-            end
-	  last_t_time <= $stime-data_delay;
-
-	  out <= #t_out_delay t_state;
-	  out <= #(t_out_delay+2) 0;
-
-	  t_state = t_state ^ 1;
-	  if (t_internal === 1)
-	    begin
-	      in_sep = in_sep + 1;
-	      sep_clr <= #(t_separation) 1;
-	    end
-	  else
-	    t_state = 1'bx;
-
-// setting the state of the t input
-	  if (t_internal === 1)
-	    begin
-	      in_hs = in_hs+1;
-	      hs_clr <= #(vt_hold+vt_setup) 1;
-	    end
-	  else
-	    t_state = 1'bx;
-
-	  t_internal <= 0;
-	end
-
-
-always @(posedge hs_clr)
-	begin
-		if ($stime - last_wr0_time < vt_hold+vt_setup)
-		  begin
-			t_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input T pulse at %0d,",
-			 $stime-data_delay-vt_hold-vt_setup);
-			$fwrite(warning_file,
-			"\tInput WRITE0 pulse at %0d.\n",
-			 last_wr0_time-wr0_delay);
-		  end
-
-		in_hs = in_hs-1;
-		hs_clr <= 0;
-	end
-
-always @(posedge sep_clr)
-	begin
-	  	in_sep = in_sep - 1;
-		sep_clr <= 0;
-	end
-
-
-always @(posedge wr0_internal)	
-	begin
-// computing the output
-		if ((wr0_internal === 1'bx) || (in_hs>0))
-		  out_value = 1'bx;
-		else
-		  out_value = t_state;
-
-// transfering the result to the output
-		rd1 <= #(wr0_out_delay) out_value;
-		rd1 <= #(wr0_out_delay+2) 0;
-
-// clearing the internal state of T1 flip-flop
-		if(in_hs == 0)
-		  t_state  = 0;
-		else
-		  t_state = 1'bx;
-
-		wr0_internal <= 0;
-		last_wr0_time = $stime;
-	end
-
-
-endmodule
-
-
-   'module',
-      'addacc1_t1ff',
-      '(',
-      't', 'wr0', 'out', 'rd1',
-      ')',
-      ';',
-     'input', 't', 'wr0', ';',
-      'output', 'out', 'rd1', ';',
-      'reg', 'out', 'rd1', ';',
-       'parameter',
-        't_separation', '=', '8',
-        'delay', '=', '35',
-        't_hold', '=', '-', '12',
-        't_setup', '=', '32',
-        'rd1_delay', '=', '17',
-        'warning_file', '=', '2',
-        'delay_file', '=', 'warning_file', '<<', '1',
-        ';',
-       'reg',
-        't_internal',
-        'wr0_internal',
-        't_state',
-        'sep_clr',
-        'hs_clr',
-        ';',
-       'integer',
-        'data_delay',
-        'wr0_delay',
-        't_out_delay',
-        'wr0_out_delay',
-        'last_t_time',
-        'last_wr0_time',
-        'in_hs',
-        'in_sep',
-        'out_value',
-        'vt_hold',
-        'vt_setup',
-        'vdelay',
-        ';',
-       'initial',
-         'begin',
-           'vt_hold', '=', 't_hold', ';',
-            'vt_setup', '=', 't_setup', ';',
-            'vdelay', '=', 'delay', ';',
-             'delay_dev', '=', 'addacc1_t1ff_variation', '*', 'delay',
-              ';',
-              'vdelay',
-                '=',
-                 '$dist_normal',
-                  '(',
-                  'addacc1_t1ff_seed',
-                  'delay',
-                  'delay_dev',
-                  ')',
-              ';',
-              'vt_hold',
-                '=',
-                 '$dist_normal',
-                  '(',
-                  'addacc1_t1ff_seed',
-                  't_hold',
-                  'addacc1_t1ff_hs_dev',
-                  ')',
-              ';',
-              'vt_setup',
-                '=',
-                't_setup',
-                '+',
-                '(',
-                't_hold', '-', 'vt_hold',
-                ')',
-              ';',
-             '#', '1',
-               '$fdisplay',
-                '(',
-                'delay_file',
-                '"module=%m, nom_delay=%0d, delay=%0d"',
-                'delay',
-                'vdelay',
-                ')',
-                ';',
-             '#', '1',
-               '$fdisplay',
-                '(',
-                'delay_file',
-                '"module=%m, nom_hold=%0d, hold=%0d"',
-                't_hold',
-                'vt_hold',
-                ')',
-                ';',
-             '#', '1',
-               '$fdisplay',
-                '(',
-                'delay_file',
-                '"module=%m, nom_setup=%0d, setup=%0d"',
-                't_setup',
-                'vt_setup',
-                ')',
-                ';',
-             'if',
-              '(', 'vt_hold', '<', '0', ')',
-               'begin',
-                 'data_delay', '=', '-', 'vt_hold', ';',
-                  'wr0_delay', '=', '0', ';',
-                'end',
-              'else',
-               'begin',
-                 'data_delay', '=', '0', ';',
-                  'wr0_delay', '=', 'vt_hold', ';',
-                'end',
-            't_out_delay', '=', 'vdelay', '-', 'data_delay', ';',
-            'wr0_out_delay', '=', 'rd1_delay', '-', 'wr0_delay', ';',
-            't_internal', '=', '0', ';',
-            'wr0_internal', '=', '0', ';',
-            't_state', '=', '0', ';',
-            'in_hs', '=', '0', ';',
-            'in_sep', '=', '0', ';',
-            'sep_clr', '=', '0', ';',
-            'hs_clr', '=', '0', ';',
-            'out', '=', '0', ';',
-            'rd1', '=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 't', ')',
-         't_internal', '<=', '#', '(', 'data_delay', ')', 't',
-          ';',
-       'always',
-        '@', '(', 'posedge', 'wr0', ')',
-         'wr0_internal', '<=', '#', '(', 'wr0_delay', ')', 'wr0',
-          ';',
-       'always',
-        '@', '(', 'posedge', 't_internal', ')',
-         'begin',
-            'if',
-              '(', 'in_sep', '>', '0', ')',
-               'begin',
-                 't_state', '=', "1 'b x", ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Violation of separation time in module %m.\\n"',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Input T pulses at %0d and at %0d.\\n"',
-                    'last_t_time',
-                    '$stime',
-                    '-',
-                    'data_delay',
-                    ')',
-                    ';',
-                'end',
-            'last_t_time', '<=', '$stime', '-', 'data_delay', ';',
-            'out', '<=', '#', 't_out_delay', 't_state', ';',
-              'out',
-                '<=',
-                '#', '(', 't_out_delay', '+', '2', ')',
-                '0',
-              ';',
-            't_state', '=', 't_state', '^', '1', ';',
-             'if',
-              '(', 't_internal', '===', '1', ')',
-               'begin',
-                 'in_sep', '=', 'in_sep', '+', '1', ';',
-                    'sep_clr',
-                      '<=',
-                      '#', '(', 't_separation', ')',
-                      '1',
-                    ';',
-                'end',
-              'else',
-              't_state', '=', "1 'b x", ';',
-             'if',
-              '(', 't_internal', '===', '1', ')',
-               'begin',
-                 'in_hs', '=', 'in_hs', '+', '1', ';',
-                    'hs_clr',
-                      '<=',
-                      '#', '(', 'vt_hold', '+', 'vt_setup', ')',
-                      '1',
-                    ';',
-                'end',
-              'else',
-              't_state', '=', "1 'b x", ';',
-            't_internal', '<=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'hs_clr', ')',
-         'begin',
-            'if',
-               '(',
-                '$stime',
-                '-',
-                'last_wr0_time',
-                '<',
-                'vt_hold',
-                '+',
-                'vt_setup',
-                ')',
-               'begin',
-                 't_state', '=', "1 'b x", ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Violation of hold/setup time in module %m.\\n"',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Input T pulse at %0d,"',
-                    '$stime',
-                    '-',
-                    'data_delay',
-                    '-',
-                    'vt_hold',
-                    '-',
-                    'vt_setup',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"\\tInput WRITE0 pulse at %0d.\\n"',
-                    'last_wr0_time',
-                    '-',
-                    'wr0_delay',
-                    ')',
-                    ';',
-                'end',
-            'in_hs', '=', 'in_hs', '-', '1', ';',
-            'hs_clr', '<=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'sep_clr', ')',
-         'begin',
-           'in_sep', '=', 'in_sep', '-', '1', ';',
-            'sep_clr', '<=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'wr0_internal', ')',
-         'begin',
-            'if',
-               '(',
-                '(',
-                'wr0_internal', '===', "1 'b x",
-                ')',
-                '||',
-                '(',
-                'in_hs', '>', '0',
-                ')',
-                ')',
-              'out_value', '=', "1 'b x", ';',
-              'else',
-              'out_value', '=', 't_state', ';',
-              'rd1',
-                '<=',
-                '#', '(', 'wr0_out_delay', ')',
-                'out_value',
-              ';',
-              'rd1',
-                '<=',
-                '#', '(', 'wr0_out_delay', '+', '2', ')',
-                '0',
-              ';',
-             'if',
-              '(', 'in_hs', '==', '0', ')',
-              't_state', '=', '0', ';',
-              'else',
-              't_state', '=', "1 'b x", ';',
-            'wr0_internal', '<=', '0', ';',
-            'last_wr0_time', '=', '$stime', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/addacc_conf.v.parsed.txt Deleted

@@ -1,311 +0,0 @@
-// Verilog HDL for "RSFQ.lib", "conf_buff" "_functional"
-
-// Module CONFLUENCE BUFFER
-module addacc_conf (in1, in2, out);
-
-input
-	in1, in2;
-
-output
-	out;
-reg 
-	out;
-
-parameter
-	t_separation = 10,
-	delay=20,
-
-// multichannel description of a warning file
-	warning_file=2,  
-// multichannel description of a delay file
-	delay_file = warning_file<<1;
-
-reg
-	sep_clr; // signal marking the end of the min separation zone
-		 //  for the last pulse
-
-integer
-	last_in_time,    // time when the last t pulse appeared
-	in_sep,	 // number of pulses within an interval t_sep before 
-		 //  the last data pulse;
-	vdelay;		 // variable delay
-
-
-`include "INIT"
-
-`ifdef RANDOM_DELAYS
- `include "RANDOM_GATE"
-`endif
-
-
-initial 
-	begin
-		vdelay = delay;
-
-`ifdef RANDOM_DELAYS
-		delay_dev = addacc_conf_variation*delay;
-		vdelay = $dist_normal(addacc_conf_seed, delay, delay_dev);
-`endif
-
-		#1 $fdisplay(delay_file, "module=%m, nom_delay=%0d, delay=%0d", delay, vdelay);
-
-// clear internal registers and the output signal
-		last_in_time = 0;
-		in_sep = 0;
-		sep_clr = 0;
-		out = 0;
-	end
-
-always @(posedge in1)
-	begin
-		out <= #vdelay ((in_sep > 0) || (in2 == 1)) ? 1'bx : 1;
-		out <= #(vdelay+2) 0;
-		
-		if((in_sep>0) || (in2 == 1))
-	          begin
-	        // generating a warning
-	            $fwrite(warning_file, 
-	            "Violation of separation time in module %m.\n");
-	            $fwrite(warning_file,
-	            "Input pulses at ");
-		    if(in_sep>0)
-			$fwrite(warning_file,
-			"%0d and at %0d.\n", last_in_time, $stime);
-		    else
-			$fwrite(warning_file,
-			"%0d and at %0d.\n", $stime, $stime);
-	    	  end
-	  	last_in_time <= $stime;
-
-		in_sep <= in_sep + 1;
-		sep_clr <= #(t_separation-1) 1;
-	end
-
-always @(posedge in2)
-	begin
-		out <= #vdelay ((in_sep > 0) || (in1 == 1)) ? 1'bx : 1;
-		out <= #(vdelay+2) 0;
-
-		if((in_sep>0) || (in1 == 1))
-	          begin
-	        // generating a warning
-	            $fwrite(warning_file, 
-	            "Violation of separation time in module %m.\n");
-	            $fwrite(warning_file,
-	            "Input pulses at ");
-		    if(in_sep>0)
-			$fwrite(warning_file,
-			"%0d and at %0d.\n", last_in_time, $stime);
-		    else
-			$fwrite(warning_file,
-			"%0d and at %0d.\n", $stime, $stime);
-	    	  end
-	  	last_in_time <= $stime;
-
-		in_sep <= in_sep + 1;
-		sep_clr <= #(t_separation-1) 1;
-	end
-
-always @(posedge sep_clr)
-	begin
-	  	in_sep <= in_sep - 1;
-		sep_clr <= 0;
-	end
-
-
-endmodule
-
-
-  'module', 'addacc_conf', '(', 'in1', 'in2', 'out', ')', ';',
-     'input', 'in1', 'in2', ';',
-      'output', 'out', ';',
-      'reg', 'out', ';',
-       'parameter',
-        't_separation', '=', '10',
-        'delay', '=', '20',
-        'warning_file', '=', '2',
-        'delay_file', '=', 'warning_file', '<<', '1',
-        ';',
-      'reg', 'sep_clr', ';',
-      'integer', 'last_in_time', 'in_sep', 'vdelay', ';',
-       'initial',
-         'begin',
-           'vdelay', '=', 'delay', ';',
-             'delay_dev', '=', 'addacc_conf_variation', '*', 'delay',
-              ';',
-              'vdelay',
-                '=',
-                 '$dist_normal',
-                  '(',
-                  'addacc_conf_seed',
-                  'delay',
-                  'delay_dev',
-                  ')',
-              ';',
-             '#', '1',
-               '$fdisplay',
-                '(',
-                'delay_file',
-                '"module=%m, nom_delay=%0d, delay=%0d"',
-                'delay',
-                'vdelay',
-                ')',
-                ';',
-            'last_in_time', '=', '0', ';',
-            'in_sep', '=', '0', ';',
-            'sep_clr', '=', '0', ';',
-            'out', '=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'in1', ')',
-         'begin',
-             'out',
-                '<=',
-                '#', 'vdelay',
-                '(',
-                 '(',
-                  'in_sep', '>', '0',
-                  ')',
-                  '||',
-                  '(',
-                  'in2', '==', '1',
-                  ')',
-                ')',
-                '?',
-                "1 'b x",
-                ':',
-                '1',
-              ';',
-             'out', '<=', '#', '(', 'vdelay', '+', '2', ')', '0',
-              ';',
-             'if',
-               '(',
-                '(',
-                'in_sep', '>', '0',
-                ')',
-                '||',
-                '(',
-                'in2', '==', '1',
-                ')',
-                ')',
-               'begin',
-                  '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Violation of separation time in module %m.\\n"',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Input pulses at "',
-                    ')',
-                    ';',
-                   'if',
-                    '(', 'in_sep', '>', '0', ')',
-                     '$fwrite',
-                      '(',
-                      'warning_file',
-                      '"%0d and at %0d.\\n"',
-                      'last_in_time',
-                      '$stime',
-                      ')',
-                      ';',
-                    'else',
-                     '$fwrite',
-                      '(',
-                      'warning_file',
-                      '"%0d and at %0d.\\n"',
-                      '$stime',
-                      '$stime',
-                      ')',
-                      ';',
-                'end',
-            'last_in_time', '<=', '$stime', ';',
-            'in_sep', '<=', 'in_sep', '+', '1', ';',
-              'sep_clr',
-                '<=',
-                '#', '(', 't_separation', '-', '1', ')',
-                '1',
-              ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'in2', ')',
-         'begin',
-             'out',
-                '<=',
-                '#', 'vdelay',
-                '(',
-                 '(',
-                  'in_sep', '>', '0',
-                  ')',
-                  '||',
-                  '(',
-                  'in1', '==', '1',
-                  ')',
-                ')',
-                '?',
-                "1 'b x",
-                ':',
-                '1',
-              ';',
-             'out', '<=', '#', '(', 'vdelay', '+', '2', ')', '0',
-              ';',
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-               '(',
-                '(',
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-                ')',
-                '||',
-                '(',
-                'in1', '==', '1',
-                ')',
-                ')',
-               'begin',
-                  '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Violation of separation time in module %m.\\n"',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Input pulses at "',
-                    ')',
-                    ';',
-                   'if',
-                    '(', 'in_sep', '>', '0', ')',
-                     '$fwrite',
-                      '(',
-                      'warning_file',
-                      '"%0d and at %0d.\\n"',
-                      'last_in_time',
-                      '$stime',
-                      ')',
-                      ';',
-                    'else',
-                     '$fwrite',
-                      '(',
-                      'warning_file',
-                      '"%0d and at %0d.\\n"',
-                      '$stime',
-                      '$stime',
-                      ')',
-                      ';',
-                'end',
-            'last_in_time', '<=', '$stime', ';',
-            'in_sep', '<=', 'in_sep', '+', '1', ';',
-              'sep_clr',
-                '<=',
-                '#', '(', 't_separation', '-', '1', ')',
-                '1',
-              ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'sep_clr', ')',
-         'begin',
-           'in_sep', '<=', 'in_sep', '-', '1', ';',
-            'sep_clr', '<=', '0', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/addacc_dro.v.parsed.txt Deleted

@@ -1,340 +0,0 @@
-// Verilog HDL for "RSFQ.lib", "dro_cell" "_functional"
-
-// Module DRO cell
-module addacc_dro (d, clk, out);
-
-input
-	d, clk;
-
-output
-	out;
-reg 
-	out;
-
-parameter
-	t_hold	= -3,
-	t_setup	= 8,
-	delay	= 13,
-
-// multichannel description of a warning file
-	warning_file=2,  
-// multichannel description of a delay file
-	delay_file = warning_file<<1;
-
-reg
-	d_internal, clk_internal,
-	d_state,          	   // internal state at the input d
-	d_set;		   	   // signal determining the moment when
-				   // the state of the d input changes to "1"
-
-integer
-	data_delay,  // delay between d and d_internal
-	clk_delay,   // delay between clk and clk_internal
-	out_delay,   // delay between clk_internal and out
-	out_value,   // output value in a given clock cycle
-	last_clk_time,	// time when the last clock pulse appeared
-	vt_hold,	// variable hold
-	vt_setup,	// variable setup
-	vdelay;		// variable delay
-
-`include "INIT"
-
-`ifdef RANDOM_DELAYS
- `include "RANDOM_GATE"
-`endif
-
-
-initial 
-	begin
-		vt_hold = t_hold;
-		vt_setup = t_setup;
-		vdelay = delay;
-
-`ifdef RANDOM_DELAYS
-		delay_dev = addacc_dro_variation*delay;
-		vdelay = $dist_normal(addacc_dro_seed, delay, delay_dev);
-		vt_hold = $dist_normal(addacc_dro_seed, t_hold,
-                                       addacc_dro_hs_dev);
-		vt_setup = t_setup + (t_hold - vt_hold);
-`endif
-
-		#1 $fdisplay(delay_file, "module=%m, nom_delay=%0d, delay=%0d", delay, vdelay);
-		#1 $fdisplay(delay_file, "module=%m, nom_hold=%0d, hold=%0d", t_hold, vt_hold);
-		#1 $fdisplay(delay_file, "module=%m, nom_setup=%0d, setup=%0d", t_setup, vt_setup);
-
-
-// define delays between inputs & outputs and the corresponding
-//  internal auxiliary registers
-	  	if(vt_hold<0)
-		  begin
-	    	  	data_delay = -vt_hold;
-	    		clk_delay  = 0;
-			out_delay  = vdelay;
-		  end
-	  	else
-		  begin
-	   	  	data_delay = 0;
-	    		clk_delay  = vt_hold;
-		  	out_delay  = vdelay-vt_hold;
-		  end
-
-// clear internal registers and the output signal
-		d_internal = 0;
-		clk_internal = 0;
-		last_clk_time = 0;
-		d_state = 0;
-		d_set = 0;
-		out = 0;
-	end
-
-
-
-always @(posedge d) 	// Execute at positive edge of d
-	  d_internal <= #(data_delay) d;
-
-always @(posedge clk)  // Execute at positive edge of clk
-	  clk_internal <= #(clk_delay) clk;
-
-
-always @(posedge d_internal)
-	begin
-// setting the state of the d input
-                d_state <= d_state | 1'bx;
-		if (d_internal === 1)
-		  d_set <= #(vt_hold+vt_setup) 1;
-
-		d_internal <= 0;
-	end
-
-always @(posedge d_set)
-	begin
-		if ($stime - last_clk_time >= vt_hold+vt_setup)
-			d_state = 1;
-		else
-		  begin
-			d_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input D pulse at %0d,",
-			 $stime-data_delay-vt_hold-vt_setup);
-			$fwrite(warning_file,
-			"\tClock pulse at %0d.\n", last_clk_time-clk_delay);
-		  end
-
-		d_set <= 0;
-	end
-
-
-always @(posedge clk_internal)	
-	begin
-// computing the output
-		if (clk_internal === 1'bx)
-		  out_value = 1'bx;
-		else
-		  out_value = d_state;
-
-// transfering the result to the output
-		out <= #(out_delay) out_value;
-		out <= #(out_delay+2) 0;
-
-// clearing the internal state of the DRO
-		d_state  <= 0;
-
-		clk_internal <= 0;
-		last_clk_time = $stime;
-	end
-
-endmodule
-
-
-  'module', 'addacc_dro', '(', 'd', 'clk', 'out', ')', ';',
-     'input', 'd', 'clk', ';',
-      'output', 'out', ';',
-      'reg', 'out', ';',
-       'parameter',
-        't_hold', '=', '-', '3',
-        't_setup', '=', '8',
-        'delay', '=', '13',
-        'warning_file', '=', '2',
-        'delay_file', '=', 'warning_file', '<<', '1',
-        ';',
-      'reg', 'd_internal', 'clk_internal', 'd_state', 'd_set', ';',
-       'integer',
-        'data_delay',
-        'clk_delay',
-        'out_delay',
-        'out_value',
-        'last_clk_time',
-        'vt_hold',
-        'vt_setup',
-        'vdelay',
-        ';',
-       'initial',
-         'begin',
-           'vt_hold', '=', 't_hold', ';',
-            'vt_setup', '=', 't_setup', ';',
-            'vdelay', '=', 'delay', ';',
-             'delay_dev', '=', 'addacc_dro_variation', '*', 'delay',
-              ';',
-              'vdelay',
-                '=',
-                 '$dist_normal',
-                  '(',
-                  'addacc_dro_seed',
-                  'delay',
-                  'delay_dev',
-                  ')',
-              ';',
-              'vt_hold',
-                '=',
-                 '$dist_normal',
-                  '(',
-                  'addacc_dro_seed',
-                  't_hold',
-                  'addacc_dro_hs_dev',
-                  ')',
-              ';',
-              'vt_setup',
-                '=',
-                't_setup',
-                '+',
-                '(',
-                't_hold', '-', 'vt_hold',
-                ')',
-              ';',
-             '#', '1',
-               '$fdisplay',
-                '(',
-                'delay_file',
-                '"module=%m, nom_delay=%0d, delay=%0d"',
-                'delay',
-                'vdelay',
-                ')',
-                ';',
-             '#', '1',
-               '$fdisplay',
-                '(',
-                'delay_file',
-                '"module=%m, nom_hold=%0d, hold=%0d"',
-                't_hold',
-                'vt_hold',
-                ')',
-                ';',
-             '#', '1',
-               '$fdisplay',
-                '(',
-                'delay_file',
-                '"module=%m, nom_setup=%0d, setup=%0d"',
-                't_setup',
-                'vt_setup',
-                ')',
-                ';',
-             'if',
-              '(', 'vt_hold', '<', '0', ')',
-               'begin',
-                 'data_delay', '=', '-', 'vt_hold', ';',
-                  'clk_delay', '=', '0', ';',
-                  'out_delay', '=', 'vdelay', ';',
-                'end',
-              'else',
-               'begin',
-                 'data_delay', '=', '0', ';',
-                  'clk_delay', '=', 'vt_hold', ';',
-                  'out_delay', '=', 'vdelay', '-', 'vt_hold', ';',
-                'end',
-            'd_internal', '=', '0', ';',
-            'clk_internal', '=', '0', ';',
-            'last_clk_time', '=', '0', ';',
-            'd_state', '=', '0', ';',
-            'd_set', '=', '0', ';',
-            'out', '=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'd', ')',
-         'd_internal', '<=', '#', '(', 'data_delay', ')', 'd',
-          ';',
-       'always',
-        '@', '(', 'posedge', 'clk', ')',
-         'clk_internal', '<=', '#', '(', 'clk_delay', ')', 'clk',
-          ';',
-       'always',
-        '@', '(', 'posedge', 'd_internal', ')',
-         'begin',
-           'd_state', '<=', 'd_state', '|', "1 'b x", ';',
-             'if',
-              '(', 'd_internal', '===', '1', ')',
-                'd_set',
-                  '<=',
-                  '#', '(', 'vt_hold', '+', 'vt_setup', ')',
-                  '1',
-                ';',
-            'd_internal', '<=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'd_set', ')',
-         'begin',
-            'if',
-               '(',
-                '$stime',
-                '-',
-                'last_clk_time',
-                '>=',
-                'vt_hold',
-                '+',
-                'vt_setup',
-                ')',
-              'd_state', '=', '1', ';',
-              'else',
-               'begin',
-                 'd_state', '=', "1 'b x", ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Violation of hold/setup time in module %m.\\n"',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Input D pulse at %0d,"',
-                    '$stime',
-                    '-',
-                    'data_delay',
-                    '-',
-                    'vt_hold',
-                    '-',
-                    'vt_setup',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"\\tClock pulse at %0d.\\n"',
-                    'last_clk_time',
-                    '-',
-                    'clk_delay',
-                    ')',
-                    ';',
-                'end',
-            'd_set', '<=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'clk_internal', ')',
-         'begin',
-            'if',
-              '(', 'clk_internal', '===', "1 'b x", ')',
-              'out_value', '=', "1 'b x", ';',
-              'else',
-              'out_value', '=', 'd_state', ';',
-             'out', '<=', '#', '(', 'out_delay', ')', 'out_value',
-              ';',
-             'out', '<=', '#', '(', 'out_delay', '+', '2', ')', '0',
-              ';',
-            'd_state', '<=', '0', ';',
-            'clk_internal', '<=', '0', ';',
-            'last_clk_time', '=', '$stime', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/addacc_t1ff.v.parsed.txt Deleted

@@ -1,478 +0,0 @@
-// Verilog HDL for "RSFQ.lib", "t1ff" "_functional"
-
-// Module T1 flip-flop
-module addacc_t1ff (t, wr0, out, rd1);
-
-input
-	t, wr0;
-
-output
-	out, rd1;
-reg 
-	out, rd1;
-
-parameter
-	t_separation 	=  8,
-	delay		= 20,
-	t_hold 		=  6,
-	t_setup 	= 15,
-	rd1_delay	= 17,
-
-// multichannel description of a warning file
-	warning_file=2,  
-// multichannel description of a delay file
-	delay_file = warning_file<<1;
-
-reg
-	t_internal, wr0_internal, // signals at inputs after i/o stage
-	t_state,  // internal state of T flip-flop
-	sep_clr,  // signal marking the end of the separation zone
-	hs_clr;	  // signal marking the end of the hold/setup zone
-
-
-integer
-	data_delay, 	// delay between t and t_internal
-	wr0_delay, 	// delay between rd and rd_internal
-	t_out_delay, 	// delay between t_internal and out
-	wr0_out_delay,  // delay between rd_internal and out
-	last_t_time,    // time when the last t pulse appeared
-	last_wr0_time,  // time when the last wr0 pulse appeared
-	in_hs,    // number of t pulses in hold/setup zone
-	in_sep,	 // number of pulses within an interval t_sep before 
-		 //  the last data pulse;
-	out_value, // value at the output
-	vt_hold,	// variable hold
-	vt_setup,	// variable setup
-	vdelay;		// variable delay
-
-`include "INIT"
-
-`ifdef RANDOM_DELAYS
- `include "RANDOM_GATE"
-`endif
-
-
-initial 
-	begin
-		vt_hold = t_hold;
-		vt_setup = t_setup;
-		vdelay = delay;
-
-`ifdef RANDOM_DELAYS
-		delay_dev = addacc_t1ff_variation*delay;
-		vdelay = $dist_normal(addacc_t1ff_seed, delay, delay_dev);
-		vt_hold = $dist_normal(addacc_t1ff_seed, t_hold,
-                                       addacc_t1ff_hs_dev);
-		vt_setup = t_setup + (t_hold - vt_hold);
-`endif
-
-		#1 $fdisplay(delay_file, "module=%m, nom_delay=%0d, delay=%0d", delay, vdelay);
-		#1 $fdisplay(delay_file, "module=%m, nom_hold=%0d, hold=%0d", t_hold, vt_hold);
-		#1 $fdisplay(delay_file, "module=%m, nom_setup=%0d, setup=%0d", t_setup, vt_setup);
-
-
-// define delays between inputs & outputs and the corresponding
-//  internal auxiliary registers
-	  	if(vt_hold<0)
-		  begin
-	    	  	data_delay = -vt_hold;
-	    		wr0_delay  = 0;
-		  end
-	  	else
-		  begin
-	   	  	data_delay = 0;
-	    		wr0_delay  = vt_hold;
-		  end
-		t_out_delay  = vdelay-data_delay;
-		wr0_out_delay = rd1_delay-wr0_delay;
-
-// clear internal registers and the output signal
-		t_internal = 0;
-		wr0_internal = 0;
-		t_state = 0;
-		in_hs = 0;
-		in_sep = 0;
-		sep_clr = 0;
-		hs_clr = 0;
-		out = 0;
-		rd1 = 0;
-	end
-
-
-always @(posedge t) 	// Execute at positive edge of t
-	  t_internal <= #(data_delay) t;
-
-always @(posedge wr0) 	// Execute at positive edge of t
-	  wr0_internal <= #(wr0_delay) wr0;
-
-
-always @(posedge t_internal)
-	begin
-	  if (in_sep>0)
-	    begin
-	      t_state = 1'bx;
-
-	    // generating a warning
-	      $fwrite(warning_file, 
-	       "Violation of separation time in module %m.\n");
-	      $fwrite(warning_file,
-	       "Input T pulses at %0d and at %0d.\n", last_t_time, 
-	       $stime-data_delay);
-	    end
-	  last_t_time <= $stime-data_delay;
-
-	  out <= #t_out_delay t_state;
-	  out <= #(t_out_delay+2) 0;
-
-	  t_state = t_state ^ 1;
-	  if (t_internal === 1)
-	    begin
-	      in_sep = in_sep + 1;
-	      sep_clr <= #(t_separation) 1;
-	    end
-	  else
-	    t_state = 1'bx;
-
-// setting the state of the t input
-	  if (t_internal === 1)
-	    begin
-	      in_hs = in_hs+1;
-	      hs_clr <= #(vt_hold+vt_setup) 1;
-	    end
-	  else
-	    t_state = 1'bx;
-
-	  t_internal <= 0;
-	end
-
-
-always @(posedge hs_clr)
-	begin
-		if ($stime - last_wr0_time < vt_hold+vt_setup)
-		  begin
-			t_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input T pulse at %0d,",
-			 $stime-data_delay-vt_hold-vt_setup);
-			$fwrite(warning_file,
-			"\tInput WRITE0 pulse at %0d.\n",
-			 last_wr0_time-wr0_delay);
-		  end
-
-		in_hs = in_hs-1;
-		hs_clr <= 0;
-	end
-
-always @(posedge sep_clr)
-	begin
-	  	in_sep = in_sep - 1;
-		sep_clr <= 0;
-	end
-
-
-always @(posedge wr0_internal)	
-	begin
-// computing the output
-		if ((wr0_internal === 1'bx) || (in_hs>0))
-		  out_value = 1'bx;
-		else
-		  out_value = t_state;
-
-// transfering the result to the output
-		rd1 <= #(wr0_out_delay) out_value;
-		rd1 <= #(wr0_out_delay+2) 0;
-
-// clearing the internal state of T1 flip-flop
-		if(in_hs == 0)
-		  t_state  = 0;
-		else
-		  t_state = 1'bx;
-
-		wr0_internal <= 0;
-		last_wr0_time = $stime;
-	end
-
-
-endmodule
-
-
-   'module',
-      'addacc_t1ff',
-      '(',
-      't', 'wr0', 'out', 'rd1',
-      ')',
-      ';',
-     'input', 't', 'wr0', ';',
-      'output', 'out', 'rd1', ';',
-      'reg', 'out', 'rd1', ';',
-       'parameter',
-        't_separation', '=', '8',
-        'delay', '=', '20',
-        't_hold', '=', '6',
-        't_setup', '=', '15',
-        'rd1_delay', '=', '17',
-        'warning_file', '=', '2',
-        'delay_file', '=', 'warning_file', '<<', '1',
-        ';',
-       'reg',
-        't_internal',
-        'wr0_internal',
-        't_state',
-        'sep_clr',
-        'hs_clr',
-        ';',
-       'integer',
-        'data_delay',
-        'wr0_delay',
-        't_out_delay',
-        'wr0_out_delay',
-        'last_t_time',
-        'last_wr0_time',
-        'in_hs',
-        'in_sep',
-        'out_value',
-        'vt_hold',
-        'vt_setup',
-        'vdelay',
-        ';',
-       'initial',
-         'begin',
-           'vt_hold', '=', 't_hold', ';',
-            'vt_setup', '=', 't_setup', ';',
-            'vdelay', '=', 'delay', ';',
-             'delay_dev', '=', 'addacc_t1ff_variation', '*', 'delay',
-              ';',
-              'vdelay',
-                '=',
-                 '$dist_normal',
-                  '(',
-                  'addacc_t1ff_seed',
-                  'delay',
-                  'delay_dev',
-                  ')',
-              ';',
-              'vt_hold',
-                '=',
-                 '$dist_normal',
-                  '(',
-                  'addacc_t1ff_seed',
-                  't_hold',
-                  'addacc_t1ff_hs_dev',
-                  ')',
-              ';',
-              'vt_setup',
-                '=',
-                't_setup',
-                '+',
-                '(',
-                't_hold', '-', 'vt_hold',
-                ')',
-              ';',
-             '#', '1',
-               '$fdisplay',
-                '(',
-                'delay_file',
-                '"module=%m, nom_delay=%0d, delay=%0d"',
-                'delay',
-                'vdelay',
-                ')',
-                ';',
-             '#', '1',
-               '$fdisplay',
-                '(',
-                'delay_file',
-                '"module=%m, nom_hold=%0d, hold=%0d"',
-                't_hold',
-                'vt_hold',
-                ')',
-                ';',
-             '#', '1',
-               '$fdisplay',
-                '(',
-                'delay_file',
-                '"module=%m, nom_setup=%0d, setup=%0d"',
-                't_setup',
-                'vt_setup',
-                ')',
-                ';',
-             'if',
-              '(', 'vt_hold', '<', '0', ')',
-               'begin',
-                 'data_delay', '=', '-', 'vt_hold', ';',
-                  'wr0_delay', '=', '0', ';',
-                'end',
-              'else',
-               'begin',
-                 'data_delay', '=', '0', ';',
-                  'wr0_delay', '=', 'vt_hold', ';',
-                'end',
-            't_out_delay', '=', 'vdelay', '-', 'data_delay', ';',
-            'wr0_out_delay', '=', 'rd1_delay', '-', 'wr0_delay', ';',
-            't_internal', '=', '0', ';',
-            'wr0_internal', '=', '0', ';',
-            't_state', '=', '0', ';',
-            'in_hs', '=', '0', ';',
-            'in_sep', '=', '0', ';',
-            'sep_clr', '=', '0', ';',
-            'hs_clr', '=', '0', ';',
-            'out', '=', '0', ';',
-            'rd1', '=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 't', ')',
-         't_internal', '<=', '#', '(', 'data_delay', ')', 't',
-          ';',
-       'always',
-        '@', '(', 'posedge', 'wr0', ')',
-         'wr0_internal', '<=', '#', '(', 'wr0_delay', ')', 'wr0',
-          ';',
-       'always',
-        '@', '(', 'posedge', 't_internal', ')',
-         'begin',
-            'if',
-              '(', 'in_sep', '>', '0', ')',
-               'begin',
-                 't_state', '=', "1 'b x", ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Violation of separation time in module %m.\\n"',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Input T pulses at %0d and at %0d.\\n"',
-                    'last_t_time',
-                    '$stime',
-                    '-',
-                    'data_delay',
-                    ')',
-                    ';',
-                'end',
-            'last_t_time', '<=', '$stime', '-', 'data_delay', ';',
-            'out', '<=', '#', 't_out_delay', 't_state', ';',
-              'out',
-                '<=',
-                '#', '(', 't_out_delay', '+', '2', ')',
-                '0',
-              ';',
-            't_state', '=', 't_state', '^', '1', ';',
-             'if',
-              '(', 't_internal', '===', '1', ')',
-               'begin',
-                 'in_sep', '=', 'in_sep', '+', '1', ';',
-                    'sep_clr',
-                      '<=',
-                      '#', '(', 't_separation', ')',
-                      '1',
-                    ';',
-                'end',
-              'else',
-              't_state', '=', "1 'b x", ';',
-             'if',
-              '(', 't_internal', '===', '1', ')',
-               'begin',
-                 'in_hs', '=', 'in_hs', '+', '1', ';',
-                    'hs_clr',
-                      '<=',
-                      '#', '(', 'vt_hold', '+', 'vt_setup', ')',
-                      '1',
-                    ';',
-                'end',
-              'else',
-              't_state', '=', "1 'b x", ';',
-            't_internal', '<=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'hs_clr', ')',
-         'begin',
-            'if',
-               '(',
-                '$stime',
-                '-',
-                'last_wr0_time',
-                '<',
-                'vt_hold',
-                '+',
-                'vt_setup',
-                ')',
-               'begin',
-                 't_state', '=', "1 'b x", ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Violation of hold/setup time in module %m.\\n"',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Input T pulse at %0d,"',
-                    '$stime',
-                    '-',
-                    'data_delay',
-                    '-',
-                    'vt_hold',
-                    '-',
-                    'vt_setup',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"\\tInput WRITE0 pulse at %0d.\\n"',
-                    'last_wr0_time',
-                    '-',
-                    'wr0_delay',
-                    ')',
-                    ';',
-                'end',
-            'in_hs', '=', 'in_hs', '-', '1', ';',
-            'hs_clr', '<=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'sep_clr', ')',
-         'begin',
-           'in_sep', '=', 'in_sep', '-', '1', ';',
-            'sep_clr', '<=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'wr0_internal', ')',
-         'begin',
-            'if',
-               '(',
-                '(',
-                'wr0_internal', '===', "1 'b x",
-                ')',
-                '||',
-                '(',
-                'in_hs', '>', '0',
-                ')',
-                ')',
-              'out_value', '=', "1 'b x", ';',
-              'else',
-              'out_value', '=', 't_state', ';',
-              'rd1',
-                '<=',
-                '#', '(', 'wr0_out_delay', ')',
-                'out_value',
-              ';',
-              'rd1',
-                '<=',
-                '#', '(', 'wr0_out_delay', '+', '2', ')',
-                '0',
-              ';',
-             'if',
-              '(', 'in_hs', '==', '0', ')',
-              't_state', '=', '0', ';',
-              'else',
-              't_state', '=', "1 'b x", ';',
-            'wr0_internal', '<=', '0', ';',
-            'last_wr0_time', '=', '$stime', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/and.v.parsed.txt Deleted

@@ -1,358 +0,0 @@
-// Verilog HDL for "gates.lib", "and_gate" "_functional"
-// Module AND gate
-module and_gate (a, b, clk, out);
-
-input
-	a, b, clk;
-
-output
-	out;
-reg 
-	out;
-
-parameter
-	t_hold	= 12,
-	t_setup	=  1,
-	delay	= 25,
-
-	warning_file=3;  // multichannel description of a warning file
-
-reg
-	a_internal, b_internal, clk_internal,
-	a_state, b_state,          // internal state at inputs a and b
-	a_set, b_set;		   // signals determining the moment when
-				   // the state of the a,b inputs changes to "1"
-integer
-	data_delay, 	// delay between a (b) and a_internal (b_internal)
-	clk_delay, 	// delay between clk and clk_internal
-	out_delay, 	// delay between clk_internal and out
-	out_value,	// output value in a given clock cycle
-	last_clk_time;	// time when the last clock pulse appeared
-
-initial 
-	begin
-// define delays between inputs & outputs and the corresponding
-//  internal auxiliary registers
-	  	if(t_hold<0)
-		  begin
-	    		data_delay = -t_hold;
-	    	  	clk_delay = 0;
-		  	out_delay = delay;
-		  end
-	  	else
-		  begin
-	    	  	data_delay = 0;
-	    	  	clk_delay = t_hold;
-		  	out_delay=delay-t_hold;
-		  end
-
-// clear internal registers and the output signal
-		a_internal = 0;
-		b_internal = 0;
-		clk_internal = 0;
-		last_clk_time = 0;
-		a_state = 0;
-		b_state = 0;
-		a_set = 0;
-		b_set = 0;
-		out = 0;
-	end
-
-always @(posedge a) 	// Execute at positive edge of a
-	  a_internal <= #(data_delay) a;
-
-always @(posedge b) 	// Execute at positive edge of b
-	  b_internal <= #(data_delay) b;
-
-always @(posedge clk) 	// Execute at positive edge of clk
-	  clk_internal <= #(clk_delay) clk;
-
-always @(posedge a_internal)
-	begin
-// setting an internal state at the input a
-                a_state <= a_state | 1'bx;
-		if (a_internal === 1)
-		  a_set <= #(t_hold+t_setup) 1;
-
-		a_internal <= 0;
-	end
-
-always @(posedge b_internal)
-	begin
-// setting an internal state at the input a
-                b_state <= b_state | 1'bx;
-		if (b_internal === 1)
-		  b_set <= #(t_hold+t_setup) 1;
-
-		b_internal <= 0;
-	end
-
-always @(posedge a_set)
-	begin
-		if ($stime - last_clk_time >= t_hold+t_setup)
-			a_state = 1;
-		else
-		  begin
-			a_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input A pulse at %0d,",
-			 $stime-data_delay-t_hold-t_setup);
-			$fwrite(warning_file,
-			"\tClock pulse at %0d.\n", last_clk_time-clk_delay);
-		  end
-
-		a_set <= 0;
-	end
-
-always @(posedge b_set)
-	begin
-		if ($stime - last_clk_time >= t_hold+t_setup)
-			b_state = 1;
-		else
-		  begin
-			b_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input B pulse at %0d,",
-			 $stime-data_delay-t_hold-t_setup);
-			$fwrite(warning_file,
-			"\tClock pulse at %0d.\n", last_clk_time-clk_delay);
-		  end
-
-		b_set <= 0;
-	end
-
-
-always @(posedge clk_internal)	
-	begin
-// computing the output
-		if (clk_internal === 1'bx)
-		  out_value = 1'bx;
-		else
-		  out_value = a_state & b_state;
-
-// transfering the result to the output
-		out <= #(out_delay) out_value;
-		out <= #(out_delay+2) 0;
-
-// clearing the internal state of A and B inputs
-		a_state  <= 0;
-		b_state  <= 0;
-
-		clk_internal <= 0;
-		last_clk_time = $stime;
-	end
-
-endmodule
-
-
-  'module', 'and_gate', '(', 'a', 'b', 'clk', 'out', ')', ';',
-     'input', 'a', 'b', 'clk', ';',
-      'output', 'out', ';',
-      'reg', 'out', ';',
-       'parameter',
-        't_hold', '=', '12',
-        't_setup', '=', '1',
-        'delay', '=', '25',
-        'warning_file', '=', '3',
-        ';',
-       'reg',
-        'a_internal',
-        'b_internal',
-        'clk_internal',
-        'a_state',
-        'b_state',
-        'a_set',
-        'b_set',
-        ';',
-       'integer',
-        'data_delay',
-        'clk_delay',
-        'out_delay',
-        'out_value',
-        'last_clk_time',
-        ';',
-       'initial',
-         'begin',
-            'if',
-              '(', 't_hold', '<', '0', ')',
-               'begin',
-                 'data_delay', '=', '-', 't_hold', ';',
-                  'clk_delay', '=', '0', ';',
-                  'out_delay', '=', 'delay', ';',
-                'end',
-              'else',
-               'begin',
-                 'data_delay', '=', '0', ';',
-                  'clk_delay', '=', 't_hold', ';',
-                  'out_delay', '=', 'delay', '-', 't_hold', ';',
-                'end',
-            'a_internal', '=', '0', ';',
-            'b_internal', '=', '0', ';',
-            'clk_internal', '=', '0', ';',
-            'last_clk_time', '=', '0', ';',
-            'a_state', '=', '0', ';',
-            'b_state', '=', '0', ';',
-            'a_set', '=', '0', ';',
-            'b_set', '=', '0', ';',
-            'out', '=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'a', ')',
-         'a_internal', '<=', '#', '(', 'data_delay', ')', 'a',
-          ';',
-       'always',
-        '@', '(', 'posedge', 'b', ')',
-         'b_internal', '<=', '#', '(', 'data_delay', ')', 'b',
-          ';',
-       'always',
-        '@', '(', 'posedge', 'clk', ')',
-         'clk_internal', '<=', '#', '(', 'clk_delay', ')', 'clk',
-          ';',
-       'always',
-        '@', '(', 'posedge', 'a_internal', ')',
-         'begin',
-           'a_state', '<=', 'a_state', '|', "1 'b x", ';',
-             'if',
-              '(', 'a_internal', '===', '1', ')',
-                'a_set',
-                  '<=',
-                  '#', '(', 't_hold', '+', 't_setup', ')',
-                  '1',
-                ';',
-            'a_internal', '<=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'b_internal', ')',
-         'begin',
-           'b_state', '<=', 'b_state', '|', "1 'b x", ';',
-             'if',
-              '(', 'b_internal', '===', '1', ')',
-                'b_set',
-                  '<=',
-                  '#', '(', 't_hold', '+', 't_setup', ')',
-                  '1',
-                ';',
-            'b_internal', '<=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'a_set', ')',
-         'begin',
-            'if',
-               '(',
-                '$stime',
-                '-',
-                'last_clk_time',
-                '>=',
-                't_hold',
-                '+',
-                't_setup',
-                ')',
-              'a_state', '=', '1', ';',
-              'else',
-               'begin',
-                 'a_state', '=', "1 'b x", ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Violation of hold/setup time in module %m.\\n"',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Input A pulse at %0d,"',
-                    '$stime',
-                    '-',
-                    'data_delay',
-                    '-',
-                    't_hold',
-                    '-',
-                    't_setup',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"\\tClock pulse at %0d.\\n"',
-                    'last_clk_time',
-                    '-',
-                    'clk_delay',
-                    ')',
-                    ';',
-                'end',
-            'a_set', '<=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'b_set', ')',
-         'begin',
-            'if',
-               '(',
-                '$stime',
-                '-',
-                'last_clk_time',
-                '>=',
-                't_hold',
-                '+',
-                't_setup',
-                ')',
-              'b_state', '=', '1', ';',
-              'else',
-               'begin',
-                 'b_state', '=', "1 'b x", ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Violation of hold/setup time in module %m.\\n"',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Input B pulse at %0d,"',
-                    '$stime',
-                    '-',
-                    'data_delay',
-                    '-',
-                    't_hold',
-                    '-',
-                    't_setup',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"\\tClock pulse at %0d.\\n"',
-                    'last_clk_time',
-                    '-',
-                    'clk_delay',
-                    ')',
-                    ';',
-                'end',
-            'b_set', '<=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'clk_internal', ')',
-         'begin',
-            'if',
-              '(', 'clk_internal', '===', "1 'b x", ')',
-              'out_value', '=', "1 'b x", ';',
-              'else',
-              'out_value', '=', 'a_state', '&', 'b_state', ';',
-             'out', '<=', '#', '(', 'out_delay', ')', 'out_value',
-              ';',
-             'out', '<=', '#', '(', 'out_delay', '+', '2', ')', '0',
-              ';',
-            'a_state', '<=', '0', ';',
-            'b_state', '<=', '0', ';',
-            'clk_internal', '<=', '0', ';',
-            'last_clk_time', '=', '$stime', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/and_gate.v.parsed.txt Deleted

@@ -1,451 +0,0 @@
-// Verilog HDL for "RSFQ.lib", "and_gate" "_functional"
-
-// Module AND gate
-module and_gate (a, b, clk, out);
-
-input
-	a, b, clk;
-
-output
-	out;
-reg 
-	out;
-
-parameter
-	t_hold	= 12,
-	t_setup	=  1,
-	delay	= 25,
-
-// multichannel description of a warning file
-	warning_file=2,  
-// multichannel description of a delay file
-	delay_file = warning_file<<1;
-
-reg
-	a_internal, b_internal, clk_internal,
-	a_state, b_state,          // internal state at inputs a and b
-	a_set, b_set;		   // signals determining the moment when
-				   // the state of the a,b inputs changes to "1"
-integer
-	data_delay, 	// delay between a (b) and a_internal (b_internal)
-	clk_delay, 	// delay between clk and clk_internal
-	out_delay, 	// delay between clk_internal and out
-	out_value,	// output value in a given clock cycle
-	last_clk_time,	// time when the last clock pulse appeared
-	vt_hold,	// variable hold
-	vt_setup,	// variable setup
-	vdelay;		// variable delay
-
-
-`include "INIT"
-
-`ifdef RANDOM_DELAYS
- `include "RANDOM_GATE"
-`endif
-
-
-initial 
-	begin
-		vt_hold = t_hold;
-		vt_setup = t_setup;
-		vdelay = delay;
-
-`ifdef RANDOM_DELAYS
-		delay_dev = and_gate_variation*delay;
-		vdelay = $dist_normal(and_gate_seed, delay, delay_dev);
-		vt_hold = $dist_normal(and_gate_seed, t_hold, and_hs_dev);
-		vt_setup = t_setup + (t_hold - vt_hold);
-`endif
-
-		#0 $fdisplay(delay_file, "module=%m, nom_delay=%0d, delay=%0d", delay, vdelay);
-		#0 $fdisplay(delay_file, "module=%m, nom_hold=%0d, hold=%0d", t_hold, vt_hold);
-		#0 $fdisplay(delay_file, "module=%m, nom_setup=%0d, setup=%0d", t_setup, vt_setup);
-
-
-// define delays between inputs & outputs and the corresponding
-//  internal auxiliary registers
-	  	if(vt_hold<0)
-		  begin
-	    		data_delay = -vt_hold;
-	    	  	clk_delay = 0;
-		  	out_delay = vdelay;
-		  end
-	  	else
-		  begin
-	    	  	data_delay = 0;
-	    	  	clk_delay = vt_hold;
-		  	out_delay=vdelay-vt_hold;
-		  end
-
-// clear internal registers and the output signal
-		a_internal = 0;
-		b_internal = 0;
-		clk_internal = 0;
-		last_clk_time = 0;
-		a_state = 0;
-		b_state = 0;
-		a_set = 0;
-		b_set = 0;
-		out = 0;
-	end
-
-always @(posedge a) 	// Execute at positive edge of a
-	  a_internal <= #(data_delay) a;
-
-always @(posedge b) 	// Execute at positive edge of b
-	  b_internal <= #(data_delay) b;
-
-always @(posedge clk) 	// Execute at positive edge of clk
-	  clk_internal <= #(clk_delay) clk;
-
-always @(posedge a_internal)
-	begin
-// setting an internal state at the input a
-                a_state <= a_state | 1'bx;
-		if (a_internal === 1)
-		  a_set <= #(vt_hold+vt_setup) 1;
-
-		a_internal <= 0;
-	end
-
-always @(posedge b_internal)
-	begin
-// setting an internal state at the input a
-                b_state <= b_state | 1'bx;
-		if (b_internal === 1)
-		  b_set <= #(vt_hold+vt_setup) 1;
-
-		b_internal <= 0;
-	end
-
-always @(posedge a_set)
-	begin
-		if ($stime - last_clk_time >= vt_hold+vt_setup)
-			a_state = 1;
-		else
-		  begin
-			a_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input A pulse at %0d,",
-			 $stime-data_delay-vt_hold-vt_setup);
-			$fwrite(warning_file,
-			"\tClock pulse at %0d.\n", last_clk_time-clk_delay);
-		  end
-
-		a_set <= 0;
-	end
-
-always @(posedge b_set)
-	begin
-		if ($stime - last_clk_time >= vt_hold+vt_setup)
-			b_state = 1;
-		else
-		  begin
-			b_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input B pulse at %0d,",
-			 $stime-data_delay-vt_hold-vt_setup);
-			$fwrite(warning_file,
-			"\tClock pulse at %0d.\n", last_clk_time-clk_delay);
-		  end
-
-		b_set <= 0;
-	end
-
-
-always @(posedge clk_internal)	
-	begin
-// computing the output
-		if (clk_internal === 1'bx)
-		  out_value = 1'bx;
-		else
-		  out_value = a_state & b_state;
-
-// transfering the result to the output
-		out <= #(out_delay) out_value;
-		out <= #(out_delay+2) 0;
-
-// clearing the internal state of A and B inputs
-		a_state  <= 0;
-		b_state  <= 0;
-
-		clk_internal <= 0;
-		last_clk_time = $stime;
-
-	end
-
-endmodule
-
-
-  'module', 'and_gate', '(', 'a', 'b', 'clk', 'out', ')', ';',
-     'input', 'a', 'b', 'clk', ';',
-      'output', 'out', ';',
-      'reg', 'out', ';',
-       'parameter',
-        't_hold', '=', '12',
-        't_setup', '=', '1',
-        'delay', '=', '25',
-        'warning_file', '=', '2',
-        'delay_file', '=', 'warning_file', '<<', '1',
-        ';',
-       'reg',
-        'a_internal',
-        'b_internal',
-        'clk_internal',
-        'a_state',
-        'b_state',
-        'a_set',
-        'b_set',
-        ';',
-       'integer',
-        'data_delay',
-        'clk_delay',
-        'out_delay',
-        'out_value',
-        'last_clk_time',
-        'vt_hold',
-        'vt_setup',
-        'vdelay',
-        ';',
-       'initial',
-         'begin',
-           'vt_hold', '=', 't_hold', ';',
-            'vt_setup', '=', 't_setup', ';',
-            'vdelay', '=', 'delay', ';',
-            'delay_dev', '=', 'and_gate_variation', '*', 'delay', ';',
-              'vdelay',
-                '=',
-                 '$dist_normal',
-                  '(',
-                  'and_gate_seed',
-                  'delay',
-                  'delay_dev',
-                  ')',
-              ';',
-              'vt_hold',
-                '=',
-                 '$dist_normal',
-                  '(',
-                  'and_gate_seed',
-                  't_hold',
-                  'and_hs_dev',
-                  ')',
-              ';',
-              'vt_setup',
-                '=',
-                't_setup',
-                '+',
-                '(',
-                't_hold', '-', 'vt_hold',
-                ')',
-              ';',
-             '#', '0',
-               '$fdisplay',
-                '(',
-                'delay_file',
-                '"module=%m, nom_delay=%0d, delay=%0d"',
-                'delay',
-                'vdelay',
-                ')',
-                ';',
-             '#', '0',
-               '$fdisplay',
-                '(',
-                'delay_file',
-                '"module=%m, nom_hold=%0d, hold=%0d"',
-                't_hold',
-                'vt_hold',
-                ')',
-                ';',
-             '#', '0',
-               '$fdisplay',
-                '(',
-                'delay_file',
-                '"module=%m, nom_setup=%0d, setup=%0d"',
-                't_setup',
-                'vt_setup',
-                ')',
-                ';',
-             'if',
-              '(', 'vt_hold', '<', '0', ')',
-               'begin',
-                 'data_delay', '=', '-', 'vt_hold', ';',
-                  'clk_delay', '=', '0', ';',
-                  'out_delay', '=', 'vdelay', ';',
-                'end',
-              'else',
-               'begin',
-                 'data_delay', '=', '0', ';',
-                  'clk_delay', '=', 'vt_hold', ';',
-                  'out_delay', '=', 'vdelay', '-', 'vt_hold', ';',
-                'end',
-            'a_internal', '=', '0', ';',
-            'b_internal', '=', '0', ';',
-            'clk_internal', '=', '0', ';',
-            'last_clk_time', '=', '0', ';',
-            'a_state', '=', '0', ';',
-            'b_state', '=', '0', ';',
-            'a_set', '=', '0', ';',
-            'b_set', '=', '0', ';',
-            'out', '=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'a', ')',
-         'a_internal', '<=', '#', '(', 'data_delay', ')', 'a',
-          ';',
-       'always',
-        '@', '(', 'posedge', 'b', ')',
-         'b_internal', '<=', '#', '(', 'data_delay', ')', 'b',
-          ';',
-       'always',
-        '@', '(', 'posedge', 'clk', ')',
-         'clk_internal', '<=', '#', '(', 'clk_delay', ')', 'clk',
-          ';',
-       'always',
-        '@', '(', 'posedge', 'a_internal', ')',
-         'begin',
-           'a_state', '<=', 'a_state', '|', "1 'b x", ';',
-             'if',
-              '(', 'a_internal', '===', '1', ')',
-                'a_set',
-                  '<=',
-                  '#', '(', 'vt_hold', '+', 'vt_setup', ')',
-                  '1',
-                ';',
-            'a_internal', '<=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'b_internal', ')',
-         'begin',
-           'b_state', '<=', 'b_state', '|', "1 'b x", ';',
-             'if',
-              '(', 'b_internal', '===', '1', ')',
-                'b_set',
-                  '<=',
-                  '#', '(', 'vt_hold', '+', 'vt_setup', ')',
-                  '1',
-                ';',
-            'b_internal', '<=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'a_set', ')',
-         'begin',
-            'if',
-               '(',
-                '$stime',
-                '-',
-                'last_clk_time',
-                '>=',
-                'vt_hold',
-                '+',
-                'vt_setup',
-                ')',
-              'a_state', '=', '1', ';',
-              'else',
-               'begin',
-                 'a_state', '=', "1 'b x", ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Violation of hold/setup time in module %m.\\n"',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Input A pulse at %0d,"',
-                    '$stime',
-                    '-',
-                    'data_delay',
-                    '-',
-                    'vt_hold',
-                    '-',
-                    'vt_setup',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"\\tClock pulse at %0d.\\n"',
-                    'last_clk_time',
-                    '-',
-                    'clk_delay',
-                    ')',
-                    ';',
-                'end',
-            'a_set', '<=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'b_set', ')',
-         'begin',
-            'if',
-               '(',
-                '$stime',
-                '-',
-                'last_clk_time',
-                '>=',
-                'vt_hold',
-                '+',
-                'vt_setup',
-                ')',
-              'b_state', '=', '1', ';',
-              'else',
-               'begin',
-                 'b_state', '=', "1 'b x", ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Violation of hold/setup time in module %m.\\n"',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Input B pulse at %0d,"',
-                    '$stime',
-                    '-',
-                    'data_delay',
-                    '-',
-                    'vt_hold',
-                    '-',
-                    'vt_setup',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"\\tClock pulse at %0d.\\n"',
-                    'last_clk_time',
-                    '-',
-                    'clk_delay',
-                    ')',
-                    ';',
-                'end',
-            'b_set', '<=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'clk_internal', ')',
-         'begin',
-            'if',
-              '(', 'clk_internal', '===', "1 'b x", ')',
-              'out_value', '=', "1 'b x", ';',
-              'else',
-              'out_value', '=', 'a_state', '&', 'b_state', ';',
-             'out', '<=', '#', '(', 'out_delay', ')', 'out_value',
-              ';',
-             'out', '<=', '#', '(', 'out_delay', '+', '2', ')', '0',
-              ';',
-            'a_state', '<=', '0', ';',
-            'b_state', '<=', '0', ';',
-            'clk_internal', '<=', '0', ';',
-            'last_clk_time', '=', '$stime', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/conf.v.parsed.txt Deleted

@@ -1,265 +0,0 @@
-// Verilog HDL for "gates.lib", "conf_buff" "_functional"
-// Module CONFLUENCE BUFFER
-module conf_buff (in1, in2, out);
-
-input
-	in1, in2;
-
-output
-	out;
-reg 
-	out;
-
-parameter
-	t_separation = 10,
-	delay=15,
-
-	warning_file=3;  // multichannel description of a warning file
-
-reg
-	sep_clr; // signal marking the end of the min separation zone
-		 //  for the last pulse
-
-integer
-	last_in_time,    // time when the last t pulse appeared
-	in_sep;	 // number of pulses within an interval t_sep before 
-		 //  the last data pulse;
-
-initial 
-	begin
-// clear internal registers and the output signal
-		last_in_time = 0;
-		in_sep = 0;
-		sep_clr = 0;
-		out = 0;
-	end
-
-always @(posedge in1)
-	begin
-		out <= #delay ((in_sep > 0) || (in2 == 1)) ? 1'bx : 1;
-		out <= #(delay+2) 0;
-		
-		if((in_sep>0) || (in2 == 1))
-	          begin
-	        // generating a warning
-	            $fwrite(warning_file, 
-	            "Violation of separation time in module %m.\n");
-	            $fwrite(warning_file,
-	            "Input pulses at ");
-		    if(in_sep>0)
-			$fwrite(warning_file,
-			"%0d and at %0d.\n", last_in_time, $stime);
-		    else
-			$fwrite(warning_file,
-			"%0d and at %0d.\n", $stime, $stime);
-	    	  end
-	  	last_in_time <= $stime;
-
-		in_sep <= in_sep + 1;
-		sep_clr <= #(t_separation-1) 1;
-	end
-
-always @(posedge in2)
-	begin
-		out <= #delay ((in_sep > 0) || (in1 == 1)) ? 1'bx : 1;
-		out <= #(delay+2) 0;
-
-		if((in_sep>0) || (in1 == 1))
-	          begin
-	        // generating a warning
-	            $fwrite(warning_file, 
-	            "Violation of separation time in module %m.\n");
-	            $fwrite(warning_file,
-	            "Input pulses at ");
-		    if(in_sep>0)
-			$fwrite(warning_file,
-			"%0d and at %0d.\n", last_in_time, $stime);
-		    else
-			$fwrite(warning_file,
-			"%0d and at %0d.\n", $stime, $stime);
-	    	  end
-	  	last_in_time <= $stime;
-
-		in_sep <= in_sep + 1;
-		sep_clr <= #(t_separation-1) 1;
-	end
-
-always @(posedge sep_clr)
-	begin
-	  	in_sep <= in_sep - 1;
-		sep_clr <= 0;
-	end
-
-
-endmodule
-
-
-  'module', 'conf_buff', '(', 'in1', 'in2', 'out', ')', ';',
-     'input', 'in1', 'in2', ';',
-      'output', 'out', ';',
-      'reg', 'out', ';',
-       'parameter',
-        't_separation', '=', '10',
-        'delay', '=', '15',
-        'warning_file', '=', '3',
-        ';',
-      'reg', 'sep_clr', ';',
-      'integer', 'last_in_time', 'in_sep', ';',
-       'initial',
-         'begin',
-           'last_in_time', '=', '0', ';',
-            'in_sep', '=', '0', ';',
-            'sep_clr', '=', '0', ';',
-            'out', '=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'in1', ')',
-         'begin',
-             'out',
-                '<=',
-                '#', 'delay',
-                '(',
-                 '(',
-                  'in_sep', '>', '0',
-                  ')',
-                  '||',
-                  '(',
-                  'in2', '==', '1',
-                  ')',
-                ')',
-                '?',
-                "1 'b x",
-                ':',
-                '1',
-              ';',
-            'out', '<=', '#', '(', 'delay', '+', '2', ')', '0', ';',
-             'if',
-               '(',
-                '(',
-                'in_sep', '>', '0',
-                ')',
-                '||',
-                '(',
-                'in2', '==', '1',
-                ')',
-                ')',
-               'begin',
-                  '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Violation of separation time in module %m.\\n"',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Input pulses at "',
-                    ')',
-                    ';',
-                   'if',
-                    '(', 'in_sep', '>', '0', ')',
-                     '$fwrite',
-                      '(',
-                      'warning_file',
-                      '"%0d and at %0d.\\n"',
-                      'last_in_time',
-                      '$stime',
-                      ')',
-                      ';',
-                    'else',
-                     '$fwrite',
-                      '(',
-                      'warning_file',
-                      '"%0d and at %0d.\\n"',
-                      '$stime',
-                      '$stime',
-                      ')',
-                      ';',
-                'end',
-            'last_in_time', '<=', '$stime', ';',
-            'in_sep', '<=', 'in_sep', '+', '1', ';',
-              'sep_clr',
-                '<=',
-                '#', '(', 't_separation', '-', '1', ')',
-                '1',
-              ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'in2', ')',
-         'begin',
-             'out',
-                '<=',
-                '#', 'delay',
-                '(',
-                 '(',
-                  'in_sep', '>', '0',
-                  ')',
-                  '||',
-                  '(',
-                  'in1', '==', '1',
-                  ')',
-                ')',
-                '?',
-                "1 'b x",
-                ':',
-                '1',
-              ';',
-            'out', '<=', '#', '(', 'delay', '+', '2', ')', '0', ';',
-             'if',
-               '(',
-                '(',
-                'in_sep', '>', '0',
-                ')',
-                '||',
-                '(',
-                'in1', '==', '1',
-                ')',
-                ')',
-               'begin',
-                  '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Violation of separation time in module %m.\\n"',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Input pulses at "',
-                    ')',
-                    ';',
-                   'if',
-                    '(', 'in_sep', '>', '0', ')',
-                     '$fwrite',
-                      '(',
-                      'warning_file',
-                      '"%0d and at %0d.\\n"',
-                      'last_in_time',
-                      '$stime',
-                      ')',
-                      ';',
-                    'else',
-                     '$fwrite',
-                      '(',
-                      'warning_file',
-                      '"%0d and at %0d.\\n"',
-                      '$stime',
-                      '$stime',
-                      ')',
-                      ';',
-                'end',
-            'last_in_time', '<=', '$stime', ';',
-            'in_sep', '<=', 'in_sep', '+', '1', ';',
-              'sep_clr',
-                '<=',
-                '#', '(', 't_separation', '-', '1', ')',
-                '1',
-              ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'sep_clr', ')',
-         'begin',
-           'in_sep', '<=', 'in_sep', '-', '1', ';',
-            'sep_clr', '<=', '0', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/core_test.v.parsed.txt Deleted

@@ -1,259 +0,0 @@
-`timescale 100ps/10ps
-/* Core Tester */
-// Author Andrew Laffely
-// Last modified: 12 Feb 03
-
-module core_test;
-
-reg gclock, reset, hold;
-wire 2:0 in_ready, out_ready;
-wire 31:0 data_in, data_out;
-reg 31:0  temp, temp2;
-reg 32:0 data_to_core;
-wire 32:0 data_from_core; 
-wire read, write;   
-wire 1:0 in_addr, out_addr;
-reg 1:0 to_addr, from_addr;
-reg valid_next;
-wire valid_back;
-reg start, start2;
-integer count, fp, fpin;
-
-/************************** INTERCONNECT ****************************/
-in_port IN_PORT_TILE1(gclock, reset, to_addr, data_to_core, in_addr, 
-			read, data_in, valid_back, in_ready);
-out_port OUT_PORT_TILE1(gclock, reset, from_addr, data_out, out_addr, 
-			write, valid_next, data_from_core, out_ready);
-/************************** END INTERCONNECT *************************/
-
-/***********************************CORE*****************************/
-adder_core CORE_TILE1(reset, hold, in_ready, out_ready, data_in, data_out, 
-			read, write, in_addr, out_addr);
-/*********************************END CORE***************************/
-
-/********************* TEST BENCH ******************************/
-initial
-begin
-	gclock = 1'b0;
-	forever #10 gclock = ~gclock;
-end
-initial
-begin
-	count=0;
-	start=0; start2=0;
-	fp=$fopen("results.dat");  //open a file pointer	
-	fpin=$fopen("inputs.dat");  //open a file pointer
-	reset = 1'b1;
-	hold = 1'b0;
-	data_to_core32=0;
-	temp=32'h00000000;
-	temp2=32'h00000000;
-	data_to_core31:0=32'h00000000;
-	valid_next=0;
-	to_addr=2'b00;
-	from_addr=2'b00;
-	#2 reset = 1'b0;
-	#26 start=1;
-	#4000 $fclose(fp);
-	$fclose(fpin);
-	$finish;
-end
-
-always @ (posedge gclock)
-  begin
-	count=count+1;
-	//Inputs
-	to_addr0 = ~to_addr0;
-	if((!valid_back)&&(start))
-	  begin
-		#1 if (!to_addr0)
-		  begin
-			data_to_core={1'b1,temp};
-			temp=temp+1;
-			$fdisplay(fpin, "Cycle=%d: InputA=%h",count,data_to_core);
-			start2=1;	
-		  end
-		else 
-		  begin
-		    if (start2)
-		      begin
-			data_to_core={1'b1,temp2};
-			temp2=temp2+256;
-			$fdisplay(fpin, "Cycle=%d: InputB=%h",count,data_to_core);	
-		      end
-		  end
-	  end
-	//Output
-	if (from_addr==2'b00)
-		from_addr=2'b11;
-	else
-		from_addr=2'b00;
-	if (data_from_core32)
-		$fdisplay(fp, "Cycle = %d: Output = %h",count,data_from_core);
-  end
-endmodule
-
-
-  'module', 'core_test', ';',
-     'reg', 'gclock', 'reset', 'hold', ';',
-      'wire', '', '2', ':', '0', '', 'in_ready', 'out_ready', ';',
-      'wire', '', '31', ':', '0', '', 'data_in', 'data_out', ';',
-      'reg', '', '31', ':', '0', '', 'temp', 'temp2', ';',
-      'reg', '', '32', ':', '0', '', 'data_to_core', ';',
-      'wire', '', '32', ':', '0', '', 'data_from_core', ';',
-      'wire', 'read', 'write', ';',
-      'wire', '', '1', ':', '0', '', 'in_addr', 'out_addr', ';',
-      'reg', '', '1', ':', '0', '', 'to_addr', 'from_addr', ';',
-      'reg', 'valid_next', ';',
-      'wire', 'valid_back', ';',
-      'reg', 'start', 'start2', ';',
-      'integer', 'count', 'fp', 'fpin', ';',
-       'in_port',
-         'IN_PORT_TILE1',
-           '(',
-            'gclock',
-            'reset',
-            'to_addr',
-            'data_to_core',
-            'in_addr',
-            'read',
-            'data_in',
-            'valid_back',
-            'in_ready',
-            ')',
-        ';',
-       'out_port',
-         'OUT_PORT_TILE1',
-           '(',
-            'gclock',
-            'reset',
-            'from_addr',
-            'data_out',
-            'out_addr',
-            'write',
-            'valid_next',
-            'data_from_core',
-            'out_ready',
-            ')',
-        ';',
-       'adder_core',
-         'CORE_TILE1',
-           '(',
-            'reset',
-            'hold',
-            'in_ready',
-            'out_ready',
-            'data_in',
-            'data_out',
-            'read',
-            'write',
-            'in_addr',
-            'out_addr',
-            ')',
-        ';',
-       'initial',
-         'begin',
-           'gclock', '=', "1 'b 0", ';',
-             'forever',
-              '#', '10', 'gclock', '=', '~', 'gclock', ';',
-          'end',
-       'initial',
-         'begin',
-           'count', '=', '0', ';',
-            'start', '=', '0', ';',
-            'start2', '=', '0', ';',
-            'fp', '=', '$fopen', '(', '"results.dat"', ')', ';',
-            'fpin', '=', '$fopen', '(', '"inputs.dat"', ')', ';',
-            'reset', '=', "1 'b 1", ';',
-            'hold', '=', "1 'b 0", ';',
-            'data_to_core', '', '32', '', '=', '0', ';',
-            'temp', '=', "32 'h 00000000", ';',
-            'temp2', '=', "32 'h 00000000", ';',
-             'data_to_core', '', '31', '0', '', '=', "32 'h 00000000",
-              ';',
-            'valid_next', '=', '0', ';',
-            'to_addr', '=', "2 'b 00", ';',
-            'from_addr', '=', "2 'b 00", ';',
-            '#', '2', 'reset', '=', "1 'b 0", ';',
-            '#', '26', 'start', '=', '1', ';',
-            '#', '4000', '$fclose', '(', 'fp', ')', ';',
-            '$fclose', '(', 'fpin', ')', ';',
-            '$finish', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'gclock', ')',
-         'begin',
-           'count', '=', 'count', '+', '1', ';',
-              'to_addr', '', '0', '',
-                '=',
-                '~',
-                'to_addr', '', '0', '',
-              ';',
-             'if',
-               '(',
-                '(',
-                '!', 'valid_back',
-                ')',
-                '&&',
-                '(',
-                'start',
-                ')',
-                ')',
-               'begin',
-                  '#', '1',
-                     'if',
-                      '(', '!', 'to_addr', '', '0', '', ')',
-                       'begin',
-                           'data_to_core',
-                              '=',
-                              '{', "1 'b 1", 'temp', '}',
-                            ';',
-                          'temp', '=', 'temp', '+', '1', ';',
-                           '$fdisplay',
-                            '(',
-                            'fpin',
-                            '"Cycle=%d: InputA=%h"',
-                            'count',
-                            'data_to_core',
-                            ')',
-                            ';',
-                          'start2', '=', '1', ';',
-                        'end',
-                      'else',
-                       'begin',
-                          'if',
-                            '(', 'start2', ')',
-                             'begin',
-                                 'data_to_core',
-                                    '=',
-                                    '{', "1 'b 1", 'temp2', '}',
-                                  ';',
-                                'temp2', '=', 'temp2', '+', '256', ';',
-                                 '$fdisplay',
-                                  '(',
-                                  'fpin',
-                                  '"Cycle=%d: InputB=%h"',
-                                  'count',
-                                  'data_to_core',
-                                  ')',
-                                  ';',
-                              'end',
-                        'end',
-                'end',
-             'if',
-              '(', 'from_addr', '==', "2 'b 00", ')',
-              'from_addr', '=', "2 'b 11", ';',
-              'else',
-              'from_addr', '=', "2 'b 00", ';',
-             'if',
-              '(', 'data_from_core', '', '32', '', ')',
-               '$fdisplay',
-                '(',
-                'fp',
-                '"Cycle = %d: Output = %h"',
-                'count',
-                'data_from_core',
-                ')',
-                ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/count2bit.v.parsed.txt Deleted

@@ -1,90 +0,0 @@
-module count2bit(cnt, clk, res_, en);
-    output 1:0 cnt; // the counter value
-    reg 1:0 cnt;
-    input clk, res_, en;
-    reg 1:0 next_cnt; // the next state
-    
-    parameter S0=2'b00, // the states
-    S1=2'b01,
-    S2=2'b10,
-    S3=2'b11;
-    
-    always @(posedge clk or negedge res_)
-        if (res_ == 1'b0)
-            cnt <= 2'b00;
-        else
-            cnt <= next_cnt;
-    
-    always @(en or cnt)
-        case (cnt)
-            S0: if (en == 1'b1) // full if-then-else implem.
-                    next_cnt = S1;
-                else
-                    next_cnt = S0;
-            S1: if (en == 1'b1) // the else path is not needed
-                    next_cnt = S2;
-            S2: next_cnt = (en == 1'b1) ? S3 : S2; // shorter
-            S3: next_cnt = (en) ? S0 : S3; // even shorter
-        endcase
-endmodule
-
-
-   'module',
-      'count2bit',
-      '(',
-      'cnt', 'clk', 'res_', 'en',
-      ')',
-      ';',
-     'output', '', '1', ':', '0', '', 'cnt', ';',
-      'reg', '', '1', ':', '0', '', 'cnt', ';',
-      'input', 'clk', 'res_', 'en', ';',
-      'reg', '', '1', ':', '0', '', 'next_cnt', ';',
-       'parameter',
-        'S0', '=', "2 'b 00",
-        'S1', '=', "2 'b 01",
-        'S2', '=', "2 'b 10",
-        'S3', '=', "2 'b 11",
-        ';',
-       'always',
-        '@', '(', 'posedge', 'clk', 'negedge', 'res_', ')',
-         'if',
-          '(', 'res_', '==', "1 'b 0", ')',
-          'cnt', '<=', "2 'b 00", ';',
-          'else',
-          'cnt', '<=', 'next_cnt', ';',
-       'always',
-        '@', '(', 'en', 'cnt', ')',
-         'case',
-          '(',
-          'cnt',
-          ')',
-          'S0',
-          ':',
-           'if',
-            '(', 'en', '==', "1 'b 1", ')',
-            'next_cnt', '=', 'S1', ';',
-            'else',
-            'next_cnt', '=', 'S0', ';',
-          'S1',
-          ':',
-           'if',
-            '(', 'en', '==', "1 'b 1", ')',
-            'next_cnt', '=', 'S2', ';',
-          'S2',
-          ':',
-            'next_cnt',
-              '=',
-              '(',
-              'en', '==', "1 'b 1",
-              ')',
-              '?',
-              'S3',
-              ':',
-              'S2',
-            ';',
-          'S3',
-          ':',
-           'next_cnt', '=', '(', 'en', ')', '?', 'S0', ':', 'S3',
-            ';',
-          'endcase',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/count_all_prims_test.v.parsed.txt Deleted

@@ -1,83 +0,0 @@
-/**********************************************************************
- * $count_primitives example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $count_primitives PLI application 
- * on a 1-bit adder modeled using gate primitives.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-  reg  a, b, ci, clk;
-  wire sum, co, sum2;
-
-  addbit i1 (a, b, ci, sum, co);
-  buf (sum2, sum);
-
-  initial
-    begin
-      #1 $count_primitives;
-      #1 $finish;
-    end
-endmodule
-
-/*** A gate level 1 bit adder model ***/
-`timescale 1ns / 1ns
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci, sum, co,
-        n1, n2, n3;
-
-  xor    (n1, a, b);
-  xor #2 (sum, n1, ci);
-  and    (n2, a, b);
-  and    (n3, n1, ci);
-  or  #2 (co, n2, n3);
-  
-  specify
-    (a *> sum) = 5;
-    (b *> sum, co) = 5;
-  endspecify
-
-endmodule
-/*********************************************************************/
-
-
-  'module', 'test', ';',
-     'reg', 'a', 'b', 'ci', 'clk', ';',
-      'wire', 'sum', 'co', 'sum2', ';',
-       'addbit',
-        'i1', '(', 'a', 'b', 'ci', 'sum', 'co', ')',
-        ';',
-      'buf', '(', 'sum2', 'sum', ')', ';',
-       'initial',
-         'begin',
-           '#', '1', '$count_primitives', ';',
-            '#', '1', '$finish', ';',
-          'end',
-    'endmodule',
-    'module',
-      'addbit',
-      '(',
-      'a', 'b', 'ci', 'sum', 'co',
-      ')',
-      ';',
-     'input', 'a', 'b', 'ci', ';',
-      'output', 'sum', 'co', ';',
-      'wire', 'a', 'b', 'ci', 'sum', 'co', 'n1', 'n2', 'n3', ';',
-      'xor', '(', 'n1', 'a', 'b', ')', ';',
-      'xor', '#', '2', '(', 'sum', 'n1', 'ci', ')', ';',
-      'and', '(', 'n2', 'a', 'b', ')', ';',
-      'and', '(', 'n3', 'n1', 'ci', ')', ';',
-      'or', '#', '2', '(', 'co', 'n2', 'n3', ')', ';',
-       'specify',
-        '(', 'a', '*>', 'sum', ')', '=', '5', ';',
-        '(', 'b', '*>', 'sum', 'co', ')', '=', '5', ';',
-        'endspecify',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/count_loads_test.v.parsed.txt Deleted

@@ -1,311 +0,0 @@
-/**********************************************************************
- * $count_loads example -- Verilog test bench source code
- *
- * Verilog test bench to test the $count_loads PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-
-/**********************************************************************
- * Top-level test bench module for a 4-bit adder model.
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-  reg    3:0 a, b;
-  wire   3:0 sum;
-  reg          ci;
-  wire         co;
-
-  add4 i1 (a, b, ci, sum, co);
-
-  initial
-    begin
-      $display("loads on i1.a1.sum = %d\n", $count_loads(i1.a1.sum));
-      $display("loads on i1.a2.r1 = %d\n", $count_loads(i1.a2.r1));
-      #1 $finish;
-    end
-endmodule
-
-/**********************************************************************
- * 4-bit adder model, using a 1-bit adder model.
- *********************************************************************/
-`timescale 1ns / 1ns
-module add4 (a, b, ci, sum, co);
-  input  3:0 a, b;
-  input        ci;
-  output 3:0 sum;
-  output       co;
-
-  wire   3:0 a, b, sum;
-  wire         ci, co, co1, co2, co3;
-  wire         n1, n2, n3, n4, n5, n6, n7, n8, n9;
-
-  addbit  a1  (a0, b0, ci,  sum0, co1, n1);
-  addbit  a2  (a1, b1, co1, sum1, co2, n2);
-  addbit  a3  (a2, b2, co2, sum2, co3, n3);
-  addbit  a4  (a3, b3, co3, sum3, co , n4);
-
-  and2    a5  (n5, sum0, sum1);
-  xor2    a6  (n6, sum0, co);
-  or2     a7  (n7, n1, n2);
-  or2     a8  (n8, n3, n4);
-  and2    a9  (n9, n7, n8);
-endmodule
-
-/**********************************************************************
- * 1-bit adder model, using cells from a library.
- *********************************************************************/
-`timescale 1ns / 1ns
-module addbit (a, b, ci, sum, co, r1);
-  input  a, b, ci;
-  output sum, co;
-  output r1;
-  
-  wire  a, b, ci, sum, co, n1, n2, n3;
-  reg   r1;
-
-  xor2  u1  (n1, a, b);
-  xor2  u2  (sum, n1, ci);
-  and2  u3  (n2, a, b);
-  and2  u4  (n3, n1, ci);
-  or2   u5  (co, n2, n3);
-
-endmodule
-/**********************************************************************
-* Cell library
- *********************************************************************/
-`resetall
-`celldefine
-`timescale 1ns / 10ps
-module or2 (y, a, b);
-  output y;
-  input  a, b;
-  wire   y, a, b;  //wire data type for cmos
-  or    (y, a, b);
-  specify
-    (a *> y) = 1.0;
-    (b *> y) = 1.0;
-    specparam BaseDelay$   = 2.5;
-    specparam InputLoad$a  = 0.3;
-    specparam InputLoad$b  = 0.3;
-    specparam InputLoad$c  = 0.3;
-    specparam in_cap_pf$a  = 0.02;
-    specparam in_cap_pf$b  = 0.02;
-    specparam in_cap_pf$c  = 0.02;
-    specparam out_cap_pf$  = 0.05;
-  endspecify
-endmodule
-`endcelldefine
-/*********************************************************************/
-`resetall
-`celldefine
-`timescale 1ns / 10ps
-module xor2 (y, a, b);
-  output y;
-  input  a, b;
-  wire   y, a, b;  //wire data type for cmos
-  xor   (y, a, b);
-  specify
-    (a *> y) = 1.0;
-    (b *> y) = 1.0;
-    specparam BaseDelay$   = 2.5;
-    specparam InputLoad$a  = 0.3;
-    specparam InputLoad$b  = 0.3;
-    specparam InputLoad$c  = 0.3;
-    specparam in_cap_pf$a  = 0.02;
-    specparam in_cap_pf$b  = 0.02;
-    specparam in_cap_pf$c  = 0.02;
-    specparam out_cap_pf$  = 0.05;
-  endspecify
-endmodule
-`endcelldefine
-/*********************************************************************/
-`resetall
-`celldefine
-`timescale 1 ns / 10 ps
-module and2 (y, a, b);
-  output y;
-  input  a, b;
-  wire   y, a, b;  //wire data type for cmos
-  and   (y, a, b);
-  specify
-    (a *> y) = 1.0;
-    (b *> y) = 1.0;
-    specparam BaseDelay$   = 2.5;
-    specparam InputLoad$a  = 0.2;
-    specparam InputLoad$b  = 0.2;
-    specparam in_cap_pf$a  = 0.02;
-    specparam in_cap_pf$b  = 0.02;
-    specparam out_cap_pf$  = 0.05;
-  endspecify
-endmodule
-`endcelldefine
-/*********************************************************************/
-
-
-
-  'module', 'test', ';',
-     'reg', '', '3', ':', '0', '', 'a', 'b', ';',
-      'wire', '', '3', ':', '0', '', 'sum', ';',
-      'reg', 'ci', ';',
-      'wire', 'co', ';',
-       'add4',
-        'i1', '(', 'a', 'b', 'ci', 'sum', 'co', ')',
-        ';',
-       'initial',
-         'begin',
-            '$display',
-              '(',
-              '"loads on i1.a1.sum = %d\\n"',
-              '$count_loads', '(', 'i1.a1.sum', ')',
-              ')',
-              ';',
-             '$display',
-              '(',
-              '"loads on i1.a2.r1 = %d\\n"',
-              '$count_loads', '(', 'i1.a2.r1', ')',
-              ')',
-              ';',
-            '#', '1', '$finish', ';',
-          'end',
-    'endmodule',
-   'module', 'add4', '(', 'a', 'b', 'ci', 'sum', 'co', ')', ';',
-     'input', '', '3', ':', '0', '', 'a', 'b', ';',
-      'input', 'ci', ';',
-      'output', '', '3', ':', '0', '', 'sum', ';',
-      'output', 'co', ';',
-      'wire', '', '3', ':', '0', '', 'a', 'b', 'sum', ';',
-      'wire', 'ci', 'co', 'co1', 'co2', 'co3', ';',
-      'wire', 'n1', 'n2', 'n3', 'n4', 'n5', 'n6', 'n7', 'n8', 'n9', ';',
-       'addbit',
-         'a1',
-           '(',
-            'a', '', '0', '',
-            'b', '', '0', '',
-            'ci',
-            'sum', '', '0', '',
-            'co1',
-            'n1',
-            ')',
-        ';',
-       'addbit',
-         'a2',
-           '(',
-            'a', '', '1', '',
-            'b', '', '1', '',
-            'co1',
-            'sum', '', '1', '',
-            'co2',
-            'n2',
-            ')',
-        ';',
-       'addbit',
-         'a3',
-           '(',
-            'a', '', '2', '',
-            'b', '', '2', '',
-            'co2',
-            'sum', '', '2', '',
-            'co3',
-            'n3',
-            ')',
-        ';',
-       'addbit',
-         'a4',
-           '(',
-            'a', '', '3', '',
-            'b', '', '3', '',
-            'co3',
-            'sum', '', '3', '',
-            'co',
-            'n4',
-            ')',
-        ';',
-       'and2',
-         'a5',
-           '(',
-            'n5',
-            'sum', '', '0', '',
-            'sum', '', '1', '',
-            ')',
-        ';',
-       'xor2',
-        'a6', '(', 'n6', 'sum', '', '0', '', 'co', ')',
-        ';',
-      'or2', 'a7', '(', 'n7', 'n1', 'n2', ')', ';',
-      'or2', 'a8', '(', 'n8', 'n3', 'n4', ')', ';',
-      'and2', 'a9', '(', 'n9', 'n7', 'n8', ')', ';',
-    'endmodule',
-    'module',
-      'addbit',
-      '(',
-      'a', 'b', 'ci', 'sum', 'co', 'r1',
-      ')',
-      ';',
-     'input', 'a', 'b', 'ci', ';',
-      'output', 'sum', 'co', ';',
-      'output', 'r1', ';',
-      'wire', 'a', 'b', 'ci', 'sum', 'co', 'n1', 'n2', 'n3', ';',
-      'reg', 'r1', ';',
-      'xor2', 'u1', '(', 'n1', 'a', 'b', ')', ';',
-      'xor2', 'u2', '(', 'sum', 'n1', 'ci', ')', ';',
-      'and2', 'u3', '(', 'n2', 'a', 'b', ')', ';',
-      'and2', 'u4', '(', 'n3', 'n1', 'ci', ')', ';',
-      'or2', 'u5', '(', 'co', 'n2', 'n3', ')', ';',
-    'endmodule',
-   'module', 'or2', '(', 'y', 'a', 'b', ')', ';',
-     'output', 'y', ';',
-      'input', 'a', 'b', ';',
-      'wire', 'y', 'a', 'b', ';',
-      'or', '(', 'y', 'a', 'b', ')', ';',
-       'specify',
-        '(', 'a', '*>', 'y', ')', '=', '1.0', ';',
-        '(', 'b', '*>', 'y', ')', '=', '1.0', ';',
-        'specparam', 'BaseDelay$', '=', '2.5', ';',
-        'specparam', 'InputLoad$a', '=', '0.3', ';',
-        'specparam', 'InputLoad$b', '=', '0.3', ';',
-        'specparam', 'InputLoad$c', '=', '0.3', ';',
-        'specparam', 'in_cap_pf$a', '=', '0.02', ';',
-        'specparam', 'in_cap_pf$b', '=', '0.02', ';',
-        'specparam', 'in_cap_pf$c', '=', '0.02', ';',
-        'specparam', 'out_cap_pf$', '=', '0.05', ';',
-        'endspecify',
-    'endmodule',
-   'module', 'xor2', '(', 'y', 'a', 'b', ')', ';',
-     'output', 'y', ';',
-      'input', 'a', 'b', ';',
-      'wire', 'y', 'a', 'b', ';',
-      'xor', '(', 'y', 'a', 'b', ')', ';',
-       'specify',
-        '(', 'a', '*>', 'y', ')', '=', '1.0', ';',
-        '(', 'b', '*>', 'y', ')', '=', '1.0', ';',
-        'specparam', 'BaseDelay$', '=', '2.5', ';',
-        'specparam', 'InputLoad$a', '=', '0.3', ';',
-        'specparam', 'InputLoad$b', '=', '0.3', ';',
-        'specparam', 'InputLoad$c', '=', '0.3', ';',
-        'specparam', 'in_cap_pf$a', '=', '0.02', ';',
-        'specparam', 'in_cap_pf$b', '=', '0.02', ';',
-        'specparam', 'in_cap_pf$c', '=', '0.02', ';',
-        'specparam', 'out_cap_pf$', '=', '0.05', ';',
-        'endspecify',
-    'endmodule',
-   'module', 'and2', '(', 'y', 'a', 'b', ')', ';',
-     'output', 'y', ';',
-      'input', 'a', 'b', ';',
-      'wire', 'y', 'a', 'b', ';',
-      'and', '(', 'y', 'a', 'b', ')', ';',
-       'specify',
-        '(', 'a', '*>', 'y', ')', '=', '1.0', ';',
-        '(', 'b', '*>', 'y', ')', '=', '1.0', ';',
-        'specparam', 'BaseDelay$', '=', '2.5', ';',
-        'specparam', 'InputLoad$a', '=', '0.2', ';',
-        'specparam', 'InputLoad$b', '=', '0.2', ';',
-        'specparam', 'in_cap_pf$a', '=', '0.02', ';',
-        'specparam', 'in_cap_pf$b', '=', '0.02', ';',
-        'specparam', 'out_cap_pf$', '=', '0.05', ';',
-        'endspecify',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/dds.v.parsed.txt Deleted

@@ -1,204 +0,0 @@
-//
-//
-// This is just a little demo of DDS.  It doesn't have any cool features
-// or anything..
-//
-module dds (
-   clk,
-   reset,
-   
-   din,
-   
-   dout
-);
-
-parameter	W = 12;
-
-input		clk;	// Primary clock.
-input		reset;	// Synchronous reset.
-input W-1:0	din;	// The "phase step".
-output W-1:0	dout;	// Output of the phase accumulator register.
-
-reg W-1:0	dout;
-
-reg W-1:0	accum;	// Phas Accumulator
-
-// Just output the accumulator...
-always @(accum)
-   dout <= accum;
-
-// Specify the accumulator..   
-always @(posedge clk) begin
-   if (reset) accum <= 0;
-   else begin
-      accum <= accum + din;
-   end
-end
-
-endmodule
-
-// synopsys translate_off
-module ddstest;
-
-reg		clk;
-reg		reset;
-reg 11:0	din;
-wire 11:0	dout;	
-reg 7:0	cosout;	
-
-// Instantiate the DDS with 12-bits.
-//
-dds #(12) dds1 (.clk(clk),  .reset(reset),  .din(din),  .dout(dout));
-
-// Here's our Cosine lookup table.
-//
-reg 7:0	costable0:4095;  // 4KBytes.
-
-// DDS Phase Accumulator output simply indexes into the Cos lookup table.
-//
-always @(dout)
-   cosout <= costabledout;
-
-// Main test thread.
-//   
-initial begin
-   $readmemh ("cos.hex", costable); // See the PERL program 'generate_cos_table.pl'
-
-   din = 12'h020; // Start at 16
-   #500000;
-   
-   din = 12'h0D0; // A little faster.. 
-   #500000;
-   
-   din = 12'h200; // Fairly fast.
-   #500000;
-   
-   $finish;
-end
-
-// Let's clock it at 1 MHz
-initial begin
-   clk = 0;
-   forever begin
-      #500 clk = 1;
-      #500 clk = 0;
-   end
-end
-
-// Reset
-initial begin
-   reset = 1;
-   #3500 reset = 0;
-end
-
-// Generate VCD file for viewing.
-initial begin
-   $dumpfile ("dds.vcd");
-   $dumpvars (0,ddstest);   
-end
-endmodule
-
-/*
-//***  Here's the Perl program for your reference...
-`ifdef WHEN_PERL_IS_A_SUBSET_OF_VERILOG
-      #!/tools2/perl/bin/perl
-      #
-      #  Generate a file of cos data for use by a DDS simulation.
-      #
-
-      $n      = 4096;	# Number of data points
-      $minval = 0;	# Smallest cos value.
-      $maxval = 255;	# Largest cos value.
-
-      $pi = 3.1415927;
-      $t = 0;
-      for ($i = 1; $i < $n; $i = $i + 1) {
-         $value = ($maxval - $minval)/2 + (($maxval - $minval)/2)*cos($t);
-         $value = int($value);
-         printf "%x\n", $value;
-         $t = $t + 2*$pi / $n;
-      }
-`endif
-*/
-
-  'module', 'dds', '(', 'clk', 'reset', 'din', 'dout', ')', ';',
-     'parameter', 'W', '=', '12', ';',
-      'input', 'clk', ';',
-      'input', 'reset', ';',
-      'input', '', 'W', '-', '1', ':', '0', '', 'din', ';',
-      'output', '', 'W', '-', '1', ':', '0', '', 'dout', ';',
-      'reg', '', 'W', '-', '1', ':', '0', '', 'dout', ';',
-      'reg', '', 'W', '-', '1', ':', '0', '', 'accum', ';',
-       'always',
-        '@', '(', 'accum', ')',
-        'dout', '<=', 'accum', ';',
-       'always',
-        '@', '(', 'posedge', 'clk', ')',
-         'begin',
-            'if',
-              '(', 'reset', ')',
-              'accum', '<=', '0', ';',
-              'else',
-               'begin',
-                'accum', '<=', 'accum', '+', 'din', ';',
-                'end',
-          'end',
-    'endmodule',
-   'module', 'ddstest', ';',
-     'reg', 'clk', ';',
-      'reg', 'reset', ';',
-      'reg', '', '11', ':', '0', '', 'din', ';',
-      'wire', '', '11', ':', '0', '', 'dout', ';',
-      'reg', '', '7', ':', '0', '', 'cosout', ';',
-       'dds',
-        '#', '(', '12', ')',
-         'dds1',
-           '(',
-            '.', 'clk', '(', 'clk', ')',
-            '.', 'reset', '(', 'reset', ')',
-            '.', 'din', '(', 'din', ')',
-            '.', 'dout', '(', 'dout', ')',
-            ')',
-        ';',
-       'reg',
-        '',
-        '7',
-        ':',
-        '0',
-        '',
-        'costable', '', '0', ':', '4095', '',
-        ';',
-       'always',
-        '@', '(', 'dout', ')',
-        'cosout', '<=', 'costable', '', 'dout', '', ';',
-       'initial',
-         'begin',
-           '$readmemh', '(', '"cos.hex"', 'costable', ')', ';',
-            'din', '=', "12 'h 020", ';',
-            '#', '500000', ';',
-            'din', '=', "12 'h 0D0", ';',
-            '#', '500000', ';',
-            'din', '=', "12 'h 200", ';',
-            '#', '500000', ';',
-            '$finish', ';',
-          'end',
-       'initial',
-         'begin',
-           'clk', '=', '0', ';',
-             'forever',
-               'begin',
-                 '#', '500', 'clk', '=', '1', ';',
-                  '#', '500', 'clk', '=', '0', ';',
-                'end',
-          'end',
-       'initial',
-         'begin',
-           'reset', '=', '1', ';',
-            '#', '3500', 'reset', '=', '0', ';',
-          'end',
-       'initial',
-         'begin',
-           '$dumpfile', '(', '"dds.vcd"', ')', ';',
-            '$dumpvars', '(', '0', 'ddstest', ')', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/diff_udp.v.parsed.txt Deleted

@@ -1,41 +0,0 @@
-primitive dff(q, clk, d);
-output q;
-reg q; // storage element
-input clk, d;
-initial q = 0;
-table
-// clk d state next
-  (01) 0 : ? : 0; // all positive transitions
-  (01) 1 : ? : 1;
-  (0x) 0 : ? : 0;
-  (0x) 1 : ? : 1;
-  (x1) 0 : ? : 0;
-  (x1) 1 : ? : 1;
-  // ignore negative edge
-  n    ? : ? : -;
-  // ignore data changes on steady clock
-  (??) ? : ? : -;
-endtable
-endprimitive
-
-  'primitive',
-    'dff',
-    '(',
-    'q', 'clk', 'd',
-    ')',
-    ';',
-    'output', 'q', ';',
-    'reg', 'q', ';',
-    'input', 'clk', 'd', ';',
-    'initial', 'q', '=', '0', ';',
-     'table',
-      '(', '0', '1', ')', '0', ':', '?', ':', '0', ';',
-      '(', '0', '1', ')', '1', ':', '?', ':', '1', ';',
-      '(', '0', 'x', ')', '0', ':', '?', ':', '0', ';',
-      '(', '0', 'x', ')', '1', ':', '?', ':', '1', ';',
-      '(', 'x', '1', ')', '0', ':', '?', ':', '0', ';',
-      '(', 'x', '1', ')', '1', ':', '?', ':', '1', ';',
-      'n', '?', ':', '?', ':', '-', ';',
-      '(', '?', '?', ')', '?', ':', '?', ':', '-', ';',
-      'endtable',
-    'endprimitive'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/display_all_nets_test.v.parsed.txt Deleted

@@ -1,104 +0,0 @@
-/**********************************************************************
- * $display_all_nets example -- Verilog test bench source code
- *
- * Verilog test bench to test the $display_all_nets PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module top;
-  reg  2:0 test;
-  reg        clock;
-  wire 1:0 results;
-
-  addbit i1 (test0, test1, test2, results0, results1);
-
-  always @(negedge clock)
-    $display_all_nets(i1);
-
-  initial
-    begin
-      clock = 1;
-      forever #5 clock = ~clock;
-    end
-
-  initial
-    begin
-      test = 3'b000;
-      @(posedge clock) test = 3'b001;
-      @(posedge clock) test = 3'b011;
-      @(posedge clock) $finish;
-    end
-endmodule
-
-/*** A gate level 1 bit adder model ***/
-`timescale 1ns / 1ns
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci, sum, co,
-        n1, n2, n3;
-
-  xor    (n1, a, b);
-  xor #2 (sum, n1, ci);
-  and    (n2, a, b);
-  and    (n3, n1, ci);
-  or  #2 (co, n2, n3);
-
-endmodule
-/*********************************************************************/
-
-
-
-  'module', 'top', ';',
-     'reg', '', '2', ':', '0', '', 'test', ';',
-      'reg', 'clock', ';',
-      'wire', '', '1', ':', '0', '', 'results', ';',
-       'addbit',
-         'i1',
-           '(',
-            'test', '', '0', '',
-            'test', '', '1', '',
-            'test', '', '2', '',
-            'results', '', '0', '',
-            'results', '', '1', '',
-            ')',
-        ';',
-       'always',
-        '@', '(', 'negedge', 'clock', ')',
-        '$display_all_nets', '(', 'i1', ')', ';',
-       'initial',
-         'begin',
-           'clock', '=', '1', ';',
-            'forever', '#', '5', 'clock', '=', '~', 'clock', ';',
-          'end',
-       'initial',
-         'begin',
-           'test', '=', "3 'b 000", ';',
-             '@', '(', 'posedge', 'clock', ')',
-              'test', '=', "3 'b 001", ';',
-             '@', '(', 'posedge', 'clock', ')',
-              'test', '=', "3 'b 011", ';',
-            '@', '(', 'posedge', 'clock', ')', '$finish', ';',
-          'end',
-    'endmodule',
-    'module',
-      'addbit',
-      '(',
-      'a', 'b', 'ci', 'sum', 'co',
-      ')',
-      ';',
-     'input', 'a', 'b', 'ci', ';',
-      'output', 'sum', 'co', ';',
-      'wire', 'a', 'b', 'ci', 'sum', 'co', 'n1', 'n2', 'n3', ';',
-      'xor', '(', 'n1', 'a', 'b', ')', ';',
-      'xor', '#', '2', '(', 'sum', 'n1', 'ci', ')', ';',
-      'and', '(', 'n2', 'a', 'b', ')', ';',
-      'and', '(', 'n3', 'n1', 'ci', ')', ';',
-      'or', '#', '2', '(', 'co', 'n2', 'n3', ')', ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/div16.v.parsed.txt Deleted

@@ -1,510 +0,0 @@
-//
-// Integer Multicycle Divide circuit (divide a 16-bit number by a 16-bit number in 16 cycles).
-//
-// a / b = q with remainder r
-//
-// Where a is 16-bits,
-// Where b is 16 bits
-//
-// Module is actually parameterized if you want other widths.
-//
-// *** Test the ranges of values for which you'll use this.  For example, you
-//     can't divide FFFF by FF without underflow (overflow?).  Mess with
-//     the testbench.  You may need to widen some thing.  ***
-//
-// The answer is 16-bits and the remainder is also 16-bits.
-// After the start pulse, the module requires 16 cycles to complete.
-// The q/r outputs stay the same until next start pulse.
-// Start pulse should be a single cycle.
-// Division by zero results in a quotient equal to FFFF and remainder equal to 'a'.
-//
-// 
-// Written by tom coonan.
-//
-// Notes:
-//    - This ain't fancy.  I wanted something straight-forward quickly.  Go study
-//      more elaborate algorithms if you want to optimize area or speed.  If you
-//      have an isolated divide and can spare N cycles for N bits; this may meet your needs.
-//    - You might want to think more about the sizes of things.  I wanted a basic estimate
-//      of gates plus I specifically needed to divide 16-bits (not even full range)
-//      by 8-bits.
-//    - Handle divide by zero at higher level..
-//    - I needed a remainder so I could easily to truncate and rounding stuff,
-//      but remove this to save gates if you don't need a remainder.
-//    - This is about 800 asic gates (0.25um, Standard Cell, 27Mhz).  27Mhz
-//      is my system clock and NOT the maximum it can go..
-//    - I tried to keep everything parameterized by N, but I only worked through
-//      the N=16 case because that's what I needed...
-//
-module div16 (clk, resetb, start, a, b, q, r, done);
-
-parameter N = 16;	// a/b = q remainder r, where all operands are N wide.
-
-input		clk;
-input		resetb;	// Asynchronous, active low reset.
-input		start;	// Pulse this to start the division.
-input N-1:0	a;	// This is the number we are dividing (the dividend)
-input N-1:0	b;	// This is the 'divisor'
-output N-1:0	q;	// This is the 'quotient'
-output N-1:0	r;	// Here is the remainder.
-output		done;	// Will be asserted when q and r are available.
-
-// Registered q
-reg N-1:0	q;
-reg		done;
-
-// Power is the current 2^n bit we are considering.  Power is a shifting
-// '1' that starts at the highest power of 2 and goes all the way down
-// to ...00001  Shift this until it is zero at which point we stop.
-//
-reg N-1:0	power;
-
-// This is the accumulator.  We are start with the accumulator set to 'a' (the dividend).
-// For each (divisor*2^N) term, we see if we can subtract (divisor*2^N) from the accumulator.
-// We subtract these terms as long as adding in the term doesn't cause the accumulator
-// to exceed a.  When we are done, whatever is left in the accumulator is the remainder.
-//
-reg N-1:0	accum;
-
-// This is the divisor*2^N term.  Essentually, we are taking the divisor ('b'), initially
-// shifting it all the way to the left, and shifting it 1 bit at a time to the right.
-//
-reg (2*N-1):0	bpower;
-
-// Remainder will be whatever is left in the accumulator.
-assign r = accum;
-
-// Do this addition here for resource sharing.  
-// ** Note that 'accum' is N bits wide, but bpower is 2*N-1 bits wide **
-//
-wire 2*N-1:0 accum_minus_bpower = accum - bpower;
-
-always @(posedge clk or negedge resetb) begin
-   if (~resetb) begin
-      q <= 0;
-      accum <= 0;
-      power <= 0;
-      bpower <= 0;
-      done <= 0;
-   end
-   else begin
-      if (start) begin
-         // Reinitialize the divide circuit.
-         q      <= 0;
-         accum  <= a; // Accumulator initially gets the dividend.  
-         powerN-1 <= 1'b1; // We start with highest power of 2 (which is a '1' in MSB)
-         bpower <= b << N-1; // Start with highest bpower, which is (divisor * 2^(N-1))
-         done <= 0;
-      end
-      else begin
-         // Go until power is zero.
-         //
-         if (power != 0) begin
-            //
-            // Can we add this divisor*2^(power) to the accumulator without going negative?
-            // Just test the MSB of the subtraction.  If it is '1', then it must be negative.
-            //
-            if ( ~accum_minus_bpower2*N-1) begin
-               // Yes!  Set this power of 2 in the quotieny and
-               // then actually comitt to the subtraction from our accumulator.
-               //
-               q     <= q | power;
-               accum <= accum_minus_bpower;
-            end
-            // Regardless, always go to next lower power of 2.
-            //
-            power  <= power >> 1;
-            bpower <= bpower >> 1;
-         end
-         else begin
-            // We're done.  Set done flag.
-            done <= 1;
-         end
-      end
-   end
-end
-endmodule
-
-// synopsys translate_off
-module test_div16;
-reg		clk;
-reg		resetb;
-reg		start;
-reg 15:0	a;
-reg 15:0	b;
-wire 15:0	q;
-wire 15:0	r;
-wire		done;
-
-integer		num_errors;
-
-div16 div16 (
-   .clk(clk),
-   .resetb(resetb),
-   .start(start),
-   .a(a),
-   .b(b),
-   .q(q),
-   .r(r),
-   .done(done)
-);
-
-initial begin
-   num_errors = 0;
-   
-   start = 0;
-   
-   // Wait till reset is completely over.
-   #200;
-   
-   // Do some divisions where divisor is constrained to 8-bits and dividend is 16-bits
-   $display ("16-bit Dividend, 8-bit divisor");
-   repeat (25) begin
-      do_divide ($random, $random & 255);
-   end
-   
-   // Do some divisions where divisor is constrained to 12-bits and dividend is 16-bits
-   $display ("\n16-bit Dividend, 12-bit divisor");
-   repeat (25) begin
-      do_divide ($random, $random & 4095);
-   end
-   
-   // Do some divisions where both divisor and dividend is 16-bits
-   $display ("\n16-bit Dividend, 16-bit divisor");
-   repeat (25) begin
-      do_divide ($random, $random);
-   end
-   
-   // Special cases
-   $display ("\nSpecial Cases:");
-   do_divide (16'hFFFF,  16'hFFFF); // largest possible quotient
-   do_divide (312,  1); // divide by 1
-   do_divide (  0, 42); // divide 0 by something else
-   do_divide (312,  0); // divide by zero
-
-   // That's all.  Summarize the test.
-   if (num_errors === 0) begin
-      $display ("\n\nSUCCESS.  There were %0d Errors.", num_errors);
-   end
-   else begin
-      $display ("\n\nFAILURE!!  There were %0d Errors.", num_errors);
-   end
-   
-   $finish;
-end
-
-task do_divide;
-   input 15:0 arga;
-   input 15:0 argb;
-   
-   begin
-      a = arga;
-      b = argb;
-      @(posedge clk);
-      #1 start = 1;
-      @(posedge clk);
-      #1 start = 0;
-      while (~done) @(posedge clk);
-      #1;
-      
-      $display ("Circuit: %0d / %0d = %0d, rem = %0d \t\t......... Reality: %0d, rem = %0d", arga, argb, q, r, a/b, a%b);
-      if (b !== 0) begin
-         if (q !== a/b) begin
-            $display ("   Error!  Unexpected Quotient\n\n");
-            num_errors = num_errors + 1;
-         end
-         if (r !== a % b) begin
-            $display ("   Error!  Unexpected Remainder\n\n");
-            num_errors = num_errors + 1;
-         end
-      end
-   end
-endtask
-
-initial begin
-   clk = 0;
-   forever begin
-      #10 clk = 1;
-      #10 clk = 0;
-   end
-end
-
-initial begin
-   resetb = 0;
-   #133 resetb = 1;
-end
-
-initial begin
-   $dumpfile ("test_div16.vcd");
-   $dumpvars (0,test_div16);   
-end
-
-endmodule
-
-
-   'module',
-      'div16',
-      '(',
-      'clk', 'resetb', 'start', 'a', 'b', 'q', 'r', 'done',
-      ')',
-      ';',
-     'parameter', 'N', '=', '16', ';',
-      'input', 'clk', ';',
-      'input', 'resetb', ';',
-      'input', 'start', ';',
-      'input', '', 'N', '-', '1', ':', '0', '', 'a', ';',
-      'input', '', 'N', '-', '1', ':', '0', '', 'b', ';',
-      'output', '', 'N', '-', '1', ':', '0', '', 'q', ';',
-      'output', '', 'N', '-', '1', ':', '0', '', 'r', ';',
-      'output', 'done', ';',
-      'reg', '', 'N', '-', '1', ':', '0', '', 'q', ';',
-      'reg', 'done', ';',
-      'reg', '', 'N', '-', '1', ':', '0', '', 'power', ';',
-      'reg', '', 'N', '-', '1', ':', '0', '', 'accum', ';',
-       'reg',
-        '',
-        '(',
-        '2', '*', 'N', '-', '1',
-        ')',
-        ':',
-        '0',
-        '',
-        'bpower',
-        ';',
-      'assign', 'r', '=', 'accum', ';',
-       'wire',
-        '',
-        '2',
-        '*',
-        'N',
-        '-',
-        '1',
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-        '0',
-        '',
-        'accum_minus_bpower', '=', 'accum', '-', 'bpower',
-        ';',
-       'always',
-        '@', '(', 'posedge', 'clk', 'negedge', 'resetb', ')',
-         'begin',
-            'if',
-              '(', '~', 'resetb', ')',
-               'begin',
-                 'q', '<=', '0', ';',
-                  'accum', '<=', '0', ';',
-                  'power', '<=', '0', ';',
-                  'bpower', '<=', '0', ';',
-                  'done', '<=', '0', ';',
-                'end',
-              'else',
-               'begin',
-                  'if',
-                    '(', 'start', ')',
-                     'begin',
-                       'q', '<=', '0', ';',
-                        'accum', '<=', 'a', ';',
-                          'power', '', 'N', '-', '1', '',
-                            '<=',
-                            "1 'b 1",
-                          ';',
-                        'bpower', '<=', 'b', '<<', 'N', '-', '1', ';',
-                        'done', '<=', '0', ';',
-                      'end',
-                    'else',
-                     'begin',
-                        'if',
-                          '(', 'power', '!=', '0', ')',
-                           'begin',
-                              'if',
-                                 '(',
-                                  '~',
-                                   'accum_minus_bpower',
-                                    '', '2', '*', 'N', '-', '1', '',
-                                  ')',
-                                 'begin',
-                                   'q', '<=', 'q', '|', 'power', ';',
-                                     'accum', '<=', 'accum_minus_bpower',
-                                      ';',
-                                  'end',
-                              'power', '<=', 'power', '>>', '1', ';',
-                              'bpower', '<=', 'bpower', '>>', '1', ';',
-                            'end',
-                          'else',
-                          'begin', 'done', '<=', '1', ';', 'end',
-                      'end',
-                'end',
-          'end',
-    'endmodule',
-   'module', 'test_div16', ';',
-     'reg', 'clk', ';',
-      'reg', 'resetb', ';',
-      'reg', 'start', ';',
-      'reg', '', '15', ':', '0', '', 'a', ';',
-      'reg', '', '15', ':', '0', '', 'b', ';',
-      'wire', '', '15', ':', '0', '', 'q', ';',
-      'wire', '', '15', ':', '0', '', 'r', ';',
-      'wire', 'done', ';',
-      'integer', 'num_errors', ';',
-       'div16',
-         'div16',
-           '(',
-            '.', 'clk', '(', 'clk', ')',
-            '.', 'resetb', '(', 'resetb', ')',
-            '.', 'start', '(', 'start', ')',
-            '.', 'a', '(', 'a', ')',
-            '.', 'b', '(', 'b', ')',
-            '.', 'q', '(', 'q', ')',
-            '.', 'r', '(', 'r', ')',
-            '.', 'done', '(', 'done', ')',
-            ')',
-        ';',
-       'initial',
-         'begin',
-           'num_errors', '=', '0', ';',
-            'start', '=', '0', ';',
-            '#', '200', ';',
-            '$display', '(', '"16-bit Dividend, 8-bit divisor"', ')', ';',
-             'repeat',
-              '(',
-              '25',
-              ')',
-               'begin',
-                  'do_divide',
-                    '(',
-                    '$random',
-                    '$random',
-                    '&',
-                    '255',
-                    ')',
-                    ';',
-                'end',
-            '$display', '(', '"\\n16-bit Dividend, 12-bit divisor"', ')', ';',
-             'repeat',
-              '(',
-              '25',
-              ')',
-               'begin',
-                  'do_divide',
-                    '(',
-                    '$random',
-                    '$random',
-                    '&',
-                    '4095',
-                    ')',
-                    ';',
-                'end',
-            '$display', '(', '"\\n16-bit Dividend, 16-bit divisor"', ')', ';',
-             'repeat',
-              '(',
-              '25',
-              ')',
-               'begin',
-                'do_divide', '(', '$random', '$random', ')', ';',
-                'end',
-            '$display', '(', '"\\nSpecial Cases:"', ')', ';',
-            'do_divide', '(', "16 'h FFFF", "16 'h FFFF", ')', ';',
-            'do_divide', '(', '312', '1', ')', ';',
-            'do_divide', '(', '0', '42', ')', ';',
-            'do_divide', '(', '312', '0', ')', ';',
-             'if',
-              '(', 'num_errors', '===', '0', ')',
-               'begin',
-                  '$display',
-                    '(',
-                    '"\\n\\nSUCCESS.  There were %0d Errors."',
-                    'num_errors',
-                    ')',
-                    ';',
-                'end',
-              'else',
-               'begin',
-                  '$display',
-                    '(',
-                    '"\\n\\nFAILURE!!  There were %0d Errors."',
-                    'num_errors',
-                    ')',
-                    ';',
-                'end',
-            '$finish', ';',
-          'end',
-       'task',
-        'do_divide',
-        ';',
-        'input', '', '15', ':', '0', '', 'arga', ';',
-        'input', '', '15', ':', '0', '', 'argb', ';',
-         'begin',
-           'a', '=', 'arga', ';',
-            'b', '=', 'argb', ';',
-            '@', '(', 'posedge', 'clk', ')', ';',
-            '#', '1', 'start', '=', '1', ';',
-            '@', '(', 'posedge', 'clk', ')', ';',
-            '#', '1', 'start', '=', '0', ';',
-             'while',
-              '(',
-              '~',
-              'done',
-              ')',
-              '@', '(', 'posedge', 'clk', ')', ';',
-            '#', '1', ';',
-             '$display',
-              '(',
-              '"Circuit: %0d / %0d = %0d, rem = %0d \\t\\t......... Reality: '
-              '%0d, rem = %0d"',
-              'arga',
-              'argb',
-              'q',
-              'r',
-              'a',
-              '/',
-              'b',
-              'a',
-              '%',
-              'b',
-              ')',
-              ';',
-             'if',
-              '(', 'b', '!==', '0', ')',
-               'begin',
-                  'if',
-                    '(', 'q', '!==', 'a', '/', 'b', ')',
-                     'begin',
-                        '$display',
-                          '(',
-                          '"   Error!  Unexpected Quotient\\n\\n"',
-                          ')',
-                          ';',
-                        'num_errors', '=', 'num_errors', '+', '1', ';',
-                      'end',
-                   'if',
-                    '(', 'r', '!==', 'a', '%', 'b', ')',
-                     'begin',
-                        '$display',
-                          '(',
-                          '"   Error!  Unexpected Remainder\\n\\n"',
-                          ')',
-                          ';',
-                        'num_errors', '=', 'num_errors', '+', '1', ';',
-                      'end',
-                'end',
-          'end',
-        'endtask',
-       'initial',
-         'begin',
-           'clk', '=', '0', ';',
-             'forever',
-               'begin',
-                 '#', '10', 'clk', '=', '1', ';',
-                  '#', '10', 'clk', '=', '0', ';',
-                'end',
-          'end',
-       'initial',
-         'begin',
-           'resetb', '=', '0', ';',
-            '#', '133', 'resetb', '=', '1', ';',
-          'end',
-       'initial',
-         'begin',
-           '$dumpfile', '(', '"test_div16.vcd"', ')', ';',
-            '$dumpvars', '(', '0', 'test_div16', ')', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/dro.v.parsed.txt Deleted

@@ -1,247 +0,0 @@
-// Verilog HDL for "gates.lib", "dro_cell" "_functional"
-// Module DRO cell
-module dro_cell (d, clk, out);
-
-input
-	d, clk;
-
-output
-	out;
-reg 
-	out;
-
-parameter
-	t_hold	= -3,
-	t_setup	= 8,
-	delay	= 9,
-
-	warning_file=3;  // multichannel description of a warning file
-
-reg
-	d_internal, clk_internal,
-	d_state,          	   // internal state at the input d
-	d_set;		   	   // signal determining the moment when
-				   // the state of the d input changes to "1"
-
-integer
-	data_delay,  // delay between d and d_internal
-	clk_delay,   // delay between clk and clk_internal
-	out_delay,   // delay between clk_internal and out
-	out_value,   // output value in a given clock cycle
-	last_clk_time;	// time when the last clock pulse appeared
-
-initial 
-	begin
-// define delays between inputs & outputs and the corresponding
-//  internal auxiliary registers
-	  	if(t_hold<0)
-		  begin
-	    	  	data_delay = -t_hold;
-	    		clk_delay  = 0;
-			out_delay  = delay;
-		  end
-	  	else
-		  begin
-	   	  	data_delay = 0;
-	    		clk_delay  = t_hold;
-		  	out_delay  = delay-t_hold;
-		  end
-
-// clear internal registers and the output signal
-		d_internal = 0;
-		clk_internal = 0;
-		last_clk_time = 0;
-		d_state = 0;
-		d_set = 0;
-		out = 0;
-	end
-
-
-
-always @(posedge d) 	// Execute at positive edge of d
-	  d_internal <= #(data_delay) d;
-
-always @(posedge clk)  // Execute at positive edge of clk
-	  clk_internal <= #(clk_delay) clk;
-
-
-always @(posedge d_internal)
-	begin
-// setting the state of the d input
-                d_state <= d_state | 1'bx;
-		if (d_internal === 1)
-		  d_set <= #(t_hold+t_setup) 1;
-
-		d_internal <= 0;
-	end
-
-always @(posedge d_set)
-	begin
-		if ($stime - last_clk_time >= t_hold+t_setup)
-			d_state = 1;
-		else
-		  begin
-			d_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input D pulse at %0d,",
-			 $stime-data_delay-t_hold-t_setup);
-			$fwrite(warning_file,
-			"\tClock pulse at %0d.\n", last_clk_time-clk_delay);
-		  end
-
-		d_set <= 0;
-	end
-
-
-always @(posedge clk_internal)	
-	begin
-// computing the output
-		if (clk_internal === 1'bx)
-		  out_value = 1'bx;
-		else
-		  out_value = d_state;
-
-// transfering the result to the output
-		out <= #(out_delay) out_value;
-		out <= #(out_delay+2) 0;
-
-// clearing the internal state of the DRO
-		d_state  <= 0;
-
-		clk_internal <= 0;
-		last_clk_time = $stime;
-	end
-
-endmodule
-
-
-  'module', 'dro_cell', '(', 'd', 'clk', 'out', ')', ';',
-     'input', 'd', 'clk', ';',
-      'output', 'out', ';',
-      'reg', 'out', ';',
-       'parameter',
-        't_hold', '=', '-', '3',
-        't_setup', '=', '8',
-        'delay', '=', '9',
-        'warning_file', '=', '3',
-        ';',
-      'reg', 'd_internal', 'clk_internal', 'd_state', 'd_set', ';',
-       'integer',
-        'data_delay',
-        'clk_delay',
-        'out_delay',
-        'out_value',
-        'last_clk_time',
-        ';',
-       'initial',
-         'begin',
-            'if',
-              '(', 't_hold', '<', '0', ')',
-               'begin',
-                 'data_delay', '=', '-', 't_hold', ';',
-                  'clk_delay', '=', '0', ';',
-                  'out_delay', '=', 'delay', ';',
-                'end',
-              'else',
-               'begin',
-                 'data_delay', '=', '0', ';',
-                  'clk_delay', '=', 't_hold', ';',
-                  'out_delay', '=', 'delay', '-', 't_hold', ';',
-                'end',
-            'd_internal', '=', '0', ';',
-            'clk_internal', '=', '0', ';',
-            'last_clk_time', '=', '0', ';',
-            'd_state', '=', '0', ';',
-            'd_set', '=', '0', ';',
-            'out', '=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'd', ')',
-         'd_internal', '<=', '#', '(', 'data_delay', ')', 'd',
-          ';',
-       'always',
-        '@', '(', 'posedge', 'clk', ')',
-         'clk_internal', '<=', '#', '(', 'clk_delay', ')', 'clk',
-          ';',
-       'always',
-        '@', '(', 'posedge', 'd_internal', ')',
-         'begin',
-           'd_state', '<=', 'd_state', '|', "1 'b x", ';',
-             'if',
-              '(', 'd_internal', '===', '1', ')',
-                'd_set',
-                  '<=',
-                  '#', '(', 't_hold', '+', 't_setup', ')',
-                  '1',
-                ';',
-            'd_internal', '<=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'd_set', ')',
-         'begin',
-            'if',
-               '(',
-                '$stime',
-                '-',
-                'last_clk_time',
-                '>=',
-                't_hold',
-                '+',
-                't_setup',
-                ')',
-              'd_state', '=', '1', ';',
-              'else',
-               'begin',
-                 'd_state', '=', "1 'b x", ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Violation of hold/setup time in module %m.\\n"',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Input D pulse at %0d,"',
-                    '$stime',
-                    '-',
-                    'data_delay',
-                    '-',
-                    't_hold',
-                    '-',
-                    't_setup',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"\\tClock pulse at %0d.\\n"',
-                    'last_clk_time',
-                    '-',
-                    'clk_delay',
-                    ')',
-                    ';',
-                'end',
-            'd_set', '<=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'clk_internal', ')',
-         'begin',
-            'if',
-              '(', 'clk_internal', '===', "1 'b x", ')',
-              'out_value', '=', "1 'b x", ';',
-              'else',
-              'out_value', '=', 'd_state', ';',
-             'out', '<=', '#', '(', 'out_delay', ')', 'out_value',
-              ';',
-             'out', '<=', '#', '(', 'out_delay', '+', '2', ')', '0',
-              ';',
-            'd_state', '<=', '0', ';',
-            'clk_internal', '<=', '0', ';',
-            'last_clk_time', '=', '$stime', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/dro1_cell.v.parsed.txt Deleted

@@ -1,339 +0,0 @@
-// Verilog HDL for "RSFQ.lib", "dro1_cell" "_functional"
-
-// Module DRO1 cell
-module dro1_cell (d, clk, out);
-
-input
-	d, clk;
-
-output
-	out;
-reg 
-	out;
-
-parameter
-	t_hold	= -6,
-	t_setup	= 11,
-	delay	=  6,
-
-// multichannel description of a warning file
-	warning_file=2,  
-// multichannel description of a delay file
-	delay_file = warning_file<<1;
-
-reg
-	d_internal, clk_internal,
-	d_state,          	   // internal state at the input d
-	d_set;		   	   // signal determining the moment when
-				   // the state of the d input changes to "1"
-
-integer
-	data_delay,  // delay between d and d_internal
-	clk_delay,   // delay between clk and clk_internal
-	out_delay,   // delay between clk_internal and out
-	out_value,   // output value in a given clock cycle
-	last_clk_time,	// time when the last clock pulse appeared
-	vt_hold,	// variable hold
-	vt_setup,	// variable setup
-	vdelay;		// variable delay
-
-`include "INIT"
-
-`ifdef RANDOM_DELAYS
- `include "RANDOM_GATE"
-`endif
-
-initial 
-	begin
-
-		vt_hold = t_hold;
-		vt_setup = t_setup;
-		vdelay = delay;
-
-`ifdef RANDOM_DELAYS
-		delay_dev = dro1_cell_variation*delay;
-		vdelay = $dist_normal(dro1_cell_seed, delay, delay_dev);
-		vt_hold = $dist_normal(dro1_cell_seed, t_hold, dro1_hs_dev);
-		vt_setup = t_setup + (t_hold - vt_hold);
-`endif
-
-		#1 $fdisplay(delay_file, "module=%m, nom_delay=%0d, delay=%0d", delay, vdelay);
-		#1 $fdisplay(delay_file, "module=%m, nom_hold=%0d, hold=%0d", t_hold, vt_hold);
-		#1 $fdisplay(delay_file, "module=%m, nom_setup=%0d, setup=%0d", t_setup, vt_setup);
-
-
-// define delays between inputs & outputs and the corresponding
-//  internal auxiliary registers
-	  	if(vt_hold<0)
-		  begin
-	    	  	data_delay = -vt_hold;
-	    		clk_delay  = 0;
-			out_delay  = vdelay;
-		  end
-	  	else
-		  begin
-	   	  	data_delay = 0;
-	    		clk_delay  = vt_hold;
-		  	out_delay  = vdelay-vt_hold;
-		  end
-
-// clear internal registers and the output signal
-		d_internal = 0;
-		clk_internal = 0;
-		last_clk_time = 0;
-		d_state = 0;
-		d_set = 0;
-		out = 0;
-	end
-
-
-
-always @(posedge d) 	// Execute at positive edge of d
-	  d_internal <= #(data_delay) d;
-
-always @(posedge clk)  // Execute at positive edge of clk
-	  clk_internal <= #(clk_delay) clk;
-
-
-always @(posedge d_internal)
-	begin
-// setting the state of the d input
-                d_state <= d_state | 1'bx;
-		if (d_internal === 1)
-		  d_set <= #(vt_hold+vt_setup) 1;
-
-		d_internal <= 0;
-	end
-
-always @(posedge d_set)
-	begin
-		if ($stime - last_clk_time >= vt_hold+vt_setup)
-			d_state = 1;
-		else
-		  begin
-			d_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input D pulse at %0d,",
-			 $stime-data_delay-vt_hold-vt_setup);
-			$fwrite(warning_file,
-			"\tClock pulse at %0d.\n", last_clk_time-clk_delay);
-		  end
-
-		d_set <= 0;
-	end
-
-
-always @(posedge clk_internal)	
-	begin
-// computing the output
-		if (clk_internal === 1'bx)
-		  out_value = 1'bx;
-		else
-		  out_value = d_state;
-
-// transfering the result to the output
-		out <= #(out_delay) out_value;
-		out <= #(out_delay+2) 0;
-
-// clearing the internal state of the DRO
-		d_state  <= 0;
-
-		clk_internal <= 0;
-		last_clk_time = $stime;
-	end
-
-endmodule
-
-
-  'module', 'dro1_cell', '(', 'd', 'clk', 'out', ')', ';',
-     'input', 'd', 'clk', ';',
-      'output', 'out', ';',
-      'reg', 'out', ';',
-       'parameter',
-        't_hold', '=', '-', '6',
-        't_setup', '=', '11',
-        'delay', '=', '6',
-        'warning_file', '=', '2',
-        'delay_file', '=', 'warning_file', '<<', '1',
-        ';',
-      'reg', 'd_internal', 'clk_internal', 'd_state', 'd_set', ';',
-       'integer',
-        'data_delay',
-        'clk_delay',
-        'out_delay',
-        'out_value',
-        'last_clk_time',
-        'vt_hold',
-        'vt_setup',
-        'vdelay',
-        ';',
-       'initial',
-         'begin',
-           'vt_hold', '=', 't_hold', ';',
-            'vt_setup', '=', 't_setup', ';',
-            'vdelay', '=', 'delay', ';',
-             'delay_dev', '=', 'dro1_cell_variation', '*', 'delay',
-              ';',
-              'vdelay',
-                '=',
-                 '$dist_normal',
-                  '(',
-                  'dro1_cell_seed',
-                  'delay',
-                  'delay_dev',
-                  ')',
-              ';',
-              'vt_hold',
-                '=',
-                 '$dist_normal',
-                  '(',
-                  'dro1_cell_seed',
-                  't_hold',
-                  'dro1_hs_dev',
-                  ')',
-              ';',
-              'vt_setup',
-                '=',
-                't_setup',
-                '+',
-                '(',
-                't_hold', '-', 'vt_hold',
-                ')',
-              ';',
-             '#', '1',
-               '$fdisplay',
-                '(',
-                'delay_file',
-                '"module=%m, nom_delay=%0d, delay=%0d"',
-                'delay',
-                'vdelay',
-                ')',
-                ';',
-             '#', '1',
-               '$fdisplay',
-                '(',
-                'delay_file',
-                '"module=%m, nom_hold=%0d, hold=%0d"',
-                't_hold',
-                'vt_hold',
-                ')',
-                ';',
-             '#', '1',
-               '$fdisplay',
-                '(',
-                'delay_file',
-                '"module=%m, nom_setup=%0d, setup=%0d"',
-                't_setup',
-                'vt_setup',
-                ')',
-                ';',
-             'if',
-              '(', 'vt_hold', '<', '0', ')',
-               'begin',
-                 'data_delay', '=', '-', 'vt_hold', ';',
-                  'clk_delay', '=', '0', ';',
-                  'out_delay', '=', 'vdelay', ';',
-                'end',
-              'else',
-               'begin',
-                 'data_delay', '=', '0', ';',
-                  'clk_delay', '=', 'vt_hold', ';',
-                  'out_delay', '=', 'vdelay', '-', 'vt_hold', ';',
-                'end',
-            'd_internal', '=', '0', ';',
-            'clk_internal', '=', '0', ';',
-            'last_clk_time', '=', '0', ';',
-            'd_state', '=', '0', ';',
-            'd_set', '=', '0', ';',
-            'out', '=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'd', ')',
-         'd_internal', '<=', '#', '(', 'data_delay', ')', 'd',
-          ';',
-       'always',
-        '@', '(', 'posedge', 'clk', ')',
-         'clk_internal', '<=', '#', '(', 'clk_delay', ')', 'clk',
-          ';',
-       'always',
-        '@', '(', 'posedge', 'd_internal', ')',
-         'begin',
-           'd_state', '<=', 'd_state', '|', "1 'b x", ';',
-             'if',
-              '(', 'd_internal', '===', '1', ')',
-                'd_set',
-                  '<=',
-                  '#', '(', 'vt_hold', '+', 'vt_setup', ')',
-                  '1',
-                ';',
-            'd_internal', '<=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'd_set', ')',
-         'begin',
-            'if',
-               '(',
-                '$stime',
-                '-',
-                'last_clk_time',
-                '>=',
-                'vt_hold',
-                '+',
-                'vt_setup',
-                ')',
-              'd_state', '=', '1', ';',
-              'else',
-               'begin',
-                 'd_state', '=', "1 'b x", ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Violation of hold/setup time in module %m.\\n"',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Input D pulse at %0d,"',
-                    '$stime',
-                    '-',
-                    'data_delay',
-                    '-',
-                    'vt_hold',
-                    '-',
-                    'vt_setup',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"\\tClock pulse at %0d.\\n"',
-                    'last_clk_time',
-                    '-',
-                    'clk_delay',
-                    ')',
-                    ';',
-                'end',
-            'd_set', '<=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'clk_internal', ')',
-         'begin',
-            'if',
-              '(', 'clk_internal', '===', "1 'b x", ')',
-              'out_value', '=', "1 'b x", ';',
-              'else',
-              'out_value', '=', 'd_state', ';',
-             'out', '<=', '#', '(', 'out_delay', ')', 'out_value',
-              ';',
-             'out', '<=', '#', '(', 'out_delay', '+', '2', ')', '0',
-              ';',
-            'd_state', '<=', '0', ';',
-            'clk_internal', '<=', '0', ';',
-            'last_clk_time', '=', '$stime', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/dro_cell.v.parsed.txt Deleted

@@ -1,337 +0,0 @@
-// Verilog HDL for "RSFQ.lib", "dro_cell" "_functional"
-
-// Module DRO cell
-module dro_cell (d, clk, out);
-
-input
-	d, clk;
-
-output
-	out;
-reg 
-	out;
-
-parameter
-	t_hold	= -3,
-	t_setup	= 8,
-	delay	= 9,
-
-// multichannel description of a warning file
-	warning_file=2,  
-// multichannel description of a delay file
-	delay_file = warning_file<<1;
-
-reg
-	d_internal, clk_internal,
-	d_state,          	   // internal state at the input d
-	d_set;		   	   // signal determining the moment when
-				   // the state of the d input changes to "1"
-
-integer
-	data_delay,  // delay between d and d_internal
-	clk_delay,   // delay between clk and clk_internal
-	out_delay,   // delay between clk_internal and out
-	out_value,   // output value in a given clock cycle
-	last_clk_time,	// time when the last clock pulse appeared
-	vt_hold,	// variable hold
-	vt_setup,	// variable setup
-	vdelay;		// variable delay
-
-`include "INIT"
-
-`ifdef RANDOM_DELAYS
- `include "RANDOM_GATE"
-`endif
-
-initial 
-	begin
-		vt_hold = t_hold;
-		vt_setup = t_setup;
-		vdelay = delay;
-
-`ifdef RANDOM_DELAYS
-		delay_dev = dro_cell_variation*delay;
-		vdelay = $dist_normal(dro_cell_seed, delay, delay_dev);
-		vt_hold = $dist_normal(dro_cell_seed, t_hold, dro_hs_dev);
-		vt_setup = t_setup + (t_hold - vt_hold);
-`endif
-
-		#1 $fdisplay(delay_file, "module=%m, nom_delay=%0d, delay=%0d", delay, vdelay);
-		#1 $fdisplay(delay_file, "module=%m, nom_hold=%0d, hold=%0d", t_hold, vt_hold);
-		#1 $fdisplay(delay_file, "module=%m, nom_setup=%0d, setup=%0d", t_setup, vt_setup);
-
-
-// define delays between inputs & outputs and the corresponding
-//  internal auxiliary registers
-	  	if(vt_hold<0)
-		  begin
-	    	  	data_delay = -vt_hold;
-	    		clk_delay  = 0;
-			out_delay  = vdelay;
-		  end
-	  	else
-		  begin
-	   	  	data_delay = 0;
-	    		clk_delay  = vt_hold;
-		  	out_delay  = vdelay-vt_hold;
-		  end
-
-// clear internal registers and the output signal
-		d_internal = 0;
-		clk_internal = 0;
-		last_clk_time = 0;
-		d_state = 0;
-		d_set = 0;
-		out = 0;
-	end
-
-
-
-always @(posedge d) 	// Execute at positive edge of d
-	  d_internal <= #(data_delay) d;
-
-always @(posedge clk)  // Execute at positive edge of clk
-	  clk_internal <= #(clk_delay) clk;
-
-
-always @(posedge d_internal)
-	begin
-// setting the state of the d input
-                d_state <= d_state | 1'bx;
-		if (d_internal === 1)
-		  d_set <= #(vt_hold+vt_setup) 1;
-
-		d_internal <= 0;
-	end
-
-always @(posedge d_set)
-	begin
-		if ($stime - last_clk_time >= vt_hold+vt_setup)
-			d_state = 1;
-		else
-		  begin
-			d_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input D pulse at %0d,",
-			 $stime-data_delay-vt_hold-vt_setup);
-			$fwrite(warning_file,
-			"\tClock pulse at %0d.\n", last_clk_time-clk_delay);
-		  end
-
-		d_set <= 0;
-	end
-
-
-always @(posedge clk_internal)	
-	begin
-// computing the output
-		if (clk_internal === 1'bx)
-		  out_value = 1'bx;
-		else
-		  out_value = d_state;
-
-// transfering the result to the output
-		out <= #(out_delay) out_value;
-		out <= #(out_delay+2) 0;
-
-// clearing the internal state of the DRO
-		d_state  <= 0;
-
-		clk_internal <= 0;
-		last_clk_time = $stime;
-	end
-
-endmodule
-
-
-  'module', 'dro_cell', '(', 'd', 'clk', 'out', ')', ';',
-     'input', 'd', 'clk', ';',
-      'output', 'out', ';',
-      'reg', 'out', ';',
-       'parameter',
-        't_hold', '=', '-', '3',
-        't_setup', '=', '8',
-        'delay', '=', '9',
-        'warning_file', '=', '2',
-        'delay_file', '=', 'warning_file', '<<', '1',
-        ';',
-      'reg', 'd_internal', 'clk_internal', 'd_state', 'd_set', ';',
-       'integer',
-        'data_delay',
-        'clk_delay',
-        'out_delay',
-        'out_value',
-        'last_clk_time',
-        'vt_hold',
-        'vt_setup',
-        'vdelay',
-        ';',
-       'initial',
-         'begin',
-           'vt_hold', '=', 't_hold', ';',
-            'vt_setup', '=', 't_setup', ';',
-            'vdelay', '=', 'delay', ';',
-            'delay_dev', '=', 'dro_cell_variation', '*', 'delay', ';',
-              'vdelay',
-                '=',
-                 '$dist_normal',
-                  '(',
-                  'dro_cell_seed',
-                  'delay',
-                  'delay_dev',
-                  ')',
-              ';',
-              'vt_hold',
-                '=',
-                 '$dist_normal',
-                  '(',
-                  'dro_cell_seed',
-                  't_hold',
-                  'dro_hs_dev',
-                  ')',
-              ';',
-              'vt_setup',
-                '=',
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-                '+',
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-                't_hold', '-', 'vt_hold',
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-              ';',
-            'd_state', '<=', '0', ';',
-            'clk_internal', '<=', '0', ';',
-            'last_clk_time', '=', '$stime', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/dump_and_fill_mem_test.v.parsed.txt Deleted

@@ -1,365 +0,0 @@
-/**********************************************************************
- * $dump_mem_hex and $fill_mem example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $dump_mem_hex, $dump_mem_ascii
- * and $fill_mem PLI applications.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns 
-module dump_mem_test;
-
-  parameter LEFT_BIT = 23, RIGHT_BIT = 00, FIRST_ADDR = 0, LAST_ADDR = 3;
-//  parameter LEFT_BIT = 00, RIGHT_BIT = 23, FIRST_ADDR = 0, LAST_ADDR = 3;
-//  parameter LEFT_BIT = 23, RIGHT_BIT = 00, FIRST_ADDR = 3, LAST_ADDR = 0;
-//  parameter LEFT_BIT = 00, RIGHT_BIT = 23, FIRST_ADDR = 3, LAST_ADDR = 0;
-//  parameter LEFT_BIT = 24, RIGHT_BIT = 01, FIRST_ADDR = 0, LAST_ADDR = 3;
-//  parameter LEFT_BIT = 01, RIGHT_BIT = 24, FIRST_ADDR = 0, LAST_ADDR = 3;
-//  parameter LEFT_BIT = 23, RIGHT_BIT = 00, FIRST_ADDR = 1, LAST_ADDR = 4;
-//  parameter LEFT_BIT = 23, RIGHT_BIT = 00, FIRST_ADDR = 4, LAST_ADDR = 1;
-
-  reg  LEFT_BIT:RIGHT_BIT RAM FIRST_ADDR:LAST_ADDR;
-
-  integer addr;
-  wire 23:0 vector1, vector2;
-
-  initial
-    begin
-      $display("Loading memory from Verilog HDL...\n");
-      fill_mem("Hello world!");
-      #1 dump_mem_hex;
-      #1 dump_mem_ascii;
-      $display("Accessing memory using $dump_mem...\n");
-      $dump_mem_hex(RAMFIRST_ADDR); /* address ignored by PLI */
-      $dump_mem_ascii(RAMFIRST_ADDR);
-
-      $display("\nModifying memory using $fill_mem...\n");
-      $fill_mem(RAMFIRST_ADDR, FIRST_ADDR);
-      #1 dump_mem_hex;
-      $dump_mem_hex(RAMFIRST_ADDR);
-      #10 $finish;
-    end
-
-  assign vector1 = RAMFIRST_ADDR;
-  always @(vector1)
-    $display("\nRAM%0d just changed to %h\n", FIRST_ADDR, RAMFIRST_ADDR);
-
-  assign vector2 = RAMLAST_ADDR;
-  always @(vector2)
-    $display("\nRAM%0d just changed to %h\n", LAST_ADDR, RAMLAST_ADDR);
-
-
-  task dump_mem_ascii;
-    begin
-      $write("Within Verilog:\n Memory contents in ASCII are:\n   ");
-      if (FIRST_ADDR < LAST_ADDR)
-        for (addr=FIRST_ADDR; addr<=LAST_ADDR; addr=addr+1)
-          $write("%s", RAMaddr);
-      else
-        for (addr=FIRST_ADDR; addr>=LAST_ADDR; addr=addr-1)
-          $write("%s", RAMaddr);
-      $display("\n");           //terminate dump string
-    end
-  endtask
-
-  task dump_mem_hex;
-    begin
-      $display("Within Verilog:\n Memory contents in hex are:");
-      if (FIRST_ADDR < LAST_ADDR)
-        for (addr=FIRST_ADDR; addr<=LAST_ADDR; addr=addr+1)
-          $display("   address %0d:\t %h", addr, RAMaddr);
-      else
-        for (addr=FIRST_ADDR; addr>=LAST_ADDR; addr=addr-1)
-          $display("   address %0d:\t %h", addr, RAMaddr);
-    end
-  endtask
-
-  task fill_mem; /* assumes at least 4 words, each word at least 24 bits wide */
-    input (20*8)-1:0 string; /* input for 20 ASCII characters */
-    begin
-      if (FIRST_ADDR < LAST_ADDR)
-        begin
-          if (   (LEFT_BIT - RIGHT_BIT) !== 23
-              && (RIGHT_BIT - LEFT_BIT) !== 23 )
-            disable fill_mem;  /* abort if word is not 24 bits wide */
-          RAMFIRST_ADDR+3 = string23: 0;
-          RAMFIRST_ADDR+2 = string47:24;
-          RAMFIRST_ADDR+1 = string71:48;
-          RAMFIRST_ADDR+0 = string95:72;
-        end
-      else
-        begin
-          if (   (LEFT_BIT - RIGHT_BIT) !== 23
-              && (RIGHT_BIT - LEFT_BIT) !== 23 )
-            disable fill_mem;  /* abort if word is not 24 bits wide */
-          RAMFIRST_ADDR-3 = string23: 0;
-          RAMFIRST_ADDR-2 = string47:24;
-          RAMFIRST_ADDR-1 = string71:48;
-          RAMFIRST_ADDR-0 = string95:72;
-        end
-    end
-  endtask
-
-endmodule
-
-
-  'module', 'dump_mem_test', ';',
-      'parameter',
-        'LEFT_BIT', '=', '23',
-        'RIGHT_BIT', '=', '00',
-        'FIRST_ADDR', '=', '0',
-        'LAST_ADDR', '=', '3',
-        ';',
-       'reg',
-        '',
-        'LEFT_BIT',
-        ':',
-        'RIGHT_BIT',
-        '',
-        'RAM', '', 'FIRST_ADDR', ':', 'LAST_ADDR', '',
-        ';',
-      'integer', 'addr', ';',
-      'wire', '', '23', ':', '0', '', 'vector1', 'vector2', ';',
-       'initial',
-         'begin',
-            '$display',
-              '(',
-              '"Loading memory from Verilog HDL...\\n"',
-              ')',
-              ';',
-            'fill_mem', '(', '"Hello world!"', ')', ';',
-            '#', '1', 'dump_mem_hex', ';',
-            '#', '1', 'dump_mem_ascii', ';',
-             '$display',
-              '(',
-              '"Accessing memory using $dump_mem...\\n"',
-              ')',
-              ';',
-             '$dump_mem_hex',
-              '(',
-              'RAM', '', 'FIRST_ADDR', '',
-              ')',
-              ';',
-             '$dump_mem_ascii',
-              '(',
-              'RAM', '', 'FIRST_ADDR', '',
-              ')',
-              ';',
-             '$display',
-              '(',
-              '"\\nModifying memory using $fill_mem...\\n"',
-              ')',
-              ';',
-             '$fill_mem',
-              '(',
-              'RAM', '', 'FIRST_ADDR', '',
-              'FIRST_ADDR',
-              ')',
-              ';',
-            '#', '1', 'dump_mem_hex', ';',
-             '$dump_mem_hex',
-              '(',
-              'RAM', '', 'FIRST_ADDR', '',
-              ')',
-              ';',
-            '#', '10', '$finish', ';',
-          'end',
-      'assign', 'vector1', '=', 'RAM', '', 'FIRST_ADDR', '', ';',
-       'always',
-        '@', '(', 'vector1', ')',
-         '$display',
-          '(',
-          '"\\nRAM%0d just changed to %h\\n"',
-          'FIRST_ADDR',
-          'RAM', '', 'FIRST_ADDR', '',
-          ')',
-          ';',
-      'assign', 'vector2', '=', 'RAM', '', 'LAST_ADDR', '', ';',
-       'always',
-        '@', '(', 'vector2', ')',
-         '$display',
-          '(',
-          '"\\nRAM%0d just changed to %h\\n"',
-          'LAST_ADDR',
-          'RAM', '', 'LAST_ADDR', '',
-          ')',
-          ';',
-       'task',
-        'dump_mem_ascii',
-        ';',
-         'begin',
-            '$write',
-              '(',
-              '"Within Verilog:\\n Memory contents in ASCII are:\\n   "',
-              ')',
-              ';',
-             'if',
-              '(', 'FIRST_ADDR', '<', 'LAST_ADDR', ')',
-               'for',
-                '(',
-                'addr', '=', 'FIRST_ADDR',
-                ';',
-                'addr', '<=', 'LAST_ADDR',
-                ';',
-                'addr', '=', 'addr', '+', '1',
-                ')',
-                 '$write',
-                  '(',
-                  '"%s"',
-                  'RAM', '', 'addr', '',
-                  ')',
-                  ';',
-              'else',
-               'for',
-                '(',
-                'addr', '=', 'FIRST_ADDR',
-                ';',
-                'addr', '>=', 'LAST_ADDR',
-                ';',
-                'addr', '=', 'addr', '-', '1',
-                ')',
-                 '$write',
-                  '(',
-                  '"%s"',
-                  'RAM', '', 'addr', '',
-                  ')',
-                  ';',
-            '$display', '(', '"\\n"', ')', ';',
-          'end',
-        'endtask',
-       'task',
-        'dump_mem_hex',
-        ';',
-         'begin',
-            '$display',
-              '(',
-              '"Within Verilog:\\n Memory contents in hex are:"',
-              ')',
-              ';',
-             'if',
-              '(', 'FIRST_ADDR', '<', 'LAST_ADDR', ')',
-               'for',
-                '(',
-                'addr', '=', 'FIRST_ADDR',
-                ';',
-                'addr', '<=', 'LAST_ADDR',
-                ';',
-                'addr', '=', 'addr', '+', '1',
-                ')',
-                 '$display',
-                  '(',
-                  '"   address %0d:\\t %h"',
-                  'addr',
-                  'RAM', '', 'addr', '',
-                  ')',
-                  ';',
-              'else',
-               'for',
-                '(',
-                'addr', '=', 'FIRST_ADDR',
-                ';',
-                'addr', '>=', 'LAST_ADDR',
-                ';',
-                'addr', '=', 'addr', '-', '1',
-                ')',
-                 '$display',
-                  '(',
-                  '"   address %0d:\\t %h"',
-                  'addr',
-                  'RAM', '', 'addr', '',
-                  ')',
-                  ';',
-          'end',
-        'endtask',
-       'task',
-        'fill_mem',
-        ';',
-         'input',
-          '',
-          '(',
-          '20', '*', '8',
-          ')',
-          '-',
-          '1',
-          ':',
-          '0',
-          '',
-          'string',
-          ';',
-         'begin',
-            'if',
-              '(', 'FIRST_ADDR', '<', 'LAST_ADDR', ')',
-               'begin',
-                  'if',
-                     '(',
-                      '(',
-                      'LEFT_BIT', '-', 'RIGHT_BIT',
-                      ')',
-                      '!==',
-                      '23',
-                      '&&',
-                      '(',
-                      'RIGHT_BIT', '-', 'LEFT_BIT',
-                      ')',
-                      '!==',
-                      '23',
-                      ')',
-                    'disable', 'fill_mem', ';',
-                    'RAM', '', 'FIRST_ADDR', '+', '3', '',
-                      '=',
-                      'string', '', '23', '0', '',
-                    ';',
-                    'RAM', '', 'FIRST_ADDR', '+', '2', '',
-                      '=',
-                      'string', '', '47', '24', '',
-                    ';',
-                    'RAM', '', 'FIRST_ADDR', '+', '1', '',
-                      '=',
-                      'string', '', '71', '48', '',
-                    ';',
-                    'RAM', '', 'FIRST_ADDR', '+', '0', '',
-                      '=',
-                      'string', '', '95', '72', '',
-                    ';',
-                'end',
-              'else',
-               'begin',
-                  'if',
-                     '(',
-                      '(',
-                      'LEFT_BIT', '-', 'RIGHT_BIT',
-                      ')',
-                      '!==',
-                      '23',
-                      '&&',
-                      '(',
-                      'RIGHT_BIT', '-', 'LEFT_BIT',
-                      ')',
-                      '!==',
-                      '23',
-                      ')',
-                    'disable', 'fill_mem', ';',
-                    'RAM', '', 'FIRST_ADDR', '-', '3', '',
-                      '=',
-                      'string', '', '23', '0', '',
-                    ';',
-                    'RAM', '', 'FIRST_ADDR', '-', '2', '',
-                      '=',
-                      'string', '', '47', '24', '',
-                    ';',
-                    'RAM', '', 'FIRST_ADDR', '-', '1', '',
-                      '=',
-                      'string', '', '71', '48', '',
-                    ';',
-                    'RAM', '', 'FIRST_ADDR', '-', '0', '',
-                      '=',
-                      'string', '', '95', '72', '',
-                    ';',
-                'end',
-          'end',
-        'endtask',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/exprinfo_test.v.parsed.txt Deleted

@@ -1,69 +0,0 @@
-/**********************************************************************
- * $exprinfo_test example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $exprinfo_test PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-  reg        reg1;
-  reg 31:0 reg2;
-  reg 0:51 reg3;
-  real       r1;
-
-  initial
-    begin
-      reg1 = 1'b0;
-      reg2 = 32'hF0F0F0F0;
-      reg3 = {13{4'b01zx}};
-      r1   = 3.1415;
-
-      #1 $exprinfo_test("Hello world");
-      #1 $exprinfo_test(r1);
-      #1 $exprinfo_test(reg1);
-      #1 $exprinfo_test(reg2);
-      #1 $exprinfo_test(reg3);
-      #1 $exprinfo_test(reg31);
-      #1 $exprinfo_test(reg34:48);
-
-      #1 $finish;
-    end
-
-endmodule
-
-/**********************************************************************/
-
-
-
-  'module', 'test', ';',
-     'reg', 'reg1', ';',
-      'reg', '', '31', ':', '0', '', 'reg2', ';',
-      'reg', '', '0', ':', '51', '', 'reg3', ';',
-      'real', 'r1', ';',
-       'initial',
-         'begin',
-           'reg1', '=', "1 'b 0", ';',
-            'reg2', '=', "32 'h F0F0F0F0", ';',
-            'reg3', '=', '{', '13', '{', "4 'b 01zx", '}', '}', ';',
-            'r1', '=', '3.1415', ';',
-            '#', '1', '$exprinfo_test', '(', '"Hello world"', ')', ';',
-            '#', '1', '$exprinfo_test', '(', 'r1', ')', ';',
-            '#', '1', '$exprinfo_test', '(', 'reg1', ')', ';',
-            '#', '1', '$exprinfo_test', '(', 'reg2', ')', ';',
-            '#', '1', '$exprinfo_test', '(', 'reg3', ')', ';',
-             '#', '1',
-              '$exprinfo_test', '(', 'reg3', '', '1', '', ')', ';',
-             '#', '1',
-               '$exprinfo_test',
-                '(',
-                'reg3', '', '4', '48', '',
-                ')',
-                ';',
-            '#', '1', '$finish', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/fetch_values_test.v.parsed.txt Deleted

@@ -1,43 +0,0 @@
-/**********************************************************************
- * $test_acc_fetch_value example -- Verilog test bench source code
- *
- * Verilog test bench to test the $test_acc_fetch_value PLI application
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module top;
-  reg  15:0 reg1;
-  real        real1;
-
-  initial
-    begin
-      reg1  = "Hi";
-      real1 = 3.1415;
-
-      #1 $test_acc_fetch_value(reg1);
-//      #1 $test_acc_fetch_value(real1);
-
-      #10 $finish;
-    end
-endmodule
-
-/*********************************************************************/
-
-
-
-  'module', 'top', ';',
-     'reg', '', '15', ':', '0', '', 'reg1', ';',
-      'real', 'real1', ';',
-       'initial',
-         'begin',
-           'reg1', '=', '"Hi"', ';',
-            'real1', '=', '3.1415', ';',
-            '#', '1', '$test_acc_fetch_value', '(', 'reg1', ')', ';',
-            '#', '10', '$finish', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/ff.v.parsed.txt Deleted

@@ -1,47 +0,0 @@
-module ff (clk, D, E, R_, Q, Q_) ; 
-  input clk ; 
-  input D ; 
-  input E ; 
-  input R_ ; 
-  output Q ; 
-  output Q_ ; 
-  reg Q ; 
-  initial begin 
-    Q = 0 ; 
-  end 
-
-  assign Q_ = ~Q ; 
-
-  always @( R_ ) if( R_ === 0 ) #1 Q = 0 ; 
-
-  always @(posedge clk) if (R_ !== 0 && E === 1 ) #1 Q = D ; 
-
-endmodule
-
-
-   'module',
-      'ff',
-      '(',
-      'clk', 'D', 'E', 'R_', 'Q', 'Q_',
-      ')',
-      ';',
-     'input', 'clk', ';',
-      'input', 'D', ';',
-      'input', 'E', ';',
-      'input', 'R_', ';',
-      'output', 'Q', ';',
-      'output', 'Q_', ';',
-      'reg', 'Q', ';',
-      'initial', 'begin', 'Q', '=', '0', ';', 'end',
-      'assign', 'Q_', '=', '~', 'Q', ';',
-       'always',
-        '@', '(', 'R_', ')',
-         'if',
-          '(', 'R_', '===', '0', ')',
-          '#', '1', 'Q', '=', '0', ';',
-       'always',
-        '@', '(', 'posedge', 'clk', ')',
-         'if',
-          '(', 'R_', '!==', '0', '&&', 'E', '===', '1', ')',
-          '#', '1', 'Q', '=', 'D', ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/ff_test.v.parsed.txt Deleted

@@ -1,91 +0,0 @@
-////////////////////////////////////////////////////// 
-// verilog testbench for module ff 
-//   created by jedatemp 
-////////////////////////////////////////////////////// 
-module ff_test ; 
-  parameter simulation_cycle = 100 ; 
-  wire CLOCK ; 
-  reg CLOCK_reg ; 
-  assign CLOCK = CLOCK_reg ; 
-  wire   ff_clk ; 
-  wire   ff_D ; 
-  wire   ff_E ; 
-  wire   ff_R_ ; 
-  wire   ff_Q ; 
-  wire   ff_Q_ ; 
-  assign ff_clk = CLOCK ; 
-  // Jeda module 
-  jeda_module jeda ( 
-    .CLOCK(CLOCK), 
-    .ff_clk(ff_clk), 
-    .ff_D(ff_D), 
-    .ff_E(ff_E), 
-    .ff_R_(ff_R_), 
-    .ff_Q(ff_Q), 
-    .ff_Q_(ff_Q_) 
-  ) ; // end of jeda_module 
-  // module ff under test 
-  ff dut ( 
-    .clk(ff_clk), 
-    .D(ff_D), 
-    .E(ff_E), 
-    .R_(ff_R_), 
-    .Q(ff_Q), 
-    .Q_(ff_Q_) 
-  ) ; 
-  // CLOCK toggling 
-  initial begin 
-    CLOCK_reg = 0 ; 
-    forever begin 
-      #(simulation_cycle/2) CLOCK_reg = ~CLOCK_reg ; 
-    end 
-  end 
-
-endmodule 
-
-
-  'module', 'ff_test', ';',
-     'parameter', 'simulation_cycle', '=', '100', ';',
-      'wire', 'CLOCK', ';',
-      'reg', 'CLOCK_reg', ';',
-      'assign', 'CLOCK', '=', 'CLOCK_reg', ';',
-      'wire', 'ff_clk', ';',
-      'wire', 'ff_D', ';',
-      'wire', 'ff_E', ';',
-      'wire', 'ff_R_', ';',
-      'wire', 'ff_Q', ';',
-      'wire', 'ff_Q_', ';',
-      'assign', 'ff_clk', '=', 'CLOCK', ';',
-       'jeda_module',
-         'jeda',
-           '(',
-            '.', 'CLOCK', '(', 'CLOCK', ')',
-            '.', 'ff_clk', '(', 'ff_clk', ')',
-            '.', 'ff_D', '(', 'ff_D', ')',
-            '.', 'ff_E', '(', 'ff_E', ')',
-            '.', 'ff_R_', '(', 'ff_R_', ')',
-            '.', 'ff_Q', '(', 'ff_Q', ')',
-            '.', 'ff_Q_', '(', 'ff_Q_', ')',
-            ')',
-        ';',
-       'ff',
-         'dut',
-           '(',
-            '.', 'clk', '(', 'ff_clk', ')',
-            '.', 'D', '(', 'ff_D', ')',
-            '.', 'E', '(', 'ff_E', ')',
-            '.', 'R_', '(', 'ff_R_', ')',
-            '.', 'Q', '(', 'ff_Q', ')',
-            '.', 'Q_', '(', 'ff_Q_', ')',
-            ')',
-        ';',
-       'initial',
-         'begin',
-           'CLOCK_reg', '=', '0', ';',
-             'forever',
-               'begin',
-                  '#', '(', 'simulation_cycle', '/', '2', ')',
-                    'CLOCK_reg', '=', '~', 'CLOCK_reg', ';',
-                'end',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/fifo.v.parsed.txt Deleted

@@ -1,704 +0,0 @@
-// Synchronous FIFO.  4 x 16 bit words.
-//
-module fifo (clk, rstp, din, writep, readp, dout, emptyp, fullp);
-input		clk;
-input		rstp;
-input 15:0	din;
-input		readp;
-input		writep;
-output 15:0	dout;
-output		emptyp;
-output		fullp;
-
-// Defines sizes in terms of bits.
-//
-parameter	DEPTH = 2,		// 2 bits, e.g. 4 words in the FIFO.
-		MAX_COUNT = 2'b11;	// topmost address in FIFO.
-
-reg 		emptyp;
-reg		fullp;
-
-// Registered output.
-reg 15:0	dout;
-
-// Define the FIFO pointers.  A FIFO is essentially a circular queue.
-//
-reg (DEPTH-1):0	tail;
-reg (DEPTH-1):0	head;
-
-// Define the FIFO counter.  Counts the number of entries in the FIFO which
-// is how we figure out things like Empty and Full.
-//
-reg (DEPTH-1):0	count;
-
-// Define our regsiter bank.  This is actually synthesizable!
-//
-reg 15:0 fifomem0:MAX_COUNT;
-
-// Dout is registered and gets the value that tail points to RIGHT NOW.
-//
-always @(posedge clk) begin
-   if (rstp == 1) begin
-      dout <= 16'h0000;
-   end
-   else begin
-      dout <= fifomemtail;
-   end
-end 
-     
-// Update FIFO memory.
-always @(posedge clk) begin
-   if (rstp == 1'b0 && writep == 1'b1 && fullp == 1'b0) begin
-      fifomemhead <= din;
-   end
-end
-                  
-// Update the head register.
-//
-always @(posedge clk) begin
-   if (rstp == 1'b1) begin
-      head <= 2'b00;
-   end
-   else begin
-      if (writep == 1'b1 && fullp == 1'b0) begin
-         // WRITE
-         head <= head + 1;
-      end
-   end
-end
-
-// Update the tail register.
-//
-always @(posedge clk) begin
-   if (rstp == 1'b1) begin
-      tail <= 2'b00;
-   end
-   else begin
-      if (readp == 1'b1 && emptyp == 1'b0) begin
-         // READ               
-         tail <= tail + 1;
-      end
-   end
-end
-
-// Update the count regsiter.
-//
-always @(posedge clk) begin
-   if (rstp == 1'b1) begin
-      count <= 2'b00;
-   end
-   else begin
-      case ({readp, writep})
-         2'b00: count <= count;
-         2'b01: 
-            // WRITE
-            if (count != MAX_COUNT) 
-               count <= count + 1;
-         2'b10: 
-            // READ
-            if (count != 2'b00)
-               count <= count - 1;
-         2'b11:
-            // Concurrent read and write.. no change in count
-            count <= count;
-      endcase
-   end
-end
-
-         
-// *** Update the flags
-//
-// First, update the empty flag.
-//
-always @(count) begin
-   if (count == 2'b00)
-      emptyp <= 1'b1;
-   else
-      emptyp <= 1'b0;
-end
-
-
-// Update the full flag
-//
-always @(count) begin
-   if (count == MAX_COUNT)
-      fullp <= 1'b1;
-   else
-      fullp <= 1'b0;
-end
-
-endmodule
-
-// synopsys translate_off
-
-`define TEST_FIFO
-// synopsys translate_off
-`ifdef TEST_FIFO
-module test_fifo;
-
-reg		clk;
-reg		rstp;
-reg 15:0	din;
-reg		readp;
-reg		writep;
-wire 15:0	dout;
-wire		emptyp;
-wire		fullp;
-
-reg 15:0	value;
-
-fifo U1 (
-   .clk		(clk),
-   .rstp	(rstp),
-   .din		(din),
-   .readp	(readp),
-   .writep	(writep),
-   .dout	(dout),
-   .emptyp	(emptyp),
-   .fullp	(fullp)
-);
-
-task read_word;
-begin
-   @(negedge clk);
-   readp = 1;
-   @(posedge clk) #5;
-   $display ("Read %0h from FIFO", dout);
-   readp = 0;
-end
-endtask
-   
-task write_word;
-input 15:0	value;
-begin
-   @(negedge clk);
-   din = value;
-   writep = 1;
-   @(posedge clk);
-   $display ("Write %0h to FIFO", din);
-   #5;
-   din = 16'hzzzz;
-   writep = 0;
-end
-endtask
-
-initial begin
-   clk = 0;
-   forever begin
-      #10 clk = 1;
-      #10 clk = 0;
-   end
-end
-
-initial begin
-   $shm_open ("./fifo.shm");
-   $shm_probe (test_fifo, "AS");
-   
-   //test1;
-   test2;
-   
-   $shm_close;
-   $finish;
-end
-
-task test1;
-begin
-   din = 16'hzzzz;
-   writep = 0;
-   readp = 0;
-
-   // Reset
-   rstp = 1;
-   #50;
-   rstp = 0;
-   #50;
-   
-   // ** Write 3 values.
-   write_word (16'h1111);
-   write_word (16'h2222);
-   write_word (16'h3333);
-   
-   // ** Read 2 values
-   read_word;
-   read_word;
-   
-   // ** Write one more
-   write_word (16'h4444);
-   
-   // ** Read a bunch of values
-   repeat (6) begin
-      read_word;
-   end
-   
-   // *** Write a bunch more values
-   write_word (16'h0001);
-   write_word (16'h0002);
-   write_word (16'h0003);
-   write_word (16'h0004);
-   write_word (16'h0005);
-   write_word (16'h0006);
-   write_word (16'h0007);
-   write_word (16'h0008);
-
-   // ** Read a bunch of values
-   repeat (6) begin
-      read_word;
-   end
-   
-   $display ("Done TEST1.");
-end
-endtask
-
-// TEST2
-//
-// This test will operate the FIFO in an orderly manner the way it normally works.
-// 2 threads are forked; a reader and a writer.  The writer writes a counter to
-// the FIFO and obeys the fullp flag and delays randomly.  The reader likewise
-// obeys the emptyp flag and reads at random intervals.  The result should be that
-// the reader reads the incrementing counter out of the FIFO.  The empty/full flags
-// should bounce around depending on the random delays.  The writer repeats some
-// fixed number of times and then terminates both threads and kills the sim.
-//
-task test2;
-reg 15:0 writer_counter;
-begin
-   writer_counter = 16'h0001;
-   din = 16'hzzzz;
-   writep = 0;
-   readp = 0;
-
-   // Reset
-   rstp = 1;
-   #50;
-   rstp = 0;
-   #50;
-   
-   fork
-      // Writer
-      begin
-         repeat (500) begin
-            @(negedge clk);
-            if (fullp == 1'b0) begin
-               write_word (writer_counter);
-               #5;
-               writer_counter = writer_counter + 1;
-            end
-            else begin
-               $display ("WRITER is waiting..");
-            end
-            // Delay a random amount of time between 0ns and 100ns
-            #(50 + ($random % 50));
-         end
-         $display ("Done with WRITER fork..");
-         $finish;
-      end
-      
-      // Reader
-      begin
-         forever begin
-            @(negedge clk);
-            if (emptyp == 1'b0) begin
-               read_word;
-            end  
-            else begin
-               $display ("READER is waiting..");
-            end
-            // Delay a random amount of time between 0ns and 100ns
-            #(50 + ($random % 50));
-         end
-      end
-   join
-end
-endtask
-
-always @(fullp)
-   $display ("fullp = %0b", fullp);
-   
-always @(emptyp)
-   $display ("emptyp = %0b", emptyp);
-
-always @(U1.head)
-   $display ("head = %0h", U1.head);
-
-always @(U1.tail)
-   $display ("tail = %0h", U1.tail);
-
-endmodule
-`endif
-
-
-   'module',
-      'fifo',
-      '(',
-       'clk',
-        'rstp',
-        'din',
-        'writep',
-        'readp',
-        'dout',
-        'emptyp',
-        'fullp',
-      ')',
-      ';',
-     'input', 'clk', ';',
-      'input', 'rstp', ';',
-      'input', '', '15', ':', '0', '', 'din', ';',
-      'input', 'readp', ';',
-      'input', 'writep', ';',
-      'output', '', '15', ':', '0', '', 'dout', ';',
-      'output', 'emptyp', ';',
-      'output', 'fullp', ';',
-      'parameter', 'DEPTH', '=', '2', 'MAX_COUNT', '=', "2 'b 11", ';',
-      'reg', 'emptyp', ';',
-      'reg', 'fullp', ';',
-      'reg', '', '15', ':', '0', '', 'dout', ';',
-       'reg',
-        '',
-        '(',
-        'DEPTH', '-', '1',
-        ')',
-        ':',
-        '0',
-        '',
-        'tail',
-        ';',
-       'reg',
-        '',
-        '(',
-        'DEPTH', '-', '1',
-        ')',
-        ':',
-        '0',
-        '',
-        'head',
-        ';',
-       'reg',
-        '',
-        '(',
-        'DEPTH', '-', '1',
-        ')',
-        ':',
-        '0',
-        '',
-        'count',
-        ';',
-       'reg',
-        '',
-        '15',
-        ':',
-        '0',
-        '',
-        'fifomem', '', '0', ':', 'MAX_COUNT', '',
-        ';',
-       'always',
-        '@', '(', 'posedge', 'clk', ')',
-         'begin',
-            'if',
-              '(', 'rstp', '==', '1', ')',
-              'begin', 'dout', '<=', "16 'h 0000", ';', 'end',
-              'else',
-               'begin',
-                'dout', '<=', 'fifomem', '', 'tail', '', ';',
-                'end',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'clk', ')',
-         'begin',
-            'if',
-               '(',
-                'rstp',
-                '==',
-                "1 'b 0",
-                '&&',
-                'writep',
-                '==',
-                "1 'b 1",
-                '&&',
-                'fullp',
-                '==',
-                "1 'b 0",
-                ')',
-               'begin',
-                'fifomem', '', 'head', '', '<=', 'din', ';',
-                'end',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'clk', ')',
-         'begin',
-            'if',
-              '(', 'rstp', '==', "1 'b 1", ')',
-              'begin', 'head', '<=', "2 'b 00", ';', 'end',
-              'else',
-               'begin',
-                  'if',
-                     '(',
-                      'writep',
-                      '==',
-                      "1 'b 1",
-                      '&&',
-                      'fullp',
-                      '==',
-                      "1 'b 0",
-                      ')',
-                     'begin',
-                      'head', '<=', 'head', '+', '1', ';',
-                      'end',
-                'end',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'clk', ')',
-         'begin',
-            'if',
-              '(', 'rstp', '==', "1 'b 1", ')',
-              'begin', 'tail', '<=', "2 'b 00", ';', 'end',
-              'else',
-               'begin',
-                  'if',
-                     '(',
-                      'readp',
-                      '==',
-                      "1 'b 1",
-                      '&&',
-                      'emptyp',
-                      '==',
-                      "1 'b 0",
-                      ')',
-                     'begin',
-                      'tail', '<=', 'tail', '+', '1', ';',
-                      'end',
-                'end',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'clk', ')',
-         'begin',
-            'if',
-              '(', 'rstp', '==', "1 'b 1", ')',
-              'begin', 'count', '<=', "2 'b 00", ';', 'end',
-              'else',
-               'begin',
-                  'case',
-                    '(',
-                    '{', 'readp', 'writep', '}',
-                    ')',
-                    "2 'b 00",
-                    ':',
-                    'count', '<=', 'count', ';',
-                    "2 'b 01",
-                    ':',
-                     'if',
-                      '(', 'count', '!=', 'MAX_COUNT', ')',
-                      'count', '<=', 'count', '+', '1', ';',
-                    "2 'b 10",
-                    ':',
-                     'if',
-                      '(', 'count', '!=', "2 'b 00", ')',
-                      'count', '<=', 'count', '-', '1', ';',
-                    "2 'b 11",
-                    ':',
-                    'count', '<=', 'count', ';',
-                    'endcase',
-                'end',
-          'end',
-       'always',
-        '@', '(', 'count', ')',
-         'begin',
-            'if',
-              '(', 'count', '==', "2 'b 00", ')',
-              'emptyp', '<=', "1 'b 1", ';',
-              'else',
-              'emptyp', '<=', "1 'b 0", ';',
-          'end',
-       'always',
-        '@', '(', 'count', ')',
-         'begin',
-            'if',
-              '(', 'count', '==', 'MAX_COUNT', ')',
-              'fullp', '<=', "1 'b 1", ';',
-              'else',
-              'fullp', '<=', "1 'b 0", ';',
-          'end',
-    'endmodule',
-   'module', 'test_fifo', ';',
-     'reg', 'clk', ';',
-      'reg', 'rstp', ';',
-      'reg', '', '15', ':', '0', '', 'din', ';',
-      'reg', 'readp', ';',
-      'reg', 'writep', ';',
-      'wire', '', '15', ':', '0', '', 'dout', ';',
-      'wire', 'emptyp', ';',
-      'wire', 'fullp', ';',
-      'reg', '', '15', ':', '0', '', 'value', ';',
-       'fifo',
-         'U1',
-           '(',
-            '.', 'clk', '(', 'clk', ')',
-            '.', 'rstp', '(', 'rstp', ')',
-            '.', 'din', '(', 'din', ')',
-            '.', 'readp', '(', 'readp', ')',
-            '.', 'writep', '(', 'writep', ')',
-            '.', 'dout', '(', 'dout', ')',
-            '.', 'emptyp', '(', 'emptyp', ')',
-            '.', 'fullp', '(', 'fullp', ')',
-            ')',
-        ';',
-       'task',
-        'read_word',
-        ';',
-         'begin',
-           '@', '(', 'negedge', 'clk', ')', ';',
-            'readp', '=', '1', ';',
-            '@', '(', 'posedge', 'clk', ')', '#', '5', ';',
-            '$display', '(', '"Read %0h from FIFO"', 'dout', ')', ';',
-            'readp', '=', '0', ';',
-          'end',
-        'endtask',
-       'task',
-        'write_word',
-        ';',
-        'input', '', '15', ':', '0', '', 'value', ';',
-         'begin',
-           '@', '(', 'negedge', 'clk', ')', ';',
-            'din', '=', 'value', ';',
-            'writep', '=', '1', ';',
-            '@', '(', 'posedge', 'clk', ')', ';',
-            '$display', '(', '"Write %0h to FIFO"', 'din', ')', ';',
-            '#', '5', ';',
-            'din', '=', "16 'h zzzz", ';',
-            'writep', '=', '0', ';',
-          'end',
-        'endtask',
-       'initial',
-         'begin',
-           'clk', '=', '0', ';',
-             'forever',
-               'begin',
-                 '#', '10', 'clk', '=', '1', ';',
-                  '#', '10', 'clk', '=', '0', ';',
-                'end',
-          'end',
-       'initial',
-         'begin',
-           '$shm_open', '(', '"./fifo.shm"', ')', ';',
-            '$shm_probe', '(', 'test_fifo', '"AS"', ')', ';',
-            'test2', ';',
-            '$shm_close', ';',
-            '$finish', ';',
-          'end',
-       'task',
-        'test1',
-        ';',
-         'begin',
-           'din', '=', "16 'h zzzz", ';',
-            'writep', '=', '0', ';',
-            'readp', '=', '0', ';',
-            'rstp', '=', '1', ';',
-            '#', '50', ';',
-            'rstp', '=', '0', ';',
-            '#', '50', ';',
-            'write_word', '(', "16 'h 1111", ')', ';',
-            'write_word', '(', "16 'h 2222", ')', ';',
-            'write_word', '(', "16 'h 3333", ')', ';',
-            'read_word', ';',
-            'read_word', ';',
-            'write_word', '(', "16 'h 4444", ')', ';',
-            'repeat', '(', '6', ')', 'begin', 'read_word', ';', 'end',
-            'write_word', '(', "16 'h 0001", ')', ';',
-            'write_word', '(', "16 'h 0002", ')', ';',
-            'write_word', '(', "16 'h 0003", ')', ';',
-            'write_word', '(', "16 'h 0004", ')', ';',
-            'write_word', '(', "16 'h 0005", ')', ';',
-            'write_word', '(', "16 'h 0006", ')', ';',
-            'write_word', '(', "16 'h 0007", ')', ';',
-            'write_word', '(', "16 'h 0008", ')', ';',
-            'repeat', '(', '6', ')', 'begin', 'read_word', ';', 'end',
-            '$display', '(', '"Done TEST1."', ')', ';',
-          'end',
-        'endtask',
-       'task',
-        'test2',
-        ';',
-        'reg', '', '15', ':', '0', '', 'writer_counter', ';',
-         'begin',
-           'writer_counter', '=', "16 'h 0001", ';',
-            'din', '=', "16 'h zzzz", ';',
-            'writep', '=', '0', ';',
-            'readp', '=', '0', ';',
-            'rstp', '=', '1', ';',
-            '#', '50', ';',
-            'rstp', '=', '0', ';',
-            '#', '50', ';',
-             'fork',
-               'begin',
-                  'repeat',
-                    '(',
-                    '500',
-                    ')',
-                     'begin',
-                       '@', '(', 'negedge', 'clk', ')', ';',
-                         'if',
-                          '(', 'fullp', '==', "1 'b 0", ')',
-                           'begin',
-                             'write_word', '(', 'writer_counter', ')', ';',
-                              '#', '5', ';',
-                                'writer_counter',
-                                  '=',
-                                  'writer_counter',
-                                  '+',
-                                  '1',
-                                ';',
-                            'end',
-                          'else',
-                           'begin',
-                              '$display',
-                                '(',
-                                '"WRITER is waiting.."',
-                                ')',
-                                ';',
-                            'end',
-                          '#',
-                            '(',
-                            '50', '+', '(', '$random', '%', '50', ')',
-                            ')',
-                          ';',
-                      'end',
-                  '$display', '(', '"Done with WRITER fork.."', ')', ';',
-                  '$finish', ';',
-                'end',
-               'begin',
-                  'forever',
-                     'begin',
-                       '@', '(', 'negedge', 'clk', ')', ';',
-                         'if',
-                          '(', 'emptyp', '==', "1 'b 0", ')',
-                          'begin', 'read_word', ';', 'end',
-                          'else',
-                           'begin',
-                              '$display',
-                                '(',
-                                '"READER is waiting.."',
-                                ')',
-                                ';',
-                            'end',
-                          '#',
-                            '(',
-                            '50', '+', '(', '$random', '%', '50', ')',
-                            ')',
-                          ';',
-                      'end',
-                'end',
-              'join',
-          'end',
-        'endtask',
-       'always',
-        '@', '(', 'fullp', ')',
-        '$display', '(', '"fullp = %0b"', 'fullp', ')', ';',
-       'always',
-        '@', '(', 'emptyp', ')',
-        '$display', '(', '"emptyp = %0b"', 'emptyp', ')', ';',
-       'always',
-        '@', '(', 'U1.head', ')',
-        '$display', '(', '"head = %0h"', 'U1.head', ')', ';',
-       'always',
-        '@', '(', 'U1.tail', ')',
-        '$display', '(', '"tail = %0h"', 'U1.tail', ')', ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/framer.v.parsed.txt Deleted

@@ -1,800 +0,0 @@
-//
-// Simple example of a "framer".  In this case, an MPEG framer where
-// data is sent in 188-byte frames which begin with a special SYNC character
-// defined as 47 hex.  Framing must, of course, handle cases where 47s
-// happen to also be embedded in the data.  Framer must be able to find
-// the period SYNC characters while not be thrown off by spurious SYNCs.
-//
-// This circuit uses a modulo-188 counter that serves as a timestamp.
-// Every received SYNC character causes the current modulo-188 counter
-// to be pushed onto a little queue.  The idea is that the timestamps
-// should all be the same if the data was perfectly framed.  If spurious
-// false SYNC characters fall in the data, then some of the timestamps
-// will be different.  This is OK as long as there is a clear majority.
-//
-// This circuit is something I started to actually have to do, but then
-// I ended up not using it.  It is not tested, so use it only for ideas
-// and not as a proven circuit!!
-//
-// tom coonan, 12/1999
-//
-module framer (clk, resetb, din, dinstb, dout, doutsync, doutstb, locked);
-input		clk;
-input		resetb;
-input 7:0	din;
-input		dinstb;
-output 7:0	dout;
-output		doutsync;
-output		doutstb;
-output		locked;
-
-parameter SYNC = 8'h47;
-
-reg 7:0	dout;
-reg		doutsync;
-reg		doutstb;
-reg		locked;
-
-/* Internals */
-
-// Free-running Modulo-188 counter
-reg 7:0	cnt188;
-
-// Modulo-188 value when SYNCs are expected once locked.
-reg 7:0	syncindex;
-
-// 6 deep queue of timestamps of every time a SYNC character is received.
-// the timestamp is the value of the modulo-188 counter when a SYNC is received.
-//
-reg 7:0	t0;	// Oldest timestamp
-reg 7:0	t1;
-reg 7:0	t2;
-reg 7:0	t3;
-reg 7:0	t4;
-reg 7:0	t5;	// Newest timestamp
-
-// Modulo-188 free-running counter.
-//
-always @(posedge clk or negedge resetb) begin
-   if (~resetb) begin
-      cnt188 <= 0;
-   end
-   else begin
-      if (dinstb) begin
-         if (cnt188 == 187) begin
-            cnt188 <= 0;
-         end
-         else begin
-            cnt188 <= cnt188 + 1;
-         end
-      end
-   end
-end
-
-// Timestamp queue.
-//
-always @(posedge clk or negedge resetb) begin
-   if (~resetb) begin
-      t0 <= 8'hff;  // Let's use FF as an invalid indicator, otherwise
-      t1 <= 8'hff;  // we'd potentially get a premature lock..
-      t2 <= 8'hff;
-      t3 <= 8'hff;
-      t4 <= 8'hff;
-      t5 <= 8'hff;
-   end
-   else begin
-      if (dinstb && (din == SYNC)) begin
-         // Add new timestamp into our queue.
-         t0 <= t1;   
-         t1 <= t2;   
-         t2 <= t3;   
-         t3 <= t4;   
-         t4 <= t5;   
-         t5 <= cnt188;   
-      end
-   end
-end
-
-// Comparators.
-wire t0equal = (t0 == cnt188) && (t0 != 8'hFF);
-wire t1equal = (t1 == cnt188) && (t1 != 8'hFF);
-wire t2equal = (t2 == cnt188) && (t2 != 8'hFF);
-wire t3equal = (t3 == cnt188) && (t3 != 8'hFF);
-wire t4equal = (t4 == cnt188) && (t4 != 8'hFF);
-wire t5equal = (t5 == cnt188) && (t5 != 8'hFF);
-
-// Count number of matches in all the prior timestamps and current modulo-188 time.
-wire 3:0 numequal = t0equal + t1equal + t2equal + t3equal + t4equal + t5equal;
-
-// Main sequential process.
-//
-always @(posedge clk or negedge resetb) begin
-   if (~resetb) begin
-      locked   <= 0;
-      dout     <= 0;
-      doutstb  <= 0;
-      doutsync <= 0;
-      syncindex <= 0;
-   end
-   else begin
-      doutstb  <= 0;  // defaults..
-      doutsync <= 0;
-      if (dinstb) begin
-         dout    <= din;
-         doutstb <= 1;
-         if (locked) begin
-            if (cnt188 == syncindex) begin
-               // We expect the data input to be a SYNC.  If it is not, we will
-               // immediately drop lock.
-               //
-               if (din == SYNC) begin
-                  $display (".. Received expected SYNC ..");
-                  doutsync <= 1;
-               end
-               else begin
-                  locked   <= 0;
-                  $display (".. Did not receive expected SYNC, dropping lock! ");
-               end
-            end
-         end
-         else begin
-            // The following line is the criteria for declaring LOCK.  It
-            // says that when a SYNC is recieved we look at the current
-            // timestamp, and if this timestamp is present in at least
-            // 4 other times in the queue, than this SYNC is an actual SYNC.
-            //
-            if ((din == SYNC) && (numequal > 3)) begin
-               doutsync <= 1;
-               locked   <= 1;
-               syncindex <= cnt188;
-               $display (".. Received SYNC (cnt188=%0h) and declaring LOCK!", cnt188);
-            end
-         end
-      end
-   end
-end
-
-endmodule
-
-// synopsys translate_off
-module test;
-
-reg		clk;
-reg		resetb;
-reg 7:0	din;
-reg		dinstb;
-wire 7:0	dout;
-wire		doutsync;
-wire		doutstb;
-wire		locked;
-
-// Instantiate the framer
-framer framer (
-   .clk(clk),
-   .resetb(resetb),
-   .din(din),
-   .dinstb(dinstb),
-   .dout(dout),
-   .doutsync(doutsync),
-   .doutstb(doutstb),
-   .locked(locked)
-);
-
-initial begin
-   fork
-      monitor_cycles(100000); // just in case..
-      genreset;
-      genclock;
-      begin
-         gendata (20);
-         $display ("Done sending good framed data, now sending trash..");
-         genradomdata (188*3);  // 3 frames worth of trash.. should drop lock.
-         $display ("Done sending trash.  Killing simulation.");
-         $finish;
-      end
-      monitor_framer_output;
-   join
-end
-
-// Generate VCD file for viewing.
-initial begin
-   $dumpfile ("framer.vcd");
-   $dumpvars (0,test);   
-end
-
-// Just a generic task for watching total cycles.
-task monitor_cycles;
-   input	maxcycles;
-   integer	maxcycles;
-   integer	cycles;
-   begin
-      forever begin
-         @(posedge clk);
-         cycles = cycles + 1;
-         if (cycles > maxcycles) begin
-            $finish;
-         end
-      end
-   end
-endtask
-
-// Watch output of framer.  Expect to see the pattern 1,2,3,4 after each SYNC.
-// This is the pattern that will be injected into framer.
-//
-task monitor_framer_output;
-   integer	cnt;
-   integer	numerrors;
-   begin
-      numerrors = 0;
-      forever begin
-         @(posedge doutstb);
-         #1;
-         if (doutsync) begin
-            $display ("Framer says SYNC..");
-            cnt = 1;
-            repeat (4) begin
-               @(posedge doutstb);
-               #1
-               $display ("   and %h..", dout);
-               if (dout != cnt) begin
-                  numerrors = numerrors + 1;
-                  $display ("!! Unexpected data from framer !! (%0d errors)", numerrors);
-               end
-               cnt = cnt + 1;
-            end
-         end
-      end
-   end
-endtask
-
-task genreset;
-   begin
-      resetb = 0;
-      repeat (2) @(posedge clk);
-      @(negedge clk);
-      resetb = 1;
-   end
-endtask
-
-task genclock;
-   begin
-      clk = 0;
-      forever begin
-         #10 clk = ~clk;
-      end
-   end
-endtask
-
-// Input framed data into the framer.  First 4 bytes of each frame should be
-// a simple counting sequence that can then be checked at its output.
-//
-task gendata;
-   input	numframes;
-   
-   integer	numframes;
-   
-   integer	cnt;
-   begin
-      cnt = $random;  // Start randomly in the frame sequence..
-      repeat (numframes*188) begin
-         repeat (3) @(posedge clk);
-         if (cnt == 0) begin
-            din = 8'h47;
-            $display ("SYNC..");
-         end
-         else begin
-            if (cnt < 5) begin
-               din = cnt;
-            end
-            else begin
-               din = $random;
-               if (din == 8'h47) begin
-                  $display ("   .. Non-SYNC 0x47 embedded in frame data !");
-               end
-            end
-         end
-      
-         dinstb = 1;
-         @(posedge clk);
-         dinstb = 0;
-         cnt = (cnt + 1) % 188;
-      end
-   end
-endtask
-
-// This will inject trash (no good framing) into framer.  Use this to show
-// that it actually drops lock.
-//
-task genradomdata;
-   input	numbytes;
-   integer	numbytes;
-   begin
-      repeat (numbytes) begin
-         repeat (3) @(posedge clk);
-         din = $random;
-         dinstb = 1;
-         @(posedge clk);
-         dinstb = 0;
-      end
-   end
-endtask
-
-endmodule
-// synopsys translate_on
-
-
-   'module',
-      'framer',
-      '(',
-       'clk',
-        'resetb',
-        'din',
-        'dinstb',
-        'dout',
-        'doutsync',
-        'doutstb',
-        'locked',
-      ')',
-      ';',
-     'input', 'clk', ';',
-      'input', 'resetb', ';',
-      'input', '', '7', ':', '0', '', 'din', ';',
-      'input', 'dinstb', ';',
-      'output', '', '7', ':', '0', '', 'dout', ';',
-      'output', 'doutsync', ';',
-      'output', 'doutstb', ';',
-      'output', 'locked', ';',
-      'parameter', 'SYNC', '=', "8 'h 47", ';',
-      'reg', '', '7', ':', '0', '', 'dout', ';',
-      'reg', 'doutsync', ';',
-      'reg', 'doutstb', ';',
-      'reg', 'locked', ';',
-      'reg', '', '7', ':', '0', '', 'cnt188', ';',
-      'reg', '', '7', ':', '0', '', 'syncindex', ';',
-      'reg', '', '7', ':', '0', '', 't0', ';',
-      'reg', '', '7', ':', '0', '', 't1', ';',
-      'reg', '', '7', ':', '0', '', 't2', ';',
-      'reg', '', '7', ':', '0', '', 't3', ';',
-      'reg', '', '7', ':', '0', '', 't4', ';',
-      'reg', '', '7', ':', '0', '', 't5', ';',
-       'always',
-        '@', '(', 'posedge', 'clk', 'negedge', 'resetb', ')',
-         'begin',
-            'if',
-              '(', '~', 'resetb', ')',
-              'begin', 'cnt188', '<=', '0', ';', 'end',
-              'else',
-               'begin',
-                  'if',
-                    '(', 'dinstb', ')',
-                     'begin',
-                        'if',
-                          '(', 'cnt188', '==', '187', ')',
-                          'begin', 'cnt188', '<=', '0', ';', 'end',
-                          'else',
-                           'begin',
-                            'cnt188', '<=', 'cnt188', '+', '1', ';',
-                            'end',
-                      'end',
-                'end',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'clk', 'negedge', 'resetb', ')',
-         'begin',
-            'if',
-              '(', '~', 'resetb', ')',
-               'begin',
-                 't0', '<=', "8 'h ff", ';',
-                  't1', '<=', "8 'h ff", ';',
-                  't2', '<=', "8 'h ff", ';',
-                  't3', '<=', "8 'h ff", ';',
-                  't4', '<=', "8 'h ff", ';',
-                  't5', '<=', "8 'h ff", ';',
-                'end',
-              'else',
-               'begin',
-                  'if',
-                     '(',
-                      'dinstb',
-                      '&&',
-                      '(',
-                      'din', '==', 'SYNC',
-                      ')',
-                      ')',
-                     'begin',
-                       't0', '<=', 't1', ';',
-                        't1', '<=', 't2', ';',
-                        't2', '<=', 't3', ';',
-                        't3', '<=', 't4', ';',
-                        't4', '<=', 't5', ';',
-                        't5', '<=', 'cnt188', ';',
-                      'end',
-                'end',
-          'end',
-       'wire',
-          't0equal',
-            '=',
-            '(',
-            't0', '==', 'cnt188',
-            ')',
-            '&&',
-            '(',
-            't0', '!=', "8 'h FF",
-            ')',
-        ';',
-       'wire',
-          't1equal',
-            '=',
-            '(',
-            't1', '==', 'cnt188',
-            ')',
-            '&&',
-            '(',
-            't1', '!=', "8 'h FF",
-            ')',
-        ';',
-       'wire',
-          't2equal',
-            '=',
-            '(',
-            't2', '==', 'cnt188',
-            ')',
-            '&&',
-            '(',
-            't2', '!=', "8 'h FF",
-            ')',
-        ';',
-       'wire',
-          't3equal',
-            '=',
-            '(',
-            't3', '==', 'cnt188',
-            ')',
-            '&&',
-            '(',
-            't3', '!=', "8 'h FF",
-            ')',
-        ';',
-       'wire',
-          't4equal',
-            '=',
-            '(',
-            't4', '==', 'cnt188',
-            ')',
-            '&&',
-            '(',
-            't4', '!=', "8 'h FF",
-            ')',
-        ';',
-       'wire',
-          't5equal',
-            '=',
-            '(',
-            't5', '==', 'cnt188',
-            ')',
-            '&&',
-            '(',
-            't5', '!=', "8 'h FF",
-            ')',
-        ';',
-       'wire',
-        '',
-        '3',
-        ':',
-        '0',
-        '',
-          'numequal',
-            '=',
-            't0equal',
-            '+',
-            't1equal',
-            '+',
-            't2equal',
-            '+',
-            't3equal',
-            '+',
-            't4equal',
-            '+',
-            't5equal',
-        ';',
-       'always',
-        '@', '(', 'posedge', 'clk', 'negedge', 'resetb', ')',
-         'begin',
-            'if',
-              '(', '~', 'resetb', ')',
-               'begin',
-                 'locked', '<=', '0', ';',
-                  'dout', '<=', '0', ';',
-                  'doutstb', '<=', '0', ';',
-                  'doutsync', '<=', '0', ';',
-                  'syncindex', '<=', '0', ';',
-                'end',
-              'else',
-               'begin',
-                 'doutstb', '<=', '0', ';',
-                  'doutsync', '<=', '0', ';',
-                   'if',
-                    '(', 'dinstb', ')',
-                     'begin',
-                       'dout', '<=', 'din', ';',
-                        'doutstb', '<=', '1', ';',
-                         'if',
-                          '(', 'locked', ')',
-                           'begin',
-                              'if',
-                                '(', 'cnt188', '==', 'syncindex', ')',
-                                 'begin',
-                                    'if',
-                                      '(', 'din', '==', 'SYNC', ')',
-                                       'begin',
-                                          '$display',
-                                            '(',
-                                            '".. Received expected SYNC .."',
-                                            ')',
-                                            ';',
-                                          'doutsync', '<=', '1', ';',
-                                        'end',
-                                      'else',
-                                       'begin',
-                                         'locked', '<=', '0', ';',
-                                           '$display',
-                                            '(',
-                                            '".. Did not receive expected '
-                                            'SYNC, dropping lock! "',
-                                            ')',
-                                            ';',
-                                        'end',
-                                  'end',
-                            'end',
-                          'else',
-                           'begin',
-                              'if',
-                                 '(',
-                                  '(',
-                                  'din', '==', 'SYNC',
-                                  ')',
-                                  '&&',
-                                  '(',
-                                  'numequal', '>', '3',
-                                  ')',
-                                  ')',
-                                 'begin',
-                                   'doutsync', '<=', '1', ';',
-                                    'locked', '<=', '1', ';',
-                                    'syncindex', '<=', 'cnt188', ';',
-                                     '$display',
-                                      '(',
-                                      '".. Received SYNC (cnt188=%0h) and '
-                                      'declaring LOCK!"',
-                                      'cnt188',
-                                      ')',
-                                      ';',
-                                  'end',
-                            'end',
-                      'end',
-                'end',
-          'end',
-    'endmodule',
-   'module', 'test', ';',
-     'reg', 'clk', ';',
-      'reg', 'resetb', ';',
-      'reg', '', '7', ':', '0', '', 'din', ';',
-      'reg', 'dinstb', ';',
-      'wire', '', '7', ':', '0', '', 'dout', ';',
-      'wire', 'doutsync', ';',
-      'wire', 'doutstb', ';',
-      'wire', 'locked', ';',
-       'framer',
-         'framer',
-           '(',
-            '.', 'clk', '(', 'clk', ')',
-            '.', 'resetb', '(', 'resetb', ')',
-            '.', 'din', '(', 'din', ')',
-            '.', 'dinstb', '(', 'dinstb', ')',
-            '.', 'dout', '(', 'dout', ')',
-            '.', 'doutsync', '(', 'doutsync', ')',
-            '.', 'doutstb', '(', 'doutstb', ')',
-            '.', 'locked', '(', 'locked', ')',
-            ')',
-        ';',
-       'initial',
-         'begin',
-            'fork',
-              'monitor_cycles', '(', '100000', ')', ';',
-              'genreset', ';',
-              'genclock', ';',
-               'begin',
-                 'gendata', '(', '20', ')', ';',
-                   '$display',
-                    '(',
-                    '"Done sending good framed data, now sending trash.."',
-                    ')',
-                    ';',
-                  'genradomdata', '(', '188', '*', '3', ')', ';',
-                   '$display',
-                    '(',
-                    '"Done sending trash.  Killing simulation."',
-                    ')',
-                    ';',
-                  '$finish', ';',
-                'end',
-              'monitor_framer_output', ';',
-              'join',
-          'end',
-       'initial',
-         'begin',
-           '$dumpfile', '(', '"framer.vcd"', ')', ';',
-            '$dumpvars', '(', '0', 'test', ')', ';',
-          'end',
-       'task',
-        'monitor_cycles',
-        ';',
-        'input', 'maxcycles', ';',
-        'integer', 'maxcycles', ';',
-        'integer', 'cycles', ';',
-         'begin',
-            'forever',
-               'begin',
-                 '@', '(', 'posedge', 'clk', ')', ';',
-                  'cycles', '=', 'cycles', '+', '1', ';',
-                   'if',
-                    '(', 'cycles', '>', 'maxcycles', ')',
-                    'begin', '$finish', ';', 'end',
-                'end',
-          'end',
-        'endtask',
-       'task',
-        'monitor_framer_output',
-        ';',
-        'integer', 'cnt', ';',
-        'integer', 'numerrors', ';',
-         'begin',
-           'numerrors', '=', '0', ';',
-             'forever',
-               'begin',
-                 '@', '(', 'posedge', 'doutstb', ')', ';',
-                  '#', '1', ';',
-                   'if',
-                    '(', 'doutsync', ')',
-                     'begin',
-                       '$display', '(', '"Framer says SYNC.."', ')', ';',
-                        'cnt', '=', '1', ';',
-                         'repeat',
-                          '(',
-                          '4',
-                          ')',
-                           'begin',
-                             '@', '(', 'posedge', 'doutstb', ')', ';',
-                               '#', '1',
-                                 '$display',
-                                  '(',
-                                  '"   and %h.."',
-                                  'dout',
-                                  ')',
-                                  ';',
-                               'if',
-                                '(', 'dout', '!=', 'cnt', ')',
-                                 'begin',
-                                     'numerrors',
-                                        '=',
-                                        'numerrors',
-                                        '+',
-                                        '1',
-                                      ';',
-                                     '$display',
-                                      '(',
-                                      '"!! Unexpected data from framer !! (%0d '
-                                      'errors)"',
-                                      'numerrors',
-                                      ')',
-                                      ';',
-                                  'end',
-                              'cnt', '=', 'cnt', '+', '1', ';',
-                            'end',
-                      'end',
-                'end',
-          'end',
-        'endtask',
-       'task',
-        'genreset',
-        ';',
-         'begin',
-           'resetb', '=', '0', ';',
-             'repeat',
-              '(',
-              '2',
-              ')',
-              '@', '(', 'posedge', 'clk', ')', ';',
-            '@', '(', 'negedge', 'clk', ')', ';',
-            'resetb', '=', '1', ';',
-          'end',
-        'endtask',
-       'task',
-        'genclock',
-        ';',
-         'begin',
-           'clk', '=', '0', ';',
-             'forever',
-               'begin',
-                '#', '10', 'clk', '=', '~', 'clk', ';',
-                'end',
-          'end',
-        'endtask',
-       'task',
-        'gendata',
-        ';',
-        'input', 'numframes', ';',
-        'integer', 'numframes', ';',
-        'integer', 'cnt', ';',
-         'begin',
-           'cnt', '=', '$random', ';',
-             'repeat',
-              '(',
-              'numframes',
-              '*',
-              '188',
-              ')',
-               'begin',
-                  'repeat',
-                    '(',
-                    '3',
-                    ')',
-                    '@', '(', 'posedge', 'clk', ')', ';',
-                   'if',
-                    '(', 'cnt', '==', '0', ')',
-                     'begin',
-                       'din', '=', "8 'h 47", ';',
-                        '$display', '(', '"SYNC.."', ')', ';',
-                      'end',
-                    'else',
-                     'begin',
-                        'if',
-                          '(', 'cnt', '<', '5', ')',
-                          'begin', 'din', '=', 'cnt', ';', 'end',
-                          'else',
-                           'begin',
-                             'din', '=', '$random', ';',
-                               'if',
-                                '(', 'din', '==', "8 'h 47", ')',
-                                 'begin',
-                                    '$display',
-                                      '(',
-                                      '"   .. Non-SYNC 0x47 embedded in frame '
-                                      'data !"',
-                                      ')',
-                                      ';',
-                                  'end',
-                            'end',
-                      'end',
-                  'dinstb', '=', '1', ';',
-                  '@', '(', 'posedge', 'clk', ')', ';',
-                  'dinstb', '=', '0', ';',
-                   'cnt', '=', '(', 'cnt', '+', '1', ')', '%', '188',
-                    ';',
-                'end',
-          'end',
-        'endtask',
-       'task',
-        'genradomdata',
-        ';',
-        'input', 'numbytes', ';',
-        'integer', 'numbytes', ';',
-         'begin',
-            'repeat',
-              '(',
-              'numbytes',
-              ')',
-               'begin',
-                  'repeat',
-                    '(',
-                    '3',
-                    ')',
-                    '@', '(', 'posedge', 'clk', ')', ';',
-                  'din', '=', '$random', ';',
-                  'dinstb', '=', '1', ';',
-                  '@', '(', 'posedge', 'clk', ')', ';',
-                  'dinstb', '=', '0', ';',
-                'end',
-          'end',
-        'endtask',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/func_72bit_test.v.parsed.txt Deleted

@@ -1,34 +0,0 @@
-/**********************************************************************
- * $func_72bit example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $func_72bit PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-  reg  71:0 result;
-
-  initial
-    begin
-      #1 result = $func_72bit();
-//      #1 $display("$func_72bit() returns %b ", result);
-    end
-
-endmodule
-
-/**********************************************************************/
-
-
-
-  'module', 'test', ';',
-     'reg', '', '71', ':', '0', '', 'result', ';',
-       'initial',
-         'begin',
-          '#', '1', 'result', '=', '$func_72bit', '(', ')', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/gen.v.parsed.txt Deleted

@@ -1,111 +0,0 @@
-// Module sig pulse generator
-module period_sig(sig_out);
-
-output
-	sig_out;
-reg
-	sig_out;
-
-// Declaration of data types
-parameter
-	sig_delay=1,
-	sig_period=100;
-
-initial		// Execute at time 0
-	begin	
-		sig_out = 0;
-		#(sig_delay -1) sig_out = 1;
-		#2 sig_out = 0;
-
-		forever		// Repeat forever
-		  begin
-			#(sig_period - 2) sig_out = 1;
-			#2 sig_out = 0;
-		  end
-
-	end
-
-endmodule
-
-
-// Module sig pulse generator
-module period_doubled_sig(sig_out);
-
-output
-	sig_out;
-reg
-	sig_out;
-
-// Declaration of data types
-parameter
-	sig_delay=1,
-	sig_period=100,
-	sig_interval=5;
-
-initial		// Execute at time 0
-	begin	
-		sig_out = 0;
-		#(sig_delay -1) sig_out = 1;
-		#2 sig_out = 0;
-		#(sig_interval-2) sig_out = 1;
-		#2 sig_out = 0;
-
-		forever		// Repeat forever
-		  begin
-			#(sig_period - 2) sig_out = 1;
-			#2 sig_out = 0;
-			#(sig_interval-2) sig_out = 1;
-			#2 sig_out = 0;
-		  end
-
-	end
-
-endmodule
-
-
-  'module', 'period_sig', '(', 'sig_out', ')', ';',
-     'output', 'sig_out', ';',
-      'reg', 'sig_out', ';',
-      'parameter', 'sig_delay', '=', '1', 'sig_period', '=', '100', ';',
-       'initial',
-         'begin',
-           'sig_out', '=', '0', ';',
-             '#', '(', 'sig_delay', '-', '1', ')',
-              'sig_out', '=', '1', ';',
-            '#', '2', 'sig_out', '=', '0', ';',
-             'forever',
-               'begin',
-                  '#', '(', 'sig_period', '-', '2', ')',
-                    'sig_out', '=', '1', ';',
-                  '#', '2', 'sig_out', '=', '0', ';',
-                'end',
-          'end',
-    'endmodule',
-   'module', 'period_doubled_sig', '(', 'sig_out', ')', ';',
-     'output', 'sig_out', ';',
-      'reg', 'sig_out', ';',
-       'parameter',
-        'sig_delay', '=', '1',
-        'sig_period', '=', '100',
-        'sig_interval', '=', '5',
-        ';',
-       'initial',
-         'begin',
-           'sig_out', '=', '0', ';',
-             '#', '(', 'sig_delay', '-', '1', ')',
-              'sig_out', '=', '1', ';',
-            '#', '2', 'sig_out', '=', '0', ';',
-             '#', '(', 'sig_interval', '-', '2', ')',
-              'sig_out', '=', '1', ';',
-            '#', '2', 'sig_out', '=', '0', ';',
-             'forever',
-               'begin',
-                  '#', '(', 'sig_period', '-', '2', ')',
-                    'sig_out', '=', '1', ';',
-                  '#', '2', 'sig_out', '=', '0', ';',
-                   '#', '(', 'sig_interval', '-', '2', ')',
-                    'sig_out', '=', '1', ';',
-                  '#', '2', 'sig_out', '=', '0', ';',
-                'end',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/gencrc.v.parsed.txt Deleted

@@ -1,635 +0,0 @@
-//
-// Behavioral Verilog for CRC16 and CRC32 for use in a testbench.
-//
-// The specific polynomials and conventions regarding bit-ordering etc.
-// are specific to the Cable Modem DOCSIS protocol, but the general scheme
-// should be reusable for other types of CRCs with some fiddling.
-//
-// This CRC code works for a specific type of network protocol, and it
-// must do certain byte swappings, etc.  You may need to play with it 
-// for your protocol.  Also, make sure the polynomials are what you
-// really want.  This is obviously, not synthesizable - I just used this
-// in a testbench at one point.
-//
-// These tasks are crude and rely on some global parameters.  They should
-// also read from a file, yada yada yada.  It is probably better to do this 
-// with a PLI call, but here it is anyway..
-//
-// The test case includes a golden DOCSIS (Cable Modem) test message that 
-// was captured in a lab.
-//
-// tom coonan, 1999.
-//
-module test_gencrc;
-
-// *** Buffer for the Golden Message ***
-reg 7:0	test_packet0:54;  
-
-// *** Global parameter block for the CRC32 calculator.
-//
-parameter	CRC32_POLY = 32'h04C11DB7;
-reg  7:0	crc32_packet0:255;
-integer		crc32_length;
-reg 31:0	crc32_result;
-
-// *** Global parameter block for the CRC16 calculator.
-//
-parameter	CRC16_POLY = 16'h1020;
-reg  7:0	crc16_packet0:255;
-integer		crc16_length;
-reg 15:0	crc16_result;
-
-`define TEST_GENCRC
-`ifdef TEST_GENCRC
-// Call the main test task and then quit.
-//
-initial begin
-   main_test;
-   $finish;
-end
-`endif
-
-// ****************************************************************
-// *
-// *   GOLDEN MESSAGE
-// *
-// *   The golden message is a DOCSIS frame that was captured off
-// *   the Broadcom reference design.  It is a MAP message.  It
-// *   includes a HCS (crc 16) and a CRC32.
-// *
-// *
-// ****************************************************************
-//
-task initialize_test_packet;
-   begin
-      test_packet00 = 8'hC2;	// FC.   HCS coverage starts here.
-      test_packet01 = 8'h00;	// MACPARAM
-      test_packet02 = 8'h00;	// MAC LEN
-      test_packet03 = 8'h30;	// MAC LEN.  HCS Coverage includes this byte and ends here.
-      test_packet04 = 8'hF2;	// CRC16 (also known as HCS)
-      test_packet05 = 8'hCF;	// CRC16 cont..
-      test_packet06 = 8'h01;	// Start of the IEEE payload.  CRC32 covererage starts here.  This is the DA field
-      test_packet07 = 8'hE0;	// DA field cont..
-      test_packet08 = 8'h2F;	// DA field cont..
-      test_packet09 = 8'h00;	// DA field cont..
-      test_packet10 = 8'h00;	// DA field cont..
-      test_packet11 = 8'h01;	// DA field cont..
-      test_packet12 = 8'h00;	// SA field
-      test_packet13 = 8'h80;	// SA field cont..
-      test_packet14 = 8'h42;	// SA field cont..
-      test_packet15 = 8'h42;	// SA field cont..
-      test_packet16 = 8'h20;	// SA field cont..
-      test_packet17 = 8'h9E;	// SA field cont..
-      test_packet18 = 8'h00;	// IEEE LEN field
-      test_packet19 = 8'h1E;	// IEEE LEN field cont.
-      test_packet20 = 8'h00;	// LLC field.
-      test_packet21 = 8'h00;	// LLC field cont...
-      test_packet22 = 8'h03;	// LLC field cont...
-      test_packet23 = 8'h01;	// LLC field cont...
-      test_packet24 = 8'h03;	// LLC field cont...  This is also the TYPE, which indicates MAP.
-      test_packet25 = 8'h00;	// LLC field cont...
-      test_packet26 = 8'h01;	// Start of MAP message payload.
-      test_packet27 = 8'h01;	// MAP message payload..
-      test_packet28 = 8'h02;	// MAP message payload..
-      test_packet29 = 8'h00;	// MAP message payload..
-      test_packet30 = 8'h00;	// MAP message payload..
-      test_packet31 = 8'h18;	// MAP message payload..
-      test_packet32 = 8'hAA;	// MAP message payload..
-      test_packet33 = 8'h58;	// MAP message payload..
-      test_packet34 = 8'h00;	// MAP message payload..
-      test_packet35 = 8'h18;	// MAP message payload..
-      test_packet36 = 8'hA8;	// MAP message payload..
-      test_packet37 = 8'hA0;	// MAP message payload..
-      test_packet38 = 8'h02;	// MAP message payload..
-      test_packet39 = 8'h03;	// MAP message payload..
-      test_packet40 = 8'h03;	// MAP message payload..
-      test_packet41 = 8'h08;	// MAP message payload..
-      test_packet42 = 8'hFF;	// MAP message payload..
-      test_packet43 = 8'hFC;	// MAP message payload..
-      test_packet44 = 8'h40;	// MAP message payload..
-      test_packet45 = 8'h00;	// MAP message payload..
-      test_packet46 = 8'h00;	// MAP message payload..
-      test_packet47 = 8'h01;	// MAP message payload..
-      test_packet48 = 8'hC0;	// MAP message payload..
-      test_packet49 = 8'h14;	// Last byte of MAP payload, last byte covered by CRC32.
-      test_packet50 = 8'hDD;	// CRC32 Starts here
-      test_packet51 = 8'hBF;	// CRC32 cont..
-      test_packet52 = 8'hC1;	// CRC32 cont..
-      test_packet53 = 8'h2E;	// Last byte of CRC32, last byte of DOCSIS.
-   end
-endtask
-
-// *************************************************************************
-// *
-// *   Main test task.
-// *
-// *   Use our primary "golden packet".  Copy into the generic global
-// *   variables that the low-level 'gencrc16' and 'gencrc32' tasks use.
-// *   Comare against the expected values and report SUCCESS or FAILURE.
-// *
-// *************************************************************************
-//
-task main_test;
-   integer	i, j;
-   integer	num_errors;
-   reg 15:0	crc16_expected;
-   reg 31:0	crc32_expected;
-   begin
-   
-   num_errors = 0;
-   
-   // Initialize the Golden Message!
-   //
-   initialize_test_packet;
-   
-   // **** TEST CRC16
-   //
-   $display ("Testing CRC16:");
-   //
-   // Copy golden test_packet into the main crc16 buffer..
-   for (i=0; i<4; i=i+1) begin
-      crc16_packeti = test_packeti;
-   end
-   crc16_expected = {test_packet4, test_packet5};
-   crc16_length = 4;  // Must tell test function the length
-   gencrc16;  // Call main test function
-   $display ("   Actual crc16_result = %h, Expected = %h", crc16_result, crc16_expected);
-   if (crc16_result == crc16_expected) begin
-      $display ("   Success.");
-   end
-   else begin
-      $display ("   ERROR!!!");
-      num_errors = num_errors + 1;
-   end
-
-   // **** TEST CRC16
-   //
-   $display ("Testing CRC32:");
-   j = 0;
-   for (i=6; i<50; i=i+1) begin
-      crc32_packetj = test_packeti;
-      j = j + 1;
-   end
-   crc32_expected = {test_packet50, test_packet51, test_packet52, test_packet53};
-   crc32_length = 44;
-   gencrc32;
-   $display ("   Actual crc32_result = %h, Expected = %h", crc32_result, crc32_expected);
-   if (crc32_result == crc32_expected) begin
-      $display ("   Success.");
-   end
-   else begin
-      $display ("   ERROR!!!");
-      num_errors = num_errors + 1;
-   end
-   
-   $display ("\nDone.  %0d Errors.", num_errors);
-   $display ("\n");
-   end
-endtask
-
-
-// ****************************************************************
-// *
-// *   Main working CRC tasks are: gencrc16, gencrc32.
-// *
-// *   These tasks rely on some globals (see front of program).
-// *
-// ****************************************************************
-
-
-// Generate a (DOCSIS) CRC16.
-//
-// Uses the GLOBAL variables:
-//
-//    Globals referenced:
-//       parameter	CRC16_POLY = 16'h1020;
-//       reg  7:0	crc16_packet0:255;
-//       integer	crc16_length;
-//
-//    Globals modified:
-//       reg 15:0	crc16_result;
-//
-task gencrc16;
-   integer	byte, bit;
-   reg		msb;
-   reg 7:0	current_byte;
-   reg 15:0	temp;
-   begin
-      crc16_result = 16'hffff;
-      for (byte = 0; byte < crc16_length; byte = byte + 1) begin
-         current_byte = crc16_packetbyte;
-         for (bit = 0; bit < 8; bit = bit + 1) begin
-            msb = crc16_result15;
-            crc16_result = crc16_result << 1;
-            if (msb != current_bytebit) begin
-               crc16_result = crc16_result ^ CRC16_POLY;
-               crc16_result0 = 1;
-            end
-         end
-      end
-      
-      // Last step is to "mirror" every bit, swap the 2 bytes, and then complement each bit.
-      //
-      // Mirror:
-      for (bit = 0; bit < 16; bit = bit + 1)
-         temp15-bit = crc16_resultbit;
-         
-      // Swap and Complement:
-      crc16_result = ~{temp7:0, temp15:8};
-   end
-endtask
-
-
-// Generate a (DOCSIS) CRC32.
-//
-// Uses the GLOBAL variables:
-//
-//    Globals referenced:
-//       parameter	CRC32_POLY = 32'h04C11DB7;
-//       reg  7:0	crc32_packet0:255;
-//       integer	crc32_length;
-//
-//    Globals modified:
-//       reg 31:0	crc32_result;
-//
-
-task gencrc32;
-   integer	byte, bit;
-   reg		msb;
-   reg 7:0	current_byte;
-   reg 31:0	temp;
-   begin
-      crc32_result = 32'hffffffff;
-      for (byte = 0; byte < crc32_length; byte = byte + 1) begin
-         current_byte = crc32_packetbyte;
-         for (bit = 0; bit < 8; bit = bit + 1) begin
-            msb = crc32_result31;
-            crc32_result = crc32_result << 1;
-            if (msb != current_bytebit) begin
-               crc32_result = crc32_result ^ CRC32_POLY;
-               crc32_result0 = 1;
-            end
-         end
-      end
-      
-      // Last step is to "mirror" every bit, swap the 4 bytes, and then complement each bit.
-      //
-      // Mirror:
-      for (bit = 0; bit < 32; bit = bit + 1)
-         temp31-bit = crc32_resultbit;
-         
-      // Swap and Complement:
-      crc32_result = ~{temp7:0, temp15:8, temp23:16, temp31:24};
-   end
-endtask
-
-endmodule
-
-
-
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-        '',
-        '7',
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-        'reg', '', '31', ':', '0', '', 'temp', ';',
-         'begin',
-           'crc32_result', '=', "32 'h ffffffff", ';',
-             'for',
-              '(',
-              'byte', '=', '0',
-              ';',
-              'byte', '<', 'crc32_length',
-              ';',
-              'byte', '=', 'byte', '+', '1',
-              ')',
-               'begin',
-                   'current_byte',
-                      '=',
-                      'crc32_packet', '', 'byte', '',
-                    ';',
-                   'for',
-                    '(',
-                    'bit', '=', '0',
-                    ';',
-                    'bit', '<', '8',
-                    ';',
-                    'bit', '=', 'bit', '+', '1',
-                    ')',
-                     'begin',
-                        'msb', '=', 'crc32_result', '', '31', '',
-                          ';',
-                         'crc32_result', '=', 'crc32_result', '<<', '1',
-                          ';',
-                         'if',
-                           '(',
-                            'msb',
-                            '!=',
-                            'current_byte', '', 'bit', '',
-                            ')',
-                           'begin',
-                               'crc32_result',
-                                  '=',
-                                  'crc32_result',
-                                  '^',
-                                  'CRC32_POLY',
-                                ';',
-                               'crc32_result', '', '0', '', '=', '1',
-                                ';',
-                            'end',
-                      'end',
-                'end',
-             'for',
-              '(',
-              'bit', '=', '0',
-              ';',
-              'bit', '<', '32',
-              ';',
-              'bit', '=', 'bit', '+', '1',
-              ')',
-                'temp', '', '31', '-', 'bit', '',
-                  '=',
-                  'crc32_result', '', 'bit', '',
-                ';',
-              'crc32_result',
-                '=',
-                '~',
-                 '{',
-                  'temp', '', '7', '0', '',
-                  'temp', '', '15', '8', '',
-                  'temp', '', '23', '16', '',
-                  'temp', '', '31', '24', '',
-                  '}',
-              ';',
-          'end',
-        'endtask',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/hadd.v.parsed.txt Deleted

@@ -1,639 +0,0 @@
-// Verilog HDL for "LIB", "hadd" "_functional"
-
-module hadd (clock, A_in, B_in, carry, sum);
-
-// Default values for the timing parameters
-parameter
-	delay_carry = 33,
-	delay_sum = 37,
-	t_hold = 1,
-	t_setup = 31,
-	t_sep = 11,
-	warning_file = 2;
-
-// Declaration of data types
-input
-	clock,
-	A_in,
-	B_in;
-
-output
-	carry,
-	sum;
-
-reg
-	trig,
-	carry,
-	sum,
-	data_A,
-	data_B,
-	extra_A,
-	extra_B;	// Multi-pulse indicators
-
-integer
-	current_time,
-	holdtime,
-	sep_time,
-	left_bound,
-	right_bound,
-	time_A,
-	time_B;
-
-initial
-  begin		// Initialization
-	trig = 0;
-	left_bound = 0;
-	{data_A, data_B} = 0;
-	{carry, sum} = 0;
-	#0 holdtime = (t_hold < 0) ? 0 : t_hold;
-  end	// initial
-
-always @(posedge A_in)
-  begin
-    // Store the time position of the data (center of the pulse)
-    time_A = $time + 1;
-    // Store the value of the data input
-    data_A = A_in;
-
-    // Display warning if more than 1 data pulse comes in 1 clock cycle
-    if (extra_A == 'b1)
-      $fdisplay(warning_file, "Extra pulse detected in module %m at input A at %0d ps.\n", time_A);
-
-    extra_A = 1;	// Set after 1 data pulse comes
-  end	// always
-
-always @(posedge B_in)
-  begin
-    // Store the time position of the data (center of the pulse)
-    time_B = $time + 1;
-    // Store the value of the data input
-    data_B = B_in;
-
-    // Display warning if more than 1 data pulse comes in 1 clock cycle
-    if (extra_B == 'b1)
-      $fdisplay(warning_file, "Extra pulse detected in module %m at input B at %0d ps.\n", time_B);
-
-    extra_B = 1;	// Set after 1 data pulse comes
-  end	// always
-
-always @(posedge clock)
-// Trigger after clock+holdtime
-  trig <= #(holdtime-1) 1;
-
-always @(posedge trig)
-  begin
-    current_time = $time+1-(holdtime-1);	// Present time of clock
-// Delay = 0.5 so that clock cycles do not overlap
-    #0.5 trig = 0;
-
-    // Generate output only if there are input pulses
-    if ((data_A !== 'b0) | (data_B !== 'b0))
-      begin
-	// Reset to receive data input in a new clock cycle
-	extra_A = 0;
-	extra_B = 0;
-	// Determine the right boundary of the time range in which there is no timing violation
-	right_bound = current_time - t_setup;
-
-	casex ({(data_A !== 'b0), (data_B !== 'b0), ((time_A >= left_bound) & (time_A <= right_bound)), ((time_B >= left_bound) & (time_B <= right_bound))})
-
-	// Two data inputs and no timing violation
-	  4'b1111:
-	    begin
-	      sep_time = time_A - time_B;
-	      sep_time = (sep_time < 0) ? -sep_time : sep_time;
-	      // Separation time violation?
-	      if (sep_time < t_sep)
-		begin
-		  carry <= #(delay_carry - holdtime) 'bx;
-		  sum <= #(delay_sum - holdtime) 'bx;
-		  $fdisplay(warning_file, "Violation of separation time in module %m.\nInput A at %0d ps, input B at %0d ps.\n", time_A, time_B);
-		end
-	      else
-		carry <= #(delay_carry - holdtime) (data_A & data_B);
-	      // Reset to receive new data values in a new clock cycle
-	      {data_A, data_B} = 0;
-	    end
-
-	// One data input and no timing violation
-	  4'b101x:
-	    begin
-	      sum <= #(delay_sum - holdtime) data_A;
-	      data_A = 0;
-	    end
-
-	// One data input and no timing violation
-	  4'b01x1:
-	    begin
-	      sum <= #(delay_sum - holdtime) data_B;
-	      data_B = 0;
-	    end
-
-	// Two data inputs and there is timing violation
-	  4'b1100:
-	    begin
-	      carry <= #(delay_carry - holdtime) 'bx;
-	      sum <= #(delay_sum - holdtime) 'bx;
-	      // Issue a warning
-	      if ((time_A > right_bound) & (time_B > right_bound))
-		$fdisplay(warning_file, "Violation of hold/setup time in module %m. \nInput A at %0d ps, input B at %0d ps, clock at %0d ps.\n", time_A, time_B, current_time);
-	      else if (time_A > right_bound)
-		begin
-		  $fdisplay(warning_file, "Violation of hold/setup time in module %m. \nInput A at %0d ps, clock at %0d ps.\n", time_A, current_time);
-		  data_B = 0;
-		end
-	      else if (time_B > right_bound)
-		begin
-		  $fdisplay(warning_file, "Violation of hold/setup time in module %m. \nInput B at %0d ps, clock at %0d ps.\n", time_B, current_time);
-		  data_A = 0;
-		end
-	      // If a warning has been issued before
-	      else
-		{data_A, data_B} = 0;
-	    end
-
-	// One data input and there is timing violation
-	  4'b100x:
-	    begin
-	      sum <= #(delay_sum - holdtime) 'bx;
-	      // Issue a warning
-	      if (time_A > right_bound)
-		$fdisplay(warning_file, "Violation of hold/setup time in module %m. \nInput A at %0d ps, clock at %0d ps.\n", time_A, current_time);
-	      // If a warning has been issued before
-	      else
-		data_A = 0;
-	    end
-
-	// One data input and there is timing violation
-	  4'b01x0:
-	    begin
-	      sum <= #(delay_sum - holdtime) 'bx;
-	      // Issue a warning
-	      if (time_B > right_bound)
-		$fdisplay(warning_file, "Violation of hold/setup time in module %m. \nInput B at %0d ps, clock at %0d ps.\n", time_B, current_time);
-	      // If a warning has been issued before
-	      else
-		data_B = 0;
-	    end
-
-	// Two data inputs and there is timing violation
-	  4'b1110:
-	    begin
-	      carry <= #(delay_carry - holdtime) 'bx;
-	      sum <= #(delay_sum - holdtime) 'bx;
-	      // Issue a warning
-	      if (time_A > right_bound)
-		$fdisplay(warning_file, "Violation of hold/setup time in module %m. \nInput A at %0d ps, clock at %0d ps.\n", time_A, current_time);
-	      // If a warning has been issued before
-	      else
-		data_A = 0;
-	    end
-
-	// Two data inputs and there is timing violation
-	  4'b1101:
-	    begin
-	      carry <= #(delay_carry - holdtime) 'bx;
-	      sum <= #(delay_sum - holdtime) 'bx;
-	      // Issue a warning
-	      if (time_B > right_bound)
-		$fdisplay(warning_file, "Violation of hold/setup time in module %m. \nInput B at %0d ps, clock at %0d ps.\n", time_B, current_time);
-	      // If a warning has been issued before
-	      else
-		data_B = 0;
-	    end
-
-	endcase
-
-	// Reset the outputs after 2ps
-	carry <= #(delay_carry - holdtime + 2) 0;
-	sum <= #(delay_sum - holdtime + 2) 0;
-      end	// if
-
-     // Determine the left boundary of the time range in which there is no timing violation
-    left_bound = current_time + t_hold;
-  end	// always
-			
-endmodule
-
-
-   'module',
-      'hadd',
-      '(',
-      'clock', 'A_in', 'B_in', 'carry', 'sum',
-      ')',
-      ';',
-      'parameter',
-        'delay_carry', '=', '33',
-        'delay_sum', '=', '37',
-        't_hold', '=', '1',
-        't_setup', '=', '31',
-        't_sep', '=', '11',
-        'warning_file', '=', '2',
-        ';',
-      'input', 'clock', 'A_in', 'B_in', ';',
-      'output', 'carry', 'sum', ';',
-       'reg',
-        'trig',
-        'carry',
-        'sum',
-        'data_A',
-        'data_B',
-        'extra_A',
-        'extra_B',
-        ';',
-       'integer',
-        'current_time',
-        'holdtime',
-        'sep_time',
-        'left_bound',
-        'right_bound',
-        'time_A',
-        'time_B',
-        ';',
-       'initial',
-         'begin',
-           'trig', '=', '0', ';',
-            'left_bound', '=', '0', ';',
-            '{', 'data_A', 'data_B', '}', '=', '0', ';',
-            '{', 'carry', 'sum', '}', '=', '0', ';',
-             '#', '0',
-                'holdtime',
-                  '=',
-                  '(',
-                  't_hold', '<', '0',
-                  ')',
-                  '?',
-                  '0',
-                  ':',
-                  't_hold',
-                ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'A_in', ')',
-         'begin',
-           'time_A', '=', '$time', '+', '1', ';',
-            'data_A', '=', 'A_in', ';',
-             'if',
-              '(', 'extra_A', '==', "'b 1", ')',
-               '$fdisplay',
-                '(',
-                'warning_file',
-                '"Extra pulse detected in module %m at input A at %0d ps.\\n"',
-                'time_A',
-                ')',
-                ';',
-            'extra_A', '=', '1', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'B_in', ')',
-         'begin',
-           'time_B', '=', '$time', '+', '1', ';',
-            'data_B', '=', 'B_in', ';',
-             'if',
-              '(', 'extra_B', '==', "'b 1", ')',
-               '$fdisplay',
-                '(',
-                'warning_file',
-                '"Extra pulse detected in module %m at input B at %0d ps.\\n"',
-                'time_B',
-                ')',
-                ';',
-            'extra_B', '=', '1', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'clock', ')',
-         'trig', '<=', '#', '(', 'holdtime', '-', '1', ')', '1',
-          ';',
-       'always',
-        '@', '(', 'posedge', 'trig', ')',
-         'begin',
-             'current_time',
-                '=',
-                '$time',
-                '+',
-                '1',
-                '-',
-                '(',
-                'holdtime', '-', '1',
-                ')',
-              ';',
-            '#', '0.5', 'trig', '=', '0', ';',
-             'if',
-               '(',
-                '(',
-                'data_A', '!==', "'b 0",
-                ')',
-                '|',
-                '(',
-                'data_B', '!==', "'b 0",
-                ')',
-                ')',
-               'begin',
-                 'extra_A', '=', '0', ';',
-                  'extra_B', '=', '0', ';',
-                   'right_bound', '=', 'current_time', '-', 't_setup',
-                    ';',
-                   'casex',
-                    '(',
-                     '{',
-                      '(',
-                      'data_A', '!==', "'b 0",
-                      ')',
-                      '(',
-                      'data_B', '!==', "'b 0",
-                      ')',
-                      '(',
-                       '(',
-                        'time_A', '>=', 'left_bound',
-                        ')',
-                        '&',
-                        '(',
-                        'time_A', '<=', 'right_bound',
-                        ')',
-                      ')',
-                      '(',
-                       '(',
-                        'time_B', '>=', 'left_bound',
-                        ')',
-                        '&',
-                        '(',
-                        'time_B', '<=', 'right_bound',
-                        ')',
-                      ')',
-                      '}',
-                    ')',
-                    "4 'b 1111",
-                    ':',
-                     'begin',
-                       'sep_time', '=', 'time_A', '-', 'time_B', ';',
-                          'sep_time',
-                            '=',
-                            '(',
-                            'sep_time', '<', '0',
-                            ')',
-                            '?',
-                            '-',
-                            'sep_time',
-                            ':',
-                            'sep_time',
-                          ';',
-                         'if',
-                          '(', 'sep_time', '<', 't_sep', ')',
-                           'begin',
-                               'carry',
-                                  '<=',
-                                   '#',
-                                    '(',
-                                    'delay_carry', '-', 'holdtime',
-                                    ')',
-                                  "'b x",
-                                ';',
-                                'sum',
-                                  '<=',
-                                   '#',
-                                    '(',
-                                    'delay_sum', '-', 'holdtime',
-                                    ')',
-                                  "'b x",
-                                ';',
-                               '$fdisplay',
-                                '(',
-                                'warning_file',
-                                '"Violation of separation time in module '
-                                '%m.\\nInput A at %0d ps, input B at %0d '
-                                'ps.\\n"',
-                                'time_A',
-                                'time_B',
-                                ')',
-                                ';',
-                            'end',
-                          'else',
-                            'carry',
-                              '<=',
-                               '#',
-                                '(',
-                                'delay_carry', '-', 'holdtime',
-                                ')',
-                              '(',
-                              'data_A', '&', 'data_B',
-                              ')',
-                            ';',
-                        '{', 'data_A', 'data_B', '}', '=', '0', ';',
-                      'end',
-                    "4 'b 101x",
-                    ':',
-                     'begin',
-                         'sum',
-                            '<=',
-                            '#', '(', 'delay_sum', '-', 'holdtime', ')',
-                            'data_A',
-                          ';',
-                        'data_A', '=', '0', ';',
-                      'end',
-                    "4 'b 01x1",
-                    ':',
-                     'begin',
-                         'sum',
-                            '<=',
-                            '#', '(', 'delay_sum', '-', 'holdtime', ')',
-                            'data_B',
-                          ';',
-                        'data_B', '=', '0', ';',
-                      'end',
-                    "4 'b 1100",
-                    ':',
-                     'begin',
-                         'carry',
-                            '<=',
-                             '#',
-                              '(',
-                              'delay_carry', '-', 'holdtime',
-                              ')',
-                            "'b x",
-                          ';',
-                          'sum',
-                            '<=',
-                            '#', '(', 'delay_sum', '-', 'holdtime', ')',
-                            "'b x",
-                          ';',
-                         'if',
-                           '(',
-                            '(',
-                            'time_A', '>', 'right_bound',
-                            ')',
-                            '&',
-                            '(',
-                            'time_B', '>', 'right_bound',
-                            ')',
-                            ')',
-                           '$fdisplay',
-                            '(',
-                            'warning_file',
-                            '"Violation of hold/setup time in module %m. '
-                            '\\nInput A at %0d ps, input B at %0d ps, clock at '
-                            '%0d ps.\\n"',
-                            'time_A',
-                            'time_B',
-                            'current_time',
-                            ')',
-                            ';',
-                          'else',
-                           'if',
-                            '(', 'time_A', '>', 'right_bound', ')',
-                             'begin',
-                                '$fdisplay',
-                                  '(',
-                                  'warning_file',
-                                  '"Violation of hold/setup time in module %m. '
-                                  '\\nInput A at %0d ps, clock at %0d ps.\\n"',
-                                  'time_A',
-                                  'current_time',
-                                  ')',
-                                  ';',
-                                'data_B', '=', '0', ';',
-                              'end',
-                            'else',
-                             'if',
-                              '(', 'time_B', '>', 'right_bound', ')',
-                               'begin',
-                                  '$fdisplay',
-                                    '(',
-                                    'warning_file',
-                                    '"Violation of hold/setup time in module '
-                                    '%m. \\nInput B at %0d ps, clock at %0d '
-                                    'ps.\\n"',
-                                    'time_B',
-                                    'current_time',
-                                    ')',
-                                    ';',
-                                  'data_A', '=', '0', ';',
-                                'end',
-                              'else',
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-                      'end',
-                    "4 'b 100x",
-                    ':',
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-                         'sum',
-                            '<=',
-                            '#', '(', 'delay_sum', '-', 'holdtime', ')',
-                            "'b x",
-                          ';',
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-                          '(', 'time_A', '>', 'right_bound', ')',
-                           '$fdisplay',
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-                            'warning_file',
-                            '"Violation of hold/setup time in module %m. '
-                            '\\nInput A at %0d ps, clock at %0d ps.\\n"',
-                            'time_A',
-                            'current_time',
-                            ')',
-                            ';',
-                          'else',
-                          'data_A', '=', '0', ';',
-                      'end',
-                    "4 'b 01x0",
-                    ':',
-                     'begin',
-                         'sum',
-                            '<=',
-                            '#', '(', 'delay_sum', '-', 'holdtime', ')',
-                            "'b x",
-                          ';',
-                         'if',
-                          '(', 'time_B', '>', 'right_bound', ')',
-                           '$fdisplay',
-                            '(',
-                            'warning_file',
-                            '"Violation of hold/setup time in module %m. '
-                            '\\nInput B at %0d ps, clock at %0d ps.\\n"',
-                            'time_B',
-                            'current_time',
-                            ')',
-                            ';',
-                          'else',
-                          'data_B', '=', '0', ';',
-                      'end',
-                    "4 'b 1110",
-                    ':',
-                     'begin',
-                         'carry',
-                            '<=',
-                             '#',
-                              '(',
-                              'delay_carry', '-', 'holdtime',
-                              ')',
-                            "'b x",
-                          ';',
-                          'sum',
-                            '<=',
-                            '#', '(', 'delay_sum', '-', 'holdtime', ')',
-                            "'b x",
-                          ';',
-                         'if',
-                          '(', 'time_A', '>', 'right_bound', ')',
-                           '$fdisplay',
-                            '(',
-                            'warning_file',
-                            '"Violation of hold/setup time in module %m. '
-                            '\\nInput A at %0d ps, clock at %0d ps.\\n"',
-                            'time_A',
-                            'current_time',
-                            ')',
-                            ';',
-                          'else',
-                          'data_A', '=', '0', ';',
-                      'end',
-                    "4 'b 1101",
-                    ':',
-                     'begin',
-                         'carry',
-                            '<=',
-                             '#',
-                              '(',
-                              'delay_carry', '-', 'holdtime',
-                              ')',
-                            "'b x",
-                          ';',
-                          'sum',
-                            '<=',
-                            '#', '(', 'delay_sum', '-', 'holdtime', ')',
-                            "'b x",
-                          ';',
-                         'if',
-                          '(', 'time_B', '>', 'right_bound', ')',
-                           '$fdisplay',
-                            '(',
-                            'warning_file',
-                            '"Violation of hold/setup time in module %m. '
-                            '\\nInput B at %0d ps, clock at %0d ps.\\n"',
-                            'time_B',
-                            'current_time',
-                            ')',
-                            ';',
-                          'else',
-                          'data_B', '=', '0', ';',
-                      'end',
-                    'endcase',
-                    'carry',
-                      '<=',
-                       '#',
-                        '(',
-                        'delay_carry', '-', 'holdtime', '+', '2',
-                        ')',
-                      '0',
-                    ';',
-                    'sum',
-                      '<=',
-                       '#',
-                        '(',
-                        'delay_sum', '-', 'holdtime', '+', '2',
-                        ')',
-                      '0',
-                    ';',
-                'end',
-            'left_bound', '=', 'current_time', '+', 't_hold', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/hello_test.v.parsed.txt Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/in_port.v.parsed.txt Deleted

@@ -1,300 +0,0 @@
-/* Input port */
-// Author Andrew Laffely
-// Last modified: 12 Feb 03
-//!!!!!!!!!!!!!!!! DO NOT CHANGE THIS FILE !!!!!!!!!!!!!!!!!!!!!
-module in_port (gclock, reset, i_addr, data_in, c_addr, c_read, c_data, valid_back, ready);
-
-input gclock, reset;
-input 1:0 i_addr;      // buffer address requested by ccm
-input 1:0 c_addr;      // buffer address requested by core
-input 32:0 data_in;    // the data to be buffered from interface
-input c_read;	         // read singal from core
-
-output valid_back;       // flow control bit sent upstream to block data
-output 31:0 c_data;    // the data sent to the core
-output 2:0 ready;      // flow control, port "ready" signal, sent to core
-reg valid_back;
-reg 31:0 c_data;
-reg 2:0 ready;   
-
-reg 5:0 valid;         // contains the valid bits of the data in the port
-reg 31:0 data 5:0;   // the data in the cdm
-reg 2:0 i_addr_hold;   // hold the buf addr while evaluating
-reg 2:0 c_addr_hold;   // hold the buf addr while evaluating
-reg 2:0 i_buf_state, c_buf_state; // first or second buf in each port
-
-reg faketiming;  // Makes level sensitive transitions work properly
-initial
-begin
-	faketiming = 1'b0;
-	forever #1 faketiming = ~faketiming;
-end
-
-// *********************** INTERCONNECT *********************** //
-always @ (posedge gclock)  //interconnect side
-begin
-  if(!reset)
-    begin
-      //update valid from last transfer
-      if(!(i_addr_hold2:1 == 2'b11))  
-	begin
-	  if(!valid_back)
-	    begin
-		validi_addr_hold=data_in32;  //glitch set
-		if (data_in32)
-		   i_buf_statei_addr_hold2:1=~i_buf_statei_addr_hold2:1;
-	    end
-	end
-	#1 i_addr_hold = {i_addr,i_buf_statei_addr};
-
-	//Send data
-	if(i_addr == 2'b11)  //default no data
-	  begin
-		#1 valid_back = 0;//upstream flow control
-	  end
-	else
-	  begin
-	 	#1 valid_back = validi_addr_hold;
-		 //upstream flow control
-	  end
-    end
-end
-// ******************** END INTERCONNECT *********************** //
-
-// *************************** CORE **************************** //
-always @ (posedge c_read)
-begin
-	c_addr_hold = {c_addr, c_buf_statec_addr};
-end
-always @ (negedge c_read) //Core
-  begin
-    if(!reset)
-      begin
-	validc_addr_hold=0;  //glitch reset
-	c_buf_statec_addr_hold2:1=~c_buf_statec_addr_hold2:1;
-      end
-end
-// ************************** END CORE ************************* //
-
-always @ (faketiming)
-  begin
-    if (reset)
-      begin
-	valid = 4'b0000;
-	valid_back = 1'b0;
-	i_addr_hold = 3'b111;
-	i_buf_state=3'b000;
-	c_buf_state=3'b000;
-      end
-    else
-      begin
-	ready0=validc_buf_state0;
-	ready1=validc_buf_state1;
-	ready2=validc_buf_state2;
-
-	// ********************* Interconnect side **************** //
-	if (!gclock)
-	  begin
-		//if valid port # and not blocked store new data in port
-		if(!(i_addr_hold2:1 == 2'b11)&&(!valid_back)) 
-		  begin
-			datai_addr_hold = data_in31:0;
-		  end
-	  end
-	// ****************** End Interconnect side **************** //
-
-	// *************************** CORE ************************ //
-	if (c_read)
-	  begin
-		c_data = datac_addr_hold;
-	  end
-        // ************************ END CORE ********************** //
-  end
-end
-
-endmodule
-
-
-   'module',
-      'in_port',
-      '(',
-       'gclock',
-        'reset',
-        'i_addr',
-        'data_in',
-        'c_addr',
-        'c_read',
-        'c_data',
-        'valid_back',
-        'ready',
-      ')',
-      ';',
-     'input', 'gclock', 'reset', ';',
-      'input', '', '1', ':', '0', '', 'i_addr', ';',
-      'input', '', '1', ':', '0', '', 'c_addr', ';',
-      'input', '', '32', ':', '0', '', 'data_in', ';',
-      'input', 'c_read', ';',
-      'output', 'valid_back', ';',
-      'output', '', '31', ':', '0', '', 'c_data', ';',
-      'output', '', '2', ':', '0', '', 'ready', ';',
-      'reg', 'valid_back', ';',
-      'reg', '', '31', ':', '0', '', 'c_data', ';',
-      'reg', '', '2', ':', '0', '', 'ready', ';',
-      'reg', '', '5', ':', '0', '', 'valid', ';',
-      'reg', '', '31', ':', '0', '', 'data', '', '5', ':', '0', '', ';',
-      'reg', '', '2', ':', '0', '', 'i_addr_hold', ';',
-      'reg', '', '2', ':', '0', '', 'c_addr_hold', ';',
-      'reg', '', '2', ':', '0', '', 'i_buf_state', 'c_buf_state', ';',
-      'reg', 'faketiming', ';',
-       'initial',
-         'begin',
-           'faketiming', '=', "1 'b 0", ';',
-             'forever',
-              '#', '1', 'faketiming', '=', '~', 'faketiming', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'gclock', ')',
-         'begin',
-            'if',
-              '(', '!', 'reset', ')',
-               'begin',
-                  'if',
-                     '(',
-                      '!',
-                      '(',
-                      'i_addr_hold', '', '2', '1', '', '==', "2 'b 11",
-                      ')',
-                      ')',
-                     'begin',
-                        'if',
-                          '(', '!', 'valid_back', ')',
-                           'begin',
-                               'valid', '', 'i_addr_hold', '',
-                                  '=',
-                                  'data_in', '', '32', '',
-                                ';',
-                               'if',
-                                '(', 'data_in', '', '32', '', ')',
-                                   'i_buf_state',
-                                       '',
-                                        'i_addr_hold', '', '2', '1', '',
-                                        '',
-                                    '=',
-                                    '~',
-                                     'i_buf_state',
-                                       '',
-                                        'i_addr_hold', '', '2', '1', '',
-                                        '',
-                                  ';',
-                            'end',
-                      'end',
-                   '#', '1',
-                      'i_addr_hold',
-                        '=',
-                         '{',
-                          'i_addr',
-                          'i_buf_state', '', 'i_addr', '',
-                          '}',
-                      ';',
-                   'if',
-                    '(', 'i_addr', '==', "2 'b 11", ')',
-                     'begin',
-                      '#', '1', 'valid_back', '=', '0', ';',
-                      'end',
-                    'else',
-                     'begin',
-                        '#', '1',
-                            'valid_back',
-                              '=',
-                              'valid', '', 'i_addr_hold', '',
-                            ';',
-                      'end',
-                'end',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'c_read', ')',
-         'begin',
-             'c_addr_hold',
-                '=',
-                 '{',
-                  'c_addr',
-                  'c_buf_state', '', 'c_addr', '',
-                  '}',
-              ';',
-          'end',
-       'always',
-        '@', '(', 'negedge', 'c_read', ')',
-         'begin',
-            'if',
-              '(', '!', 'reset', ')',
-               'begin',
-                 'valid', '', 'c_addr_hold', '', '=', '0', ';',
-                     'c_buf_state',
-                        '', 'c_addr_hold', '', '2', '1', '', '',
-                      '=',
-                      '~',
-                       'c_buf_state',
-                        '', 'c_addr_hold', '', '2', '1', '', '',
-                    ';',
-                'end',
-          'end',
-       'always',
-        '@', '(', 'faketiming', ')',
-         'begin',
-            'if',
-              '(', 'reset', ')',
-               'begin',
-                 'valid', '=', "4 'b 0000", ';',
-                  'valid_back', '=', "1 'b 0", ';',
-                  'i_addr_hold', '=', "3 'b 111", ';',
-                  'i_buf_state', '=', "3 'b 000", ';',
-                  'c_buf_state', '=', "3 'b 000", ';',
-                'end',
-              'else',
-               'begin',
-                   'ready', '', '0', '',
-                      '=',
-                      'valid', '', 'c_buf_state', '', '0', '', '',
-                    ';',
-                    'ready', '', '1', '',
-                      '=',
-                      'valid', '', 'c_buf_state', '', '1', '', '',
-                    ';',
-                    'ready', '', '2', '',
-                      '=',
-                      'valid', '', 'c_buf_state', '', '2', '', '',
-                    ';',
-                   'if',
-                    '(', '!', 'gclock', ')',
-                     'begin',
-                        'if',
-                           '(',
-                            '!',
-                            '(',
-                             'i_addr_hold', '', '2', '1', '',
-                              '==',
-                              "2 'b 11",
-                            ')',
-                            '&&',
-                            '(',
-                            '!', 'valid_back',
-                            ')',
-                            ')',
-                           'begin',
-                               'data', '', 'i_addr_hold', '',
-                                  '=',
-                                  'data_in', '', '31', '0', '',
-                                ';',
-                            'end',
-                      'end',
-                   'if',
-                    '(', 'c_read', ')',
-                     'begin',
-                         'c_data',
-                            '=',
-                            'data', '', 'c_addr_hold', '',
-                          ';',
-                      'end',
-                'end',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/inv.v.parsed.txt Deleted

@@ -1,247 +0,0 @@
-// Verilog HDL for "gates.lib", "inv_cell" "_functional"
-// Module INV cell
-module inv_cell (d, clk, out);
-
-input
-	d, clk;
-
-output
-	out;
-reg 
-	out;
-
-parameter
-	t_hold=5,
-	t_setup=10,
-	delay=15,
-
-	warning_file=3;  // multichannel description of a warning file
-
-reg
-	d_internal, clk_internal,
-	d_state,          	   // internal state at the input d
-	d_set;		   	   // signal determining the moment when
-				   // the state of the d input changes to "1"
-
-integer
-	data_delay,  // delay between d and d_internal
-	clk_delay,   // delay between clk and clk_internal
-	out_delay,   // delay between clk_internal and out
-	out_value,   // output value in a given clock cycle
-	last_clk_time;	// time when the last clock pulse appeared
-
-initial 
-	begin
-// define delays between inputs & outputs and the corresponding
-//  internal auxiliary registers
-	  	if(t_hold<0)
-		  begin
-	    	  	data_delay = -t_hold;
-	    		clk_delay  = 0;
-			out_delay  = delay;
-		  end
-	  	else
-		  begin
-	   	  	data_delay = 0;
-	    		clk_delay  = t_hold;
-		  	out_delay  = delay-t_hold;
-		  end
-
-// clear internal registers and the output signal
-		d_internal = 0;
-		clk_internal = 0;
-		last_clk_time = 0;
-		d_state = 0;
-		d_set = 0;
-		out = 0;
-	end
-
-
-
-always @(posedge d) 	// Execute at positive edge of d
-	  d_internal <= #(data_delay) d;
-
-always @(posedge clk)  // Execute at positive edge of clk
-	  clk_internal <= #(clk_delay) clk;
-
-
-always @(posedge d_internal)
-	begin
-// setting the state of the d input
-                d_state <= d_state | 1'bx;
-		if (d_internal === 1)
-		  d_set <= #(t_hold+t_setup) 1;
-
-		d_internal <= 0;
-	end
-
-always @(posedge d_set)
-	begin
-		if ($stime - last_clk_time >= t_hold+t_setup)
-			d_state = 1;
-		else
-		  begin
-			d_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input D pulse at %0d,",
-			 $stime-data_delay-t_hold-t_setup);
-			$fwrite(warning_file,
-			"\tClock pulse at %0d.\n", last_clk_time-clk_delay);
-		  end
-
-		d_set <= 0;
-	end
-
-
-always @(posedge clk_internal)	
-	begin
-// computing the output
-		if (clk_internal === 1'bx)
-		  out_value = 1'bx;
-		else
-		  out_value = ~d_state;
-
-// transfering the result to the output
-		out <= #(out_delay) out_value;
-		out <= #(out_delay+2) 0;
-
-// clearing the internal state of the DRO
-		d_state  <= 0;
-
-		clk_internal <= 0;
-		last_clk_time = $stime;
-	end
-
-endmodule
-
-
-  'module', 'inv_cell', '(', 'd', 'clk', 'out', ')', ';',
-     'input', 'd', 'clk', ';',
-      'output', 'out', ';',
-      'reg', 'out', ';',
-       'parameter',
-        't_hold', '=', '5',
-        't_setup', '=', '10',
-        'delay', '=', '15',
-        'warning_file', '=', '3',
-        ';',
-      'reg', 'd_internal', 'clk_internal', 'd_state', 'd_set', ';',
-       'integer',
-        'data_delay',
-        'clk_delay',
-        'out_delay',
-        'out_value',
-        'last_clk_time',
-        ';',
-       'initial',
-         'begin',
-            'if',
-              '(', 't_hold', '<', '0', ')',
-               'begin',
-                 'data_delay', '=', '-', 't_hold', ';',
-                  'clk_delay', '=', '0', ';',
-                  'out_delay', '=', 'delay', ';',
-                'end',
-              'else',
-               'begin',
-                 'data_delay', '=', '0', ';',
-                  'clk_delay', '=', 't_hold', ';',
-                  'out_delay', '=', 'delay', '-', 't_hold', ';',
-                'end',
-            'd_internal', '=', '0', ';',
-            'clk_internal', '=', '0', ';',
-            'last_clk_time', '=', '0', ';',
-            'd_state', '=', '0', ';',
-            'd_set', '=', '0', ';',
-            'out', '=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'd', ')',
-         'd_internal', '<=', '#', '(', 'data_delay', ')', 'd',
-          ';',
-       'always',
-        '@', '(', 'posedge', 'clk', ')',
-         'clk_internal', '<=', '#', '(', 'clk_delay', ')', 'clk',
-          ';',
-       'always',
-        '@', '(', 'posedge', 'd_internal', ')',
-         'begin',
-           'd_state', '<=', 'd_state', '|', "1 'b x", ';',
-             'if',
-              '(', 'd_internal', '===', '1', ')',
-                'd_set',
-                  '<=',
-                  '#', '(', 't_hold', '+', 't_setup', ')',
-                  '1',
-                ';',
-            'd_internal', '<=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'd_set', ')',
-         'begin',
-            'if',
-               '(',
-                '$stime',
-                '-',
-                'last_clk_time',
-                '>=',
-                't_hold',
-                '+',
-                't_setup',
-                ')',
-              'd_state', '=', '1', ';',
-              'else',
-               'begin',
-                 'd_state', '=', "1 'b x", ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Violation of hold/setup time in module %m.\\n"',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Input D pulse at %0d,"',
-                    '$stime',
-                    '-',
-                    'data_delay',
-                    '-',
-                    't_hold',
-                    '-',
-                    't_setup',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"\\tClock pulse at %0d.\\n"',
-                    'last_clk_time',
-                    '-',
-                    'clk_delay',
-                    ')',
-                    ';',
-                'end',
-            'd_set', '<=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'clk_internal', ')',
-         'begin',
-            'if',
-              '(', 'clk_internal', '===', "1 'b x", ')',
-              'out_value', '=', "1 'b x", ';',
-              'else',
-              'out_value', '=', '~', 'd_state', ';',
-             'out', '<=', '#', '(', 'out_delay', ')', 'out_value',
-              ';',
-             'out', '<=', '#', '(', 'out_delay', '+', '2', ')', '0',
-              ';',
-            'd_state', '<=', '0', ';',
-            'clk_internal', '<=', '0', ';',
-            'last_clk_time', '=', '$stime', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/inv_cell.v.parsed.txt Deleted

@@ -1,339 +0,0 @@
-// Verilog HDL for "RSFQ.lib", "inv_cell" "_functional"
-
-// Module INV cell
-module inv_cell (d, clk, out);
-
-input
-	d, clk;
-
-output
-	out;
-reg 
-	out;
-
-parameter
-	t_hold=5,
-	t_setup=10,
-	delay=15,
-
-// multichannel description of a warning file
-	warning_file=2,  
-// multichannel description of a delay file
-	delay_file = warning_file<<1;
-
-reg
-	d_internal, clk_internal,
-	d_state,          	   // internal state at the input d
-	d_set;		   	   // signal determining the moment when
-				   // the state of the d input changes to "1"
-
-integer
-	data_delay,  // delay between d and d_internal
-	clk_delay,   // delay between clk and clk_internal
-	out_delay,   // delay between clk_internal and out
-	out_value,   // output value in a given clock cycle
-	last_clk_time,	// time when the last clock pulse appeared
-	vt_hold,	// variable hold
-	vt_setup,	// variable setup
-	vdelay;		// variable delay
-
-`include "INIT"
-
-`ifdef RANDOM_DELAYS
- `include "RANDOM_GATE"
-`endif
-
-
-initial 
-	begin
-
-		vt_hold = t_hold;
-		vt_setup = t_setup;
-		vdelay = delay;
-
-`ifdef RANDOM_DELAYS
-		delay_dev = inv_cell_variation*delay;
-		vdelay = $dist_normal(inv_cell_seed, delay, delay_dev);
-		vt_hold = $dist_normal(inv_cell_seed, t_hold, inv_hs_dev);
-		vt_setup = t_setup + (t_hold - vt_hold);
-`endif
-
-		#1 $fdisplay(delay_file, "module=%m, nom_delay=%0d, delay=%0d", delay, vdelay);
-		#1 $fdisplay(delay_file, "module=%m, nom_hold=%0d, hold=%0d", t_hold, vt_hold);
-		#1 $fdisplay(delay_file, "module=%m, nom_setup=%0d, setup=%0d", t_setup, vt_setup);
-
-
-// define delays between inputs & outputs and the corresponding
-//  internal auxiliary registers
-	  	if(vt_hold<0)
-		  begin
-	    	  	data_delay = -vt_hold;
-	    		clk_delay  = 0;
-			out_delay  = vdelay;
-		  end
-	  	else
-		  begin
-	   	  	data_delay = 0;
-	    		clk_delay  = vt_hold;
-		  	out_delay  = vdelay-vt_hold;
-		  end
-
-// clear internal registers and the output signal
-		d_internal = 0;
-		clk_internal = 0;
-		last_clk_time = 0;
-		d_state = 0;
-		d_set = 0;
-		out = 0;
-	end
-
-
-
-always @(posedge d) 	// Execute at positive edge of d
-	  d_internal <= #(data_delay) d;
-
-always @(posedge clk)  // Execute at positive edge of clk
-	  clk_internal <= #(clk_delay) clk;
-
-
-always @(posedge d_internal)
-	begin
-// setting the state of the d input
-                d_state <= d_state | 1'bx;
-		if (d_internal === 1)
-		  d_set <= #(vt_hold+vt_setup) 1;
-
-		d_internal <= 0;
-	end
-
-always @(posedge d_set)
-	begin
-		if ($stime - last_clk_time >= vt_hold+vt_setup)
-			d_state = 1;
-		else
-		  begin
-			d_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input D pulse at %0d,",
-			 $stime-data_delay-vt_hold-vt_setup);
-			$fwrite(warning_file,
-			"\tClock pulse at %0d.\n", last_clk_time-clk_delay);
-		  end
-
-		d_set <= 0;
-	end
-
-
-always @(posedge clk_internal)	
-	begin
-// computing the output
-		if (clk_internal === 1'bx)
-		  out_value = 1'bx;
-		else
-		  out_value = ~d_state;
-
-// transfering the result to the output
-		out <= #(out_delay) out_value;
-		out <= #(out_delay+2) 0;
-
-// clearing the internal state of the DRO
-		d_state  <= 0;
-
-		clk_internal <= 0;
-		last_clk_time = $stime;
-	end
-
-endmodule
-
-
-  'module', 'inv_cell', '(', 'd', 'clk', 'out', ')', ';',
-     'input', 'd', 'clk', ';',
-      'output', 'out', ';',
-      'reg', 'out', ';',
-       'parameter',
-        't_hold', '=', '5',
-        't_setup', '=', '10',
-        'delay', '=', '15',
-        'warning_file', '=', '2',
-        'delay_file', '=', 'warning_file', '<<', '1',
-        ';',
-      'reg', 'd_internal', 'clk_internal', 'd_state', 'd_set', ';',
-       'integer',
-        'data_delay',
-        'clk_delay',
-        'out_delay',
-        'out_value',
-        'last_clk_time',
-        'vt_hold',
-        'vt_setup',
-        'vdelay',
-        ';',
-       'initial',
-         'begin',
-           'vt_hold', '=', 't_hold', ';',
-            'vt_setup', '=', 't_setup', ';',
-            'vdelay', '=', 'delay', ';',
-            'delay_dev', '=', 'inv_cell_variation', '*', 'delay', ';',
-              'vdelay',
-                '=',
-                 '$dist_normal',
-                  '(',
-                  'inv_cell_seed',
-                  'delay',
-                  'delay_dev',
-                  ')',
-              ';',
-              'vt_hold',
-                '=',
-                 '$dist_normal',
-                  '(',
-                  'inv_cell_seed',
-                  't_hold',
-                  'inv_hs_dev',
-                  ')',
-              ';',
-              'vt_setup',
-                '=',
-                't_setup',
-                '+',
-                '(',
-                't_hold', '-', 'vt_hold',
-                ')',
-              ';',
-             '#', '1',
-               '$fdisplay',
-                '(',
-                'delay_file',
-                '"module=%m, nom_delay=%0d, delay=%0d"',
-                'delay',
-                'vdelay',
-                ')',
-                ';',
-             '#', '1',
-               '$fdisplay',
-                '(',
-                'delay_file',
-                '"module=%m, nom_hold=%0d, hold=%0d"',
-                't_hold',
-                'vt_hold',
-                ')',
-                ';',
-             '#', '1',
-               '$fdisplay',
-                '(',
-                'delay_file',
-                '"module=%m, nom_setup=%0d, setup=%0d"',
-                't_setup',
-                'vt_setup',
-                ')',
-                ';',
-             'if',
-              '(', 'vt_hold', '<', '0', ')',
-               'begin',
-                 'data_delay', '=', '-', 'vt_hold', ';',
-                  'clk_delay', '=', '0', ';',
-                  'out_delay', '=', 'vdelay', ';',
-                'end',
-              'else',
-               'begin',
-                 'data_delay', '=', '0', ';',
-                  'clk_delay', '=', 'vt_hold', ';',
-                  'out_delay', '=', 'vdelay', '-', 'vt_hold', ';',
-                'end',
-            'd_internal', '=', '0', ';',
-            'clk_internal', '=', '0', ';',
-            'last_clk_time', '=', '0', ';',
-            'd_state', '=', '0', ';',
-            'd_set', '=', '0', ';',
-            'out', '=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'd', ')',
-         'd_internal', '<=', '#', '(', 'data_delay', ')', 'd',
-          ';',
-       'always',
-        '@', '(', 'posedge', 'clk', ')',
-         'clk_internal', '<=', '#', '(', 'clk_delay', ')', 'clk',
-          ';',
-       'always',
-        '@', '(', 'posedge', 'd_internal', ')',
-         'begin',
-           'd_state', '<=', 'd_state', '|', "1 'b x", ';',
-             'if',
-              '(', 'd_internal', '===', '1', ')',
-                'd_set',
-                  '<=',
-                  '#', '(', 'vt_hold', '+', 'vt_setup', ')',
-                  '1',
-                ';',
-            'd_internal', '<=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'd_set', ')',
-         'begin',
-            'if',
-               '(',
-                '$stime',
-                '-',
-                'last_clk_time',
-                '>=',
-                'vt_hold',
-                '+',
-                'vt_setup',
-                ')',
-              'd_state', '=', '1', ';',
-              'else',
-               'begin',
-                 'd_state', '=', "1 'b x", ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Violation of hold/setup time in module %m.\\n"',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Input D pulse at %0d,"',
-                    '$stime',
-                    '-',
-                    'data_delay',
-                    '-',
-                    'vt_hold',
-                    '-',
-                    'vt_setup',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"\\tClock pulse at %0d.\\n"',
-                    'last_clk_time',
-                    '-',
-                    'clk_delay',
-                    ')',
-                    ';',
-                'end',
-            'd_set', '<=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'clk_internal', ')',
-         'begin',
-            'if',
-              '(', 'clk_internal', '===', "1 'b x", ')',
-              'out_value', '=', "1 'b x", ';',
-              'else',
-              'out_value', '=', '~', 'd_state', ';',
-             'out', '<=', '#', '(', 'out_delay', ')', 'out_value',
-              ';',
-             'out', '<=', '#', '(', 'out_delay', '+', '2', ')', '0',
-              ';',
-            'd_state', '<=', '0', ';',
-            'clk_internal', '<=', '0', ';',
-            'last_clk_time', '=', '$stime', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/invoke_commands_test.v.parsed.txt Deleted

@@ -1,34 +0,0 @@
-/**************************************************************************
- * $print_invoke_commands example -- Verilog test bench source code
- *
- * Verilog test bench to test the $print_invoke_commands PLI application.
- *
- * NOTE: This test uses two supplemental files: invoke_options_test1.f and
- * invoke_options_test1.f.  This test is designed to be invoked as follows:
- *
- *   <simulator_name> +a +b -f invoke_options_test1.f +c
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *************************************************************************/
-`timescale 1ns / 1ns
-module test;
-
-  initial
-    begin
-      $print_invoke_commands;
-      #1 $finish;
-    end
-
-endmodule
-
-
-  'module', 'test', ';',
-      'initial',
-         'begin',
-          '$print_invoke_commands', ';', '#', '1', '$finish', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/invoke_options_test.v.parsed.txt Deleted

@@ -1,75 +0,0 @@
-/**************************************************************************
- * $test_invoke_options example -- Verilog test bench source code
- *
- * Verilog test bench to test the $test_invoke_options PLI application.
- *
- * NOTE: This test uses two supplemental files: invoke_options_test1.f and
- * invoke_options_test1.f.  This test is designed to be invoked as follows:
- *
- *   <simulator_name> +a +b -f invoke_options_test1.f +c
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *************************************************************************/
-`timescale 1ns / 1ns
-module test;
-  reg option_exists;
-  initial
-    begin
-      option_exists = $test_invoke_options("+test1");
-      if (option_exists)
-        $display("\nSimulation WAS invoked with a +test1 option\n");
-      else
-        $display("\nSimulation was NOT invoked with a +test1 option\n");
-
-      if ($test_invoke_options("+test2"))
-        $display("\nSimulation WAS invoked with a +test2 option\n");
-      else
-        $display("\nSimulation was NOT invoked with a +test2 option\n");
-
-      #1 $finish;
-    end
-
-endmodule
-
-
-  'module', 'test', ';',
-     'reg', 'option_exists', ';',
-       'initial',
-         'begin',
-             'option_exists',
-                '=',
-                '$test_invoke_options', '(', '"+test1"', ')',
-              ';',
-             'if',
-              '(', 'option_exists', ')',
-               '$display',
-                '(',
-                '"\\nSimulation WAS invoked with a +test1 option\\n"',
-                ')',
-                ';',
-              'else',
-               '$display',
-                '(',
-                '"\\nSimulation was NOT invoked with a +test1 option\\n"',
-                ')',
-                ';',
-             'if',
-              '(', '$test_invoke_options', '(', '"+test2"', ')', ')',
-               '$display',
-                '(',
-                '"\\nSimulation WAS invoked with a +test2 option\\n"',
-                ')',
-                ';',
-              'else',
-               '$display',
-                '(',
-                '"\\nSimulation was NOT invoked with a +test2 option\\n"',
-                ')',
-                ';',
-            '#', '1', '$finish', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/jtl2.v.parsed.txt Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/list_cells_test.v.parsed.txt Deleted

@@ -1,271 +0,0 @@
-/**********************************************************************
- * $list_cells example -- Verilog test bench source code
- *
- * Verilog test bench to test the $list_cells PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-
-/**********************************************************************
- * Top-level test bench module for a 4-bit adder model.
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-  reg    3:0 a, b;
-  wire   3:0 sum;
-  reg          ci;
-  wire         co;
-
-  add4 i1 (a, b, ci, sum, co);
-
-  initial
-    begin
-      #1 $list_cells(i1);
-      #1 $finish;
-    end
-endmodule
-
-/**********************************************************************
- * 4-bit adder model, using a 1-bit adder model.
- *********************************************************************/
-`timescale 1ns / 1ns
-module add4 (a, b, ci, sum, co);
-  input  3:0 a, b;
-  input        ci;
-  output 3:0 sum;
-  output       co;
-
-  wire   3:0 a, b, sum;
-  wire         ci, co, co1, co2, co3;
-
-  addbit  a1  (a0, b0, ci,  sum0, co1);
-  addbit  a2  (a1, b1, co1, sum1, co2);
-  addbit  a3  (a2, b2, co2, sum2, co3);
-  addbit  a4  (a3, b3, co3, sum3, co );
-
-endmodule
-
-/**********************************************************************
- * 1-bit adder model, using cells from a library.
- *********************************************************************/
-`timescale 1ns / 1ns
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci, sum, co,
-        n1, n2, n3;
-
-  xor2  u1  (n1, a, b);
-  xor2  u2  (sum, n1, ci);
-  and2  u3  (n2, a, b);
-  and2  u4  (n3, n1, ci);
-  or2   u5  (co, n2, n3);
-
-endmodule
-/**********************************************************************
-* Cell library
- *********************************************************************/
-`resetall
-`celldefine
-`timescale 1ns / 10ps
-module or2 (y, a, b);
-  output y;
-  input  a, b;
-  wire   y, a, b;  //wire data type for cmos
-  or    (y, a, b);
-  specify
-    (a *> y) = 1.0;
-    (b *> y) = 1.0;
-    specparam BaseDelay$   = 2.5;
-    specparam InputLoad$a  = 0.3;
-    specparam InputLoad$b  = 0.3;
-    specparam InputLoad$c  = 0.3;
-    specparam in_cap_pf$a  = 0.02;
-    specparam in_cap_pf$b  = 0.02;
-    specparam in_cap_pf$c  = 0.02;
-    specparam out_cap_pf$  = 0.05;
-  endspecify
-endmodule
-`endcelldefine
-/*********************************************************************/
-`resetall
-`celldefine
-`timescale 1ns / 10ps
-module xor2 (y, a, b);
-  output y;
-  input  a, b;
-  wire   y, a, b;  //wire data type for cmos
-  xor   (y, a, b);
-  specify
-    (a *> y) = 1.0;
-    (b *> y) = 1.0;
-    specparam BaseDelay$   = 2.5;
-    specparam InputLoad$a  = 0.3;
-    specparam InputLoad$b  = 0.3;
-    specparam InputLoad$c  = 0.3;
-    specparam in_cap_pf$a  = 0.02;
-    specparam in_cap_pf$b  = 0.02;
-    specparam in_cap_pf$c  = 0.02;
-    specparam out_cap_pf$  = 0.05;
-  endspecify
-endmodule
-`endcelldefine
-/*********************************************************************/
-`resetall
-`celldefine
-`timescale 1 ns / 10 ps
-module and2 (y, a, b);
-  output y;
-  input  a, b;
-  wire   y, a, b;  //wire data type for cmos
-  and   (y, a, b);
-  specify
-    (a *> y) = 1.0;
-    (b *> y) = 1.0;
-    specparam BaseDelay$   = 2.5;
-    specparam InputLoad$a  = 0.2;
-    specparam InputLoad$b  = 0.2;
-    specparam in_cap_pf$a  = 0.02;
-    specparam in_cap_pf$b  = 0.02;
-    specparam out_cap_pf$  = 0.05;
-  endspecify
-endmodule
-`endcelldefine
-/*********************************************************************/
-
-
-
-  'module', 'test', ';',
-     'reg', '', '3', ':', '0', '', 'a', 'b', ';',
-      'wire', '', '3', ':', '0', '', 'sum', ';',
-      'reg', 'ci', ';',
-      'wire', 'co', ';',
-       'add4',
-        'i1', '(', 'a', 'b', 'ci', 'sum', 'co', ')',
-        ';',
-       'initial',
-         'begin',
-           '#', '1', '$list_cells', '(', 'i1', ')', ';',
-            '#', '1', '$finish', ';',
-          'end',
-    'endmodule',
-   'module', 'add4', '(', 'a', 'b', 'ci', 'sum', 'co', ')', ';',
-     'input', '', '3', ':', '0', '', 'a', 'b', ';',
-      'input', 'ci', ';',
-      'output', '', '3', ':', '0', '', 'sum', ';',
-      'output', 'co', ';',
-      'wire', '', '3', ':', '0', '', 'a', 'b', 'sum', ';',
-      'wire', 'ci', 'co', 'co1', 'co2', 'co3', ';',
-       'addbit',
-         'a1',
-           '(',
-            'a', '', '0', '',
-            'b', '', '0', '',
-            'ci',
-            'sum', '', '0', '',
-            'co1',
-            ')',
-        ';',
-       'addbit',
-         'a2',
-           '(',
-            'a', '', '1', '',
-            'b', '', '1', '',
-            'co1',
-            'sum', '', '1', '',
-            'co2',
-            ')',
-        ';',
-       'addbit',
-         'a3',
-           '(',
-            'a', '', '2', '',
-            'b', '', '2', '',
-            'co2',
-            'sum', '', '2', '',
-            'co3',
-            ')',
-        ';',
-       'addbit',
-         'a4',
-           '(',
-            'a', '', '3', '',
-            'b', '', '3', '',
-            'co3',
-            'sum', '', '3', '',
-            'co',
-            ')',
-        ';',
-    'endmodule',
-    'module',
-      'addbit',
-      '(',
-      'a', 'b', 'ci', 'sum', 'co',
-      ')',
-      ';',
-     'input', 'a', 'b', 'ci', ';',
-      'output', 'sum', 'co', ';',
-      'wire', 'a', 'b', 'ci', 'sum', 'co', 'n1', 'n2', 'n3', ';',
-      'xor2', 'u1', '(', 'n1', 'a', 'b', ')', ';',
-      'xor2', 'u2', '(', 'sum', 'n1', 'ci', ')', ';',
-      'and2', 'u3', '(', 'n2', 'a', 'b', ')', ';',
-      'and2', 'u4', '(', 'n3', 'n1', 'ci', ')', ';',
-      'or2', 'u5', '(', 'co', 'n2', 'n3', ')', ';',
-    'endmodule',
-   'module', 'or2', '(', 'y', 'a', 'b', ')', ';',
-     'output', 'y', ';',
-      'input', 'a', 'b', ';',
-      'wire', 'y', 'a', 'b', ';',
-      'or', '(', 'y', 'a', 'b', ')', ';',
-       'specify',
-        '(', 'a', '*>', 'y', ')', '=', '1.0', ';',
-        '(', 'b', '*>', 'y', ')', '=', '1.0', ';',
-        'specparam', 'BaseDelay$', '=', '2.5', ';',
-        'specparam', 'InputLoad$a', '=', '0.3', ';',
-        'specparam', 'InputLoad$b', '=', '0.3', ';',
-        'specparam', 'InputLoad$c', '=', '0.3', ';',
-        'specparam', 'in_cap_pf$a', '=', '0.02', ';',
-        'specparam', 'in_cap_pf$b', '=', '0.02', ';',
-        'specparam', 'in_cap_pf$c', '=', '0.02', ';',
-        'specparam', 'out_cap_pf$', '=', '0.05', ';',
-        'endspecify',
-    'endmodule',
-   'module', 'xor2', '(', 'y', 'a', 'b', ')', ';',
-     'output', 'y', ';',
-      'input', 'a', 'b', ';',
-      'wire', 'y', 'a', 'b', ';',
-      'xor', '(', 'y', 'a', 'b', ')', ';',
-       'specify',
-        '(', 'a', '*>', 'y', ')', '=', '1.0', ';',
-        '(', 'b', '*>', 'y', ')', '=', '1.0', ';',
-        'specparam', 'BaseDelay$', '=', '2.5', ';',
-        'specparam', 'InputLoad$a', '=', '0.3', ';',
-        'specparam', 'InputLoad$b', '=', '0.3', ';',
-        'specparam', 'InputLoad$c', '=', '0.3', ';',
-        'specparam', 'in_cap_pf$a', '=', '0.02', ';',
-        'specparam', 'in_cap_pf$b', '=', '0.02', ';',
-        'specparam', 'in_cap_pf$c', '=', '0.02', ';',
-        'specparam', 'out_cap_pf$', '=', '0.05', ';',
-        'endspecify',
-    'endmodule',
-   'module', 'and2', '(', 'y', 'a', 'b', ')', ';',
-     'output', 'y', ';',
-      'input', 'a', 'b', ';',
-      'wire', 'y', 'a', 'b', ';',
-      'and', '(', 'y', 'a', 'b', ')', ';',
-       'specify',
-        '(', 'a', '*>', 'y', ')', '=', '1.0', ';',
-        '(', 'b', '*>', 'y', ')', '=', '1.0', ';',
-        'specparam', 'BaseDelay$', '=', '2.5', ';',
-        'specparam', 'InputLoad$a', '=', '0.2', ';',
-        'specparam', 'InputLoad$b', '=', '0.2', ';',
-        'specparam', 'in_cap_pf$a', '=', '0.02', ';',
-        'specparam', 'in_cap_pf$b', '=', '0.02', ';',
-        'specparam', 'out_cap_pf$', '=', '0.05', ';',
-        'endspecify',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/list_nets_test.v.parsed.txt Deleted

@@ -1,88 +0,0 @@
-/**********************************************************************
- * $list_nets example -- Verilog test bench source code
- *
- * Verilog test bench to test the $list_nets PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module top;
-  reg  2:0 test;
-  wire 2:0 results;
-
-  addbit i1 (test0, test1, test2, results0, results1);
-
-  initial
-    begin
-      test = 3'b000;
-      #10 test = 3'b001;
-
-      #10 $list_nets(top);
-      #10 $list_nets(i1);
-
-      #10 $finish;
-    end
-endmodule
-
-/*** A gate level 1 bit adder model ***/
-`timescale 1ns / 1ns
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci, sum, co, n1, n2, n3;
-  wire  3:0 foo = 4'bXZ10;
-
-  xor    (n1, a, b);
-  xor #2 (sum, n1, ci);
-  and    (n2, a, b);
-  and    (n3, n1, ci);
-  or  #2 (co, n2, n3);
-
-endmodule
-/*********************************************************************/
-
-
-
-  'module', 'top', ';',
-     'reg', '', '2', ':', '0', '', 'test', ';',
-      'wire', '', '2', ':', '0', '', 'results', ';',
-       'addbit',
-         'i1',
-           '(',
-            'test', '', '0', '',
-            'test', '', '1', '',
-            'test', '', '2', '',
-            'results', '', '0', '',
-            'results', '', '1', '',
-            ')',
-        ';',
-       'initial',
-         'begin',
-           'test', '=', "3 'b 000", ';',
-            '#', '10', 'test', '=', "3 'b 001", ';',
-            '#', '10', '$list_nets', '(', 'top', ')', ';',
-            '#', '10', '$list_nets', '(', 'i1', ')', ';',
-            '#', '10', '$finish', ';',
-          'end',
-    'endmodule',
-    'module',
-      'addbit',
-      '(',
-      'a', 'b', 'ci', 'sum', 'co',
-      ')',
-      ';',
-     'input', 'a', 'b', 'ci', ';',
-      'output', 'sum', 'co', ';',
-      'wire', 'a', 'b', 'ci', 'sum', 'co', 'n1', 'n2', 'n3', ';',
-      'wire', '', '3', ':', '0', '', 'foo', '=', "4 'b XZ10", ';',
-      'xor', '(', 'n1', 'a', 'b', ')', ';',
-      'xor', '#', '2', '(', 'sum', 'n1', 'ci', ')', ';',
-      'and', '(', 'n2', 'a', 'b', ')', ';',
-      'and', '(', 'n3', 'n1', 'ci', ')', ';',
-      'or', '#', '2', '(', 'co', 'n2', 'n3', ')', ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/list_parameters_test.v.parsed.txt Deleted

@@ -1,102 +0,0 @@
-/**********************************************************************
- * $list_parameters example -- Verilog test bench source code
- *
- * Verilog test bench to test the $list_parameters PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module top;
-  reg  2:0 test;
-  wire 1:0 results;
-
-  addbit i1 (test0, test1, test2, results0, results1);
-
-  initial
-    begin
-      #1 $list_parameters(i1);
-      #1 $finish;
-    end
-endmodule
-
-/*** A gate level 1 bit adder model ***/
-`timescale 1ns / 10ps
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  parameter int_param = 1;
-  parameter real_param = 2.0;
-  parameter string_param = "3.0";
-  parameter 3:0 vector_param = 4'b01zx;
-  
-  wire  a, b, ci, sum, co, n1, n2, n3, n4;
-  wire  3:0 foo = 4'bXZ10;
-
-  xor #1.87       p1 (n1, a, b);    // all transitions have same delay
-  xor #(1.8, 2.2) p2 (sum, n1, ci); //rise, fall delays
-  and             p3 (n2, a, b);
-  and             p4 (n3, n1, ci);
-  or  #4          p5 (co, n2, n3);  //integer delay
-
-endmodule
-/*********************************************************************/
-
-
-
-  'module', 'top', ';',
-     'reg', '', '2', ':', '0', '', 'test', ';',
-      'wire', '', '1', ':', '0', '', 'results', ';',
-       'addbit',
-         'i1',
-           '(',
-            'test', '', '0', '',
-            'test', '', '1', '',
-            'test', '', '2', '',
-            'results', '', '0', '',
-            'results', '', '1', '',
-            ')',
-        ';',
-       'initial',
-         'begin',
-           '#', '1', '$list_parameters', '(', 'i1', ')', ';',
-            '#', '1', '$finish', ';',
-          'end',
-    'endmodule',
-    'module',
-      'addbit',
-      '(',
-      'a', 'b', 'ci', 'sum', 'co',
-      ')',
-      ';',
-     'input', 'a', 'b', 'ci', ';',
-      'output', 'sum', 'co', ';',
-      'parameter', 'int_param', '=', '1', ';',
-      'parameter', 'real_param', '=', '2.0', ';',
-      'parameter', 'string_param', '=', '"3.0"', ';',
-       'parameter',
-        '',
-        '3',
-        ':',
-        '0',
-        '',
-        'vector_param', '=', "4 'b 01zx",
-        ';',
-      'wire', 'a', 'b', 'ci', 'sum', 'co', 'n1', 'n2', 'n3', 'n4', ';',
-      'wire', '', '3', ':', '0', '', 'foo', '=', "4 'b XZ10", ';',
-      'xor', '#', '1.87', 'p1', '(', 'n1', 'a', 'b', ')', ';',
-       'xor',
-        '#', '(', '1.8', '2.2', ')',
-        'p2',
-        '(',
-        'sum', 'n1', 'ci',
-        ')',
-        ';',
-      'and', 'p3', '(', 'n2', 'a', 'b', ')', ';',
-      'and', 'p4', '(', 'n3', 'n1', 'ci', ')', ';',
-      'or', '#', '4', 'p5', '(', 'co', 'n2', 'n3', ')', ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/list_path_delays_test.v.parsed.txt Deleted

@@ -1,102 +0,0 @@
-/**********************************************************************
- * $list_path_delays example -- Verilog test bench source code
- *
- * Verilog test bench to test the $list_path_delays PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module top;
-  reg  2:0 test;
-  wire 1:0 results;
-
-  addbit i1 (test0, test1, test2, results0, results1);
-
-  initial
-    begin
-      #1 $list_path_delays(i1);
-      #1 $finish;
-    end
-endmodule
-
-/*** A gate level 1 bit adder model ***/
-`timescale 1ns / 10ps
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci, sum, co, n1, n2, n3, n4;
-  wire  3:0 foo = 4'bXZ10;
-
-  xor    p1 (n1, a, b);    // all transitions have same delay
-  xor    p2 (sum, n1, ci); //rise, fall delays
-  and    p3 (n2, a, b);
-  and    p4 (n3, n1, ci);
-//  or     p5 (co, n2, n3);  //integer delay
-  bufif1 p6 (co, n2, 1'b0); //all delay values
-
-  specify
-    (a *> sum) = 3.1415;
-    (b *> sum) = (1:2:3, 4:5:6, 7:8:9);
-    (ci *> sum, co) = (1, 2, 3, 4, 5, 6);
-  endspecify
-
-endmodule
-/*********************************************************************/
-
-
-
-  'module', 'top', ';',
-     'reg', '', '2', ':', '0', '', 'test', ';',
-      'wire', '', '1', ':', '0', '', 'results', ';',
-       'addbit',
-         'i1',
-           '(',
-            'test', '', '0', '',
-            'test', '', '1', '',
-            'test', '', '2', '',
-            'results', '', '0', '',
-            'results', '', '1', '',
-            ')',
-        ';',
-       'initial',
-         'begin',
-           '#', '1', '$list_path_delays', '(', 'i1', ')', ';',
-            '#', '1', '$finish', ';',
-          'end',
-    'endmodule',
-    'module',
-      'addbit',
-      '(',
-      'a', 'b', 'ci', 'sum', 'co',
-      ')',
-      ';',
-     'input', 'a', 'b', 'ci', ';',
-      'output', 'sum', 'co', ';',
-      'wire', 'a', 'b', 'ci', 'sum', 'co', 'n1', 'n2', 'n3', 'n4', ';',
-      'wire', '', '3', ':', '0', '', 'foo', '=', "4 'b XZ10", ';',
-      'xor', 'p1', '(', 'n1', 'a', 'b', ')', ';',
-      'xor', 'p2', '(', 'sum', 'n1', 'ci', ')', ';',
-      'and', 'p3', '(', 'n2', 'a', 'b', ')', ';',
-      'and', 'p4', '(', 'n3', 'n1', 'ci', ')', ';',
-      'bufif1', 'p6', '(', 'co', 'n2', "1 'b 0", ')', ';',
-       'specify',
-        '(', 'a', '*>', 'sum', ')', '=', '3.1415', ';',
-         '(', 'b', '*>', 'sum', ')',
-          '=',
-           '(',
-             '1', ':', '2', ':', '3',
-              '4', ':', '5', ':', '6',
-              '7', ':', '8', ':', '9',
-            ')',
-          ';',
-         '(', 'ci', '*>', 'sum', 'co', ')',
-          '=',
-          '(', '1', '2', '3', '4', '5', '6', ')',
-          ';',
-        'endspecify',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/list_pathout_ports_test.v.parsed.txt Deleted

@@ -1,108 +0,0 @@
-/**********************************************************************
- * $list_pathout_ports example -- Verilog test bench source code
- *
- * Verilog test bench to test the $list_pathout_ports PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-  reg  a, b, ci, clk;
-  wire sum, co, foo;
-
-  addbit i1 (a, b, ci, sum, co, foo);
-
-  initial
-    begin
-      $monitor("At %0d: \t a=%b  b=%b  ci=%b  sum=%b  co=%b",
-               $time, a, b, ci, sum, co);
-      clk = 0;
-      a = 0;
-      b = 0;
-      ci = 0;
-      #10 a = 1;
-      #10 b = 1;
-
-      #10 $list_pathout_ports(i1);
-
-      #10 $finish;
-    end
-endmodule
-
-/*** A gate level 1 bit adder model ***/
-`timescale 1ns / 1ns
-module addbit (a, b, ci, sum, co, foo);
-  input  a, b, ci;
-  output sum, co, foo;
-
-  wire  a, b, ci, sum, co, foo,
-        n1, n2, n3;
-
-  xor    (n1, a, b);
-  xor    (sum, n1, ci);
-  and    (n2, a, b);
-  and    (n3, n1, ci);
-  or     (co, n2, n3);
-
-  specify
-    (a,b,ci => sum) = 2;
-    (a,b,ci => co)  = 3;
-  endspecify
-
-endmodule
-/*********************************************************************/
-
-
-
-  'module', 'test', ';',
-     'reg', 'a', 'b', 'ci', 'clk', ';',
-      'wire', 'sum', 'co', 'foo', ';',
-       'addbit',
-        'i1', '(', 'a', 'b', 'ci', 'sum', 'co', 'foo', ')',
-        ';',
-       'initial',
-         'begin',
-            '$monitor',
-              '(',
-              '"At %0d: \\t a=%b  b=%b  ci=%b  sum=%b  co=%b"',
-              '$time',
-              'a',
-              'b',
-              'ci',
-              'sum',
-              'co',
-              ')',
-              ';',
-            'clk', '=', '0', ';',
-            'a', '=', '0', ';',
-            'b', '=', '0', ';',
-            'ci', '=', '0', ';',
-            '#', '10', 'a', '=', '1', ';',
-            '#', '10', 'b', '=', '1', ';',
-            '#', '10', '$list_pathout_ports', '(', 'i1', ')', ';',
-            '#', '10', '$finish', ';',
-          'end',
-    'endmodule',
-    'module',
-      'addbit',
-      '(',
-      'a', 'b', 'ci', 'sum', 'co', 'foo',
-      ')',
-      ';',
-     'input', 'a', 'b', 'ci', ';',
-      'output', 'sum', 'co', 'foo', ';',
-      'wire', 'a', 'b', 'ci', 'sum', 'co', 'foo', 'n1', 'n2', 'n3', ';',
-      'xor', '(', 'n1', 'a', 'b', ')', ';',
-      'xor', '(', 'sum', 'n1', 'ci', ')', ';',
-      'and', '(', 'n2', 'a', 'b', ')', ';',
-      'and', '(', 'n3', 'n1', 'ci', ')', ';',
-      'or', '(', 'co', 'n2', 'n3', ')', ';',
-       'specify',
-        '(', 'a', 'b', 'ci', '=>', 'sum', ')', '=', '2', ';',
-        '(', 'a', 'b', 'ci', '=>', 'co', ')', '=', '3', ';',
-        'endspecify',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/list_prim_delays_test.v.parsed.txt Deleted

@@ -1,100 +0,0 @@
-/**********************************************************************
- * $list_prim_delays example -- Verilog test bench source code
- *
- * Verilog test bench to test the $list_prim_delays PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module top;
-  reg  2:0 test;
-  wire 1:0 results;
-
-  addbit i1 (test0, test1, test2, results0, results1);
-
-  initial
-    begin
-      #1 $list_prim_delays(i1);
-      #1 $finish;
-    end
-endmodule
-
-/*** A gate level 1 bit adder model ***/
-`timescale 1ns / 10ps
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci, sum, co, n1, n2, n3, n4;
-  wire  3:0 foo = 4'bXZ10;
-
-  xor #1.87       p1 (n1, a, b);    // all transitions have same delay
-  xor #(1.8, 2.2) p2 (sum, n1, ci); //rise, fall delays
-  and             p3 (n2, a, b);
-  and             p4 (n3, n1, ci);
-  or  #4          p5 (co, n2, n3);  //integer delay
-  
-  bufif1 #(1:2:3, 4:5:6, 7:8:9) p6 (n4, n2, n3); //all delay values
-
-endmodule
-/*********************************************************************/
-
-
-
-  'module', 'top', ';',
-     'reg', '', '2', ':', '0', '', 'test', ';',
-      'wire', '', '1', ':', '0', '', 'results', ';',
-       'addbit',
-         'i1',
-           '(',
-            'test', '', '0', '',
-            'test', '', '1', '',
-            'test', '', '2', '',
-            'results', '', '0', '',
-            'results', '', '1', '',
-            ')',
-        ';',
-       'initial',
-         'begin',
-           '#', '1', '$list_prim_delays', '(', 'i1', ')', ';',
-            '#', '1', '$finish', ';',
-          'end',
-    'endmodule',
-    'module',
-      'addbit',
-      '(',
-      'a', 'b', 'ci', 'sum', 'co',
-      ')',
-      ';',
-     'input', 'a', 'b', 'ci', ';',
-      'output', 'sum', 'co', ';',
-      'wire', 'a', 'b', 'ci', 'sum', 'co', 'n1', 'n2', 'n3', 'n4', ';',
-      'wire', '', '3', ':', '0', '', 'foo', '=', "4 'b XZ10", ';',
-      'xor', '#', '1.87', 'p1', '(', 'n1', 'a', 'b', ')', ';',
-       'xor',
-        '#', '(', '1.8', '2.2', ')',
-        'p2',
-        '(',
-        'sum', 'n1', 'ci',
-        ')',
-        ';',
-      'and', 'p3', '(', 'n2', 'a', 'b', ')', ';',
-      'and', 'p4', '(', 'n3', 'n1', 'ci', ')', ';',
-      'or', '#', '4', 'p5', '(', 'co', 'n2', 'n3', ')', ';',
-       'bufif1',
-         '#',
-          '(',
-           '1', ':', '2', ':', '3',
-            '4', ':', '5', ':', '6',
-            '7', ':', '8', ':', '9',
-          ')',
-        'p6',
-        '(',
-        'n4', 'n2', 'n3',
-        ')',
-        ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/load_in.v.parsed.txt Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/load_out.v.parsed.txt Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/mem_arb.v.parsed.txt Deleted

@@ -1,291 +0,0 @@
-/////////////////////////////////////////////////////////////////////
-////                                                             ////
-////  Memory Buffer Arbiter                                      ////
-////  Arbitrates between the internal DMA and external bus       ////
-////  interface for the internal buffer memory                   ////
-////                                                             ////
-////  Author: Rudolf Usselmann                                   ////
-////          rudi@asics.ws                                      ////
-////                                                             ////
-////                                                             ////
-////  Downloaded from: http://www.opencores.org/cores/usb/       ////
-////                                                             ////
-/////////////////////////////////////////////////////////////////////
-////                                                             ////
-//// Copyright (C) 2000 Rudolf Usselmann                         ////
-////                    rudi@asics.ws                            ////
-////                                                             ////
-//// This source file may be used and distributed without        ////
-//// restriction provided that this copyright statement is not   ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer.////
-////                                                             ////
-////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
-//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
-//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
-//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
-//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
-//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
-//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
-//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
-//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
-//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
-//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
-//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
-//// POSSIBILITY OF SUCH DAMAGE.                                 ////
-////                                                             ////
-/////////////////////////////////////////////////////////////////////
-
-//  CVS Log
-//
-//  $Id: mem_arb.v,v 1.0 2001/03/07 09:17:12 rudi Exp $
-//
-//  $Date: 2001/03/07 09:17:12 $
-//  $Revision: 1.0 $
-//  $Author: rudi $
-//  $Locker:  $
-//  $State: Exp $
-//
-// Change History:
-//               $Log: mem_arb.v,v $
-//               Revision 1.0  2001/03/07 09:17:12  rudi
-//
-//
-//               Changed all revisions to revision 1.0. This is because OpenCores CVS
-//               interface could not handle the original '0.1' revision ....
-//
-//               Revision 0.1.0.1  2001/02/28 08:10:52  rudi
-//               Initial Release
-//
-//
-
-`include "usb_defines.v"
-
-module mem_arb(	phy_clk, wclk, rst,
-
-		// SSRAM Interface
-		radr, rdin, rdout, rre, rwe,
-
-		// IDMA Memory Interface
-		madr, mdout, mdin, mwe, mreq, mack,
-
-		// WISHBONE Memory Interface
-		wadr, wdout, wdin, wwe, wreq, wack
-
-		);
-
-input		phy_clk, wclk, rst;
-
-output	14:0	radr;
-input	31:0	rdin;
-output	31:0	rdout;
-output		rre, rwe;
-
-input	14:0	madr;
-output	31:0	mdout;
-input	31:0	mdin;
-input		mwe;
-input		mreq;
-output		mack;
-
-input	14:0	wadr;
-output	31:0	wdout;
-input	31:0	wdin;
-input		wwe;
-input		wreq;
-output		wack;
-
-///////////////////////////////////////////////////////////////////
-//
-// Local Wires and Registers
-//
-
-wire		wsel;
-reg	14:0	radr;
-reg	31:0	rdout;
-reg		rwe;
-reg		mack;
-reg		mack_r;
-wire		mcyc;
-reg		wack;
-wire		wcyc;
-reg		wwe_r;
-
-///////////////////////////////////////////////////////////////////
-//
-// Memory Arbiter Logic
-//
-
-// IDMA has always first priority
-
-// -----------------------------------------
-// Ctrl Signals
-
-assign wsel = (wreq | wcyc) & !mreq;
-
-// -----------------------------------------
-// SSRAM Specific
-// Data Path
-always @(wsel or wdin or mdin)
-	if(wsel)	rdout = wdin;
-	else		rdout = mdin;
-
-// Address Path
-always @(wsel or wadr or madr)
-	if(wsel)	radr = wadr;
-	else		radr = madr;
-
-// Write Enable Path
-always @(wsel or wwe_r or mwe or mcyc or wcyc)
-	if(wsel)	rwe = wwe_r & wcyc;
-	else		rwe = mwe & mcyc;
-
-assign rre = 1;
-
-// -----------------------------------------
-// IDMA specific
-assign mdout = rdin;
-
-always @(mreq)
-	mack = mreq;
-
-always @(posedge phy_clk)
-	mack_r <= #1 mack;
-
-assign mcyc = mack;	// Qualifier for writes
-
-// -----------------------------------------
-// WISHBONE specific
-assign wdout = rdin;
-
-reg	wack_d, wack_r;
-
-always @(wack_d or mreq)
-	wack = wack_d & !mreq;
-
-always @(posedge phy_clk)
-	wack_r <= #1 wack_d;
-
-always @(wreq or mreq)
-	if(!mreq)	wack_d = wreq;
-	else		wack_d = 0;
-
-always @(posedge phy_clk)
-	wwe_r <= #1 wwe;
-
-assign wcyc = wack_d | wack_r;	// Qualifier for writes
-
-endmodule
-
-
-
-   'module',
-      'mem_arb',
-      '(',
-       'phy_clk',
-        'wclk',
-        'rst',
-        'radr',
-        'rdin',
-        'rdout',
-        'rre',
-        'rwe',
-        'madr',
-        'mdout',
-        'mdin',
-        'mwe',
-        'mreq',
-        'mack',
-        'wadr',
-        'wdout',
-        'wdin',
-        'wwe',
-        'wreq',
-        'wack',
-      ')',
-      ';',
-     'input', 'phy_clk', 'wclk', 'rst', ';',
-      'output', '', '14', ':', '0', '', 'radr', ';',
-      'input', '', '31', ':', '0', '', 'rdin', ';',
-      'output', '', '31', ':', '0', '', 'rdout', ';',
-      'output', 'rre', 'rwe', ';',
-      'input', '', '14', ':', '0', '', 'madr', ';',
-      'output', '', '31', ':', '0', '', 'mdout', ';',
-      'input', '', '31', ':', '0', '', 'mdin', ';',
-      'input', 'mwe', ';',
-      'input', 'mreq', ';',
-      'output', 'mack', ';',
-      'input', '', '14', ':', '0', '', 'wadr', ';',
-      'output', '', '31', ':', '0', '', 'wdout', ';',
-      'input', '', '31', ':', '0', '', 'wdin', ';',
-      'input', 'wwe', ';',
-      'input', 'wreq', ';',
-      'output', 'wack', ';',
-      'wire', 'wsel', ';',
-      'reg', '', '14', ':', '0', '', 'radr', ';',
-      'reg', '', '31', ':', '0', '', 'rdout', ';',
-      'reg', 'rwe', ';',
-      'reg', 'mack', ';',
-      'reg', 'mack_r', ';',
-      'wire', 'mcyc', ';',
-      'reg', 'wack', ';',
-      'wire', 'wcyc', ';',
-      'reg', 'wwe_r', ';',
-       'assign',
-         'wsel',
-          '=',
-          '(',
-          'wreq', '|', 'wcyc',
-          ')',
-          '&',
-          '!',
-          'mreq',
-        ';',
-       'always',
-        '@', '(', 'wsel', 'wdin', 'mdin', ')',
-         'if',
-          '(', 'wsel', ')',
-          'rdout', '=', 'wdin', ';',
-          'else',
-          'rdout', '=', 'mdin', ';',
-       'always',
-        '@', '(', 'wsel', 'wadr', 'madr', ')',
-         'if',
-          '(', 'wsel', ')',
-          'radr', '=', 'wadr', ';',
-          'else',
-          'radr', '=', 'madr', ';',
-       'always',
-        '@', '(', 'wsel', 'wwe_r', 'mwe', 'mcyc', 'wcyc', ')',
-         'if',
-          '(', 'wsel', ')',
-          'rwe', '=', 'wwe_r', '&', 'wcyc', ';',
-          'else',
-          'rwe', '=', 'mwe', '&', 'mcyc', ';',
-      'assign', 'rre', '=', '1', ';',
-      'assign', 'mdout', '=', 'rdin', ';',
-      'always', '@', '(', 'mreq', ')', 'mack', '=', 'mreq', ';',
-       'always',
-        '@', '(', 'posedge', 'phy_clk', ')',
-        'mack_r', '<=', '#', '1', 'mack', ';',
-      'assign', 'mcyc', '=', 'mack', ';',
-      'assign', 'wdout', '=', 'rdin', ';',
-      'reg', 'wack_d', 'wack_r', ';',
-       'always',
-        '@', '(', 'wack_d', 'mreq', ')',
-        'wack', '=', 'wack_d', '&', '!', 'mreq', ';',
-       'always',
-        '@', '(', 'posedge', 'phy_clk', ')',
-        'wack_r', '<=', '#', '1', 'wack_d', ';',
-       'always',
-        '@', '(', 'wreq', 'mreq', ')',
-         'if',
-          '(', '!', 'mreq', ')',
-          'wack_d', '=', 'wreq', ';',
-          'else',
-          'wack_d', '=', '0', ';',
-       'always',
-        '@', '(', 'posedge', 'phy_clk', ')',
-        'wwe_r', '<=', '#', '1', 'wwe', ';',
-      'assign', 'wcyc', '=', 'wack_d', '|', 'wack_r', ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/mipd_delays_test.v.parsed.txt Deleted

@@ -1,97 +0,0 @@
-/**********************************************************************
- * $append_gate_delays example -- Verilog test bench source code
- *
- * Verilog test bench to test the $append_gate_delays PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 100ps
-module top;
-  reg  2:0 test;
-  wire 1:0 results;
-
-  addbit i1 (test0, test1, test2, results0, results1);
-
-  initial
-    begin
-      $mipd_delays(i1.ci, 1.4, 1.6, 1.9, 1.1, 1.3, 1.5, 0.6, 0.8, 0.9);
-      #1 $finish;
-    end
-endmodule
-
-/*** A gate level 1 bit adder model ***/
-`timescale 1ns / 10ps
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci, sum, co, n1, n2, n3, n4;
-
-  xor #1.87       p1 (n1, a, b);    // all transitions have same delay
-  xor #(1.8, 2.2) p2 (sum, n1, ci); //rise, fall delays
-  and             p3 (n2, a, b);
-  and             p4 (n3, n1, ci);
-  or  #4          p5 (co, n2, n3);  //integer delay
-  
-endmodule
-/*********************************************************************/
-
-
-
-  'module', 'top', ';',
-     'reg', '', '2', ':', '0', '', 'test', ';',
-      'wire', '', '1', ':', '0', '', 'results', ';',
-       'addbit',
-         'i1',
-           '(',
-            'test', '', '0', '',
-            'test', '', '1', '',
-            'test', '', '2', '',
-            'results', '', '0', '',
-            'results', '', '1', '',
-            ')',
-        ';',
-       'initial',
-         'begin',
-            '$mipd_delays',
-              '(',
-              'i1.ci',
-              '1.4',
-              '1.6',
-              '1.9',
-              '1.1',
-              '1.3',
-              '1.5',
-              '0.6',
-              '0.8',
-              '0.9',
-              ')',
-              ';',
-            '#', '1', '$finish', ';',
-          'end',
-    'endmodule',
-    'module',
-      'addbit',
-      '(',
-      'a', 'b', 'ci', 'sum', 'co',
-      ')',
-      ';',
-     'input', 'a', 'b', 'ci', ';',
-      'output', 'sum', 'co', ';',
-      'wire', 'a', 'b', 'ci', 'sum', 'co', 'n1', 'n2', 'n3', 'n4', ';',
-      'xor', '#', '1.87', 'p1', '(', 'n1', 'a', 'b', ')', ';',
-       'xor',
-        '#', '(', '1.8', '2.2', ')',
-        'p2',
-        '(',
-        'sum', 'n1', 'ci',
-        ')',
-        ';',
-      'and', 'p3', '(', 'n2', 'a', 'b', ')', ';',
-      'and', 'p4', '(', 'n3', 'n1', 'ci', ')', ';',
-      'or', '#', '4', 'p5', '(', 'co', 'n2', 'n3', ')', ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/mult16.v.parsed.txt Deleted

@@ -1,312 +0,0 @@
-// **** Here's a simple, sequential multiplier.  Very simple, unsigned..
-// Not very well tested, play with testbench, use at your own risk, blah blah blah..
-//
-
-//
-// Unsigned 16-bit multiply (multiply two 16-bit inputs to get a 32-bit output)
-//
-// Present data and assert start synchronous with clk.
-// Assert start for ONLY one cycle.
-// Wait N cycles for answer (at most).  Answer will remain stable until next start.
-// You may use DONE signal as handshake.
-//
-// Written by tom coonan
-//
-module mult16 (clk, resetb, start, done, ain, bin, yout);
-parameter N = 16;
-input			clk;
-input			resetb;
-input			start; // Register the ain and bin inputs (they can change afterwards)
-input N-1:0		ain;
-input N-1:0		bin;
-output 2*N-1:0	yout;
-output			done;
-
-reg 2*N-1:0		a;
-reg N-1:0		b;
-reg 2*N-1:0		yout;
-
-reg		done;
-
-always @(posedge clk or negedge resetb) begin
-   if (~resetb) begin
-      a <= 0;
-      b <= 0;
-      yout <= 0;
-      done <= 1'b1;
-   end
-   else begin
-      // Load will register the input and clear the counter.
-      if (start) begin
-         a    <= ain;
-         b    <= bin;
-         yout <= 0;
-         done <= 0;
-      end
-      else begin
-         // Go until b is zero
-         if (~done) begin
-            if (b != 0) begin
-               // If '1' then add a to sum
-               if (b0) begin
-                  yout <= yout + a;
-               end
-               b <= b >> 1;
-               a <= a << 1;
-               //$display ("a = %b, b = %b, yout = %b", a,b,yout);
-            end
-            else begin
-               done <= 1'b1;
-            end
-         end
-      end
-   end
-end
-endmodule
-
-// synopsys translate_off
-//`define TESTMULT16
-`ifdef TESTMULT16
-
-module testmult16;
-reg clk, resetb, start;
-reg 15:0 a;
-reg 15:0 b;
-wire 31:0 y;
-wire done;
-
-mult16 mult16inst (clk, resetb, start, done, a, b, y);
-
-initial begin
-   clk = 0;
-   forever begin
-      #10 clk = ~clk;
-   end
-end
-
-initial begin
-   resetb = 0;
-   #30 resetb = 1;
-end
-
-integer num_errors;
-parameter MAX_TRIALS = 1000;
-
-initial begin
-   $dumpfile ("multdiv.vcd");
-   $dumpvars (0,testmult16);   
-   num_errors = 0;
-
-   #100;
-
-   // Do a bunch of random multiplies
-   repeat (MAX_TRIALS) begin
-      test_multiply ($random, $random);
-   end
-   
-   // Special cases
-   test_multiply ($random, 1);
-   test_multiply (1, $random);
-   test_multiply ($random, 0);
-   test_multiply (0, $random);
-   
-   $display ("Done.  %0d Errors", num_errors);
-   #800;
-   $finish;
-end
-
-task test_multiply;
-   input 15:0 aarg;
-   input 15:0 barg;
-   
-   integer expected_answer;
-   
-   begin
-      if (~done) begin
-         $display ("Multiplier is Busy!!");
-      end
-      else begin
-         @(negedge clk);
-         start = 1;
-         a = aarg;
-         b = barg;
-         @(negedge clk) start = 0;
-         @(posedge done); 
-         expected_answer = a*b;
-         $display ("%0d * %0d = %0h, Reality = %0h", a, b, y, expected_answer);
-         if (y !== expected_answer) begin
-            $display ("   FAILURE!");
-            num_errors = num_errors + 1;
-         end
-      end
-   end
-endtask
-
-endmodule
-`endif
-     
-
-   'module',
-      'mult16',
-      '(',
-      'clk', 'resetb', 'start', 'done', 'ain', 'bin', 'yout',
-      ')',
-      ';',
-     'parameter', 'N', '=', '16', ';',
-      'input', 'clk', ';',
-      'input', 'resetb', ';',
-      'input', 'start', ';',
-      'input', '', 'N', '-', '1', ':', '0', '', 'ain', ';',
-      'input', '', 'N', '-', '1', ':', '0', '', 'bin', ';',
-      'output', '', '2', '*', 'N', '-', '1', ':', '0', '', 'yout', ';',
-      'output', 'done', ';',
-      'reg', '', '2', '*', 'N', '-', '1', ':', '0', '', 'a', ';',
-      'reg', '', 'N', '-', '1', ':', '0', '', 'b', ';',
-      'reg', '', '2', '*', 'N', '-', '1', ':', '0', '', 'yout', ';',
-      'reg', 'done', ';',
-       'always',
-        '@', '(', 'posedge', 'clk', 'negedge', 'resetb', ')',
-         'begin',
-            'if',
-              '(', '~', 'resetb', ')',
-               'begin',
-                 'a', '<=', '0', ';',
-                  'b', '<=', '0', ';',
-                  'yout', '<=', '0', ';',
-                  'done', '<=', "1 'b 1", ';',
-                'end',
-              'else',
-               'begin',
-                  'if',
-                    '(', 'start', ')',
-                     'begin',
-                       'a', '<=', 'ain', ';',
-                        'b', '<=', 'bin', ';',
-                        'yout', '<=', '0', ';',
-                        'done', '<=', '0', ';',
-                      'end',
-                    'else',
-                     'begin',
-                        'if',
-                          '(', '~', 'done', ')',
-                           'begin',
-                              'if',
-                                '(', 'b', '!=', '0', ')',
-                                 'begin',
-                                    'if',
-                                      '(', 'b', '', '0', '', ')',
-                                       'begin',
-                                           'yout',
-                                              '<=',
-                                              'yout',
-                                              '+',
-                                              'a',
-                                            ';',
-                                        'end',
-                                    'b', '<=', 'b', '>>', '1', ';',
-                                    'a', '<=', 'a', '<<', '1', ';',
-                                  'end',
-                                'else',
-                                 'begin',
-                                  'done', '<=', "1 'b 1", ';',
-                                  'end',
-                            'end',
-                      'end',
-                'end',
-          'end',
-    'endmodule',
-   'module', 'testmult16', ';',
-     'reg', 'clk', 'resetb', 'start', ';',
-      'reg', '', '15', ':', '0', '', 'a', ';',
-      'reg', '', '15', ':', '0', '', 'b', ';',
-      'wire', '', '31', ':', '0', '', 'y', ';',
-      'wire', 'done', ';',
-       'mult16',
-         'mult16inst',
-           '(',
-            'clk',
-            'resetb',
-            'start',
-            'done',
-            'a',
-            'b',
-            'y',
-            ')',
-        ';',
-       'initial',
-         'begin',
-           'clk', '=', '0', ';',
-             'forever',
-               'begin',
-                '#', '10', 'clk', '=', '~', 'clk', ';',
-                'end',
-          'end',
-       'initial',
-         'begin',
-           'resetb', '=', '0', ';',
-            '#', '30', 'resetb', '=', '1', ';',
-          'end',
-      'integer', 'num_errors', ';',
-      'parameter', 'MAX_TRIALS', '=', '1000', ';',
-       'initial',
-         'begin',
-           '$dumpfile', '(', '"multdiv.vcd"', ')', ';',
-            '$dumpvars', '(', '0', 'testmult16', ')', ';',
-            'num_errors', '=', '0', ';',
-            '#', '100', ';',
-             'repeat',
-              '(',
-              'MAX_TRIALS',
-              ')',
-               'begin',
-                'test_multiply', '(', '$random', '$random', ')', ';',
-                'end',
-            'test_multiply', '(', '$random', '1', ')', ';',
-            'test_multiply', '(', '1', '$random', ')', ';',
-            'test_multiply', '(', '$random', '0', ')', ';',
-            'test_multiply', '(', '0', '$random', ')', ';',
-            '$display', '(', '"Done.  %0d Errors"', 'num_errors', ')', ';',
-            '#', '800', ';',
-            '$finish', ';',
-          'end',
-       'task',
-        'test_multiply',
-        ';',
-        'input', '', '15', ':', '0', '', 'aarg', ';',
-        'input', '', '15', ':', '0', '', 'barg', ';',
-        'integer', 'expected_answer', ';',
-         'begin',
-            'if',
-              '(', '~', 'done', ')',
-               'begin',
-                '$display', '(', '"Multiplier is Busy!!"', ')', ';',
-                'end',
-              'else',
-               'begin',
-                 '@', '(', 'negedge', 'clk', ')', ';',
-                  'start', '=', '1', ';',
-                  'a', '=', 'aarg', ';',
-                  'b', '=', 'barg', ';',
-                   '@', '(', 'negedge', 'clk', ')',
-                    'start', '=', '0', ';',
-                  '@', '(', 'posedge', 'done', ')', ';',
-                  'expected_answer', '=', 'a', '*', 'b', ';',
-                   '$display',
-                    '(',
-                    '"%0d * %0d = %0h, Reality = %0h"',
-                    'a',
-                    'b',
-                    'y',
-                    'expected_answer',
-                    ')',
-                    ';',
-                   'if',
-                    '(', 'y', '!==', 'expected_answer', ')',
-                     'begin',
-                       '$display', '(', '"   FAILURE!"', ')', ';',
-                        'num_errors', '=', 'num_errors', '+', '1', ';',
-                      'end',
-                'end',
-          'end',
-        'endtask',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/multi21_udp.v.parsed.txt Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/my_monitor1_test.v.parsed.txt Deleted

@@ -1,61 +0,0 @@
-/**********************************************************************
- * $my_monitor1 example -- Verilog test bench source code
- *
- * Verilog test bench to test the $my_monitor1 PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-
-  reg 3:0 q, d;
-  reg clock;
-  
-  initial
-    $my_monitor1(clock, q, d);
-    
-  always @(posedge clock)
-    q <= #1 d;
-    
-  initial
-    begin
-      clock = 0;
-      forever #5 clock = ~ clock;
-    end
-  
-  initial
-    begin
-      d = 4'h0;
-      @(negedge clock) d = 4'h1;
-      @(negedge clock) d = 4'hF;
-      @(negedge clock) $finish;
-    end
-endmodule
-      
-
-  'module', 'test', ';',
-     'reg', '', '3', ':', '0', '', 'q', 'd', ';',
-      'reg', 'clock', ';',
-      'initial', '$my_monitor1', '(', 'clock', 'q', 'd', ')', ';',
-       'always',
-        '@', '(', 'posedge', 'clock', ')',
-        'q', '<=', '#', '1', 'd', ';',
-       'initial',
-         'begin',
-           'clock', '=', '0', ';',
-            'forever', '#', '5', 'clock', '=', '~', 'clock', ';',
-          'end',
-       'initial',
-         'begin',
-           'd', '=', "4 'h 0", ';',
-             '@', '(', 'negedge', 'clock', ')',
-              'd', '=', "4 'h 1", ';',
-             '@', '(', 'negedge', 'clock', ')',
-              'd', '=', "4 'h F", ';',
-            '@', '(', 'negedge', 'clock', ')', '$finish', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/my_monitor2_test.v.parsed.txt Deleted

@@ -1,61 +0,0 @@
-/**********************************************************************
- * $my_monitor2 example -- Verilog test bench source code
- *
- * Verilog test bench to test the $my_monitor1 PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-
-  reg 3:0 q, d;
-  reg clock;
-  
-  initial
-    $my_monitor2(clock, q, d);
-    
-  always @(posedge clock)
-    q <= #1 d;
-    
-  initial
-    begin
-      clock = 0;
-      forever #5 clock = ~ clock;
-    end
-  
-  initial
-    begin
-      d = 4'h0;
-      @(negedge clock) d = 4'h1;
-      @(negedge clock) d = 4'hF;
-      @(negedge clock) $finish;
-    end
-endmodule
-      
-
-  'module', 'test', ';',
-     'reg', '', '3', ':', '0', '', 'q', 'd', ';',
-      'reg', 'clock', ';',
-      'initial', '$my_monitor2', '(', 'clock', 'q', 'd', ')', ';',
-       'always',
-        '@', '(', 'posedge', 'clock', ')',
-        'q', '<=', '#', '1', 'd', ';',
-       'initial',
-         'begin',
-           'clock', '=', '0', ';',
-            'forever', '#', '5', 'clock', '=', '~', 'clock', ';',
-          'end',
-       'initial',
-         'begin',
-           'd', '=', "4 'h 0", ';',
-             '@', '(', 'negedge', 'clock', ')',
-              'd', '=', "4 'h 1", ';',
-             '@', '(', 'negedge', 'clock', ')',
-              'd', '=', "4 'h F", ';',
-            '@', '(', 'negedge', 'clock', ')', '$finish', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/my_monitor_test.v.parsed.txt Deleted

@@ -1,85 +0,0 @@
-/**********************************************************************
- * $my_monitor example -- Verilog test bench source code
- *
- * Verilog test bench to test the $my_monitor PLI application on
- * a 1-bit adder modeled using RTL code.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module top;
-  integer    test;
-  tri  1:0 results;
-
-  addbit i1 (test0, test1, test2, results0, results1);
-
-  initial
-    begin
-      $my_monitor(results0);
-      $my_monitor(i1.sum, i1.co);
-      test = 3'b000;
-      #10 test = 3'b001;
-      #10 test = 3'b011;
-      #10 $finish;
-    end
-endmodule
-
-/*** An RTL level 1 bit adder model ***/
-`timescale 1ns / 1ns
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci;
-  reg   sum, co;
-
-  always @(a or b or ci)
-    {co, sum} = a + b + ci;
-
-endmodule
-/*********************************************************************/
-
-
-
-  'module', 'top', ';',
-     'integer', 'test', ';',
-      'tri', '', '1', ':', '0', '', 'results', ';',
-       'addbit',
-         'i1',
-           '(',
-            'test', '', '0', '',
-            'test', '', '1', '',
-            'test', '', '2', '',
-            'results', '', '0', '',
-            'results', '', '1', '',
-            ')',
-        ';',
-       'initial',
-         'begin',
-           '$my_monitor', '(', 'results', '', '0', '', ')', ';',
-            '$my_monitor', '(', 'i1.sum', 'i1.co', ')', ';',
-            'test', '=', "3 'b 000", ';',
-            '#', '10', 'test', '=', "3 'b 001", ';',
-            '#', '10', 'test', '=', "3 'b 011", ';',
-            '#', '10', '$finish', ';',
-          'end',
-    'endmodule',
-    'module',
-      'addbit',
-      '(',
-      'a', 'b', 'ci', 'sum', 'co',
-      ')',
-      ';',
-     'input', 'a', 'b', 'ci', ';',
-      'output', 'sum', 'co', ';',
-      'wire', 'a', 'b', 'ci', ';',
-      'reg', 'sum', 'co', ';',
-       'always',
-        '@', '(', 'a', 'b', 'ci', ')',
-         '{', 'co', 'sum', '}', '=', 'a', '+', 'b', '+', 'ci',
-          ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/my_strobe_test.v.parsed.txt Deleted

@@ -1,198 +0,0 @@
-/**********************************************************************
- * $my_strobe example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $my_strobe PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-  reg  a, b, ci, clk;
-  reg  sum, co;
-
-  always @(a or b or ci)
-    {co,sum} = a + b + ci;
-
-  initial
-    begin
-      $strobe ("$strobe   : At %0d: \t %m.sum = %d",$time, sum);
-      $display("$display  : At %0d: \t %m.sum = %d",$time, sum);
-      $my_strobe(sum);
-      a = 0; b = 0; ci = 0;
-
-      #10 $display("");
-      a = 1;
-      $my_strobe(sum);
-      $strobe ("$strobe   : At %0d: \t %m.sum = %d",$time, sum);
-      $display("$display  : At %0d: \t %m.sum = %d",$time, sum);
-      
-      #10 $display("");
-      a = 0;
-      $my_strobe(sum);
-      $display("$display  : At %0d: \t %m.sum = %d",$time, sum);
-      $strobe ("$strobe   : At %0d: \t %m.sum = %d",$time, sum);
-
-      #10 $display("");
-      b = 1;
-      $strobe ("$strobe   : At %0d: \t %m.sum = %d",$time, sum);
-      $my_strobe(sum);
-      $display("$display  : At %0d: \t %m.sum = %d",$time, sum);
-      a = 1;
-      $my_strobe(sum);
-      $strobe ("$strobe   : At %0d: \t %m.sum = %d",$time, sum);
-      $display("$display  : At %0d: \t %m.sum = %d",$time, sum);
-
-      #10 $display("");
-      $finish;
-    end
-
-  initial
-      $monitor("$monitor  : At %0d: \t %m.sum = %d",$time, sum);
-  
-endmodule
-
-/*** A gate level 1 bit adder model ***/
-`timescale 1ns / 1ns
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci, sum, co,
-        n1, n2, n3;
-
-  xor    (n1, a, b);
-  xor    (sum, n1, ci);
-  and    (n2, a, b);
-  and    (n3, n1, ci);
-  or     (co, n2, n3);
-
-endmodule
-/*********************************************************************/
-
-
-
-  'module', 'test', ';',
-     'reg', 'a', 'b', 'ci', 'clk', ';',
-      'reg', 'sum', 'co', ';',
-       'always',
-        '@', '(', 'a', 'b', 'ci', ')',
-         '{', 'co', 'sum', '}', '=', 'a', '+', 'b', '+', 'ci',
-          ';',
-       'initial',
-         'begin',
-            '$strobe',
-              '(',
-              '"$strobe   : At %0d: \\t %m.sum = %d"',
-              '$time',
-              'sum',
-              ')',
-              ';',
-             '$display',
-              '(',
-              '"$display  : At %0d: \\t %m.sum = %d"',
-              '$time',
-              'sum',
-              ')',
-              ';',
-            '$my_strobe', '(', 'sum', ')', ';',
-            'a', '=', '0', ';',
-            'b', '=', '0', ';',
-            'ci', '=', '0', ';',
-            '#', '10', '$display', '(', '""', ')', ';',
-            'a', '=', '1', ';',
-            '$my_strobe', '(', 'sum', ')', ';',
-             '$strobe',
-              '(',
-              '"$strobe   : At %0d: \\t %m.sum = %d"',
-              '$time',
-              'sum',
-              ')',
-              ';',
-             '$display',
-              '(',
-              '"$display  : At %0d: \\t %m.sum = %d"',
-              '$time',
-              'sum',
-              ')',
-              ';',
-            '#', '10', '$display', '(', '""', ')', ';',
-            'a', '=', '0', ';',
-            '$my_strobe', '(', 'sum', ')', ';',
-             '$display',
-              '(',
-              '"$display  : At %0d: \\t %m.sum = %d"',
-              '$time',
-              'sum',
-              ')',
-              ';',
-             '$strobe',
-              '(',
-              '"$strobe   : At %0d: \\t %m.sum = %d"',
-              '$time',
-              'sum',
-              ')',
-              ';',
-            '#', '10', '$display', '(', '""', ')', ';',
-            'b', '=', '1', ';',
-             '$strobe',
-              '(',
-              '"$strobe   : At %0d: \\t %m.sum = %d"',
-              '$time',
-              'sum',
-              ')',
-              ';',
-            '$my_strobe', '(', 'sum', ')', ';',
-             '$display',
-              '(',
-              '"$display  : At %0d: \\t %m.sum = %d"',
-              '$time',
-              'sum',
-              ')',
-              ';',
-            'a', '=', '1', ';',
-            '$my_strobe', '(', 'sum', ')', ';',
-             '$strobe',
-              '(',
-              '"$strobe   : At %0d: \\t %m.sum = %d"',
-              '$time',
-              'sum',
-              ')',
-              ';',
-             '$display',
-              '(',
-              '"$display  : At %0d: \\t %m.sum = %d"',
-              '$time',
-              'sum',
-              ')',
-              ';',
-            '#', '10', '$display', '(', '""', ')', ';',
-            '$finish', ';',
-          'end',
-       'initial',
-         '$monitor',
-          '(',
-          '"$monitor  : At %0d: \\t %m.sum = %d"',
-          '$time',
-          'sum',
-          ')',
-          ';',
-    'endmodule',
-    'module',
-      'addbit',
-      '(',
-      'a', 'b', 'ci', 'sum', 'co',
-      ')',
-      ';',
-     'input', 'a', 'b', 'ci', ';',
-      'output', 'sum', 'co', ';',
-      'wire', 'a', 'b', 'ci', 'sum', 'co', 'n1', 'n2', 'n3', ';',
-      'xor', '(', 'n1', 'a', 'b', ')', ';',
-      'xor', '(', 'sum', 'n1', 'ci', ')', ';',
-      'and', '(', 'n2', 'a', 'b', ')', ';',
-      'and', '(', 'n3', 'n1', 'ci', ')', ';',
-      'or', '(', 'co', 'n2', 'n3', ')', ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/myram64x16.v.parsed.txt Deleted

@@ -1,63 +0,0 @@
-// Define the black box
-module myram64x16 (data,address,inclock,outclock,we,q)
-/* syn_black_box 
-
-   LPM_WIDTH=16 
-   LPM_WIDTHAD=6 
-   LPM_TYPE="LPM_RAM_DQ"  */ ; 
-
-input 15:0 data;
-input 5:0 address;
-input inclock, outclock;
-input we;
-output 15:0 q;
-
-endmodule
-
-// Instantiate the LPM parameterized module in the 
-//    higher-level module myram
-module myram(clock, we, data, address, q);
-input clock, we;
-input 15:0 data;
-input 5:0 address;
-output 15:0 q;
-
-
-       myram_64x16 inst1 (data, address, clock, clock, we, q);
-
-endmodule
-
-   'module',
-      'myram64x16',
-      '(',
-      'data', 'address', 'inclock', 'outclock', 'we', 'q',
-      ')',
-      ';',
-     'input', '', '15', ':', '0', '', 'data', ';',
-      'input', '', '5', ':', '0', '', 'address', ';',
-      'input', 'inclock', 'outclock', ';',
-      'input', 'we', ';',
-      'output', '', '15', ':', '0', '', 'q', ';',
-    'endmodule',
-    'module',
-      'myram',
-      '(',
-      'clock', 'we', 'data', 'address', 'q',
-      ')',
-      ';',
-     'input', 'clock', 'we', ';',
-      'input', '', '15', ':', '0', '', 'data', ';',
-      'input', '', '5', ':', '0', '', 'address', ';',
-      'output', '', '15', ':', '0', '', 'q', ';',
-       'myram_64x16',
-         'inst1',
-           '(',
-            'data',
-            'address',
-            'clock',
-            'clock',
-            'we',
-            'q',
-            ')',
-        ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/nco.v.parsed.txt Deleted

@@ -1,489 +0,0 @@
-//
-// NCO Demo (Numerically controlled Oscillator).
-//
-// One type of NCO is based on the idea of a continuously wrapping modulo
-// counter.  The NCO is a programmable modulo counter.  For example, if
-// the MOD input is set to 10, then it'll count 0,1,2,3,4,5,6,7,8,9,0,1,2 etc.
-// The STEP input is continuously added to the modulo counter.  What's important
-// is not the counter value itself, but the number of times it "wraps".  If
-// you do the math, the counter will wrap at a rate of F*S/M (F is the system
-// clock frequency, S is the step input, and M is the modulo).  Every wrap
-// occurance is a little pulse.  The pulse output could be used as the clock itself
-// except that it may have a very small duty cycle.  Instead, take the WRAP
-// pulse signal and use it to increment a TICKS counter.  The TICKS counter will
-// then count at the programmed frequency.
-//
-// The TICK counter could be used in itself for, say, a TDMA slot counter.  Any
-// number of TICKS LSB bits can be thrown away to "reduce jitter" but also
-// reduce the rate.  This NCO has a little MASK input and an internal OR gate
-// so you can pick off whichever TICKS bits you wish for your final FOUT output.
-//
-// In an open-loop mode, you program your Modulo and Step inputs and you are done.
-// If you are tracking some other reference (e.g. like in a PLL style circuit) you
-// would somehow control STEP via some sort of "phase detector" and loop filter.
-// None of this is shown here.
-//
-// Anyway, this is just the guts of the NCO, which can be applied in many, many
-// ways.
-//
-// Oh.. And this NCO seems to be off by a small percentage..?!..  I'm not sure
-// why.  It may be the circuit or the testbench.  Let me know if you play with it
-// and find out.  My application is closed-loop, so, I'm not highly motivated
-// to figure it out.
-//
-// Written by tom coonan
-//
-module nco (
-   clk,
-   resetb,
-   step,	// Step input is continuously added to the modulo counter
-   mod,		// modulo
-   mask,	// Mask is ANDed with ticks and gen ORed to produce fout
-   ticks,	// Tick counter output
-   fout		// Output.
-);
-
-parameter W_ACCUM = 24; // Width of the Accumulator
-parameter W_TICK  = 8; // Width of the Tick counter.
-parameter W_STEP  = 24;
-parameter W_MOD   = 24;
-
-input			clk;
-input			resetb;
-input W_STEP-1:0	step;
-input W_MOD-1:0	mod;
-input W_TICK-1:0	mask;
-output W_TICK-1:0	ticks;
-output			fout;
-
-// Registered outputs
-
-// Internals
-reg W_ACCUM-1:0	accum, accum_in;
-reg W_TICK-1:0	ticks;
-
-// *** Modulo Counter ***
-// Registered outputs
-reg		wrap;
-
-wire W_ACCUM-1:0	sum = accum + step;
-wire W_ACCUM-1:0	rem = sum - mod;
-wire			over = (sum >= mod);
-
-always @(posedge clk or negedge resetb)
-   if (~resetb) accum <= 0;
-   else         accum <= accum_in;
-   
-always @(over or rem or sum) begin
-   if (over) begin
-      // Wrap!
-      accum_in <= rem; // load remainder instead of sum
-      wrap <= 1;
-   end
-   else begin
-      // No wrap, just add
-      accum_in <= sum;
-      wrap <= 0;
-   end
-end
-
-// *** Tick Counter ***
-//
-always @(posedge clk) begin
-   if (~resetb) ticks <= 0;
-   else begin
-      // Whenever Modulo counter wraps, increment the tick counter.
-      if (wrap) 
-         ticks <= ticks + 1;
-   end
-end
-
-// *** Masks and final output *** //
-
-assign fout = |(ticks & mask);
-
-endmodule
-
-module ncotest;
-
-reg		clk;
-reg		resetb;
-reg 23:0	step;
-reg 23:0	mod;
-reg 7:0	mask;
-wire		fout;
-wire 7:0	ticks;	
-
-parameter W_ACCUM = 24; // Width of the Accumulator
-parameter W_TICK  = 8; // Width of the Tick counter.
-parameter W_STEP  = 24;
-parameter W_MOD   = 24;
-
-nco nco1 (
-   .clk(clk),
-   .resetb(resetb),
-   .step(step),
-   .mod(mod),
-   .mask(mask),
-   .fout(fout),
-   .ticks(ticks)
-);
-
-parameter PERIOD_NS = 36;
-parameter DUMP_ON = 1;
-
-real	sys_freq;
-
-initial begin
-   step = 0;
-   mod = 0;
-   mask = 8'b00000001; // Final Divider for FOUT
-   
-   sys_freq = 1000000000.0/(PERIOD_NS);
-   
-   #300;
-
-   // Display the basic such as system clock frequency, etc.
-   //
-   $display ("NCO Test.  NCO Accumulator width is %0d bits, system clock period is %0d ns (%fMHz).",
-      W_ACCUM,
-      PERIOD_NS,
-      sys_freq
-   );
-   
-   // Program Modulo and Step for desired frequency.  Modulo and Step values should
-   // not be divisible by each other (I'm not mathematically strong enough to
-   // justify this...).  Find the ratio of S/M, integerize it, and reduce to lowest
-   // common divisors.  Then, multiply up by a big power of 2 so we can get some
-   // resolution on the NCO.
-   // 
-   
-   // Let's generate 1Mhz, Fsys*(Step/Mod)/2 = 27777777.777*(S/M)/2 = 1000000
-   //    S/M = 0.072 = 72/1000 = 9/125 (9 * 2^12) / (125 * 2^12)
-   //
-   mod  = 125 << 12; // Shift up so we get resolution..
-   step =   9 << 12; // Shift up so we get resolution..
-   nco_test (mod, step, 1000000); // Run test for specified interval (units are NS)
-   
-   // Generate 10.24MHz: Fsys*(Step/Mod)/2 = 27777777.777*(S/M)/2 = 10240000
-   //    S/M = 0.73728 = 73728/100000 = 9216/12500 = 4608/6250 = 2304/3125
-   //
-   mod  = 3125 << 10; // Shift up so we get resolution..
-   step = 2304 << 10; // Shift up so we get resolution..
-   nco_test (mod, step, 1000000); // Run test for specified interval (units are NS)
-   
-   // Generate 32.768 KHz using TICKS MSB (divide by 8): 
-   //    Fsys*(Step/Mod) = 27777777.777*(S/M) = 32768*256
-   //    S/M = 0.301989888 =~ 0.302 = 302/1000 = 151/500
-   //
-   mask = 8'b10000000; // Divide by 256
-   mod  = 500 << 12;
-   step = (151 << 12) - 9566;  // Manually Tweaked this to get the right number..
-                               // this is expected since didn't have a good integer
-                               // ratio above..
-   nco_test (mod, step, 1000000); // Run test for specified interval (units are NS)
-      
-   $display ("Done.");
-   
-   $finish;
-end
-
-// Run a single trial of the NCO test.
-//   
-task nco_test;
-   input 23:0 mod_arg;
-   input 23:0 step_arg;
-   input	interval;
-   
-   integer	interval;   // Use $time..  Make sure timescale is correct!
-   integer	start_time;
-   integer	fout_edges;
-   
-   begin
-      step = step_arg; // Configure NCO
-      mod  = mod_arg;
-      
-      // Count rising edges on FOUT which is the output frequency
-      fout_edges = 0;
-      start_time = $time; // Note our starting time
-      // Loop for at least the specified amount of time
-      while ( ($time - start_time) < interval) begin
-         @(posedge fout); // Wait for an edge on FOUT
-         fout_edges = fout_edges + 1;
-      end
-      
-      // Done.  Display results and expected results.
-      $display ("For Mod=%0d(0x%h), Step=%0d(0x%h), Frequency of fout = %f Hz, Expected fout is %f Hz.",
-         mod, mod,
-         step, step,
-         ((fout_edges*1.0)/($time - start_time))*1000000000.0, // measured..
-         ((step*1.0)/(mod*1.0))*(sys_freq)/(mask*2.0)   // expected..
-      );
-   end
-endtask
-
-// Let's clock it at about 27 MHz
-initial begin
-   clk = 0;
-   forever begin
-      #(PERIOD_NS/2) clk = ~clk;
-   end
-end
-
-initial begin
-   resetb = 0;
-   #200 resetb = 1;
-end
-
-initial begin
-   if (DUMP_ON) begin
-      $dumpfile ("nco.vcd");
-      $dumpvars (0,ncotest);   
-   end
-end
-endmodule
-
-
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-              ';',
-            '#', '300', ';',
-             '$display',
-              '(',
-              '"NCO Test.  NCO Accumulator width is %0d bits, system clock '
-              'period is %0d ns (%fMHz)."',
-              'W_ACCUM',
-              'PERIOD_NS',
-              'sys_freq',
-              ')',
-              ';',
-            'mod', '=', '125', '<<', '12', ';',
-            'step', '=', '9', '<<', '12', ';',
-            'nco_test', '(', 'mod', 'step', '1000000', ')', ';',
-            'mod', '=', '3125', '<<', '10', ';',
-            'step', '=', '2304', '<<', '10', ';',
-            'nco_test', '(', 'mod', 'step', '1000000', ')', ';',
-            'mask', '=', "8 'b 10000000", ';',
-            'mod', '=', '500', '<<', '12', ';',
-            'step', '=', '(', '151', '<<', '12', ')', '-', '9566', ';',
-            'nco_test', '(', 'mod', 'step', '1000000', ')', ';',
-            '$display', '(', '"Done."', ')', ';',
-            '$finish', ';',
-          'end',
-       'task',
-        'nco_test',
-        ';',
-        'input', '', '23', ':', '0', '', 'mod_arg', ';',
-        'input', '', '23', ':', '0', '', 'step_arg', ';',
-        'input', 'interval', ';',
-        'integer', 'interval', ';',
-        'integer', 'start_time', ';',
-        'integer', 'fout_edges', ';',
-         'begin',
-           'step', '=', 'step_arg', ';',
-            'mod', '=', 'mod_arg', ';',
-            'fout_edges', '=', '0', ';',
-            'start_time', '=', '$time', ';',
-             'while',
-              '(',
-              '(',
-              '$time', '-', 'start_time',
-              ')',
-              '<',
-              'interval',
-              ')',
-               'begin',
-                 '@', '(', 'posedge', 'fout', ')', ';',
-                  'fout_edges', '=', 'fout_edges', '+', '1', ';',
-                'end',
-             '$display',
-              '(',
-              '"For Mod=%0d(0x%h), Step=%0d(0x%h), Frequency of fout = %f Hz, '
-              'Expected fout is %f Hz."',
-              'mod',
-              'mod',
-              'step',
-              'step',
-              '(',
-               '(',
-                'fout_edges', '*', '1.0',
-                ')',
-                '/',
-                '(',
-                '$time', '-', 'start_time',
-                ')',
-              ')',
-              '*',
-              '1000000000.0',
-              '(',
-               '(',
-                'step', '*', '1.0',
-                ')',
-                '/',
-                '(',
-                'mod', '*', '1.0',
-                ')',
-              ')',
-              '*',
-              '(',
-              'sys_freq',
-              ')',
-              '/',
-              '(',
-              'mask', '*', '2.0',
-              ')',
-              ')',
-              ';',
-          'end',
-        'endtask',
-       'initial',
-         'begin',
-           'clk', '=', '0', ';',
-             'forever',
-               'begin',
-                  '#', '(', 'PERIOD_NS', '/', '2', ')',
-                    'clk', '=', '~', 'clk', ';',
-                'end',
-          'end',
-       'initial',
-         'begin',
-           'resetb', '=', '0', ';',
-            '#', '200', 'resetb', '=', '1', ';',
-          'end',
-       'initial',
-         'begin',
-            'if',
-              '(', 'DUMP_ON', ')',
-               'begin',
-                 '$dumpfile', '(', '"nco.vcd"', ')', ';',
-                  '$dumpvars', '(', '0', 'ncotest', ')', ';',
-                'end',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/ndro.v.parsed.txt Deleted

@@ -1,320 +0,0 @@
-// Verilog HDL for "RSFQ.lib", "ndro_cell" "_functional"
-// Module NDRO cell
-
-module ndro_cell (on, off, sig, out, dout);
-
-input
-	on, off, sig;
-
-output
-	out, dout;
-reg 
-	out, dout;
-
-parameter
-	off_sig_hold	= -3,
-	off_sig_setup	= 8,
-	on_sig_hold	= 10,
-	on_sig_setup	= 7,
-	on_off_hold	= 6,
-	on_off_setup	= 10,
-	sig_out_delay	= 12,
-	off_dout_delay  = 10,
-
-	warning_file=3;  // multichannel description of a warning file
-
-reg
-	on_internal, off_internal, sig_internal,
-	ndro_state,          	   // internal state
-	d_set;		   	   // signal determining the moment when
-				   // the state of the d input changes to "1"
-
-integer
-	data_delay,  // delay between d and d_internal
-	clk_delay,   // delay between clk and clk_internal
-	out_delay,   // delay between clk_internal and out
-	out_value,   // output value in a given clock cycle
-	last_clk_time;	// time when the last clock pulse appeared
-
-initial 
-	begin
-// define delays between inputs & outputs and the corresponding
-//  internal auxiliary registers
-	  	if(t_hold<0)
-		  begin
-	    	  	data_delay = -t_hold;
-	    		clk_delay  = 0;
-			out_delay  = delay;
-		  end
-	  	else
-		  begin
-	   	  	data_delay = 0;
-	    		clk_delay  = t_hold;
-		  	out_delay  = delay-t_hold;
-		  end
-
-// clear internal registers and the output signal
-		d_internal = 0;
-		clk_internal = 0;
-		last_clk_time = 0;
-		d_state = 0;
-		d_set = 0;
-		out = 0;
-	end
-
-
-
-always @(posedge on) 	// Execute at positive edge of on
-	  on_internal <= #(data_delay) on;
-
-always @(posedge off)  // Execute at positive edge of off
-	  off_internal <= #(clk_delay) off;
-
-always @(posedge sig)  // Execute at positive edge of sig
-	  sig_internal <= #(clk_delay) sig;
-
-
-always @(posedge on_internal)
-	begin
-                ndro_state <= ndro_state | 1'bx;
-		if (on_internal === 1)
-		  on_sig_set <= #(on_sig_hold+on_sig_setup) 1;
-
-		on_internal <= 0;
-	end
-
-always @(posedge on_set)
-	begin
-		if ($stime - last_sig_time >= on_sig_hold+on_sig_setup)
-			ndro_state = 1;
-		else
-		  begin
-			ndro_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input ON pulse at %0d,",
-			 $stime-data_delay-t_hold-t_setup);
-			$fwrite(warning_file,
-			"\tSIG pulse at %0d.\n", last_clk_time-clk_delay);
-		  end
-
-		on_set <= 0;
-	end
-
-
-always @(posedge sig_internal)	
-	begin
-// computing the output
-		if (sig_internal === 1'bx)
-		  out_value = 1'bx;
-		else
-		  out_value = ndro_state;
-
-// transfering the result to the output
-		out <= #(out_delay) out_value;
-		out <= #(out_delay+2) 0;
-
-                ndro_state <= ndro_state | 1'bx;
-		if (sig_internal === 1)
-		  sig_off_set <= #(sig_off_hold+sig_off_setup) 1;
-
-		sig_internal <= 0;
-		last_sig_time = $stime;
-	end
-
-
-always @(posedge off_internal)	
-	begin
-// computing the output
-		if (off_internal === 1'bx)
-		  out_value = 1'bx;
-		else
-		  out_value = ndro_state;
-
-// transfering the result to the output
-		out <= #(out_delay) out_value;
-		out <= #(out_delay+2) 0;
-
-// clearing the internal state of the NDRO
-		ndro_state  <= 0;
-
-		off_internal <= 0;
-		last_off_time = $stime;
-	end
-
-
-endmodule
-
-
-   'module',
-      'ndro_cell',
-      '(',
-      'on', 'off', 'sig', 'out', 'dout',
-      ')',
-      ';',
-     'input', 'on', 'off', 'sig', ';',
-      'output', 'out', 'dout', ';',
-      'reg', 'out', 'dout', ';',
-       'parameter',
-        'off_sig_hold', '=', '-', '3',
-        'off_sig_setup', '=', '8',
-        'on_sig_hold', '=', '10',
-        'on_sig_setup', '=', '7',
-        'on_off_hold', '=', '6',
-        'on_off_setup', '=', '10',
-        'sig_out_delay', '=', '12',
-        'off_dout_delay', '=', '10',
-        'warning_file', '=', '3',
-        ';',
-       'reg',
-        'on_internal',
-        'off_internal',
-        'sig_internal',
-        'ndro_state',
-        'd_set',
-        ';',
-       'integer',
-        'data_delay',
-        'clk_delay',
-        'out_delay',
-        'out_value',
-        'last_clk_time',
-        ';',
-       'initial',
-         'begin',
-            'if',
-              '(', 't_hold', '<', '0', ')',
-               'begin',
-                 'data_delay', '=', '-', 't_hold', ';',
-                  'clk_delay', '=', '0', ';',
-                  'out_delay', '=', 'delay', ';',
-                'end',
-              'else',
-               'begin',
-                 'data_delay', '=', '0', ';',
-                  'clk_delay', '=', 't_hold', ';',
-                  'out_delay', '=', 'delay', '-', 't_hold', ';',
-                'end',
-            'd_internal', '=', '0', ';',
-            'clk_internal', '=', '0', ';',
-            'last_clk_time', '=', '0', ';',
-            'd_state', '=', '0', ';',
-            'd_set', '=', '0', ';',
-            'out', '=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'on', ')',
-         'on_internal', '<=', '#', '(', 'data_delay', ')', 'on',
-          ';',
-       'always',
-        '@', '(', 'posedge', 'off', ')',
-         'off_internal', '<=', '#', '(', 'clk_delay', ')', 'off',
-          ';',
-       'always',
-        '@', '(', 'posedge', 'sig', ')',
-         'sig_internal', '<=', '#', '(', 'clk_delay', ')', 'sig',
-          ';',
-       'always',
-        '@', '(', 'posedge', 'on_internal', ')',
-         'begin',
-           'ndro_state', '<=', 'ndro_state', '|', "1 'b x", ';',
-             'if',
-              '(', 'on_internal', '===', '1', ')',
-                'on_sig_set',
-                  '<=',
-                  '#', '(', 'on_sig_hold', '+', 'on_sig_setup', ')',
-                  '1',
-                ';',
-            'on_internal', '<=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'on_set', ')',
-         'begin',
-            'if',
-               '(',
-                '$stime',
-                '-',
-                'last_sig_time',
-                '>=',
-                'on_sig_hold',
-                '+',
-                'on_sig_setup',
-                ')',
-              'ndro_state', '=', '1', ';',
-              'else',
-               'begin',
-                 'ndro_state', '=', "1 'b x", ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Violation of hold/setup time in module %m.\\n"',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Input ON pulse at %0d,"',
-                    '$stime',
-                    '-',
-                    'data_delay',
-                    '-',
-                    't_hold',
-                    '-',
-                    't_setup',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"\\tSIG pulse at %0d.\\n"',
-                    'last_clk_time',
-                    '-',
-                    'clk_delay',
-                    ')',
-                    ';',
-                'end',
-            'on_set', '<=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'sig_internal', ')',
-         'begin',
-            'if',
-              '(', 'sig_internal', '===', "1 'b x", ')',
-              'out_value', '=', "1 'b x", ';',
-              'else',
-              'out_value', '=', 'ndro_state', ';',
-             'out', '<=', '#', '(', 'out_delay', ')', 'out_value',
-              ';',
-             'out', '<=', '#', '(', 'out_delay', '+', '2', ')', '0',
-              ';',
-            'ndro_state', '<=', 'ndro_state', '|', "1 'b x", ';',
-             'if',
-              '(', 'sig_internal', '===', '1', ')',
-                'sig_off_set',
-                  '<=',
-                  '#', '(', 'sig_off_hold', '+', 'sig_off_setup', ')',
-                  '1',
-                ';',
-            'sig_internal', '<=', '0', ';',
-            'last_sig_time', '=', '$stime', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'off_internal', ')',
-         'begin',
-            'if',
-              '(', 'off_internal', '===', "1 'b x", ')',
-              'out_value', '=', "1 'b x", ';',
-              'else',
-              'out_value', '=', 'ndro_state', ';',
-             'out', '<=', '#', '(', 'out_delay', ')', 'out_value',
-              ';',
-             'out', '<=', '#', '(', 'out_delay', '+', '2', ')', '0',
-              ';',
-            'ndro_state', '<=', '0', ';',
-            'off_internal', '<=', '0', ';',
-            'last_off_time', '=', '$stime', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/nodeinfo_test.v.parsed.txt Deleted

@@ -1,134 +0,0 @@
-/**********************************************************************
- * $nodeinfo_test example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $nodeinfo_test PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-  reg     reg1;
-  reg 39:0 reg2;
-  integer int1;
-  time    time1;
-  real    real1;
-  wire (strong0, weak1) w1 = reg1;
-  wire 0:39 w2 = reg2;
-  parameter param1 = 1;
-  parameter 7:0 param2 = 2;
-  parameter 47:0 param3 = 3;
-  parameter param4 = 4.1;
-
-  reg 23:0 RAM 0:3;
-  integer ARRAY 1:0;
-
-  initial
-    begin
-      reg1 = 1'bx;
-      reg2 = {10{4'b01ZX}};
-      int1 = "ABCD";
-      time1 = 'h25;
-      real1 = 3.1415;
-      RAM0 = "EFG";
-
-      #1 $nodeinfo_test(reg1);
-      #1 $nodeinfo_test(reg2);
-      #1 $nodeinfo_test(reg229:20);
-      #1 $nodeinfo_test(int19:2);
-      #1 $nodeinfo_test(time13);
-      #1 $nodeinfo_test(real1);
-      #1 $nodeinfo_test(w1);
-      #1 $nodeinfo_test(w2);
-      #1 $nodeinfo_test(param1);
-      #1 $nodeinfo_test(param2);
-      #1 $nodeinfo_test(param3);
-      #1 $nodeinfo_test(param4);
-      #1 $nodeinfo_test(RAM0);
-      #1 $nodeinfo_test(ARRAY0);
-
-      //unsupported expressions
-      #1 $nodeinfo_test(w239);
-      #1 $nodeinfo_test(w236:39);
-      #1 $nodeinfo_test();
-      #1 $nodeinfo_test(5);
-      #1 $nodeinfo_test("foobar");
-
-      #1 $finish;
-    end
-
-endmodule
-
-/**********************************************************************/
-
-
-
-  'module', 'test', ';',
-     'reg', 'reg1', ';',
-      'reg', '', '39', ':', '0', '', 'reg2', ';',
-      'integer', 'int1', ';',
-      'time', 'time1', ';',
-      'real', 'real1', ';',
-       'wire',
-        '(', 'strong0', ',', 'weak1', ')',
-        'w1', '=', 'reg1',
-        ';',
-      'wire', '', '0', ':', '39', '', 'w2', '=', 'reg2', ';',
-      'parameter', 'param1', '=', '1', ';',
-      'parameter', '', '7', ':', '0', '', 'param2', '=', '2', ';',
-      'parameter', '', '47', ':', '0', '', 'param3', '=', '3', ';',
-      'parameter', 'param4', '=', '4.1', ';',
-      'reg', '', '23', ':', '0', '', 'RAM', '', '0', ':', '3', '', ';',
-      'integer', 'ARRAY', '', '1', ':', '0', '', ';',
-       'initial',
-         'begin',
-           'reg1', '=', "1 'b x", ';',
-            'reg2', '=', '{', '10', '{', "4 'b 01ZX", '}', '}', ';',
-            'int1', '=', '"ABCD"', ';',
-            'time1', '=', "'h 25", ';',
-            'real1', '=', '3.1415', ';',
-            'RAM', '', '0', '', '=', '"EFG"', ';',
-            '#', '1', '$nodeinfo_test', '(', 'reg1', ')', ';',
-            '#', '1', '$nodeinfo_test', '(', 'reg2', ')', ';',
-             '#', '1',
-               '$nodeinfo_test',
-                '(',
-                'reg2', '', '29', '20', '',
-                ')',
-                ';',
-             '#', '1',
-               '$nodeinfo_test',
-                '(',
-                'int1', '', '9', '2', '',
-                ')',
-                ';',
-             '#', '1',
-              '$nodeinfo_test', '(', 'time1', '', '3', '', ')', ';',
-            '#', '1', '$nodeinfo_test', '(', 'real1', ')', ';',
-            '#', '1', '$nodeinfo_test', '(', 'w1', ')', ';',
-            '#', '1', '$nodeinfo_test', '(', 'w2', ')', ';',
-            '#', '1', '$nodeinfo_test', '(', 'param1', ')', ';',
-            '#', '1', '$nodeinfo_test', '(', 'param2', ')', ';',
-            '#', '1', '$nodeinfo_test', '(', 'param3', ')', ';',
-            '#', '1', '$nodeinfo_test', '(', 'param4', ')', ';',
-             '#', '1',
-              '$nodeinfo_test', '(', 'RAM', '', '0', '', ')', ';',
-             '#', '1',
-              '$nodeinfo_test', '(', 'ARRAY', '', '0', '', ')', ';',
-             '#', '1',
-              '$nodeinfo_test', '(', 'w2', '', '39', '', ')', ';',
-             '#', '1',
-               '$nodeinfo_test',
-                '(',
-                'w2', '', '36', '39', '',
-                ')',
-                ';',
-            '#', '1', '$nodeinfo_test', '(', ')', ';',
-            '#', '1', '$nodeinfo_test', '(', '5', ')', ';',
-            '#', '1', '$nodeinfo_test', '(', '"foobar"', ')', ';',
-            '#', '1', '$finish', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/onehot.v.parsed.txt Deleted

@@ -1,436 +0,0 @@
-// 
-// Just a little demo of some FSM techniques, including One-Hot and
-// using 'default' settings and the case statements to selectively
-// update registers (sort of like J-K flip-flops).
-//
-// tom coonan, 12/98.
-//
-module onehot (clk, resetb, a, b, x, y);
-
-input clk;
-input resetb;
-input 7:0 a;
-input 7:0 b;
-output 7:0 x;
-output 7:0 y;
-
-// Use One-Hot encoding.  There will be 16 states.
-//
-reg 15:0 state, next_state;
-
-// These are working registers.  Declare the register itself (e.g. 'x') and then
-// the input bus used to load in a new value (e.g. 'x_in').  The 'x_in' bus will
-// physically be a wire bus and 'x' will be the flip-flop register ('x_in' must
-// be declared 'reg' because it's used in an always block.
-//
-reg 7:0 x, x_in;
-reg 7:0 y, y_in;
-
-// Update state.  'state' is the actual flip-flop register and next_state is the combinatorial
-// bus used to update 'state''s value.  Check for the ZERO state which means an unexpected
-// next state was computed.  If this occurs, jump to our initialization state; state0.
-// 
-// It is considered good practice by many designers to seperate the combinatorial
-// and sequential aspects of state registers, and often registers in general.
-//
-always @(posedge clk or negedge resetb) begin
-   if (~resetb) state <= 0;
-   else begin
-      if (next_state == 0) begin
-         state <= 16'h0001;
-      end
-      else begin
-         state <= next_state;
-      end
-   end
-end
-
-// Implement the X flip-flop register.  Always load the input bus into the register.
-// Reset to zero.
-//
-always @(posedge clk or negedge resetb) begin
-   if (~resetb) x <= 0;
-   else         x <= x_in;
-end
-
-// Implement the Y flip-flop register.  Always load the input bus into the register.
-// Reset to zero.
-//
-always @(posedge clk or negedge resetb) begin
-   if (~resetb) y <= 0;
-   else         y <= y_in;
-end
-
-// Generate the next_state function.  Also, based on the current state, generate
-// any new values for X and Y.
-//
-always @(state or a or b or x or y) begin
-   // *** Establish defaults.
-   
-   // Working registers by default retain their current value.  If any particular
-   // state does NOT need to change a register, then it doesn't have to reference
-   // the register at all.  In these cases, the default below takes affect.  This
-   // turns out to be a pretty succinct way to control stuff from the FSM.
-   //
-   x_in <= x;
-   y_in <= y;
-   
-   // State by default will be cleared.  If we somehow ever got into an unknown
-   // state, then the default would throw state machine back to zero.  Look
-   // at the sequential 'always' block for state to see how this is handled.
-   //
-   next_state <= 0;
-   
-   // One-Hot State Machine Encoding.
-   //
-   // *** Using a 1'b1 in the case statement is the trick to doing One-Hot...
-   //     DON'T include a 'default' clause within the case because we want to
-   //     establish the defaults above. ***
-   //
-   case (1'b1) // synopsys parallel_case
-   
-      // Initialization state.  Set X and Y register to some interesting starting values.
-      //
-      state0:
-         begin
-            x_in <= 8'd20;
-            y_in <= 8'd100;
-            next_state1 <= 1'b1;
-         end
-      
-      // Just for fun.. Jump through states..  
-      state1: next_state2 <= 1'b1;
-      state2: next_state3 <= 1'b1;
-      state3: next_state4 <= 1'b1;
-      state4: next_state5 <= 1'b1;
-      state5: next_state6 <= 1'b1;
-      state6: next_state7 <= 1'b1;
-      
-      // Conditionally decrement Y register.
-      state7:
-         begin
-            if (a == 1) begin
-               y_in <= y - 1;
-               next_state1 <= 1'b1;
-            end
-            else begin
-               next_state8 <= 1'b1;
-            end
-         end
-        
-      // Just for fun.. Jump through states..  
-      state8: next_state9   <= 1'b1;
-      state9: next_state10  <= 1'b1;
-      state10: next_state11 <= 1'b1;
-
-      // Conditionally increment X register.
-      state11:
-         begin
-            if (b == 1) begin
-               x_in <= x + 1;
-               next_state1 <= 1'b1;
-            end
-            else begin
-               next_state12 <= 1'b1;
-            end
-         end
-
-      // Just for fun.. Jump through states..  
-      state12: next_state13 <= 1'b1;
-      state13: next_state14 <= 1'b1;
-      state14: next_state15 <= 1'b1;
-      state15: next_state1  <= 1'b1; // Don't go back to our initialization state, but state following that one.
-    endcase
-end
-endmodule
-
-// synopsys translate_off
-module test_onehot;
-reg clk, resetb;
-reg 7:0 a;
-reg 7:0 b;
-wire 7:0 x;
-wire 7:0 y;
-
-// Instantiate module.
-//
-onehot onehot (
-   .clk(clk),
-   .resetb(resetb),
-   .a(a),
-   .b(b),
-   .x(x),
-   .y(y)
-);
-
-// Generate clock.
-//
-initial begin
-   clk = 0;
-   forever begin
-      #10 clk = ~clk;
-   end
-end
-
-// Reset..
-//
-initial begin
-   resetb = 0;
-   #33 resetb = 1;
-end
-
-// Here's the test.
-//
-// Should see X and Y get initially loaded with their starting values.
-// As long as a and b are zero, nothing should change.
-// When a is asserted, Y should slowly decrement.  When b is asserted, X should
-// slowly increment.  That's it.
-//
-initial begin 
-   a = 0;
-   b = 0;
-   repeat (64) @(posedge clk);
-   #1
-   
-   // Y should be decremented..
-   a = 1;
-   b = 0;
-   repeat (256) @(posedge clk);
-   #1
-   
-   // X should be incremented..
-   a = 0;
-   b = 1;
-   repeat (256) @(posedge clk);
-   
-   $finish;
-end
-
-// Monitor the module.
-//
-initial begin
-   forever begin
-      @(posedge clk);
-      #1;
-      $display ("a = %b, b = %b, x = %0d, y = %0d", a,b,x,y);
-   end
-end
-      
-endmodule
-
-
-
-   'module',
-      'onehot',
-      '(',
-      'clk', 'resetb', 'a', 'b', 'x', 'y',
-      ')',
-      ';',
-     'input', 'clk', ';',
-      'input', 'resetb', ';',
-      'input', '', '7', ':', '0', '', 'a', ';',
-      'input', '', '7', ':', '0', '', 'b', ';',
-      'output', '', '7', ':', '0', '', 'x', ';',
-      'output', '', '7', ':', '0', '', 'y', ';',
-      'reg', '', '15', ':', '0', '', 'state', 'next_state', ';',
-      'reg', '', '7', ':', '0', '', 'x', 'x_in', ';',
-      'reg', '', '7', ':', '0', '', 'y', 'y_in', ';',
-       'always',
-        '@', '(', 'posedge', 'clk', 'negedge', 'resetb', ')',
-         'begin',
-            'if',
-              '(', '~', 'resetb', ')',
-              'state', '<=', '0', ';',
-              'else',
-               'begin',
-                  'if',
-                    '(', 'next_state', '==', '0', ')',
-                    'begin', 'state', '<=', "16 'h 0001", ';', 'end',
-                    'else',
-                     'begin',
-                      'state', '<=', 'next_state', ';',
-                      'end',
-                'end',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'clk', 'negedge', 'resetb', ')',
-         'begin',
-            'if',
-              '(', '~', 'resetb', ')',
-              'x', '<=', '0', ';',
-              'else',
-              'x', '<=', 'x_in', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'clk', 'negedge', 'resetb', ')',
-         'begin',
-            'if',
-              '(', '~', 'resetb', ')',
-              'y', '<=', '0', ';',
-              'else',
-              'y', '<=', 'y_in', ';',
-          'end',
-       'always',
-        '@', '(', 'state', 'a', 'b', 'x', 'y', ')',
-         'begin',
-           'x_in', '<=', 'x', ';',
-            'y_in', '<=', 'y', ';',
-            'next_state', '<=', '0', ';',
-             'case',
-              '(',
-              "1 'b 1",
-              ')',
-              'state', '', '0', '',
-              ':',
-               'begin',
-                 'x_in', '<=', "8 'd 20", ';',
-                  'y_in', '<=', "8 'd 100", ';',
-                  'next_state', '', '1', '', '<=', "1 'b 1", ';',
-                'end',
-              'state', '', '1', '',
-              ':',
-              'next_state', '', '2', '', '<=', "1 'b 1", ';',
-              'state', '', '2', '',
-              ':',
-              'next_state', '', '3', '', '<=', "1 'b 1", ';',
-              'state', '', '3', '',
-              ':',
-              'next_state', '', '4', '', '<=', "1 'b 1", ';',
-              'state', '', '4', '',
-              ':',
-              'next_state', '', '5', '', '<=', "1 'b 1", ';',
-              'state', '', '5', '',
-              ':',
-              'next_state', '', '6', '', '<=', "1 'b 1", ';',
-              'state', '', '6', '',
-              ':',
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-               'begin',
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-                         'next_state', '', '1', '', '<=', "1 'b 1",
-                          ';',
-                      'end',
-                    'else',
-                     'begin',
-                        'next_state', '', '8', '', '<=', "1 'b 1",
-                          ';',
-                      'end',
-                'end',
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-              'state', '', '10', '',
-              ':',
-              'next_state', '', '11', '', '<=', "1 'b 1", ';',
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-              ':',
-               'begin',
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-                    '(', 'b', '==', '1', ')',
-                     'begin',
-                       'x_in', '<=', 'x', '+', '1', ';',
-                         'next_state', '', '1', '', '<=', "1 'b 1",
-                          ';',
-                      'end',
-                    'else',
-                     'begin',
-                        'next_state', '', '12', '', '<=', "1 'b 1",
-                          ';',
-                      'end',
-                'end',
-              'state', '', '12', '',
-              ':',
-              'next_state', '', '13', '', '<=', "1 'b 1", ';',
-              'state', '', '13', '',
-              ':',
-              'next_state', '', '14', '', '<=', "1 'b 1", ';',
-              'state', '', '14', '',
-              ':',
-              'next_state', '', '15', '', '<=', "1 'b 1", ';',
-              'state', '', '15', '',
-              ':',
-              'next_state', '', '1', '', '<=', "1 'b 1", ';',
-              'endcase',
-          'end',
-    'endmodule',
-   'module', 'test_onehot', ';',
-     'reg', 'clk', 'resetb', ';',
-      'reg', '', '7', ':', '0', '', 'a', ';',
-      'reg', '', '7', ':', '0', '', 'b', ';',
-      'wire', '', '7', ':', '0', '', 'x', ';',
-      'wire', '', '7', ':', '0', '', 'y', ';',
-       'onehot',
-         'onehot',
-           '(',
-            '.', 'clk', '(', 'clk', ')',
-            '.', 'resetb', '(', 'resetb', ')',
-            '.', 'a', '(', 'a', ')',
-            '.', 'b', '(', 'b', ')',
-            '.', 'x', '(', 'x', ')',
-            '.', 'y', '(', 'y', ')',
-            ')',
-        ';',
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-           'clk', '=', '0', ';',
-             'forever',
-               'begin',
-                '#', '10', 'clk', '=', '~', 'clk', ';',
-                'end',
-          'end',
-       'initial',
-         'begin',
-           'resetb', '=', '0', ';',
-            '#', '33', 'resetb', '=', '1', ';',
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-           'a', '=', '0', ';',
-            'b', '=', '0', ';',
-             'repeat',
-              '(',
-              '64',
-              ')',
-              '@', '(', 'posedge', 'clk', ')', ';',
-            '#', '1', 'a', '=', '1', ';',
-            'b', '=', '0', ';',
-             'repeat',
-              '(',
-              '256',
-              ')',
-              '@', '(', 'posedge', 'clk', ')', ';',
-            '#', '1', 'a', '=', '0', ';',
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-             'repeat',
-              '(',
-              '256',
-              ')',
-              '@', '(', 'posedge', 'clk', ')', ';',
-            '$finish', ';',
-          'end',
-       'initial',
-         'begin',
-            'forever',
-               'begin',
-                 '@', '(', 'posedge', 'clk', ')', ';',
-                  '#', '1', ';',
-                   '$display',
-                    '(',
-                    '"a = %b, b = %b, x = %0d, y = %0d"',
-                    'a',
-                    'b',
-                    'x',
-                    'y',
-                    ')',
-                    ';',
-                'end',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/or.v.parsed.txt Deleted

@@ -1,358 +0,0 @@
-// Verilog HDL for "gates.lib", "or_gate" "_functional"
-// Module OR gate
-module or_gate (a, b, clk, out);
-
-input
-	a, b, clk;
-
-output
-	out;
-reg 
-	out;
-
-parameter
-	t_hold=5,
-	t_setup=10,
-	delay=15,
-
-	warning_file=3;  // multichannel description of a warning file
-
-reg
-	a_internal, b_internal, clk_internal,
-	a_state, b_state,          // internal state at inputs a and b
-	a_set, b_set;		   // signals determining the moment when
-				   // the state of the a,b inputs changes to "1"
-integer
-	data_delay, 	// delay between a (b) and a_internal (b_internal)
-	clk_delay, 	// delay between clk and clk_internal
-	out_delay, 	// delay between clk_internal and out
-	out_value,	// output value in a given clock cycle
-	last_clk_time;	// time when the last clock pulse appeared
-
-initial 
-	begin
-// define delays between inputs & outputs and the corresponding
-//  internal auxiliary registers
-	  	if(t_hold<0)
-		  begin
-	    		data_delay = -t_hold;
-	    	  	clk_delay = 0;
-		  	out_delay = delay;
-		  end
-	  	else
-		  begin
-	    	  	data_delay = 0;
-	    	  	clk_delay = t_hold;
-		  	out_delay=delay-t_hold;
-		  end
-
-// clear internal registers and the output signal
-		a_internal = 0;
-		b_internal = 0;
-		clk_internal = 0;
-		last_clk_time = 0;
-		a_state = 0;
-		b_state = 0;
-		a_set = 0;
-		b_set = 0;
-		out = 0;
-	end
-
-always @(posedge a) 	// Execute at positive edge of a
-	  a_internal <= #(data_delay) a;
-
-always @(posedge b) 	// Execute at positive edge of b
-	  b_internal <= #(data_delay) b;
-
-always @(posedge clk) 	// Execute at positive edge of clk
-	  clk_internal <= #(clk_delay) clk;
-
-always @(posedge a_internal)
-	begin
-// setting an internal state at the input a
-                a_state <= a_state | 1'bx;
-		if (a_internal === 1)
-		  a_set <= #(t_hold+t_setup) 1;
-
-		a_internal <= 0;
-	end
-
-always @(posedge b_internal)
-	begin
-// setting an internal state at the input a
-                b_state <= b_state | 1'bx;
-		if (b_internal === 1)
-		  b_set <= #(t_hold+t_setup) 1;
-
-		b_internal <= 0;
-	end
-
-always @(posedge a_set)
-	begin
-		if ($stime - last_clk_time >= t_hold+t_setup)
-			a_state = 1;
-		else
-		  begin
-			a_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input A pulse at %0d,",
-			 $stime-data_delay-t_hold-t_setup);
-			$fwrite(warning_file,
-			"\tClock pulse at %0d.\n", last_clk_time-clk_delay);
-		  end
-
-		a_set <= 0;
-	end
-
-always @(posedge b_set)
-	begin
-		if ($stime - last_clk_time >= t_hold+t_setup)
-			b_state = 1;
-		else
-		  begin
-			b_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input B pulse at %0d,",
-			 $stime-data_delay-t_hold-t_setup);
-			$fwrite(warning_file,
-			"\tClock pulse at %0d.\n", last_clk_time-clk_delay);
-		  end
-
-		b_set <= 0;
-	end
-
-
-always @(posedge clk_internal)	
-	begin
-// computing the output
-		if (clk_internal === 1'bx)
-		  out_value = 1'bx;
-		else
-		  out_value = a_state | b_state;
-
-// transfering the result to the output
-		out <= #(out_delay) out_value;
-		out <= #(out_delay+2) 0;
-
-// clearing the internal state of A and B inputs
-		a_state  <= 0;
-		b_state  <= 0;
-
-		clk_internal <= 0;
-		last_clk_time = $stime;
-	end
-
-endmodule
-
-
-  'module', 'or_gate', '(', 'a', 'b', 'clk', 'out', ')', ';',
-     'input', 'a', 'b', 'clk', ';',
-      'output', 'out', ';',
-      'reg', 'out', ';',
-       'parameter',
-        't_hold', '=', '5',
-        't_setup', '=', '10',
-        'delay', '=', '15',
-        'warning_file', '=', '3',
-        ';',
-       'reg',
-        'a_internal',
-        'b_internal',
-        'clk_internal',
-        'a_state',
-        'b_state',
-        'a_set',
-        'b_set',
-        ';',
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-        'clk_delay',
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-        'last_clk_time',
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-                    ')',
-                    ';',
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-                    ')',
-                    ';',
-                   '$fwrite',
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-                    ')',
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-                    'last_clk_time',
-                    '-',
-                    'clk_delay',
-                    ')',
-                    ';',
-                'end',
-            'b_set', '<=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'clk_internal', ')',
-         'begin',
-            'if',
-              '(', 'clk_internal', '===', "1 'b x", ')',
-              'out_value', '=', "1 'b x", ';',
-              'else',
-              'out_value', '=', 'a_state', '|', 'b_state', ';',
-             'out', '<=', '#', '(', 'out_delay', ')', 'out_value',
-              ';',
-             'out', '<=', '#', '(', 'out_delay', '+', '2', ')', '0',
-              ';',
-            'a_state', '<=', '0', ';',
-            'b_state', '<=', '0', ';',
-            'clk_internal', '<=', '0', ';',
-            'last_clk_time', '=', '$stime', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/out_port.v.parsed.txt Deleted

@@ -1,266 +0,0 @@
-/* Output port */
-// Author Andrew Laffely
-// Last modified: 12 Feb 03
-// !!!!!!!!!!!!!!! DO NOT CHANGE THIS FILE !!!!!!!!!!!!!!!!!!!!!!!!!
-module out_port (gclock, reset, i_addr, c_data, c_addr, c_write, valid_next, data_out, ready);
-
-input gclock, reset;
-input 1:0 i_addr;     // buffer address requested by ccm
-input 1:0 c_addr;     // buffer address requested by core
-input 31:0 c_data;    // the data sent from the core
-input valid_next;       // flow control bit sent from upstream block
-input c_write;	        // write singal from core
-
-output 32:0 data_out; // the data to be sent to interface
-output 2:0 ready;     // flow control, port "ready" signal, sent to core
-reg 32:0 data_out;
-reg 2:0 ready;        // Port ready signal
-
-reg 6:0 valid;        // contains the valid bits of the data in the port
-reg 31:0 data 6:0;  // the data in the cdm
-reg 2:0 i_addr_hold;  // hold the buf addr while evaluating  
-reg 2:0 c_addr_hold;  // hold the buf addr while evaluating
-reg 2:0 i_buf_state, c_buf_state; // first or second buf in each port
-
-reg faketiming;         // Makes level sensitive transitions work properly
-initial
-begin
-	faketiming = 1'b0;
-	forever #1 faketiming = ~faketiming;
-end
-
-// *********************** INTERCONNECT *********************** //
-always @ (posedge gclock)  //interconnect side
-  begin
-    if(!reset)
-      begin
-	//update valid from last transfer
-	if(!(i_addr_hold2:1 == 2'b11))  
-	  begin
-	    if(!(valid_next)&&data_out32)
-	      begin
-		i_buf_statei_addr_hold2:1=~i_buf_statei_addr_hold2:1;
-		validi_addr_hold=0;
-	      end
-	  end
-
-	#1 i_addr_hold = {i_addr,i_buf_statei_addr};
-
-	//send data
-	if(!(i_addr == 2'b11))  //default no data
-		#1 data_out={validi_addr_hold, datai_addr_hold};
-	else
-		#1 data_out32=0;
-	end
-end
-// ******************** END INTERCONNECT *********************** //
-
-// *************************** CORE **************************** //
-always @ (posedge c_write)
-  begin
-	c_addr_hold = {c_addr, c_buf_statec_addr};
-  end
-
-always @ (negedge c_write) //Core
-  begin
-	if(!reset)
-	  begin
-		c_buf_statec_addr_hold2:1=~c_buf_statec_addr_hold2:1;
-		validc_addr_hold=1;  //glitch reset
-	  end
-  end
-// ************************** END CORE ************************* //
-
-always @ (faketiming)
-  begin
-    if (reset)
-      begin
-	valid = 4'b0000;
-	i_addr_hold = 3'b111;
-	i_buf_state=3'b000;
-	c_buf_state=3'b000;
-      end
-   else
-      begin
-	ready0=~validc_buf_state0;
-	ready1=~validc_buf_state1;
-	ready2=~validc_buf_state2;
-
-	// *************************** CORE ************************ //
-	if (c_write)
-	  begin
-		datac_addr_hold=c_data31:0;
-	  end
-	// ************************ END CORE ********************** //
-  end
-end
-endmodule
-
-
-
-   'module',
-      'out_port',
-      '(',
-       'gclock',
-        'reset',
-        'i_addr',
-        'c_data',
-        'c_addr',
-        'c_write',
-        'valid_next',
-        'data_out',
-        'ready',
-      ')',
-      ';',
-     'input', 'gclock', 'reset', ';',
-      'input', '', '1', ':', '0', '', 'i_addr', ';',
-      'input', '', '1', ':', '0', '', 'c_addr', ';',
-      'input', '', '31', ':', '0', '', 'c_data', ';',
-      'input', 'valid_next', ';',
-      'input', 'c_write', ';',
-      'output', '', '32', ':', '0', '', 'data_out', ';',
-      'output', '', '2', ':', '0', '', 'ready', ';',
-      'reg', '', '32', ':', '0', '', 'data_out', ';',
-      'reg', '', '2', ':', '0', '', 'ready', ';',
-      'reg', '', '6', ':', '0', '', 'valid', ';',
-      'reg', '', '31', ':', '0', '', 'data', '', '6', ':', '0', '', ';',
-      'reg', '', '2', ':', '0', '', 'i_addr_hold', ';',
-      'reg', '', '2', ':', '0', '', 'c_addr_hold', ';',
-      'reg', '', '2', ':', '0', '', 'i_buf_state', 'c_buf_state', ';',
-      'reg', 'faketiming', ';',
-       'initial',
-         'begin',
-           'faketiming', '=', "1 'b 0", ';',
-             'forever',
-              '#', '1', 'faketiming', '=', '~', 'faketiming', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'gclock', ')',
-         'begin',
-            'if',
-              '(', '!', 'reset', ')',
-               'begin',
-                  'if',
-                     '(',
-                      '!',
-                      '(',
-                      'i_addr_hold', '', '2', '1', '', '==', "2 'b 11",
-                      ')',
-                      ')',
-                     'begin',
-                        'if',
-                           '(',
-                            '!',
-                            '(',
-                            'valid_next',
-                            ')',
-                            '&&',
-                            'data_out', '', '32', '',
-                            ')',
-                           'begin',
-                                'i_buf_state',
-                                     '',
-                                      'i_addr_hold', '', '2', '1', '',
-                                      '',
-                                  '=',
-                                  '~',
-                                   'i_buf_state',
-                                     '',
-                                      'i_addr_hold', '', '2', '1', '',
-                                      '',
-                                ';',
-                                'valid', '', 'i_addr_hold', '',
-                                  '=',
-                                  '0',
-                                ';',
-                            'end',
-                      'end',
-                   '#', '1',
-                      'i_addr_hold',
-                        '=',
-                         '{',
-                          'i_addr',
-                          'i_buf_state', '', 'i_addr', '',
-                          '}',
-                      ';',
-                   'if',
-                    '(', '!', '(', 'i_addr', '==', "2 'b 11", ')', ')',
-                     '#', '1',
-                        'data_out',
-                          '=',
-                           '{',
-                            'valid', '', 'i_addr_hold', '',
-                            'data', '', 'i_addr_hold', '',
-                            '}',
-                        ';',
-                    'else',
-                     '#', '1',
-                      'data_out', '', '32', '', '=', '0', ';',
-                'end',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'c_write', ')',
-         'begin',
-             'c_addr_hold',
-                '=',
-                 '{',
-                  'c_addr',
-                  'c_buf_state', '', 'c_addr', '',
-                  '}',
-              ';',
-          'end',
-       'always',
-        '@', '(', 'negedge', 'c_write', ')',
-         'begin',
-            'if',
-              '(', '!', 'reset', ')',
-               'begin',
-                    'c_buf_state',
-                        '', 'c_addr_hold', '', '2', '1', '', '',
-                      '=',
-                      '~',
-                       'c_buf_state',
-                        '', 'c_addr_hold', '', '2', '1', '', '',
-                    ';',
-                  'valid', '', 'c_addr_hold', '', '=', '1', ';',
-                'end',
-          'end',
-       'always',
-        '@', '(', 'faketiming', ')',
-         'begin',
-            'if',
-              '(', 'reset', ')',
-               'begin',
-                 'valid', '=', "4 'b 0000", ';',
-                  'i_addr_hold', '=', "3 'b 111", ';',
-                  'i_buf_state', '=', "3 'b 000", ';',
-                  'c_buf_state', '=', "3 'b 000", ';',
-                'end',
-              'else',
-               'begin',
-                   'ready', '', '0', '',
-                      '=',
-                      '~',
-                      'valid', '', 'c_buf_state', '', '0', '', '',
-                    ';',
-                    'ready', '', '1', '',
-                      '=',
-                      '~',
-                      'valid', '', 'c_buf_state', '', '1', '', '',
-                    ';',
-                    'ready', '', '2', '',
-                      '=',
-                      '~',
-                      'valid', '', 'c_buf_state', '', '2', '', '',
-                    ';',
-                   'if',
-                    '(', 'c_write', ')',
-                     'begin',
-                         'data', '', 'c_addr_hold', '',
-                            '=',
-                            'c_data', '', '31', '0', '',
-                          ';',
-                      'end',
-                'end',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/pic.v.parsed.txt Deleted

@@ -1,6283 +0,0 @@
-// 
-// SYNTHETIC PIC 2.0                                          4/23/98
-//
-//    This is a synthesizable Microchip 16C57 compatible
-//    microcontroller.  This core is not intended as a high fidelity model of
-//    the PIC, but simply a way to offer a simple processor core to people
-//    familiar with the PIC who also have PIC tools.  
-//
-//    pictest.v  -   top-level testbench (NOT SYNTHESIZABLE)
-//    piccpu.v   -   top-level synthesizable module
-//    picregs.v  -   register file instantiated under piccpu
-//    picalu.v   -   ALU instantiated under piccpu
-//    picidec.v  -   Instruction Decoder instantiated under piccpu
-//    hex2rom.c  -   C program used to translate MPLAB's INTEL HEX output
-//                   into the Verilog $readmemh compatible file
-//    test*.asm  -   (note the wildcard..) Several test programs used
-//                   to help debug the verilog.  I used MPLAB and the simulator
-//                   to develop these programs and get the expected results.
-//                   Then, I ran them on Verilog-XL where they appeared to
-//                   match.
-//
-//    Copyright, Tom Coonan, '97.
-//    Use freely, but not for resale as is.  You may use this in your
-//    own projects as desired.  Just don't try to sell it as is!
-//
-//
-module picalu (
-   op,
-   a,
-   b,
-   y,
-   cin,
-   cout,
-   zout
-);
-
-input  3:0	op;	// ALU Operation
-input  7:0	a;	// 8-bit Input a
-input  7:0	b;	// 8-bit Input b
-output 7:0	y;	// 8-bit Output
-input		cin;
-output		cout;
-output		zout;
-
-// Reg declarations for outputs
-reg		cout;
-reg		zout;
-reg 7:0	y;
-
-// Internal declarations
-reg		addercout; // Carry out straight from the adder itself.
- 
-parameter 3:0 ALUOP_ADD        = 4'b0000;
-parameter 3:0 ALUOP_SUB        = 4'b1000;
-parameter 3:0 ALUOP_AND        = 4'b0001;
-parameter 3:0 ALUOP_OR         = 4'b0010;
-parameter 3:0 ALUOP_XOR        = 4'b0011;
-parameter 3:0 ALUOP_COM        = 4'b0100;
-parameter 3:0 ALUOP_ROR        = 4'b0101;
-parameter 3:0 ALUOP_ROL        = 4'b0110;
-parameter 3:0 ALUOP_SWAP       = 4'b0111;
-
-always @(a or b or cin or op) begin
-   case (op) // synopsys full_case parallel_case
-      ALUOP_ADD:  {addercout,  y}  <= a + b;
-      ALUOP_SUB:  {addercout,  y}  <= a - b; // Carry out is really "borrow"
-      ALUOP_AND:  {addercout,  y}  <= {1'b0, a & b};
-      ALUOP_OR:   {addercout,  y}  <= {1'b0, a | b};
-      ALUOP_XOR:  {addercout,  y}  <= {1'b0, a ^ b};
-      ALUOP_COM:  {addercout,  y}  <= {1'b0, ~a};
-      ALUOP_ROR:  {addercout,  y}  <= {a0, cin, a7:1};
-      ALUOP_ROL:  {addercout,  y}  <= {a7, a6:0, cin};
-      ALUOP_SWAP: {addercout,  y}  <= {1'b0, a3:0, a7:4};
-      default:    {addercout,  y}  <= {1'b0, 8'h00};
-   endcase
-end
-
-always @(y)
-   zout <= (y == 8'h00);
-
-always @(addercout or op)
-   if (op == ALUOP_SUB) cout <= ~addercout; // Invert adder's carry to get borrow
-   else                 cout <=  addercout;
-      
-endmodule
-// 
-// SYNTHETIC PIC 2.0                                          4/23/98
-//
-//    This is a synthesizable Microchip 16C57 compatible
-//    microcontroller.  This core is not intended as a high fidelity model of
-//    the PIC, but simply a way to offer a simple processor core to people
-//    familiar with the PIC who also have PIC tools.  
-//
-//    pictest.v  -   top-level testbench (NOT SYNTHESIZABLE)
-//    piccpu.v   -   top-level synthesizable module
-//    picregs.v  -   register file instantiated under piccpu
-//    picalu.v   -   ALU instantiated under piccpu
-//    picidec.v  -   Instruction Decoder instantiated under piccpu
-//    hex2rom.c  -   C program used to translate MPLAB's INTEL HEX output
-//                   into the Verilog $readmemh compatible file
-//    test*.asm  -   (note the wildcard..) Several test programs used
-//                   to help debug the verilog.  I used MPLAB and the simulator
-//                   to develop these programs and get the expected results.
-//                   Then, I ran them on Verilog-XL where they appeared to
-//                   match.
-//
-//    Copyright, Tom Coonan, '97.
-//    Use freely, but not for resale as is.  You may use this in your
-//    own projects as desired.  Just don't try to sell it as is!
-//
-//
-module piccpu (
-   clk,
-   reset,
-   paddr,
-   pdata,
-   portain,
-   portbout,
-   portcout,
-   
-   debugw,
-   debugpc,
-   debuginst,
-   debugstatus
-);
-
-input		clk;
-input		reset;
-output 8:0	paddr;
-input  11:0	pdata;
-input  7:0	portain;
-output 7:0	portbout;
-output 7:0	portcout;
-
-output 7:0	debugw;
-output 8:0	debugpc;
-output 11:0	debuginst;
-output 7:0	debugstatus;
-
-// Register declarations for outputs
-reg 8:0	paddr;
-reg 7:0	portbout;
-reg 7:0	portcout;
-
-// This should be set to the ROM location where our restart vector is.
-// As set here, we have 512 words of program space.
-//
-parameter RESET_VECTOR = 9'h1FF;
-
-parameter	INDF_ADDRESS	= 3'h0,
-		TMR0_ADDRESS	= 3'h1,
-		PCL_ADDRESS	= 3'h2,
-		STATUS_ADDRESS	= 3'h3,
-		FSR_ADDRESS	= 3'h4,
-		PORTA_ADDRESS	= 3'h5,
-		PORTB_ADDRESS	= 3'h6,
-		PORTC_ADDRESS	= 3'h7;
-
-// Experimental custom peripheral, "Lil Adder (a 4-bit adder)" is at this address.
-//
-parameter	EXPADDRESS_LILADDER = 7'h7F;
-
-// *********  Special internal registers
-
-// Instruction Register
-reg  11:0	inst;
-
-// Program Counter
-reg  8:0	pc;
-reg  8:0	pcplus1; // Output of the pc incrementer.
-
-// Stack Registers and Stack "levels" register.
-reg  1:0	stacklevel;
-reg  8:0	stack1;
-reg  8:0	stack2;
-
-// W Register
-reg  7:0	w;
-
-// The STATUS register (#3) is 8 bits wide, however, we only currently use 2 bits
-// of it; the C and Z bit.
-//
-// bit 0  -  C
-// bit 2  -  Z
-//
-reg  7:0	status;
-
-// The FSR register is the pointer register used for Indirect addressing (e.g. using INDF).
-reg   7:0	fsr;
-
-// Timer 0
-reg   7:0	tmr0;
-reg   7:0	prescaler;
-
-// Option Register
-reg 7:0	option;
-
-// Tristate Control registers. We do not neccessarily support bidirectional ports, but
-//    will save a place for these registers and the TRIS instruction.  Use for debug.
-reg 7:0	trisa;
-reg 7:0	trisb;
-reg 7:0	trisc;
-
-// I/O Port registers
-//
-reg 7:0	porta;	// Input PORT
-reg 7:0	portb;	// Output PORT
-reg 7:0	portc;	// Output PORT
-
-// ********** Instruction Related signals ******
-
-reg 		skip;  // When HI force a NOP (all zeros) into inst
-
-reg  2:0	pcinsel;
-
-// Derive special sub signals from inst register
-wire  7:0	k;
-wire  4:0	fsel;
-wire  8:0	longk;
-wire		d;
-wire  2:0	b;
-
-// ********** File Address ************
-//
-// This is the 7-bit Data Address that includes the lower 5-bit fsel, the
-// FSR bits and any indirect addressing.
-// Use this bus to address the Register File as well as all special registers, etc.
-//
-reg 6:0	fileaddr;
-
-// Address Selects
-reg		specialsel;
-reg		regfilesel;
-reg		expsel;
-
-// ******  Instruction Decoder Outputs **************
-
-// Write enable for the actual ZERO and CARRY bits within the status register.
-// Generated by the Instruction Decoder.
-//
-wire 1:0	aluasel;
-wire 1:0	alubsel;
-wire 3:0	aluop;
-
-wire		zwe;
-wire		cwe;
-
-wire		isoption;
-wire		istris;
-
-wire		fwe;	// High if any "register" is being written to at all.
-wire		wwe;	// Write Enable for the W register.  Produced by Instruction Decoder.
-
-// *************  Internal Busses, mux connections, etc.  ********************
-
-// Bit decoder bits.  
-reg 7:0	bd;	// Final decoder value after any polarity inversion.
-reg 7:0	bdec;	// e.g. "Bit Decoded"
-
-// Data in and out of the and out of the register file
-//
-reg 7:0	regfilein;	// Input into Register File, is connected to the dbus.
-wire 7:0	regfileout;	// Path leaving the register file, goes to SBUS Mux
-reg		regfilewe;	// Write Enable
-reg		regfilere;	// Read Enable
-
-//
-// The dbus (Destination Bus) comes out of the ALU.  It is available to all
-// writable registers.
-//
-// The sbus (Source Bus) comes from all readable registers as well as the output
-// of the Register File.  It is one of the primary inputs into the ALU muxes.
-//
-// The ebus (Expansion Bus) comes from any of our custom modules.  They must
-// all coordinate to place whoever's data onto ebus.
-//
-reg  7:0	dbus;
-reg  7:0	sbus;
-reg  7:0	ebus;
-
-
-// ALU Signals
-//
-reg  7:0	alua;
-reg  7:0	alub;
-wire 7:0	aluout;
-wire 		alucin;
-wire		alucout;
-wire       	aluz;
-
-// ALU A and B mux selects.
-//
-parameter 1:0	ALUASEL_W	= 2'b00,
-		ALUASEL_SBUS	= 2'b01,
-		ALUASEL_K	= 2'b10,
-		ALUASEL_BD	= 2'b11;
-		
-parameter 1:0	ALUBSEL_W	= 2'b00,
-		ALUBSEL_SBUS	= 2'b01,
-		ALUBSEL_K	= 2'b10,
-		ALUBSEL_1	= 2'b11;
-
-// ALU Operation codes.
-//		
-parameter  3:0 ALUOP_ADD  = 4'b0000;
-parameter  3:0 ALUOP_SUB  = 4'b1000;
-parameter  3:0 ALUOP_AND  = 4'b0001;
-parameter  3:0 ALUOP_OR   = 4'b0010;
-parameter  3:0 ALUOP_XOR  = 4'b0011;
-parameter  3:0 ALUOP_COM  = 4'b0100;
-parameter  3:0 ALUOP_ROR  = 4'b0101;
-parameter  3:0 ALUOP_ROL  = 4'b0110;
-parameter  3:0 ALUOP_SWAP = 4'b0111;
-
-
-// Instantiate each of our subcomponents
-//
-picregs  regs (
-   .clk		(clk), 
-   .reset	(reset),
-   .we  	(regfilewe),
-   .re		(regfilere),
-   .bank	(fileaddr6:5), 
-   .location	(fileaddr4:0),
-   .din		(regfilein), 
-   .dout	(regfileout)
-);
-
-// Instatiate the ALU.
-//
-picalu   alu  (
-   .op         (aluop), 
-   .a          (alua), 
-   .b          (alub),
-   .y          (aluout),
-   .cin        (status0), 
-   .cout       (alucout), 
-   .zout       (aluz)
-);
-
-// Instantiate the Instruction Decoder.  This is really just a lookup table.
-// Given the instruction, generate all the signals we need.  
-//
-// For example, each instruction implies a specific ALU operation.  Some of
-// these are obvious such as the ADDW uses an ADD alu op.  Less obvious is
-// that a mov instruction uses an OR op which lets us do a simple copy.
-// 
-// Data has to funnel through the ALU, which sometimes makes for contrived
-// ALU ops.
-//
-picidec  idec (
-   .inst     (inst),
-   .aluasel  (aluasel),
-   .alubsel  (alubsel),
-   .aluop    (aluop),
-   .wwe      (wwe),
-   .fwe      (fwe),
-   .zwe      (zwe),
-   .cwe      (cwe),
-   .bdpol    (bdpol),
-   .option   (isoption),
-   .tris     (istris)
-);
-
-// *********** Debug ****************
-assign	debugw = w;
-assign	debugpc = pc;
-assign	debuginst = inst;
-assign	debugstatus = status;
-
-// *********** REGISTER FILE Addressing ****************
-//
-// We implement the following:
-//    - The 5-bit fsel address is within a "BANK" which is 32 bytes.
-//    - The FSR bits 6:5 are the BANK select, so there are 4 BANKS, a 
-//      total of 128 bytes.  Minus the 8 special registers, that's 
-//      really 120 bytes.
-//    - The INDF register is for indirect addressing.  Referencing INDF
-//      uses FSR as the pointer.  Therefore, using INDF/FSR you address
-//      7-bits of memory.
-// We DO NOT currently implement the PAGE for program (e.g. STATUS register
-// bits 6:5)
-//
-// The fsel address *may* be zero in which case, we are to do indirect
-// addressing, using FSR register as the 8-bit pointer.
-//
-// Otherwise, use the 5-bits of FSEL (from the Instruction itself) and 
-// 2 bank bits from the FSR register (bits 6:5).
-//
-always @(fsel or fsr) begin
-   if (fsel == INDF_ADDRESS) begin
-      // The INDEX register is addressed.  There really is no INDEX register.
-      // Use the FSR as an index, e.g. the FSR contents are the fsel.
-      //
-      fileaddr <= fsr6:0;
-   end
-   else begin
-      // Use FSEL field and status bank select bits
-      //
-      fileaddr <= {fsr6:5, fsel};
-   end
-end
-
-// Write Enable to Register File.  
-// Assert this when the general fwe (write enable to *any* register) is true AND Register File
-//    address range is specified.
-//  
-always @(regfilesel or fwe)
-   regfilewe <= regfilesel & fwe;
-
-// Read Enable (this if nothing else, helps in debug.)
-// Assert if Register File address range is specified AND the ALU is actually using some
-//    data off the SBUS.
-//   
-always @(regfilesel or aluasel or alubsel)
-   regfilere <= regfilesel & ((aluasel == ALUASEL_SBUS) | (alubsel == ALUBSEL_SBUS));
-
-// *********** Address Decodes **************
-//
-// Generate 3 selects: specialsel, regfilesel and expsel
-always @(fileaddr) begin
-   casex (fileaddr)
-      7'bXX00XXX: // The SPECIAL Registers are lower 8 addresses, in ALL BANKS
-         begin
-            specialsel	<= 1'b1;
-            regfilesel	<= 1'b0;
-            expsel	<= 1'b0;
-         end
-      7'b1111111: // EXPANSION Registers are the top (1) addresses
-         begin
-            specialsel	<= 1'b0;
-            regfilesel	<= 1'b0;
-            expsel	<= 1'b1;
-         end
-      default:  // Anything else must be in the Register File
-         begin
-            specialsel	<= 1'b0;
-            regfilesel	<= 1'b1;
-            expsel	<= 1'b0;
-         end
-   endcase
-end
-  
-// *********** SBUS **************
-// The sbus (Source Bus) is the output of a multiplexor that takes
-// inputs from the Register File, and all other special registers
-// and input ports.  The Source Bus then, one of the inputs to the ALU
-
-
-// First MUX selects from all the special regsiters
-//
-always @(fsel or fsr or tmr0 or pc or status
-         or porta or portb or portc or regfileout or ebus
-         or specialsel or regfilesel or expsel) begin
-         
-   // For our current mix of registers and peripherals, only the first 8 addresses
-   // are "special" registers (e.g. not in the Register File).  As more peripheral
-   // registers are added, they must be muxed into this MUX as well.
-   //
-   // We currently prohibit tristates.
-   //
-   //
-   if (specialsel) begin
-      // Special register
-      case (fsel2:0) // synopsys parallel_case full_case
-         3'h0:	sbus <= fsr;
-         3'h1:	sbus <= tmr0;
-         3'h2:	sbus <= pc7:0;
-         3'h3:	sbus <= status;
-         3'h4:	sbus <= fsr;
-         3'h5:	sbus <= porta; // PORTA is an input-only port
-         3'h6:	sbus <= portb; // PORTB is an output-only port
-         3'h7:	sbus <= portc; // PORTC is an output-only port
-      endcase
-   end
-   else begin
-      //
-      // Put whatever address equation is neccessary here.  Remember to remove unnecessary
-      // memory elements from Register File (picregs.v).  It'll still work, but they'd be
-      // wasted flip-flops.
-      //
-      if (expsel) begin
-         sbus <= ebus;
-      end
-      else begin
-         if (regfilesel) begin
-            // Final Priority is Choose the register file
-            sbus <= regfileout;
-         end
-         else begin
-            sbus <= 8'h00;
-         end
-      end
-   end
-end
-
-// ************** DBUS ******
-//  The Destination bus is just the output of the ALU.
-//
-always @(aluout)
-   dbus <= aluout;
-
-always @(dbus)
-   regfilein <= dbus;
-   
-// Drive the ROM address bus straight from the PC
-//
-always @(pc)
-   paddr = pc;
-
-
-// Define sub-signals out of inst
-//
-assign k =     inst7:0;
-assign fsel  = inst4:0;
-assign longk = inst8:0;
-assign d     = inst5;
-assign b     = inst7:5;
-
-// Bit Decoder.
-//
-// Simply take the 3-bit b field in the PIC instruction and create the
-// expanded 8-bit decoder field, which is used as a mask.
-//
-
-
-always @(b) begin
-   case (b)
-      3'b000: bdec <= 8'b00000001;
-      3'b001: bdec <= 8'b00000010;
-      3'b010: bdec <= 8'b00000100;
-      3'b011: bdec <= 8'b00001000;
-      3'b100: bdec <= 8'b00010000;
-      3'b101: bdec <= 8'b00100000;
-      3'b110: bdec <= 8'b01000000;
-      3'b111: bdec <= 8'b10000000;
-   endcase
-end
-
-always @(bdec or bdpol)
-   bd <= bdec ^ bdpol;
-
-// Instruction regsiter usually get the ROM data as its input, but
-// sometimes for branching, the skip signal must cause a NOP.
-//
-always @(posedge clk) begin
-   if (reset) begin
-      inst <= 12'h000;
-   end
-   else begin
-      if (skip == 1'b1) begin
-         inst <= 12'b000000000000; // FORCE NOP
-      end
-      else begin
-         inst <= pdata;
-      end
-   end
-end
-
-// SKIP signal.
-//
-// We want to insert the NOP instruction for the following conditions:
-//    GOTO,CALL and RETLW instructions (All have inst11:10 = 2'b10
-//    BTFSS instruction when aluz is HI  (
-//    BTFSC instruction when aluz is LO
-//
-always @(inst or aluz) begin
-   casex ({inst, aluz})
-      13'b10??_????_????_?:    // A GOTO, CALL or RETLW instructions
-         skip <= 1'b1;
-         
-      13'b0110_????_????_1:    // BTFSC instruction and aluz == 1
-         skip <= 1'b1;
-	
-      13'b0111_????_????_0:    // BTFSS instruction and aluz == 0
-         skip <= 1'b1;
-      
-      13'b0010_11??_????_1:    // DECFSZ instruction and aluz == 1
-         skip <= 1'b1;
-	
-      13'b0011_11??_????_1:    // INCFSZ instruction and aluz == 1
-         skip <= 1'b1;
-      default:
-         skip <= 1'b0;
-   endcase
-end
-
-// 4:1 Data MUX into alua
-//
-//
-always @(aluasel or w or sbus or k or bd) begin
-   case (aluasel)
-      2'b00: alua <= w;
-      2'b01: alua <= sbus;
-      2'b10: alua <= k;
-      2'b11: alua <= bd;
-   endcase
-end
-
-// 4:1 Data MUX into alub
-//
-//
-always @(alubsel or w or sbus or k) begin
-   case (alubsel)
-      2'b00: alub <= w;
-      2'b01: alub <= sbus;
-      2'b10: alub <= k;
-      2'b11: alub <= 8'b00000001;
-   endcase
-end
-
-// W Register
-always @(posedge clk) begin
-   if (reset) begin
-      w <= 8'h00;
-   end
-   else begin
-      if (wwe) begin
-         w <= dbus;
-      end
-   end   
-end
-
-// ************ Writes to various Special Registers (fsel between 0 and 7)
-
-// INDF Register (Register #0)
-//
-//    Not a real register.  This is the Indirect Addressing mode register.
-//    See the regfileaddr logic.
-
-// TMR0 Register (Register #1)
-//
-//    Timer0 is currently only a free-running timer clocked by the main system clock.
-//
-always @(posedge clk) begin
-   if (reset) begin
-      tmr0 <= 8'h00;
-   end
-   else begin
-      // See if the status register is actually being written to
-      if (fwe & specialsel & (fsel == TMR0_ADDRESS)) begin
-         // Yes, so just update the register from the dbus
-         tmr0 <= dbus;
-      end
-      else begin
-         // Mask off the prescaler value based on desired divide ratio.
-         // Whenever this is zero, then that is our divided pulse.  Increment
-         // the final timer value when it's zero.
-         //
-         case (option2:0) // synopsys parallel_case full_case
-            3'b000: if (~|(prescaler & 8'b00000001)) tmr0 <= tmr0 + 1;
-            3'b001: if (~|(prescaler & 8'b00000011)) tmr0 <= tmr0 + 1;
-            3'b010: if (~|(prescaler & 8'b00000111)) tmr0 <= tmr0 + 1;
-            3'b011: if (~|(prescaler & 8'b00001111)) tmr0 <= tmr0 + 1;
-            3'b100: if (~|(prescaler & 8'b00011111)) tmr0 <= tmr0 + 1;
-            3'b101: if (~|(prescaler & 8'b00111111)) tmr0 <= tmr0 + 1;
-            3'b110: if (~|(prescaler & 8'b01111111)) tmr0 <= tmr0 + 1;
-            3'b111: if (~|(prescaler & 8'b11111111)) tmr0 <= tmr0 + 1;
-         endcase            
-      end
-   end
-end
-
-// The prescaler is always counting from 00 to FF
-always @(posedge clk) begin
-   if (reset) begin
-      prescaler <= 8'h00;
-   end
-   else begin
-      // See if the status register is actually being written to
-      prescaler <= prescaler + 1;
-   end
-end
-
-
-// PCL Register (Register #2)
-//
-//    PC Lower 8 bits.  This is handled in the PC section below...
-
-
-// STATUS Register (Register #3)
-//
-always @(posedge clk) begin
-   if (reset) begin
-      status <= 8'h00;
-   end
-   else begin
-      // See if the status register is actually being written to
-      if (fwe & specialsel & (fsel == STATUS_ADDRESS)) begin
-         // Yes, so just update the register from the dbus
-         status <= dbus;
-      end
-      else begin
-         // Update status register on a bit-by-bit basis.
-         //
-         // For the carry and zero flags, each instruction has its own rule as
-         // to whether to update this flag or not.  The instruction decoder is
-         // providing us with an enable for C and Z.  Use this to decide whether
-         // to retain the existing value, or update with the new alu status output.
-         //
-         status <= {
-            status7,			// BIT 7: Undefined.. (maybe use for debugging)
-            status6,			// BIT 6: Program Page, HI bit
-            status5,			// BIT 5: Program Page, LO bit
-            status4,			// BIT 4: Time Out bit (not implemented at this time)
-            status3,			// BIT 3: Power Down bit (not implemented at this time)
-            (zwe) ? aluz : status2,	// BIT 2: Z
-            status1,			// BIT 1: DC
-            (cwe) ? alucout : status0	// BIT 0: C
-         };
-      end
-   end
-end
-
-// FSR Register  (Register #4)
-//            
-always @(posedge clk) begin
-   if (reset) begin
-      fsr <= 8'h00;
-   end
-   else begin
-      // See if the status register is actually being written to
-      if (fwe & specialsel & (fsel == FSR_ADDRESS)) begin
-         fsr <= dbus;
-      end
-   end
-end
-
-// OPTION Register
-//
-// The special OPTION instruction should move W into the OPTION register.
-always @(posedge clk) begin
-   if (reset) begin
-      option <= 8'h00;
-   end
-   else begin
-      if (isoption)
-         option <= dbus;
-   end   
-end
-
-// PORTA Input Port   (Register #5)
-//
-// Register anything on the module's porta input on every single clock.
-//
-always @(posedge clk) begin
-   if (reset) begin
-      porta <= 8'h00;
-   end
-   else begin
-      porta <= portain;
-   end   
-end
-
-// PORTB Output Port  (Register #6)
-always @(posedge clk) begin
-   if (reset) begin
-      portb <= 8'h00;
-   end
-   else begin
-      if (fwe & specialsel & (fsel == PORTB_ADDRESS) & ~istris) begin
-         portb <= dbus;
-      end
-   end   
-end
-
-// Connect the output ports to the register output.
-always @(portb)
-   portbout <= portb;
-   
-// PORTC Output Port  (Register #7)
-always @(posedge clk) begin
-   if (reset) begin
-      portc <= 8'h00;
-   end
-   else begin
-      if (fwe & specialsel & (fsel == PORTC_ADDRESS) & ~istris) begin
-         portc <= dbus;
-      end
-   end   
-end
-
-// Connect the output ports to the register output.
-always @(portc)
-   portcout <= portc;
- 
-// TRIS Registers
-always @(posedge clk) begin
-   if (reset) begin
-      trisa <= 8'hff; // Default is to tristate them
-   end
-   else begin
-      if (fwe & specialsel & (fsel == PORTA_ADDRESS) & istris) begin
-         trisa <= dbus;
-      end
-   end   
-end
-
-always @(posedge clk) begin
-   if (reset) begin
-      trisb <= 8'hff; // Default is to tristate them
-   end
-   else begin
-      if (fwe & specialsel & (fsel == PORTB_ADDRESS) & istris) begin
-         trisb <= dbus;
-      end
-   end   
-end
-
-always @(posedge clk) begin
-   if (reset) begin
-      trisc <= 8'hff; // Default is to tristate them
-   end
-   else begin
-      if (fwe & specialsel & (fsel == PORTC_ADDRESS) & istris) begin
-         trisc <= dbus;
-      end
-   end   
-end
-  
-
-// ********** PC AND STACK *************************
-//
-// There are 4 ways to change the PC.  They are:
-//    GOTO  101k_kkkk_kkkk
-//    CALL  1001_kkkk_kkkk
-//    RETLW 1000_kkkk_kkkk
-//    MOVF  0010_0010_0010  (e.g. a write to reg #2)
-//
-// Remember that the skip instructions work by inserting
-// a NOP instruction or not into program stream and don't
-// change the PC.
-//
-
-// We need pc + 1 in several places, so lets define this incrementor and
-// its output signal it in one place so that we never get redundant adders.
-//
-always @(pc)
-   pcplus1 <= pc + 1;
-   
-parameter	PC_SELECT_PCPLUS1	= 3'b000,
-		PC_SELECT_K             = 3'b001,
-		PC_SELECT_STACK1        = 3'b010,
-		PC_SELECT_STACK2        = 3'b011,
-		PC_SELECT_DBUS          = 3'b100,
-		PC_SELECT_RESET_VECTOR  = 3'b101;
-
-// 8:1 Data MUX into PC 
-always @(posedge clk) begin
-   case (pcinsel) // synopsys parallel_case full_case
-      3'b000:  pc <= pcplus1;
-      3'b001:  pc <= k;
-      3'b010:  pc <= stack1;
-      3'b011:  pc <= stack2;
-      3'b100:  pc <= dbus;
-      3'b101:  pc <= RESET_VECTOR;
-      
-      // Don't really carry about these...
-      3'b110:  pc <= pc;
-      3'b111:  pc <= pc;
-   endcase
-end
-
-// Select for the MUX going into the PC.
-//
-//
-always @(inst or stacklevel or reset) begin
-   if (reset == 1'b1) begin
-      pcinsel <= PC_SELECT_RESET_VECTOR;
-   end
-   else begin
-      casex ({inst, stacklevel})
-         14'b101?_????_????_??: pcinsel <= PC_SELECT_K;		// GOTO
-         14'b1001_????_????_??: pcinsel <= PC_SELECT_K;		// CALL
-         14'b1000_????_????_00: pcinsel <= PC_SELECT_STACK1;	// RETLW
-         14'b1000_????_????_01: pcinsel <= PC_SELECT_STACK1;	// RETLW
-         14'b1000_????_????_10: pcinsel <= PC_SELECT_STACK2;	// RETLW
-         14'b1000_????_????_11: pcinsel <= PC_SELECT_STACK2;	// RETLW
-         14'b0010_0010_0010_??: pcinsel <= PC_SELECT_DBUS;	// MOVF where f=PC
-         default:
-            pcinsel <= PC_SELECT_PCPLUS1;
-      endcase
-   end
-end
-
-
-// Implement STACK1 and STACK2 registers
-//
-// The Stack registers are only fed from the PC itself!
-//
-always @(posedge clk) begin
-   if (reset) begin
-      stack1 <= 9'h000;
-   end
-   else begin
-      // CALL instruction
-      if (inst11:8 == 4'b1001) begin
-         case (stacklevel)
-            2'b00:
-               // No previous CALLs 
-               begin
-                  stack1 <= pc;
-                  $display ("Write to STACK1: %0h", pc);
-               end
-            2'b01:
-               // ONE previous CALL 
-               begin
-                  stack2 <= pc;
-                  $display ("Write to STACK2: %0h", pc);
-               end
-            2'b10:
-               // TWO previous CALLs -- This is illegal on the 16C5X! 
-               begin
-                  $display ("Too many CALLs!!");
-               end
-            2'b11: 
-               begin
-                  $display ("Too many CALLs!!");
-               end
-         endcase
-      end
-   end
-end
-
-// Write to stacklevel
-//
-// The stacklevel register keeps track of the current stack depth.  On this
-// puny processor, there are only 2 levels (you could fiddle with this and
-// increase the stack depth).  There are two stack registers, stack1 and stack2.
-// The stack1 register is used first (e.g. the first time a call is performed),
-// then stack2.  As CALLs are done, stacklevel increments.  Conversely, as
-// RETs are done, stacklevel goes down. 
-
-always @(posedge clk) begin
-   if (reset == 1'b1) begin
-      stacklevel <= 2'b00;  // On reset, there should be no CALLs in progress
-   end
-   else begin
-      casex ({inst, stacklevel})
-         // Call instructions
-         14'b1001_????_????_00: stacklevel <= 2'b01;  // Record 1st CALL
-         14'b1001_????_????_01: stacklevel <= 2'b10;  // Record 2nd CALL
-         14'b1001_????_????_10: stacklevel <= 2'b10;  // Already 2! Ignore
-         14'b1001_????_????_11: stacklevel <= 2'b00;  // {shouldn't happen}
-
-         // Return instructions
-         14'b1000_????_????_00: stacklevel <= 2'b00;  // {shouldn't happen}
-         14'b1000_????_????_01: stacklevel <= 2'b00;  // Go back to no CALL in progress
-         14'b1000_????_????_10: stacklevel <= 2'b01;  // Go back to 1 CALL in progress
-         14'b1000_????_????_11: stacklevel <= 2'b10;  // {shouldn't happen} sort of like, Go back to 2 calls in progress
-         default:
-            stacklevel <= stacklevel;
-      endcase
-   end
-end
-
-
-
-// ************  EXPANSION  *************************
-//
-// The following is an example of customization.
-//
-// Example:  Create a read/write port located at address 7F.  It'll be 8-bits, where
-//           the upper 4 bits are outputs and the lower 4 bits are inputs.  
-//           Use indirect addressing to access it (INDF/FSR).  Just for fun, let's
-//           attach a special loop-back circuit between the outputs and inputs.
-//           Let's attach... say... a 4-bit adder.
-//
-
-reg 3:0	special_peripheral_writeable_bits;
-reg 3:0	special_peripheral_readeable_bits;
-
-// Implement the writeable bits.
-//
-always @(posedge clk) begin
-   if (reset) begin
-      special_peripheral_writeable_bits <= 4'b0000;
-   end
-   else begin
-      if (fwe & expsel & (fileaddr == EXPADDRESS_LILADDER)) begin
-         special_peripheral_writeable_bits <= dbus;
-      end
-   end
-end
-
-// Implement the special peripheral function (the 4-bit adder for this example).
-always @(special_peripheral_writeable_bits) begin
-   special_peripheral_readeable_bits <= special_peripheral_writeable_bits + 1;
-end
-
-// Drive the ebus.  With only one custom address, no more muxing needs to be
-// done, but if there are multiple custom circuits, everyone needs to cooperate
-// and drive ebus properly.
-//
-always @(fileaddr or special_peripheral_readeable_bits) begin
-   if (fileaddr == EXPADDRESS_LILADDER)
-      ebus <= special_peripheral_readeable_bits;
-   else
-      ebus <= 8'hff;
-end
-
-endmodule
-// 
-// SYNTHETIC PIC 2.0                                          4/23/98
-//
-//    This is a synthesizable Microchip 16C57 compatible
-//    microcontroller.  This core is not intended as a high fidelity model of
-//    the PIC, but simply a way to offer a simple processor core to people
-//    familiar with the PIC who also have PIC tools.  
-//
-//    pictest.v  -   top-level testbench (NOT SYNTHESIZABLE)
-//    piccpu.v   -   top-level synthesizable module
-//    picregs.v  -   register file instantiated under piccpu
-//    picalu.v   -   ALU instantiated under piccpu
-//    picidec.v  -   Instruction Decoder instantiated under piccpu
-//    hex2rom.c  -   C program used to translate MPLAB's INTEL HEX output
-//                   into the Verilog $readmemh compatible file
-//    test*.asm  -   (note the wildcard..) Several test programs used
-//                   to help debug the verilog.  I used MPLAB and the simulator
-//                   to develop these programs and get the expected results.
-//                   Then, I ran them on Verilog-XL where they appeared to
-//                   match.
-//
-//    Copyright, Tom Coonan, '97.
-//    Use freely, but not for resale as is.  You may use this in your
-//    own projects as desired.  Just don't try to sell it as is!
-//
-//
-// This is the PIC Instruction Decoder.
-//
-// The 12-bit PIC instruction must result in a set of control
-// signals to the ALU, register write enables and other wires.
-// This is purely combinatorial.  This can physically be
-// implemented as a ROM, or, in this implementation a Verilog
-// casex statement is used to directly synthesize the signals.
-// This approach is more portable, and hopefully much reduction
-// occurs in the equations.
-//
-// The Synthetic PIC Manual contains a table that better shows
-// all the required signals per instruction.  I basically
-// took that table and created the Verilog implementation below.
-//
-
-module picidec (
-	inst,
-	aluasel,
-	alubsel,
-	aluop,
-	wwe,
-	fwe,
-	zwe,
-	cwe,
-	bdpol,
-	option,
-	tris
-);
-
-input  11:0	inst;
-
-output 1:0	aluasel;
-output 1:0	alubsel;
-output 3:0	aluop;
-output		wwe;
-output		fwe;
-output		zwe;
-output		cwe;
-output		bdpol;
-output		option;
-output		tris;
-
-reg 14:0 decodes;
-
-// For reference, the ALU Op codes are:
-//
-//   ADD  0000
-//   SUB  1000
-//   AND  0001
-//   OR   0010
-//   XOR  0011
-//   COM  0100
-//   ROR  0101
-//   ROL  0110
-//   SWAP 0111
-
-assign {	aluasel,	// Select source for ALU A input. 00=W, 01=SBUS, 10=K, 11=BD
-		alubsel,	// Select source for ALU B input. 00=W, 01=SBUS, 10=K, 11="1"
-		aluop,		// ALU Operation (see comments above for these codes)
-		wwe,		// W register Write Enable
-		fwe,		// File Register Write Enable
-		zwe,		// Status register Z bit update
-		cwe,		// Status register Z bit update
-		bdpol,		// Polarity on bit decode vector (0=no inversion, 1=invert)
-		tris,		// Instruction is an TRIS instruction
-		option		// Instruction is an OPTION instruction
-	} = decodes;
-
-// This is a large combinatorial decoder.
-// I use the casex statement.
-
-always @(inst) begin
-	casex (inst)
-		// *** Byte-Oriented File Register Operations
-		//
-		//                                 A  A  ALU  W F Z C B T O
-		//                                 L  L   O   W W W W D R P
-		//                                 U  U   P   E E E E P I T
-		//                                 A  B               O S
-		//                                                    L
-		12'b0000_0000_0000: decodes <= 15'b00_00_0000_0_0_0_0_0_0_0; // NOP
-		12'b0000_001X_XXXX: decodes <= 15'b00_00_0010_0_1_0_0_0_0_0; // MOVWF
-		12'b0000_0100_0000: decodes <= 15'b00_00_0011_1_0_1_0_0_0_0; // CLRW
-		12'b0000_011X_XXXX: decodes <= 15'b00_00_0011_0_1_1_0_0_0_0; // CLRF
-		12'b0000_100X_XXXX: decodes <= 15'b01_00_1000_1_0_1_1_0_0_0; // SUBWF (d=0)
-		12'b0000_101X_XXXX: decodes <= 15'b01_00_1000_0_1_1_1_0_0_0; // SUBWF (d=1)
-		12'b0000_110X_XXXX: decodes <= 15'b01_11_1000_1_0_1_0_0_0_0; // DECF  (d=0)
-		12'b0000_111X_XXXX: decodes <= 15'b01_11_1000_0_1_1_0_0_0_0; // DECF  (d=1)
-		12'b0001_000X_XXXX: decodes <= 15'b00_01_0010_1_0_1_0_0_0_0; // IORWF (d=0)
-		12'b0001_001X_XXXX: decodes <= 15'b00_01_0010_0_1_1_0_0_0_0; // IORWF (d=1)
-		12'b0001_010X_XXXX: decodes <= 15'b00_01_0001_1_0_1_0_0_0_0; // ANDWF (d=0)
-		12'b0001_011X_XXXX: decodes <= 15'b00_01_0001_0_1_1_0_0_0_0; // ANDWF (d=1)
-		12'b0001_100X_XXXX: decodes <= 15'b00_01_0011_1_0_1_0_0_0_0; // XORWF (d=0)
-		12'b0001_101X_XXXX: decodes <= 15'b00_01_0011_0_1_1_0_0_0_0; // XORWF (d=1)
-		12'b0001_110X_XXXX: decodes <= 15'b00_01_0000_1_0_1_1_0_0_0; // ADDWF (d=0)
-		12'b0001_111X_XXXX: decodes <= 15'b00_01_0000_0_1_1_1_0_0_0; // ADDWF (d=1)
-		12'b0010_000X_XXXX: decodes <= 15'b01_01_0010_1_0_1_0_0_0_0; // MOVF  (d=0)
-		12'b0010_001X_XXXX: decodes <= 15'b01_01_0010_0_1_1_0_0_0_0; // MOVF  (d=1)
-		12'b0010_010X_XXXX: decodes <= 15'b01_01_0100_1_0_1_0_0_0_0; // COMF  (d=0)
-		12'b0010_011X_XXXX: decodes <= 15'b01_01_0100_0_1_1_0_0_0_0; // COMF  (d=1)
-		12'b0010_100X_XXXX: decodes <= 15'b01_11_0000_1_0_1_0_0_0_0; // INCF  (d=0)
-		12'b0010_101X_XXXX: decodes <= 15'b01_11_0000_0_1_1_0_0_0_0; // INCF  (d=1)
-		12'b0010_110X_XXXX: decodes <= 15'b01_11_1000_1_0_0_0_0_0_0; // DECFSZ(d=0)
-		12'b0010_111X_XXXX: decodes <= 15'b01_11_1000_0_1_0_0_0_0_0; // DECFSZ(d=1)
-		12'b0011_000X_XXXX: decodes <= 15'b01_01_0101_1_0_0_1_0_0_0; // RRF   (d=0)
-		12'b0011_001X_XXXX: decodes <= 15'b01_01_0101_0_1_0_1_0_0_0; // RRF   (d=1)
-		12'b0011_010X_XXXX: decodes <= 15'b01_01_0110_1_0_0_1_0_0_0; // RLF   (d=0)
-		12'b0011_011X_XXXX: decodes <= 15'b01_01_0110_0_1_0_1_0_0_0; // RLF   (d=1)
-		12'b0011_100X_XXXX: decodes <= 15'b01_01_0111_1_0_0_0_0_0_0; // SWAPF (d=0)
-		12'b0011_101X_XXXX: decodes <= 15'b01_01_0111_0_1_0_0_0_0_0; // SWAPF (d=1)
-		12'b0011_110X_XXXX: decodes <= 15'b01_11_0000_1_0_0_0_0_0_0; // INCFSZ(d=0)
-		12'b0011_111X_XXXX: decodes <= 15'b01_11_0000_0_1_0_0_0_0_0; // INCFSZ(d=1)
-
-		// *** Bit-Oriented File Register Operations
-                //
-		//                                 A  A  ALU  W F Z C B T O
-		//                                 L  L   O   W W W W D R P
-		//                                 U  U   P   E E E E P I T
-		//                                 A  B               O S
-		//                                                    L
-		12'b0100_XXXX_XXXX: decodes <= 15'b11_01_0001_0_1_0_0_1_0_0; // BCF
-		12'b0101_XXXX_XXXX: decodes <= 15'b11_01_0010_0_1_0_0_0_0_0; // BSF
-		12'b0110_XXXX_XXXX: decodes <= 15'b11_01_0001_0_0_0_0_0_0_0; // BTFSC
-		12'b0111_XXXX_XXXX: decodes <= 15'b11_01_0001_0_0_0_0_0_0_0; // BTFSS
-
-		// *** Literal and Control Operations
-                //
-		//                                 A  A  ALU  W F Z C B T O
-		//                                 L  L   O   W W W W D R P
-		//                                 U  U   P   E E E E P I T
-		//                                 A  B               O S
-		//                                                    L
-		12'b0000_0000_0010: decodes <= 15'b00_00_0010_0_1_0_0_0_0_1; // OPTION
-		12'b0000_0000_0011: decodes <= 15'b00_00_0000_0_0_0_0_0_0_0; // SLEEP
-		12'b0000_0000_0100: decodes <= 15'b00_00_0000_0_0_0_0_0_0_0; // CLRWDT
-		12'b0000_0000_0101: decodes <= 15'b00_00_0000_0_1_0_0_0_1_0; // TRIS 5
-		12'b0000_0000_0110: decodes <= 15'b00_00_0010_0_1_0_0_0_1_0; // TRIS 6
-		12'b0000_0000_0111: decodes <= 15'b00_00_0010_0_1_0_0_0_1_0; // TRIS 7
-                //
-		//                                 A  A  ALU  W F Z C B T O
-		//                                 L  L   O   W W W W D R P
-		//                                 U  U   P   E E E E P I T
-		//                                 A  B               O S
-		//                                                    L
-		12'b1000_XXXX_XXXX: decodes <= 15'b10_10_0010_1_0_0_0_0_0_0; // RETLW
-		12'b1001_XXXX_XXXX: decodes <= 15'b10_10_0010_0_0_0_0_0_0_0; // CALL
-		12'b101X_XXXX_XXXX: decodes <= 15'b10_10_0010_0_0_0_0_0_0_0; // GOTO
-		12'b1100_XXXX_XXXX: decodes <= 15'b10_10_0010_1_0_0_0_0_0_0; // MOVLW
-		12'b1101_XXXX_XXXX: decodes <= 15'b00_10_0010_1_0_1_0_0_0_0; // IORLW
-		12'b1110_XXXX_XXXX: decodes <= 15'b00_10_0001_1_0_1_0_0_0_0; // ANDLW
-		12'b1111_XXXX_XXXX: decodes <= 15'b00_10_0011_1_0_1_0_0_0_0; // XORLW
-
-		default:
-			decodes <= 15'b00_00_0000_0_0_0_0_0_0_0;
-	endcase
-end
-
-endmodule
-
-
-// 
-// SYNTHETIC PIC 2.0                                          4/23/98
-//
-//    This is a synthesizable Microchip 16C57 compatible
-//    microcontroller.  This core is not intended as a high fidelity model of
-//    the PIC, but simply a way to offer a simple processor core to people
-//    familiar with the PIC who also have PIC tools.  
-//
-//    pictest.v  -   top-level testbench (NOT SYNTHESIZABLE)
-//    piccpu.v   -   top-level synthesizable module
-//    picregs.v  -   register file instantiated under piccpu
-//    picalu.v   -   ALU instantiated under piccpu
-//    picidec.v  -   Instruction Decoder instantiated under piccpu
-//    hex2rom.c  -   C program used to translate MPLAB's INTEL HEX output
-//                   into the Verilog $readmemh compatible file
-//    test*.asm  -   (note the wildcard..) Several test programs used
-//                   to help debug the verilog.  I used MPLAB and the simulator
-//                   to develop these programs and get the expected results.
-//                   Then, I ran them on Verilog-XL where they appeared to
-//                   match.
-//
-//    Copyright, Tom Coonan, '97.
-//    Use freely, but not for resale as is.  You may use this in your
-//    own projects as desired.  Just don't try to sell it as is!
-//
-//
-
-//`define DEBUG_SHOWREADS
-//`define DEBUG_SHOWWRITES
-
-// Memory Map:
-//
-// PIC Data Memory addressing is complicated.  See the Data Book for full explanation..
-//
-// Basically, each BANK contains 32 locations.  The lowest 16 locations in ALL Banks
-// are really all mapped to the same bank (bank #0).  The first 8 locations are the Special
-// registers like the STATUS and PC registers.  The upper 16 words in each bank, really are
-// unique to each bank.  The smallest PIC (16C54) only has the one bank #0.
-//
-// So, as a programmer, what you get is this.  No matter what bank you are in (FSR6:5)
-// you always have access to your special registers and also to registers 8-15.  You can
-// change to a 1 of 4 banks by setting FSR6:5 and get 4 different sets of registers
-// 16-31.
-//
-// For numbering purposes, I've numbered the registers as if they are one linear memory
-// space, just like in the Data Book (see Figure 4-15 "Direct/Indirect Addressing").
-// So, the unique 16 registers in bank #1 are named r48 - r63 (I use decimal).  The
-// unique registers in bank #3 are therefore r112 - r127.  There is no r111 because,
-// remember, the lower 16 registers each each bank are all reall the same registers 0-15.
-// 
-// Confused?!  The Data Book explains it better than I can.
-//
-//   bank location 
-//     XX 00rrr  -  The special registers are not implemented in this register file.
-//     XX 01rrr  -  The 8 common words, just above the Special Regs, same for all Banks
-//     00 1rrrr  -  The 16 words unique to Bank #0
-//     01 1rrrr  -  The 16 words unique to Bank #1
-//     10 1rrrr  -  The 16 words unique to Bank #2
-//     11 1rrrr  -  The 16 words unique to Bank #3
-//
-//  So, 
-//     Special Regs are location4:3 == 00
-//     Common Regs are  location4:3 == 01
-//     Words in banks   location4   == 1
-// 
-//
-//  I had problems trying to use simple register file declarations that
-//  would always, always work right, were synthesizable and allowed
-//  me to easily remove locations from the memory space.  SOOOooo... I
-//  did the brute force thing and enumerated all the locations..
-//
-//  Much larger spaces will probably need a RAM and whatever I do would need
-//  custom hacking anyway..  I don't see an obvious solution to all this, but
-//  welcome suggestions..
-//
-module picregs (clk, reset, we, re, bank, location, din, dout);
-
-input		clk;
-input		reset;
-input		we;
-input		re;
-input  1:0	bank;		// Bank 0,1,2,3
-input  4:0	location;	// Location
-input  7:0	din;		// Input 
-output 7:0	dout;		// Output 
-
-//parameter	MAX_ADDRESS = 127;
-
-reg 7:0	dout;
-
-integer index;
-
-// Declare the major busses in and out of each block.
-//
-reg 7:0	commonblockout;	// Data Memory common across all banks
-reg 7:0	highblock0out;	// Upper 16 bytes in BANK #0
-reg 7:0	highblock1out;	// Upper 16 bytes in BANK #1
-reg 7:0	highblock2out;	// Upper 16 bytes in BANK #2
-reg 7:0	highblock3out;	// Upper 16 bytes in BANK #3
-
-reg 7:0	commonblockin;	// Data Memory common across all banks
-reg 7:0	highblock0in;	// Upper 16 bytes in BANK #0
-reg 7:0	highblock1in;	// Upper 16 bytes in BANK #1
-reg 7:0	highblock2in;	// Upper 16 bytes in BANK #2
-reg 7:0	highblock3in;	// Upper 16 bytes in BANK #3
-
-reg		commonblocksel;	// Select
-reg		highblock0sel;	// Select
-reg		highblock1sel;	// Select
-reg		highblock2sel;	// Select
-reg		highblock3sel;	// Select
-// synopsys translate_off
-integer cycle_counter;
-initial cycle_counter = 0;
-always @(negedge clk) begin
-   if (re) begin
-`ifdef DEBUG_SHOWREADS   
-      $display ("%0d Read:  data = %0h(hex), from bank #%0d(dec) location %0h", cycle_counter, dout, bank, location);
-`endif
-   end
-   if (we) begin
-`ifdef DEBUG_SHOWWRITES   
-      $display ("%0d Write: data = %0h(hex), to   bank #%0d(dec) location %0h", cycle_counter, din, bank, location);
-`endif
-   end
-   if (~reset) cycle_counter = cycle_counter + 1;
-end  
-// synopsys translate_on
-
-// READ the Register File
-//
-always @(bank or location or re
-		or commonblockout 
-		or highblock0out 
-		or highblock1out 
-		or highblock2out 
-		or highblock3out) begin
-   if (re) begin		
-      if (location4:3 == 2'b01) begin
-         // This is the lower 8 words, common to all banks, just above special registers
-         dout <= commonblockout;	// Access to first 8 locations past Special Registers 
-      end
-      else begin
-         if (location4) begin
-            // Address is in the upper 16 words on one of the 4 banks
-            case (bank) // synopsys full_case parallel_case
-               2'b00:  dout <= highblock0out;	// Upper 16 words of Bank #0
-               2'b01:  dout <= highblock1out;	// Upper 16 words of Bank #1
-               2'b10:  dout <= highblock2out;	// Upper 16 words of Bank #2
-               2'b11:  dout <= highblock3out;	// Upper 16 words of Bank #3
-            endcase
-         end
-         else begin
-            dout <= 8'hff;
-         end
-      end
-   end
-   else begin
-      dout <= 8'hff;
-   end
-end
-
-// Initial Write logic.
-//
-// Generate the specific write enables based on the PIC's bank/location rules.
-// The individual memory blocks will do the actual synchronous write.
-//
-always @(we or bank or location or reset) begin
-   if (reset) begin
-      commonblocksel <= 1'b0;
-      highblock0sel  <= 1'b0;
-      highblock1sel  <= 1'b0;
-      highblock2sel  <= 1'b0;
-      highblock3sel  <= 1'b0;
-   end
-   else begin
-      if (we) begin
-         if (location4:3 == 2'b01) begin
-            // This is the lower 8 words, common to all banks, just above special registers
-            commonblocksel <= 1'b1;
-            highblock0sel  <= 1'b0;
-            highblock1sel  <= 1'b0;
-            highblock2sel  <= 1'b0;
-            highblock3sel  <= 1'b0;
-         end
-         else begin
-            if (location4) begin
-               // Address is in the upper 16 words on one of the 4 banks
-               commonblocksel <= 1'b0;
-               case (bank) // synopsys full_case parallel_case
-                  2'b00:  {highblock0sel, highblock1sel, highblock2sel, highblock3sel} <= 4'b1000; // Upper 16 words of Bank #0
-                  2'b01:  {highblock0sel, highblock1sel, highblock2sel, highblock3sel} <= 4'b0100; // Upper 16 words of Bank #1
-                  2'b10:  {highblock0sel, highblock1sel, highblock2sel, highblock3sel} <= 4'b0010; // Upper 16 words of Bank #2
-                  2'b11:  {highblock0sel, highblock1sel, highblock2sel, highblock3sel} <= 4'b0001; // Upper 16 words of Bank #3
-               endcase
-            end
-            else begin
-               commonblocksel <= 1'b0;
-               highblock0sel  <= 1'b0;
-               highblock1sel  <= 1'b0;
-               highblock2sel  <= 1'b0;
-               highblock3sel  <= 1'b0;
-            end
-         end
-      end
-      else begin
-         commonblocksel <= 1'b0;
-         highblock0sel  <= 1'b0;
-         highblock1sel  <= 1'b0;
-         highblock2sel  <= 1'b0;
-         highblock3sel  <= 1'b0;
-      end
-   end
-end
-
-// *** Buses feeding the memory blocks are driven directly from din.
-
-always @(din)
-   commonblockin <= din;
-
-always @(din)
-   highblock0in <= din;
-
-always @(din)
-   highblock1in <= din;
-
-always @(din)
-   highblock2in <= din;
-
-always @(din)
-   highblock3in <= din;
-
-// ****************** Common Block *************
-
-reg 7:0	r8, r9, r10, r11, r12, r13, r14, r15;
-
-// Read from common block
-always @(location or
-		r8 or r9 or r10 or r11 or r12 or r13 or r14 or r15) begin
-   case (location2:0)
-      3'h0: commonblockout <= r8;
-      3'h1: commonblockout <= r9;
-      3'h2: commonblockout <= r10;
-      3'h3: commonblockout <= r11;
-      3'h4: commonblockout <= r12;
-      3'h5: commonblockout <= r13;
-      3'h6: commonblockout <= r14;
-      3'h7: commonblockout <= r15;
-   endcase
-end
-      
-// Write to common block
-always @(posedge clk) begin
-   if (we & commonblocksel) begin
-      case (location2:0)
-         3'h0: r8  <= commonblockin;
-         3'h1: r9  <= commonblockin;
-         3'h2: r10 <= commonblockin;
-         3'h3: r11 <= commonblockin;
-         3'h4: r12 <= commonblockin;
-         3'h5: r13 <= commonblockin;
-         3'h6: r14 <= commonblockin;
-         3'h7: r15 <= commonblockin;
-      endcase
-   end
-end
-
-// **************** Highblock0 ****************
-
-reg 7:0	r16, r17, r18, r19, r20, r21, r22, r23;
-reg 7:0	r24, r25, r26, r27, r28, r29, r30, r31;
-
-// Read from high block bank0
-always @(location or
-		r16 or r17 or r18 or r19 or r20 or r21 or r22 or r23 or
-		r24 or r25 or r26 or r27 or r28 or r29 or r30 or r31
-) begin
-   case (location3:0)
-      4'h0: highblock0out <= r16;
-      4'h1: highblock0out <= r17;
-      4'h2: highblock0out <= r18;
-      4'h3: highblock0out <= r19;
-      4'h4: highblock0out <= r20;
-      4'h5: highblock0out <= r21;
-      4'h6: highblock0out <= r22;
-      4'h7: highblock0out <= r23;
-      4'h8: highblock0out <= r24;
-      4'h9: highblock0out <= r25;
-      4'hA: highblock0out <= r26;
-      4'hB: highblock0out <= r27;
-      4'hC: highblock0out <= r28;
-      4'hD: highblock0out <= r29;
-      4'hE: highblock0out <= r30;
-      4'hF: highblock0out <= r31;
-   endcase
-end
-      
-// Write to high block bank 0
-always @(posedge clk) begin
-   if (we & highblock0sel) begin
-      case (location3:0)
-         4'h0: r16 <= highblock0in;
-         4'h1: r17 <= highblock0in;
-         4'h2: r18 <= highblock0in;
-         4'h3: r19 <= highblock0in;
-         4'h4: r20 <= highblock0in;
-         4'h5: r21 <= highblock0in;
-         4'h6: r22 <= highblock0in;
-         4'h7: r23 <= highblock0in;
-         4'h8: r24 <= highblock0in;
-         4'h9: r25 <= highblock0in;
-         4'hA: r26 <= highblock0in;
-         4'hB: r27 <= highblock0in;
-         4'hC: r28 <= highblock0in;
-         4'hD: r29 <= highblock0in;
-         4'hE: r30 <= highblock0in;
-         4'hF: r31 <= highblock0in;
-      endcase
-   end
-end
-
-// **************** Highblock1 ****************
-
-reg 7:0	r48, r49, r50, r51, r52, r53, r54, r55;
-reg 7:0	r56, r57, r58, r59, r60, r61, r62, r63;
-
-// Read
-always @(location or
-		r48 or r49 or r50 or r51 or r52 or r53 or r54 or r55 or
-		r56 or r57 or r58 or r59 or r60 or r61 or r62 or r63
-) begin
-   case (location3:0)
-      4'h0: highblock1out <= r48;
-      4'h1: highblock1out <= r49;
-      4'h2: highblock1out <= r50;
-      4'h3: highblock1out <= r51;
-      4'h4: highblock1out <= r52;
-      4'h5: highblock1out <= r53;
-      4'h6: highblock1out <= r54;
-      4'h7: highblock1out <= r55;
-      4'h8: highblock1out <= r56;
-      4'h9: highblock1out <= r57;
-      4'hA: highblock1out <= r58;
-      4'hB: highblock1out <= r59;
-      4'hC: highblock1out <= r60;
-      4'hD: highblock1out <= r61;
-      4'hE: highblock1out <= r62;
-      4'hF: highblock1out <= r63;
-   endcase
-end
-
-// Write
-always @(posedge clk) begin
-   if (we & highblock1sel) begin
-      case (location3:0)
-         4'h0: r48 <= highblock1in;
-         4'h1: r49 <= highblock1in;
-         4'h2: r50 <= highblock1in;
-         4'h3: r51 <= highblock1in;
-         4'h4: r52 <= highblock1in;
-         4'h5: r53 <= highblock1in;
-         4'h6: r54 <= highblock1in;
-         4'h7: r55 <= highblock1in;
-         4'h8: r56 <= highblock1in;
-         4'h9: r57 <= highblock1in;
-         4'hA: r58 <= highblock1in;
-         4'hB: r59 <= highblock1in;
-         4'hC: r60 <= highblock1in;
-         4'hD: r61 <= highblock1in;
-         4'hE: r62 <= highblock1in;
-         4'hF: r63 <= highblock1in;
-      endcase
-   end
-end
-      
-
-// **************** Highblock2 ****************
-
-reg 7:0	r80, r81, r82, r83, r84, r85, r86, r87;
-reg 7:0	r88, r89, r90, r91, r92, r93, r94, r95;
-
-// Read
-always @(location or
-		r80 or r81 or r82 or r83 or r84 or r85 or r86 or r87 or
-		r88 or r89 or r90 or r91 or r92 or r93 or r94 or r95
-) begin
-   case (location3:0)
-      4'h0: highblock2out <= r80;
-      4'h1: highblock2out <= r81;
-      4'h2: highblock2out <= r82;
-      4'h3: highblock2out <= r83;
-      4'h4: highblock2out <= r84;
-      4'h5: highblock2out <= r85;
-      4'h6: highblock2out <= r86;
-      4'h7: highblock2out <= r87;
-      4'h8: highblock2out <= r88;
-      4'h9: highblock2out <= r89;
-      4'hA: highblock2out <= r90;
-      4'hB: highblock2out <= r91;
-      4'hC: highblock2out <= r92;
-      4'hD: highblock2out <= r93;
-      4'hE: highblock2out <= r94;
-      4'hF: highblock2out <= r95;
-   endcase
-end
-
-// Write
-always @(posedge clk) begin
-   if (we & highblock2sel) begin
-      case (location3:0)
-         4'h0: r80 <= highblock2in;
-         4'h1: r81 <= highblock2in;
-         4'h2: r82 <= highblock2in;
-         4'h3: r83 <= highblock2in;
-         4'h4: r84 <= highblock2in;
-         4'h5: r85 <= highblock2in;
-         4'h6: r86 <= highblock2in;
-         4'h7: r87 <= highblock2in;
-         4'h8: r88 <= highblock2in;
-         4'h9: r89 <= highblock2in;
-         4'hA: r90 <= highblock2in;
-         4'hB: r91 <= highblock2in;
-         4'hC: r92 <= highblock2in;
-         4'hD: r93 <= highblock2in;
-         4'hE: r94 <= highblock2in;
-         4'hF: r95 <= highblock2in;
-      endcase
-   end
-end
-
-// **************** Highblock3 ****************
-
-// *** The Following Registers are removed because of CUSTOM Hardware (see piccpu.v) **
-//
-//    r129 (or 7E)
-//
-// **********
-reg 7:0	r112, r113, r114, r115, r116, r117, r118, r119;
-reg 7:0	r120, r121, r122, r123, r124, r125, r126 ;// /*, r127*/ ;
-
-// Read
-always @(location or
-		r112 or r113 or r114 or r115 or r116 or r117 or r118 or r119 or
-		r120 or r121 or r122 or r123 or r124 or r125 or r126 // /* or r127 */
-) begin
-   case (location3:0)
-      4'h0: highblock3out <= r112;
-      4'h1: highblock3out <= r113;
-      4'h2: highblock3out <= r114;
-      4'h3: highblock3out <= r115;
-      4'h4: highblock3out <= r116;
-      4'h5: highblock3out <= r117;
-      4'h6: highblock3out <= r118;
-      4'h7: highblock3out <= r119;
-      4'h8: highblock3out <= r120;
-      4'h9: highblock3out <= r121;
-      4'hA: highblock3out <= r122;
-      4'hB: highblock3out <= r123;
-      4'hC: highblock3out <= r124;
-      4'hD: highblock3out <= r125;
-      4'hE: highblock3out <= r126;
-      4'hF: highblock3out <= 8'hff ;// /* r127*/ ;
-   endcase
-end
-
-// Write
-always @(posedge clk) begin
-   if (we & highblock3sel) begin
-      case (location3:0)
-         4'h0: r112 <= highblock3in;
-         4'h1: r113 <= highblock3in;
-         4'h2: r114 <= highblock3in;
-         4'h3: r115 <= highblock3in;
-         4'h4: r116 <= highblock3in;
-         4'h5: r117 <= highblock3in;
-         4'h6: r118 <= highblock3in;
-         4'h7: r119 <= highblock3in;
-         4'h8: r120 <= highblock3in;
-         4'h9: r121 <= highblock3in;
-         4'hA: r122 <= highblock3in;
-         4'hB: r123 <= highblock3in;
-         4'hC: r124 <= highblock3in;
-         4'hD: r125 <= highblock3in;
-         4'hE: r126 <= highblock3in;
-         4'hF: ; // /* r127 <= highblock3in */;
-      endcase
-   end
-end
-
-// synopsys translate_off
-`define CLEAR_MEMORY
-`ifdef CLEAR_MEMORY
-initial
-begin
-   $display ("Clearing SRAM.");
-   clear_memory;
-end
-task clear_memory;
-begin
-   // Common registers
-   r8  = 0;
-   r9  = 0;
-   r10 = 0;
-   r11 = 0;
-   r12 = 0;
-   r13 = 0;
-   r14 = 0;
-   r15 = 0;
-
-   // Bank #0
-   r16 = 0;
-   r17 = 0;
-   r18 = 0;
-   r19 = 0;
-   r20 = 0;
-   r21 = 0;
-   r22 = 0;
-   r23 = 0;
-   r24 = 0;
-   r25 = 0;
-   r26 = 0;
-   r27 = 0;
-   r28 = 0;
-   r29 = 0;
-   r30 = 0;
-   r31 = 0;
-
-   // Bank #1
-   r48 = 0;
-   r49 = 0;
-   r50 = 0;
-   r51 = 0;
-   r52 = 0;
-   r53 = 0;
-   r54 = 0;
-   r55 = 0;
-   r56 = 0;
-   r57 = 0;
-   r58 = 0;
-   r59 = 0;
-   r60 = 0;
-   r61 = 0;
-   r62 = 0;
-   r63 = 0;
-
-   // Bank #2
-   r80 = 0;
-   r94 = 0;
-
-   // Bank #3
-   r112 = 0;
-   r126 = 0;
-  
-end
-endtask
-`endif
-// synopsys translate_on 
-endmodule
-// 
-// SYNTHETIC PIC 2.0                                          4/23/98
-//
-//    This is a synthesizable Microchip 16C57 compatible
-//    microcontroller.  This core is not intended as a high fidelity model of
-//    the PIC, but simply a way to offer a simple processor core to people
-//    familiar with the PIC who also have PIC tools.  
-//
-//    pictest.v  -   top-level testbench (NOT SYNTHESIZABLE)
-//    piccpu.v   -   top-level synthesizable module
-//    picregs.v  -   register file instantiated under piccpu
-//    picalu.v   -   ALU instantiated under piccpu
-//    picidec.v  -   Instruction Decoder instantiated under piccpu
-//    hex2rom.c  -   C program used to translate MPLAB's INTEL HEX output
-//                   into the Verilog $readmemh compatible file
-//    test*.asm  -   (note the wildcard..) Several test programs used
-//                   to help debug the verilog.  I used MPLAB and the simulator
-//                   to develop these programs and get the expected results.
-//                   Then, I ran them on Verilog-XL where they appeared to
-//                   match.
-//
-//    Copyright, Tom Coonan, '97.
-//    Use freely, but not for resale as is.  You may use this in your
-//    own projects as desired.  Just don't try to sell it as is!
-//
-//
-`timescale 1ns / 10ps
-
-module pictest;
-
-// Select which test to run HERE..
-parameter	TEST_NUMBER = 9;
-
-// *** Testing variables
-// Debug flags.
-integer		dbg_showporta;	// Are set in an 'initial' for default values, 
-integer		dbg_showportb;	//    override in specific tests...
-integer		dbg_showportc;	// Setting to 1 will cause variable to be displayed.
-integer		dbg_showinst;
-integer		dbg_showrom;
-integer		dbg_showw;
-integer		dbg_showpc;
-
-// cycles counter variables
-integer		dbg_showcycles;	// Set to 1 to see cycles
-integer		dbg_limitcycles;// Set to one to enable maxcycles check
-integer		dbg_maxcycles;	// Limit simulation to some number of cycles.
-integer		cycles;		// Cycles counter.
-
-
-
-// *** Interface to the PICCPU
-reg		clk;
-reg		reset;
-reg  7:0	porta;
-wire 7:0	portb;
-wire 7:0	portc;
-
-reg  11:0	rom0:511;
-wire 8:0	romaddr;
-reg  11:0	romdata;
-
-// ROM Interface
-always @(romaddr) begin
-   romdata = romromaddr;
-end
-
-reg 7:0	last_debugw;
-reg 8:0	last_debugpc;
-reg 11:0	last_debuginst;
-reg 7:0	last_debugstatus;
-wire 7:0	debugw;
-wire 8:0	debugpc;
-wire 11:0	debuginst;
-wire 7:0	debugstatus;
-
-// Instantiate one PICCPU to be tested.
-piccpu piccpu_inst (
-   .clk		(clk),
-   .reset	(reset),
-   .paddr	(romaddr),
-   .pdata	(romdata),
-   .portain	(porta),
-   .portbout	(portb),
-   .portcout	(portc),
-   .debugw	(debugw),
-   .debugpc	(debugpc),
-   .debuginst	(debuginst),
-   .debugstatus	(debugstatus)
-);
-
-// Capture some data
-initial begin
-   $dumpfile ("pic.vcd");
-   $dumpvars (0, pictest);
-end
-
-// Reset
-initial begin
-   reset = 1;
-   #200;
-   reset = 0;
-end
-
-  
-// Drive the clock input
-initial begin
-   clk  = 0;
-   forever begin
-      #50 clk = 1;
-      #50 clk = 0;
-   end
-end
-
-// Debug defaults.  Override in individual test tasks.
-//
-initial begin
-   dbg_showporta  = 0;
-   dbg_showportb  = 0;
-   dbg_showportc  = 0;
-   dbg_showinst   = 0;
-   dbg_showrom    = 0;
-   dbg_showw      = 0;
-   dbg_showpc     = 0;
-   dbg_showcycles = 0;
-   
-   dbg_limitcycles = 1;
-   dbg_maxcycles   = 50000;
-end
-
-// Call the appropriate test task based on the TEST_NUMBER parameter set at top.
-//
-initial begin
-   case (TEST_NUMBER)
-      1: test1;
-      2: test2;
-      3: test3;
-      4: test4;
-      5: test5;
-      6: test6;
-      7: test7;
-      8: test8;
-      9: test9;
-      default: 
-         begin
-            $display ("ERROR: Unknown Test Number: %0d", TEST_NUMBER);
-            $finish;
-         end
-   endcase
-end
-
-task test1;
-begin
-   $display ("SYNTHETIC PIC 2.0.  This is TEST #1");
-   #1;
-   
-   // Only Watch Port B
-   dbg_showportb  = 1;
-   dbg_showcycles = 1;
-
-   $readmemh ("TEST1.ROM", rom);
-   dbg_limitcycles = 1;
-   dbg_maxcycles   = 500;
-end
-endtask
-
-task test2;
-begin
-   $display ("SYNTHETIC PIC 2.0.  This is TEST #2");
-   #1;
-
-   // Only Watch Port B
-   dbg_showportb = 1;
-
-   $readmemh ("TEST2.ROM", rom);
-   dbg_limitcycles = 1;
-   dbg_maxcycles = 500;
-end
-endtask
-
-task test3;
-begin
-   $display ("SYNTHETIC PIC 2.0.  This is TEST #3");
-   #1;
-
-   // Only Watch Port B
-   dbg_showportb = 1;
-
-   $readmemh ("TEST3.ROM", rom);
-   dbg_limitcycles = 1;
-   dbg_maxcycles = 500;
-end
-endtask
-
-task test4;
-begin
-   $display ("SYNTHETIC PIC 2.0.  This is TEST #4");
-   #1;
-
-   // Only Watch Port B
-   dbg_showportb = 1;
-
-   $readmemh ("TEST4.ROM", rom);
-   dbg_limitcycles = 1;
-   dbg_maxcycles = 500;
-end
-endtask
-
-task test5;
-begin
-   $display ("SYNTHETIC PIC 2.0.  This is TEST #5");
-   #1;
-
-   // Only Watch Port B
-   dbg_showportb = 1;
-
-   $readmemh ("TEST5.ROM", rom);
-   dbg_limitcycles = 1;
-   dbg_maxcycles = 500;
-end
-endtask
-
-task test6;
-begin
-   $display ("SYNTHETIC PIC 2.0.  This is TEST #6");
-   #1;
-
-   // Watch Port B and C
-   dbg_showportb = 1;
-   dbg_showportc = 1;
-   dbg_limitcycles = 0;
-
-   $readmemh ("TEST6.ROM", rom);
-   #200;
-   
-   repeat (20) begin
-      porta = $random;
-      #10000;
-   end
-   
-   $finish;
-end
-endtask
-
-task test7;
-begin
-   $display ("SYNTHETIC PIC 2.0.  This is TEST #7");
-   #1;
-
-   // Only Watch Port B
-   dbg_showportb = 1;
-
-   $readmemh ("TEST7.ROM", rom);
-   dbg_limitcycles = 1;
-   dbg_maxcycles = 500;
-end
-endtask
-
-task test8;
-begin
-   $display ("SYNTHETIC PIC 2.0.  This is TEST #8");
-   #1;
-
-   // Watch All ports
-   dbg_showporta = 1;
-   dbg_showportb = 1;
-   dbg_showportc = 1;
-
-   $readmemh ("TEST8.ROM", rom);
-   dbg_limitcycles = 1;
-   dbg_maxcycles = 500;
-end
-endtask
-
-task test9;
-begin
-   $display ("SYNTHETIC PIC 2.0.  This is TEST #9");
-   #1;
-
-   // Watch All ports
-   dbg_showportb = 1;
-   dbg_showportc = 1;
-
-   $readmemh ("TEST9.ROM", rom);
-   dbg_limitcycles = 1;
-   dbg_maxcycles = 2000;
-end
-endtask
-
-// ******** END Of TEST TASKS
-
-// Cycles counter
-//
-initial begin
-   cycles = 0;
-   #1;
-   // Don't start counting until after reset.
-   @(negedge reset);
-   
-   forever begin
-      @(posedge clk);
-      cycles = cycles + 1;
-      if ((cycles % 256) == 0) begin
-         if (dbg_showcycles) begin
-            $display ("#Cycles = %0d", cycles);
-         end
-      end
-   
-      if (dbg_limitcycles) begin
-         if (cycles > dbg_maxcycles) begin
-            $display ("Maximum cycles (%0d) Exceeded.  Halting simulation.", dbg_maxcycles);
-            $finish;
-         end
-      end
-   end
-end
-
-always @(romaddr) begin
-   if (dbg_showrom) 
-      $display ("ROM Address = %h, Data = %h", romaddr, romdata);
-end
-
-always @(porta) begin
-   if (dbg_showporta)
-      $display ("porta changes to: %h", porta);
-end
-
-always @(portb) begin
-   if (dbg_showportb)
-      $display ("portb changes to: %h", portb);
-end
-
-always @(portc) begin
-   if (dbg_showportc)
-      $display ("portc changes to: %h", portc);
-end
-
-initial begin
-   if (dbg_showw) begin
-      forever begin
-         @(negedge clk);
-         if (debugw != last_debugw) begin
-            $display ("W = %0h", debugw);
-         end
-         last_debugw = debugw;
-      end
-   end
-end
-
-initial begin
-   if (dbg_showpc) begin
-      forever begin
-         @(negedge clk);
-         $display ("PC = %0h", debugpc);
-      end
-   end
-end
-
-
-
-reg 11:0 last_pc;
-
-always @(posedge clk) begin
-   last_pc = debugpc;
-end
-
-initial begin
-   if (dbg_showinst) begin
-      forever begin
-        @(negedge clk);
-
-	if (debuginst11:0 == 12'b0000_0000_0000) begin
-		$display ("%h NOP", last_pc);
-	end
-	else if (debuginst11:5 == 7'b0000_001) begin
-		$display ("%h MOVWF  f=0x%0h", last_pc, debuginst4:0);
-	end
-	else if (debuginst == 12'b0000_0100_0000) begin
-		$display ("%h CLRW", last_pc);
-	end
-	else if (debuginst11:5 == 7'b0000_011) begin
-		$display ("%h CLRF  f=0x%0h", last_pc, debuginst4:0);
-	end
-	else if (debuginst11:6 == 7'b0000_10) begin
-		if (piccpu_inst.d == 0)	$display ("%h SUBWF  f=0x%0h, W", last_pc, debuginst4:0);
-		else       	$display ("%h SUBWF  f=0x%0h, f", last_pc, debuginst4:0);
-	end
-
-	else if (debuginst11:6 == 7'b0000_11) begin
-		if (piccpu_inst.d == 0)	$display ("%h DECF  f=0x%0h, W", last_pc, debuginst4:0);
-		else       	$display ("%h DECF  f=0x%0h, f", last_pc, debuginst4:0);
-	end
-	else if (debuginst11:6 == 7'b0001_00) begin
-		if (piccpu_inst.d == 0)	$display ("%h IORWF  f=0x%0h, W", last_pc, debuginst4:0);
-		else       	$display ("%h IORWF  f=0x%0h, f", last_pc, debuginst4:0);
-	end
-	else if (debuginst11:6 == 7'b0001_01) begin
-		if (piccpu_inst.d == 0)	$display ("%h ANDWF  f=0x%0h, W", last_pc, debuginst4:0);
-		else       	$display ("%h ANDWF  f=0x%0h, f", last_pc, debuginst4:0);
-	end
-	else if (debuginst11:6 == 7'b0001_10) begin
-		if (piccpu_inst.d == 0)	$display ("XORWF  f=0x%0h, W", last_pc, debuginst4:0);
-		else       	$display ("%h XORWF  f=0x%0h, f", last_pc, debuginst4:0);
-	end
-	else if (debuginst11:6 == 7'b0001_11) begin
-		if (piccpu_inst.d == 0)	$display ("%h ADDWF  f=0x%0h, W", last_pc, debuginst4:0);
-		else       	$display ("%h ADDWF  f=0x%0h, f", last_pc, debuginst4:0);
-	end
-	else if (debuginst11:6 == 7'b0010_00) begin
-		if (piccpu_inst.d == 0)	$display ("%h MOVF  f=0x%0h, W", last_pc, debuginst4:0);
-		else       	$display ("%h MOVF  f=0x%0h, f", last_pc, debuginst4:0);
-	end
-	else if (debuginst11:6 == 7'b0010_01) begin
-		if (piccpu_inst.d == 0)	$display ("%h COMF  f=0x%0h, W", last_pc, debuginst4:0);
-		else       	$display ("%h COMF  f=0x%0h, f", last_pc, debuginst4:0);
-	end
-	else if (debuginst11:6 == 7'b0010_10) begin
-		if (piccpu_inst.d == 0)	$display ("%h INCF  f=0x%0h, W", last_pc, debuginst4:0);
-		else       	$display ("%h INCF  f=0x%0h, f", last_pc, debuginst4:0);
-	end
-	else if (debuginst11:6 == 7'b0010_11) begin
-		if (piccpu_inst.d == 0)	$display ("%h DECFSZ  f=0x%0h, W", last_pc, debuginst4:0);
-		else       	$display ("%h DECFSZ  f=0x%0h, f", last_pc, debuginst4:0);
-	end
-	else if (debuginst11:6 == 7'b0011_00) begin
-		if (piccpu_inst.d == 0)	$display ("%h RRF  f=0x%0h, W", last_pc, debuginst4:0);
-		else       	$display ("%h RRF  f=0x%0h, f", last_pc, debuginst4:0);
-	end
-	else if (debuginst11:6 == 7'b0011_01) begin
-		if (piccpu_inst.d == 0)	$display ("%h RLF  f=0x%0h, W", last_pc, debuginst4:0);
-		else       	$display ("%h RLF  f=0x%0h, f", last_pc, debuginst4:0);
-	end
-	else if (debuginst11:6 == 7'b0011_10) begin
-		if (piccpu_inst.d == 0)	$display ("%h SWAPF  f=0x%0h, W", last_pc, debuginst4:0);
-		else       	$display ("%h SWAPF  f=0x%0h, f", last_pc, debuginst4:0);
-	end
-	else if (debuginst11:6 == 7'b0011_11) begin
-		if (piccpu_inst.d == 0)	$display ("%h INCFSZ  f=0x%0h, W", last_pc, debuginst4:0);
-		else       	$display ("%h INCFSZ  f=0x%0h, f", last_pc, debuginst4:0);
-	end
-
-	// Bit-Oriented File Register Operations
-	else if (debuginst11:8 == 4'b0100) begin
-		$display ("%h BCF  f=0x%0h, bit=%0d", last_pc, debuginst4:0, piccpu_inst.b);
-	end
-	else if (debuginst11:8 == 4'b0101) begin
-		$display ("%h BCF  f=0x%0h, bit=%0d", last_pc, debuginst4:0, piccpu_inst.b);
-	end
-	else if (debuginst11:8 == 4'b0110) begin
-		if (piccpu_inst.skip) $display ("%h BTFSC  f=0x%0h, bit=%0d  {Will Skip..}", last_pc, debuginst4:0, piccpu_inst.b);
-		else      $display ("%h BTFSC  f=0x%0h, bit=%0d  {Will NOT Skip..}", last_pc, debuginst4:0, piccpu_inst.b);
-	end
-	else if (debuginst11:8 == 4'b0111) begin
-		if (piccpu_inst.skip) $display ("%h BTFSS  f=0x%0h, bit=%0d  {Will Skip..}", last_pc, debuginst4:0, piccpu_inst.b);
-		else      $display ("%h BTFSS  f=0x%0h, bit=%0d  {Will NOT Skip..}", last_pc, debuginst4:0, piccpu_inst.b);
-	end
-
-	// Literal and Control Operations
-	else if (debuginst11:0 == 16'b0000_0000_0010) begin
-		$display ("%h OPTION", last_pc);
-	end
-	else if (debuginst11:0 == 16'b0000_0000_0011) begin
-		$display ("%h SLEEP", last_pc);
-	end
-	else if (debuginst11:0 == 16'b0000_0000_0100) begin
-		$display ("%h CLRWDT", last_pc);
-	end
-	else if (debuginst11:3 == 13'b0000_0000_0) begin
-		$display ("%h TRIS,  f=0x%0h", last_pc, debuginst2:0);
-	end
-	else if (debuginst11:8 == 4'b1000) begin
-		$display ("%h RETLW,  k=0x%0h", last_pc, debuginst7:0);
-	end
-	else if (debuginst11:8 == 4'b1001) begin
-		$display ("%h CALL,  k=0x%0h", last_pc, debuginst7:0);
-	end
-	else if (debuginst11:9 == 3'b101) begin
-		$display ("%h GOTO,  k=0x%0h", last_pc, debuginst8:0);
-	end
-	else if (debuginst11:8 == 4'b1100) begin
-		$display ("%h MOVLW,  k=0x%0h", last_pc, debuginst7:0);
-	end
-	else if (debuginst11:8 == 4'b1101) begin
-		$display ("%h IORLW,  k=0x%0h", last_pc, debuginst7:0);
-	end
-	else if (debuginst11:8 == 4'b1110) begin
-		$display ("%h ANDLW,  k=0x%0h", last_pc, debuginst7:0);
-	end
-	else if (debuginst11:8 == 4'b1111) begin
-		$display ("%h XORLW,  k=0x%0h", last_pc, debuginst7:0);
-	end
-	else begin
-		$display ("Hmmm!  instruction not recognized?! %0h", debuginst);
-	end
-      end
-   end
-end
-
-
-endmodule
-
-
-
-   'module',
-      'picalu',
-      '(',
-      'op', 'a', 'b', 'y', 'cin', 'cout', 'zout',
-      ')',
-      ';',
-     'input', '', '3', ':', '0', '', 'op', ';',
-      'input', '', '7', ':', '0', '', 'a', ';',
-      'input', '', '7', ':', '0', '', 'b', ';',
-      'output', '', '7', ':', '0', '', 'y', ';',
-      'input', 'cin', ';',
-      'output', 'cout', ';',
-      'output', 'zout', ';',
-      'reg', 'cout', ';',
-      'reg', 'zout', ';',
-      'reg', '', '7', ':', '0', '', 'y', ';',
-      'reg', 'addercout', ';',
-       'parameter',
-        '',
-        '3',
-        ':',
-        '0',
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-        'TMR0_ADDRESS', '=', "3 'h 1",
-        'PCL_ADDRESS', '=', "3 'h 2",
-        'STATUS_ADDRESS', '=', "3 'h 3",
-        'FSR_ADDRESS', '=', "3 'h 4",
-        'PORTA_ADDRESS', '=', "3 'h 5",
-        'PORTB_ADDRESS', '=', "3 'h 6",
-        'PORTC_ADDRESS', '=', "3 'h 7",
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-              'decodes', '<=', "15 'b 01_01_0101_1_0_0_1_0_0_0", ';',
-              "12 'b 0011_001X_XXXX",
-              ':',
-              'decodes', '<=', "15 'b 01_01_0101_0_1_0_1_0_0_0", ';',
-              "12 'b 0011_010X_XXXX",
-              ':',
-              'decodes', '<=', "15 'b 01_01_0110_1_0_0_1_0_0_0", ';',
-              "12 'b 0011_011X_XXXX",
-              ':',
-              'decodes', '<=', "15 'b 01_01_0110_0_1_0_1_0_0_0", ';',
-              "12 'b 0011_100X_XXXX",
-              ':',
-              'decodes', '<=', "15 'b 01_01_0111_1_0_0_0_0_0_0", ';',
-              "12 'b 0011_101X_XXXX",
-              ':',
-              'decodes', '<=', "15 'b 01_01_0111_0_1_0_0_0_0_0", ';',
-              "12 'b 0011_110X_XXXX",
-              ':',
-              'decodes', '<=', "15 'b 01_11_0000_1_0_0_0_0_0_0", ';',
-              "12 'b 0011_111X_XXXX",
-              ':',
-              'decodes', '<=', "15 'b 01_11_0000_0_1_0_0_0_0_0", ';',
-              "12 'b 0100_XXXX_XXXX",
-              ':',
-              'decodes', '<=', "15 'b 11_01_0001_0_1_0_0_1_0_0", ';',
-              "12 'b 0101_XXXX_XXXX",
-              ':',
-              'decodes', '<=', "15 'b 11_01_0010_0_1_0_0_0_0_0", ';',
-              "12 'b 0110_XXXX_XXXX",
-              ':',
-              'decodes', '<=', "15 'b 11_01_0001_0_0_0_0_0_0_0", ';',
-              "12 'b 0111_XXXX_XXXX",
-              ':',
-              'decodes', '<=', "15 'b 11_01_0001_0_0_0_0_0_0_0", ';',
-              "12 'b 0000_0000_0010",
-              ':',
-              'decodes', '<=', "15 'b 00_00_0010_0_1_0_0_0_0_1", ';',
-              "12 'b 0000_0000_0011",
-              ':',
-              'decodes', '<=', "15 'b 00_00_0000_0_0_0_0_0_0_0", ';',
-              "12 'b 0000_0000_0100",
-              ':',
-              'decodes', '<=', "15 'b 00_00_0000_0_0_0_0_0_0_0", ';',
-              "12 'b 0000_0000_0101",
-              ':',
-              'decodes', '<=', "15 'b 00_00_0000_0_1_0_0_0_1_0", ';',
-              "12 'b 0000_0000_0110",
-              ':',
-              'decodes', '<=', "15 'b 00_00_0010_0_1_0_0_0_1_0", ';',
-              "12 'b 0000_0000_0111",
-              ':',
-              'decodes', '<=', "15 'b 00_00_0010_0_1_0_0_0_1_0", ';',
-              "12 'b 1000_XXXX_XXXX",
-              ':',
-              'decodes', '<=', "15 'b 10_10_0010_1_0_0_0_0_0_0", ';',
-              "12 'b 1001_XXXX_XXXX",
-              ':',
-              'decodes', '<=', "15 'b 10_10_0010_0_0_0_0_0_0_0", ';',
-              "12 'b 101X_XXXX_XXXX",
-              ':',
-              'decodes', '<=', "15 'b 10_10_0010_0_0_0_0_0_0_0", ';',
-              "12 'b 1100_XXXX_XXXX",
-              ':',
-              'decodes', '<=', "15 'b 10_10_0010_1_0_0_0_0_0_0", ';',
-              "12 'b 1101_XXXX_XXXX",
-              ':',
-              'decodes', '<=', "15 'b 00_10_0010_1_0_1_0_0_0_0", ';',
-              "12 'b 1110_XXXX_XXXX",
-              ':',
-              'decodes', '<=', "15 'b 00_10_0001_1_0_1_0_0_0_0", ';',
-              "12 'b 1111_XXXX_XXXX",
-              ':',
-              'decodes', '<=', "15 'b 00_10_0011_1_0_1_0_0_0_0", ';',
-              'default',
-              ':',
-              'decodes', '<=', "15 'b 00_00_0000_0_0_0_0_0_0_0", ';',
-              'endcase',
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-      '(',
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-      'input', '', '1', ':', '0', '', 'bank', ';',
-      'input', '', '4', ':', '0', '', 'location', ';',
-      'input', '', '7', ':', '0', '', 'din', ';',
-      'output', '', '7', ':', '0', '', 'dout', ';',
-      'reg', '', '7', ':', '0', '', 'dout', ';',
-      'integer', 'index', ';',
-      'reg', '', '7', ':', '0', '', 'commonblockout', ';',
-      'reg', '', '7', ':', '0', '', 'highblock0out', ';',
-      'reg', '', '7', ':', '0', '', 'highblock1out', ';',
-      'reg', '', '7', ':', '0', '', 'highblock2out', ';',
-      'reg', '', '7', ':', '0', '', 'highblock3out', ';',
-      'reg', '', '7', ':', '0', '', 'commonblockin', ';',
-      'reg', '', '7', ':', '0', '', 'highblock0in', ';',
-      'reg', '', '7', ':', '0', '', 'highblock1in', ';',
-      'reg', '', '7', ':', '0', '', 'highblock2in', ';',
-      'reg', '', '7', ':', '0', '', 'highblock3in', ';',
-      'reg', 'commonblocksel', ';',
-      'reg', 'highblock0sel', ';',
-      'reg', 'highblock1sel', ';',
-      'reg', 'highblock2sel', ';',
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-               'begin',
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-                    '"%0d Read:  data = %0h(hex), from bank #%0d(dec) '
-                    'location %0h"',
-                    'cycle_counter',
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-                    'location',
-                    ')',
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-                'end',
-             'if',
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-               'begin',
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-                    '"%0d Write: data = %0h(hex), to   bank #%0d(dec) '
-                    'location %0h"',
-                    'cycle_counter',
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-                    'location',
-                    ')',
-                    ';',
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-            'highblock3out',
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-            'if',
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-                  'if',
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-                      '==',
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-                     'begin',
-                      'dout', '<=', 'commonblockout', ';',
-                      'end',
-                    'else',
-                     'begin',
-                        'if',
-                          '(', 'location', '', '4', '', ')',
-                           'begin',
-                              'case',
-                                '(',
-                                'bank',
-                                ')',
-                                "2 'b 00",
-                                ':',
-                                'dout', '<=', 'highblock0out', ';',
-                                "2 'b 01",
-                                ':',
-                                'dout', '<=', 'highblock1out', ';',
-                                "2 'b 10",
-                                ':',
-                                'dout', '<=', 'highblock2out', ';',
-                                "2 'b 11",
-                                ':',
-                                'dout', '<=', 'highblock3out', ';',
-                                'endcase',
-                            'end',
-                          'else',
-                           'begin',
-                            'dout', '<=', "8 'h ff", ';',
-                            'end',
-                      'end',
-                'end',
-              'else',
-              'begin', 'dout', '<=', "8 'h ff", ';', 'end',
-          'end',
-       'always',
-        '@', '(', 'we', 'bank', 'location', 'reset', ')',
-         'begin',
-            'if',
-              '(', 'reset', ')',
-               'begin',
-                 'commonblocksel', '<=', "1 'b 0", ';',
-                  'highblock0sel', '<=', "1 'b 0", ';',
-                  'highblock1sel', '<=', "1 'b 0", ';',
-                  'highblock2sel', '<=', "1 'b 0", ';',
-                  'highblock3sel', '<=', "1 'b 0", ';',
-                'end',
-              'else',
-               'begin',
-                  'if',
-                    '(', 'we', ')',
-                     'begin',
-                        'if',
-                           '(',
-                            'location', '', '4', '3', '',
-                            '==',
-                            "2 'b 01",
-                            ')',
-                           'begin',
-                             'commonblocksel', '<=', "1 'b 1", ';',
-                              'highblock0sel', '<=', "1 'b 0", ';',
-                              'highblock1sel', '<=', "1 'b 0", ';',
-                              'highblock2sel', '<=', "1 'b 0", ';',
-                              'highblock3sel', '<=', "1 'b 0", ';',
-                            'end',
-                          'else',
-                           'begin',
-                              'if',
-                                '(', 'location', '', '4', '', ')',
-                                 'begin',
-                                   'commonblocksel', '<=', "1 'b 0", ';',
-                                     'case',
-                                      '(',
-                                      'bank',
-                                      ')',
-                                      "2 'b 00",
-                                      ':',
-                                         '{',
-                                            'highblock0sel',
-                                            'highblock1sel',
-                                            'highblock2sel',
-                                            'highblock3sel',
-                                            '}',
-                                          '<=',
-                                          "4 'b 1000",
-                                        ';',
-                                      "2 'b 01",
-                                      ':',
-                                         '{',
-                                            'highblock0sel',
-                                            'highblock1sel',
-                                            'highblock2sel',
-                                            'highblock3sel',
-                                            '}',
-                                          '<=',
-                                          "4 'b 0100",
-                                        ';',
-                                      "2 'b 10",
-                                      ':',
-                                         '{',
-                                            'highblock0sel',
-                                            'highblock1sel',
-                                            'highblock2sel',
-                                            'highblock3sel',
-                                            '}',
-                                          '<=',
-                                          "4 'b 0010",
-                                        ';',
-                                      "2 'b 11",
-                                      ':',
-                                         '{',
-                                            'highblock0sel',
-                                            'highblock1sel',
-                                            'highblock2sel',
-                                            'highblock3sel',
-                                            '}',
-                                          '<=',
-                                          "4 'b 0001",
-                                        ';',
-                                      'endcase',
-                                  'end',
-                                'else',
-                                 'begin',
-                                   'commonblocksel', '<=', "1 'b 0", ';',
-                                    'highblock0sel', '<=', "1 'b 0", ';',
-                                    'highblock1sel', '<=', "1 'b 0", ';',
-                                    'highblock2sel', '<=', "1 'b 0", ';',
-                                    'highblock3sel', '<=', "1 'b 0", ';',
-                                  'end',
-                            'end',
-                      'end',
-                    'else',
-                     'begin',
-                       'commonblocksel', '<=', "1 'b 0", ';',
-                        'highblock0sel', '<=', "1 'b 0", ';',
-                        'highblock1sel', '<=', "1 'b 0", ';',
-                        'highblock2sel', '<=', "1 'b 0", ';',
-                        'highblock3sel', '<=', "1 'b 0", ';',
-                      'end',
-                'end',
-          'end',
-       'always',
-        '@', '(', 'din', ')',
-        'commonblockin', '<=', 'din', ';',
-       'always',
-        '@', '(', 'din', ')',
-        'highblock0in', '<=', 'din', ';',
-       'always',
-        '@', '(', 'din', ')',
-        'highblock1in', '<=', 'din', ';',
-       'always',
-        '@', '(', 'din', ')',
-        'highblock2in', '<=', 'din', ';',
-       'always',
-        '@', '(', 'din', ')',
-        'highblock3in', '<=', 'din', ';',
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-        'r9',
-        'r10',
-        'r11',
-        'r12',
-        'r13',
-        'r14',
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-        ';',
-       'always',
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-            'r9',
-            'r10',
-            'r11',
-            'r12',
-            'r13',
-            'r14',
-            'r15',
-          ')',
-         'begin',
-            'case',
-              '(',
-              'location', '', '2', '0', '',
-              ')',
-              "3 'h 0",
-              ':',
-              'commonblockout', '<=', 'r8', ';',
-              "3 'h 1",
-              ':',
-              'commonblockout', '<=', 'r9', ';',
-              "3 'h 2",
-              ':',
-              'commonblockout', '<=', 'r10', ';',
-              "3 'h 3",
-              ':',
-              'commonblockout', '<=', 'r11', ';',
-              "3 'h 4",
-              ':',
-              'commonblockout', '<=', 'r12', ';',
-              "3 'h 5",
-              ':',
-              'commonblockout', '<=', 'r13', ';',
-              "3 'h 6",
-              ':',
-              'commonblockout', '<=', 'r14', ';',
-              "3 'h 7",
-              ':',
-              'commonblockout', '<=', 'r15', ';',
-              'endcase',
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-        '@', '(', 'posedge', 'clk', ')',
-         'begin',
-            'if',
-              '(', 'we', '&', 'commonblocksel', ')',
-               'begin',
-                  'case',
-                    '(',
-                    'location', '', '2', '0', '',
-                    ')',
-                    "3 'h 0",
-                    ':',
-                    'r8', '<=', 'commonblockin', ';',
-                    "3 'h 1",
-                    ':',
-                    'r9', '<=', 'commonblockin', ';',
-                    "3 'h 2",
-                    ':',
-                    'r10', '<=', 'commonblockin', ';',
-                    "3 'h 3",
-                    ':',
-                    'r11', '<=', 'commonblockin', ';',
-                    "3 'h 4",
-                    ':',
-                    'r12', '<=', 'commonblockin', ';',
-                    "3 'h 5",
-                    ':',
-                    'r13', '<=', 'commonblockin', ';',
-                    "3 'h 6",
-                    ':',
-                    'r14', '<=', 'commonblockin', ';',
-                    "3 'h 7",
-                    ':',
-                    'r15', '<=', 'commonblockin', ';',
-                    'endcase',
-                'end',
-          'end',
-       'reg',
-        '',
-        '7',
-        ':',
-        '0',
-        '',
-        'r16',
-        'r17',
-        'r18',
-        'r19',
-        'r20',
-        'r21',
-        'r22',
-        'r23',
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-        '7',
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-        '0',
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-        'r24',
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-        'r29',
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-            'r19',
-            'r20',
-            'r21',
-            'r22',
-            'r23',
-            'r24',
-            'r25',
-            'r26',
-            'r27',
-            'r28',
-            'r29',
-            'r30',
-            'r31',
-          ')',
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-            'case',
-              '(',
-              'location', '', '3', '0', '',
-              ')',
-              "4 'h 0",
-              ':',
-              'highblock0out', '<=', 'r16', ';',
-              "4 'h 1",
-              ':',
-              'highblock0out', '<=', 'r17', ';',
-              "4 'h 2",
-              ':',
-              'highblock0out', '<=', 'r18', ';',
-              "4 'h 3",
-              ':',
-              'highblock0out', '<=', 'r19', ';',
-              "4 'h 4",
-              ':',
-              'highblock0out', '<=', 'r20', ';',
-              "4 'h 5",
-              ':',
-              'highblock0out', '<=', 'r21', ';',
-              "4 'h 6",
-              ':',
-              'highblock0out', '<=', 'r22', ';',
-              "4 'h 7",
-              ':',
-              'highblock0out', '<=', 'r23', ';',
-              "4 'h 8",
-              ':',
-              'highblock0out', '<=', 'r24', ';',
-              "4 'h 9",
-              ':',
-              'highblock0out', '<=', 'r25', ';',
-              "4 'h A",
-              ':',
-              'highblock0out', '<=', 'r26', ';',
-              "4 'h B",
-              ':',
-              'highblock0out', '<=', 'r27', ';',
-              "4 'h C",
-              ':',
-              'highblock0out', '<=', 'r28', ';',
-              "4 'h D",
-              ':',
-              'highblock0out', '<=', 'r29', ';',
-              "4 'h E",
-              ':',
-              'highblock0out', '<=', 'r30', ';',
-              "4 'h F",
-              ':',
-              'highblock0out', '<=', 'r31', ';',
-              'endcase',
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-       'always',
-        '@', '(', 'posedge', 'clk', ')',
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-              '(', 'we', '&', 'highblock0sel', ')',
-               'begin',
-                  'case',
-                    '(',
-                    'location', '', '3', '0', '',
-                    ')',
-                    "4 'h 0",
-                    ':',
-                    'r16', '<=', 'highblock0in', ';',
-                    "4 'h 1",
-                    ':',
-                    'r17', '<=', 'highblock0in', ';',
-                    "4 'h 2",
-                    ':',
-                    'r18', '<=', 'highblock0in', ';',
-                    "4 'h 3",
-                    ':',
-                    'r19', '<=', 'highblock0in', ';',
-                    "4 'h 4",
-                    ':',
-                    'r20', '<=', 'highblock0in', ';',
-                    "4 'h 5",
-                    ':',
-                    'r21', '<=', 'highblock0in', ';',
-                    "4 'h 6",
-                    ':',
-                    'r22', '<=', 'highblock0in', ';',
-                    "4 'h 7",
-                    ':',
-                    'r23', '<=', 'highblock0in', ';',
-                    "4 'h 8",
-                    ':',
-                    'r24', '<=', 'highblock0in', ';',
-                    "4 'h 9",
-                    ':',
-                    'r25', '<=', 'highblock0in', ';',
-                    "4 'h A",
-                    ':',
-                    'r26', '<=', 'highblock0in', ';',
-                    "4 'h B",
-                    ':',
-                    'r27', '<=', 'highblock0in', ';',
-                    "4 'h C",
-                    ':',
-                    'r28', '<=', 'highblock0in', ';',
-                    "4 'h D",
-                    ':',
-                    'r29', '<=', 'highblock0in', ';',
-                    "4 'h E",
-                    ':',
-                    'r30', '<=', 'highblock0in', ';',
-                    "4 'h F",
-                    ':',
-                    'r31', '<=', 'highblock0in', ';',
-                    'endcase',
-                'end',
-          'end',
-       'reg',
-        '',
-        '7',
-        ':',
-        '0',
-        '',
-        'r48',
-        'r49',
-        'r50',
-        'r51',
-        'r52',
-        'r53',
-        'r54',
-        'r55',
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-        '7',
-        ':',
-        '0',
-        '',
-        'r56',
-        'r57',
-        'r58',
-        'r59',
-        'r60',
-        'r61',
-        'r62',
-        'r63',
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-           'location',
-            'r48',
-            'r49',
-            'r50',
-            'r51',
-            'r52',
-            'r53',
-            'r54',
-            'r55',
-            'r56',
-            'r57',
-            'r58',
-            'r59',
-            'r60',
-            'r61',
-            'r62',
-            'r63',
-          ')',
-         'begin',
-            'case',
-              '(',
-              'location', '', '3', '0', '',
-              ')',
-              "4 'h 0",
-              ':',
-              'highblock1out', '<=', 'r48', ';',
-              "4 'h 1",
-              ':',
-              'highblock1out', '<=', 'r49', ';',
-              "4 'h 2",
-              ':',
-              'highblock1out', '<=', 'r50', ';',
-              "4 'h 3",
-              ':',
-              'highblock1out', '<=', 'r51', ';',
-              "4 'h 4",
-              ':',
-              'highblock1out', '<=', 'r52', ';',
-              "4 'h 5",
-              ':',
-              'highblock1out', '<=', 'r53', ';',
-              "4 'h 6",
-              ':',
-              'highblock1out', '<=', 'r54', ';',
-              "4 'h 7",
-              ':',
-              'highblock1out', '<=', 'r55', ';',
-              "4 'h 8",
-              ':',
-              'highblock1out', '<=', 'r56', ';',
-              "4 'h 9",
-              ':',
-              'highblock1out', '<=', 'r57', ';',
-              "4 'h A",
-              ':',
-              'highblock1out', '<=', 'r58', ';',
-              "4 'h B",
-              ':',
-              'highblock1out', '<=', 'r59', ';',
-              "4 'h C",
-              ':',
-              'highblock1out', '<=', 'r60', ';',
-              "4 'h D",
-              ':',
-              'highblock1out', '<=', 'r61', ';',
-              "4 'h E",
-              ':',
-              'highblock1out', '<=', 'r62', ';',
-              "4 'h F",
-              ':',
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-              '"SYNTHETIC PIC 2.0.  This is TEST #9"',
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-                                '"Maximum cycles (%0d) Exceeded.  Halting '
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-                            "12 'b 0000_0000_0000",
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-                                '"%h NOP"',
-                                'last_pc',
-                                ')',
-                                ';',
-                            'end',
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-                              'debuginst', '', '11', '5', '',
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-                              "7 'b 0000_001",
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-                                  '"%h MOVWF  f=0x%0h"',
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-                                  ')',
-                                  ';',
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-                             'if',
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-                                "12 'b 0000_0100_0000",
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-                                    '"%h CLRW"',
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-                                    ')',
-                                    ';',
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-                                  'debuginst', '', '11', '5', '',
-                                  '==',
-                                  "7 'b 0000_011",
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-                                      '"%h CLRF  f=0x%0h"',
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-                                      ')',
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-                                          ')',
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-                                                      '', '4', '0', '',
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-                                                    'last_pc',
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-                                                      '"%h MOVF  f=0x%0h, f"',
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-                                                        '0',
-                                                        ')',
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-                                                        '(',
-                                                        '"%h COMF  f=0x%0h, W"',
-                                                        'last_pc',
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-                                                          '', '4', '0', '',
-                                                        ')',
-                                                        ';',
-                                                      'else',
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-                                                        '(',
-                                                        '"%h COMF  f=0x%0h, f"',
-                                                        'last_pc',
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-                                                     'debuginst',
-                                                      '', '11', '6', '',
-                                                    '==',
-                                                    "7 'b 0010_10",
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-                                                          '0',
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-                                                          '(',
-                                                          '"%h INCF  f=0x%0h, '
-                                                          'W"',
-                                                          'last_pc',
-                                                           'debuginst',
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-                                                              '4',
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-                                                              '',
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-                                                          '(',
-                                                          '"%h INCF  f=0x%0h, '
-                                                          'f"',
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-                                                       'debuginst',
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-                                                            '0',
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-                                                            '"%h DECFSZ  '
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-                                                                '4',
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-                                                          'else',
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-                                                            '(',
-                                                            '"%h DECFSZ  '
-                                                            'f=0x%0h, f"',
-                                                            'last_pc',
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-                                                              '0',
-                                                              ')',
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-                                                              '"%h RRF  '
-                                                              'f=0x%0h, W"',
-                                                              'last_pc',
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-                                                                  '4',
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-                                                                  '',
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-                                                              '"%h RRF  '
-                                                              'f=0x%0h, f"',
-                                                              'last_pc',
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-                                                              '11',
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-                                                                '0',
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-                                                                '"%h RLF  '
-                                                                'f=0x%0h, W"',
-                                                                'last_pc',
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-                                                                    '',
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-                                                                '(',
-                                                                '"%h RLF  '
-                                                                'f=0x%0h, f"',
-                                                                'last_pc',
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-                                                                '11',
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-                                                                  '0',
-                                                                  ')',
-                                                                 '$display',
-                                                                  '(',
-                                                                  '"%h SWAPF  '
-                                                                  'f=0x%0h, W"',
-                                                                  'last_pc',
-                                                                   'debuginst',
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-                                                                      '4',
-                                                                      '0',
-                                                                      '',
-                                                                  ')',
-                                                                  ';',
-                                                                'else',
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-                                                                  '(',
-                                                                  '"%h SWAPF  '
-                                                                  'f=0x%0h, f"',
-                                                                  'last_pc',
-                                                                   'debuginst',
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-                                                                      '0',
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-                                                                  '11',
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-                                                                     'piccpu_inst.d',
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-                                                                    '0',
-                                                                    ')',
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-                                                                    '(',
-                                                                    '"%h '
-                                                                    'INCFSZ  '
-                                                                    'f=0x%0h, '
-                                                                    'W"',
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-                                                                        '4',
-                                                                        '0',
-                                                                        '',
-                                                                    ')',
-                                                                    ';',
-                                                                  'else',
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-                                                                    '(',
-                                                                    '"%h '
-                                                                    'INCFSZ  '
-                                                                    'f=0x%0h, '
-                                                                    'f"',
-                                                                    'last_pc',
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-                                                                    '"%h BCF  '
-                                                                    'f=0x%0h, '
-                                                                    'bit=%0d"',
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-                                                                      '11',
-                                                                      '8',
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-                                                                  '==',
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-                                                                      '"%h '
-                                                                      'BCF  '
-                                                                      'f=0x%0h, '
-                                                                      'bit=%0d"',
-                                                                       'last_pc',
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-                                                                          '4',
-                                                                          '0',
-                                                                          '',
-                                                                       'piccpu_inst.b',
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-                                                                   '(',
-                                                                     'debuginst',
-                                                                       '',
-                                                                        '11',
-                                                                        '8',
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_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/pipe1.v.parsed.txt Deleted

@@ -1,358 +0,0 @@
-// pipe1.v      Verilog version using modules in this file
-//              basic five stage pipeline of just Instruction Register
-//              The 411 course pipeline has the same five stages
-//              IF Instruction Fetch includes PC and instruction memory
-//              ID Instruction Decode and registers
-//              EX Execution including the ALU Arithmetic Logic Unit
-//              MEM data Memory
-//              WB Write Back into registers
-//
-// This self contained Verilog file defines:
-//
-//     a 32 bit adder module using behavioral code
-//     a 32 bit register module with clock and clear inputs
-//     an instruction memory module using behavioral code
-//
-//     a top level module, pipe1, test bench
-//     the wires for interconnecting the entities
-//     the modules instantiated to connect the wires
-//     printout that shows the registers in the pipeline each clock
-//
-
-`timescale 1ps/1ps // times in pico seconds
-
-module add32(a, b, cin, sum, cout);
-  parameter n=31;
-  input  n:0 a;     // a input
-  input  n:0 b;     // b input
-  input        cin;   // carry-in
-  output n:0 sum;   // sum output
-  output       cout;  // carry-out
-  assign #250 {cout, sum} = a + b + cin;
-endmodule // add32
-
-module register_32(clk, clear, inp, out);
-  input         clk;    // accept  inp  on posedge
-  input         clear;  // clear when high
-  input  31:0 inp;    // input data
-  output 31:0 out;    // output of register
-  wire   31:0 inp;
-  wire   31:0 out;
-  reg    31:0 stored;        // temporary variable
-
-  initial stored = 32'h00000000;
-
-  assign out = stored;  // set output wire
-
-  always @(posedge clk)
-    begin  // behavior
-      #200 stored <= inp;
-    end
-endmodule // register_32
-
-module instruction_memory(addr, inst);
-  input 31:0 addr;
-  output 31:0 inst;
-  integer word_addr;
-  reg 31:0 memory 0:6;
-  reg 31:0 inst_word;
-
-  assign inst = inst_word;
-
-  function 31:0 to_integer;
-    input 31:0 argument;
-    to_integer = argument;
-  endfunction // to_integer
-
-  initial
-    begin
-      memory0 = 32'h00000001;
-      memory1 = 32'h00000002;
-      memory2 = 32'h00000003;
-      memory3 = 32'h00000004;
-      memory4 = 32'h00000005;
-      memory5 = 32'h00000006;
-      memory6 = 32'h00000007;
-    end
-
-  always @(addr)
-    begin  // behavior
-      word_addr = to_integer(addr)/4;
-      #250 inst_word = memoryword_addr;
-    end
-endmodule // instruction_memory
-
-
-module pipe1;  // test bench
-  // signals used in test bench (the interconnections)
-  
-  reg 31:0 zero_32; // = 32'h00000000;   // 32 bit zero
-  reg        zero;    // = 0;              // one bit zero
-  reg 31:0 four_32; // = 32'h00000004;   // four
-
-  reg        clear;   // = 1;    // one shot clear
-  reg        clk;     // = 0;    // master clock
-  integer    counter; // = 0;    // master clock counter, raising edge
-  wire       nc1;                // a No-Connection for unused output
-
-  wire 31:0 IF_PC_next;        // next value of PC 
-  wire 31:0 IF_PC;             // Program Counter
-  wire 31:0 inst;              // instruction fetched
-  wire 31:0 ID_IR;             // ID Instruction Register
-  wire 31:0 EX_IR;             // EX Instruction Register
-  wire 31:0 MEM_IR;            // MEM Instruction Register
-  wire 31:0 WB_IR;             // WB Instruction Register
-
-  function 31:0 to_integer;
-    input 31:0 argument;
-    to_integer = argument;
-  endfunction // to_integer
-  
-  initial
-    begin
-      zero_32 = 32'h00000000;   // 32 bit zero
-      zero    = 0;              // one bit zero
-      four_32 = 32'h00000004;   // four
-      clear   = 1;              // one shot clear
-      clk     = 0;              // master clock
-      counter = 0;              // master clock counter, raising edge
-      #200 clear = 0;           // clear time finished
-      forever #5000 clk = ~clk; // run clock 10ns period
-    end
-
-  initial #60000 $finish; // stop after 60 ns
-
-  // schematic of pipe1, behavior and test bench
-
-  // IF, Instruction Fetch pipeline stage
-  register_32 PC_reg(clk, clear, IF_PC_next, IF_PC);
-  add32 PC_incr(IF_PC, four_32, zero, IF_PC_next, nc1);
-  instruction_memory inst_mem(IF_PC, inst);
-
-  // ID, Instruction Decode and register stack pipeline stage
-  register_32 ID_IR_reg(clk, clear, inst, ID_IR);
-
-  // EX, Execute pipeline stage
-  register_32 EX_IR_reg(clk, clear, ID_IR, EX_IR);
-
-  // MEM Data Memory pipeline stage
-  register_32 MEM_IR_reg(clk, clear, EX_IR, MEM_IR);
-
-  // WB, Write Back pipeline stage
-  register_32 WB_IR_reg(clk, clear, MEM_IR, WB_IR);
-
-  always @(posedge clk) // to show state of registers in pipeline
-    begin
-      $write("at clock ");
-      $write("%0d", counter);
-      $write("  PC=");
-      $write("%h", IF_PC);
-      $write("\n");
-      $write("IF  stage inst=");
-      $write("%h", inst);
-      $write("\n");
-      $write("IF_PC_next    =");
-      $write("%h", IF_PC_next);
-      $write("\n");
-      $write("ID  stage   IR=");
-      $write("%h", ID_IR);
-      $write("\n");
-      $write("EX  stage   IR=");
-      $write("%h", EX_IR);
-      $write("\n");
-      $write("MEM stage   IR=");
-      $write("%h", MEM_IR);
-      $write("\n");
-      $write("WB  stage   IR=");
-      $write("%h", WB_IR);
-      $write("\n");
-      $write("\n");         // blank line
-      counter = counter+1;
-    end
-
-endmodule // pipe1
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-        ';',
-       'register_32',
-        'ID_IR_reg', '(', 'clk', 'clear', 'inst', 'ID_IR', ')',
-        ';',
-       'register_32',
-        'EX_IR_reg', '(', 'clk', 'clear', 'ID_IR', 'EX_IR', ')',
-        ';',
-       'register_32',
-        'MEM_IR_reg', '(', 'clk', 'clear', 'EX_IR', 'MEM_IR', ')',
-        ';',
-       'register_32',
-        'WB_IR_reg', '(', 'clk', 'clear', 'MEM_IR', 'WB_IR', ')',
-        ';',
-       'always',
-        '@', '(', 'posedge', 'clk', ')',
-         'begin',
-           '$write', '(', '"at clock "', ')', ';',
-            '$write', '(', '"%0d"', 'counter', ')', ';',
-            '$write', '(', '"  PC="', ')', ';',
-            '$write', '(', '"%h"', 'IF_PC', ')', ';',
-            '$write', '(', '"\\n"', ')', ';',
-            '$write', '(', '"IF  stage inst="', ')', ';',
-            '$write', '(', '"%h"', 'inst', ')', ';',
-            '$write', '(', '"\\n"', ')', ';',
-            '$write', '(', '"IF_PC_next    ="', ')', ';',
-            '$write', '(', '"%h"', 'IF_PC_next', ')', ';',
-            '$write', '(', '"\\n"', ')', ';',
-            '$write', '(', '"ID  stage   IR="', ')', ';',
-            '$write', '(', '"%h"', 'ID_IR', ')', ';',
-            '$write', '(', '"\\n"', ')', ';',
-            '$write', '(', '"EX  stage   IR="', ')', ';',
-            '$write', '(', '"%h"', 'EX_IR', ')', ';',
-            '$write', '(', '"\\n"', ')', ';',
-            '$write', '(', '"MEM stage   IR="', ')', ';',
-            '$write', '(', '"%h"', 'MEM_IR', ')', ';',
-            '$write', '(', '"\\n"', ')', ';',
-            '$write', '(', '"WB  stage   IR="', ')', ';',
-            '$write', '(', '"%h"', 'WB_IR', ')', ';',
-            '$write', '(', '"\\n"', ')', ';',
-            '$write', '(', '"\\n"', ')', ';',
-            'counter', '=', 'counter', '+', '1', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/pipe2.v.parsed.txt Deleted

@@ -1,1189 +0,0 @@
-// pipe2.v      Verilog version using modules in this file
-//              basic five stage pipeline of just Instruction Register
-//              The 411 course pipeline has the same five stages
-//              IF Instruction Fetch includes PC and instruction memory
-//              ID Instruction Decode and registers
-//              EX Execution including the ALU Arithmetic Logic Unit
-//              MEM data Memory
-//              WB Write Back into registers
-//
-// This self contained Verilog file defines:
-//
-//     a 32 bit adder module using behavioral code
-//     32 and 5 bit register module with clock and clear inputs
-//     an instruction memory module using behavioral code
-//     a data memory module using behavioral code
-//     a general register module using behavioral code
-//     32 and 5 bit multiplexor module using behavioral code
-//
-//     a top level module, pipe2, test bench
-//     the wires for interconnecting the entities
-//     the modules instantiated to connect the wires
-//     printout that shows the registers in the pipeline each clock
-//
-
-`timescale 1ps/1ps // times in pico seconds
-
-module add32(a, b, cin, sum, cout);
-  parameter n=31;
-  input  n:0 a;     // a input
-  input  n:0 b;     // b input
-  input        cin;   // carry-in
-  output n:0 sum;   // sum output
-  output       cout;  // carry-out
-  assign #250 {cout, sum} = a + b + cin;
-endmodule // add32
-
-
-module register_32(clk, clear, inp, out);
-  input         clk;    // accept  inp  on posedge
-  input         clear;  // clear when high
-  input  31:0 inp;    // input data
-  output 31:0 out;    // output of register
-  wire   31:0 inp;
-  wire   31:0 out;
-  reg    31:0 stored;        // temporary variable
-
-  initial stored = 32'h00000000;
-
-  assign out = stored;  // set output wire
-
-  always @(posedge clk) #200 stored <= inp;
-endmodule // register_32
-
-
-module register_5(clk, clear, inp, out);
-  input        clk;    // accept  inp  on posedge
-  input        clear;  // clear when high
-  input  4:0 inp;    // input data
-  output 4:0 out;    // output of register
-  wire   4:0 out;
-  reg    4:0 stored;        // temporary variable
-
-  initial stored = 5'b00000;
-
-  assign out = stored;  // set output wire
-
-  always @(posedge clk) #200 stored <= inp;
-endmodule // register_5
-
-
-module instruction_memory(addr, inst);
-  input 31:0 addr;
-  output 31:0 inst;
-  integer word_addr;
-  reg 31:0 memory 0:15;
-  reg 31:0 inst_word;
-
-  assign inst = inst_word;
-
-  function 31:0 to_integer;
-    input 31:0 argument;
-    to_integer = argument;
-  endfunction // to_integer
-
-  initial
-    begin
-      memory0 = 32'b10001100000000010000000000000100;  // lw
-      memory1 = 32'b10001100000000100000000000001000;  // lw
-      memory2 = 32'b00000000000000000000000000000000;  // nop
-      memory3 = 32'b00000000000000000000000000000000;  // nop
-      memory4 = 32'b00000000001000100001100000100000;  // add
-      memory5 = 32'b00000000011000100010000000100010;  // sub
-      memory6 = 32'b00000000000000010010101111000001;  // sll
-      memory7 = 32'b00000000000000100011010000000010;  // srl
-      memory8 = 32'b00000000000000110011100000000100;  // cmpl
-      memory9 = 32'b10101100000000010000000000001000;  // sw
-      memory10= 32'b00000000000000000000000000000000;  // nop
-      memory11= 32'b00000000000000000000000000000000;  // nop
-      memory12= 32'b00000000000000000000000000000000;  // nop
-      memory13= 32'b00000000000000000000000000000000;  // nop
-      memory14= 32'b00000000000000000000000000000000;  // nop
-      memory15= 32'b00000000000000000000000000000000;  // nop
-    end
-
-  always @(addr)
-    begin  // behavior
-      word_addr = to_integer(addr)/4;
-      #250 inst_word = memoryword_addr;
-    end
-endmodule // instruction_memory
-
-
-module data_memory(address, write_data, read_enable, write_enable,
-                   write_clk, read_data);
-  input  31:0 address;
-  input  31:0 write_data;
-  input         read_enable;
-  input         write_enable;
-  input         write_clk;
-  output 31:0 read_data;
-  wire   31:0 read_data;
-
-  integer word_addr;
-  integer write_addr;
-  reg 31:0 memory 0:1000;
-  reg 31:0 data_word;
-
-  assign read_data = data_word;
-
-  function 31:0 to_integer;
-    input 31:0 argument;
-    to_integer = argument;
-  endfunction // to_integer
-
-  initial
-    begin
-      memory0 = 32'b00010001000100010001000100010001; // h0
-      memory1 = 32'b00100010001000100010001000100010; // h4
-      memory2 = 32'b00110011001100110011001100110011; // h8
-    end // rest is XXXXXXXXXX
-
-  always @(address or posedge read_enable)
-    begin  // behavior
-      word_addr = to_integer(address)/4;
-      if(read_enable==1)
-        #250 data_word <= memoryword_addr;
-    end
-
-  always @(negedge read_enable)
-         #200 data_word = 32'b00000000000000000000000000000000;
-
-  always @(posedge write_clk)
-    begin
-      if(write_enable==1)
-        begin
-          write_addr = to_integer(address)/4;
-          memorywrite_addr = write_data;
-        end
-    end
-endmodule // data_memory
-
-
-module registers(read_reg_1, read_reg_2, write_reg,
-                 write_data, write_enable, write_clk,
-                 read_data_1, read_data_2);
-  input   4:0 read_reg_1;    // 5 bit register address to read data 1
-  input   4:0 read_reg_2;    // 5 bit register address to read data 2
-  input   4:0 write_reg;     // 5 bit register address to write
-  input  31:0 write_data;    // 32 bit word to write into register
-  input         write_enable;  // rising clock and enable
-  input         write_clk;     // required to write
-  output 31:0 read_data_1;   // register content of read_reg_1
-  output 31:0 read_data_2;   // register content of read_reg_2
-  wire   31:0 read_data_1;
-  wire   31:0 read_data_2;
-
-  integer reg_addr_1;
-  integer reg_addr_2;
-  integer write_addr;
-  integer i;
-  reg 31:0 memory 0:31;
-  reg 31:0 reg_word_1;
-  reg 31:0 reg_word_2;
-
-  assign read_data_1 = reg_word_1;
-  assign read_data_2 = reg_word_2;
-
-  function 5:0 to_integer;
-    input 5:0 argument;
-    to_integer = argument;
-  endfunction // to_integer
-
-  initial
-    begin
-      for(i=0; i<32; i=i+1) memoryi = 32'h00000000;
-      reg_word_1 = 32'h00000000;
-      reg_word_2 = 32'h00000000;
-    end
-
-  always @(read_reg_1)
-    begin
-      reg_addr_1 = to_integer(read_reg_1);
-      #50 reg_word_1 <= memoryreg_addr_1;
-    end
-
-  always @(read_reg_2)
-    begin
-      reg_addr_2 = to_integer(read_reg_2);
-      #50 reg_word_2 <= memoryreg_addr_2;
-    end
-
-  always @(posedge write_clk)
-    begin  // behavior
-      write_addr = to_integer(write_reg);
-      if(write_enable==1)
-        begin
-          #100 memorywrite_addr = write_data;
-          if(write_reg==read_reg_1) reg_word_1 = write_data;
-          if(write_reg==read_reg_2) reg_word_2 = write_data;
-        end
-    end
-endmodule // registers
-
-
-module mux_32(in0, in1, ctl, result);
-  parameter n=31;
-  input  n:0 in0;     // 0 input
-  input  n:0 in1;     // 1 input
-  input        ctl;     // control
-  output n:0 result;  // output
-  assign result = (ctl==0) ? in0 : in1;
-endmodule // mux_32
-
-
-module mux_5(in0, in1, ctl, result);
-  parameter n=4;
-  input  n:0 in0;     // 0 input
-  input  n:0 in1;     // 1 input
-  input        ctl;     // control
-  output n:0 result;  // output
-  assign result = (ctl==0) ? in0 : in1;
-endmodule // mux_5
-
-module alu_32(inA, inB, inst, result);
-  input  31:0 inA;
-  input  31:0 inB;
-  input  31:0 inst;
-  output 31:0 result;
-  wire   31:0 result;
-  reg           cin; //=0
-  wire          cout;
-
-  initial cin=0;
-
-  add32 adder(inA, inB, cin, result, cout);
-
-endmodule // alu_32
-
- 
-module pipe2;  // test bench
-  // signals used in test bench (the interconnections)
-  
-  reg 31:0 zero_32; // = 32'h00000000;   // 32 bit zero
-  reg        zero;    // = 0;              // one bit zero
-  reg 31:0 four_32; // = 32'h00000004;   // four
-
-  reg        clear;   // = 1;    // one shot clear
-  reg        clk;     // = 0;    // master clock
-  wire       clk_bar;            // split phase for mem write
-  integer    counter; // = 0;    // master clock counter, raising edge
-  wire       nc1;                // a No-Connection for unused output
-
-  wire 31:0 PC_next;        // next value of PC 
-  wire 31:0 PC;             // Program Counter
-  wire 31:0 inst;              // instruction fetched
-
-
-  wire 31:0 ID_IR;             // ID Instruction Register
-  wire 31:0 ID_read_data_1;    // ID Register read data 1
-  wire 31:0 ID_read_data_2;    // ID Register read data 2
-  wire 31:0 ID_sign_ext;       // ID sign extension
-  wire  4:0 ID_rd;             // ID register destination
-  wire 15:0 ID_addr;           // ID_IR15:0 address
-  wire        RegDst; //=0       // ID selects destination register
-  wire        S;                 // ID for sign extend
-
-  wire 31:0 EX_IR;             // EX Instruction Register
-  wire 31:0 EX_A;              // EX data A
-  wire 31:0 EX_B;              // EX data B
-  wire 31:0 EX_C;              // EX data C
-  wire  4:0 EX_rd;             // EX register destination
-  wire 31:0 EX_aluB;           // EX into ALU B
-  wire        ALUSrc; //=1       // EX ALU B side source control
-  wire 31:0 EX_result;         // EX ALU output
-
-
-  wire 31:0 MEM_IR;            // MEM Instruction Register
-  wire 31:0 MEM_addr;          // MEM address
-  wire 31:0 MEM_data;          // MEM write data
-  wire 31:0 MEM_read_data;     // MEM read data
-  wire  4:0 MEM_rd;            // MEM register destination
-  wire        MEMRead;           // MEM enable read
-  wire        MEMWrite; //=0;    // MEM enable write
-
-  wire 31:0 WB_IR;             // WB Instruction Register
-  wire 31:0 WB_read;           // WB read data
-  wire 31:0 WB_pass;           // WB pass data
-  wire  4:0 WB_rd;             // WB register destination
-  wire        MemtoReg;          // WB mux control
-  wire 31:0 WB_result;         // WB mux output
-  wire        WB_write_enb; //=1 // WB enable register write
-
-  function 31:0 to_integer;
-    input 31:0 argument;
-    to_integer = argument;
-  endfunction // to_integer
-  
-  initial
-    begin
-      zero_32 = 32'h00000000;    // 32 bit zero
-      zero    = 0;               // one bit zero
-      four_32 = 32'h00000004;    // four
-      clear   = 1;               // one shot clear
-      clk     = 0;               // master clock
-      counter = 0;               // master clock counter, raising edge
-      #200 clear = 0;            // clear time finished
-      forever #5000 clk = ~clk;  // run clock 10ns period
-    end
-
-  initial #140000 $finish;       // stop after 140 ns
-
-  assign ALUSrc = 1;             // change to correct expression
-  assign RegDst = 0;             // change to correct expression
-  assign MEMWrite = 0;           // change to correct expression
-  assign WB_write_enb = 1;       // change to correct expression
-
-  // schematic of pipe2, behavior and test bench
-  assign  clk_bar = ~clk;        // for split phase registers
-
-  // IF, Instruction Fetch pipeline stage
-  register_32 PC_reg(clk, clear, PC_next, PC);
-  add32 PC_incr(PC, four_32, zero, PC_next, nc1);
-  instruction_memory inst_mem(PC, inst);
-
-  // ID, Instruction Decode and register stack pipeline stage
-  register_32 ID_IR_reg(clk, clear, inst, ID_IR);
-  registers ID_regs(.read_reg_1(ID_IR25:21),
-                    .read_reg_2(ID_IR20:16),
-                    .write_reg(WB_rd),
-                    .write_data(WB_result),
-                    .write_enable(WB_write_enb),
-                    .write_clk(clk_bar),
-                    .read_data_1(ID_read_data_1),
-                    .read_data_2(ID_read_data_2));
-  mux_5 ID_mux_rd(.in0(ID_IR20:16),
-                  .in1(ID_IR15:11),
-                  .ctl(RegDst),
-                  .result(ID_rd));
-             assign ID_sign_ext15:0 = ID_IR15:0;  // just wiring
-             assign ID_sign_ext31:16 =
-                    {S,S,S,S,S,S,S,S,S,S,S,S,S,S,S,S};
-             assign S = ID_IR15;
-  // EX, Execute pipeline stage
-  register_32 EX_IR_reg(clk, clear, ID_IR, EX_IR);
-  register_32 EX_A_reg(clk, clear, ID_read_data_1, EX_A);
-  register_32 EX_B_reg(clk, clear, ID_read_data_2, EX_B);
-  register_32 EX_C_reg(clk, clear, ID_sign_ext, EX_C);
-  register_5  EX_rd_reg(clk, clear, ID_rd, EX_rd);
-  mux_32 EX_mux1(.in0(EX_B), .in1(EX_C), .ctl(ALUSrc), .result(EX_aluB));
-  alu_32 ALU(.inA(EX_A),
-             .inB(EX_aluB),
-             .inst(EX_IR),
-             .result(EX_result));
-
-  // MEM Data Memory pipeline stage
-  register_32 MEM_IR_reg(clk, clear, EX_IR, MEM_IR);
-  register_32 MEM_addr_reg(clk, clear, EX_result, MEM_addr);
-  register_32 MEM_data_reg(clk, clear, EX_B, MEM_data);
-  register_5  MEM_rd_reg(clk, clear, EX_rd, MEM_rd);
-              assign MEMRead = (MEM_IR31:26 == 6'b100011 );
-  data_memory data_mem(.address(MEM_addr),
-                       .write_data(MEM_data),
-                       .read_enable(MEMRead),
-                       .write_enable(MEMWrite),
-                       .write_clk(clk_bar),
-                       .read_data(MEM_read_data));
-
-  // WB, Write Back pipeline stage
-  register_32 WB_IR_reg(clk, clear, MEM_IR, WB_IR);
-  register_32 WB_read_reg(clk, clear, MEM_read_data, WB_read);
-  register_32 WB_pass_reg(clk, clear, MEM_addr, WB_pass);
-  register_5  WB_rd_reg(clk, clear, MEM_rd, WB_rd);
-              assign MemtoReg = (WB_IR31:26 == 6'b100011 );
-  mux_32 WB_mux(.in0(WB_pass),
-                .in1(WB_read),
-                .ctl(MemtoReg),
-                .result(WB_result));
-
-             
-
-
-             
-
-  always @(posedge clk) // to show state of registers in pipeline
-    begin
-      $write("clock %0d", counter);
-      $write("  inst=%h", inst);
-      $write("  PC   =%h", PC);
-      $write(" PCnext=%h", PC_next);
-      $write("\n");
-      $write("ID  stage  IR=%h", ID_IR);
-      if((WB_write_enb==1)&&(WB_rd!=5'b00000))
-        begin
-          $write("  write=%h", WB_result);
-          $write("  into =000000%h", {3'b000,WB_rd});
-          $write("               ");
-        end
-      else
-        $write("                                               ");
-
-      $write("  rd=%b", ID_rd);
-      $write("\n");
-      $write("EX  stage  IR=%h", EX_IR);
-      $write("  EX_A =%h", EX_A);
-      $write("  EX_B =%h", EX_B);
-      $write("  EX_C =%h", EX_C);
-      $write(" rd=%b", EX_rd);
-      $write("\n");
-      $write("EX  stage             ");
-      $write("EX_aluB=%h", EX_aluB);
-      $write(" EX_res=%h", EX_result);
-      $write("\n");
-      $write("MEM stage  IR=%h", MEM_IR);
-      $write("  addr =%h", MEM_addr);
-      $write("  data =%h", MEM_data);
-      if(MEMRead==1)
-        $write("  read =%h", MEM_read_data);
-      else if(MEMWrite==1)
-        $write("  wrote=%h", MEM_data);
-      else
-        $write("                ");
-
-      $write(" rd=%b", MEM_rd);
-      $write("\n");
-      $write("WB  stage  IR=%h", WB_IR);
-      $write("  read =%h", WB_read);
-      $write("  pass =%h", WB_pass);
-      $write(" result=%h", WB_result);
-      $write(" rd=%b", WB_rd);
-      $write("\n");
-      $write("control RegDst=%b", RegDst);
-      $write("  ALUSrc=%b", ALUSrc);
-      $write("  MemtoReg=%b", MemtoReg);
-      $write("  MEMRead=%b", MEMRead);
-      $write("  MEMWrite=%b", MEMWrite);
-      $write("  WB_write_enb=%b", WB_write_enb);
-      $write("\n");
-      $write("\n");         // blank line
-      counter = counter+1;
-    end
-endmodule // pipe2
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-            '$write', '(', '"WB  stage  IR=%h"', 'WB_IR', ')', ';',
-            '$write', '(', '"  read =%h"', 'WB_read', ')', ';',
-            '$write', '(', '"  pass =%h"', 'WB_pass', ')', ';',
-            '$write', '(', '" result=%h"', 'WB_result', ')', ';',
-            '$write', '(', '" rd=%b"', 'WB_rd', ')', ';',
-            '$write', '(', '"\\n"', ')', ';',
-            '$write', '(', '"control RegDst=%b"', 'RegDst', ')', ';',
-            '$write', '(', '"  ALUSrc=%b"', 'ALUSrc', ')', ';',
-            '$write', '(', '"  MemtoReg=%b"', 'MemtoReg', ')', ';',
-            '$write', '(', '"  MEMRead=%b"', 'MEMRead', ')', ';',
-            '$write', '(', '"  MEMWrite=%b"', 'MEMWrite', ')', ';',
-            '$write', '(', '"  WB_write_enb=%b"', 'WB_write_enb', ')', ';',
-            '$write', '(', '"\\n"', ')', ';',
-            '$write', '(', '"\\n"', ')', ';',
-            'counter', '=', 'counter', '+', '1', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/pl.v.parsed.txt Deleted

@@ -1,833 +0,0 @@
-/////////////////////////////////////////////////////////////////////
-////                                                             ////
-////  Protocol Layer                                             ////
-////  This block is typically referred to as the SEI in USB      ////
-////  Specification. It encapsulates the Packet Assembler,       ////
-////  disassembler, protocol engine and internal DMA             ////
-////                                                             ////
-////  Author: Rudolf Usselmann                                   ////
-////          rudi@asics.ws                                      ////
-////                                                             ////
-////                                                             ////
-////  Downloaded from: http://www.opencores.org/cores/usb/       ////
-////                                                             ////
-/////////////////////////////////////////////////////////////////////
-////                                                             ////
-//// Copyright (C) 2000 Rudolf Usselmann                         ////
-////                    rudi@asics.ws                            ////
-////                                                             ////
-//// This source file may be used and distributed without        ////
-//// restriction provided that this copyright statement is not   ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer.////
-////                                                             ////
-////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
-//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
-//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
-//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
-//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
-//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
-//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
-//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
-//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
-//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
-//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
-//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
-//// POSSIBILITY OF SUCH DAMAGE.                                 ////
-////                                                             ////
-/////////////////////////////////////////////////////////////////////
-
-//  CVS Log
-//
-//  $Id: pl.v,v 1.0 2001/03/07 09:17:12 rudi Exp $
-//
-//  $Date: 2001/03/07 09:17:12 $
-//  $Revision: 1.0 $
-//  $Author: rudi $
-//  $Locker:  $
-//  $State: Exp $
-//
-// Change History:
-//               $Log: pl.v,v $
-//               Revision 1.0  2001/03/07 09:17:12  rudi
-//
-//
-//               Changed all revisions to revision 1.0. This is because OpenCores CVS
-//               interface could not handle the original '0.1' revision ....
-//
-//               Revision 0.1.0.1  2001/02/28 08:11:11  rudi
-//               Initial Release
-//
-//
-
-`include "usb_defines.v"
-
-module pl(  clk, rst,
-
-        // UTMI Interface
-        rx_data, rx_valid, rx_active, rx_err,
-        tx_data, tx_valid, tx_valid_last, tx_ready,
-        tx_first, tx_valid_out,
-        mode_hs, usb_reset, usb_suspend, usb_attached,
-
-        // memory interface
-        madr, mdout, mdin, mwe, mreq, mack,
-
-        // Register File Interface
-        fa, idin,
-        ep_sel, match,
-        dma_in_buf_sz1, dma_out_buf_avail,
-        buf0_rl, buf0_set, buf1_set,
-        uc_bsel_set, uc_dpd_set,
-
-        int_buf1_set, int_buf0_set, int_upid_set,
-        int_crc16_set, int_to_set, int_seqerr_set,
-
-        csr, buf0, buf1,
-
-        // Misc
-        frm_nat,
-        pid_cs_err, nse_err,
-        crc5_err
-
-        );
-
-// UTMI Interface
-input       clk, rst;
-input   7:0   rx_data;
-input       rx_valid, rx_active, rx_err;
-output  7:0   tx_data;
-output      tx_valid;
-output      tx_valid_last;
-input       tx_ready;
-output      tx_first;
-input       tx_valid_out;
-input       mode_hs;    // High Speed Mode
-input       usb_reset;  // USB Reset
-input       usb_suspend;    // USB Suspend
-input       usb_attached;   // Attached to USB
-
-
-// Memory Arbiter Interface
-output  14:0  madr;       // word address
-output  31:0  mdout;
-input   31:0  mdin;
-output      mwe;
-output      mreq;
-input       mack;
-
-
-// Register File interface
-input   6:0   fa;     // Function Address (as set by the controller)
-output  31:0  idin;       // Data Input
-output  3:0   ep_sel;     // Endpoint Number Input
-input       match;      // Endpoint Matched
-input       dma_in_buf_sz1;
-input       dma_out_buf_avail;
-output      nse_err;    // no such endpoint error
-
-output      buf0_rl;    // Reload Buf 0 with original values
-output      buf0_set;   // Write to buf 0
-output      buf1_set;   // Write to buf 1
-output      uc_bsel_set;    // Write to the uc_bsel field
-output      uc_dpd_set; // Write to the uc_dpd field
-output      int_buf1_set;   // Set buf1 full/empty interrupt
-output      int_buf0_set;   // Set buf0 full/empty interrupt
-output      int_upid_set;   // Set unsupported PID interrupt
-output      int_crc16_set;  // Set CRC16 error interrupt
-output      int_to_set; // Set time out interrupt
-output      int_seqerr_set; // Set PID sequence error interrupt
-
-input   31:0  csr;        // Internal CSR Output
-input   31:0  buf0;       // Internal Buf 0 Output
-input   31:0  buf1;       // Internal Buf 1 Output
-
-// Misc
-output      pid_cs_err; // pid checksum error
-output      crc5_err;   // crc5 error
-output  31:0  frm_nat;
-
-
-///////////////////////////////////////////////////////////////////
-//
-// Local Wires and Registers
-//
-
-// Packet Disassembler Interface
-wire        clk, rst;
-wire    7:0   rx_data;
-wire        rx_valid, rx_active, rx_err;
-wire        pid_OUT, pid_IN, pid_SOF, pid_SETUP;
-wire        pid_DATA0, pid_DATA1, pid_DATA2, pid_MDATA;
-wire        pid_ACK, pid_NACK, pid_STALL, pid_NYET;
-wire        pid_PRE, pid_ERR, pid_SPLIT, pid_PING;
-wire    6:0   token_fadr;
-wire        token_valid;
-wire        crc5_err;
-wire    11:0  frame_no;
-wire    7:0   rx_data_st;
-wire        rx_data_valid;
-wire        rx_data_done;
-wire        crc16_err;
-wire        rx_seq_err;
-
-// Packet Assembler Interface
-wire        send_token;
-wire    1:0   token_pid_sel;
-wire        send_data;
-wire    1:0   data_pid_sel;
-wire    7:0   tx_data_st;
-wire        rd_next;
-
-// IDMA Interface
-wire        rx_dma_en;  // Allows the data to be stored
-wire        tx_dma_en;  // Allows for data to be retrieved
-wire        abort;      // Abort Transfer (time_out, crc_err or rx_error)
-wire        idma_done;  // DMA is done
-wire    16:0  adr;        // Byte Address
-wire    13:0  size;       // Size in bytes
-wire    10:0  sizu_c;     // Up and Down counting size registers, used
-                // to update
-wire    13:0  buf_size;   // Actual buffer size
-wire        dma_en;     // external dma enabled
-
-// Memory Arbiter Interface
-wire    14:0  madr;       // word address
-wire    31:0  mdout;
-wire    31:0  mdin;
-wire        mwe;
-wire        mreq;
-wire        mack;
-
-// Local signals
-wire        pid_bad, pid_bad1, pid_bad2;
-
-reg     hms_clk;    // 0.5 Micro Second Clock
-reg 4:0   hms_cnt;
-
-reg 11:0  frame_no_r; // Current Frame Number register
-wire        frame_no_we;
-reg     frame_no_same;  // Indicates current and prev. frame numbers
-                // are equal
-reg 3:0   mfm_cnt;    // Micro Frame Counter
-reg 11:0  sof_time;   // Time since last sof
-reg     clr_sof_time;
-
-wire        fsel;       // This Function is selected
-
-wire        match_o;
-
-///////////////////////////////////////////////////////////////////
-//
-// Misc Logic
-//
-
-
-// PIDs we should never receive
-assign pid_bad1 = pid_ACK | pid_NACK | pid_STALL | pid_NYET | pid_PRE |
-            pid_ERR | pid_SPLIT;
-
-// PIDs we should never get in full speed mode (high speed mode only)
-assign pid_bad2 = !mode_hs & pid_PING;
-
-// All bad pids
-assign pid_bad = pid_bad1 | pid_bad2;
-
-assign match_o = !pid_bad & match & token_valid & !crc5_err;
-
-// Frame Number (from SOF token)
-reg frame_no_we_r;
-
-assign frame_no_we = token_valid & !crc5_err & pid_SOF;
-
-always @(posedge clk)
-    frame_no_we_r <= #1 frame_no_we;
-
-always @(posedge clk)
-    if(!rst)    frame_no_r <= #1 0;
-    else
-    if(frame_no_we) frame_no_r <= #1 frame_no;
-
-// Micro Frame Counter
-always @(posedge clk)
-    frame_no_same <= #1 frame_no_we & (frame_no_r == frame_no);
-
-always @(posedge clk)
-    if(!rst)        mfm_cnt <= #1 0;
-    else
-    if(frame_no_we & !frame_no_same)
-                mfm_cnt <= #1 0;
-    else
-    if(frame_no_same)   mfm_cnt <= #1 mfm_cnt + 1;
-
-//SOF delay counter
-always @(posedge clk)
-    clr_sof_time <= #1 frame_no_we;
-
-always @(posedge clk)
-    if(clr_sof_time)    sof_time <= #1 0;
-    else
-    if(hms_clk)     sof_time <= #1 sof_time + 1;
-
-assign frm_nat = {mfm_cnt, frame_no_r, 4'h0, sof_time};
-
-
-// 0.5 Micro Seconds Clock Generator
-always @(posedge clk)
-    if(!rst | hms_clk | frame_no_we)    hms_cnt <= #1 0;
-    else                    hms_cnt <= #1 hms_cnt + 1;
-
-//always @(posedge clk)
-//    hms_clk <= #1 (hms_cnt == `HMS_DEL);
-
-///////////////////////////////////////////////////////////////////
-
-// This function is addressed
-assign fsel = (token_fadr == fa);
-
-///////////////////////////////////////////////////////////////////
-//
-// Module Instantiations
-//
-
-//Packet Decoder
-pd  u0( .clk(       clk     ),
-        .rst(       rst     ),
-        .rx_data(   rx_data     ),
-        .rx_valid(  rx_valid    ),
-        .rx_active( rx_active   ),
-        .rx_err(    rx_err      ),
-        .pid_OUT(   pid_OUT     ),
-        .pid_IN(    pid_IN      ),
-        .pid_SOF(   pid_SOF     ),
-        .pid_SETUP( pid_SETUP   ),
-        .pid_DATA0( pid_DATA0   ),
-        .pid_DATA1( pid_DATA1   ),
-        .pid_DATA2( pid_DATA2   ),
-        .pid_MDATA( pid_MDATA   ),
-        .pid_ACK(   pid_ACK     ),
-        .pid_NACK(  pid_NACK    ),
-        .pid_STALL( pid_STALL   ),
-        .pid_NYET(  pid_NYET    ),
-        .pid_PRE(   pid_PRE     ),
-        .pid_ERR(   pid_ERR     ),
-        .pid_SPLIT( pid_SPLIT   ),
-        .pid_PING(  pid_PING    ),
-        .pid_cks_err(   pid_cs_err  ),
-        .token_fadr(    token_fadr  ),
-        .token_endp(    ep_sel      ),
-        .token_valid(   token_valid ),
-        .crc5_err(  crc5_err    ),
-        .frame_no(  frame_no    ),
-        .rx_data_st(    rx_data_st  ),
-        .rx_data_valid( rx_data_valid   ),
-        .rx_data_done(  rx_data_done    ),
-        .crc16_err( crc16_err   ),
-        .seq_err(   rx_seq_err  )
-        );
-
-// Packet Assembler
-pa  u1( .clk(       clk     ),
-        .rst(       rst     ),
-        .tx_data(   tx_data     ),
-        .tx_valid(  tx_valid    ),
-        .tx_valid_last( tx_valid_last   ),
-        .tx_ready(  tx_ready    ),
-        .tx_first(  tx_first    ),
-        .send_token(    send_token  ),
-        .token_pid_sel( token_pid_sel   ),
-        .send_data( send_data   ),
-        .data_pid_sel(  data_pid_sel    ),
-        .tx_data_st(    tx_data_st  ),
-        .rd_next(   rd_next     )
-        );
-
-// Internal DMA / Memory Arbiter Interface
-idma    u2( .clk(       clk     ),
-        .rst(       rst     ),
-        .rx_data_st(    rx_data_st  ),
-        .rx_data_valid( rx_data_valid   ),
-        .rx_data_done(  rx_data_done    ),
-        .send_data( send_data   ),
-        .tx_data_st(    tx_data_st  ),
-        .rd_next(   rd_next     ),
-        .rx_dma_en( rx_dma_en   ),
-        .tx_dma_en( tx_dma_en   ),
-        .abort(     abort       ),
-        .idma_done( idma_done   ),
-        .adr(       adr     ),
-        .size(      size        ),
-        .buf_size(  buf_size    ),
-        .dma_en(    dma_en      ),
-        .madr(      madr        ),
-        .sizu_c(    sizu_c      ),
-        .mdout(     mdout       ),
-        .mdin(      mdin        ),
-        .mwe(       mwe     ),
-        .mreq(      mreq        ),
-        .mack(      mack        )
-        );
-
-// Protocol Engine
-pe  u3( .clk(           clk         ),
-        .rst(           rst         ),
-        .tx_valid(      tx_valid_out        ),
-        .rx_active(     rx_active       ),
-        .pid_OUT(       pid_OUT         ),
-        .pid_IN(        pid_IN          ),
-        .pid_SOF(       pid_SOF         ),
-        .pid_SETUP(     pid_SETUP       ),
-        .pid_DATA0(     pid_DATA0       ),
-        .pid_DATA1(     pid_DATA1       ),
-        .pid_DATA2(     pid_DATA2       ),
-        .pid_MDATA(     pid_MDATA       ),
-        .pid_ACK(       pid_ACK         ),
-        .pid_NACK(      pid_NACK        ),
-        .pid_STALL(     pid_STALL       ),
-        .pid_NYET(      pid_NYET        ),
-        .pid_PRE(       pid_PRE         ),
-        .pid_ERR(       pid_ERR         ),
-        .pid_SPLIT(     pid_SPLIT       ),
-        .pid_PING(      pid_PING        ),
-        .mode_hs(       mode_hs         ),
-        .token_valid(       token_valid     ),
-        .crc5_err(      crc5_err        ),
-        .rx_data_valid(     rx_data_valid       ),
-        .rx_data_done(      rx_data_done        ),
-        .crc16_err(     crc16_err       ),
-        .send_token(        send_token      ),
-        .token_pid_sel(     token_pid_sel       ),
-        .data_pid_sel(      data_pid_sel        ),
-        .rx_dma_en(     rx_dma_en       ),
-        .tx_dma_en(     tx_dma_en       ),
-        .abort(         abort           ),
-        .idma_done(     idma_done       ),
-        .adr(           adr         ),
-        .size(          size            ),
-        .buf_size(      buf_size        ),
-        .sizu_c(        sizu_c          ),
-        .dma_en(        dma_en          ),
-        .fsel(          fsel            ),
-        .idin(          idin            ),
-        .ep_sel(        ep_sel          ),
-        .match(         match_o         ),
-        .dma_in_buf_sz1(    dma_in_buf_sz1      ),
-        .dma_out_buf_avail( dma_out_buf_avail   ),
-        .nse_err(       nse_err         ),
-        .buf0_rl(       buf0_rl         ),
-        .buf0_set(      buf0_set        ),
-        .buf1_set(      buf1_set        ),
-        .uc_bsel_set(       uc_bsel_set     ),
-        .uc_dpd_set(        uc_dpd_set      ),
-        .int_buf1_set(      int_buf1_set        ),
-        .int_buf0_set(      int_buf0_set        ),
-        .int_upid_set(      int_upid_set        ),
-        .int_crc16_set(     int_crc16_set       ),
-        .int_to_set(        int_to_set      ),
-        .int_seqerr_set(    int_seqerr_set      ),
-        .csr(           csr         ),
-        .buf0(          buf0            ),
-        .buf1(          buf1            )
-        );
-
-endmodule
-
-
-
-   'module',
-      'pl',
-      '(',
-       'clk',
-        'rst',
-        'rx_data',
-        'rx_valid',
-        'rx_active',
-        'rx_err',
-        'tx_data',
-        'tx_valid',
-        'tx_valid_last',
-        'tx_ready',
-        'tx_first',
-        'tx_valid_out',
-        'mode_hs',
-        'usb_reset',
-        'usb_suspend',
-        'usb_attached',
-        'madr',
-        'mdout',
-        'mdin',
-        'mwe',
-        'mreq',
-        'mack',
-        'fa',
-        'idin',
-        'ep_sel',
-        'match',
-        'dma_in_buf_sz1',
-        'dma_out_buf_avail',
-        'buf0_rl',
-        'buf0_set',
-        'buf1_set',
-        'uc_bsel_set',
-        'uc_dpd_set',
-        'int_buf1_set',
-        'int_buf0_set',
-        'int_upid_set',
-        'int_crc16_set',
-        'int_to_set',
-        'int_seqerr_set',
-        'csr',
-        'buf0',
-        'buf1',
-        'frm_nat',
-        'pid_cs_err',
-        'nse_err',
-        'crc5_err',
-      ')',
-      ';',
-     'input', 'clk', 'rst', ';',
-      'input', '', '7', ':', '0', '', 'rx_data', ';',
-      'input', 'rx_valid', 'rx_active', 'rx_err', ';',
-      'output', '', '7', ':', '0', '', 'tx_data', ';',
-      'output', 'tx_valid', ';',
-      'output', 'tx_valid_last', ';',
-      'input', 'tx_ready', ';',
-      'output', 'tx_first', ';',
-      'input', 'tx_valid_out', ';',
-      'input', 'mode_hs', ';',
-      'input', 'usb_reset', ';',
-      'input', 'usb_suspend', ';',
-      'input', 'usb_attached', ';',
-      'output', '', '14', ':', '0', '', 'madr', ';',
-      'output', '', '31', ':', '0', '', 'mdout', ';',
-      'input', '', '31', ':', '0', '', 'mdin', ';',
-      'output', 'mwe', ';',
-      'output', 'mreq', ';',
-      'input', 'mack', ';',
-      'input', '', '6', ':', '0', '', 'fa', ';',
-      'output', '', '31', ':', '0', '', 'idin', ';',
-      'output', '', '3', ':', '0', '', 'ep_sel', ';',
-      'input', 'match', ';',
-      'input', 'dma_in_buf_sz1', ';',
-      'input', 'dma_out_buf_avail', ';',
-      'output', 'nse_err', ';',
-      'output', 'buf0_rl', ';',
-      'output', 'buf0_set', ';',
-      'output', 'buf1_set', ';',
-      'output', 'uc_bsel_set', ';',
-      'output', 'uc_dpd_set', ';',
-      'output', 'int_buf1_set', ';',
-      'output', 'int_buf0_set', ';',
-      'output', 'int_upid_set', ';',
-      'output', 'int_crc16_set', ';',
-      'output', 'int_to_set', ';',
-      'output', 'int_seqerr_set', ';',
-      'input', '', '31', ':', '0', '', 'csr', ';',
-      'input', '', '31', ':', '0', '', 'buf0', ';',
-      'input', '', '31', ':', '0', '', 'buf1', ';',
-      'output', 'pid_cs_err', ';',
-      'output', 'crc5_err', ';',
-      'output', '', '31', ':', '0', '', 'frm_nat', ';',
-      'wire', 'clk', 'rst', ';',
-      'wire', '', '7', ':', '0', '', 'rx_data', ';',
-      'wire', 'rx_valid', 'rx_active', 'rx_err', ';',
-      'wire', 'pid_OUT', 'pid_IN', 'pid_SOF', 'pid_SETUP', ';',
-      'wire', 'pid_DATA0', 'pid_DATA1', 'pid_DATA2', 'pid_MDATA', ';',
-      'wire', 'pid_ACK', 'pid_NACK', 'pid_STALL', 'pid_NYET', ';',
-      'wire', 'pid_PRE', 'pid_ERR', 'pid_SPLIT', 'pid_PING', ';',
-      'wire', '', '6', ':', '0', '', 'token_fadr', ';',
-      'wire', 'token_valid', ';',
-      'wire', 'crc5_err', ';',
-      'wire', '', '11', ':', '0', '', 'frame_no', ';',
-      'wire', '', '7', ':', '0', '', 'rx_data_st', ';',
-      'wire', 'rx_data_valid', ';',
-      'wire', 'rx_data_done', ';',
-      'wire', 'crc16_err', ';',
-      'wire', 'rx_seq_err', ';',
-      'wire', 'send_token', ';',
-      'wire', '', '1', ':', '0', '', 'token_pid_sel', ';',
-      'wire', 'send_data', ';',
-      'wire', '', '1', ':', '0', '', 'data_pid_sel', ';',
-      'wire', '', '7', ':', '0', '', 'tx_data_st', ';',
-      'wire', 'rd_next', ';',
-      'wire', 'rx_dma_en', ';',
-      'wire', 'tx_dma_en', ';',
-      'wire', 'abort', ';',
-      'wire', 'idma_done', ';',
-      'wire', '', '16', ':', '0', '', 'adr', ';',
-      'wire', '', '13', ':', '0', '', 'size', ';',
-      'wire', '', '10', ':', '0', '', 'sizu_c', ';',
-      'wire', '', '13', ':', '0', '', 'buf_size', ';',
-      'wire', 'dma_en', ';',
-      'wire', '', '14', ':', '0', '', 'madr', ';',
-      'wire', '', '31', ':', '0', '', 'mdout', ';',
-      'wire', '', '31', ':', '0', '', 'mdin', ';',
-      'wire', 'mwe', ';',
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-        ';',
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-            '.', 'rx_active', '(', 'rx_active', ')',
-            '.', 'rx_err', '(', 'rx_err', ')',
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-            '.', 'pid_IN', '(', 'pid_IN', ')',
-            '.', 'pid_SOF', '(', 'pid_SOF', ')',
-            '.', 'pid_SETUP', '(', 'pid_SETUP', ')',
-            '.', 'pid_DATA0', '(', 'pid_DATA0', ')',
-            '.', 'pid_DATA1', '(', 'pid_DATA1', ')',
-            '.', 'pid_DATA2', '(', 'pid_DATA2', ')',
-            '.', 'pid_MDATA', '(', 'pid_MDATA', ')',
-            '.', 'pid_ACK', '(', 'pid_ACK', ')',
-            '.', 'pid_NACK', '(', 'pid_NACK', ')',
-            '.', 'pid_STALL', '(', 'pid_STALL', ')',
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-            '.', 'pid_SPLIT', '(', 'pid_SPLIT', ')',
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-            '.', 'pid_cks_err', '(', 'pid_cs_err', ')',
-            '.', 'token_fadr', '(', 'token_fadr', ')',
-            '.', 'token_endp', '(', 'ep_sel', ')',
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-            '.', 'crc5_err', '(', 'crc5_err', ')',
-            '.', 'frame_no', '(', 'frame_no', ')',
-            '.', 'rx_data_st', '(', 'rx_data_st', ')',
-            '.', 'rx_data_valid', '(', 'rx_data_valid', ')',
-            '.', 'rx_data_done', '(', 'rx_data_done', ')',
-            '.', 'crc16_err', '(', 'crc16_err', ')',
-            '.', 'seq_err', '(', 'rx_seq_err', ')',
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-            '.', 'tx_valid_last', '(', 'tx_valid_last', ')',
-            '.', 'tx_ready', '(', 'tx_ready', ')',
-            '.', 'tx_first', '(', 'tx_first', ')',
-            '.', 'send_token', '(', 'send_token', ')',
-            '.', 'token_pid_sel', '(', 'token_pid_sel', ')',
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-            '.', 'rx_dma_en', '(', 'rx_dma_en', ')',
-            '.', 'tx_dma_en', '(', 'tx_dma_en', ')',
-            '.', 'abort', '(', 'abort', ')',
-            '.', 'idma_done', '(', 'idma_done', ')',
-            '.', 'adr', '(', 'adr', ')',
-            '.', 'size', '(', 'size', ')',
-            '.', 'buf_size', '(', 'buf_size', ')',
-            '.', 'dma_en', '(', 'dma_en', ')',
-            '.', 'madr', '(', 'madr', ')',
-            '.', 'sizu_c', '(', 'sizu_c', ')',
-            '.', 'mdout', '(', 'mdout', ')',
-            '.', 'mdin', '(', 'mdin', ')',
-            '.', 'mwe', '(', 'mwe', ')',
-            '.', 'mreq', '(', 'mreq', ')',
-            '.', 'mack', '(', 'mack', ')',
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-            '.', 'pid_SETUP', '(', 'pid_SETUP', ')',
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-            '.', 'pid_DATA2', '(', 'pid_DATA2', ')',
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-            '.', 'pid_SPLIT', '(', 'pid_SPLIT', ')',
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-            '.', 'token_valid', '(', 'token_valid', ')',
-            '.', 'crc5_err', '(', 'crc5_err', ')',
-            '.', 'rx_data_valid', '(', 'rx_data_valid', ')',
-            '.', 'rx_data_done', '(', 'rx_data_done', ')',
-            '.', 'crc16_err', '(', 'crc16_err', ')',
-            '.', 'send_token', '(', 'send_token', ')',
-            '.', 'token_pid_sel', '(', 'token_pid_sel', ')',
-            '.', 'data_pid_sel', '(', 'data_pid_sel', ')',
-            '.', 'rx_dma_en', '(', 'rx_dma_en', ')',
-            '.', 'tx_dma_en', '(', 'tx_dma_en', ')',
-            '.', 'abort', '(', 'abort', ')',
-            '.', 'idma_done', '(', 'idma_done', ')',
-            '.', 'adr', '(', 'adr', ')',
-            '.', 'size', '(', 'size', ')',
-            '.', 'buf_size', '(', 'buf_size', ')',
-            '.', 'sizu_c', '(', 'sizu_c', ')',
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-            '.', 'ep_sel', '(', 'ep_sel', ')',
-            '.', 'match', '(', 'match_o', ')',
-            '.', 'dma_in_buf_sz1', '(', 'dma_in_buf_sz1', ')',
-            '.', 'dma_out_buf_avail', '(', 'dma_out_buf_avail', ')',
-            '.', 'nse_err', '(', 'nse_err', ')',
-            '.', 'buf0_rl', '(', 'buf0_rl', ')',
-            '.', 'buf0_set', '(', 'buf0_set', ')',
-            '.', 'buf1_set', '(', 'buf1_set', ')',
-            '.', 'uc_bsel_set', '(', 'uc_bsel_set', ')',
-            '.', 'uc_dpd_set', '(', 'uc_dpd_set', ')',
-            '.', 'int_buf1_set', '(', 'int_buf1_set', ')',
-            '.', 'int_buf0_set', '(', 'int_buf0_set', ')',
-            '.', 'int_upid_set', '(', 'int_upid_set', ')',
-            '.', 'int_crc16_set', '(', 'int_crc16_set', ')',
-            '.', 'int_to_set', '(', 'int_to_set', ')',
-            '.', 'int_seqerr_set', '(', 'int_seqerr_set', ')',
-            '.', 'csr', '(', 'csr', ')',
-            '.', 'buf0', '(', 'buf0', ')',
-            '.', 'buf1', '(', 'buf1', ')',
-            ')',
-        ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/port_info_test.v.parsed.txt Deleted

@@ -1,73 +0,0 @@
-/**********************************************************************
- * $port_info example -- Verilog test bench source code
- *
- * Verilog test bench to test the $port_info PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-  reg  a, b, ci, clk;
-  wire sum, co;
-
-  addbit i1 (a, b, ci, sum, co);
-
-  initial
-    begin
-      #10 $port_info(i1);
-      #10 $finish;
-    end
-endmodule
-
-/*** A gate level 1 bit adder model ***/
-`timescale 1ns / 1ns
-module addbit (a, b, ci, sum, co, foo);
-  input  a, b, ci;
-  output sum, co;
-  output 3:0 foo;
-
-  wire  a, b, ci;
-  reg   sum, co;
-  wand  scalared 3:0 foo;
-
-  always @(a or b or ci)
-    {co,sum} = a + b + ci;
-
-endmodule
-/*********************************************************************/
-
-
-
-  'module', 'test', ';',
-     'reg', 'a', 'b', 'ci', 'clk', ';',
-      'wire', 'sum', 'co', ';',
-       'addbit',
-        'i1', '(', 'a', 'b', 'ci', 'sum', 'co', ')',
-        ';',
-       'initial',
-         'begin',
-           '#', '10', '$port_info', '(', 'i1', ')', ';',
-            '#', '10', '$finish', ';',
-          'end',
-    'endmodule',
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-      'addbit',
-      '(',
-      'a', 'b', 'ci', 'sum', 'co', 'foo',
-      ')',
-      ';',
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-      'output', 'sum', 'co', ';',
-      'output', '', '3', ':', '0', '', 'foo', ';',
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-      'reg', 'sum', 'co', ';',
-      'wand', 'scalared', '', '3', ':', '0', '', 'foo', ';',
-       'always',
-        '@', '(', 'a', 'b', 'ci', ')',
-         '{', 'co', 'sum', '}', '=', 'a', '+', 'b', '+', 'ci',
-          ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/pow_test.v.parsed.txt Deleted

@@ -1,73 +0,0 @@
-/**********************************************************************
- * $pow example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $pow PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-  reg  32:0 result;
-  reg         a, b;
-
-  buf i1 (c,a);
-  initial
-    begin
-      a = 1;
-      b = 0;
-      /* Test $pow with invalid arguments */
-      /* These invalid calls will need to be commented out to use */
-      /* the valid calls to $pow in simulation */
-//      #1 result = $pow;
-//      #1 result = $pow();
-//      #1 result = $pow(1);
-//      #1 result = $pow(2,i1);
-//      #1 result = $pow(1,2,3);
-
-      /* Test $pow with valid values */
-      #1 $display("$pow(2,3) returns %d", $pow(2,3));
-      #1 result = $pow(a,b);
-      #1 $display("$pow(a,b) returns %d (a=%d b=%d)", result, a, b);
-      #1 $stop;
-      $finish;
-    end
-
-endmodule
-/*********************************************************************/
-
-
-
-  'module', 'test', ';',
-     'reg', '', '32', ':', '0', '', 'result', ';',
-      'reg', 'a', 'b', ';',
-      'buf', 'i1', '(', 'c', 'a', ')', ';',
-       'initial',
-         'begin',
-           'a', '=', '1', ';',
-            'b', '=', '0', ';',
-             '#', '1',
-               '$display',
-                '(',
-                '"$pow(2,3) returns %d"',
-                '$pow', '(', '2', '3', ')',
-                ')',
-                ';',
-             '#', '1',
-              'result', '=', '$pow', '(', 'a', 'b', ')', ';',
-             '#', '1',
-               '$display',
-                '(',
-                '"$pow(a,b) returns %d (a=%d b=%d)"',
-                'result',
-                'a',
-                'b',
-                ')',
-                ';',
-            '#', '1', '$stop', ';',
-            '$finish', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/primitives.v.parsed.txt Deleted

@@ -1,137 +0,0 @@
-/////////////////////////////////////////////////////////////////////
-////                                                             ////
-////  USB function core primitives                               ////
-////  This file contains all technology dependent primitives     ////
-////  such as SSRAMs.                                            ////
-////                                                             ////
-////  Author: Rudolf Usselmann                                   ////
-////          rudi@asics.ws                                      ////
-////                                                             ////
-////                                                             ////
-////  Downloaded from: http://www.opencores.org/cores/usb/       ////
-////                                                             ////
-/////////////////////////////////////////////////////////////////////
-////                                                             ////
-//// Copyright (C) 2000 Rudolf Usselmann                         ////
-////                    rudi@asics.ws                            ////
-////                                                             ////
-//// This source file may be used and distributed without        ////
-//// restriction provided that this copyright statement is not   ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer.////
-////                                                             ////
-////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
-//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
-//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
-//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
-//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
-//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
-//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
-//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
-//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
-//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
-//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
-//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
-//// POSSIBILITY OF SUCH DAMAGE.                                 ////
-////                                                             ////
-/////////////////////////////////////////////////////////////////////
-
-//  CVS Log
-//
-//  $Id: primitives.v,v 1.0 2001/03/07 09:17:12 rudi Exp $
-//
-//  $Date: 2001/03/07 09:17:12 $
-//  $Revision: 1.0 $
-//  $Author: rudi $
-//  $Locker:  $
-//  $State: Exp $
-//
-// Change History:
-//               $Log: primitives.v,v $
-//               Revision 1.0  2001/03/07 09:17:12  rudi
-//
-//
-//               Changed all revisions to revision 1.0. This is because OpenCores CVS
-//               interface could not handle the original '0.1' revision ....
-//
-//               Revision 0.1.0.1  2001/02/28 08:11:11  rudi
-//               Initial Release
-//
-//
-
-`include "usb_defines.v"
-
-///////////////////////////////////////////////////////////////////
-//
-// SSRAM Model
-//
-///////////////////////////////////////////////////////////////////
-module ssram(	clk, rst,
-		radr, rdin, rdout, rre, rwe
-		);
-
-input		clk, rst;
-input	14:0	radr;
-input	31:0	rdin;
-output	31:0	rdout;
-input		rre, rwe;
-
-///////////////////////////////////////////////////////////////////
-//
-// Local Wires and Registers
-//
-
-reg	31:0	mem0:8192;
-reg	31:0	rdout;
-wire	11:0	adr_i = radr11:0;
-
-///////////////////////////////////////////////////////////////////
-//
-// Memory Logic
-//
-
-//always @(posedge clk)
-//	if(rst & rwe)	memadr_i <= #1 rdin;
-
-always @(posedge clk)
-	if(rst & rre)	rdout <= #1 memadr_i;
-
-endmodule
-
-
-
-   'module',
-      'ssram',
-      '(',
-      'clk', 'rst', 'radr', 'rdin', 'rdout', 'rre', 'rwe',
-      ')',
-      ';',
-     'input', 'clk', 'rst', ';',
-      'input', '', '14', ':', '0', '', 'radr', ';',
-      'input', '', '31', ':', '0', '', 'rdin', ';',
-      'output', '', '31', ':', '0', '', 'rdout', ';',
-      'input', 'rre', 'rwe', ';',
-       'reg',
-        '',
-        '31',
-        ':',
-        '0',
-        '',
-        'mem', '', '0', ':', '8192', '',
-        ';',
-      'reg', '', '31', ':', '0', '', 'rdout', ';',
-       'wire',
-        '',
-        '11',
-        ':',
-        '0',
-        '',
-        'adr_i', '=', 'radr', '', '11', '0', '',
-        ';',
-       'always',
-        '@', '(', 'posedge', 'clk', ')',
-         'if',
-          '(', 'rst', '&', 'rre', ')',
-           'rdout', '<=', '#', '1', 'mem', '', 'adr_i', '',
-            ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/propagatep_test.v.parsed.txt Deleted

@@ -1,104 +0,0 @@
-/**********************************************************************
- * $propagatep_test example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $propagatep_test PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-  reg  7:0 reg1;
-  real       real1;
-  reg  7:0 mem1 0:3;
-
-  initial
-    begin
-      $monitor("\nAt time %0d in test bench: reg1=%h  real1=%2.1f  mem10=%h\n",
-               $stime, reg1, real1, mem10);
-      reg1  = 1'b0;
-      real1 = 0.0;
-
-      #1 $display("Calling $propagatep_test(reg1)...");
-         $propagatep_test(reg1);
-
-      #1 $display("Calling $propagatep_test(real1)...");
-         $propagatep_test(real1);
-
-      #1 $display("Calling $propagatep_test(reg12)...");
-         $propagatep_test(reg12);
-
-      #1 $display("Calling $propagatep_test(reg17:4)...");
-         $propagatep_test(reg17:4);
-
-      #1 $display("Calling $propagatep_test(mem10)...");
-         $propagatep_test(mem10);
-
-      #1 $finish;
-    end
-
-endmodule
-
-/**********************************************************************/
-
-
-
-  'module', 'test', ';',
-     'reg', '', '7', ':', '0', '', 'reg1', ';',
-      'real', 'real1', ';',
-      'reg', '', '7', ':', '0', '', 'mem1', '', '0', ':', '3', '', ';',
-       'initial',
-         'begin',
-            '$monitor',
-              '(',
-              '"\\nAt time %0d in test bench: reg1=%h  real1=%2.1f  '
-              'mem10=%h\\n"',
-              '$stime',
-              'reg1',
-              'real1',
-              'mem1', '', '0', '',
-              ')',
-              ';',
-            'reg1', '=', "1 'b 0", ';',
-            'real1', '=', '0.0', ';',
-             '#', '1',
-               '$display',
-                '(',
-                '"Calling $propagatep_test(reg1)..."',
-                ')',
-                ';',
-            '$propagatep_test', '(', 'reg1', ')', ';',
-             '#', '1',
-               '$display',
-                '(',
-                '"Calling $propagatep_test(real1)..."',
-                ')',
-                ';',
-            '$propagatep_test', '(', 'real1', ')', ';',
-             '#', '1',
-               '$display',
-                '(',
-                '"Calling $propagatep_test(reg12)..."',
-                ')',
-                ';',
-            '$propagatep_test', '(', 'reg1', '', '2', '', ')', ';',
-             '#', '1',
-               '$display',
-                '(',
-                '"Calling $propagatep_test(reg17:4)..."',
-                ')',
-                ';',
-            '$propagatep_test', '(', 'reg1', '', '7', '4', '', ')', ';',
-             '#', '1',
-               '$display',
-                '(',
-                '"Calling $propagatep_test(mem10)..."',
-                ')',
-                ';',
-            '$propagatep_test', '(', 'mem1', '', '0', '', ')', ';',
-            '#', '1', '$finish', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/psr1.v.parsed.txt Deleted

@@ -1,67 +0,0 @@
-// Verilog HDL for "gates.lib", "psr1" "_functional"
-// Module Parallel Shift Register 1
-module psr1 (sin, pin, clk, sout, pout);
-
-input
-	sin, pin, clk;
-
-output
-	sout, pout;
-wire
-	sout, pout;
-
-parameter
-	t_hold	= -14,
-	t_setup	= 23,
-	delay	= 20,
-	t_separation = 10;
-
-defparam
-	psr1conf.t_separation = t_separation,
-	psr1conf.delay  = 15,
-	psr1split.delay = 10,
-	psr1dro.t_hold 	= t_hold + 15,
-	psr1dro.t_setup = t_setup - 15,
-	psr1dro.delay 	= delay - 10;
-
-wire
-	din, dout;
-
-conf_buff psr1conf(sin, pin, din);
-dro_cell  psr1dro(din, clk, dout);
-splitter  psr1split(dout, sout, pout);
-
-endmodule
-	
-
-
-   'module',
-      'psr1',
-      '(',
-      'sin', 'pin', 'clk', 'sout', 'pout',
-      ')',
-      ';',
-     'input', 'sin', 'pin', 'clk', ';',
-      'output', 'sout', 'pout', ';',
-      'wire', 'sout', 'pout', ';',
-       'parameter',
-        't_hold', '=', '-', '14',
-        't_setup', '=', '23',
-        'delay', '=', '20',
-        't_separation', '=', '10',
-        ';',
-       'defparam',
-        'psr1conf.t_separation', '=', 't_separation',
-        'psr1conf.delay', '=', '15',
-        'psr1split.delay', '=', '10',
-        'psr1dro.t_hold', '=', 't_hold', '+', '15',
-        'psr1dro.t_setup', '=', 't_setup', '-', '15',
-        'psr1dro.delay', '=', 'delay', '-', '10',
-        ';',
-      'wire', 'din', 'dout', ';',
-      'conf_buff', 'psr1conf', '(', 'sin', 'pin', 'din', ')', ';',
-      'dro_cell', 'psr1dro', '(', 'din', 'clk', 'dout', ')', ';',
-       'splitter',
-        'psr1split', '(', 'dout', 'sout', 'pout', ')',
-        ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/psr1_conf.v.parsed.txt Deleted

@@ -1,311 +0,0 @@
-// Verilog HDL for "RSFQ.lib", "psr1_conf" "_functional"
-
-// Module CONFLUENCE BUFFER
-module psr1_conf (in1, in2, out);
-
-input
-	in1, in2;
-
-output
-	out;
-reg 
-	out;
-
-parameter
-	t_separation = 10,
-	delay=15,
-
-// multichannel description of a warning file
-	warning_file=2,  
-// multichannel description of a delay file
-	delay_file = warning_file<<1;
-
-reg
-	sep_clr; // signal marking the end of the min separation zone
-		 //  for the last pulse
-
-integer
-	last_in_time,    // time when the last t pulse appeared
-	in_sep,	 // number of pulses within an interval t_sep before 
-		 //  the last data pulse;
-	vdelay;		 // variable delay
-
-
-`include "INIT"
-
-`ifdef RANDOM_DELAYS
- `include "RANDOM_GATE"
-`endif
-
-
-initial 
-	begin
-		vdelay = delay;
-
-`ifdef RANDOM_DELAYS
-		delay_dev = psr1_conf_variation*delay;
-		vdelay = $dist_normal(psr1_conf_seed, delay, delay_dev);
-`endif
-
-		#1 $fdisplay(delay_file, "module=%m, nom_delay=%0d, delay=%0d", delay, vdelay);
-
-// clear internal registers and the output signal
-		last_in_time = 0;
-		in_sep = 0;
-		sep_clr = 0;
-		out = 0;
-	end
-
-always @(posedge in1)
-	begin
-		out <= #vdelay ((in_sep > 0) || (in2 == 1)) ? 1'bx : 1;
-		out <= #(vdelay+2) 0;
-		
-		if((in_sep>0) || (in2 == 1))
-	          begin
-	        // generating a warning
-	            $fwrite(warning_file, 
-	            "Violation of separation time in module %m.\n");
-	            $fwrite(warning_file,
-	            "Input pulses at ");
-		    if(in_sep>0)
-			$fwrite(warning_file,
-			"%0d and at %0d.\n", last_in_time, $stime);
-		    else
-			$fwrite(warning_file,
-			"%0d and at %0d.\n", $stime, $stime);
-	    	  end
-	  	last_in_time <= $stime;
-
-		in_sep <= in_sep + 1;
-		sep_clr <= #(t_separation-1) 1;
-	end
-
-always @(posedge in2)
-	begin
-		out <= #vdelay ((in_sep > 0) || (in1 == 1)) ? 1'bx : 1;
-		out <= #(vdelay+2) 0;
-
-		if((in_sep>0) || (in1 == 1))
-	          begin
-	        // generating a warning
-	            $fwrite(warning_file, 
-	            "Violation of separation time in module %m.\n");
-	            $fwrite(warning_file,
-	            "Input pulses at ");
-		    if(in_sep>0)
-			$fwrite(warning_file,
-			"%0d and at %0d.\n", last_in_time, $stime);
-		    else
-			$fwrite(warning_file,
-			"%0d and at %0d.\n", $stime, $stime);
-	    	  end
-	  	last_in_time <= $stime;
-
-		in_sep <= in_sep + 1;
-		sep_clr <= #(t_separation-1) 1;
-	end
-
-always @(posedge sep_clr)
-	begin
-	  	in_sep <= in_sep - 1;
-		sep_clr <= 0;
-	end
-
-
-endmodule
-
-
-  'module', 'psr1_conf', '(', 'in1', 'in2', 'out', ')', ';',
-     'input', 'in1', 'in2', ';',
-      'output', 'out', ';',
-      'reg', 'out', ';',
-       'parameter',
-        't_separation', '=', '10',
-        'delay', '=', '15',
-        'warning_file', '=', '2',
-        'delay_file', '=', 'warning_file', '<<', '1',
-        ';',
-      'reg', 'sep_clr', ';',
-      'integer', 'last_in_time', 'in_sep', 'vdelay', ';',
-       'initial',
-         'begin',
-           'vdelay', '=', 'delay', ';',
-             'delay_dev', '=', 'psr1_conf_variation', '*', 'delay',
-              ';',
-              'vdelay',
-                '=',
-                 '$dist_normal',
-                  '(',
-                  'psr1_conf_seed',
-                  'delay',
-                  'delay_dev',
-                  ')',
-              ';',
-             '#', '1',
-               '$fdisplay',
-                '(',
-                'delay_file',
-                '"module=%m, nom_delay=%0d, delay=%0d"',
-                'delay',
-                'vdelay',
-                ')',
-                ';',
-            'last_in_time', '=', '0', ';',
-            'in_sep', '=', '0', ';',
-            'sep_clr', '=', '0', ';',
-            'out', '=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'in1', ')',
-         'begin',
-             'out',
-                '<=',
-                '#', 'vdelay',
-                '(',
-                 '(',
-                  'in_sep', '>', '0',
-                  ')',
-                  '||',
-                  '(',
-                  'in2', '==', '1',
-                  ')',
-                ')',
-                '?',
-                "1 'b x",
-                ':',
-                '1',
-              ';',
-             'out', '<=', '#', '(', 'vdelay', '+', '2', ')', '0',
-              ';',
-             'if',
-               '(',
-                '(',
-                'in_sep', '>', '0',
-                ')',
-                '||',
-                '(',
-                'in2', '==', '1',
-                ')',
-                ')',
-               'begin',
-                  '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Violation of separation time in module %m.\\n"',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Input pulses at "',
-                    ')',
-                    ';',
-                   'if',
-                    '(', 'in_sep', '>', '0', ')',
-                     '$fwrite',
-                      '(',
-                      'warning_file',
-                      '"%0d and at %0d.\\n"',
-                      'last_in_time',
-                      '$stime',
-                      ')',
-                      ';',
-                    'else',
-                     '$fwrite',
-                      '(',
-                      'warning_file',
-                      '"%0d and at %0d.\\n"',
-                      '$stime',
-                      '$stime',
-                      ')',
-                      ';',
-                'end',
-            'last_in_time', '<=', '$stime', ';',
-            'in_sep', '<=', 'in_sep', '+', '1', ';',
-              'sep_clr',
-                '<=',
-                '#', '(', 't_separation', '-', '1', ')',
-                '1',
-              ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'in2', ')',
-         'begin',
-             'out',
-                '<=',
-                '#', 'vdelay',
-                '(',
-                 '(',
-                  'in_sep', '>', '0',
-                  ')',
-                  '||',
-                  '(',
-                  'in1', '==', '1',
-                  ')',
-                ')',
-                '?',
-                "1 'b x",
-                ':',
-                '1',
-              ';',
-             'out', '<=', '#', '(', 'vdelay', '+', '2', ')', '0',
-              ';',
-             'if',
-               '(',
-                '(',
-                'in_sep', '>', '0',
-                ')',
-                '||',
-                '(',
-                'in1', '==', '1',
-                ')',
-                ')',
-               'begin',
-                  '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Violation of separation time in module %m.\\n"',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Input pulses at "',
-                    ')',
-                    ';',
-                   'if',
-                    '(', 'in_sep', '>', '0', ')',
-                     '$fwrite',
-                      '(',
-                      'warning_file',
-                      '"%0d and at %0d.\\n"',
-                      'last_in_time',
-                      '$stime',
-                      ')',
-                      ';',
-                    'else',
-                     '$fwrite',
-                      '(',
-                      'warning_file',
-                      '"%0d and at %0d.\\n"',
-                      '$stime',
-                      '$stime',
-                      ')',
-                      ';',
-                'end',
-            'last_in_time', '<=', '$stime', ';',
-            'in_sep', '<=', 'in_sep', '+', '1', ';',
-              'sep_clr',
-                '<=',
-                '#', '(', 't_separation', '-', '1', ')',
-                '1',
-              ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'sep_clr', ')',
-         'begin',
-           'in_sep', '<=', 'in_sep', '-', '1', ';',
-            'sep_clr', '<=', '0', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/psr1_dro.v.parsed.txt Deleted

@@ -1,342 +0,0 @@
-// Verilog HDL for "RSFQ.lib", "psr1_dro" "_functional"
-
-// Module DRO cell
-module psr1_dro (d, clk, out);
-
-input
-	d, clk;
-
-output
-	out;
-reg 
-	out;
-
-parameter
-	t_hold	= 1,
-	t_setup	= 8,
-	delay	= 10,
-
-// multichannel description of a warning file
-	warning_file=2,  
-// multichannel description of a delay file
-	delay_file = warning_file<<1;
-
-reg
-	d_internal, clk_internal,
-	d_state,          	   // internal state at the input d
-	d_set;		   	   // signal determining the moment when
-				   // the state of the d input changes to "1"
-
-integer
-	data_delay,  // delay between d and d_internal
-	clk_delay,   // delay between clk and clk_internal
-	out_delay,   // delay between clk_internal and out
-	out_value,   // output value in a given clock cycle
-	last_clk_time,	// time when the last clock pulse appeared
-	vt_hold,	// variable hold
-	vt_setup,	// variable setup
-	vdelay;		 // variable delay
-
-
-`include "INIT"
-
-`ifdef RANDOM_DELAYS
- `include "RANDOM_GATE"
-`endif
-
-
-initial 
-	begin
-		vt_hold = t_hold;
-		vt_setup = t_setup;
-		vdelay = delay;
-
-`ifdef RANDOM_DELAYS
-		delay_dev = psr1_dro_variation*delay;
-		vdelay = $dist_normal(psr1_dro_seed, delay, delay_dev);
-		vt_hold = $dist_normal(psr1_dro_seed, t_hold, 
-                                       psr1_dro_hs_dev);
-		vt_setup = t_setup + (t_hold - vt_hold);
-
-`endif
-
-		#1 $fdisplay(delay_file, "module=%m, nom_delay=%0d, delay=%0d", delay, vdelay);
-		#1 $fdisplay(delay_file, "module=%m, nom_hold=%0d, hold=%0d", t_hold, vt_hold);
-		#1 $fdisplay(delay_file, "module=%m, nom_setup=%0d, setup=%0d", t_setup, vt_setup);
-
-
-
-// define delays between inputs & outputs and the corresponding
-//  internal auxiliary registers
-	  	if(vt_hold<0)
-		  begin
-	    	  	data_delay = -vt_hold;
-	    		clk_delay  = 0;
-			out_delay  = vdelay;
-		  end
-	  	else
-		  begin
-	   	  	data_delay = 0;
-	    		clk_delay  = vt_hold;
-		  	out_delay  = vdelay-vt_hold;
-		  end
-
-// clear internal registers and the output signal
-		d_internal = 0;
-		clk_internal = 0;
-		last_clk_time = 0;
-		d_state = 0;
-		d_set = 0;
-		out = 0;
-	end
-
-
-
-always @(posedge d) 	// Execute at positive edge of d
-	  d_internal <= #(data_delay) d;
-
-always @(posedge clk)  // Execute at positive edge of clk
-	  clk_internal <= #(clk_delay) clk;
-
-
-always @(posedge d_internal)
-	begin
-// setting the state of the d input
-                d_state <= d_state | 1'bx;
-		if (d_internal === 1)
-		  d_set <= #(vt_hold+vt_setup) 1;
-
-		d_internal <= 0;
-	end
-
-always @(posedge d_set)
-	begin
-		if ($stime - last_clk_time >= vt_hold+vt_setup)
-			d_state = 1;
-		else
-		  begin
-			d_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input D pulse at %0d,",
-			 $stime-data_delay-vt_hold-vt_setup);
-			$fwrite(warning_file,
-			"\tClock pulse at %0d.\n", last_clk_time-clk_delay);
-		  end
-
-		d_set <= 0;
-	end
-
-
-always @(posedge clk_internal)	
-	begin
-// computing the output
-		if (clk_internal === 1'bx)
-		  out_value = 1'bx;
-		else
-		  out_value = d_state;
-
-// transfering the result to the output
-		out <= #(out_delay) out_value;
-		out <= #(out_delay+2) 0;
-
-// clearing the internal state of the DRO
-		d_state  <= 0;
-
-		clk_internal <= 0;
-		last_clk_time = $stime;
-	end
-
-endmodule
-
-
-  'module', 'psr1_dro', '(', 'd', 'clk', 'out', ')', ';',
-     'input', 'd', 'clk', ';',
-      'output', 'out', ';',
-      'reg', 'out', ';',
-       'parameter',
-        't_hold', '=', '1',
-        't_setup', '=', '8',
-        'delay', '=', '10',
-        'warning_file', '=', '2',
-        'delay_file', '=', 'warning_file', '<<', '1',
-        ';',
-      'reg', 'd_internal', 'clk_internal', 'd_state', 'd_set', ';',
-       'integer',
-        'data_delay',
-        'clk_delay',
-        'out_delay',
-        'out_value',
-        'last_clk_time',
-        'vt_hold',
-        'vt_setup',
-        'vdelay',
-        ';',
-       'initial',
-         'begin',
-           'vt_hold', '=', 't_hold', ';',
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-            'vdelay', '=', 'delay', ';',
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-              'vdelay',
-                '=',
-                 '$dist_normal',
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-                  'psr1_dro_seed',
-                  'delay',
-                  'delay_dev',
-                  ')',
-              ';',
-              'vt_hold',
-                '=',
-                 '$dist_normal',
-                  '(',
-                  'psr1_dro_seed',
-                  't_hold',
-                  'psr1_dro_hs_dev',
-                  ')',
-              ';',
-              'vt_setup',
-                '=',
-                't_setup',
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-                ')',
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-             '#', '1',
-               '$fdisplay',
-                '(',
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-                '"module=%m, nom_setup=%0d, setup=%0d"',
-                't_setup',
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-              '(', 'vt_hold', '<', '0', ')',
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-            'clk_internal', '=', '0', ';',
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-         'begin',
-           'd_state', '<=', 'd_state', '|', "1 'b x", ';',
-             'if',
-              '(', 'd_internal', '===', '1', ')',
-                'd_set',
-                  '<=',
-                  '#', '(', 'vt_hold', '+', 'vt_setup', ')',
-                  '1',
-                ';',
-            'd_internal', '<=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'd_set', ')',
-         'begin',
-            'if',
-               '(',
-                '$stime',
-                '-',
-                'last_clk_time',
-                '>=',
-                'vt_hold',
-                '+',
-                'vt_setup',
-                ')',
-              'd_state', '=', '1', ';',
-              'else',
-               'begin',
-                 'd_state', '=', "1 'b x", ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Violation of hold/setup time in module %m.\\n"',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Input D pulse at %0d,"',
-                    '$stime',
-                    '-',
-                    'data_delay',
-                    '-',
-                    'vt_hold',
-                    '-',
-                    'vt_setup',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"\\tClock pulse at %0d.\\n"',
-                    'last_clk_time',
-                    '-',
-                    'clk_delay',
-                    ')',
-                    ';',
-                'end',
-            'd_set', '<=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'clk_internal', ')',
-         'begin',
-            'if',
-              '(', 'clk_internal', '===', "1 'b x", ')',
-              'out_value', '=', "1 'b x", ';',
-              'else',
-              'out_value', '=', 'd_state', ';',
-             'out', '<=', '#', '(', 'out_delay', ')', 'out_value',
-              ';',
-             'out', '<=', '#', '(', 'out_delay', '+', '2', ')', '0',
-              ';',
-            'd_state', '<=', '0', ';',
-            'clk_internal', '<=', '0', ';',
-            'last_clk_time', '=', '$stime', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/psr1_split.v.parsed.txt Deleted

@@ -1,104 +0,0 @@
-// Verilog HDL for "gates.lib", "splitter" "_functional"
-
-module psr1_split (out1, out2, in);
-
-input
-	in;
-
-output
-	out1, out2;
-reg 
-	out1, out2;
-
-parameter
-	delay=10,
-
-// multichannel description of a warning file
-	warning_file=2,  
-// multichannel description of a delay file
-	delay_file = warning_file<<1;
-
-integer
-	vdelay;		 // variable delay
-
-
-`include "INIT"
-
-`ifdef RANDOM_DELAYS
- `include "RANDOM_GATE"
-`endif
-
-
-initial 
-	begin
-		vdelay = delay;
-
-`ifdef RANDOM_DELAYS
-		delay_dev = psr1_split_variation*delay;
-		vdelay = $dist_normal(psr1_dro_seed, delay, delay_dev);
-`endif
-
-		#1 $fdisplay(delay_file, "module=%m, nom_delay=%0d, delay=%0d", delay, vdelay);
-
-		out1 = 0;
-		out2 = 0;
-	end
-
-always @(posedge in) 	// Execute at positive edge of in
-	begin
-	  out1 <= #vdelay in;
-	  out1 <= #(vdelay+2) 0;
-	  out2 <= #vdelay in;
-	  out2 <= #(vdelay+2) 0;
-	end
-
-endmodule
-
-
-  'module', 'psr1_split', '(', 'out1', 'out2', 'in', ')', ';',
-     'input', 'in', ';',
-      'output', 'out1', 'out2', ';',
-      'reg', 'out1', 'out2', ';',
-       'parameter',
-        'delay', '=', '10',
-        'warning_file', '=', '2',
-        'delay_file', '=', 'warning_file', '<<', '1',
-        ';',
-      'integer', 'vdelay', ';',
-       'initial',
-         'begin',
-           'vdelay', '=', 'delay', ';',
-             'delay_dev', '=', 'psr1_split_variation', '*', 'delay',
-              ';',
-              'vdelay',
-                '=',
-                 '$dist_normal',
-                  '(',
-                  'psr1_dro_seed',
-                  'delay',
-                  'delay_dev',
-                  ')',
-              ';',
-             '#', '1',
-               '$fdisplay',
-                '(',
-                'delay_file',
-                '"module=%m, nom_delay=%0d, delay=%0d"',
-                'delay',
-                'vdelay',
-                ')',
-                ';',
-            'out1', '=', '0', ';',
-            'out2', '=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'in', ')',
-         'begin',
-           'out1', '<=', '#', 'vdelay', 'in', ';',
-             'out1', '<=', '#', '(', 'vdelay', '+', '2', ')', '0',
-              ';',
-            'out2', '<=', '#', 'vdelay', 'in', ';',
-             'out2', '<=', '#', '(', 'vdelay', '+', '2', ')', '0',
-              ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/psr2.v.parsed.txt Deleted

@@ -1,61 +0,0 @@
-// Verilog HDL for "gates.lib", "psr2" "_functional"
-// Module Parallel Shift Register 2
-module psr2 (sin, clr, clk, sout, pout);
-
-input
-	sin, clr, clk;
-
-output
-	sout, pout;
-wire
-	sout, pout;
-
-parameter
-	t_hold	= 14,
-	t_setup	= -3,
-	delay	= 31;
-
-defparam
-	psr2split.delay = 10,
-	psr2and.t_hold = t_hold,
-	psr2and.t_setup = t_setup,
-	psr2and.delay = delay - 10;
-
-wire
-	aout;
-
-and_gate  psr2and(sin, clr, clk, aout);
-splitter  psr2split(aout, sout, pout);
-
-endmodule
-	
-
-
-   'module',
-      'psr2',
-      '(',
-      'sin', 'clr', 'clk', 'sout', 'pout',
-      ')',
-      ';',
-     'input', 'sin', 'clr', 'clk', ';',
-      'output', 'sout', 'pout', ';',
-      'wire', 'sout', 'pout', ';',
-       'parameter',
-        't_hold', '=', '14',
-        't_setup', '=', '-', '3',
-        'delay', '=', '31',
-        ';',
-       'defparam',
-        'psr2split.delay', '=', '10',
-        'psr2and.t_hold', '=', 't_hold',
-        'psr2and.t_setup', '=', 't_setup',
-        'psr2and.delay', '=', 'delay', '-', '10',
-        ';',
-      'wire', 'aout', ';',
-       'and_gate',
-        'psr2and', '(', 'sin', 'clr', 'clk', 'aout', ')',
-        ';',
-       'splitter',
-        'psr2split', '(', 'aout', 'sout', 'pout', ')',
-        ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/psr2_and.v.parsed.txt Deleted

@@ -1,451 +0,0 @@
-// Verilog HDL for "RSFQ.lib", "and_gate" "_functional"
-
-// Module AND gate
-module psr2_and (a, b, clk, out);
-
-input
-	a, b, clk;
-
-output
-	out;
-reg 
-	out;
-
-parameter
-	t_hold	= 14,
-	t_setup	= -3,
-	delay	= 21,
-
-// multichannel description of a warning file
-	warning_file=2,  
-// multichannel description of a delay file
-	delay_file = warning_file<<1;
-
-reg
-	a_internal, b_internal, clk_internal,
-	a_state, b_state,          // internal state at inputs a and b
-	a_set, b_set;		   // signals determining the moment when
-				   // the state of the a,b inputs changes to "1"
-integer
-	data_delay, 	// delay between a (b) and a_internal (b_internal)
-	clk_delay, 	// delay between clk and clk_internal
-	out_delay, 	// delay between clk_internal and out
-	out_value,	// output value in a given clock cycle
-	last_clk_time,	// time when the last clock pulse appeared
-	vt_hold,	// variable hold
-	vt_setup,	// variable setup
-	vdelay;		// variable delay
-
-
-`include "INIT"
-
-`ifdef RANDOM_DELAYS
- `include "RANDOM_GATE"
-`endif
-
-
-initial 
-	begin
-		vt_hold = t_hold;
-		vt_setup = t_setup;
-		vdelay = delay;
-
-`ifdef RANDOM_DELAYS
-		delay_dev = psr2_and_variation*delay;
-		vdelay = $dist_normal(psr2_and_seed, delay, delay_dev);
-		vt_hold = $dist_normal(psr2_and_seed, t_hold, 
-                                         psr2_and_hs_dev);
-		vt_setup = t_setup + (t_hold - vt_hold);
-`endif
-
-		#1 $fdisplay(delay_file, "module=%m, nom_delay=%0d, delay=%0d", delay, vdelay);
-		#1 $fdisplay(delay_file, "module=%m, nom_hold=%0d, hold=%0d", t_hold, vt_hold);
-		#1 $fdisplay(delay_file, "module=%m, nom_setup=%0d, setup=%0d", t_setup, vt_setup);
-
-
-// define delays between inputs & outputs and the corresponding
-//  internal auxiliary registers
-	  	if(vt_hold<0)
-		  begin
-	    		data_delay = -vt_hold;
-	    	  	clk_delay = 0;
-		  	out_delay = vdelay;
-		  end
-	  	else
-		  begin
-	    	  	data_delay = 0;
-	    	  	clk_delay = vt_hold;
-		  	out_delay=vdelay-vt_hold;
-		  end
-
-// clear internal registers and the output signal
-		a_internal = 0;
-		b_internal = 0;
-		clk_internal = 0;
-		last_clk_time = 0;
-		a_state = 0;
-		b_state = 0;
-		a_set = 0;
-		b_set = 0;
-		out = 0;
-	end
-
-always @(posedge a) 	// Execute at positive edge of a
-	  a_internal <= #(data_delay) a;
-
-always @(posedge b) 	// Execute at positive edge of b
-	  b_internal <= #(data_delay) b;
-
-always @(posedge clk) 	// Execute at positive edge of clk
-	  clk_internal <= #(clk_delay) clk;
-
-always @(posedge a_internal)
-	begin
-// setting an internal state at the input a
-                a_state <= a_state | 1'bx;
-		if (a_internal === 1)
-		  a_set <= #(vt_hold+vt_setup) 1;
-
-		a_internal <= 0;
-	end
-
-always @(posedge b_internal)
-	begin
-// setting an internal state at the input a
-                b_state <= b_state | 1'bx;
-		if (b_internal === 1)
-		  b_set <= #(vt_hold+vt_setup) 1;
-
-		b_internal <= 0;
-	end
-
-always @(posedge a_set)
-	begin
-		if ($stime - last_clk_time >= vt_hold+vt_setup)
-			a_state = 1;
-		else
-		  begin
-			a_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input A pulse at %0d,",
-			 $stime-data_delay-vt_hold-vt_setup);
-			$fwrite(warning_file,
-			"\tClock pulse at %0d.\n", last_clk_time-clk_delay);
-		  end
-
-		a_set <= 0;
-	end
-
-always @(posedge b_set)
-	begin
-		if ($stime - last_clk_time >= vt_hold+vt_setup)
-			b_state = 1;
-		else
-		  begin
-			b_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input B pulse at %0d,",
-			 $stime-data_delay-vt_hold-vt_setup);
-			$fwrite(warning_file,
-			"\tClock pulse at %0d.\n", last_clk_time-clk_delay);
-		  end
-
-		b_set <= 0;
-	end
-
-
-always @(posedge clk_internal)	
-	begin
-// computing the output
-		if (clk_internal === 1'bx)
-		  out_value = 1'bx;
-		else
-		  out_value = a_state & b_state;
-
-// transfering the result to the output
-		out <= #(out_delay) out_value;
-		out <= #(out_delay+2) 0;
-
-// clearing the internal state of A and B inputs
-		a_state  <= 0;
-		b_state  <= 0;
-
-		clk_internal <= 0;
-		last_clk_time = $stime;
-	end
-
-endmodule
-
-
-  'module', 'psr2_and', '(', 'a', 'b', 'clk', 'out', ')', ';',
-     'input', 'a', 'b', 'clk', ';',
-      'output', 'out', ';',
-      'reg', 'out', ';',
-       'parameter',
-        't_hold', '=', '14',
-        't_setup', '=', '-', '3',
-        'delay', '=', '21',
-        'warning_file', '=', '2',
-        'delay_file', '=', 'warning_file', '<<', '1',
-        ';',
-       'reg',
-        'a_internal',
-        'b_internal',
-        'clk_internal',
-        'a_state',
-        'b_state',
-        'a_set',
-        'b_set',
-        ';',
-       'integer',
-        'data_delay',
-        'clk_delay',
-        'out_delay',
-        'out_value',
-        'last_clk_time',
-        'vt_hold',
-        'vt_setup',
-        'vdelay',
-        ';',
-       'initial',
-         'begin',
-           'vt_hold', '=', 't_hold', ';',
-            'vt_setup', '=', 't_setup', ';',
-            'vdelay', '=', 'delay', ';',
-            'delay_dev', '=', 'psr2_and_variation', '*', 'delay', ';',
-              'vdelay',
-                '=',
-                 '$dist_normal',
-                  '(',
-                  'psr2_and_seed',
-                  'delay',
-                  'delay_dev',
-                  ')',
-              ';',
-              'vt_hold',
-                '=',
-                 '$dist_normal',
-                  '(',
-                  'psr2_and_seed',
-                  't_hold',
-                  'psr2_and_hs_dev',
-                  ')',
-              ';',
-              'vt_setup',
-                '=',
-                't_setup',
-                '+',
-                '(',
-                't_hold', '-', 'vt_hold',
-                ')',
-              ';',
-             '#', '1',
-               '$fdisplay',
-                '(',
-                'delay_file',
-                '"module=%m, nom_delay=%0d, delay=%0d"',
-                'delay',
-                'vdelay',
-                ')',
-                ';',
-             '#', '1',
-               '$fdisplay',
-                '(',
-                'delay_file',
-                '"module=%m, nom_hold=%0d, hold=%0d"',
-                't_hold',
-                'vt_hold',
-                ')',
-                ';',
-             '#', '1',
-               '$fdisplay',
-                '(',
-                'delay_file',
-                '"module=%m, nom_setup=%0d, setup=%0d"',
-                't_setup',
-                'vt_setup',
-                ')',
-                ';',
-             'if',
-              '(', 'vt_hold', '<', '0', ')',
-               'begin',
-                 'data_delay', '=', '-', 'vt_hold', ';',
-                  'clk_delay', '=', '0', ';',
-                  'out_delay', '=', 'vdelay', ';',
-                'end',
-              'else',
-               'begin',
-                 'data_delay', '=', '0', ';',
-                  'clk_delay', '=', 'vt_hold', ';',
-                  'out_delay', '=', 'vdelay', '-', 'vt_hold', ';',
-                'end',
-            'a_internal', '=', '0', ';',
-            'b_internal', '=', '0', ';',
-            'clk_internal', '=', '0', ';',
-            'last_clk_time', '=', '0', ';',
-            'a_state', '=', '0', ';',
-            'b_state', '=', '0', ';',
-            'a_set', '=', '0', ';',
-            'b_set', '=', '0', ';',
-            'out', '=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'a', ')',
-         'a_internal', '<=', '#', '(', 'data_delay', ')', 'a',
-          ';',
-       'always',
-        '@', '(', 'posedge', 'b', ')',
-         'b_internal', '<=', '#', '(', 'data_delay', ')', 'b',
-          ';',
-       'always',
-        '@', '(', 'posedge', 'clk', ')',
-         'clk_internal', '<=', '#', '(', 'clk_delay', ')', 'clk',
-          ';',
-       'always',
-        '@', '(', 'posedge', 'a_internal', ')',
-         'begin',
-           'a_state', '<=', 'a_state', '|', "1 'b x", ';',
-             'if',
-              '(', 'a_internal', '===', '1', ')',
-                'a_set',
-                  '<=',
-                  '#', '(', 'vt_hold', '+', 'vt_setup', ')',
-                  '1',
-                ';',
-            'a_internal', '<=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'b_internal', ')',
-         'begin',
-           'b_state', '<=', 'b_state', '|', "1 'b x", ';',
-             'if',
-              '(', 'b_internal', '===', '1', ')',
-                'b_set',
-                  '<=',
-                  '#', '(', 'vt_hold', '+', 'vt_setup', ')',
-                  '1',
-                ';',
-            'b_internal', '<=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'a_set', ')',
-         'begin',
-            'if',
-               '(',
-                '$stime',
-                '-',
-                'last_clk_time',
-                '>=',
-                'vt_hold',
-                '+',
-                'vt_setup',
-                ')',
-              'a_state', '=', '1', ';',
-              'else',
-               'begin',
-                 'a_state', '=', "1 'b x", ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Violation of hold/setup time in module %m.\\n"',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Input A pulse at %0d,"',
-                    '$stime',
-                    '-',
-                    'data_delay',
-                    '-',
-                    'vt_hold',
-                    '-',
-                    'vt_setup',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"\\tClock pulse at %0d.\\n"',
-                    'last_clk_time',
-                    '-',
-                    'clk_delay',
-                    ')',
-                    ';',
-                'end',
-            'a_set', '<=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'b_set', ')',
-         'begin',
-            'if',
-               '(',
-                '$stime',
-                '-',
-                'last_clk_time',
-                '>=',
-                'vt_hold',
-                '+',
-                'vt_setup',
-                ')',
-              'b_state', '=', '1', ';',
-              'else',
-               'begin',
-                 'b_state', '=', "1 'b x", ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Violation of hold/setup time in module %m.\\n"',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Input B pulse at %0d,"',
-                    '$stime',
-                    '-',
-                    'data_delay',
-                    '-',
-                    'vt_hold',
-                    '-',
-                    'vt_setup',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"\\tClock pulse at %0d.\\n"',
-                    'last_clk_time',
-                    '-',
-                    'clk_delay',
-                    ')',
-                    ';',
-                'end',
-            'b_set', '<=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'clk_internal', ')',
-         'begin',
-            'if',
-              '(', 'clk_internal', '===', "1 'b x", ')',
-              'out_value', '=', "1 'b x", ';',
-              'else',
-              'out_value', '=', 'a_state', '&', 'b_state', ';',
-             'out', '<=', '#', '(', 'out_delay', ')', 'out_value',
-              ';',
-             'out', '<=', '#', '(', 'out_delay', '+', '2', ')', '0',
-              ';',
-            'a_state', '<=', '0', ';',
-            'b_state', '<=', '0', ';',
-            'clk_internal', '<=', '0', ';',
-            'last_clk_time', '=', '$stime', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/psr2_split.v.parsed.txt Deleted

@@ -1,104 +0,0 @@
-// Verilog HDL for "gates.lib", "splitter" "_functional"
-
-module psr2_split (out1, out2, in);
-
-input
-	in;
-
-output
-	out1, out2;
-reg 
-	out1, out2;
-
-parameter
-	delay=10,
-
-// multichannel description of a warning file
-	warning_file=2,  
-// multichannel description of a delay file
-	delay_file = warning_file<<1;
-
-integer
-	vdelay;		 // variable delay
-
-
-`include "INIT"
-
-`ifdef RANDOM_DELAYS
- `include "RANDOM_GATE"
-`endif
-
-
-initial 
-	begin
-		vdelay = delay;
-
-`ifdef RANDOM_DELAYS
-		delay_dev = psr2_split_variation*delay;
-		vdelay = $dist_normal(psr2_split_seed, delay, delay_dev);
-`endif
-
-		#1 $fdisplay(delay_file, "module=%m, nom_delay=%0d, delay=%0d", delay, vdelay);
-
-		out1 = 0;
-		out2 = 0;
-	end
-
-always @(posedge in) 	// Execute at positive edge of in
-	begin
-	  out1 <= #vdelay in;
-	  out1 <= #(vdelay+2) 0;
-	  out2 <= #vdelay in;
-	  out2 <= #(vdelay+2) 0;
-	end
-
-endmodule
-
-
-  'module', 'psr2_split', '(', 'out1', 'out2', 'in', ')', ';',
-     'input', 'in', ';',
-      'output', 'out1', 'out2', ';',
-      'reg', 'out1', 'out2', ';',
-       'parameter',
-        'delay', '=', '10',
-        'warning_file', '=', '2',
-        'delay_file', '=', 'warning_file', '<<', '1',
-        ';',
-      'integer', 'vdelay', ';',
-       'initial',
-         'begin',
-           'vdelay', '=', 'delay', ';',
-             'delay_dev', '=', 'psr2_split_variation', '*', 'delay',
-              ';',
-              'vdelay',
-                '=',
-                 '$dist_normal',
-                  '(',
-                  'psr2_split_seed',
-                  'delay',
-                  'delay_dev',
-                  ')',
-              ';',
-             '#', '1',
-               '$fdisplay',
-                '(',
-                'delay_file',
-                '"module=%m, nom_delay=%0d, delay=%0d"',
-                'delay',
-                'vdelay',
-                ')',
-                ';',
-            'out1', '=', '0', ';',
-            'out2', '=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'in', ')',
-         'begin',
-           'out1', '<=', '#', 'vdelay', 'in', ';',
-             'out1', '<=', '#', '(', 'vdelay', '+', '2', ')', '0',
-              ';',
-            'out2', '<=', '#', 'vdelay', 'in', ';',
-             'out2', '<=', '#', '(', 'vdelay', '+', '2', ')', '0',
-              ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/read_4state_value_test.v.parsed.txt Deleted

@@ -1,70 +0,0 @@
-/**********************************************************************
- * $read_4state_value example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $read_4state_value PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-  reg        reg1;
-  reg 31:0 reg2;
-  reg 0:51 reg3;
-  real       r1;
-
-  initial
-    begin
-      reg1 = 1'b0;
-      reg2 = 32'hF0F0F0F0;
-      reg3 = {13{4'b01zx}};
-      r1   = 3.1415;
-
-      #1 $read_4state_value("Hello world");
-      #1 $read_4state_value(r1);
-      #1 $read_4state_value(reg1);
-      #1 $read_4state_value(reg2);
-      #1 $read_4state_value(reg3);
-      #1 $read_4state_value(reg31);
-      #1 $read_4state_value(reg34:48);
-
-      #1 $finish;
-    end
-
-endmodule
-
-/**********************************************************************/
-
-
-
-  'module', 'test', ';',
-     'reg', 'reg1', ';',
-      'reg', '', '31', ':', '0', '', 'reg2', ';',
-      'reg', '', '0', ':', '51', '', 'reg3', ';',
-      'real', 'r1', ';',
-       'initial',
-         'begin',
-           'reg1', '=', "1 'b 0", ';',
-            'reg2', '=', "32 'h F0F0F0F0", ';',
-            'reg3', '=', '{', '13', '{', "4 'b 01zx", '}', '}', ';',
-            'r1', '=', '3.1415', ';',
-             '#', '1',
-              '$read_4state_value', '(', '"Hello world"', ')', ';',
-            '#', '1', '$read_4state_value', '(', 'r1', ')', ';',
-            '#', '1', '$read_4state_value', '(', 'reg1', ')', ';',
-            '#', '1', '$read_4state_value', '(', 'reg2', ')', ';',
-            '#', '1', '$read_4state_value', '(', 'reg3', ')', ';',
-             '#', '1',
-              '$read_4state_value', '(', 'reg3', '', '1', '', ')', ';',
-             '#', '1',
-               '$read_4state_value',
-                '(',
-                'reg3', '', '4', '48', '',
-                ')',
-                ';',
-            '#', '1', '$finish', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/read_attribute_test.v.parsed.txt Deleted

@@ -1,86 +0,0 @@
-/**********************************************************************
- * $read_attribute example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $read_attribute PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-  reg  a, b, ci, clk;
-  wire sum, co;
-
-  addbit i1 (a, b, ci, sum, co);
-
-  initial
-    begin
-      #1 $read_attribute(i1, "InputLoad$");
-      #1 $read_attribute(i1, "Foo$");
-      #1 $finish;
-    end
-endmodule
-
-/*** A gate level 1 bit adder model ***/
-`timescale 1ns / 1ns
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci, sum, co,
-        n1, n2, n3;
-
-  xor    (n1, a, b);
-  xor #2 (sum, n1, ci);
-  and    (n2, a, b);
-  and    (n3, n1, ci);
-  or  #2 (co, n2, n3);
-  
-  specify
-    specparam InputLoad$a = 1.1;
-    specparam InputLoad$b = 2.2;
-    specparam InputLoad$  = 3.3;
-  endspecify
-
-endmodule
-/*********************************************************************/
-
-
-
-  'module', 'test', ';',
-     'reg', 'a', 'b', 'ci', 'clk', ';',
-      'wire', 'sum', 'co', ';',
-       'addbit',
-        'i1', '(', 'a', 'b', 'ci', 'sum', 'co', ')',
-        ';',
-       'initial',
-         'begin',
-            '#', '1',
-              '$read_attribute', '(', 'i1', '"InputLoad$"', ')', ';',
-            '#', '1', '$read_attribute', '(', 'i1', '"Foo$"', ')', ';',
-            '#', '1', '$finish', ';',
-          'end',
-    'endmodule',
-    'module',
-      'addbit',
-      '(',
-      'a', 'b', 'ci', 'sum', 'co',
-      ')',
-      ';',
-     'input', 'a', 'b', 'ci', ';',
-      'output', 'sum', 'co', ';',
-      'wire', 'a', 'b', 'ci', 'sum', 'co', 'n1', 'n2', 'n3', ';',
-      'xor', '(', 'n1', 'a', 'b', ')', ';',
-      'xor', '#', '2', '(', 'sum', 'n1', 'ci', ')', ';',
-      'and', '(', 'n2', 'a', 'b', ')', ';',
-      'and', '(', 'n3', 'n1', 'ci', ')', ';',
-      'or', '#', '2', '(', 'co', 'n2', 'n3', ')', ';',
-       'specify',
-        'specparam', 'InputLoad$a', '=', '1.1', ';',
-        'specparam', 'InputLoad$b', '=', '2.2', ';',
-        'specparam', 'InputLoad$', '=', '3.3', ';',
-        'endspecify',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/read_delays_test.v.parsed.txt Deleted

@@ -1,87 +0,0 @@
-/**********************************************************************
- * $list_delays example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $list_delays PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-  reg  a, b, ci, clk;
-  wire sum, co;
-
-  addbit i1 (a, b, ci, sum, co);
-
-  initial
-    begin
-      #1 $read_delays(i1);
-      #1 $finish;
-    end
-endmodule
-
-/*** A gate level 1 bit adder model ***/
-`timescale 1ns / 1ns
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci, sum, co,
-        n1, n2, n3;
-
-  xor    (n1, a, b);
-  xor #2 (sum, n1, ci);
-  and    (n2, a, b);
-  and    (n3, n1, ci);
-  or  #2 (co, n2, n3);
-  
-  specify
-    (a *> sum) = (3, 5);
-    (b *> sum, co) = (1.3, 2.2);
-  endspecify
-
-endmodule
-/*********************************************************************/
-
-
-
-  'module', 'test', ';',
-     'reg', 'a', 'b', 'ci', 'clk', ';',
-      'wire', 'sum', 'co', ';',
-       'addbit',
-        'i1', '(', 'a', 'b', 'ci', 'sum', 'co', ')',
-        ';',
-       'initial',
-         'begin',
-           '#', '1', '$read_delays', '(', 'i1', ')', ';',
-            '#', '1', '$finish', ';',
-          'end',
-    'endmodule',
-    'module',
-      'addbit',
-      '(',
-      'a', 'b', 'ci', 'sum', 'co',
-      ')',
-      ';',
-     'input', 'a', 'b', 'ci', ';',
-      'output', 'sum', 'co', ';',
-      'wire', 'a', 'b', 'ci', 'sum', 'co', 'n1', 'n2', 'n3', ';',
-      'xor', '(', 'n1', 'a', 'b', ')', ';',
-      'xor', '#', '2', '(', 'sum', 'n1', 'ci', ')', ';',
-      'and', '(', 'n2', 'a', 'b', ')', ';',
-      'and', '(', 'n3', 'n1', 'ci', ')', ';',
-      'or', '#', '2', '(', 'co', 'n2', 'n3', ')', ';',
-       'specify',
-         '(', 'a', '*>', 'sum', ')',
-          '=',
-          '(', '3', '5', ')',
-          ';',
-         '(', 'b', '*>', 'sum', 'co', ')',
-          '=',
-          '(', '1.3', '2.2', ')',
-          ';',
-        'endspecify',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/read_stimulus_short_test.v.parsed.txt Deleted

@@ -1,163 +0,0 @@
-/**********************************************************************
- * $read_stimulus_short example -- Verilog test bench source code
- *
- * Verilog test bench to test the $read_stimulus_short PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-  reg   8:0 input_vector;
-  wire  3:0 a, b, sum;
-  wire        ci, co;
-
-  add4 i1 (a, b, ci, sum, co);
-
-  assign {ci, a, b} = input_vector;
-  
-  initial
-    begin
-      $timeformat(-9,0," ns",10);
-      $monitor("%t:  a=%b  b=%b  ci=%b  sum=%b  co=%b",
-               $time, a, b, ci, sum, co);
-      $read_stimulus_short("read_stimulus.pat", input_vector);
-      #500 $finish;
-    end
-endmodule
-
-/*** A netlist level 4-bit adder model ***/
-`timescale 1ns / 1ns
-module add4 (a, b, ci, sum, co);
-  input  3:0 a, b;
-  input        ci;
-  output 3:0 sum;
-  output       co;
-
-  wire   3:0 a, b, sum;
-  wire         ci, c0, c1, c2, co;
-
-  addbit u0 (a0, b0, ci, sum0, c0);
-  addbit u1 (a1, b1, c0, sum1, c1);
-  addbit u2 (a2, b2, c1, sum2, c2);
-  addbit u3 (a3, b3, c2, sum3, co);
-
-endmodule
-
-/*** A gate level 1-bit adder model ***/
-`timescale 1ns / 1ns
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci, sum, co,
-        n1, n2, n3;
-
-  xor    (n1, a, b);
-  xor #2 (sum, n1, ci);
-  and    (n2, a, b);
-  and    (n3, n1, ci);
-  or  #2 (co, n2, n3);
-endmodule
-/**********************************************************************/
-
-
-  'module', 'test', ';',
-     'reg', '', '8', ':', '0', '', 'input_vector', ';',
-      'wire', '', '3', ':', '0', '', 'a', 'b', 'sum', ';',
-      'wire', 'ci', 'co', ';',
-       'add4',
-        'i1', '(', 'a', 'b', 'ci', 'sum', 'co', ')',
-        ';',
-       'assign',
-        '{', 'ci', 'a', 'b', '}', '=', 'input_vector',
-        ';',
-       'initial',
-         'begin',
-           '$timeformat', '(', '-', '9', '0', '" ns"', '10', ')', ';',
-             '$monitor',
-              '(',
-              '"%t:  a=%b  b=%b  ci=%b  sum=%b  co=%b"',
-              '$time',
-              'a',
-              'b',
-              'ci',
-              'sum',
-              'co',
-              ')',
-              ';',
-             '$read_stimulus_short',
-              '(',
-              '"read_stimulus.pat"',
-              'input_vector',
-              ')',
-              ';',
-            '#', '500', '$finish', ';',
-          'end',
-    'endmodule',
-   'module', 'add4', '(', 'a', 'b', 'ci', 'sum', 'co', ')', ';',
-     'input', '', '3', ':', '0', '', 'a', 'b', ';',
-      'input', 'ci', ';',
-      'output', '', '3', ':', '0', '', 'sum', ';',
-      'output', 'co', ';',
-      'wire', '', '3', ':', '0', '', 'a', 'b', 'sum', ';',
-      'wire', 'ci', 'c0', 'c1', 'c2', 'co', ';',
-       'addbit',
-         'u0',
-           '(',
-            'a', '', '0', '',
-            'b', '', '0', '',
-            'ci',
-            'sum', '', '0', '',
-            'c0',
-            ')',
-        ';',
-       'addbit',
-         'u1',
-           '(',
-            'a', '', '1', '',
-            'b', '', '1', '',
-            'c0',
-            'sum', '', '1', '',
-            'c1',
-            ')',
-        ';',
-       'addbit',
-         'u2',
-           '(',
-            'a', '', '2', '',
-            'b', '', '2', '',
-            'c1',
-            'sum', '', '2', '',
-            'c2',
-            ')',
-        ';',
-       'addbit',
-         'u3',
-           '(',
-            'a', '', '3', '',
-            'b', '', '3', '',
-            'c2',
-            'sum', '', '3', '',
-            'co',
-            ')',
-        ';',
-    'endmodule',
-    'module',
-      'addbit',
-      '(',
-      'a', 'b', 'ci', 'sum', 'co',
-      ')',
-      ';',
-     'input', 'a', 'b', 'ci', ';',
-      'output', 'sum', 'co', ';',
-      'wire', 'a', 'b', 'ci', 'sum', 'co', 'n1', 'n2', 'n3', ';',
-      'xor', '(', 'n1', 'a', 'b', ')', ';',
-      'xor', '#', '2', '(', 'sum', 'n1', 'ci', ')', ';',
-      'and', '(', 'n2', 'a', 'b', ')', ';',
-      'and', '(', 'n3', 'n1', 'ci', ')', ';',
-      'or', '#', '2', '(', 'co', 'n2', 'n3', ')', ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/read_stimulus_test.v.parsed.txt Deleted

@@ -1,165 +0,0 @@
-/**********************************************************************
- * $read_stimulus_ba example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $read_stimulus_ba PLI application.
- * NOTE: this test uses a data file called "read_stimulus_test.pat",
- * which has several 9-bit binary test vector values (represented in 
- * ASCII) and the simulation time in which each value is to be applied.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-
-module test;
-  reg   8:0 input_vector;
-  wire  3:0 a, b, sum;
-  wire        ci, co;
-
-  add4 i1 (a, b, ci, sum, co);
-
-  assign {ci, a, b} = input_vector;
-  
-  initial
-    begin
-      $timeformat(-9,0," ns",10);
-      $monitor("%t:  a=%b  b=%b  ci=%b  sum=%b  co=%b",
-               $time, a, b, ci, sum, co);
-      $read_stimulus_ba("read_stimulus_test.pat", input_vector);
-    end
-endmodule
-
-/*** A netlist level 4-bit adder model ***/
-`timescale 1ns / 1ns
-module add4 (a, b, ci, sum, co);
-  input  3:0 a, b;
-  input        ci;
-  output 3:0 sum;
-  output       co;
-
-  wire   3:0 a, b, sum;
-  wire         ci, c0, c1, c2, co;
-
-  addbit u0 (a0, b0, ci, sum0, c0);
-  addbit u1 (a1, b1, c0, sum1, c1);
-  addbit u2 (a2, b2, c1, sum2, c2);
-  addbit u3 (a3, b3, c2, sum3, co);
-
-endmodule
-
-/*** A gate level 1-bit adder model ***/
-`timescale 1ns / 1ns
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci, sum, co,
-        n1, n2, n3;
-
-  xor    (n1, a, b);
-  xor #2 (sum, n1, ci);
-  and    (n2, a, b);
-  and    (n3, n1, ci);
-  or  #2 (co, n2, n3);
-endmodule
-/**********************************************************************/
-
-
-  'module', 'test', ';',
-     'reg', '', '8', ':', '0', '', 'input_vector', ';',
-      'wire', '', '3', ':', '0', '', 'a', 'b', 'sum', ';',
-      'wire', 'ci', 'co', ';',
-       'add4',
-        'i1', '(', 'a', 'b', 'ci', 'sum', 'co', ')',
-        ';',
-       'assign',
-        '{', 'ci', 'a', 'b', '}', '=', 'input_vector',
-        ';',
-       'initial',
-         'begin',
-           '$timeformat', '(', '-', '9', '0', '" ns"', '10', ')', ';',
-             '$monitor',
-              '(',
-              '"%t:  a=%b  b=%b  ci=%b  sum=%b  co=%b"',
-              '$time',
-              'a',
-              'b',
-              'ci',
-              'sum',
-              'co',
-              ')',
-              ';',
-             '$read_stimulus_ba',
-              '(',
-              '"read_stimulus_test.pat"',
-              'input_vector',
-              ')',
-              ';',
-          'end',
-    'endmodule',
-   'module', 'add4', '(', 'a', 'b', 'ci', 'sum', 'co', ')', ';',
-     'input', '', '3', ':', '0', '', 'a', 'b', ';',
-      'input', 'ci', ';',
-      'output', '', '3', ':', '0', '', 'sum', ';',
-      'output', 'co', ';',
-      'wire', '', '3', ':', '0', '', 'a', 'b', 'sum', ';',
-      'wire', 'ci', 'c0', 'c1', 'c2', 'co', ';',
-       'addbit',
-         'u0',
-           '(',
-            'a', '', '0', '',
-            'b', '', '0', '',
-            'ci',
-            'sum', '', '0', '',
-            'c0',
-            ')',
-        ';',
-       'addbit',
-         'u1',
-           '(',
-            'a', '', '1', '',
-            'b', '', '1', '',
-            'c0',
-            'sum', '', '1', '',
-            'c1',
-            ')',
-        ';',
-       'addbit',
-         'u2',
-           '(',
-            'a', '', '2', '',
-            'b', '', '2', '',
-            'c1',
-            'sum', '', '2', '',
-            'c2',
-            ')',
-        ';',
-       'addbit',
-         'u3',
-           '(',
-            'a', '', '3', '',
-            'b', '', '3', '',
-            'c2',
-            'sum', '', '3', '',
-            'co',
-            ')',
-        ';',
-    'endmodule',
-    'module',
-      'addbit',
-      '(',
-      'a', 'b', 'ci', 'sum', 'co',
-      ')',
-      ';',
-     'input', 'a', 'b', 'ci', ';',
-      'output', 'sum', 'co', ';',
-      'wire', 'a', 'b', 'ci', 'sum', 'co', 'n1', 'n2', 'n3', ';',
-      'xor', '(', 'n1', 'a', 'b', ')', ';',
-      'xor', '#', '2', '(', 'sum', 'n1', 'ci', ')', ';',
-      'and', '(', 'n2', 'a', 'b', ')', ';',
-      'and', '(', 'n3', 'n1', 'ci', ')', ';',
-      'or', '#', '2', '(', 'co', 'n2', 'n3', ')', ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/read_strengthval_test.v.parsed.txt Deleted

@@ -1,75 +0,0 @@
-/**********************************************************************
- * $read_strengthval example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $read_strengthval PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-  wire a = 1'b0;
-  wire b = 1'b1;
-  wire c = 1'bz;
-  wire d = 1'bx;
-  wire e;
-  assign (pull0, pull1) e = 1'b1;  /* wired logic on e */
-  assign (pull1, pull0) e = 1'b0;
-  
-  wire f;
-  bufif1 (f, 1'b0, 1'bx); /* ambiguous output 'L' */
-  
-  wire g;
-  notif1 (g, 1'b0, 1'bx); /* ambiguous output 'H' */
-  
-  initial
-    begin
-      #1 
-      $read_strengthval(a);
-      $read_strengthval(b);
-      $read_strengthval(c);
-      $read_strengthval(d);
-      $read_strengthval(e);
-      $read_strengthval(f);
-      $read_strengthval(g);
-      #1 $finish;
-    end
-endmodule
-
-/*********************************************************************/
-
-
-
-  'module', 'test', ';',
-     'wire', 'a', '=', "1 'b 0", ';',
-      'wire', 'b', '=', "1 'b 1", ';',
-      'wire', 'c', '=', "1 'b z", ';',
-      'wire', 'd', '=', "1 'b x", ';',
-      'wire', 'e', ';',
-       'assign',
-        '(', 'pull0', ',', 'pull1', ')',
-        'e', '=', "1 'b 1",
-        ';',
-       'assign',
-        '(', 'pull1', ',', 'pull0', ')',
-        'e', '=', "1 'b 0",
-        ';',
-      'wire', 'f', ';',
-      'bufif1', '(', 'f', "1 'b 0", "1 'b x", ')', ';',
-      'wire', 'g', ';',
-      'notif1', '(', 'g', "1 'b 0", "1 'b x", ')', ';',
-       'initial',
-         'begin',
-           '#', '1', '$read_strengthval', '(', 'a', ')', ';',
-            '$read_strengthval', '(', 'b', ')', ';',
-            '$read_strengthval', '(', 'c', ')', ';',
-            '$read_strengthval', '(', 'd', ')', ';',
-            '$read_strengthval', '(', 'e', ')', ';',
-            '$read_strengthval', '(', 'f', ')', ';',
-            '$read_strengthval', '(', 'g', ')', ';',
-            '#', '1', '$finish', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/read_test_vector_test.v.parsed.txt Deleted

@@ -1,71 +0,0 @@
-/**********************************************************************
- * $read_test_vector example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $read_test_vector PLI application.
- * NOTE: this test uses two data file, "read_vector_test1.pat" and
- * "read_vector_test2.pat".  Each file has several 8-bit binary test
- * vector values (represented in ASCII).
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-
-  reg 7:0 vector;
-  reg       clk;
-
-  initial
-    begin
-      $monitor("at %d: clk = %b  vector = %b", $stime, clk, vector);
-      clk = 0;
-      forever #10 clk = ~clk;
-    end
-
-  always @(posedge clk)
-    $read_test_vector("read_vector_test1.pat", vector);
- 
-  always @(negedge clk)
-    $read_test_vector("read_vector_test2.pat", vector);
- 
- endmodule
-/**********************************************************************/
-
-
-
-  'module', 'test', ';',
-     'reg', '', '7', ':', '0', '', 'vector', ';',
-      'reg', 'clk', ';',
-       'initial',
-         'begin',
-            '$monitor',
-              '(',
-              '"at %d: clk = %b  vector = %b"',
-              '$stime',
-              'clk',
-              'vector',
-              ')',
-              ';',
-            'clk', '=', '0', ';',
-            'forever', '#', '10', 'clk', '=', '~', 'clk', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'clk', ')',
-         '$read_test_vector',
-          '(',
-          '"read_vector_test1.pat"',
-          'vector',
-          ')',
-          ';',
-       'always',
-        '@', '(', 'negedge', 'clk', ')',
-         '$read_test_vector',
-          '(',
-          '"read_vector_test2.pat"',
-          'vector',
-          ')',
-          ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/read_timeval_test.v.parsed.txt Deleted

@@ -1,40 +0,0 @@
-/**********************************************************************
- * $read_timeval example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $read_timeval PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-  time T;
-  
-  initial
-    begin
-      T = 0;
-      T1 = 1;
-      T32 = 1;
-      #1 $read_timeval(T);
-      #1 $finish;
-    end
-endmodule
-
-/*********************************************************************/
-
-
-
-  'module', 'test', ';',
-     'time', 'T', ';',
-       'initial',
-         'begin',
-           'T', '=', '0', ';',
-            'T', '', '1', '', '=', '1', ';',
-            'T', '', '32', '', '=', '1', ';',
-            '#', '1', '$read_timeval', '(', 'T', ')', ';',
-            '#', '1', '$finish', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/read_vector_test.v.parsed.txt Deleted

@@ -1,71 +0,0 @@
-/**********************************************************************
- * $read_test_vector example -- Verilog test bench source code
- *
- * Verilog test bench to test the $read_test_vector PLI application.
- * NOTE: this test uses two data file, "read_vector_test1.pat" and
- * "read_vector_test2.pat".  Each file has several 8-bit binary values
- * (represented in ASCII).
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-
-  reg 7:0 vector;
-  reg       clk;
-
-  initial
-    begin
-      $monitor("at %d: clk = %b  vector = %b", $stime, clk, vector);
-      clk = 0;
-      forever #10 clk = ~clk;
-    end
-
-  always @(posedge clk)
-    $read_test_vector("read_vector_test1.pat", vector);
- 
-  always @(negedge clk)
-    $read_test_vector("read_vector_test2.pat", vector);
- 
- endmodule
-/**********************************************************************/
-
-
-
-  'module', 'test', ';',
-     'reg', '', '7', ':', '0', '', 'vector', ';',
-      'reg', 'clk', ';',
-       'initial',
-         'begin',
-            '$monitor',
-              '(',
-              '"at %d: clk = %b  vector = %b"',
-              '$stime',
-              'clk',
-              'vector',
-              ')',
-              ';',
-            'clk', '=', '0', ';',
-            'forever', '#', '10', 'clk', '=', '~', 'clk', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'clk', ')',
-         '$read_test_vector',
-          '(',
-          '"read_vector_test1.pat"',
-          'vector',
-          ')',
-          ';',
-       'always',
-        '@', '(', 'negedge', 'clk', ')',
-         '$read_test_vector',
-          '(',
-          '"read_vector_test2.pat"',
-          'vector',
-          ')',
-          ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/read_vecval_test.v.parsed.txt Deleted

@@ -1,42 +0,0 @@
-/**********************************************************************
- * $read_vecval example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $read_vecval PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-  reg 39:0 data;
-
-  initial
-    begin
-      data     = 40'b0;
-      data0  = 1'b1;
-      data16 = 1'bz;
-      data39 = 1'bx;
-      #1 $read_vecval(data);
-      #1 $finish;
-    end
-endmodule
-
-/*********************************************************************/
-
-
-
-  'module', 'test', ';',
-     'reg', '', '39', ':', '0', '', 'data', ';',
-       'initial',
-         'begin',
-           'data', '=', "40 'b 0", ';',
-            'data', '', '0', '', '=', "1 'b 1", ';',
-            'data', '', '16', '', '=', "1 'b z", ';',
-            'data', '', '39', '', '=', "1 'b x", ';',
-            '#', '1', '$read_vecval', '(', 'data', ')', ';',
-            '#', '1', '$finish', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/realpow_test.v.parsed.txt Deleted

@@ -1,68 +0,0 @@
-/**********************************************************************
- * $realpow example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $realpow PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-  integer i;
-  real    m, n;
-
-  initial
-    begin
-      i = 0;
-      m = 1.5;
-      n = 0.5;
-      #1 $display("$realpow(1.5, 3) returns %2.2f",
-                   $realpow(1.5, 3));
-      #1 $display("$realpow(4.0, n) returns %2.2f (n=%2.2f)",
-                   $realpow(4.0, n), n);
-      #1 $display("$realpow(m, i)   returns %2.2f (m=%2.2f i=%0d)",
-                   $realpow(m, i), m, i);
-    end
-
-endmodule
-
-/*********************************************************************/
-
-
-  'module', 'test', ';',
-     'integer', 'i', ';',
-      'real', 'm', 'n', ';',
-       'initial',
-         'begin',
-           'i', '=', '0', ';',
-            'm', '=', '1.5', ';',
-            'n', '=', '0.5', ';',
-             '#', '1',
-               '$display',
-                '(',
-                '"$realpow(1.5, 3) returns %2.2f"',
-                '$realpow', '(', '1.5', '3', ')',
-                ')',
-                ';',
-             '#', '1',
-               '$display',
-                '(',
-                '"$realpow(4.0, n) returns %2.2f (n=%2.2f)"',
-                '$realpow', '(', '4.0', 'n', ')',
-                'n',
-                ')',
-                ';',
-             '#', '1',
-               '$display',
-                '(',
-                '"$realpow(m, i)   returns %2.2f (m=%2.2f i=%0d)"',
-                '$realpow', '(', 'm', 'i', ')',
-                'm',
-                'i',
-                ')',
-                ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/rf.v.parsed.txt Deleted

@@ -1,2774 +0,0 @@
-/////////////////////////////////////////////////////////////////////
-////                                                             ////
-////  Register File                                              ////
-////  This module contains all top level registers and           ////
-////  instantiates the register files for endpoints              ////
-////                                                             ////
-////  Author: Rudolf Usselmann                                   ////
-////          rudi@asics.ws                                      ////
-////                                                             ////
-////                                                             ////
-////  Downloaded from: http://www.opencores.org/cores/usb/       ////
-////                                                             ////
-/////////////////////////////////////////////////////////////////////
-////                                                             ////
-//// Copyright (C) 2000 Rudolf Usselmann                         ////
-////                    rudi@asics.ws                            ////
-////                                                             ////
-//// This source file may be used and distributed without        ////
-//// restriction provided that this copyright statement is not   ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer.////
-////                                                             ////
-////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
-//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
-//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
-//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
-//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
-//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
-//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
-//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
-//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
-//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
-//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
-//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
-//// POSSIBILITY OF SUCH DAMAGE.                                 ////
-////                                                             ////
-/////////////////////////////////////////////////////////////////////
-
-//  CVS Log
-//
-//  $Id: rf.v,v 1.0 2001/03/07 09:17:12 rudi Exp $
-//
-//  $Date: 2001/03/07 09:17:12 $
-//  $Revision: 1.0 $
-//  $Author: rudi $
-//  $Locker:  $
-//  $State: Exp $
-//
-// Change History:
-//               $Log: rf.v,v $
-//               Revision 1.0  2001/03/07 09:17:12  rudi
-//
-//
-//               Changed all revisions to revision 1.0. This is because OpenCores CVS
-//               interface could not handle the original '0.1' revision ....
-//
-//               Revision 0.2  2001/03/07 09:08:13  rudi
-//
-//               Added USB controll signaling (Line Status) block. Fixed some minor
-//               typos, added resume bit and signal.
-//
-//               Revision 0.1.0.1  2001/02/28 08:11:32  rudi
-//               Initial Release
-//
-//
-
-`include "usb_defines.v"
-
-// Endpoint register File
-module rf(  clk, wclk, rst,
-
-        // Wishbone Interface
-        adr, re, we, din, dout, inta, intb,
-        dma_req, dma_ack,
-
-        // Internal Interface
-        idin,
-        ep_sel, match,
-        buf0_rl, buf0_set, buf1_set,
-        uc_bsel_set, uc_dpd_set,
-
-        int_buf1_set, int_buf0_set, int_upid_set,
-        int_crc16_set, int_to_set, int_seqerr_set,
-
-        csr, buf0, buf1,
-        funct_adr,
-        dma_in_buf_sz1, dma_out_buf_avail,
-
-        // Misc
-        frm_nat,
-        
-        // UTMI Interface
-        utmi_vend_stat, utmi_vend_ctrl, utmi_vend_wr,
-        
-        line_stat, usb_attached, mode_hs, suspend,
-        attached, usb_reset, pid_cs_err, nse_err,
-        crc5_err, rx_err, rf_resume_req
-        );
-
-input       clk, wclk, rst;
-input   6:0   adr;
-input       re;
-input       we;
-input   31:0  din;
-output  31:0  dout;
-output      inta, intb;
-output  14:0  dma_req;
-input   14:0  dma_ack;
-
-input   31:0  idin;       // Data Input
-input   3:0   ep_sel;     // Endpoint Number Input
-output      match;      // Endpoint Matched
-input       buf0_rl;    // Reload Buf 0 with original values
-
-input       buf0_set;   // Write to buf 0
-input       buf1_set;   // Write to buf 1
-input       uc_bsel_set;    // Write to the uc_bsel field
-input       uc_dpd_set; // Write to the uc_dpd field
-input       int_buf1_set;   // Set buf1 full/empty interrupt
-input       int_buf0_set;   // Set buf0 full/empty interrupt
-input       int_upid_set;   // Set unsupported PID interrupt
-input       int_crc16_set;  // Set CRC16 error interrupt
-input       int_to_set; // Set time out interrupt
-input       int_seqerr_set; // Set PID Sequence Error Interrupt
-
-output  31:0  csr;        // Internal CSR Output
-output  31:0  buf0;       // Internal Buf 0 Output
-output  31:0  buf1;       // Internal Buf 1 Output
-output  6:0   funct_adr;  // Function Address
-output      dma_in_buf_sz1, dma_out_buf_avail;
-
-input   31:0  frm_nat;
-
-input   7:0   utmi_vend_stat; // UTMI Vendor C/S bus
-output  3:0   utmi_vend_ctrl;
-output      utmi_vend_wr;
-
-input   1:0   line_stat;  // Below are signals for interrupt generation
-input       usb_attached;
-input       mode_hs;
-input       suspend;
-input       attached;
-input       usb_reset;
-input       nse_err;
-input       pid_cs_err;
-input       crc5_err;
-input       rx_err;
-output      rf_resume_req;
-
-///////////////////////////////////////////////////////////////////
-//
-// Local Wires and Registers
-//
-
-wire    31:0  ep0_dout, ep1_dout, ep2_dout, ep3_dout;
-wire    31:0  ep4_dout, ep5_dout, ep6_dout, ep7_dout;
-wire    31:0  ep8_dout, ep9_dout, ep10_dout, ep11_dout;
-wire    31:0  ep12_dout, ep13_dout, ep14_dout, ep15_dout;
-
-wire        ep0_re, ep1_re, ep2_re, ep3_re;
-wire        ep4_re, ep5_re, ep6_re, ep7_re;
-wire        ep8_re, ep9_re, ep10_re, ep11_re;
-wire        ep12_re, ep13_re, ep14_re, ep15_re;
-
-wire        ep0_we, ep1_we, ep2_we, ep3_we;
-wire        ep4_we, ep5_we, ep6_we, ep7_we;
-wire        ep8_we, ep9_we, ep10_we, ep11_we;
-wire        ep12_we, ep13_we, ep14_we, ep15_we;
-
-wire        ep0_inta, ep1_inta, ep2_inta, ep3_inta;
-wire        ep4_inta, ep5_inta, ep6_inta, ep7_inta;
-wire        ep8_inta, ep9_inta, ep10_inta, ep11_inta;
-wire        ep12_inta, ep13_inta, ep14_inta, ep15_inta;
-
-wire        ep0_intb, ep1_intb, ep2_intb, ep3_intb;
-wire        ep4_intb, ep5_intb, ep6_intb, ep7_intb;
-wire        ep8_intb, ep9_intb, ep10_intb, ep11_intb;
-wire        ep12_intb, ep13_intb, ep14_intb, ep15_intb;
-
-wire        ep0_match, ep1_match, ep2_match, ep3_match;
-wire        ep4_match, ep5_match, ep6_match, ep7_match;
-wire        ep8_match, ep9_match, ep10_match, ep11_match;
-wire        ep12_match, ep13_match, ep14_match, ep15_match;
-
-wire    31:0  ep0_csr, ep1_csr, ep2_csr, ep3_csr;
-wire    31:0  ep4_csr, ep5_csr, ep6_csr, ep7_csr;
-wire    31:0  ep8_csr, ep9_csr, ep10_csr, ep11_csr;
-wire    31:0  ep12_csr, ep13_csr, ep14_csr, ep15_csr;
-
-wire    31:0  ep0_buf0, ep1_buf0, ep2_buf0, ep3_buf0;
-wire    31:0  ep4_buf0, ep5_buf0, ep6_buf0, ep7_buf0;
-wire    31:0  ep8_buf0, ep9_buf0, ep10_buf0, ep11_buf0;
-wire    31:0  ep12_buf0, ep13_buf0, ep14_buf0, ep15_buf0;
-
-wire    31:0  ep0_buf1, ep1_buf1, ep2_buf1, ep3_buf1;
-wire    31:0  ep4_buf1, ep5_buf1, ep6_buf1, ep7_buf1;
-wire    31:0  ep8_buf1, ep9_buf1, ep10_buf1, ep11_buf1;
-wire    31:0  ep12_buf1, ep13_buf1, ep14_buf1, ep15_buf1;
-
-wire        ep0_dma_in_buf_sz1, ep1_dma_in_buf_sz1;
-wire        ep2_dma_in_buf_sz1, ep3_dma_in_buf_sz1;
-wire        ep4_dma_in_buf_sz1, ep5_dma_in_buf_sz1;
-wire        ep6_dma_in_buf_sz1, ep7_dma_in_buf_sz1;
-wire        ep8_dma_in_buf_sz1, ep9_dma_in_buf_sz1;
-wire        ep10_dma_in_buf_sz1, ep11_dma_in_buf_sz1;
-wire        ep12_dma_in_buf_sz1, ep13_dma_in_buf_sz1;
-wire        ep14_dma_in_buf_sz1, ep15_dma_in_buf_sz1;
-
-wire        ep0_dma_out_buf_avail, ep1_dma_out_buf_avail;
-wire        ep2_dma_out_buf_avail, ep3_dma_out_buf_avail;
-wire        ep4_dma_out_buf_avail, ep5_dma_out_buf_avail;
-wire        ep6_dma_out_buf_avail, ep7_dma_out_buf_avail;
-wire        ep8_dma_out_buf_avail, ep9_dma_out_buf_avail;
-wire        ep10_dma_out_buf_avail, ep11_dma_out_buf_avail;
-wire        ep12_dma_out_buf_avail, ep13_dma_out_buf_avail;
-wire        ep14_dma_out_buf_avail, ep15_dma_out_buf_avail;
-
-reg     dma_in_buf_sz1;
-reg     dma_out_buf_avail;
-
-reg 31:0  dtmp;
-reg 31:0  dout;
-
-wire    31:0  main_csr;
-reg 6:0   funct_adr;
-reg 8:0   intb_msk, inta_msk;
-
-reg     match_r1, match_r2;
-reg 31:0  csr;
-reg 31:0  buf0;
-reg 31:0  buf1;
-
-reg 3:0   utmi_vend_ctrl;
-reg     utmi_vend_wr;
-reg 7:0   utmi_vend_stat_r;
-
-reg     int_src_re;
-reg 8:0   int_srcb;
-reg 15:0  int_srca;
-reg     attach_r, attach_r1;
-wire        attach, deattach;
-reg     suspend_r, suspend_r1;
-wire        suspend_start, suspend_end;
-reg     usb_reset_r;
-reg     rx_err_r;
-reg     nse_err_r;
-reg     pid_cs_err_r;
-reg     crc5_err_r;
-
-reg     rf_resume_req_r, rf_resume_req;
-
-///////////////////////////////////////////////////////////////////
-//
-// WISHBONE Access
-//
-
-// Main CSR Alias
-assign main_csr = {28'h0, line_stat, usb_attached, mode_hs, suspend};
-
-// Read Registers Logic
-always @(adr or main_csr or funct_adr or inta_msk or intb_msk or int_srca
-    or int_srcb or frm_nat or utmi_vend_stat_r)
-    case(adr2:0)      // synopsys full_case parallel_case
-       0: dtmp = main_csr;
-       1: dtmp = { 25'h0, funct_adr};
-       2: dtmp = {7'h0, intb_msk, 7'h0, inta_msk};
-       3: dtmp = {3'h0, int_srcb, 4'h0, int_srca};
-       4: dtmp = frm_nat;
-       5: dtmp = {24'h0, utmi_vend_stat_r};
-    endcase
-
-// Interrupt Source Read Register
-always @(posedge wclk)
-    int_src_re <= #1 adr6:0 == 3 & re;
-
-// UTMI Vendor Control Stuff
-always @(posedge wclk)
-    utmi_vend_stat_r <= #1 utmi_vend_stat;
-
-always @(posedge wclk)
-    utmi_vend_wr <= #1 adr6:0 == 5 & we;
-
-always @(posedge wclk)
-    if(adr6:0 == 5 & we)  utmi_vend_ctrl <= #1 din3:0;
-
-// Resume Request
-always @(posedge wclk)
-    if(!rst)        rf_resume_req_r <= #1 0;
-    else
-    if(adr6:0 == 0 & we)  rf_resume_req_r <= #1 din5;
-    else
-    if(rf_resume_req)   rf_resume_req_r <= #1 0;
-
-always @(posedge clk)
-    rf_resume_req <= #1 rf_resume_req_r;
-
-// Function Address Register
-always @(posedge wclk)
-    if(!rst)        funct_adr <= #1 0;
-    else
-    if(adr6:0 == 1 & we)  funct_adr <= #1 din6:0;
-
-// Interrup Mask Register
-always @(posedge wclk)
-    if(!rst)
-       begin
-        inta_msk <= #1 0;
-        intb_msk <= #1 0;
-       end
-    else
-    if(adr6:0 == 2 & we)
-       begin
-        intb_msk <= #1 din24:16;
-        inta_msk <= #1 din08:00;
-       end
-
-always @(posedge wclk)
-    case(adr6:2)      // synopsys full_case parallel_case
-       0: dout <= #1 dtmp;  // Addr: 0h
-       1: dout <= #1 dtmp;
-       2: dout <= #1 32'h0;
-       3: dout <= #1 32'h0;
-       4: dout <= #1 ep0_dout;  // Addr: 010h
-       5: dout <= #1 ep1_dout;
-       6: dout <= #1 ep2_dout;
-       7: dout <= #1 ep3_dout;
-       8: dout <= #1 ep4_dout;  // Addr: 020h
-       9: dout <= #1 ep5_dout;
-      10: dout <= #1 ep6_dout;
-      11: dout <= #1 ep7_dout;
-      12: dout <= #1 ep8_dout;  // Addr: 030h
-      13: dout <= #1 ep9_dout;
-      14: dout <= #1 ep10_dout;
-      15: dout <= #1 ep11_dout;
-      16: dout <= #1 ep12_dout;
-      17: dout <= #1 ep13_dout;
-      18: dout <= #1 ep14_dout;
-      19: dout <= #1 ep15_dout; // Addr: 04ch
-    endcase
-
-assign ep0_re  = (adr6:2 ==  4) & re;
-assign ep1_re  = (adr6:2 ==  5) & re;
-assign ep2_re  = (adr6:2 ==  6) & re;
-assign ep3_re  = (adr6:2 ==  7) & re;
-assign ep4_re  = (adr6:2 ==  8) & re;
-assign ep5_re  = (adr6:2 ==  9) & re;
-assign ep6_re  = (adr6:2 == 10) & re;
-assign ep7_re  = (adr6:2 == 11) & re;
-assign ep8_re  = (adr6:2 == 12) & re;
-assign ep9_re  = (adr6:2 == 13) & re;
-assign ep10_re = (adr6:2 == 14) & re;
-assign ep11_re = (adr6:2 == 15) & re;
-assign ep12_re = (adr6:2 == 16) & re;
-assign ep13_re = (adr6:2 == 17) & re;
-assign ep14_re = (adr6:2 == 18) & re;
-assign ep15_re = (adr6:2 == 19) & re;
-
-assign ep0_we  = (adr6:2 ==  4) & we;
-assign ep1_we  = (adr6:2 ==  5) & we;
-assign ep2_we  = (adr6:2 ==  6) & we;
-assign ep3_we  = (adr6:2 ==  7) & we;
-assign ep4_we  = (adr6:2 ==  8) & we;
-assign ep5_we  = (adr6:2 ==  9) & we;
-assign ep6_we  = (adr6:2 == 10) & we;
-assign ep7_we  = (adr6:2 == 11) & we;
-assign ep8_we  = (adr6:2 == 12) & we;
-assign ep9_we  = (adr6:2 == 13) & we;
-assign ep10_we = (adr6:2 == 14) & we;
-assign ep11_we = (adr6:2 == 15) & we;
-assign ep12_we = (adr6:2 == 16) & we;
-assign ep13_we = (adr6:2 == 17) & we;
-assign ep14_we = (adr6:2 == 18) & we;
-assign ep15_we = (adr6:2 == 19) & we;
-
-///////////////////////////////////////////////////////////////////
-//
-// Internal Access
-//
-
-assign match = match_r1;
-
-always @(posedge clk)
-    match_r2 <= #1 match_r1;
-
-always @(posedge clk)
-    match_r1 <= #1  ep0_match | ep1_match | ep2_match | ep3_match |
-            ep4_match | ep5_match | ep6_match | ep7_match |
-            ep8_match | ep9_match | ep10_match | ep11_match |
-            ep12_match | ep13_match | ep14_match | ep15_match;
-
-always @(posedge clk)
-    if(ep0_match)   csr <= #1 ep0_csr;
-    else
-    if(ep1_match)   csr <= #1 ep1_csr;
-    else
-    if(ep2_match)   csr <= #1 ep2_csr;
-    else
-    if(ep3_match)   csr <= #1 ep3_csr;
-    else
-    if(ep4_match)   csr <= #1 ep4_csr;
-    else
-    if(ep5_match)   csr <= #1 ep5_csr;
-    else
-    if(ep6_match)   csr <= #1 ep6_csr;
-    else
-    if(ep7_match)   csr <= #1 ep7_csr;
-    else
-    if(ep8_match)   csr <= #1 ep8_csr;
-    else
-    if(ep9_match)   csr <= #1 ep9_csr;
-    else
-    if(ep10_match)  csr <= #1 ep10_csr;
-    else
-    if(ep11_match)  csr <= #1 ep11_csr;
-    else
-    if(ep12_match)  csr <= #1 ep12_csr;
-    else
-    if(ep13_match)  csr <= #1 ep13_csr;
-    else
-    if(ep14_match)  csr <= #1 ep14_csr;
-    else
-    if(ep15_match)  csr <= #1 ep15_csr;
-
-always @(posedge clk)
-    if(ep0_match)   buf0 <= #1 ep0_buf0;
-    else
-    if(ep1_match)   buf0 <= #1 ep1_buf0;
-    else
-    if(ep2_match)   buf0 <= #1 ep2_buf0;
-    else
-    if(ep3_match)   buf0 <= #1 ep3_buf0;
-    else
-    if(ep4_match)   buf0 <= #1 ep4_buf0;
-    else
-    if(ep5_match)   buf0 <= #1 ep5_buf0;
-    else
-    if(ep6_match)   buf0 <= #1 ep6_buf0;
-    else
-    if(ep7_match)   buf0 <= #1 ep7_buf0;
-    else
-    if(ep8_match)   buf0 <= #1 ep8_buf0;
-    else
-    if(ep9_match)   buf0 <= #1 ep9_buf0;
-    else
-    if(ep10_match)  buf0 <= #1 ep10_buf0;
-    else
-    if(ep11_match)  buf0 <= #1 ep11_buf0;
-    else
-    if(ep12_match)  buf0 <= #1 ep12_buf0;
-    else
-    if(ep13_match)  buf0 <= #1 ep13_buf0;
-    else
-    if(ep14_match)  buf0 <= #1 ep14_buf0;
-    else
-    if(ep15_match)  buf0 <= #1 ep15_buf0;
-
-always @(posedge clk)
-    if(ep0_match)   buf1 <= #1 ep0_buf1;
-    else
-    if(ep1_match)   buf1 <= #1 ep1_buf1;
-    else
-    if(ep2_match)   buf1 <= #1 ep2_buf1;
-    else
-    if(ep3_match)   buf1 <= #1 ep3_buf1;
-    else
-    if(ep4_match)   buf1 <= #1 ep4_buf1;
-    else
-    if(ep5_match)   buf1 <= #1 ep5_buf1;
-    else
-    if(ep6_match)   buf1 <= #1 ep6_buf1;
-    else
-    if(ep7_match)   buf1 <= #1 ep7_buf1;
-    else
-    if(ep8_match)   buf1 <= #1 ep8_buf1;
-    else
-    if(ep9_match)   buf1 <= #1 ep9_buf1;
-    else
-    if(ep10_match)  buf1 <= #1 ep10_buf1;
-    else
-    if(ep11_match)  buf1 <= #1 ep11_buf1;
-    else
-    if(ep12_match)  buf1 <= #1 ep12_buf1;
-    else
-    if(ep13_match)  buf1 <= #1 ep13_buf1;
-    else
-    if(ep14_match)  buf1 <= #1 ep14_buf1;
-    else
-    if(ep15_match)  buf1 <= #1 ep15_buf1;
-
-always @(posedge clk)
-    if(ep0_match)   dma_in_buf_sz1 <= #1 ep0_dma_in_buf_sz1;
-    else
-    if(ep1_match)   dma_in_buf_sz1 <= #1 ep1_dma_in_buf_sz1;
-    else
-    if(ep2_match)   dma_in_buf_sz1 <= #1 ep2_dma_in_buf_sz1;
-    else
-    if(ep3_match)   dma_in_buf_sz1 <= #1 ep3_dma_in_buf_sz1;
-    else
-    if(ep4_match)   dma_in_buf_sz1 <= #1 ep4_dma_in_buf_sz1;
-    else
-    if(ep5_match)   dma_in_buf_sz1 <= #1 ep5_dma_in_buf_sz1;
-    else
-    if(ep6_match)   dma_in_buf_sz1 <= #1 ep6_dma_in_buf_sz1;
-    else
-    if(ep7_match)   dma_in_buf_sz1 <= #1 ep7_dma_in_buf_sz1;
-    else
-    if(ep8_match)   dma_in_buf_sz1 <= #1 ep8_dma_in_buf_sz1;
-    else
-    if(ep9_match)   dma_in_buf_sz1 <= #1 ep9_dma_in_buf_sz1;
-    else
-    if(ep10_match)  dma_in_buf_sz1 <= #1 ep10_dma_in_buf_sz1;
-    else
-    if(ep11_match)  dma_in_buf_sz1 <= #1 ep11_dma_in_buf_sz1;
-    else
-    if(ep12_match)  dma_in_buf_sz1 <= #1 ep12_dma_in_buf_sz1;
-    else
-    if(ep13_match)  dma_in_buf_sz1 <= #1 ep13_dma_in_buf_sz1;
-    else
-    if(ep14_match)  dma_in_buf_sz1 <= #1 ep14_dma_in_buf_sz1;
-    else
-    if(ep15_match)  dma_in_buf_sz1 <= #1 ep15_dma_in_buf_sz1;
-
-always @(posedge clk)
-    if(ep0_match)   dma_out_buf_avail <= #1 ep0_dma_out_buf_avail;
-    else
-    if(ep1_match)   dma_out_buf_avail <= #1 ep1_dma_out_buf_avail;
-    else
-    if(ep2_match)   dma_out_buf_avail <= #1 ep2_dma_out_buf_avail;
-    else
-    if(ep3_match)   dma_out_buf_avail <= #1 ep3_dma_out_buf_avail;
-    else
-    if(ep4_match)   dma_out_buf_avail <= #1 ep4_dma_out_buf_avail;
-    else
-    if(ep5_match)   dma_out_buf_avail <= #1 ep5_dma_out_buf_avail;
-    else
-    if(ep6_match)   dma_out_buf_avail <= #1 ep6_dma_out_buf_avail;
-    else
-    if(ep7_match)   dma_out_buf_avail <= #1 ep7_dma_out_buf_avail;
-    else
-    if(ep8_match)   dma_out_buf_avail <= #1 ep8_dma_out_buf_avail;
-    else
-    if(ep9_match)   dma_out_buf_avail <= #1 ep9_dma_out_buf_avail;
-    else
-    if(ep10_match)  dma_out_buf_avail <= #1 ep10_dma_out_buf_avail;
-    else
-    if(ep11_match)  dma_out_buf_avail <= #1 ep11_dma_out_buf_avail;
-    else
-    if(ep12_match)  dma_out_buf_avail <= #1 ep12_dma_out_buf_avail;
-    else
-    if(ep13_match)  dma_out_buf_avail <= #1 ep13_dma_out_buf_avail;
-    else
-    if(ep14_match)  dma_out_buf_avail <= #1 ep14_dma_out_buf_avail;
-    else
-    if(ep15_match)  dma_out_buf_avail <= #1 ep15_dma_out_buf_avail;
-
-
-///////////////////////////////////////////////////////////////////
-//
-// Interrupt Generation
-//
-
-always @(posedge wclk)
-    attach_r <= usb_attached;
-
-always @(posedge wclk)
-    attach_r1 <= attach_r;
-
-always @(posedge wclk)
-    suspend_r <= suspend;
-
-always @(posedge wclk)
-    suspend_r1 <= suspend_r;
-
-always @(posedge wclk)
-    usb_reset_r <= #1 usb_reset;
-
-always @(posedge wclk)
-    rx_err_r <= #1 rx_err;
-
-always @(posedge wclk)
-    nse_err_r <= #1 nse_err;
-
-always @(posedge wclk)
-    pid_cs_err_r <= #1 pid_cs_err;
-
-always @(posedge wclk)
-    crc5_err_r <= #1 crc5_err;
-
-assign  attach = !attach_r1 & attach_r;
-assign  deattach = attach_r1 & !attach_r;
-assign  suspend_start = !suspend_r1 & suspend_r;
-assign  suspend_end   = suspend_r1 & !suspend_r;
-
-always @(posedge wclk)
-    if(!rst | int_src_re)   int_srcb8 <= #1 0;
-    else
-    if(usb_reset_r)     int_srcb8 <= #1 1;
-
-always @(posedge wclk)
-    if(!rst | int_src_re)   int_srcb7 <= #1 0;
-    else
-    if(rx_err_r)        int_srcb7 <= #1 1;
-
-always @(posedge wclk)
-    if(!rst | int_src_re)   int_srcb6 <= #1 0;
-    else
-    if(deattach)        int_srcb6 <= #1 1;
-
-always @(posedge wclk)
-    if(!rst | int_src_re)   int_srcb5 <= #1 0;
-    else
-    if(attach)      int_srcb5 <= #1 1;
-
-always @(posedge wclk)
-    if(!rst | int_src_re)   int_srcb4 <= #1 0;
-    else
-    if(suspend_end)     int_srcb4 <= #1 1;
-
-always @(posedge wclk)
-    if(!rst | int_src_re)   int_srcb3 <= #1 0;
-    else
-    if(suspend_start)   int_srcb3 <= #1 1;
-
-always @(posedge wclk)
-    if(!rst | int_src_re)   int_srcb2 <= #1 0;
-    else
-    if(nse_err_r)       int_srcb2 <= #1 1;
-
-always @(posedge wclk)
-    if(!rst | int_src_re)   int_srcb1 <= #1 0;
-    else
-    if(pid_cs_err_r)    int_srcb1 <= #1 1;
-
-always @(posedge wclk)
-    if(!rst | int_src_re)   int_srcb0 <= #1 0;
-    else
-    if(crc5_err_r)      int_srcb0 <= #1 1;
-
-always @(posedge wclk)
-   begin
-    int_srca15 <= #1 ep15_inta | ep15_intb;
-    int_srca14 <= #1 ep14_inta | ep14_intb;
-    int_srca13 <= #1 ep13_inta | ep13_intb;
-    int_srca12 <= #1 ep12_inta | ep12_intb;
-    int_srca11 <= #1 ep11_inta | ep11_intb;
-    int_srca10 <= #1 ep10_inta | ep10_intb;
-    int_srca09 <= #1 ep9_inta | ep9_intb;
-    int_srca08 <= #1 ep8_inta | ep8_intb;
-    int_srca07 <= #1 ep7_inta | ep7_intb;
-    int_srca06 <= #1 ep6_inta | ep6_intb;
-    int_srca05 <= #1 ep5_inta | ep5_intb;
-    int_srca04 <= #1 ep4_inta | ep4_intb;
-    int_srca03 <= #1 ep3_inta | ep3_intb;
-    int_srca02 <= #1 ep2_inta | ep2_intb;
-    int_srca01 <= #1 ep1_inta | ep1_intb;
-    int_srca00 <= #1 ep0_inta | ep0_intb;
-   end
-
-///////////////////////////////////////////////////////////////////
-//
-// Endpoint Register Files
-//
-
-ep_rf   u0( .clk(           clk         ),
-        .wclk(          wclk            ),
-        .rst(           rst         ),
-        .adr(           adr1:0        ),
-        .re(            ep0_re          ),
-        .we(            ep0_we          ),
-        .din(           din         ),
-        .dout(          ep0_dout        ),
-        .inta(          ep0_inta        ),
-        .intb(          ep0_intb        ),
-        .dma_req(       dma_req0      ),
-        .dma_ack(       dma_ack0      ),
-        .idin(          idin            ),
-        .ep_sel(        ep_sel          ),
-        .ep_match(      ep0_match       ),
-        .buf0_rl(       buf0_rl         ),
-        .buf0_set(      buf0_set        ),
-        .buf1_set(      buf1_set        ),
-        .uc_bsel_set(       uc_bsel_set     ),
-        .uc_dpd_set(        uc_dpd_set      ),
-        .int_buf1_set(      int_buf1_set        ),
-        .int_buf0_set(      int_buf0_set        ),
-        .int_upid_set(      int_upid_set        ),
-        .int_crc16_set(     int_crc16_set       ),
-        .int_to_set(        int_to_set      ),
-        .int_seqerr_set(    int_seqerr_set      ),
-        .csr(           ep0_csr         ),
-        .buf0(          ep0_buf0        ),
-        .buf1(          ep0_buf1        ),
-        .dma_in_buf_sz1(    ep0_dma_in_buf_sz1  ),
-        .dma_out_buf_avail( ep0_dma_out_buf_avail   )
-        );
-
-ep_rf   u1( .clk(           clk         ),
-        .wclk(          wclk            ),
-        .rst(           rst         ),
-        .adr(           adr1:0        ),
-        .re(            ep1_re          ),
-        .we(            ep1_we          ),
-        .din(           din         ),
-        .dout(          ep1_dout        ),
-        .inta(          ep1_inta        ),
-        .intb(          ep1_intb        ),
-        .dma_req(       dma_req1      ),
-        .dma_ack(       dma_ack1      ),
-        .idin(          idin            ),
-        .ep_sel(        ep_sel          ),
-        .ep_match(      ep1_match       ),
-        .buf0_rl(       buf0_rl         ),
-        .buf0_set(      buf0_set        ),
-        .buf1_set(      buf1_set        ),
-        .uc_bsel_set(       uc_bsel_set     ),
-        .uc_dpd_set(        uc_dpd_set      ),
-        .int_buf1_set(      int_buf1_set        ),
-        .int_buf0_set(      int_buf0_set        ),
-        .int_upid_set(      int_upid_set        ),
-        .int_crc16_set(     int_crc16_set       ),
-        .int_to_set(        int_to_set      ),
-        .int_seqerr_set(    int_seqerr_set      ),
-        .csr(           ep1_csr         ),
-        .buf0(          ep1_buf0        ),
-        .buf1(          ep1_buf1        ),
-        .dma_in_buf_sz1(    ep1_dma_in_buf_sz1  ),
-        .dma_out_buf_avail( ep1_dma_out_buf_avail   )
-        );
-
-ep_rf   u2( .clk(           clk         ),
-        .wclk(          wclk            ),
-        .rst(           rst         ),
-        .adr(           adr1:0        ),
-        .re(            ep2_re          ),
-        .we(            ep2_we          ),
-        .din(           din         ),
-        .dout(          ep2_dout        ),
-        .inta(          ep2_inta        ),
-        .intb(          ep2_intb        ),
-        .dma_req(       dma_req2      ),
-        .dma_ack(       dma_ack2      ),
-        .idin(          idin            ),
-        .ep_sel(        ep_sel          ),
-        .ep_match(      ep2_match       ),
-        .buf0_rl(       buf0_rl         ),
-        .buf0_set(      buf0_set        ),
-        .buf1_set(      buf1_set        ),
-        .uc_bsel_set(       uc_bsel_set     ),
-        .uc_dpd_set(        uc_dpd_set      ),
-        .int_buf1_set(      int_buf1_set        ),
-        .int_buf0_set(      int_buf0_set        ),
-        .int_upid_set(      int_upid_set        ),
-        .int_crc16_set(     int_crc16_set       ),
-        .int_to_set(        int_to_set      ),
-        .int_seqerr_set(    int_seqerr_set      ),
-        .csr(           ep2_csr         ),
-        .buf0(          ep2_buf0        ),
-        .buf1(          ep2_buf1        ),
-        .dma_in_buf_sz1(    ep2_dma_in_buf_sz1  ),
-        .dma_out_buf_avail( ep2_dma_out_buf_avail   )
-        );
-
-ep_rf   u3( .clk(           clk         ),
-        .wclk(          wclk            ),
-        .rst(           rst         ),
-        .adr(           adr1:0        ),
-        .re(            ep3_re          ),
-        .we(            ep3_we          ),
-        .din(           din         ),
-        .dout(          ep3_dout        ),
-        .inta(          ep3_inta        ),
-        .intb(          ep3_intb        ),
-        .dma_req(       dma_req3      ),
-        .dma_ack(       dma_ack3      ),
-        .idin(          idin            ),
-        .ep_sel(        ep_sel          ),
-        .ep_match(      ep3_match       ),
-        .buf0_rl(       buf0_rl         ),
-        .buf0_set(      buf0_set        ),
-        .buf1_set(      buf1_set        ),
-        .uc_bsel_set(       uc_bsel_set     ),
-        .uc_dpd_set(        uc_dpd_set      ),
-        .int_buf1_set(      int_buf1_set        ),
-        .int_buf0_set(      int_buf0_set        ),
-        .int_upid_set(      int_upid_set        ),
-        .int_crc16_set(     int_crc16_set       ),
-        .int_to_set(        int_to_set      ),
-        .int_seqerr_set(    int_seqerr_set      ),
-        .csr(           ep3_csr         ),
-        .buf0(          ep3_buf0        ),
-        .buf1(          ep3_buf1        ),
-        .dma_in_buf_sz1(    ep3_dma_in_buf_sz1  ),
-        .dma_out_buf_avail( ep3_dma_out_buf_avail   )
-        );
-
-ep_rf   u4( .clk(           clk         ),
-        .wclk(          wclk            ),
-        .rst(           rst         ),
-        .adr(           adr1:0        ),
-        .re(            ep4_re          ),
-        .we(            ep4_we          ),
-        .din(           din         ),
-        .dout(          ep4_dout        ),
-        .inta(          ep4_inta        ),
-        .intb(          ep4_intb        ),
-        .dma_req(       dma_req4      ),
-        .dma_ack(       dma_ack4      ),
-        .idin(          idin            ),
-        .ep_sel(        ep_sel          ),
-        .ep_match(      ep4_match       ),
-        .buf0_rl(       buf0_rl         ),
-        .buf0_set(      buf0_set        ),
-        .buf1_set(      buf1_set        ),
-        .uc_bsel_set(       uc_bsel_set     ),
-        .uc_dpd_set(        uc_dpd_set      ),
-        .int_buf1_set(      int_buf1_set        ),
-        .int_buf0_set(      int_buf0_set        ),
-        .int_upid_set(      int_upid_set        ),
-        .int_crc16_set(     int_crc16_set       ),
-        .int_to_set(        int_to_set      ),
-        .int_seqerr_set(    int_seqerr_set      ),
-        .csr(           ep4_csr         ),
-        .buf0(          ep4_buf0        ),
-        .buf1(          ep4_buf1        ),
-        .dma_in_buf_sz1(    ep4_dma_in_buf_sz1  ),
-        .dma_out_buf_avail( ep4_dma_out_buf_avail   )
-        );
-
-ep_rf   u5( .clk(           clk         ),
-        .wclk(          wclk            ),
-        .rst(           rst         ),
-        .adr(           adr1:0        ),
-        .re(            ep5_re          ),
-        .we(            ep5_we          ),
-        .din(           din         ),
-        .dout(          ep5_dout        ),
-        .inta(          ep5_inta        ),
-        .intb(          ep5_intb        ),
-        .dma_req(       dma_req5      ),
-        .dma_ack(       dma_ack5      ),
-        .idin(          idin            ),
-        .ep_sel(        ep_sel          ),
-        .ep_match(      ep5_match       ),
-        .buf0_rl(       buf0_rl         ),
-        .buf0_set(      buf0_set        ),
-        .buf1_set(      buf1_set        ),
-        .uc_bsel_set(       uc_bsel_set     ),
-        .uc_dpd_set(        uc_dpd_set      ),
-        .int_buf1_set(      int_buf1_set        ),
-        .int_buf0_set(      int_buf0_set        ),
-        .int_upid_set(      int_upid_set        ),
-        .int_crc16_set(     int_crc16_set       ),
-        .int_to_set(        int_to_set      ),
-        .int_seqerr_set(    int_seqerr_set      ),
-        .csr(           ep5_csr         ),
-        .buf0(          ep5_buf0        ),
-        .buf1(          ep5_buf1        ),
-        .dma_in_buf_sz1(    ep5_dma_in_buf_sz1  ),
-        .dma_out_buf_avail( ep5_dma_out_buf_avail   )
-        );
-
-ep_rf   u6( .clk(           clk         ),
-        .wclk(          wclk            ),
-        .rst(           rst         ),
-        .adr(           adr1:0        ),
-        .re(            ep6_re          ),
-        .we(            ep6_we          ),
-        .din(           din         ),
-        .dout(          ep6_dout        ),
-        .inta(          ep6_inta        ),
-        .intb(          ep6_intb        ),
-        .dma_req(       dma_req6      ),
-        .dma_ack(       dma_ack6      ),
-        .idin(          idin            ),
-        .ep_sel(        ep_sel          ),
-        .ep_match(      ep6_match       ),
-        .buf0_rl(       buf0_rl         ),
-        .buf0_set(      buf0_set        ),
-        .buf1_set(      buf1_set        ),
-        .uc_bsel_set(       uc_bsel_set     ),
-        .uc_dpd_set(        uc_dpd_set      ),
-        .int_buf1_set(      int_buf1_set        ),
-        .int_buf0_set(      int_buf0_set        ),
-        .int_upid_set(      int_upid_set        ),
-        .int_crc16_set(     int_crc16_set       ),
-        .int_to_set(        int_to_set      ),
-        .int_seqerr_set(    int_seqerr_set      ),
-        .csr(           ep6_csr         ),
-        .buf0(          ep6_buf0        ),
-        .buf1(          ep6_buf1        ),
-        .dma_in_buf_sz1(    ep6_dma_in_buf_sz1  ),
-        .dma_out_buf_avail( ep6_dma_out_buf_avail   )
-        );
-
-ep_rf   u7( .clk(           clk         ),
-        .wclk(          wclk            ),
-        .rst(           rst         ),
-        .adr(           adr1:0        ),
-        .re(            ep7_re          ),
-        .we(            ep7_we          ),
-        .din(           din         ),
-        .dout(          ep7_dout        ),
-        .inta(          ep7_inta        ),
-        .intb(          ep7_intb        ),
-        .dma_req(       dma_req7      ),
-        .dma_ack(       dma_ack7      ),
-        .idin(          idin            ),
-        .ep_sel(        ep_sel          ),
-        .ep_match(      ep7_match       ),
-        .buf0_rl(       buf0_rl         ),
-        .buf0_set(      buf0_set        ),
-        .buf1_set(      buf1_set        ),
-        .uc_bsel_set(       uc_bsel_set     ),
-        .uc_dpd_set(        uc_dpd_set      ),
-        .int_buf1_set(      int_buf1_set        ),
-        .int_buf0_set(      int_buf0_set        ),
-        .int_upid_set(      int_upid_set        ),
-        .int_crc16_set(     int_crc16_set       ),
-        .int_to_set(        int_to_set      ),
-        .int_seqerr_set(    int_seqerr_set      ),
-        .csr(           ep7_csr         ),
-        .buf0(          ep7_buf0        ),
-        .buf1(          ep7_buf1        ),
-        .dma_in_buf_sz1(    ep7_dma_in_buf_sz1  ),
-        .dma_out_buf_avail( ep7_dma_out_buf_avail   )
-        );
-
-assign ep8_match = 0;
-assign ep9_match = 0;
-assign ep10_match = 0;
-assign ep11_match = 0;
-assign ep12_match = 0;
-assign ep13_match = 0;
-assign ep14_match = 0;
-assign ep15_match = 0;
-
-endmodule
-
-
-
-   'module',
-      'rf',
-      '(',
-       'clk',
-        'wclk',
-        'rst',
-        'adr',
-        're',
-        'we',
-        'din',
-        'dout',
-        'inta',
-        'intb',
-        'dma_req',
-        'dma_ack',
-        'idin',
-        'ep_sel',
-        'match',
-        'buf0_rl',
-        'buf0_set',
-        'buf1_set',
-        'uc_bsel_set',
-        'uc_dpd_set',
-        'int_buf1_set',
-        'int_buf0_set',
-        'int_upid_set',
-        'int_crc16_set',
-        'int_to_set',
-        'int_seqerr_set',
-        'csr',
-        'buf0',
-        'buf1',
-        'funct_adr',
-        'dma_in_buf_sz1',
-        'dma_out_buf_avail',
-        'frm_nat',
-        'utmi_vend_stat',
-        'utmi_vend_ctrl',
-        'utmi_vend_wr',
-        'line_stat',
-        'usb_attached',
-        'mode_hs',
-        'suspend',
-        'attached',
-        'usb_reset',
-        'pid_cs_err',
-        'nse_err',
-        'crc5_err',
-        'rx_err',
-        'rf_resume_req',
-      ')',
-      ';',
-     'input', 'clk', 'wclk', 'rst', ';',
-      'input', '', '6', ':', '0', '', 'adr', ';',
-      'input', 're', ';',
-      'input', 'we', ';',
-      'input', '', '31', ':', '0', '', 'din', ';',
-      'output', '', '31', ':', '0', '', 'dout', ';',
-      'output', 'inta', 'intb', ';',
-      'output', '', '14', ':', '0', '', 'dma_req', ';',
-      'input', '', '14', ':', '0', '', 'dma_ack', ';',
-      'input', '', '31', ':', '0', '', 'idin', ';',
-      'input', '', '3', ':', '0', '', 'ep_sel', ';',
-      'output', 'match', ';',
-      'input', 'buf0_rl', ';',
-      'input', 'buf0_set', ';',
-      'input', 'buf1_set', ';',
-      'input', 'uc_bsel_set', ';',
-      'input', 'uc_dpd_set', ';',
-      'input', 'int_buf1_set', ';',
-      'input', 'int_buf0_set', ';',
-      'input', 'int_upid_set', ';',
-      'input', 'int_crc16_set', ';',
-      'input', 'int_to_set', ';',
-      'input', 'int_seqerr_set', ';',
-      'output', '', '31', ':', '0', '', 'csr', ';',
-      'output', '', '31', ':', '0', '', 'buf0', ';',
-      'output', '', '31', ':', '0', '', 'buf1', ';',
-      'output', '', '6', ':', '0', '', 'funct_adr', ';',
-      'output', 'dma_in_buf_sz1', 'dma_out_buf_avail', ';',
-      'input', '', '31', ':', '0', '', 'frm_nat', ';',
-      'input', '', '7', ':', '0', '', 'utmi_vend_stat', ';',
-      'output', '', '3', ':', '0', '', 'utmi_vend_ctrl', ';',
-      'output', 'utmi_vend_wr', ';',
-      'input', '', '1', ':', '0', '', 'line_stat', ';',
-      'input', 'usb_attached', ';',
-      'input', 'mode_hs', ';',
-      'input', 'suspend', ';',
-      'input', 'attached', ';',
-      'input', 'usb_reset', ';',
-      'input', 'nse_err', ';',
-      'input', 'pid_cs_err', ';',
-      'input', 'crc5_err', ';',
-      'input', 'rx_err', ';',
-      'output', 'rf_resume_req', ';',
-       'wire',
-        '',
-        '31',
-        ':',
-        '0',
-        '',
-        'ep0_dout', 'ep1_dout', 'ep2_dout', 'ep3_dout',
-        ';',
-       'wire',
-        '',
-        '31',
-        ':',
-        '0',
-        '',
-        'ep4_dout', 'ep5_dout', 'ep6_dout', 'ep7_dout',
-        ';',
-       'wire',
-        '',
-        '31',
-        ':',
-        '0',
-        '',
-        'ep8_dout', 'ep9_dout', 'ep10_dout', 'ep11_dout',
-        ';',
-       'wire',
-        '',
-        '31',
-        ':',
-        '0',
-        '',
-        'ep12_dout', 'ep13_dout', 'ep14_dout', 'ep15_dout',
-        ';',
-      'wire', 'ep0_re', 'ep1_re', 'ep2_re', 'ep3_re', ';',
-      'wire', 'ep4_re', 'ep5_re', 'ep6_re', 'ep7_re', ';',
-      'wire', 'ep8_re', 'ep9_re', 'ep10_re', 'ep11_re', ';',
-      'wire', 'ep12_re', 'ep13_re', 'ep14_re', 'ep15_re', ';',
-      'wire', 'ep0_we', 'ep1_we', 'ep2_we', 'ep3_we', ';',
-      'wire', 'ep4_we', 'ep5_we', 'ep6_we', 'ep7_we', ';',
-      'wire', 'ep8_we', 'ep9_we', 'ep10_we', 'ep11_we', ';',
-      'wire', 'ep12_we', 'ep13_we', 'ep14_we', 'ep15_we', ';',
-      'wire', 'ep0_inta', 'ep1_inta', 'ep2_inta', 'ep3_inta', ';',
-      'wire', 'ep4_inta', 'ep5_inta', 'ep6_inta', 'ep7_inta', ';',
-      'wire', 'ep8_inta', 'ep9_inta', 'ep10_inta', 'ep11_inta', ';',
-      'wire', 'ep12_inta', 'ep13_inta', 'ep14_inta', 'ep15_inta', ';',
-      'wire', 'ep0_intb', 'ep1_intb', 'ep2_intb', 'ep3_intb', ';',
-      'wire', 'ep4_intb', 'ep5_intb', 'ep6_intb', 'ep7_intb', ';',
-      'wire', 'ep8_intb', 'ep9_intb', 'ep10_intb', 'ep11_intb', ';',
-      'wire', 'ep12_intb', 'ep13_intb', 'ep14_intb', 'ep15_intb', ';',
-      'wire', 'ep0_match', 'ep1_match', 'ep2_match', 'ep3_match', ';',
-      'wire', 'ep4_match', 'ep5_match', 'ep6_match', 'ep7_match', ';',
-      'wire', 'ep8_match', 'ep9_match', 'ep10_match', 'ep11_match', ';',
-      'wire', 'ep12_match', 'ep13_match', 'ep14_match', 'ep15_match', ';',
-       'wire',
-        '',
-        '31',
-        ':',
-        '0',
-        '',
-        'ep0_csr', 'ep1_csr', 'ep2_csr', 'ep3_csr',
-        ';',
-       'wire',
-        '',
-        '31',
-        ':',
-        '0',
-        '',
-        'ep4_csr', 'ep5_csr', 'ep6_csr', 'ep7_csr',
-        ';',
-       'wire',
-        '',
-        '31',
-        ':',
-        '0',
-        '',
-        'ep8_csr', 'ep9_csr', 'ep10_csr', 'ep11_csr',
-        ';',
-       'wire',
-        '',
-        '31',
-        ':',
-        '0',
-        '',
-        'ep12_csr', 'ep13_csr', 'ep14_csr', 'ep15_csr',
-        ';',
-       'wire',
-        '',
-        '31',
-        ':',
-        '0',
-        '',
-        'ep0_buf0', 'ep1_buf0', 'ep2_buf0', 'ep3_buf0',
-        ';',
-       'wire',
-        '',
-        '31',
-        ':',
-        '0',
-        '',
-        'ep4_buf0', 'ep5_buf0', 'ep6_buf0', 'ep7_buf0',
-        ';',
-       'wire',
-        '',
-        '31',
-        ':',
-        '0',
-        '',
-        'ep8_buf0', 'ep9_buf0', 'ep10_buf0', 'ep11_buf0',
-        ';',
-       'wire',
-        '',
-        '31',
-        ':',
-        '0',
-        '',
-        'ep12_buf0', 'ep13_buf0', 'ep14_buf0', 'ep15_buf0',
-        ';',
-       'wire',
-        '',
-        '31',
-        ':',
-        '0',
-        '',
-        'ep0_buf1', 'ep1_buf1', 'ep2_buf1', 'ep3_buf1',
-        ';',
-       'wire',
-        '',
-        '31',
-        ':',
-        '0',
-        '',
-        'ep4_buf1', 'ep5_buf1', 'ep6_buf1', 'ep7_buf1',
-        ';',
-       'wire',
-        '',
-        '31',
-        ':',
-        '0',
-        '',
-        'ep8_buf1', 'ep9_buf1', 'ep10_buf1', 'ep11_buf1',
-        ';',
-       'wire',
-        '',
-        '31',
-        ':',
-        '0',
-        '',
-        'ep12_buf1', 'ep13_buf1', 'ep14_buf1', 'ep15_buf1',
-        ';',
-      'wire', 'ep0_dma_in_buf_sz1', 'ep1_dma_in_buf_sz1', ';',
-      'wire', 'ep2_dma_in_buf_sz1', 'ep3_dma_in_buf_sz1', ';',
-      'wire', 'ep4_dma_in_buf_sz1', 'ep5_dma_in_buf_sz1', ';',
-      'wire', 'ep6_dma_in_buf_sz1', 'ep7_dma_in_buf_sz1', ';',
-      'wire', 'ep8_dma_in_buf_sz1', 'ep9_dma_in_buf_sz1', ';',
-      'wire', 'ep10_dma_in_buf_sz1', 'ep11_dma_in_buf_sz1', ';',
-      'wire', 'ep12_dma_in_buf_sz1', 'ep13_dma_in_buf_sz1', ';',
-      'wire', 'ep14_dma_in_buf_sz1', 'ep15_dma_in_buf_sz1', ';',
-      'wire', 'ep0_dma_out_buf_avail', 'ep1_dma_out_buf_avail', ';',
-      'wire', 'ep2_dma_out_buf_avail', 'ep3_dma_out_buf_avail', ';',
-      'wire', 'ep4_dma_out_buf_avail', 'ep5_dma_out_buf_avail', ';',
-      'wire', 'ep6_dma_out_buf_avail', 'ep7_dma_out_buf_avail', ';',
-      'wire', 'ep8_dma_out_buf_avail', 'ep9_dma_out_buf_avail', ';',
-      'wire', 'ep10_dma_out_buf_avail', 'ep11_dma_out_buf_avail', ';',
-      'wire', 'ep12_dma_out_buf_avail', 'ep13_dma_out_buf_avail', ';',
-      'wire', 'ep14_dma_out_buf_avail', 'ep15_dma_out_buf_avail', ';',
-      'reg', 'dma_in_buf_sz1', ';',
-      'reg', 'dma_out_buf_avail', ';',
-      'reg', '', '31', ':', '0', '', 'dtmp', ';',
-      'reg', '', '31', ':', '0', '', 'dout', ';',
-      'wire', '', '31', ':', '0', '', 'main_csr', ';',
-      'reg', '', '6', ':', '0', '', 'funct_adr', ';',
-      'reg', '', '8', ':', '0', '', 'intb_msk', 'inta_msk', ';',
-      'reg', 'match_r1', 'match_r2', ';',
-      'reg', '', '31', ':', '0', '', 'csr', ';',
-      'reg', '', '31', ':', '0', '', 'buf0', ';',
-      'reg', '', '31', ':', '0', '', 'buf1', ';',
-      'reg', '', '3', ':', '0', '', 'utmi_vend_ctrl', ';',
-      'reg', 'utmi_vend_wr', ';',
-      'reg', '', '7', ':', '0', '', 'utmi_vend_stat_r', ';',
-      'reg', 'int_src_re', ';',
-      'reg', '', '8', ':', '0', '', 'int_srcb', ';',
-      'reg', '', '15', ':', '0', '', 'int_srca', ';',
-      'reg', 'attach_r', 'attach_r1', ';',
-      'wire', 'attach', 'deattach', ';',
-      'reg', 'suspend_r', 'suspend_r1', ';',
-      'wire', 'suspend_start', 'suspend_end', ';',
-      'reg', 'usb_reset_r', ';',
-      'reg', 'rx_err_r', ';',
-      'reg', 'nse_err_r', ';',
-      'reg', 'pid_cs_err_r', ';',
-      'reg', 'crc5_err_r', ';',
-      'reg', 'rf_resume_req_r', 'rf_resume_req', ';',
-       'assign',
-         'main_csr',
-          '=',
-           '{',
-            "28 'h 0",
-            'line_stat',
-            'usb_attached',
-            'mode_hs',
-            'suspend',
-            '}',
-        ';',
-       'always',
-         '@',
-          '(',
-           'adr',
-            'main_csr',
-            'funct_adr',
-            'inta_msk',
-            'intb_msk',
-            'int_srca',
-            'int_srcb',
-            'frm_nat',
-            'utmi_vend_stat_r',
-          ')',
-         'case',
-          '(',
-          'adr', '', '2', '0', '',
-          ')',
-          '0',
-          ':',
-          'dtmp', '=', 'main_csr', ';',
-          '1',
-          ':',
-          'dtmp', '=', '{', "25 'h 0", 'funct_adr', '}', ';',
-          '2',
-          ':',
-            'dtmp',
-              '=',
-              '{', "7 'h 0", 'intb_msk', "7 'h 0", 'inta_msk', '}',
-            ';',
-          '3',
-          ':',
-            'dtmp',
-              '=',
-              '{', "3 'h 0", 'int_srcb', "4 'h 0", 'int_srca', '}',
-            ';',
-          '4',
-          ':',
-          'dtmp', '=', 'frm_nat', ';',
-          '5',
-          ':',
-          'dtmp', '=', '{', "24 'h 0", 'utmi_vend_stat_r', '}', ';',
-          'endcase',
-       'always',
-        '@', '(', 'posedge', 'wclk', ')',
-          'int_src_re',
-            '<=',
-            '#', '1',
-            'adr', '', '6', '0', '',
-            '==',
-            '3',
-            '&',
-            're',
-          ';',
-       'always',
-        '@', '(', 'posedge', 'wclk', ')',
-        'utmi_vend_stat_r', '<=', '#', '1', 'utmi_vend_stat', ';',
-       'always',
-        '@', '(', 'posedge', 'wclk', ')',
-          'utmi_vend_wr',
-            '<=',
-            '#', '1',
-            'adr', '', '6', '0', '',
-            '==',
-            '5',
-            '&',
-            'we',
-          ';',
-       'always',
-        '@', '(', 'posedge', 'wclk', ')',
-         'if',
-          '(', 'adr', '', '6', '0', '', '==', '5', '&', 'we', ')',
-            'utmi_vend_ctrl',
-              '<=',
-              '#', '1',
-              'din', '', '3', '0', '',
-            ';',
-       'always',
-        '@', '(', 'posedge', 'wclk', ')',
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-            '.', 'dma_ack', '(', 'dma_ack', '', '4', '', ')',
-            '.', 'idin', '(', 'idin', ')',
-            '.', 'ep_sel', '(', 'ep_sel', ')',
-            '.', 'ep_match', '(', 'ep4_match', ')',
-            '.', 'buf0_rl', '(', 'buf0_rl', ')',
-            '.', 'buf0_set', '(', 'buf0_set', ')',
-            '.', 'buf1_set', '(', 'buf1_set', ')',
-            '.', 'uc_bsel_set', '(', 'uc_bsel_set', ')',
-            '.', 'uc_dpd_set', '(', 'uc_dpd_set', ')',
-            '.', 'int_buf1_set', '(', 'int_buf1_set', ')',
-            '.', 'int_buf0_set', '(', 'int_buf0_set', ')',
-            '.', 'int_upid_set', '(', 'int_upid_set', ')',
-            '.', 'int_crc16_set', '(', 'int_crc16_set', ')',
-            '.', 'int_to_set', '(', 'int_to_set', ')',
-            '.', 'int_seqerr_set', '(', 'int_seqerr_set', ')',
-            '.', 'csr', '(', 'ep4_csr', ')',
-            '.', 'buf0', '(', 'ep4_buf0', ')',
-            '.', 'buf1', '(', 'ep4_buf1', ')',
-            '.', 'dma_in_buf_sz1', '(', 'ep4_dma_in_buf_sz1', ')',
-            '.', 'dma_out_buf_avail', '(', 'ep4_dma_out_buf_avail', ')',
-            ')',
-        ';',
-       'ep_rf',
-         'u5',
-           '(',
-            '.', 'clk', '(', 'clk', ')',
-            '.', 'wclk', '(', 'wclk', ')',
-            '.', 'rst', '(', 'rst', ')',
-            '.', 'adr', '(', 'adr', '', '1', '0', '', ')',
-            '.', 're', '(', 'ep5_re', ')',
-            '.', 'we', '(', 'ep5_we', ')',
-            '.', 'din', '(', 'din', ')',
-            '.', 'dout', '(', 'ep5_dout', ')',
-            '.', 'inta', '(', 'ep5_inta', ')',
-            '.', 'intb', '(', 'ep5_intb', ')',
-            '.', 'dma_req', '(', 'dma_req', '', '5', '', ')',
-            '.', 'dma_ack', '(', 'dma_ack', '', '5', '', ')',
-            '.', 'idin', '(', 'idin', ')',
-            '.', 'ep_sel', '(', 'ep_sel', ')',
-            '.', 'ep_match', '(', 'ep5_match', ')',
-            '.', 'buf0_rl', '(', 'buf0_rl', ')',
-            '.', 'buf0_set', '(', 'buf0_set', ')',
-            '.', 'buf1_set', '(', 'buf1_set', ')',
-            '.', 'uc_bsel_set', '(', 'uc_bsel_set', ')',
-            '.', 'uc_dpd_set', '(', 'uc_dpd_set', ')',
-            '.', 'int_buf1_set', '(', 'int_buf1_set', ')',
-            '.', 'int_buf0_set', '(', 'int_buf0_set', ')',
-            '.', 'int_upid_set', '(', 'int_upid_set', ')',
-            '.', 'int_crc16_set', '(', 'int_crc16_set', ')',
-            '.', 'int_to_set', '(', 'int_to_set', ')',
-            '.', 'int_seqerr_set', '(', 'int_seqerr_set', ')',
-            '.', 'csr', '(', 'ep5_csr', ')',
-            '.', 'buf0', '(', 'ep5_buf0', ')',
-            '.', 'buf1', '(', 'ep5_buf1', ')',
-            '.', 'dma_in_buf_sz1', '(', 'ep5_dma_in_buf_sz1', ')',
-            '.', 'dma_out_buf_avail', '(', 'ep5_dma_out_buf_avail', ')',
-            ')',
-        ';',
-       'ep_rf',
-         'u6',
-           '(',
-            '.', 'clk', '(', 'clk', ')',
-            '.', 'wclk', '(', 'wclk', ')',
-            '.', 'rst', '(', 'rst', ')',
-            '.', 'adr', '(', 'adr', '', '1', '0', '', ')',
-            '.', 're', '(', 'ep6_re', ')',
-            '.', 'we', '(', 'ep6_we', ')',
-            '.', 'din', '(', 'din', ')',
-            '.', 'dout', '(', 'ep6_dout', ')',
-            '.', 'inta', '(', 'ep6_inta', ')',
-            '.', 'intb', '(', 'ep6_intb', ')',
-            '.', 'dma_req', '(', 'dma_req', '', '6', '', ')',
-            '.', 'dma_ack', '(', 'dma_ack', '', '6', '', ')',
-            '.', 'idin', '(', 'idin', ')',
-            '.', 'ep_sel', '(', 'ep_sel', ')',
-            '.', 'ep_match', '(', 'ep6_match', ')',
-            '.', 'buf0_rl', '(', 'buf0_rl', ')',
-            '.', 'buf0_set', '(', 'buf0_set', ')',
-            '.', 'buf1_set', '(', 'buf1_set', ')',
-            '.', 'uc_bsel_set', '(', 'uc_bsel_set', ')',
-            '.', 'uc_dpd_set', '(', 'uc_dpd_set', ')',
-            '.', 'int_buf1_set', '(', 'int_buf1_set', ')',
-            '.', 'int_buf0_set', '(', 'int_buf0_set', ')',
-            '.', 'int_upid_set', '(', 'int_upid_set', ')',
-            '.', 'int_crc16_set', '(', 'int_crc16_set', ')',
-            '.', 'int_to_set', '(', 'int_to_set', ')',
-            '.', 'int_seqerr_set', '(', 'int_seqerr_set', ')',
-            '.', 'csr', '(', 'ep6_csr', ')',
-            '.', 'buf0', '(', 'ep6_buf0', ')',
-            '.', 'buf1', '(', 'ep6_buf1', ')',
-            '.', 'dma_in_buf_sz1', '(', 'ep6_dma_in_buf_sz1', ')',
-            '.', 'dma_out_buf_avail', '(', 'ep6_dma_out_buf_avail', ')',
-            ')',
-        ';',
-       'ep_rf',
-         'u7',
-           '(',
-            '.', 'clk', '(', 'clk', ')',
-            '.', 'wclk', '(', 'wclk', ')',
-            '.', 'rst', '(', 'rst', ')',
-            '.', 'adr', '(', 'adr', '', '1', '0', '', ')',
-            '.', 're', '(', 'ep7_re', ')',
-            '.', 'we', '(', 'ep7_we', ')',
-            '.', 'din', '(', 'din', ')',
-            '.', 'dout', '(', 'ep7_dout', ')',
-            '.', 'inta', '(', 'ep7_inta', ')',
-            '.', 'intb', '(', 'ep7_intb', ')',
-            '.', 'dma_req', '(', 'dma_req', '', '7', '', ')',
-            '.', 'dma_ack', '(', 'dma_ack', '', '7', '', ')',
-            '.', 'idin', '(', 'idin', ')',
-            '.', 'ep_sel', '(', 'ep_sel', ')',
-            '.', 'ep_match', '(', 'ep7_match', ')',
-            '.', 'buf0_rl', '(', 'buf0_rl', ')',
-            '.', 'buf0_set', '(', 'buf0_set', ')',
-            '.', 'buf1_set', '(', 'buf1_set', ')',
-            '.', 'uc_bsel_set', '(', 'uc_bsel_set', ')',
-            '.', 'uc_dpd_set', '(', 'uc_dpd_set', ')',
-            '.', 'int_buf1_set', '(', 'int_buf1_set', ')',
-            '.', 'int_buf0_set', '(', 'int_buf0_set', ')',
-            '.', 'int_upid_set', '(', 'int_upid_set', ')',
-            '.', 'int_crc16_set', '(', 'int_crc16_set', ')',
-            '.', 'int_to_set', '(', 'int_to_set', ')',
-            '.', 'int_seqerr_set', '(', 'int_seqerr_set', ')',
-            '.', 'csr', '(', 'ep7_csr', ')',
-            '.', 'buf0', '(', 'ep7_buf0', ')',
-            '.', 'buf1', '(', 'ep7_buf1', ')',
-            '.', 'dma_in_buf_sz1', '(', 'ep7_dma_in_buf_sz1', ')',
-            '.', 'dma_out_buf_avail', '(', 'ep7_dma_out_buf_avail', ')',
-            ')',
-        ';',
-      'assign', 'ep8_match', '=', '0', ';',
-      'assign', 'ep9_match', '=', '0', ';',
-      'assign', 'ep10_match', '=', '0', ';',
-      'assign', 'ep11_match', '=', '0', ';',
-      'assign', 'ep12_match', '=', '0', ';',
-      'assign', 'ep13_match', '=', '0', ';',
-      'assign', 'ep14_match', '=', '0', ';',
-      'assign', 'ep15_match', '=', '0', ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/sci_alu_comb_calltf_shell.v.parsed.txt Deleted

@@ -1,81 +0,0 @@
-/**********************************************************************
- * $scientific_alu example -- Verilog HDL shell module
- *
- * Scientific ALU C model, combinational logic version.
- *
- * Note: The Verilog language does not permit floating point numbers
- * to be connected to module ports.  However, the language provides
- * built-in system functions which convert real numbers to 64-bit
- * vectors, and vice-versa, so the real values can be passed through
- * a module the port connection. These built-in system functions are
- * $realtobits() and $bitstoreal().
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module scientific_alu(a_in, b_in, opcode,
-                      result_out, exception, error);
-  input  63:0 a_in, b_in;
-  input   3:0 opcode;
-  output 63:0 result_out;
-  output        exception, error;
-
-  real          a, b, result; // real variables used in this module
-  reg           exception, error;
-
-  // convert real numbers to/from 64-bit vector port connections
-  assign result_out = $realtobits(result);
-  always @(a_in) a  = $bitstoreal(a_in);
-  always @(b_in) b  = $bitstoreal(b_in);
-
-  //call the PLI application which interfaces to the C model
-  //using combinational logic input sensitivity  
-  always @(a or b or opcode)
-    $scientific_alu(a, b, opcode, result, exception, error);
-
-endmodule
-
-
-   'module',
-      'scientific_alu',
-      '(',
-       'a_in',
-        'b_in',
-        'opcode',
-        'result_out',
-        'exception',
-        'error',
-      ')',
-      ';',
-     'input', '', '63', ':', '0', '', 'a_in', 'b_in', ';',
-      'input', '', '3', ':', '0', '', 'opcode', ';',
-      'output', '', '63', ':', '0', '', 'result_out', ';',
-      'output', 'exception', 'error', ';',
-      'real', 'a', 'b', 'result', ';',
-      'reg', 'exception', 'error', ';',
-       'assign',
-        'result_out', '=', '$realtobits', '(', 'result', ')',
-        ';',
-       'always',
-        '@', '(', 'a_in', ')',
-        'a', '=', '$bitstoreal', '(', 'a_in', ')', ';',
-       'always',
-        '@', '(', 'b_in', ')',
-        'b', '=', '$bitstoreal', '(', 'b_in', ')', ';',
-       'always',
-        '@', '(', 'a', 'b', 'opcode', ')',
-         '$scientific_alu',
-          '(',
-          'a',
-          'b',
-          'opcode',
-          'result',
-          'exception',
-          'error',
-          ')',
-          ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/sci_alu_comb_calltf_test.v.parsed.txt Deleted

@@ -1,102 +0,0 @@
-/**********************************************************************
- * $scientific_alu example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $scientific_alu C model PLI 
- * application.  This test uses the Scientific Alu as a combinational
- * logic device.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-
-`include "sci_alu_comb_calltf_shell.v"
-
-`timescale 1ns / 1ns
-module test;
-
-  reg   4:0 opcode;
-  wire        excep, err;
-  real        a, b, result;
-  wire 63:0 a_in, b_in, result_out;
-
-  // convert real numbers to/from 64-bit vector port connections
-  always @(result_out) result = $bitstoreal(result_out);
-  assign a_in = $realtobits(a);
-  assign b_in = $realtobits(b);
-
-  scientific_alu i1 (a_in, b_in, opcode3:0, result_out, excep, err);
-
-  initial
-    begin
-      $timeformat(-9,0," ns",7);
-      $monitor("At %t: result=%.2f \t excep=%b  err=%b  a=%.1f  b=%.1f  opcode=%h",
-               $time, result, excep, err, a, b, opcode3:0);
-      a = 16.0;
-      b =  2.0;
-      for (opcode=0; opcode<=15; opcode=opcode+1)
-        #1 ;
-      
-      #10 $display("\n");
-      $finish;
-    end
-
-endmodule
-
-/*********************************************************************/
-
-
-  'module', 'test', ';',
-     'reg', '', '4', ':', '0', '', 'opcode', ';',
-      'wire', 'excep', 'err', ';',
-      'real', 'a', 'b', 'result', ';',
-      'wire', '', '63', ':', '0', '', 'a_in', 'b_in', 'result_out', ';',
-       'always',
-        '@', '(', 'result_out', ')',
-        'result', '=', '$bitstoreal', '(', 'result_out', ')', ';',
-      'assign', 'a_in', '=', '$realtobits', '(', 'a', ')', ';',
-      'assign', 'b_in', '=', '$realtobits', '(', 'b', ')', ';',
-       'scientific_alu',
-         'i1',
-           '(',
-            'a_in',
-            'b_in',
-            'opcode', '', '3', '0', '',
-            'result_out',
-            'excep',
-            'err',
-            ')',
-        ';',
-       'initial',
-         'begin',
-           '$timeformat', '(', '-', '9', '0', '" ns"', '7', ')', ';',
-             '$monitor',
-              '(',
-              '"At %t: result=%.2f \\t excep=%b  err=%b  a=%.1f  b=%.1f  '
-              'opcode=%h"',
-              '$time',
-              'result',
-              'excep',
-              'err',
-              'a',
-              'b',
-              'opcode', '', '3', '0', '',
-              ')',
-              ';',
-            'a', '=', '16.0', ';',
-            'b', '=', '2.0', ';',
-             'for',
-              '(',
-              'opcode', '=', '0',
-              ';',
-              'opcode', '<=', '15',
-              ';',
-              'opcode', '=', 'opcode', '+', '1',
-              ')',
-              '#', '1', ';',
-            '#', '10', '$display', '(', '"\\n"', ')', ';',
-            '$finish', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/sci_alu_comb_misctf_shell.v.parsed.txt Deleted

@@ -1,79 +0,0 @@
-/**********************************************************************
- * $scientific_alu example -- Verilog HDL shell module
- *
- * Scientific ALU C model, combinational logic version.
- *
- * Note: The Verilog language does not permit floating point numbers
- * to be connected to module ports.  However, the language provides
- * built-in system functions which convert real numbers to 64-bit
- * vectors, and vice-versa, so the real values can be passed through
- * a module the port connection. These built-in system functions are
- * $realtobits() and $bitstoreal().
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module scientific_alu(a_in, b_in, opcode,
-                      result_out, exception, error);
-  input  63:0 a_in, b_in;
-  input   3:0 opcode;
-  output 63:0 result_out;
-  output        exception, error;
-
-  real          a, b, result; // real variables used in this module
-  reg           exception, error;
-
-  // convert real numbers to/from 64-bit vector port connections
-  assign result_out = $realtobits(result);
-  always @(a_in) a  = $bitstoreal(a_in);
-  always @(b_in) b  = $bitstoreal(b_in);
-
-  //call the PLI application which interfaces to the C model  
-  initial
-    $scientific_alu(a, b, opcode, result, exception, error);
-
-endmodule
-
-
-   'module',
-      'scientific_alu',
-      '(',
-       'a_in',
-        'b_in',
-        'opcode',
-        'result_out',
-        'exception',
-        'error',
-      ')',
-      ';',
-     'input', '', '63', ':', '0', '', 'a_in', 'b_in', ';',
-      'input', '', '3', ':', '0', '', 'opcode', ';',
-      'output', '', '63', ':', '0', '', 'result_out', ';',
-      'output', 'exception', 'error', ';',
-      'real', 'a', 'b', 'result', ';',
-      'reg', 'exception', 'error', ';',
-       'assign',
-        'result_out', '=', '$realtobits', '(', 'result', ')',
-        ';',
-       'always',
-        '@', '(', 'a_in', ')',
-        'a', '=', '$bitstoreal', '(', 'a_in', ')', ';',
-       'always',
-        '@', '(', 'b_in', ')',
-        'b', '=', '$bitstoreal', '(', 'b_in', ')', ';',
-       'initial',
-         '$scientific_alu',
-          '(',
-          'a',
-          'b',
-          'opcode',
-          'result',
-          'exception',
-          'error',
-          ')',
-          ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/sci_alu_comb_misctf_test.v.parsed.txt Deleted

@@ -1,102 +0,0 @@
-/**********************************************************************
- * $scientific_alu example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $scientific_alu C model PLI 
- * application.  This test uses the Scientific Alu as a combinational
- * logic device.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-
-`include "sci_alu_comb_misctf_shell.v"
-
-`timescale 1ns / 1ns
-module test;
-
-  reg   4:0 opcode;
-  wire        excep, err;
-  real        a, b, result;
-  wire 63:0 a_in, b_in, result_out;
-
-  // convert real numbers to/from 64-bit vector port connections
-  always @(result_out) result = $bitstoreal(result_out);
-  assign a_in = $realtobits(a);
-  assign b_in = $realtobits(b);
-
-  scientific_alu i1 (a_in, b_in, opcode3:0, result_out, excep, err);
-
-  initial
-    begin
-      $timeformat(-9,0," ns",7);
-      $monitor("At %t: result=%.2f \t excep=%b  err=%b  a=%.1f  b=%.1f  opcode=%h",
-               $time, result, excep, err, a, b, opcode3:0);
-      a = 16.0;
-      b =  2.0;
-      for (opcode=0; opcode<=15; opcode=opcode+1)
-        #1 ;
-      
-      #10 $display("\n");
-      $finish;
-    end
-
-endmodule
-
-/*********************************************************************/
-
-
-  'module', 'test', ';',
-     'reg', '', '4', ':', '0', '', 'opcode', ';',
-      'wire', 'excep', 'err', ';',
-      'real', 'a', 'b', 'result', ';',
-      'wire', '', '63', ':', '0', '', 'a_in', 'b_in', 'result_out', ';',
-       'always',
-        '@', '(', 'result_out', ')',
-        'result', '=', '$bitstoreal', '(', 'result_out', ')', ';',
-      'assign', 'a_in', '=', '$realtobits', '(', 'a', ')', ';',
-      'assign', 'b_in', '=', '$realtobits', '(', 'b', ')', ';',
-       'scientific_alu',
-         'i1',
-           '(',
-            'a_in',
-            'b_in',
-            'opcode', '', '3', '0', '',
-            'result_out',
-            'excep',
-            'err',
-            ')',
-        ';',
-       'initial',
-         'begin',
-           '$timeformat', '(', '-', '9', '0', '" ns"', '7', ')', ';',
-             '$monitor',
-              '(',
-              '"At %t: result=%.2f \\t excep=%b  err=%b  a=%.1f  b=%.1f  '
-              'opcode=%h"',
-              '$time',
-              'result',
-              'excep',
-              'err',
-              'a',
-              'b',
-              'opcode', '', '3', '0', '',
-              ')',
-              ';',
-            'a', '=', '16.0', ';',
-            'b', '=', '2.0', ';',
-             'for',
-              '(',
-              'opcode', '=', '0',
-              ';',
-              'opcode', '<=', '15',
-              ';',
-              'opcode', '=', 'opcode', '+', '1',
-              ')',
-              '#', '1', ';',
-            '#', '10', '$display', '(', '"\\n"', ')', ';',
-            '$finish', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/sci_alu_combinational_shell.v.parsed.txt Deleted

@@ -1,79 +0,0 @@
-/**********************************************************************
- * $scientific_alu example -- Verilog HDL shell module
- *
- * Scientific ALU C model, combinational logic version.
- *
- * Note: The Verilog language does not permit floating point numbers
- * to be connected to module ports.  However, the language provides
- * built-in system functions which convert real numbers to 64-bit
- * vectors, and vice-versa, so the real values can be passed through
- * a module the port connection. These built-in system functions are
- * $realtobits() and $bitstoreal().
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module scientific_alu(a_in, b_in, opcode,
-                      result_out, exception, error);
-  input  63:0 a_in, b_in;
-  input   3:0 opcode;
-  output 63:0 result_out;
-  output        exception, error;
-
-  real          a, b, result; // real variables used in this module
-  reg           exception, error;
-
-  // convert real numbers to/from 64-bit vector port connections
-  assign result_out = $realtobits(result);
-  always @(a_in) a  = $bitstoreal(a_in);
-  always @(b_in) b  = $bitstoreal(b_in);
-
-  //call the PLI application which interfaces to the C model
-  initial
-    $scientific_alu(a, b, opcode, result, exception, error);
-
-endmodule
-
-
-   'module',
-      'scientific_alu',
-      '(',
-       'a_in',
-        'b_in',
-        'opcode',
-        'result_out',
-        'exception',
-        'error',
-      ')',
-      ';',
-     'input', '', '63', ':', '0', '', 'a_in', 'b_in', ';',
-      'input', '', '3', ':', '0', '', 'opcode', ';',
-      'output', '', '63', ':', '0', '', 'result_out', ';',
-      'output', 'exception', 'error', ';',
-      'real', 'a', 'b', 'result', ';',
-      'reg', 'exception', 'error', ';',
-       'assign',
-        'result_out', '=', '$realtobits', '(', 'result', ')',
-        ';',
-       'always',
-        '@', '(', 'a_in', ')',
-        'a', '=', '$bitstoreal', '(', 'a_in', ')', ';',
-       'always',
-        '@', '(', 'b_in', ')',
-        'b', '=', '$bitstoreal', '(', 'b_in', ')', ';',
-       'initial',
-         '$scientific_alu',
-          '(',
-          'a',
-          'b',
-          'opcode',
-          'result',
-          'exception',
-          'error',
-          ')',
-          ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/sci_alu_combinational_test.v.parsed.txt Deleted

@@ -1,102 +0,0 @@
-/**********************************************************************
- * $scientific_alu example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $scientific_alu C model PLI 
- * application.  This test uses the Scientific Alu as a combinational
- * logic device.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-
-`include "sci_alu_combinational_shell.v"
-
-`timescale 1ns / 1ns
-module test;
-
-  reg   4:0 opcode;
-  wire        excep, err;
-  real        a, b, result;
-  wire 63:0 a_in, b_in, result_out;
-
-  // convert real numbers to/from 64-bit vector port connections
-  always @(result_out) result = $bitstoreal(result_out);
-  assign a_in = $realtobits(a);
-  assign b_in = $realtobits(b);
-
-  scientific_alu i1 (a_in, b_in, opcode3:0, result_out, excep, err);
-
-  initial
-    begin
-      $timeformat(-9,0," ns",7);
-      $monitor("At %t: result=%.2f \t excep=%b  err=%b  a=%.1f  b=%.1f  opcode=%h",
-               $time, result, excep, err, a, b, opcode3:0);
-      a = 16.0;
-      b =  2.0;
-      for (opcode=0; opcode<=15; opcode=opcode+1)
-        #1 ;
-      
-      #10 $display("\n");
-      $finish;
-    end
-
-endmodule
-
-/*********************************************************************/
-
-
-  'module', 'test', ';',
-     'reg', '', '4', ':', '0', '', 'opcode', ';',
-      'wire', 'excep', 'err', ';',
-      'real', 'a', 'b', 'result', ';',
-      'wire', '', '63', ':', '0', '', 'a_in', 'b_in', 'result_out', ';',
-       'always',
-        '@', '(', 'result_out', ')',
-        'result', '=', '$bitstoreal', '(', 'result_out', ')', ';',
-      'assign', 'a_in', '=', '$realtobits', '(', 'a', ')', ';',
-      'assign', 'b_in', '=', '$realtobits', '(', 'b', ')', ';',
-       'scientific_alu',
-         'i1',
-           '(',
-            'a_in',
-            'b_in',
-            'opcode', '', '3', '0', '',
-            'result_out',
-            'excep',
-            'err',
-            ')',
-        ';',
-       'initial',
-         'begin',
-           '$timeformat', '(', '-', '9', '0', '" ns"', '7', ')', ';',
-             '$monitor',
-              '(',
-              '"At %t: result=%.2f \\t excep=%b  err=%b  a=%.1f  b=%.1f  '
-              'opcode=%h"',
-              '$time',
-              'result',
-              'excep',
-              'err',
-              'a',
-              'b',
-              'opcode', '', '3', '0', '',
-              ')',
-              ';',
-            'a', '=', '16.0', ';',
-            'b', '=', '2.0', ';',
-             'for',
-              '(',
-              'opcode', '=', '0',
-              ';',
-              'opcode', '<=', '15',
-              ';',
-              'opcode', '=', 'opcode', '+', '1',
-              ')',
-              '#', '1', ';',
-            '#', '10', '$display', '(', '"\\n"', ')', ';',
-            '$finish', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/sci_alu_latched_shell.v.parsed.txt Deleted

@@ -1,83 +0,0 @@
-/**********************************************************************
- * $scientific_alu example -- Verilog HDL shell module
- *
- * Scientific ALU C model, latched logic version.
- *
- * Note: The Verilog language does not permit floating point numbers
- * to be connected to module ports.  However, the language provides
- * built-in system functions which convert real numbers to 64-bit
- * vectors, and vice-versa, so the real values can be passed through
- * a module the port connection. These built-in system functions are
- * $realtobits() and $bitstoreal().
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module scientific_alu(enable, a_in, b_in, opcode,
-                      result_out, exception, error);
-  input         enable;
-  input  63:0 a_in, b_in;
-  input   3:0 opcode;
-  output 63:0 result_out;
-  output        exception, error;
-
-  real          a, b, result; // real variables used in this module
-  reg           exception, error;
-
-  // convert real numbers to/from 64-bit vector port connections
-  assign result_out = $realtobits(result);
-  always @(a_in) a  = $bitstoreal(a_in);
-  always @(b_in) b  = $bitstoreal(b_in);
-
-  //call the PLI application which interfaces to the C model  
-  initial
-    $scientific_alu(enable, a, b, opcode, result, exception, error);
-
-endmodule
-
-
-   'module',
-      'scientific_alu',
-      '(',
-       'enable',
-        'a_in',
-        'b_in',
-        'opcode',
-        'result_out',
-        'exception',
-        'error',
-      ')',
-      ';',
-     'input', 'enable', ';',
-      'input', '', '63', ':', '0', '', 'a_in', 'b_in', ';',
-      'input', '', '3', ':', '0', '', 'opcode', ';',
-      'output', '', '63', ':', '0', '', 'result_out', ';',
-      'output', 'exception', 'error', ';',
-      'real', 'a', 'b', 'result', ';',
-      'reg', 'exception', 'error', ';',
-       'assign',
-        'result_out', '=', '$realtobits', '(', 'result', ')',
-        ';',
-       'always',
-        '@', '(', 'a_in', ')',
-        'a', '=', '$bitstoreal', '(', 'a_in', ')', ';',
-       'always',
-        '@', '(', 'b_in', ')',
-        'b', '=', '$bitstoreal', '(', 'b_in', ')', ';',
-       'initial',
-         '$scientific_alu',
-          '(',
-          'enable',
-          'a',
-          'b',
-          'opcode',
-          'result',
-          'exception',
-          'error',
-          ')',
-          ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/sci_alu_latched_test.v.parsed.txt Deleted

@@ -1,139 +0,0 @@
-/**********************************************************************
- * $scientific_alu example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $scientific_alu C model PLI 
- * application.  This test uses the Scientific Alu as a latched
- * logic device.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
- 
-`include "sci_alu_latched_shell.v"
-
-`timescale 1ns / 1ns
-module test;
-
-  reg   4:0 opcode;
-  reg         enable;
-  wire        excep, err;
-  real        a, b, result1, result2;
-  wire 63:0 a_in, b_in, result_out1, result_out2;
-
-  // convert real numbers to/from 64-bit vector port connections
-  always @(result_out1) result1 = $bitstoreal(result_out1);
-  always @(result_out2) result2 = $bitstoreal(result_out2);
-  assign a_in = $realtobits(a);
-  assign b_in = $realtobits(b);
-
-  scientific_alu i1 (enable, a_in, b_in,  opcode3:0, result_out1, excep, err);
-  scientific_alu i2 (enable, a_in, b_in, ~opcode3:0, result_out2, excep, err);
-
-  initial
-    begin
-      $timeformat(-9,0," ns",7);
-      $monitor("At %t: result1=%.2f \tresult2=%.2f \t  excep=%b  err=%b  a=%.1f  b=%.1f  opcode=%h, enable=%b",
-               $time, result1, result2, excep, err, a, b, opcode3:0, enable);
-      enable = 1;
-      a = 16.0;
-      b =  2.0;
-      for (opcode=0; opcode<=15; opcode=opcode+1)
-        #1 ;
-      
-      #10 $display("");
-      enable = 0;
-
-      #10 $display("\n");
-      $finish;
-    end
-
-endmodule
-
-/*********************************************************************/
-
-
-  'module', 'test', ';',
-     'reg', '', '4', ':', '0', '', 'opcode', ';',
-      'reg', 'enable', ';',
-      'wire', 'excep', 'err', ';',
-      'real', 'a', 'b', 'result1', 'result2', ';',
-       'wire',
-        '',
-        '63',
-        ':',
-        '0',
-        '',
-        'a_in', 'b_in', 'result_out1', 'result_out2',
-        ';',
-       'always',
-        '@', '(', 'result_out1', ')',
-        'result1', '=', '$bitstoreal', '(', 'result_out1', ')', ';',
-       'always',
-        '@', '(', 'result_out2', ')',
-        'result2', '=', '$bitstoreal', '(', 'result_out2', ')', ';',
-      'assign', 'a_in', '=', '$realtobits', '(', 'a', ')', ';',
-      'assign', 'b_in', '=', '$realtobits', '(', 'b', ')', ';',
-       'scientific_alu',
-         'i1',
-           '(',
-            'enable',
-            'a_in',
-            'b_in',
-            'opcode', '', '3', '0', '',
-            'result_out1',
-            'excep',
-            'err',
-            ')',
-        ';',
-       'scientific_alu',
-         'i2',
-           '(',
-            'enable',
-            'a_in',
-            'b_in',
-            '~',
-            'opcode', '', '3', '0', '',
-            'result_out2',
-            'excep',
-            'err',
-            ')',
-        ';',
-       'initial',
-         'begin',
-           '$timeformat', '(', '-', '9', '0', '" ns"', '7', ')', ';',
-             '$monitor',
-              '(',
-              '"At %t: result1=%.2f \\tresult2=%.2f \\t  excep=%b  err=%b  '
-              'a=%.1f  b=%.1f  opcode=%h, enable=%b"',
-              '$time',
-              'result1',
-              'result2',
-              'excep',
-              'err',
-              'a',
-              'b',
-              'opcode', '', '3', '0', '',
-              'enable',
-              ')',
-              ';',
-            'enable', '=', '1', ';',
-            'a', '=', '16.0', ';',
-            'b', '=', '2.0', ';',
-             'for',
-              '(',
-              'opcode', '=', '0',
-              ';',
-              'opcode', '<=', '15',
-              ';',
-              'opcode', '=', 'opcode', '+', '1',
-              ')',
-              '#', '1', ';',
-            '#', '10', '$display', '(', '""', ')', ';',
-            'enable', '=', '0', ';',
-            '#', '10', '$display', '(', '"\\n"', ')', ';',
-            '$finish', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/sci_alu_sequential_shell.v.parsed.txt Deleted

@@ -1,83 +0,0 @@
-/**********************************************************************
- * $scientific_alu example -- Verilog HDL shell module
- *
- * Scientific ALU C model, sequential logic version.
- *
- * Note: The Verilog language does not permit floating point numbers
- * to be connected to module ports.  However, the language provides
- * built-in system functions which convert real numbers to 64-bit
- * vectors, and vice-versa, so the real values can be passed through
- * a module the port connection. These built-in system functions are
- * $realtobits() and $bitstoreal().
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module scientific_alu(clock, a_in, b_in, opcode,
-                      result_out, exception, error);
-  input         clock;
-  input  63:0 a_in, b_in;
-  input   3:0 opcode;
-  output 63:0 result_out;
-  output        exception, error;
-
-  real          a, b, result; // real variables used in this module
-  reg           exception, error;
-
-  // convert real numbers to/from 64-bit vector port connections
-  assign result_out = $realtobits(result);
-  always @(a_in) a  = $bitstoreal(a_in);
-  always @(b_in) b  = $bitstoreal(b_in);
-
-  //call the PLI application which interfaces to the C model  
-  initial
-    $scientific_alu(clock, a, b, opcode, result, exception, error);
-
-endmodule
-
-
-   'module',
-      'scientific_alu',
-      '(',
-       'clock',
-        'a_in',
-        'b_in',
-        'opcode',
-        'result_out',
-        'exception',
-        'error',
-      ')',
-      ';',
-     'input', 'clock', ';',
-      'input', '', '63', ':', '0', '', 'a_in', 'b_in', ';',
-      'input', '', '3', ':', '0', '', 'opcode', ';',
-      'output', '', '63', ':', '0', '', 'result_out', ';',
-      'output', 'exception', 'error', ';',
-      'real', 'a', 'b', 'result', ';',
-      'reg', 'exception', 'error', ';',
-       'assign',
-        'result_out', '=', '$realtobits', '(', 'result', ')',
-        ';',
-       'always',
-        '@', '(', 'a_in', ')',
-        'a', '=', '$bitstoreal', '(', 'a_in', ')', ';',
-       'always',
-        '@', '(', 'b_in', ')',
-        'b', '=', '$bitstoreal', '(', 'b_in', ')', ';',
-       'initial',
-         '$scientific_alu',
-          '(',
-          'clock',
-          'a',
-          'b',
-          'opcode',
-          'result',
-          'exception',
-          'error',
-          ')',
-          ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/sci_alu_sequential_test.v.parsed.txt Deleted

@@ -1,110 +0,0 @@
-/**********************************************************************
- * $scientific_alu example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $scientific_alu C model PLI 
- * application.  This test uses the Scientific Alu as a sequential
- * logic device.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
- 
-`include "sci_alu_sequential_shell.v"
-
-`timescale 1ns / 1ns
-module test;
-
-  reg   4:0 opcode;
-  reg         clk;
-  wire        excep, err;
-  real        a, b, result;
-  wire 63:0 a_in, b_in, result_out;
-
-  // convert real numbers to/from 64-bit vector port connections
-  always @(result_out) result = $bitstoreal(result_out);
-  assign a_in = $realtobits(a);
-  assign b_in = $realtobits(b);
-
-  scientific_alu i1 (clk, a_in, b_in, opcode3:0, result_out, excep, err);
-
-  always #5 clk = ~clk;
-  
-  initial
-    begin
-      $timeformat(-9,0," ns",7);
-      $monitor("At %t: result=%.2f \t excep=%b  err=%b  a=%.1f  b=%.1f  opcode=%h",
-               $time, result, excep, err, a, b, opcode3:0);
-      clk = 0;
-      a = 16.0;
-      b =  2.0;
-      for (opcode=0; opcode<=15; opcode=opcode+1)
-        @(negedge clk) ;
-      
-      #10 $display("\n");
-     $finish;
-    end
-
-endmodule
-
-/*********************************************************************/
-
-
-  'module', 'test', ';',
-     'reg', '', '4', ':', '0', '', 'opcode', ';',
-      'reg', 'clk', ';',
-      'wire', 'excep', 'err', ';',
-      'real', 'a', 'b', 'result', ';',
-      'wire', '', '63', ':', '0', '', 'a_in', 'b_in', 'result_out', ';',
-       'always',
-        '@', '(', 'result_out', ')',
-        'result', '=', '$bitstoreal', '(', 'result_out', ')', ';',
-      'assign', 'a_in', '=', '$realtobits', '(', 'a', ')', ';',
-      'assign', 'b_in', '=', '$realtobits', '(', 'b', ')', ';',
-       'scientific_alu',
-         'i1',
-           '(',
-            'clk',
-            'a_in',
-            'b_in',
-            'opcode', '', '3', '0', '',
-            'result_out',
-            'excep',
-            'err',
-            ')',
-        ';',
-      'always', '#', '5', 'clk', '=', '~', 'clk', ';',
-       'initial',
-         'begin',
-           '$timeformat', '(', '-', '9', '0', '" ns"', '7', ')', ';',
-             '$monitor',
-              '(',
-              '"At %t: result=%.2f \\t excep=%b  err=%b  a=%.1f  b=%.1f  '
-              'opcode=%h"',
-              '$time',
-              'result',
-              'excep',
-              'err',
-              'a',
-              'b',
-              'opcode', '', '3', '0', '',
-              ')',
-              ';',
-            'clk', '=', '0', ';',
-            'a', '=', '16.0', ';',
-            'b', '=', '2.0', ';',
-             'for',
-              '(',
-              'opcode', '=', '0',
-              ';',
-              'opcode', '<=', '15',
-              ';',
-              'opcode', '=', 'opcode', '+', '1',
-              ')',
-              '@', '(', 'negedge', 'clk', ')', ';',
-            '#', '10', '$display', '(', '"\\n"', ')', ';',
-            '$finish', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/sci_alu_synchronized_shell.v.parsed.txt Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/sci_alu_synchronized_test.v.parsed.txt Deleted

@@ -1,127 +0,0 @@
-/**********************************************************************
- * $scientific_alu example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $scientific_alu C model PLI 
- * application.  This test uses the Scientific Alu as a combinational
- * logic device.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
- 
-`include "sci_alu_synchronized_shell.v"
-
-`timescale 1ns / 1ns
-module test;
-
-  reg   4:0 opcode;
-  wire        excep, err;
-  real        a, b, result1, result2;
-  wire 63:0 a_in, b_in, result_out1, result_out2;
-
-  // convert real numbers to/from 64-bit vector port connections
-  always @(result_out1) result1 = $bitstoreal(result_out1);
-  always @(result_out2) result2 = $bitstoreal(result_out2);
-  assign a_in = $realtobits(a);
-  assign b_in = $realtobits(b);
-
-  scientific_alu i1 (a_in, b_in,  opcode3:0, result_out1, excep, err);
-  scientific_alu i2 (a_in, b_in, ~opcode3:0, result_out2, excep, err);
-
-  initial
-    begin
-      $timeformat(-9,0," ns",7);
-      $monitor("At %t: result1=%.2f \tresult2=%.2f \t  excep=%b  err=%b  a=%.1f  b=%.1f  opcode=%h",
-               $time, result1, result2, excep, err, a, b, opcode3:0);
-      a = 16.0;
-      b =  2.0;
-      for (opcode=0; opcode<=15; opcode=opcode+1)
-        #1 ;
-      
-      #10 $display("\n");
-     $finish;
-    end
-
-endmodule
-
-/*********************************************************************/
-
-
-  'module', 'test', ';',
-     'reg', '', '4', ':', '0', '', 'opcode', ';',
-      'wire', 'excep', 'err', ';',
-      'real', 'a', 'b', 'result1', 'result2', ';',
-       'wire',
-        '',
-        '63',
-        ':',
-        '0',
-        '',
-        'a_in', 'b_in', 'result_out1', 'result_out2',
-        ';',
-       'always',
-        '@', '(', 'result_out1', ')',
-        'result1', '=', '$bitstoreal', '(', 'result_out1', ')', ';',
-       'always',
-        '@', '(', 'result_out2', ')',
-        'result2', '=', '$bitstoreal', '(', 'result_out2', ')', ';',
-      'assign', 'a_in', '=', '$realtobits', '(', 'a', ')', ';',
-      'assign', 'b_in', '=', '$realtobits', '(', 'b', ')', ';',
-       'scientific_alu',
-         'i1',
-           '(',
-            'a_in',
-            'b_in',
-            'opcode', '', '3', '0', '',
-            'result_out1',
-            'excep',
-            'err',
-            ')',
-        ';',
-       'scientific_alu',
-         'i2',
-           '(',
-            'a_in',
-            'b_in',
-            '~',
-            'opcode', '', '3', '0', '',
-            'result_out2',
-            'excep',
-            'err',
-            ')',
-        ';',
-       'initial',
-         'begin',
-           '$timeformat', '(', '-', '9', '0', '" ns"', '7', ')', ';',
-             '$monitor',
-              '(',
-              '"At %t: result1=%.2f \\tresult2=%.2f \\t  excep=%b  err=%b  '
-              'a=%.1f  b=%.1f  opcode=%h"',
-              '$time',
-              'result1',
-              'result2',
-              'excep',
-              'err',
-              'a',
-              'b',
-              'opcode', '', '3', '0', '',
-              ')',
-              ';',
-            'a', '=', '16.0', ';',
-            'b', '=', '2.0', ';',
-             'for',
-              '(',
-              'opcode', '=', '0',
-              ';',
-              'opcode', '<=', '15',
-              ';',
-              'opcode', '=', 'opcode', '+', '1',
-              ')',
-              '#', '1', ';',
-            '#', '10', '$display', '(', '"\\n"', ')', ';',
-            '$finish', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/sci_alu_with_delays_shell.v.parsed.txt Deleted

@@ -1,165 +0,0 @@
-/**********************************************************************
- * $scientific_alu example -- Verilog HDL shell module
- *
- * Scientific ALU C model, combinational logic version with pin-to-pin
- * path delays.  The path delays are represented using a Verilog 
- * specify block.
- *
- * NOTES:
- * - Note: The Verilog language does not permit floating point numbers
- *   to be connected to module ports.  However, the language provides
- *   built-in system functions which convert real numbers to 64-bit
- *   vectors, and vice-versa, so the real values can be passed through
- *   a module the port connection. These built-in system functions are
- *   $realtobits() and $bitstoreal().
- *
- * - Some Verilog simulators require that path delays to be used with
- *   models where all ports are connected to uni-directional
- *   primitives with nets data types connected to the inputs an outputs
- *   of the primitives.  This model satisfies this restriction by
- *   adding buffers to all input and output ports.
- *
- * - This shell module uses the array of instances from the IEEE 1364
- *   Verilog standard.  Some simulators do not support this construct,
- *   and may require using a separate instance statement for each bit
- *   of a vector.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 100ps
-module scientific_alu(a_in, b_in, opcode_in,
-                      result_out, exception, error);
-  output 63:0 result_out;
-  output        exception, error;
-  input  63:0 a_in, b_in;
-  input   3:0 opcode_in;
-
-  wire   63:0 result_out, result_vector;
-  wire   63:0 a_in, a_vector;
-  wire   63:0 b_in, b_vector;
-  wire    3:0 opcode_in, opcode_vector;
-  wire          exception, error;
-
-  reg           exception_reg, error_reg;
-  real          a, b, result; // real variables used in this module
-
-  // convert real numbers to/from 64-bit vector port connections
-  assign result_vector = $realtobits(result);
-  always @(a_vector)  a = $bitstoreal(a_vector);
-  always @(b_vector)  b = $bitstoreal(b_vector);
-
-  //call the PLI application which interfaces to the C model  
-  initial
-    $scientific_alu(a, b, opcode_vector,
-                    result, exception_reg, error_reg);
-
-  specify
-    (a_in, b_in *> result_out, exception, error) = (5.6, 4.7);
-    (opcode_in  *> result_out, exception, error) = (3.4, 3.8);
-  endspecify
-
-  // add buffers to all ports, with nets connected to each buffer
-  // (this example uses the array of instance syntax in the
-  // from the IEEE 1364-1995 Verilog standard
-  buf result_buf63:0 (result_out, result_vector);
-  buf excep_buf        (exception,  exception_reg);
-  buf error_buf        (error,      error_reg);
-
-  buf a_buf63:0      (a_vector, a_in);
-  buf b_buf63:0      (b_vector, b_in);
-  buf opcode_buf3:0  (opcode_vector, opcode_in);
-
-endmodule
-
-
-   'module',
-      'scientific_alu',
-      '(',
-       'a_in',
-        'b_in',
-        'opcode_in',
-        'result_out',
-        'exception',
-        'error',
-      ')',
-      ';',
-     'output', '', '63', ':', '0', '', 'result_out', ';',
-      'output', 'exception', 'error', ';',
-      'input', '', '63', ':', '0', '', 'a_in', 'b_in', ';',
-      'input', '', '3', ':', '0', '', 'opcode_in', ';',
-      'wire', '', '63', ':', '0', '', 'result_out', 'result_vector', ';',
-      'wire', '', '63', ':', '0', '', 'a_in', 'a_vector', ';',
-      'wire', '', '63', ':', '0', '', 'b_in', 'b_vector', ';',
-      'wire', '', '3', ':', '0', '', 'opcode_in', 'opcode_vector', ';',
-      'wire', 'exception', 'error', ';',
-      'reg', 'exception_reg', 'error_reg', ';',
-      'real', 'a', 'b', 'result', ';',
-       'assign',
-        'result_vector', '=', '$realtobits', '(', 'result', ')',
-        ';',
-       'always',
-        '@', '(', 'a_vector', ')',
-        'a', '=', '$bitstoreal', '(', 'a_vector', ')', ';',
-       'always',
-        '@', '(', 'b_vector', ')',
-        'b', '=', '$bitstoreal', '(', 'b_vector', ')', ';',
-       'initial',
-         '$scientific_alu',
-          '(',
-          'a',
-          'b',
-          'opcode_vector',
-          'result',
-          'exception_reg',
-          'error_reg',
-          ')',
-          ';',
-       'specify',
-          '(',
-            'a_in', 'b_in',
-            '*>',
-            'result_out', 'exception', 'error',
-            ')',
-          '=',
-          '(', '5.6', '4.7', ')',
-          ';',
-          '(',
-            'opcode_in',
-            '*>',
-            'result_out', 'exception', 'error',
-            ')',
-          '=',
-          '(', '3.4', '3.8', ')',
-          ';',
-        'endspecify',
-       'buf',
-        'result_buf', '', '63', ':', '0', '',
-        '(',
-        'result_out', 'result_vector',
-        ')',
-        ';',
-      'buf', 'excep_buf', '(', 'exception', 'exception_reg', ')', ';',
-      'buf', 'error_buf', '(', 'error', 'error_reg', ')', ';',
-       'buf',
-        'a_buf', '', '63', ':', '0', '',
-        '(',
-        'a_vector', 'a_in',
-        ')',
-        ';',
-       'buf',
-        'b_buf', '', '63', ':', '0', '',
-        '(',
-        'b_vector', 'b_in',
-        ')',
-        ';',
-       'buf',
-        'opcode_buf', '', '3', ':', '0', '',
-        '(',
-        'opcode_vector', 'opcode_in',
-        ')',
-        ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/sci_alu_with_delays_test.v.parsed.txt Deleted

@@ -1,102 +0,0 @@
-/**********************************************************************
- * $scientific_alu example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $scientific_alu C model PLI 
- * application.  This test uses the Scientific Alu as a combinational
- * logic device.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-
-`include "sci_alu_with_delays_shell.v"
-
-`timescale 1ns / 1ns
-module test;
-
-  reg   4:0 opcode;
-  wire        excep, err;
-  real        a, b, result;
-  wire 63:0 a_in, b_in, result_out;
-
-  // convert real numbers to/from 64-bit vector port connections
-  always @(result_out) result = $bitstoreal(result_out);
-  assign a_in = $realtobits(a);
-  assign b_in = $realtobits(b);
-
-  scientific_alu i1 (a_in, b_in, opcode3:0, result_out, excep, err);
-
-  initial
-    begin
-      $timeformat(-9,0," ns",7);
-      $monitor("At %t: result=%.2f \t excep=%b  err=%b  a=%.1f  b=%.1f  opcode=%h",
-               $time, result, excep, err, a, b, opcode3:0);
-      a = 16.0;
-      b =  2.0;
-      for (opcode=0; opcode<=15; opcode=opcode+1)
-        #10 ;
-      
-      #10 $display("\n");
-      $finish;
-    end
-
-endmodule
-
-/*********************************************************************/
-
-
-  'module', 'test', ';',
-     'reg', '', '4', ':', '0', '', 'opcode', ';',
-      'wire', 'excep', 'err', ';',
-      'real', 'a', 'b', 'result', ';',
-      'wire', '', '63', ':', '0', '', 'a_in', 'b_in', 'result_out', ';',
-       'always',
-        '@', '(', 'result_out', ')',
-        'result', '=', '$bitstoreal', '(', 'result_out', ')', ';',
-      'assign', 'a_in', '=', '$realtobits', '(', 'a', ')', ';',
-      'assign', 'b_in', '=', '$realtobits', '(', 'b', ')', ';',
-       'scientific_alu',
-         'i1',
-           '(',
-            'a_in',
-            'b_in',
-            'opcode', '', '3', '0', '',
-            'result_out',
-            'excep',
-            'err',
-            ')',
-        ';',
-       'initial',
-         'begin',
-           '$timeformat', '(', '-', '9', '0', '" ns"', '7', ')', ';',
-             '$monitor',
-              '(',
-              '"At %t: result=%.2f \\t excep=%b  err=%b  a=%.1f  b=%.1f  '
-              'opcode=%h"',
-              '$time',
-              'result',
-              'excep',
-              'err',
-              'a',
-              'b',
-              'opcode', '', '3', '0', '',
-              ')',
-              ';',
-            'a', '=', '16.0', ';',
-            'b', '=', '2.0', ';',
-             'for',
-              '(',
-              'opcode', '=', '0',
-              ';',
-              'opcode', '<=', '15',
-              ';',
-              'opcode', '=', 'opcode', '+', '1',
-              ')',
-              '#', '10', ';',
-            '#', '10', '$display', '(', '"\\n"', ')', ';',
-            '$finish', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/set_mipd_delays_test.v.parsed.txt Deleted

@@ -1,99 +0,0 @@
-/**********************************************************************
- * $set_mipd_delays example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $set_mipd_delays PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 10ps
-module test;
-  reg  a, b, ci, clk;
-  wire sum, co;
-
-  addbit i1 (a, b, ci, sum, co);
-
-  initial
-    begin
-      $set_mipd_delays(i1.a, 2.3, 2.4, 2.5);
-      a = 0; b = 0; ci = 0;
-      #10 a = 1;
-      #10 b = 1;
-      #10 a = 0;
-      #1 $finish;
-    end
-    
-  initial
-    $monitor("At %0.2f: a=%d b=%d ci%d sum=%d co=%d",
-             $realtime, a, b, ci, sum, co);
-    
-endmodule
-
-/*** A gate level 1 bit adder model ***/
-`timescale 1ns / 10ps
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci, sum, co,
-        n1, n2, n3;
-
-  xor  (n1, a, b);
-  xor  (sum, n1, ci);
-  and  (n2, a, b);
-  and  (n3, n1, ci);
-  or   (co, n2, n3);
-  
-endmodule
-/*********************************************************************/
-
-
-
-  'module', 'test', ';',
-     'reg', 'a', 'b', 'ci', 'clk', ';',
-      'wire', 'sum', 'co', ';',
-       'addbit',
-        'i1', '(', 'a', 'b', 'ci', 'sum', 'co', ')',
-        ';',
-       'initial',
-         'begin',
-           '$set_mipd_delays', '(', 'i1.a', '2.3', '2.4', '2.5', ')', ';',
-            'a', '=', '0', ';',
-            'b', '=', '0', ';',
-            'ci', '=', '0', ';',
-            '#', '10', 'a', '=', '1', ';',
-            '#', '10', 'b', '=', '1', ';',
-            '#', '10', 'a', '=', '0', ';',
-            '#', '1', '$finish', ';',
-          'end',
-       'initial',
-         '$monitor',
-          '(',
-          '"At %0.2f: a=%d b=%d ci%d sum=%d co=%d"',
-          '$realtime',
-          'a',
-          'b',
-          'ci',
-          'sum',
-          'co',
-          ')',
-          ';',
-    'endmodule',
-    'module',
-      'addbit',
-      '(',
-      'a', 'b', 'ci', 'sum', 'co',
-      ')',
-      ';',
-     'input', 'a', 'b', 'ci', ';',
-      'output', 'sum', 'co', ';',
-      'wire', 'a', 'b', 'ci', 'sum', 'co', 'n1', 'n2', 'n3', ';',
-      'xor', '(', 'n1', 'a', 'b', ')', ';',
-      'xor', '(', 'sum', 'n1', 'ci', ')', ';',
-      'and', '(', 'n2', 'a', 'b', ')', ';',
-      'and', '(', 'n3', 'n1', 'ci', ')', ';',
-      'or', '(', 'co', 'n2', 'n3', ')', ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/show_all_nets_test.v.parsed.txt Deleted

@@ -1,89 +0,0 @@
-/**********************************************************************
- * $show_all_nets example -- Verilog test bench source code
- *
- * Verilog test bench to test the $show_all_nets PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module top;
-  reg  2:0 test;
-  tri  1:0 results;
-
-  addbit i1 (test0, test1, test2, results0, results1);
-
-  initial
-    begin
-      test = 3'b000;
-      #10 test = 3'b001;
-
-      #10 $show_all_nets(top);
-      #10 $show_all_nets(i1);
-
-      #10 $stop;
-      #10 $finish;
-    end
-endmodule
-
-/*** A gate level 1 bit adder model ***/
-`timescale 1ns / 1ns
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci, sum, co,
-        n1, n2, n3;
-
-  xor    (n1, a, b);
-  xor #2 (sum, n1, ci);
-  and    (n2, a, b);
-  and    (n3, n1, ci);
-  or  #2 (co, n2, n3);
-
-endmodule
-/*********************************************************************/
-
-
-
-  'module', 'top', ';',
-     'reg', '', '2', ':', '0', '', 'test', ';',
-      'tri', '', '1', ':', '0', '', 'results', ';',
-       'addbit',
-         'i1',
-           '(',
-            'test', '', '0', '',
-            'test', '', '1', '',
-            'test', '', '2', '',
-            'results', '', '0', '',
-            'results', '', '1', '',
-            ')',
-        ';',
-       'initial',
-         'begin',
-           'test', '=', "3 'b 000", ';',
-            '#', '10', 'test', '=', "3 'b 001", ';',
-            '#', '10', '$show_all_nets', '(', 'top', ')', ';',
-            '#', '10', '$show_all_nets', '(', 'i1', ')', ';',
-            '#', '10', '$stop', ';',
-            '#', '10', '$finish', ';',
-          'end',
-    'endmodule',
-    'module',
-      'addbit',
-      '(',
-      'a', 'b', 'ci', 'sum', 'co',
-      ')',
-      ';',
-     'input', 'a', 'b', 'ci', ';',
-      'output', 'sum', 'co', ';',
-      'wire', 'a', 'b', 'ci', 'sum', 'co', 'n1', 'n2', 'n3', ';',
-      'xor', '(', 'n1', 'a', 'b', ')', ';',
-      'xor', '#', '2', '(', 'sum', 'n1', 'ci', ')', ';',
-      'and', '(', 'n2', 'a', 'b', ')', ';',
-      'and', '(', 'n3', 'n1', 'ci', ')', ';',
-      'or', '#', '2', '(', 'co', 'n2', 'n3', ')', ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/show_all_signals1_test.v.parsed.txt Deleted

@@ -1,87 +0,0 @@
-/**********************************************************************
- * $show_all_signals example -- Verilog test bench source code
- *
- * Verilog test bench to test the $show_all_signals PLI application on
- * a 1-bit adder modeled using RTL code.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module top;
-  integer    test;
-  tri  1:0 results;
-
-  addbit i1 (test0, test1, test2, results0, results1);
-
-  initial
-    begin
-      test = 3'b000;
-      #10 test = 3'b001;
-
-      #10 $show_all_signals1(top);
-      #10 $show_all_signals1(i1);
-
-      #10 $stop;
-      #10 $finish;
-    end
-endmodule
-
-/*** An RTL level 1 bit adder model ***/
-`timescale 1ns / 1ns
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci;
-  reg   sum, co;
-
-  always @(a or b or ci)
-    {co, sum} = a + b + ci;
-
-endmodule
-/*********************************************************************/
-
-
-
-  'module', 'top', ';',
-     'integer', 'test', ';',
-      'tri', '', '1', ':', '0', '', 'results', ';',
-       'addbit',
-         'i1',
-           '(',
-            'test', '', '0', '',
-            'test', '', '1', '',
-            'test', '', '2', '',
-            'results', '', '0', '',
-            'results', '', '1', '',
-            ')',
-        ';',
-       'initial',
-         'begin',
-           'test', '=', "3 'b 000", ';',
-            '#', '10', 'test', '=', "3 'b 001", ';',
-            '#', '10', '$show_all_signals1', '(', 'top', ')', ';',
-            '#', '10', '$show_all_signals1', '(', 'i1', ')', ';',
-            '#', '10', '$stop', ';',
-            '#', '10', '$finish', ';',
-          'end',
-    'endmodule',
-    'module',
-      'addbit',
-      '(',
-      'a', 'b', 'ci', 'sum', 'co',
-      ')',
-      ';',
-     'input', 'a', 'b', 'ci', ';',
-      'output', 'sum', 'co', ';',
-      'wire', 'a', 'b', 'ci', ';',
-      'reg', 'sum', 'co', ';',
-       'always',
-        '@', '(', 'a', 'b', 'ci', ')',
-         '{', 'co', 'sum', '}', '=', 'a', '+', 'b', '+', 'ci',
-          ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/show_all_signals2_test.v.parsed.txt Deleted

@@ -1,89 +0,0 @@
-/**********************************************************************
- * $show_all_signals example -- Verilog test bench source code
- *
- * Verilog test bench to test the $show_all_signals PLI application on
- * a 1-bit adder modeled using RTL code.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module top;
-  integer    test;
-  tri  1:0 results;
-
-  addbit i1 (test0, test1, test2, results0, results1);
-
-  initial
-    begin
-      test = 3'b000;
-      #10 test = 3'b001;
-
-      #10 $show_all_signals2();
-      #10 $show_all_signals2(top.i1);
-
-//      #10 $stop;
-      #10 $finish;
-    end
-endmodule
-
-/*** An RTL level 1 bit adder model ***/
-`timescale 1ns / 1ns
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci;
-  reg   sum, co;
-
-  always @(a or b or ci)
-    {co, sum} = a + b + ci;
-
-  always @(sum)
-    $show_all_signals2;
-
-endmodule
-/*********************************************************************/
-
-
-  'module', 'top', ';',
-     'integer', 'test', ';',
-      'tri', '', '1', ':', '0', '', 'results', ';',
-       'addbit',
-         'i1',
-           '(',
-            'test', '', '0', '',
-            'test', '', '1', '',
-            'test', '', '2', '',
-            'results', '', '0', '',
-            'results', '', '1', '',
-            ')',
-        ';',
-       'initial',
-         'begin',
-           'test', '=', "3 'b 000", ';',
-            '#', '10', 'test', '=', "3 'b 001", ';',
-            '#', '10', '$show_all_signals2', '(', ')', ';',
-            '#', '10', '$show_all_signals2', '(', 'top.i1', ')', ';',
-            '#', '10', '$finish', ';',
-          'end',
-    'endmodule',
-    'module',
-      'addbit',
-      '(',
-      'a', 'b', 'ci', 'sum', 'co',
-      ')',
-      ';',
-     'input', 'a', 'b', 'ci', ';',
-      'output', 'sum', 'co', ';',
-      'wire', 'a', 'b', 'ci', ';',
-      'reg', 'sum', 'co', ';',
-       'always',
-        '@', '(', 'a', 'b', 'ci', ')',
-         '{', 'co', 'sum', '}', '=', 'a', '+', 'b', '+', 'ci',
-          ';',
-      'always', '@', '(', 'sum', ')', '$show_all_signals2', ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/show_all_signals3_test.v.parsed.txt Deleted

@@ -1,88 +0,0 @@
-/**********************************************************************
- * $show_all_signals example -- Verilog test bench source code
- *
- * Verilog test bench to test the $show_all_signals PLI application on
- * a 1-bit adder modeled using RTL code.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module top;
-  integer    test;
-  tri  1:0 results;
-
-  addbit i1 (test0, test1, test2, results0, results1);
-
-  initial
-    begin
-      test = 3'b000;
-      #10 test = 3'b001;
-
-      #10 $show_all_signals3(top.i1, ); /* second arg is null */
-
-//      #10 $stop;
-      #10 $finish;
-    end
-endmodule
-
-/*** An RTL level 1 bit adder model ***/
-`timescale 1ns / 1ns
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci;
-  reg   sum, co;
-
-  always @(a or b or ci)
-    {co, sum} = a + b + ci;
-
-  always @(sum)
-    $show_all_signals3;
-
-endmodule
-/*********************************************************************/
-
-
-
-  'module', 'top', ';',
-     'integer', 'test', ';',
-      'tri', '', '1', ':', '0', '', 'results', ';',
-       'addbit',
-         'i1',
-           '(',
-            'test', '', '0', '',
-            'test', '', '1', '',
-            'test', '', '2', '',
-            'results', '', '0', '',
-            'results', '', '1', '',
-            ')',
-        ';',
-       'initial',
-         'begin',
-           'test', '=', "3 'b 000", ';',
-            '#', '10', 'test', '=', "3 'b 001", ';',
-            '#', '10', '$show_all_signals3', '(', 'top.i1', ')', ';',
-            '#', '10', '$finish', ';',
-          'end',
-    'endmodule',
-    'module',
-      'addbit',
-      '(',
-      'a', 'b', 'ci', 'sum', 'co',
-      ')',
-      ';',
-     'input', 'a', 'b', 'ci', ';',
-      'output', 'sum', 'co', ';',
-      'wire', 'a', 'b', 'ci', ';',
-      'reg', 'sum', 'co', ';',
-       'always',
-        '@', '(', 'a', 'b', 'ci', ')',
-         '{', 'co', 'sum', '}', '=', 'a', '+', 'b', '+', 'ci',
-          ';',
-      'always', '@', '(', 'sum', ')', '$show_all_signals3', ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/show_all_signals_1_test.v.parsed.txt Deleted

@@ -1,104 +0,0 @@
-/**********************************************************************
- * $show_all_signals example 1 -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $show_all_signals PLI application on
- * a 1-bit adder modeled using gate primitives.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module top;
-  tri  1:0 results;
-  integer    test;
-  real       foo;
-  time       bar;
-
-  addbit i1 (test0, test1, test2, results0, results1);
-
-  initial
-    begin
-      test = 3'b000;
-      foo = 3.14;
-      bar = 0;
-      bar63:60 = 4'hF;
-      bar35:32 = 4'hA;
-      bar31:28 = 4'hC;
-      bar03:00 = 4'hE;
-      
-      #1 test = 3'b011;
-
-      #1 $show_all_signals(top);
-      #1 $show_all_signals(i1);
-
-      #1 $stop;
-      #1 $finish;
-    end
-endmodule
-
-/*** An RTL level 1 bit adder model ***/
-`timescale 1ns / 1ns
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci;
-  reg   sum, co;
-
-  always @(a or b or ci)
-    {co, sum} = a + b + ci;
-
-endmodule
-/*********************************************************************/
-
-
-
-  'module', 'top', ';',
-     'tri', '', '1', ':', '0', '', 'results', ';',
-      'integer', 'test', ';',
-      'real', 'foo', ';',
-      'time', 'bar', ';',
-       'addbit',
-         'i1',
-           '(',
-            'test', '', '0', '',
-            'test', '', '1', '',
-            'test', '', '2', '',
-            'results', '', '0', '',
-            'results', '', '1', '',
-            ')',
-        ';',
-       'initial',
-         'begin',
-           'test', '=', "3 'b 000", ';',
-            'foo', '=', '3.14', ';',
-            'bar', '=', '0', ';',
-            'bar', '', '63', '60', '', '=', "4 'h F", ';',
-            'bar', '', '35', '32', '', '=', "4 'h A", ';',
-            'bar', '', '31', '28', '', '=', "4 'h C", ';',
-            'bar', '', '03', '00', '', '=', "4 'h E", ';',
-            '#', '1', 'test', '=', "3 'b 011", ';',
-            '#', '1', '$show_all_signals', '(', 'top', ')', ';',
-            '#', '1', '$show_all_signals', '(', 'i1', ')', ';',
-            '#', '1', '$stop', ';',
-            '#', '1', '$finish', ';',
-          'end',
-    'endmodule',
-    'module',
-      'addbit',
-      '(',
-      'a', 'b', 'ci', 'sum', 'co',
-      ')',
-      ';',
-     'input', 'a', 'b', 'ci', ';',
-      'output', 'sum', 'co', ';',
-      'wire', 'a', 'b', 'ci', ';',
-      'reg', 'sum', 'co', ';',
-       'always',
-        '@', '(', 'a', 'b', 'ci', ')',
-         '{', 'co', 'sum', '}', '=', 'a', '+', 'b', '+', 'ci',
-          ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/show_all_signals_2_test.v.parsed.txt Deleted

@@ -1,96 +0,0 @@
-/**********************************************************************
- * $show_all_signals example 2 -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $show_all_signals PLI application on
- * a 1-bit adder modeled using gate primitives.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module top;
-  integer    test;
-  tri  1:0 results;
-
-  addbit i1 (test0, test1, test2, results0, results1);
-
-  initial
-    begin: local
-      reg foobar;
-      test = 3'b000;
-      #1 test = 3'b011;
-
-      #1 $show_all_signals;
-      #1 $show_all_signals(top.i1);
-
-//      #1 $stop;
-      #1 $finish;
-    end
-endmodule
-
-/*** An RTL level 1 bit adder model ***/
-`timescale 1ns / 1ns
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci;
-  reg   sum, co;
-
-  always @(a or b or ci)
-    {co, sum} = a + b + ci;
-
-  always @(sum)
-    $show_all_signals();
-
-endmodule
-/*********************************************************************/
-
-
-
-  'module', 'top', ';',
-     'integer', 'test', ';',
-      'tri', '', '1', ':', '0', '', 'results', ';',
-       'addbit',
-         'i1',
-           '(',
-            'test', '', '0', '',
-            'test', '', '1', '',
-            'test', '', '2', '',
-            'results', '', '0', '',
-            'results', '', '1', '',
-            ')',
-        ';',
-       'initial',
-         'begin',
-          ':',
-          'local',
-          'reg', 'foobar', ';',
-          'test', '=', "3 'b 000", ';',
-          '#', '1', 'test', '=', "3 'b 011", ';',
-          '#', '1', '$show_all_signals', ';',
-          '#', '1', '$show_all_signals', '(', 'top.i1', ')', ';',
-          '#', '1', '$finish', ';',
-          'end',
-    'endmodule',
-    'module',
-      'addbit',
-      '(',
-      'a', 'b', 'ci', 'sum', 'co',
-      ')',
-      ';',
-     'input', 'a', 'b', 'ci', ';',
-      'output', 'sum', 'co', ';',
-      'wire', 'a', 'b', 'ci', ';',
-      'reg', 'sum', 'co', ';',
-       'always',
-        '@', '(', 'a', 'b', 'ci', ')',
-         '{', 'co', 'sum', '}', '=', 'a', '+', 'b', '+', 'ci',
-          ';',
-       'always',
-        '@', '(', 'sum', ')',
-        '$show_all_signals', '(', ')', ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/show_all_signals_3_test.v.parsed.txt Deleted

@@ -1,89 +0,0 @@
-/**********************************************************************
- * $show_all_signals example 3 -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $show_all_signals PLI application on
- * a 1-bit adder modeled using gate primitives.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module top;
-  integer    test;
-  tri  1:0 results;
-
-  addbit i1 (test0, test1, test2, results0, results1);
-
-  initial
-    begin
-      test = 3'b000;
-      #1 test = 3'b001;
-
-      #1 $show_all_signals(top.i1, ,top); /* second arg is null */
-
-//      #1 $stop;
-      #1 $finish;
-    end
-endmodule
-
-/*** An RTL level 1 bit adder model ***/
-`timescale 1ns / 1ns
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci;
-  reg   sum, co;
-
-  always @(a or b or ci)
-    {co, sum} = a + b + ci;
-
-  always @(sum)
-    $show_all_signals;
-
-endmodule
-/*********************************************************************/
-
-
-
-  'module', 'top', ';',
-     'integer', 'test', ';',
-      'tri', '', '1', ':', '0', '', 'results', ';',
-       'addbit',
-         'i1',
-           '(',
-            'test', '', '0', '',
-            'test', '', '1', '',
-            'test', '', '2', '',
-            'results', '', '0', '',
-            'results', '', '1', '',
-            ')',
-        ';',
-       'initial',
-         'begin',
-           'test', '=', "3 'b 000", ';',
-            '#', '1', 'test', '=', "3 'b 001", ';',
-             '#', '1',
-              '$show_all_signals', '(', 'top.i1', 'top', ')', ';',
-            '#', '1', '$finish', ';',
-          'end',
-    'endmodule',
-    'module',
-      'addbit',
-      '(',
-      'a', 'b', 'ci', 'sum', 'co',
-      ')',
-      ';',
-     'input', 'a', 'b', 'ci', ';',
-      'output', 'sum', 'co', ';',
-      'wire', 'a', 'b', 'ci', ';',
-      'reg', 'sum', 'co', ';',
-       'always',
-        '@', '(', 'a', 'b', 'ci', ')',
-         '{', 'co', 'sum', '}', '=', 'a', '+', 'b', '+', 'ci',
-          ';',
-      'always', '@', '(', 'sum', ')', '$show_all_signals', ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/show_value_test.v.parsed.txt Deleted

@@ -1,95 +0,0 @@
-/**********************************************************************
- * $show_value example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $show_value PLI application on a 
- * 1-bit adder modeled using gate primitives.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-  reg  a, b, ci, clk;
-  wire sum, co;
-
-  addbit i1 (a, b, ci, sum, co);
-
-  initial
-    begin
-//      $monitor("At %0d: \t a=%b  b=%b  ci=%b  sum=%b  co=%b",
-//               $time, a, b, ci, sum, co);
-      clk = 0;
-      a = 0;
-      b = 0;
-      ci = 0;
-      #10 a = 1;
-      #10 b = 1;
-
-      $show_value(sum);
-      $show_value(co);
-      $show_value(i1.n3);
-
-      #10 $stop;
-      $finish;
-    end
-endmodule
-
-/*** A gate level 1 bit adder model ***/
-`timescale 1ns / 1ns
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci, sum, co,
-        n1, n2, n3;
-
-  xor    (n1, a, b);
-  xor #2 (sum, n1, ci);
-  and    (n2, a, b);
-  and    (n3, n1, ci);
-  or  #2 (co, n2, n3);
-
-endmodule
-/**********************************************************************/
-
-
-
-  'module', 'test', ';',
-     'reg', 'a', 'b', 'ci', 'clk', ';',
-      'wire', 'sum', 'co', ';',
-       'addbit',
-        'i1', '(', 'a', 'b', 'ci', 'sum', 'co', ')',
-        ';',
-       'initial',
-         'begin',
-           'clk', '=', '0', ';',
-            'a', '=', '0', ';',
-            'b', '=', '0', ';',
-            'ci', '=', '0', ';',
-            '#', '10', 'a', '=', '1', ';',
-            '#', '10', 'b', '=', '1', ';',
-            '$show_value', '(', 'sum', ')', ';',
-            '$show_value', '(', 'co', ')', ';',
-            '$show_value', '(', 'i1.n3', ')', ';',
-            '#', '10', '$stop', ';',
-            '$finish', ';',
-          'end',
-    'endmodule',
-    'module',
-      'addbit',
-      '(',
-      'a', 'b', 'ci', 'sum', 'co',
-      ')',
-      ';',
-     'input', 'a', 'b', 'ci', ';',
-      'output', 'sum', 'co', ';',
-      'wire', 'a', 'b', 'ci', 'sum', 'co', 'n1', 'n2', 'n3', ';',
-      'xor', '(', 'n1', 'a', 'b', ')', ';',
-      'xor', '#', '2', '(', 'sum', 'n1', 'ci', ')', ';',
-      'and', '(', 'n2', 'a', 'b', ')', ';',
-      'and', '(', 'n3', 'n1', 'ci', ')', ';',
-      'or', '#', '2', '(', 'co', 'n2', 'n3', ')', ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/sig_gen.v.parsed.txt Deleted

@@ -1,49 +0,0 @@
-// Verilog HDL for "gates.lib", "sig_gen" "_functional"
-// Module sig pulse generator
-module sig_gen(out);
-
-output
-	out;
-reg
-	out;
-
-// Declaration of data types
-parameter
-	sig_delay=10,
-	sig_period=100;
-
-initial		// Execute at time 0
-	begin	
-		out = 0;
-		#(sig_delay -1) out = 1;
-		#2 out = 0;
-
-		forever		// Repeat forever
-		  begin
-			#(sig_period - 2) out = 1;
-			#2 out = 0;
-		  end
-
-	end
-
-endmodule
-
-
-  'module', 'sig_gen', '(', 'out', ')', ';',
-     'output', 'out', ';',
-      'reg', 'out', ';',
-      'parameter', 'sig_delay', '=', '10', 'sig_period', '=', '100', ';',
-       'initial',
-         'begin',
-           'out', '=', '0', ';',
-             '#', '(', 'sig_delay', '-', '1', ')',
-              'out', '=', '1', ';',
-            '#', '2', 'out', '=', '0', ';',
-             'forever',
-               'begin',
-                  '#', '(', 'sig_period', '-', '2', ')',
-                    'out', '=', '1', ';',
-                  '#', '2', 'out', '=', '0', ';',
-                'end',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/simple_core.v.parsed.txt Deleted

@@ -1,318 +0,0 @@
-/* simple_core */
-// Author Andrew Laffely
-// Last modified: 12 Feb 03
-
-module adder_core (reset, hold, in_ready, out_ready, data_in, data_out, read, write, in_addr, out_addr);
-input reset, hold;                // External control signals
-input 2:0 in_ready, out_ready;  // Input and Output port ready registers
-input 31:0 data_in;             // Input data
-
-output read, write;               // Read and Write signals
-output 31:0 data_out;
-output 1:0 in_addr, out_addr;   // Port addresses.
-reg read, write; 
-reg 31:0 data_out;
-reg 1:0 in_addr, out_addr;   
-
-reg 31:0 opA, opB;
-reg 31:0 res;
-reg ops_ready, res_ready; //Internal flow conrol
-reg stall, go;
-  
-reg lclock;
-initial
-begin
-	#3 lclock = 1'b0;
-	forever #47 lclock = ~lclock;  // Use 10 or 20 or 40 or 80 etc.
-end
-
-/*********************** READ DATA *****************************/
-always @ (posedge lclock)
-  begin
-	#1 if(((!ops_ready)||(!stall))&&(!hold)&&(!reset))  
-	// Do not read anymore if full and stalled
-		if(in_readyin_addr)  // check port
-			read = 1;
-  end
-
-always @ (negedge lclock)
-  begin
-	read = 0;
-  end
-
-always @ (negedge read)
-  begin
-    if (!reset)
-      begin
-	if ((in_addr0)&&(!hold))
-	  begin
-		opB=data_in;
-		ops_ready=1;
-	  end
-	else
-	  begin
-		opA=data_in;
-	  end
-	$display("In Core=%h addr=%b ops_ready=%b",data_in, in_addr, ops_ready);
-	#1 in_addr0=~in_addr0;   // next data	
-      end
-  end
-/********************* End READ DATA ***************************/
-
-/*********************** Write DATA ****************************/
-always @ (posedge lclock)
-  begin
-	if((res_ready)&&(!hold)&&(!reset)) // wait until the pipe is full
-		if(out_readyout_addr)  // check port
-			write = 1;
-  end
-
-always @ (negedge lclock)
-  begin
-	write = 0;
-  end
-
-always @ (negedge write)
-  begin
-	if(!reset)
-	  begin
-		data_out=res;
-		$display("Out Core=%h out_addr=%b ops_ready=%b",data_out, out_addr, ops_ready);
-	res_ready=0;
-	  end
-  end
-/******************** End Write DATA ***************************/
-
-/************************ Reset ********************************/
-always @ (reset)
-  begin
-	read=0;
-	write=0;
-	in_addr=0;
-	out_addr=0;
-	ops_ready=0;
-	res_ready=0;
-	stall = 0;
-  end
-/*********************** End Reset *****************************/
-
-/******************* Core flow Control *************************/
-// stall tells the pipeline to stop adding and stop taking in data
-always @ (posedge lclock)
-  begin
-	if(!out_readyout_addr)
-		stall = 1;
-  end
-
-always @ (posedge out_readyout_addr)
-  begin
-	stall=0;
-  end
-/******************* End flow Control *************************/
-
-/************************ Proccessing *************************/
-always @ (posedge lclock)
-  begin
-	if((ops_ready)&&(!stall)&&(!hold))
-	  begin
-		res=opA+opB;  //Wow this 32 bit adder is fast
-		res_ready=1;
-		ops_ready=0;
-		
-	  end
-  end
-/********************* End Proccessing *************************/
-endmodule
-
-
-   'module',
-      'adder_core',
-      '(',
-       'reset',
-        'hold',
-        'in_ready',
-        'out_ready',
-        'data_in',
-        'data_out',
-        'read',
-        'write',
-        'in_addr',
-        'out_addr',
-      ')',
-      ';',
-     'input', 'reset', 'hold', ';',
-      'input', '', '2', ':', '0', '', 'in_ready', 'out_ready', ';',
-      'input', '', '31', ':', '0', '', 'data_in', ';',
-      'output', 'read', 'write', ';',
-      'output', '', '31', ':', '0', '', 'data_out', ';',
-      'output', '', '1', ':', '0', '', 'in_addr', 'out_addr', ';',
-      'reg', 'read', 'write', ';',
-      'reg', '', '31', ':', '0', '', 'data_out', ';',
-      'reg', '', '1', ':', '0', '', 'in_addr', 'out_addr', ';',
-      'reg', '', '31', ':', '0', '', 'opA', 'opB', ';',
-      'reg', '', '31', ':', '0', '', 'res', ';',
-      'reg', 'ops_ready', 'res_ready', ';',
-      'reg', 'stall', 'go', ';',
-      'reg', 'lclock', ';',
-       'initial',
-         'begin',
-           '#', '3', 'lclock', '=', "1 'b 0", ';',
-             'forever',
-              '#', '47', 'lclock', '=', '~', 'lclock', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'lclock', ')',
-         'begin',
-            '#', '1',
-               'if',
-                 '(',
-                  '(',
-                   '(',
-                    '!', 'ops_ready',
-                    ')',
-                    '||',
-                    '(',
-                    '!', 'stall',
-                    ')',
-                  ')',
-                  '&&',
-                  '(',
-                  '!', 'hold',
-                  ')',
-                  '&&',
-                  '(',
-                  '!', 'reset',
-                  ')',
-                  ')',
-                 'if',
-                  '(', 'in_ready', '', 'in_addr', '', ')',
-                  'read', '=', '1', ';',
-          'end',
-       'always',
-        '@', '(', 'negedge', 'lclock', ')',
-        'begin', 'read', '=', '0', ';', 'end',
-       'always',
-        '@', '(', 'negedge', 'read', ')',
-         'begin',
-            'if',
-              '(', '!', 'reset', ')',
-               'begin',
-                  'if',
-                     '(',
-                      '(',
-                      'in_addr', '', '0', '',
-                      ')',
-                      '&&',
-                      '(',
-                      '!', 'hold',
-                      ')',
-                      ')',
-                     'begin',
-                       'opB', '=', 'data_in', ';',
-                        'ops_ready', '=', '1', ';',
-                      'end',
-                    'else',
-                    'begin', 'opA', '=', 'data_in', ';', 'end',
-                   '$display',
-                    '(',
-                    '"In Core=%h addr=%b ops_ready=%b"',
-                    'data_in',
-                    'in_addr',
-                    'ops_ready',
-                    ')',
-                    ';',
-                   '#', '1',
-                      'in_addr', '', '0', '',
-                        '=',
-                        '~',
-                        'in_addr', '', '0', '',
-                      ';',
-                'end',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'lclock', ')',
-         'begin',
-            'if',
-               '(',
-                '(',
-                'res_ready',
-                ')',
-                '&&',
-                '(',
-                '!', 'hold',
-                ')',
-                '&&',
-                '(',
-                '!', 'reset',
-                ')',
-                ')',
-               'if',
-                '(', 'out_ready', '', 'out_addr', '', ')',
-                'write', '=', '1', ';',
-          'end',
-       'always',
-        '@', '(', 'negedge', 'lclock', ')',
-        'begin', 'write', '=', '0', ';', 'end',
-       'always',
-        '@', '(', 'negedge', 'write', ')',
-         'begin',
-            'if',
-              '(', '!', 'reset', ')',
-               'begin',
-                 'data_out', '=', 'res', ';',
-                   '$display',
-                    '(',
-                    '"Out Core=%h out_addr=%b ops_ready=%b"',
-                    'data_out',
-                    'out_addr',
-                    'ops_ready',
-                    ')',
-                    ';',
-                  'res_ready', '=', '0', ';',
-                'end',
-          'end',
-       'always',
-        '@', '(', 'reset', ')',
-         'begin',
-           'read', '=', '0', ';',
-            'write', '=', '0', ';',
-            'in_addr', '=', '0', ';',
-            'out_addr', '=', '0', ';',
-            'ops_ready', '=', '0', ';',
-            'res_ready', '=', '0', ';',
-            'stall', '=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'lclock', ')',
-         'begin',
-            'if',
-              '(', '!', 'out_ready', '', 'out_addr', '', ')',
-              'stall', '=', '1', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'out_ready', '', 'out_addr', '', ')',
-        'begin', 'stall', '=', '0', ';', 'end',
-       'always',
-        '@', '(', 'posedge', 'lclock', ')',
-         'begin',
-            'if',
-               '(',
-                '(',
-                'ops_ready',
-                ')',
-                '&&',
-                '(',
-                '!', 'stall',
-                ')',
-                '&&',
-                '(',
-                '!', 'hold',
-                ')',
-                ')',
-               'begin',
-                 'res', '=', 'opA', '+', 'opB', ';',
-                  'res_ready', '=', '1', ';',
-                  'ops_ready', '=', '0', ';',
-                'end',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/splitter.v.parsed.txt Deleted

@@ -1,52 +0,0 @@
-// Verilog HDL for "gates.lib", "splitter" "_functional"
-// SPLITTER
-module splitter (in, out1, out2);
-
-input
-	in;
-
-output
-	out1, out2;
-reg 
-	out1, out2;
-
-parameter
-	delay	= 10;
-
-initial 
-	begin
-		out1 = 0;
-		out2 = 0;
-	end
-
-always @(posedge in) 	// Execute at positive edge of in
-	begin
-	  out1 <= #delay in;
-	  out1 <= #(delay+2) 0;
-	  out2 <= #delay in;
-	  out2 <= #(delay+2) 0;
-	end
-
-endmodule
-
-
-  'module', 'splitter', '(', 'in', 'out1', 'out2', ')', ';',
-     'input', 'in', ';',
-      'output', 'out1', 'out2', ';',
-      'reg', 'out1', 'out2', ';',
-      'parameter', 'delay', '=', '10', ';',
-       'initial',
-         'begin',
-          'out1', '=', '0', ';', 'out2', '=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'in', ')',
-         'begin',
-           'out1', '<=', '#', 'delay', 'in', ';',
-             'out1', '<=', '#', '(', 'delay', '+', '2', ')', '0',
-              ';',
-            'out2', '<=', '#', 'delay', 'in', ';',
-             'out2', '<=', '#', '(', 'delay', '+', '2', ')', '0',
-              ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/sqrt32.v.parsed.txt Deleted

@@ -1,2305 +0,0 @@
-// sqrt32.v unsigned integer sqrt 32-bits computing unsigned integer 16-bits
-//   sqrt(00000000000000000000000000000100) = 0000000000000010   sqrt(4)=2
-//   sqrt(00000000000000000000000001000000) = 0000000000001000   sqrt(64)=8
-
-`timescale 1ns/1ns
-
-module Sm(x, y, b, u, d, bo);  // subtractor multiplexor 
-  input  x;
-  input  y;
-  input  b;
-  input  u;
-  output d;
-  output bo;
-
-  wire t011, t111, t010, t001, t100, td;
-  wire x_, y_, b_, u_, if_td, if_x;
-
-  // circuits of Sm
-  not notx(x_, x);
-  not noty(y_, y);
-  not notb(b_, b);
-  and a011(t011, x_, y,  b );
-  and a111(t111, x,  y,  b );
-  and a010(t010, x_, y,  b_);
-  and a001(t001, x_, y_, b );
-  and a100(t100, x,  y_, b_);
-  or  #1 or1(bo, t011, t111, t010, t001);
-  or  or2(td, t100, t001, t010, t111);
-  not notu(u_, u);  // four gate mux
-  and atd(if_td, td, u); 
-  and ax (if_x,   x, u_);
-  or  #1 or3(d, if_td, if_x);
-endmodule  // Sm
-
-module Sb(x, y, b, bo);  // subtractor multiplexor stage b 
-  input  x;
-  input  y;
-  input  b;
-  output bo;
-
-  wire t011, t111, t010, t001;
-  wire x_, y_, b_;
-
-  // circuits of Sb
-  not n01(x_, x);
-  not n02(y_, y);
-  not n03(b_, b);
-  and a011(t011, x_, y,  b);
-  and a111(t111, x,  y,  b);
-  and a010(t010, x_, y,  b_);
-  and a001(t001, x_, y_,  b);
-  or #1 bor(bo, t011, t111, t010, t001);
-endmodule  // Sb
-
-module S1(x, b, u, d, bo);  // subtractor multiplexor stage 1
-  input  x;
-  input  b;
-  input  u;
-  output d;
-  output bo;
-
-  wire t100, t001, td;
-  wire x_, b_, u_, if_td, if_x;
-
-  // circuits of S1
-  not not1(x_, x);
-  not not2(b_, b);
-  and a011(t001, x_,  b);
-  and a100(t100, x,   b_);
-  buf #1 buf1(bo, t001);
-  or or1(td, t100, t001);
-  not notu(u_, u);  // four gate mux
-  and atd(if_td, td, u); 
-  and ax (if_x,   x, u_);
-  or  #1 or3(d, if_td, if_x);
-endmodule  //  S1
-
-module S0(x, u, d, bo);    // subtractor multiplexor stage 0
-  input  x;
-  input  u;
-  output d;
-  output bo;
-
-  wire u_, if_bo, if_x;
-
-  // circuits of S0
-  not #1 n1(bo, x);
-  not notu(u_, u);  // four gate mux
-  and atd(if_bo, bo, u); 
-  and ax (if_x,   x, u_);
-  or  #1 or3(d, if_bo, if_x);
-endmodule  //  S0
-
-module Sn(x, b, bo); // subtractor multiplexor stage n 
-  input  x;
-  input  b;
-  output bo;
-
-  wire x_;
-
-  // circuits of Sn, complemented
-  not  n00(x_, x);
-  nand #1 n01(bo, x_, b);
-endmodule  //  Sn
-
-module S0b(x, bo);   // subtractor multiplexor stage 0b
-  input  x;
-  output bo;
-
-  // circuits of S0b
-  not #1 n0(bo, x);
-endmodule  //  S0b
-
-module S1b(x, b, bo);     // subtractor multiplexor stage 1b
-  input  x;
-  input  b;
-  output bo;
-
-  wire x_;
-
-  // circuits of S1b
-  not n00(x_, x);
-  and #1 n01(bo, x_, b);
-endmodule  //  S1b
-
-
-module sqrt32(P, U);
-  input 31:0 P;
-  output 15:0 U;
-
-  wire b0000, b0001, b0002, b0003, b0004, b0005, b0006, b0007, b0008,
-       b0009, b0010, b0011, b0012, b0013, b0014, b0015, b0016, b0017;  
-  wire x0102, x0103, x0104, x0105, x0106, x0107, x0108, x0109, x0110,
-       x0111, x0112, x0113, x0114, x0115, x0116, x0117;  
-  wire b0102, b0103, b0104, b0105, b0106, b0107, b0108, b0109, b0110,
-       b0111, b0112, b0113, b0114, b0115, b0116, b0117, b0118;
-  wire x0204, x0205, x0206, x0207, x0208, x0209, x0210, x0211, x0212,
-       x0213, x0214, x0215, x0216, x0217, x0218;  
-  wire b0204, b0205, b0206, b0207, b0208, b0209, b0210, b0211, b0212,
-       b0213, b0214, b0215, b0216, b0217, b0218, b0219;  
-  wire x0306, x0307, x0308, x0309, x0310, x0311, x0312, x0313, x0314,
-       x0315, x0316, x0317, x0318, x0319;  
-  wire b0306, b0307, b0308, b0309, b0310, b0311, b0312, b0313, b0314,
-       b0315, b0316, b0317, b0318, b0319, b0320;  
-  wire x0408, x0409, x0410, x0411, x0412, x0413, x0414, x0415, x0416,
-       x0417, x0418, x0419, x0420;  
-  wire b0408, b0409, b0410, b0411, b0412, b0413, b0414, b0415, b0416,
-       b0417, b0418, b0419, b0420, b0421;  
-  wire x0510, x0511, x0512, x0513, x0514, x0515, x0516, x0517, x0518,
-       x0519, x0520, x0521;  
-  wire b0510, b0511, b0512, b0513, b0514, b0515, b0516, b0517, b0518,
-       b0519, b0520, b0521, b0522;  
-  wire x0612, x0613, x0614, x0615, x0616, x0617, x0618, x0619, x0620,
-       x0621, x0622;  
-  wire b0612, b0613, b0614, b0615, b0616, b0617, b0618, b0619, b0620,
-       b0621, b0622, b0623;  
-  wire x0714, x0715, x0716, x0717, x0718, x0719, x0720, x0721, x0722,
-       x0723;  
-  wire b0714, b0715, b0716, b0717, b0718, b0719, b0720, b0721, b0722,
-       b0723, b0724;  
-  wire x0816, x0817, x0818, x0819, x0820, x0821, x0822, x0823, x0824;  
-  wire b0816, b0817, b0818, b0819, b0820, b0821, b0822, b0823, b0824,
-       b0825;  
-  wire x0918, x0919, x0920, x0921, x0922, x0923, x0924, x0925;  
-  wire b0918, b0919, b0920, b0921, b0922, b0923, b0924, b0925, b0926;  
-  wire x1020, x1021, x1022, x1023, x1024, x1025, x1026;  
-  wire b1020, b1021, b1022, b1023, b1024, b1025, b1026, b1027;  
-  wire x1122, x1123, x1124, x1125, x1126, x1127;  
-  wire b1122, b1123, b1124, b1125, b1126, b1127, b1128;  
-  wire x1224, x1225, x1226, x1227, x1228;  
-  wire b1224, b1225, b1226, b1227, b1228, b1229;  
-  wire x1326, x1327, x1328, x1329;  
-  wire b1326, b1327, b1328, b1329, b1330;  
-  wire x1428, x1429, x1430;  
-  wire b1428, b1429, b1430, b1431;  
-  wire x1530, x1531;  
-  wire b1530, b1531, bxx;  
-
-  //                              x      y      b      u      d      bo
-  S0 s1530(P30,               b1531, x1530, b1530);
-  S1 s1531(P31,        b1530, b1531, x1531, bxx );
-  not n1(b1531, bxx);
-
-  S0 s1428(P28,               b1431, x1428, b1428);
-  S1 s1429(P29,        b1428, b1431, x1429, b1429);
-  Sm s1430(x1530, b1531, b1429, b1431, x1430, b1430);
-  Sn s1431(x1531,        b1430,               b1431);
-  
-  S0 s1326(P26,               b1330, x1326, b1326);
-  S1 s1327(P27,        b1326, b1330, x1327, b1327);
-  Sm s1328(x1428, b1431, b1327, b1330, x1328, b1328);
-  Sm s1329(x1429, b1531, b1328, b1330, x1329, b1329);
-  Sn s1330(x1430,        b1329,               b1330);
-
-  S0 s1224(P24,               b1229, x1224, b1224);
-  S1 s1225(P25,        b1224, b1229, x1225, b1225);
-  Sm s1226(x1326, b1330, b1225, b1229, x1226, b1226);
-  Sm s1227(x1327, b1431, b1226, b1229, x1227, b1227);
-  Sm s1228(x1328, b1531, b1227, b1229, x1228, b1228);
-  Sn s1229(x1329,        b1228,               b1229);
-
-  S0 s1122(P22,               b1128, x1122, b1122);
-  S1 s1123(P23,        b1122, b1128, x1123, b1123);
-  Sm s1124(x1224, b1229, b1123, b1128, x1124, b1124);
-  Sm s1125(x1225, b1330, b1124, b1128, x1125, b1125);
-  Sm s1126(x1226, b1431, b1125, b1128, x1126, b1126);
-  Sm s1127(x1227, b1531, b1126, b1128, x1127, b1127);
-  Sn s1128(x1228,        b1127,               b1128);
-
-  S0 s1020(P20,               b1027, x1020, b1020);
-  S1 s1021(P21,        b1020, b1027, x1021, b1021);
-  Sm s1022(x1122, b1128, b1021, b1027, x1022, b1022);
-  Sm s1023(x1123, b1229, b1022, b1027, x1023, b1023);
-  Sm s1024(x1124, b1330, b1023, b1027, x1024, b1024);
-  Sm s1025(x1125, b1431, b1024, b1027, x1025, b1025);
-  Sm s1026(x1126, b1531, b1025, b1027, x1026, b1026);
-  Sn s1027(x1127,        b1026,               b1027);
-
-  S0 s0918(P18,               b0926, x0918, b0918);
-  S1 s0919(P19,        b0918, b0926, x0919, b0919);
-  Sm s0920(x1020, b1027, b0919, b0926, x0920, b0920);
-  Sm s0921(x1021, b1128, b0920, b0926, x0921, b0921);
-  Sm s0922(x1022, b1229, b0921, b0926, x0922, b0922);
-  Sm s0923(x1023, b1330, b0922, b0926, x0923, b0923);
-  Sm s0924(x1024, b1431, b0923, b0926, x0924, b0924);
-  Sm s0925(x1025, b1531, b0924, b0926, x0925, b0925);
-  Sn s0926(x1026,        b0925,               b0926);
-
-  S0 s0816(P16,               b0825, x0816, b0816);
-  S1 s0817(P17,        b0816, b0825, x0817, b0817);
-  Sm s0818(x0918, b0926, b0817, b0825, x0818, b0818);
-  Sm s0819(x0919, b1027, b0818, b0825, x0819, b0819);
-  Sm s0820(x0920, b1128, b0819, b0825, x0820, b0820);
-  Sm s0821(x0921, b1229, b0820, b0825, x0821, b0821);
-  Sm s0822(x0922, b1330, b0821, b0825, x0822, b0822);
-  Sm s0823(x0923, b1431, b0822, b0825, x0823, b0823);
-  Sm s0824(x0924, b1531, b0823, b0825, x0824, b0824);
-  Sn s0825(x0925,        b0824,               b0825);
-
-  S0 s0714(P14,               b0724, x0714, b0714);
-  S1 s0715(P15,        b0714, b0724, x0715, b0715);
-  Sm s0716(x0816, b0825, b0715, b0724, x0716, b0716);
-  Sm s0717(x0817, b0926, b0716, b0724, x0717, b0717);
-  Sm s0718(x0818, b1027, b0717, b0724, x0718, b0718);
-  Sm s0719(x0819, b1128, b0718, b0724, x0719, b0719);
-  Sm s0720(x0820, b1229, b0719, b0724, x0720, b0720);
-  Sm s0721(x0821, b1330, b0720, b0724, x0721, b0721);
-  Sm s0722(x0822, b1431, b0721, b0724, x0722, b0722);
-  Sm s0723(x0823, b1531, b0722, b0724, x0723, b0723);
-  Sn s0724(x0824,        b0723,               b0724);
- 
-  S0 s0612(P12,               b0623, x0612, b0612);
-  S1 s0613(P13,        b0612, b0623, x0613, b0613);
-  Sm s0614(x0714, b0724, b0613, b0623, x0614, b0614);
-  Sm s0615(x0715, b0825, b0614, b0623, x0615, b0615);
-  Sm s0616(x0716, b0926, b0615, b0623, x0616, b0616);
-  Sm s0617(x0717, b1027, b0616, b0623, x0617, b0617);
-  Sm s0618(x0718, b1128, b0617, b0623, x0618, b0618);
-  Sm s0619(x0719, b1229, b0618, b0623, x0619, b0619);
-  Sm s0620(x0720, b1330, b0619, b0623, x0620, b0620);
-  Sm s0621(x0721, b1431, b0620, b0623, x0621, b0621);
-  Sm s0622(x0722, b1531, b0621, b0623, x0622, b0622);
-  Sn s0623(x0723,        b0622,               b0623);
-  
-  S0 s0510(P10,               b0522, x0510, b0510);
-  S1 s0511(P11,        b0510, b0522, x0511, b0511);
-  Sm s0512(x0612, b0622, b0511, b0522, x0512, b0512);
-  Sm s0513(x0613, b0723, b0512, b0522, x0513, b0513);
-  Sm s0514(x0614, b0825, b0513, b0522, x0514, b0514);
-  Sm s0515(x0615, b0926, b0514, b0522, x0515, b0515);
-  Sm s0516(x0616, b1027, b0515, b0522, x0516, b0516);
-  Sm s0517(x0617, b1128, b0516, b0522, x0517, b0517);
-  Sm s0518(x0618, b1229, b0517, b0522, x0518, b0518);
-  Sm s0519(x0619, b1330, b0518, b0522, x0519, b0519);
-  Sm s0520(x0620, b1431, b0519, b0522, x0520, b0520);
-  Sm s0521(x0621, b1531, b0520, b0522, x0521, b0521);
-  Sn s0522(x0622,        b0521,               b0522);
-
-  S0 s0408(P8,                b0421, x0408, b0408);
-  S1 s0409(P9,         b0408, b0421, x0409, b0409);
-  Sm s0410(x0510, b0522, b0409, b0421, x0410, b0410);
-  Sm s0411(x0511, b0623, b0410, b0421, x0411, b0411);
-  Sm s0412(x0512, b0724, b0411, b0421, x0412, b0412);
-  Sm s0413(x0513, b0825, b0412, b0421, x0413, b0413);
-  Sm s0414(x0514, b0926, b0413, b0421, x0414, b0414);
-  Sm s0415(x0515, b1027, b0414, b0421, x0415, b0415);
-  Sm s0416(x0516, b1128, b0415, b0421, x0416, b0416);
-  Sm s0417(x0517, b1229, b0416, b0421, x0417, b0417);
-  Sm s0418(x0518, b1330, b0417, b0421, x0418, b0418);
-  Sm s0419(x0519, b1431, b0418, b0421, x0419, b0419);
-  Sm s0420(x0520, b1531, b0419, b0421, x0420, b0420);
-  Sn s0421(x0521,        b0420,               b0421);
-
-  S0 s0306(P6,                b0320, x0306, b0306);
-  S1 s0307(P7,         b0306, b0320, x0307, b0307);
-  Sm s0308(x0408, b0421, b0307, b0320, x0308, b0308);
-  Sm s0309(x0409, b0522, b0308, b0320, x0309, b0309);
-  Sm s0310(x0410, b0623, b0309, b0320, x0310, b0310);
-  Sm s0311(x0411, b0724, b0310, b0320, x0311, b0311);
-  Sm s0312(x0412, b0825, b0311, b0320, x0312, b0312);
-  Sm s0313(x0413, b0926, b0312, b0320, x0313, b0313);
-  Sm s0314(x0414, b1027, b0313, b0320, x0314, b0314);
-  Sm s0315(x0415, b1128, b0314, b0320, x0315, b0315);
-  Sm s0316(x0416, b1229, b0315, b0320, x0316, b0316);
-  Sm s0317(x0417, b1330, b0316, b0320, x0317, b0317);
-  Sm s0318(x0418, b1431, b0317, b0320, x0318, b0318);
-  Sm s0319(x0419, b1531, b0318, b0320, x0319, b0319);
-  Sn s0320(x0420,        b0319,               b0320);
-
-  S0 s0204(P4,                b0219, x0204, b0204);
-  S1 s0205(P5,         b0204, b0219, x0205, b0205);
-  Sm s0206(x0306, b0320, b0205, b0219, x0206, b0206);
-  Sm s0207(x0307, b0421, b0206, b0219, x0207, b0207);
-  Sm s0208(x0308, b0522, b0207, b0219, x0208, b0208);
-  Sm s0209(x0309, b0623, b0208, b0219, x0209, b0209);
-  Sm s0210(x0310, b0724, b0209, b0219, x0210, b0210);
-  Sm s0211(x0311, b0825, b0210, b0219, x0211, b0211);
-  Sm s0212(x0312, b0926, b0211, b0219, x0212, b0212);
-  Sm s0213(x0313, b1027, b0212, b0219, x0213, b0213);
-  Sm s0214(x0314, b1128, b0213, b0219, x0214, b0214);
-  Sm s0215(x0315, b1229, b0214, b0219, x0215, b0215);
-  Sm s0216(x0316, b1330, b0215, b0219, x0216, b0216);
-  Sm s0217(x0317, b1431, b0216, b0219, x0217, b0217);
-  Sm s0218(x0318, b1531, b0217, b0219, x0218, b0218);
-  Sn s0219(x0319,        b0218,               b0219);
-
-  S0 s0102(P2,                b0118, x0102, b0102);
-  S1 s0103(P3,         b0102, b0118, x0103, b0103);
-  Sm s0104(x0204, b0219, b0103, b0118, x0104, b0104);
-  Sm s0105(x0205, b0320, b0104, b0118, x0105, b0105);
-  Sm s0106(x0206, b0421, b0105, b0118, x0106, b0106);
-  Sm s0107(x0207, b0522, b0106, b0118, x0107, b0107);
-  Sm s0108(x0208, b0623, b0107, b0118, x0108, b0108);
-  Sm s0109(x0209, b0724, b0108, b0118, x0109, b0109);
-  Sm s0110(x0210, b0825, b0109, b0118, x0110, b0110);
-  Sm s0111(x0211, b0926, b0110, b0118, x0111, b0111);
-  Sm s0112(x0212, b1027, b0111, b0118, x0112, b0112);
-  Sm s0113(x0213, b1128, b0112, b0118, x0113, b0113);
-  Sm s0114(x0214, b1229, b0113, b0118, x0114, b0114);
-  Sm s0115(x0215, b1330, b0114, b0118, x0115, b0115);
-  Sm s0116(x0216, b1431, b0115, b0118, x0116, b0116);
-  Sm s0117(x0217, b1531, b0116, b0118, x0117, b0117);
-  Sn s0118(x0218,        b0117,               b0118);
-
-  S0b s0000(P0,                              b0000);
-  S1b s0001(P1,         b0000,               b0001);
-  Sb s0002(x0102, b0118, b0001,               b0002);
-  Sb s0003(x0103, b0219, b0002,               b0003);
-  Sb s0004(x0104, b0320, b0003,               b0004);
-  Sb s0005(x0105, b0421, b0004,               b0005);
-  Sb s0006(x0106, b0522, b0005,               b0006);
-  Sb s0007(x0107, b0623, b0006,               b0007);
-  Sb s0008(x0108, b0724, b0007,               b0008);
-  Sb s0009(x0109, b0825, b0008,               b0009);
-  Sb s0010(x0110, b0926, b0009,               b0010);
-  Sb s0011(x0111, b1027, b0010,               b0011);
-  Sb s0012(x0112, b1128, b0011,               b0012);
-  Sb s0013(x0113, b1229, b0012,               b0013);
-  Sb s0014(x0114, b1330, b0013,               b0014);
-  Sb s0015(x0115, b1431, b0014,               b0015);
-  Sb s0016(x0116, b1531, b0015,               b0016);
-  Sn s0017(x0117,        b0016,               b0017);
-
-  buf b0 (U0,  b0017); // set output bits
-  buf b1 (U1,  b0118);
-  buf b2 (U2,  b0219);
-  buf b3 (U3,  b0320);
-  buf b4 (U4,  b0421);
-  buf b5 (U5,  b0522);
-  buf b6 (U6,  b0623);
-  buf b7 (U7,  b0724);
-  buf b8 (U8,  b0825);
-  buf b9 (U9,  b0926);
-  buf b10(U10, b1027);
-  buf b11(U11, b1128);
-  buf b12(U12, b1229);
-  buf b13(U13, b1330);
-  buf b14(U14, b1431);
-  buf b15(U15, b1531);        
-endmodule  //  sqrt32
-
-
-module tsqrt32;  // test driver
-  reg 31:0 P;
-  wire 15:0 U;
-  reg 7:0 temp;
-  integer i;
-  
-  // test of sqrt32
-  sqrt32 s1(P, U);    // instantiate module
-  initial
-    begin  // test cases
-      for(i=0; i<256; i=i+1)
-        begin
-          temp = i;
-          P = {temp,temp,temp,temp};
-          #257 $display("sqrt( %b )= %b", P, U);
-        end
-    end
-endmodule  //  tsqrt32
-
-
-   'module',
-      'Sm',
-      '(',
-      'x', 'y', 'b', 'u', 'd', 'bo',
-      ')',
-      ';',
-     'input', 'x', ';',
-      'input', 'y', ';',
-      'input', 'b', ';',
-      'input', 'u', ';',
-      'output', 'd', ';',
-      'output', 'bo', ';',
-      'wire', 't011', 't111', 't010', 't001', 't100', 'td', ';',
-      'wire', 'x_', 'y_', 'b_', 'u_', 'if_td', 'if_x', ';',
-      'not', 'notx', '(', 'x_', 'x', ')', ';',
-      'not', 'noty', '(', 'y_', 'y', ')', ';',
-      'not', 'notb', '(', 'b_', 'b', ')', ';',
-      'and', 'a011', '(', 't011', 'x_', 'y', 'b', ')', ';',
-      'and', 'a111', '(', 't111', 'x', 'y', 'b', ')', ';',
-      'and', 'a010', '(', 't010', 'x_', 'y', 'b_', ')', ';',
-      'and', 'a001', '(', 't001', 'x_', 'y_', 'b', ')', ';',
-      'and', 'a100', '(', 't100', 'x', 'y_', 'b_', ')', ';',
-       'or',
-        '#', '1',
-        'or1',
-        '(',
-        'bo', 't011', 't111', 't010', 't001',
-        ')',
-        ';',
-       'or',
-        'or2',
-        '(',
-        'td', 't100', 't001', 't010', 't111',
-        ')',
-        ';',
-      'not', 'notu', '(', 'u_', 'u', ')', ';',
-      'and', 'atd', '(', 'if_td', 'td', 'u', ')', ';',
-      'and', 'ax', '(', 'if_x', 'x', 'u_', ')', ';',
-      'or', '#', '1', 'or3', '(', 'd', 'if_td', 'if_x', ')', ';',
-    'endmodule',
-   'module', 'Sb', '(', 'x', 'y', 'b', 'bo', ')', ';',
-     'input', 'x', ';',
-      'input', 'y', ';',
-      'input', 'b', ';',
-      'output', 'bo', ';',
-      'wire', 't011', 't111', 't010', 't001', ';',
-      'wire', 'x_', 'y_', 'b_', ';',
-      'not', 'n01', '(', 'x_', 'x', ')', ';',
-      'not', 'n02', '(', 'y_', 'y', ')', ';',
-      'not', 'n03', '(', 'b_', 'b', ')', ';',
-      'and', 'a011', '(', 't011', 'x_', 'y', 'b', ')', ';',
-      'and', 'a111', '(', 't111', 'x', 'y', 'b', ')', ';',
-      'and', 'a010', '(', 't010', 'x_', 'y', 'b_', ')', ';',
-      'and', 'a001', '(', 't001', 'x_', 'y_', 'b', ')', ';',
-       'or',
-        '#', '1',
-        'bor',
-        '(',
-        'bo', 't011', 't111', 't010', 't001',
-        ')',
-        ';',
-    'endmodule',
-   'module', 'S1', '(', 'x', 'b', 'u', 'd', 'bo', ')', ';',
-     'input', 'x', ';',
-      'input', 'b', ';',
-      'input', 'u', ';',
-      'output', 'd', ';',
-      'output', 'bo', ';',
-      'wire', 't100', 't001', 'td', ';',
-      'wire', 'x_', 'b_', 'u_', 'if_td', 'if_x', ';',
-      'not', 'not1', '(', 'x_', 'x', ')', ';',
-      'not', 'not2', '(', 'b_', 'b', ')', ';',
-      'and', 'a011', '(', 't001', 'x_', 'b', ')', ';',
-      'and', 'a100', '(', 't100', 'x', 'b_', ')', ';',
-      'buf', '#', '1', 'buf1', '(', 'bo', 't001', ')', ';',
-      'or', 'or1', '(', 'td', 't100', 't001', ')', ';',
-      'not', 'notu', '(', 'u_', 'u', ')', ';',
-      'and', 'atd', '(', 'if_td', 'td', 'u', ')', ';',
-      'and', 'ax', '(', 'if_x', 'x', 'u_', ')', ';',
-      'or', '#', '1', 'or3', '(', 'd', 'if_td', 'if_x', ')', ';',
-    'endmodule',
-   'module', 'S0', '(', 'x', 'u', 'd', 'bo', ')', ';',
-     'input', 'x', ';',
-      'input', 'u', ';',
-      'output', 'd', ';',
-      'output', 'bo', ';',
-      'wire', 'u_', 'if_bo', 'if_x', ';',
-      'not', '#', '1', 'n1', '(', 'bo', 'x', ')', ';',
-      'not', 'notu', '(', 'u_', 'u', ')', ';',
-      'and', 'atd', '(', 'if_bo', 'bo', 'u', ')', ';',
-      'and', 'ax', '(', 'if_x', 'x', 'u_', ')', ';',
-      'or', '#', '1', 'or3', '(', 'd', 'if_bo', 'if_x', ')', ';',
-    'endmodule',
-   'module', 'Sn', '(', 'x', 'b', 'bo', ')', ';',
-     'input', 'x', ';',
-      'input', 'b', ';',
-      'output', 'bo', ';',
-      'wire', 'x_', ';',
-      'not', 'n00', '(', 'x_', 'x', ')', ';',
-      'nand', '#', '1', 'n01', '(', 'bo', 'x_', 'b', ')', ';',
-    'endmodule',
-   'module', 'S0b', '(', 'x', 'bo', ')', ';',
-     'input', 'x', ';',
-      'output', 'bo', ';',
-      'not', '#', '1', 'n0', '(', 'bo', 'x', ')', ';',
-    'endmodule',
-   'module', 'S1b', '(', 'x', 'b', 'bo', ')', ';',
-     'input', 'x', ';',
-      'input', 'b', ';',
-      'output', 'bo', ';',
-      'wire', 'x_', ';',
-      'not', 'n00', '(', 'x_', 'x', ')', ';',
-      'and', '#', '1', 'n01', '(', 'bo', 'x_', 'b', ')', ';',
-    'endmodule',
-   'module', 'sqrt32', '(', 'P', 'U', ')', ';',
-     'input', '', '31', ':', '0', '', 'P', ';',
-      'output', '', '15', ':', '0', '', 'U', ';',
-       'wire',
-         'b0000',
-          'b0001',
-          'b0002',
-          'b0003',
-          'b0004',
-          'b0005',
-          'b0006',
-          'b0007',
-          'b0008',
-          'b0009',
-          'b0010',
-          'b0011',
-          'b0012',
-          'b0013',
-          'b0014',
-          'b0015',
-          'b0016',
-          'b0017',
-        ';',
-       'wire',
-         'x0102',
-          'x0103',
-          'x0104',
-          'x0105',
-          'x0106',
-          'x0107',
-          'x0108',
-          'x0109',
-          'x0110',
-          'x0111',
-          'x0112',
-          'x0113',
-          'x0114',
-          'x0115',
-          'x0116',
-          'x0117',
-        ';',
-       'wire',
-         'b0102',
-          'b0103',
-          'b0104',
-          'b0105',
-          'b0106',
-          'b0107',
-          'b0108',
-          'b0109',
-          'b0110',
-          'b0111',
-          'b0112',
-          'b0113',
-          'b0114',
-          'b0115',
-          'b0116',
-          'b0117',
-          'b0118',
-        ';',
-       'wire',
-         'x0204',
-          'x0205',
-          'x0206',
-          'x0207',
-          'x0208',
-          'x0209',
-          'x0210',
-          'x0211',
-          'x0212',
-          'x0213',
-          'x0214',
-          'x0215',
-          'x0216',
-          'x0217',
-          'x0218',
-        ';',
-       'wire',
-         'b0204',
-          'b0205',
-          'b0206',
-          'b0207',
-          'b0208',
-          'b0209',
-          'b0210',
-          'b0211',
-          'b0212',
-          'b0213',
-          'b0214',
-          'b0215',
-          'b0216',
-          'b0217',
-          'b0218',
-          'b0219',
-        ';',
-       'wire',
-         'x0306',
-          'x0307',
-          'x0308',
-          'x0309',
-          'x0310',
-          'x0311',
-          'x0312',
-          'x0313',
-          'x0314',
-          'x0315',
-          'x0316',
-          'x0317',
-          'x0318',
-          'x0319',
-        ';',
-       'wire',
-         'b0306',
-          'b0307',
-          'b0308',
-          'b0309',
-          'b0310',
-          'b0311',
-          'b0312',
-          'b0313',
-          'b0314',
-          'b0315',
-          'b0316',
-          'b0317',
-          'b0318',
-          'b0319',
-          'b0320',
-        ';',
-       'wire',
-         'x0408',
-          'x0409',
-          'x0410',
-          'x0411',
-          'x0412',
-          'x0413',
-          'x0414',
-          'x0415',
-          'x0416',
-          'x0417',
-          'x0418',
-          'x0419',
-          'x0420',
-        ';',
-       'wire',
-         'b0408',
-          'b0409',
-          'b0410',
-          'b0411',
-          'b0412',
-          'b0413',
-          'b0414',
-          'b0415',
-          'b0416',
-          'b0417',
-          'b0418',
-          'b0419',
-          'b0420',
-          'b0421',
-        ';',
-       'wire',
-         'x0510',
-          'x0511',
-          'x0512',
-          'x0513',
-          'x0514',
-          'x0515',
-          'x0516',
-          'x0517',
-          'x0518',
-          'x0519',
-          'x0520',
-          'x0521',
-        ';',
-       'wire',
-         'b0510',
-          'b0511',
-          'b0512',
-          'b0513',
-          'b0514',
-          'b0515',
-          'b0516',
-          'b0517',
-          'b0518',
-          'b0519',
-          'b0520',
-          'b0521',
-          'b0522',
-        ';',
-       'wire',
-         'x0612',
-          'x0613',
-          'x0614',
-          'x0615',
-          'x0616',
-          'x0617',
-          'x0618',
-          'x0619',
-          'x0620',
-          'x0621',
-          'x0622',
-        ';',
-       'wire',
-         'b0612',
-          'b0613',
-          'b0614',
-          'b0615',
-          'b0616',
-          'b0617',
-          'b0618',
-          'b0619',
-          'b0620',
-          'b0621',
-          'b0622',
-          'b0623',
-        ';',
-       'wire',
-         'x0714',
-          'x0715',
-          'x0716',
-          'x0717',
-          'x0718',
-          'x0719',
-          'x0720',
-          'x0721',
-          'x0722',
-          'x0723',
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-                'end',
-          'end',
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_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/sqrt8m.v.parsed.txt Deleted

@@ -1,410 +0,0 @@
-// sqrt8m.v     unsigned integer sqrt 8-bits computing unsigned integer 4-bits
-//             sqrt(00000100) = 0010   sqrt(4)=2
-//             sqrt(01000000) = 1000   sqrt(64)=8
-
-`timescale 1ns/1ns
-
-module Sm(x, y, b, u, d, bo);  // subtractor multiplexor 
-  input  x;
-  input  y;
-  input  b;
-  input  u;
-  output d;
-  output bo;
-
-  wire t011, t111, t010, t001, t100, td;
-  wire x_, y_, b_, u_, if_td, if_x;
-
-  // circuits of Sm
-  not notx(x_, x);
-  not noty(y_, y);
-  not notb(b_, b);
-  and a011(t011, x_, y,  b );
-  and a111(t111, x,  y,  b );
-  and a010(t010, x_, y,  b_);
-  and a001(t001, x_, y_, b );
-  and a100(t100, x,  y_, b_);
-  or  #1 or1(bo, t011, t111, t010, t001);
-  or  or2(td, t100, t001, t010, t111);
-  not notu(u_, u);  // four gate mux
-  and atd(if_td, td, u); 
-  and ax (if_x,   x, u_);
-  or  #1 or3(d, if_td, if_x);
-endmodule  // Sm
-
-
-module Sb(x, y, b, bo);  // subtractor multiplexor stage b 
-  input  x;
-  input  y;
-  input  b;
-  output bo;
-
-  wire t011, t111, t010, t001;
-  wire x_, y_, b_;
-
-  // circuits of Sb
-  not n01(x_, x);
-  not n02(y_, y);
-  not n03(b_, b);
-  and a011(t011, x_, y,  b);
-  and a111(t111, x,  y,  b);
-  and a010(t010, x_, y,  b_);
-  and a001(t001, x_, y_,  b);
-  or #1 bor(bo, t011, t111, t010, t001);
-endmodule  // Sb
-
-module S1(x, b, u, d, bo);  // subtractor multiplexor stage 1
-  input  x;
-  input  b;
-  input  u;
-  output d;
-  output bo;
-
-  wire t100, t001, td;
-  wire x_, b_, u_, if_td, if_x;
-
-  // circuits of S1
-  not not1(x_, x);
-  not not2(b_, b);
-  and a011(t001, x_,  b);
-  and a100(t100, x,   b_);
-  buf #1 buf1(bo, t001);
-  or or1(td, t100, t001);
-  not notu(u_, u);  // four gate mux
-  and atd(if_td, td, u); 
-  and ax (if_x,   x, u_);
-  or  #1 or3(d, if_td, if_x);
-endmodule  //  S1
-
-module S0(x, u, d, bo);    // subtractor multiplexor stage 0
-  input  x;
-  input  u;
-  output d;
-  output bo;
-
-  wire u_, if_bo, if_x;
-
-  // circuits of S0
-  not #1 n1(bo, x);
-  not notu(u_, u);  // four gate mux
-  and atd(if_bo, bo, u); 
-  and ax (if_x,   x, u_);
-  or  #1 or3(d, if_bo, if_x);
-endmodule  //  S0
-
-module Sn(x, b, bo); // subtractor multiplexor stage n 
-  input  x;
-  input  b;
-  output bo;
-
-  wire x_;
-
-  // circuits of Sn, complemented
-  not  n00(x_, x);
-  nand #1 n01(bo, x_, b);
-endmodule  //  Sn
-
-module S0b(x, bo);   // subtractor multiplexor stage 0b
-  input  x;
-  output bo;
-
-  // circuits of S0b
-  not #1 n0(bo, x);
-endmodule  //  S0b
-
-module S1b(x, b, bo);     // subtractor multiplexor stage 1b
-  input  x;
-  input  b;
-  output bo;
-
-  wire x_;
-
-  // circuits of S1b
-  not n00(x_, x);
-  and #1 n01(bo, x_, b);
-endmodule  //  S1b
-
-
-module psqrt(P, U);
-  input 7:0 P;
-  output 3:0 U;
-
-  wire b00, b01, b02, b03, b04, b05;  
-  wire x12, x13, x14, x15;  
-  wire b12, b13, b14, b15, b16;  
-  wire x24, x25, x26;  
-  wire b24, b25, b26, b27;  
-  wire x36, x37, bxx;  
-  wire b36, b37;  
-
-  // circuits of psqrt
-  //       x     y    b    u    d    bo
-  S0  s36(P6,           b37, x36, b36);
-  S1  s37(P7,      b36, b37, x37, bxx);
-  not t37(b37,  bxx);
-
-  S0  s24(P4,           b27, x24, b24);
-  S1  s25(P5,      b24, b27, x25, b25);
-  Sm  s26(x36 , b37, b25, b27, x26, b26);
-  Sn  s27(x37 ,      b26,           b27);
-
-  S0  s12(P2,           b16, x12, b12);
-  S1  s13(P3,      b12, b16, x13, b13);
-  Sm  s14(x24 , b27, b13, b16, x14, b14);
-  Sm  s15(x25 , b37, b14, b16, x15, b15);
-  Sn  s16(x26 ,      b15,           b16);
-
-  S0b s00(P0,                     b00);
-  S1b s01(P1,      b00,           b01);
-  Sb  s02(x12 , b16, b01,           b02);
-  Sb  s03(x13 , b27, b02,           b03);
-  Sb  s04(x14 , b37, b03,           b04);
-  Sn  s05(x15 ,      b04,           b05);
-  buf buf1(U0, b05);
-  buf buf2(U1, b16);
-  buf buf3(U2, b27);
-  buf buf4(U3, b37);
-
-endmodule  // psqrt
-
-module sqrt8m;  // test driver
-  reg 7:0 P;
-  wire 3:0 U;
-  integer i;
-  
-  // test of sqrt8m
-  psqrt s1(P, U);    // instantiate module
-  initial
-    begin  // test cases
-      for(i=0; i<256; i=i+1)
-        begin
-          P = i;
-          #40 $display("sqrt( %b )= %b", P, U);
-        end
-    end
-endmodule  //  sqrt8m
-
-
-
-   'module',
-      'Sm',
-      '(',
-      'x', 'y', 'b', 'u', 'd', 'bo',
-      ')',
-      ';',
-     'input', 'x', ';',
-      'input', 'y', ';',
-      'input', 'b', ';',
-      'input', 'u', ';',
-      'output', 'd', ';',
-      'output', 'bo', ';',
-      'wire', 't011', 't111', 't010', 't001', 't100', 'td', ';',
-      'wire', 'x_', 'y_', 'b_', 'u_', 'if_td', 'if_x', ';',
-      'not', 'notx', '(', 'x_', 'x', ')', ';',
-      'not', 'noty', '(', 'y_', 'y', ')', ';',
-      'not', 'notb', '(', 'b_', 'b', ')', ';',
-      'and', 'a011', '(', 't011', 'x_', 'y', 'b', ')', ';',
-      'and', 'a111', '(', 't111', 'x', 'y', 'b', ')', ';',
-      'and', 'a010', '(', 't010', 'x_', 'y', 'b_', ')', ';',
-      'and', 'a001', '(', 't001', 'x_', 'y_', 'b', ')', ';',
-      'and', 'a100', '(', 't100', 'x', 'y_', 'b_', ')', ';',
-       'or',
-        '#', '1',
-        'or1',
-        '(',
-        'bo', 't011', 't111', 't010', 't001',
-        ')',
-        ';',
-       'or',
-        'or2',
-        '(',
-        'td', 't100', 't001', 't010', 't111',
-        ')',
-        ';',
-      'not', 'notu', '(', 'u_', 'u', ')', ';',
-      'and', 'atd', '(', 'if_td', 'td', 'u', ')', ';',
-      'and', 'ax', '(', 'if_x', 'x', 'u_', ')', ';',
-      'or', '#', '1', 'or3', '(', 'd', 'if_td', 'if_x', ')', ';',
-    'endmodule',
-   'module', 'Sb', '(', 'x', 'y', 'b', 'bo', ')', ';',
-     'input', 'x', ';',
-      'input', 'y', ';',
-      'input', 'b', ';',
-      'output', 'bo', ';',
-      'wire', 't011', 't111', 't010', 't001', ';',
-      'wire', 'x_', 'y_', 'b_', ';',
-      'not', 'n01', '(', 'x_', 'x', ')', ';',
-      'not', 'n02', '(', 'y_', 'y', ')', ';',
-      'not', 'n03', '(', 'b_', 'b', ')', ';',
-      'and', 'a011', '(', 't011', 'x_', 'y', 'b', ')', ';',
-      'and', 'a111', '(', 't111', 'x', 'y', 'b', ')', ';',
-      'and', 'a010', '(', 't010', 'x_', 'y', 'b_', ')', ';',
-      'and', 'a001', '(', 't001', 'x_', 'y_', 'b', ')', ';',
-       'or',
-        '#', '1',
-        'bor',
-        '(',
-        'bo', 't011', 't111', 't010', 't001',
-        ')',
-        ';',
-    'endmodule',
-   'module', 'S1', '(', 'x', 'b', 'u', 'd', 'bo', ')', ';',
-     'input', 'x', ';',
-      'input', 'b', ';',
-      'input', 'u', ';',
-      'output', 'd', ';',
-      'output', 'bo', ';',
-      'wire', 't100', 't001', 'td', ';',
-      'wire', 'x_', 'b_', 'u_', 'if_td', 'if_x', ';',
-      'not', 'not1', '(', 'x_', 'x', ')', ';',
-      'not', 'not2', '(', 'b_', 'b', ')', ';',
-      'and', 'a011', '(', 't001', 'x_', 'b', ')', ';',
-      'and', 'a100', '(', 't100', 'x', 'b_', ')', ';',
-      'buf', '#', '1', 'buf1', '(', 'bo', 't001', ')', ';',
-      'or', 'or1', '(', 'td', 't100', 't001', ')', ';',
-      'not', 'notu', '(', 'u_', 'u', ')', ';',
-      'and', 'atd', '(', 'if_td', 'td', 'u', ')', ';',
-      'and', 'ax', '(', 'if_x', 'x', 'u_', ')', ';',
-      'or', '#', '1', 'or3', '(', 'd', 'if_td', 'if_x', ')', ';',
-    'endmodule',
-   'module', 'S0', '(', 'x', 'u', 'd', 'bo', ')', ';',
-     'input', 'x', ';',
-      'input', 'u', ';',
-      'output', 'd', ';',
-      'output', 'bo', ';',
-      'wire', 'u_', 'if_bo', 'if_x', ';',
-      'not', '#', '1', 'n1', '(', 'bo', 'x', ')', ';',
-      'not', 'notu', '(', 'u_', 'u', ')', ';',
-      'and', 'atd', '(', 'if_bo', 'bo', 'u', ')', ';',
-      'and', 'ax', '(', 'if_x', 'x', 'u_', ')', ';',
-      'or', '#', '1', 'or3', '(', 'd', 'if_bo', 'if_x', ')', ';',
-    'endmodule',
-   'module', 'Sn', '(', 'x', 'b', 'bo', ')', ';',
-     'input', 'x', ';',
-      'input', 'b', ';',
-      'output', 'bo', ';',
-      'wire', 'x_', ';',
-      'not', 'n00', '(', 'x_', 'x', ')', ';',
-      'nand', '#', '1', 'n01', '(', 'bo', 'x_', 'b', ')', ';',
-    'endmodule',
-   'module', 'S0b', '(', 'x', 'bo', ')', ';',
-     'input', 'x', ';',
-      'output', 'bo', ';',
-      'not', '#', '1', 'n0', '(', 'bo', 'x', ')', ';',
-    'endmodule',
-   'module', 'S1b', '(', 'x', 'b', 'bo', ')', ';',
-     'input', 'x', ';',
-      'input', 'b', ';',
-      'output', 'bo', ';',
-      'wire', 'x_', ';',
-      'not', 'n00', '(', 'x_', 'x', ')', ';',
-      'and', '#', '1', 'n01', '(', 'bo', 'x_', 'b', ')', ';',
-    'endmodule',
-   'module', 'psqrt', '(', 'P', 'U', ')', ';',
-     'input', '', '7', ':', '0', '', 'P', ';',
-      'output', '', '3', ':', '0', '', 'U', ';',
-      'wire', 'b00', 'b01', 'b02', 'b03', 'b04', 'b05', ';',
-      'wire', 'x12', 'x13', 'x14', 'x15', ';',
-      'wire', 'b12', 'b13', 'b14', 'b15', 'b16', ';',
-      'wire', 'x24', 'x25', 'x26', ';',
-      'wire', 'b24', 'b25', 'b26', 'b27', ';',
-      'wire', 'x36', 'x37', 'bxx', ';',
-      'wire', 'b36', 'b37', ';',
-       'S0',
-         's36',
-          '(', 'P', '', '6', '', 'b37', 'x36', 'b36', ')',
-        ';',
-       'S1',
-         's37',
-           '(',
-            'P', '', '7', '',
-            'b36',
-            'b37',
-            'x37',
-            'bxx',
-            ')',
-        ';',
-      'not', 't37', '(', 'b37', 'bxx', ')', ';',
-       'S0',
-         's24',
-          '(', 'P', '', '4', '', 'b27', 'x24', 'b24', ')',
-        ';',
-       'S1',
-         's25',
-           '(',
-            'P', '', '5', '',
-            'b24',
-            'b27',
-            'x25',
-            'b25',
-            ')',
-        ';',
-       'Sm',
-         's26',
-          '(', 'x36', 'b37', 'b25', 'b27', 'x26', 'b26', ')',
-        ';',
-      'Sn', 's27', '(', 'x37', 'b26', 'b27', ')', ';',
-       'S0',
-         's12',
-          '(', 'P', '', '2', '', 'b16', 'x12', 'b12', ')',
-        ';',
-       'S1',
-         's13',
-           '(',
-            'P', '', '3', '',
-            'b12',
-            'b16',
-            'x13',
-            'b13',
-            ')',
-        ';',
-       'Sm',
-         's14',
-          '(', 'x24', 'b27', 'b13', 'b16', 'x14', 'b14', ')',
-        ';',
-       'Sm',
-         's15',
-          '(', 'x25', 'b37', 'b14', 'b16', 'x15', 'b15', ')',
-        ';',
-      'Sn', 's16', '(', 'x26', 'b15', 'b16', ')', ';',
-      'S0b', 's00', '(', 'P', '', '0', '', 'b00', ')', ';',
-       'S1b',
-        's01', '(', 'P', '', '1', '', 'b00', 'b01', ')',
-        ';',
-      'Sb', 's02', '(', 'x12', 'b16', 'b01', 'b02', ')', ';',
-      'Sb', 's03', '(', 'x13', 'b27', 'b02', 'b03', ')', ';',
-      'Sb', 's04', '(', 'x14', 'b37', 'b03', 'b04', ')', ';',
-      'Sn', 's05', '(', 'x15', 'b04', 'b05', ')', ';',
-      'buf', 'buf1', '(', 'U', '', '0', '', 'b05', ')', ';',
-      'buf', 'buf2', '(', 'U', '', '1', '', 'b16', ')', ';',
-      'buf', 'buf3', '(', 'U', '', '2', '', 'b27', ')', ';',
-      'buf', 'buf4', '(', 'U', '', '3', '', 'b37', ')', ';',
-    'endmodule',
-   'module', 'sqrt8m', ';',
-     'reg', '', '7', ':', '0', '', 'P', ';',
-      'wire', '', '3', ':', '0', '', 'U', ';',
-      'integer', 'i', ';',
-      'psqrt', 's1', '(', 'P', 'U', ')', ';',
-       'initial',
-         'begin',
-            'for',
-              '(',
-              'i', '=', '0',
-              ';',
-              'i', '<', '256',
-              ';',
-              'i', '=', 'i', '+', '1',
-              ')',
-               'begin',
-                 'P', '=', 'i', ';',
-                   '#', '40',
-                     '$display',
-                      '(',
-                      '"sqrt( %b )= %b"',
-                      'P',
-                      'U',
-                      ')',
-                      ';',
-                'end',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/sr_nv_ctf.v.parsed.txt Deleted

@@ -1,269 +0,0 @@
-
-// Module counterflow shift register cell
-module sr_nv_ctf (din, cin, dout, cout);
-
-input
-	din, cin;
-
-output
-	dout, cout;
-reg 
-	dout, cout;
-
-parameter
-	t_hold	= -3,
-	t_setup	= 8,
-	delay = 9,        // delay between cin and dout
-	delay_clk = 14,   // delay between cin and cout
-
-	warning_file=3;   // multichannel description of a warning file
-
-reg
-	dinternal, cinternal,
-	d_state,          	   // internal state at the input d
-	d_set;		   	   // signal determining the moment when
-				   // the state of the d input changes to "1"
-
-integer
-	data_delay,  // delay between d and dinternal
-	clk_delay,   // delay between clk and cinternal
-	out_delay,   // delay between cinternal and out
-	out_value,   // output value in a given clock cycle
-	last_clk_time;	// time when the last clock pulse appeared
-
-initial 
-	begin
-// define delays between inputs & outputs and the corresponding
-//  internal auxiliary registers
-	  	if(t_hold<0)
-		  begin
-	    	  	data_delay = -t_hold;
-	    		clk_delay  = 0;
-			out_delay  = delay;
-		  end
-	  	else
-		  begin
-	   	  	data_delay = 0;
-	    		clk_delay  = t_hold;
-		  	out_delay  = delay-t_hold;
-		  end
-
-// clear internal registers and the output signal
-		dinternal = 0;
-		cinternal = 0;
-		last_clk_time = 0;
-		d_state = 0;
-		d_set = 0;
-		dout = 0;
-		cout = 0;
-	end
-
-
-
-always @(posedge din) 	// Execute at positive edge of din
-	  dinternal <= #(data_delay) din;
-
-always @(posedge cin)  // Execute at positive edge of cin
-	  cinternal <= #(clk_delay) cin;
-
-
-always @(posedge dinternal)
-	begin
-// setting the state of the d input
-                d_state <= d_state | 1'bx;
-		if (dinternal === 1)
-		  d_set <= #(t_hold+t_setup) 1;
-
-		dinternal <= 0;
-	end
-
-always @(posedge d_set)
-	begin
-		if ($stime - last_clk_time >= t_hold+t_setup)
-			d_state = 1;
-		else
-		  begin
-			d_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input D pulse at %0d,",
-			 $stime-data_delay-t_hold-t_setup);
-			$fwrite(warning_file,
-			"\tClock pulse at %0d.\n", last_clk_time-clk_delay);
-		  end
-
-		d_set <= 0;
-	end
-
-
-always @(posedge cinternal)	
-	begin
-// computing the output
-		if (cinternal === 1'bx)
-		  out_value = 1'bx;
-		else
-		  out_value = d_state;
-
-// transfering the result to the output
-		dout <= #(out_delay) out_value;
-		dout <= #(out_delay+2) 0;
-
-		cout <= #(delay_clk-clk_delay) cinternal;
-		cout <= #(delay_clk-clk_delay+2) 0;
-
-// clearing the internal state of the DRO
-		d_state  <= 0;
-
-		cinternal <= 0;
-		last_clk_time = $stime;
-	end
-
-endmodule
-
-
-   'module',
-      'sr_nv_ctf',
-      '(',
-      'din', 'cin', 'dout', 'cout',
-      ')',
-      ';',
-     'input', 'din', 'cin', ';',
-      'output', 'dout', 'cout', ';',
-      'reg', 'dout', 'cout', ';',
-       'parameter',
-        't_hold', '=', '-', '3',
-        't_setup', '=', '8',
-        'delay', '=', '9',
-        'delay_clk', '=', '14',
-        'warning_file', '=', '3',
-        ';',
-      'reg', 'dinternal', 'cinternal', 'd_state', 'd_set', ';',
-       'integer',
-        'data_delay',
-        'clk_delay',
-        'out_delay',
-        'out_value',
-        'last_clk_time',
-        ';',
-       'initial',
-         'begin',
-            'if',
-              '(', 't_hold', '<', '0', ')',
-               'begin',
-                 'data_delay', '=', '-', 't_hold', ';',
-                  'clk_delay', '=', '0', ';',
-                  'out_delay', '=', 'delay', ';',
-                'end',
-              'else',
-               'begin',
-                 'data_delay', '=', '0', ';',
-                  'clk_delay', '=', 't_hold', ';',
-                  'out_delay', '=', 'delay', '-', 't_hold', ';',
-                'end',
-            'dinternal', '=', '0', ';',
-            'cinternal', '=', '0', ';',
-            'last_clk_time', '=', '0', ';',
-            'd_state', '=', '0', ';',
-            'd_set', '=', '0', ';',
-            'dout', '=', '0', ';',
-            'cout', '=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'din', ')',
-         'dinternal', '<=', '#', '(', 'data_delay', ')', 'din',
-          ';',
-       'always',
-        '@', '(', 'posedge', 'cin', ')',
-         'cinternal', '<=', '#', '(', 'clk_delay', ')', 'cin',
-          ';',
-       'always',
-        '@', '(', 'posedge', 'dinternal', ')',
-         'begin',
-           'd_state', '<=', 'd_state', '|', "1 'b x", ';',
-             'if',
-              '(', 'dinternal', '===', '1', ')',
-                'd_set',
-                  '<=',
-                  '#', '(', 't_hold', '+', 't_setup', ')',
-                  '1',
-                ';',
-            'dinternal', '<=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'd_set', ')',
-         'begin',
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-               '(',
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-                'last_clk_time',
-                '>=',
-                't_hold',
-                '+',
-                't_setup',
-                ')',
-              'd_state', '=', '1', ';',
-              'else',
-               'begin',
-                 'd_state', '=', "1 'b x", ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Violation of hold/setup time in module %m.\\n"',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Input D pulse at %0d,"',
-                    '$stime',
-                    '-',
-                    'data_delay',
-                    '-',
-                    't_hold',
-                    '-',
-                    't_setup',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"\\tClock pulse at %0d.\\n"',
-                    'last_clk_time',
-                    '-',
-                    'clk_delay',
-                    ')',
-                    ';',
-                'end',
-            'd_set', '<=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'cinternal', ')',
-         'begin',
-            'if',
-              '(', 'cinternal', '===', "1 'b x", ')',
-              'out_value', '=', "1 'b x", ';',
-              'else',
-              'out_value', '=', 'd_state', ';',
-             'dout', '<=', '#', '(', 'out_delay', ')', 'out_value',
-              ';',
-             'dout', '<=', '#', '(', 'out_delay', '+', '2', ')', '0',
-              ';',
-              'cout',
-                '<=',
-                '#', '(', 'delay_clk', '-', 'clk_delay', ')',
-                'cinternal',
-              ';',
-              'cout',
-                '<=',
-                '#', '(', 'delay_clk', '-', 'clk_delay', '+', '2', ')',
-                '0',
-              ';',
-            'd_state', '<=', '0', ';',
-            'cinternal', '<=', '0', ';',
-            'last_clk_time', '=', '$stime', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/srcnt.v.parsed.txt Deleted

@@ -1,270 +0,0 @@
-// Verilog HDL for "RSFQ.lib", "srcnt" "_functional"
-
-// Module counterflow shift register cell
-module srcnt (din, clkin, dout, clkout);
-
-input
-	din, clkin;
-
-output
-	dout, clkout;
-reg 
-	dout, clkout;
-
-parameter
-	t_hold	= -3,
-	t_setup	= 8,
-	delay = 9,        // delay between clkin and dout
-	delay_clk = 12,   // delay between clkin and clkout
-
-	warning_file=3;   // multichannel description of a warning file
-
-reg
-	dinternal, clkinternal,
-	d_state,          	   // internal state at the input d
-	d_set;		   	   // signal determining the moment when
-				   // the state of the d input changes to "1"
-
-integer
-	data_delay,  // delay between d and dinternal
-	clk_delay,   // delay between clk and clkinternal
-	out_delay,   // delay between clkinternal and out
-	out_value,   // output value in a given clock cycle
-	last_clk_time;	// time when the last clock pulse appeared
-
-initial 
-	begin
-// define delays between inputs & outputs and the corresponding
-//  internal auxiliary registers
-	  	if(t_hold<0)
-		  begin
-	    	  	data_delay = -t_hold;
-	    		clk_delay  = 0;
-			out_delay  = delay;
-		  end
-	  	else
-		  begin
-	   	  	data_delay = 0;
-	    		clk_delay  = t_hold;
-		  	out_delay  = delay-t_hold;
-		  end
-
-// clear internal registers and the output signal
-		dinternal = 0;
-		clkinternal = 0;
-		last_clk_time = 0;
-		d_state = 0;
-		d_set = 0;
-		dout = 0;
-		clkout = 0;
-	end
-
-
-
-always @(posedge din) 	// Execute at positive edge of din
-	  dinternal <= #(data_delay) din;
-
-always @(posedge clkin)  // Execute at positive edge of clkin
-	  clkinternal <= #(clk_delay) clkin;
-
-
-always @(posedge dinternal)
-	begin
-// setting the state of the d input
-                d_state <= d_state | 1'bx;
-		if (dinternal === 1)
-		  d_set <= #(t_hold+t_setup) 1;
-
-		dinternal <= 0;
-	end
-
-always @(posedge d_set)
-	begin
-		if ($stime - last_clk_time >= t_hold+t_setup)
-			d_state = 1;
-		else
-		  begin
-			d_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input D pulse at %0d,",
-			 $stime-data_delay-t_hold-t_setup);
-			$fwrite(warning_file,
-			"\tClock pulse at %0d.\n", last_clk_time-clk_delay);
-		  end
-
-		d_set <= 0;
-	end
-
-
-always @(posedge clkinternal)	
-	begin
-// computing the output
-		if (clkinternal === 1'bx)
-		  out_value = 1'bx;
-		else
-		  out_value = d_state;
-
-// transfering the result to the output
-		dout <= #(out_delay) out_value;
-		dout <= #(out_delay+2) 0;
-
-		clkout <= #(delay_clk-clk_delay) clkinternal;
-		clkout <= #(delay_clk-clk_delay+2) 0;
-
-// clearing the internal state of the DRO
-		d_state  <= 0;
-
-		clkinternal <= 0;
-		last_clk_time = $stime;
-	end
-
-endmodule
-
-
-   'module',
-      'srcnt',
-      '(',
-      'din', 'clkin', 'dout', 'clkout',
-      ')',
-      ';',
-     'input', 'din', 'clkin', ';',
-      'output', 'dout', 'clkout', ';',
-      'reg', 'dout', 'clkout', ';',
-       'parameter',
-        't_hold', '=', '-', '3',
-        't_setup', '=', '8',
-        'delay', '=', '9',
-        'delay_clk', '=', '12',
-        'warning_file', '=', '3',
-        ';',
-      'reg', 'dinternal', 'clkinternal', 'd_state', 'd_set', ';',
-       'integer',
-        'data_delay',
-        'clk_delay',
-        'out_delay',
-        'out_value',
-        'last_clk_time',
-        ';',
-       'initial',
-         'begin',
-            'if',
-              '(', 't_hold', '<', '0', ')',
-               'begin',
-                 'data_delay', '=', '-', 't_hold', ';',
-                  'clk_delay', '=', '0', ';',
-                  'out_delay', '=', 'delay', ';',
-                'end',
-              'else',
-               'begin',
-                 'data_delay', '=', '0', ';',
-                  'clk_delay', '=', 't_hold', ';',
-                  'out_delay', '=', 'delay', '-', 't_hold', ';',
-                'end',
-            'dinternal', '=', '0', ';',
-            'clkinternal', '=', '0', ';',
-            'last_clk_time', '=', '0', ';',
-            'd_state', '=', '0', ';',
-            'd_set', '=', '0', ';',
-            'dout', '=', '0', ';',
-            'clkout', '=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'din', ')',
-         'dinternal', '<=', '#', '(', 'data_delay', ')', 'din',
-          ';',
-       'always',
-        '@', '(', 'posedge', 'clkin', ')',
-         'clkinternal', '<=', '#', '(', 'clk_delay', ')', 'clkin',
-          ';',
-       'always',
-        '@', '(', 'posedge', 'dinternal', ')',
-         'begin',
-           'd_state', '<=', 'd_state', '|', "1 'b x", ';',
-             'if',
-              '(', 'dinternal', '===', '1', ')',
-                'd_set',
-                  '<=',
-                  '#', '(', 't_hold', '+', 't_setup', ')',
-                  '1',
-                ';',
-            'dinternal', '<=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'd_set', ')',
-         'begin',
-            'if',
-               '(',
-                '$stime',
-                '-',
-                'last_clk_time',
-                '>=',
-                't_hold',
-                '+',
-                't_setup',
-                ')',
-              'd_state', '=', '1', ';',
-              'else',
-               'begin',
-                 'd_state', '=', "1 'b x", ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Violation of hold/setup time in module %m.\\n"',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Input D pulse at %0d,"',
-                    '$stime',
-                    '-',
-                    'data_delay',
-                    '-',
-                    't_hold',
-                    '-',
-                    't_setup',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"\\tClock pulse at %0d.\\n"',
-                    'last_clk_time',
-                    '-',
-                    'clk_delay',
-                    ')',
-                    ';',
-                'end',
-            'd_set', '<=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'clkinternal', ')',
-         'begin',
-            'if',
-              '(', 'clkinternal', '===', "1 'b x", ')',
-              'out_value', '=', "1 'b x", ';',
-              'else',
-              'out_value', '=', 'd_state', ';',
-             'dout', '<=', '#', '(', 'out_delay', ')', 'out_value',
-              ';',
-             'dout', '<=', '#', '(', 'out_delay', '+', '2', ')', '0',
-              ';',
-              'clkout',
-                '<=',
-                '#', '(', 'delay_clk', '-', 'clk_delay', ')',
-                'clkinternal',
-              ';',
-              'clkout',
-                '<=',
-                '#', '(', 'delay_clk', '-', 'clk_delay', '+', '2', ')',
-                '0',
-              ';',
-            'd_state', '<=', '0', ';',
-            'clkinternal', '<=', '0', ';',
-            'last_clk_time', '=', '$stime', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/string.v.parsed.txt Deleted

@@ -1,140 +0,0 @@
-//
-// Demonstrate how to display strings for a particular signal.
-// This allows you to see a text string for a bus, which at times, might
-// help out in debugging.  This is not intended for synthesis, of course.
-// Keep these funny "string" signals seperate so we can disable them
-// at synthesis time and so they never impact the circuit.
-//
-//
-module test;
-
-// Declare a register with enough bits for the ASCII string.
-// synopsys translate_off
-reg 9*8-1:0 string_signal; // **** FOR TESTING
-// synopsys translate_on
-
-// Here's the *real* circuit signal
-reg 3:0 shift_register;
-
-reg clk, reset;
-
-// Here's the real circuit
-always @(posedge clk)
-   if (reset) shift_register <= 4'b0001;
-   else       shift_register <= {shift_register2:0, shift_register3};
-
-// Now we assign to our string signal based on the real signal.
-// Disable this code when synthesizing.
-//   
-// synopsys translate_off
-always @(shift_register)
-   case (shift_register)
-      4'b0001: string_signal <= "BIT  ZERO";
-      4'b0010: string_signal <= "BIT   ONE";
-      4'b0100: string_signal <= "BIT   TWO";
-      4'b1000: string_signal <= "BIT THREE";
-      default: string_signal <= "?????????";                  
-   endcase
-// synopsys translate_on
-
-initial begin
-   clk =  0;
-   forever begin
-      #10 clk = ~clk;
-   end
-end
-
-initial begin
-   reset = 0;
-   #2 reset = 1;  
-   #13 reset = 0;
-   #200;
-   $finish;
-end
-
-// Generate VCD file for viewing.
-//
-// Once we are in the Waveform Viewer, just set the format of 'string_signal'
-// to ASCII!
-//
-initial begin
-   $dumpfile ("test_string_signal.vcd");
-   $dumpvars (0,test);   
-end
-
-   
-endmodule
-
-
-  'module', 'test', ';',
-      'reg',
-        '',
-        '9',
-        '*',
-        '8',
-        '-',
-        '1',
-        ':',
-        '0',
-        '',
-        'string_signal',
-        ';',
-      'reg', '', '3', ':', '0', '', 'shift_register', ';',
-      'reg', 'clk', 'reset', ';',
-       'always',
-        '@', '(', 'posedge', 'clk', ')',
-         'if',
-          '(', 'reset', ')',
-          'shift_register', '<=', "4 'b 0001", ';',
-          'else',
-            'shift_register',
-              '<=',
-               '{',
-                'shift_register', '', '2', '0', '',
-                'shift_register', '', '3', '',
-                '}',
-            ';',
-       'always',
-        '@', '(', 'shift_register', ')',
-         'case',
-          '(',
-          'shift_register',
-          ')',
-          "4 'b 0001",
-          ':',
-          'string_signal', '<=', '"BIT  ZERO"', ';',
-          "4 'b 0010",
-          ':',
-          'string_signal', '<=', '"BIT   ONE"', ';',
-          "4 'b 0100",
-          ':',
-          'string_signal', '<=', '"BIT   TWO"', ';',
-          "4 'b 1000",
-          ':',
-          'string_signal', '<=', '"BIT THREE"', ';',
-          'default',
-          ':',
-          'string_signal', '<=', '"?????????"', ';',
-          'endcase',
-       'initial',
-         'begin',
-           'clk', '=', '0', ';',
-             'forever',
-               'begin',
-                '#', '10', 'clk', '=', '~', 'clk', ';',
-                'end',
-          'end',
-       'initial',
-         'begin',
-           'reset', '=', '0', ';',
-            '#', '2', 'reset', '=', '1', ';',
-            '#', '13', 'reset', '=', '0', ';',
-            '#', '200', ';',
-            '$finish', ';',
-          'end',
-       'initial',
-         'begin',
-           '$dumpfile', '(', '"test_string_signal.vcd"', ')', ';',
-            '$dumpvars', '(', '0', 'test', ')', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/t1ff.v.parsed.txt Deleted

@@ -1,380 +0,0 @@
-// Verilog HDL for "gates.lib", "t1ff" "_functional"
-// Module T1 flip-flop
-module t1ff (t, wr0, out, rd1);
-
-input
-	t, wr0;
-
-output
-	out, rd1;
-reg 
-	out, rd1;
-
-parameter
-	t_separation = 10,
-	delay=8,
-	t_hold = 7,
-	t_setup = 6,
-	rd1_delay=10,
-
-	warning_file=3;  // multichannel description of a warning file
-
-reg
-	t_internal, wr0_internal, // signals at inputs after i/o stage
-	t_state,  // internal state of T flip-flop
-	sep_clr,  // signal marking the end of the separation zone
-	hs_clr;	  // signal marking the end of the hold/setup zone
-
-
-integer
-	data_delay, 	// delay between t and t_internal
-	wr0_delay, 	// delay between rd and rd_internal
-	t_out_delay, 	// delay between t_internal and out
-	wr0_out_delay,  // delay between rd_internal and out
-	last_t_time,    // time when the last t pulse appeared
-	last_wr0_time,  // time when the last wr0 pulse appeared
-	in_hs,    // number of t pulses in hold/setup zone
-	in_sep,	 // number of pulses within an interval t_sep before 
-		 //  the last data pulse;
-	out_value; // value at the output;
-
-initial 
-	begin
-// define delays between inputs & outputs and the corresponding
-//  internal auxiliary registers
-	  	if(t_hold<0)
-		  begin
-	    	  	data_delay = -t_hold;
-	    		wr0_delay  = 0;
-		  end
-	  	else
-		  begin
-	   	  	data_delay = 0;
-	    		wr0_delay  = t_hold;
-		  end
-		t_out_delay  = delay-data_delay;
-		wr0_out_delay = rd1_delay-wr0_delay;
-
-// clear internal registers and the output signal
-		t_internal = 0;
-		wr0_internal = 0;
-		t_state = 0;
-		in_hs = 0;
-		in_sep = 0;
-		sep_clr = 0;
-		hs_clr = 0;
-		out = 0;
-		rd1 = 0;
-	end
-
-
-always @(posedge t) 	// Execute at positive edge of t
-	  t_internal <= #(data_delay) t;
-
-always @(posedge wr0) 	// Execute at positive edge of t
-	  wr0_internal <= #(wr0_delay) wr0;
-
-
-always @(posedge t_internal)
-	begin
-	  if (in_sep>0)
-	    begin
-	      t_state = 1'bx;
-
-	    // generating a warning
-	      $fwrite(warning_file, 
-	       "Violation of separation time in module %m.\n");
-	      $fwrite(warning_file,
-	       "Input T pulses at %0d and at %0d.\n", last_t_time, 
-	       $stime-data_delay);
-	    end
-	  last_t_time <= $stime-data_delay;
-
-	  out <= #t_out_delay t_state;
-	  out <= #(t_out_delay+2) 0;
-
-	  t_state = t_state ^ 1;
-	  if (t_internal === 1)
-	    begin
-	      in_sep = in_sep + 1;
-	      sep_clr <= #(t_separation) 1;
-	    end
-	  else
-	    t_state = 1'bx;
-
-// setting the state of the t input
-	  if (t_internal === 1)
-	    begin
-	      in_hs = in_hs+1;
-	      hs_clr <= #(t_hold+t_setup) 1;
-	    end
-	  else
-	    t_state = 1'bx;
-
-	  t_internal <= 0;
-	end
-
-
-always @(posedge hs_clr)
-	begin
-		if ($stime - last_wr0_time < t_hold+t_setup)
-		  begin
-			t_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input T pulse at %0d,",
-			 $stime-data_delay-t_hold-t_setup);
-			$fwrite(warning_file,
-			"\tInput WRITE0 pulse at %0d.\n",
-			 last_wr0_time-wr0_delay);
-		  end
-
-		in_hs = in_hs-1;
-		hs_clr <= 0;
-	end
-
-always @(posedge sep_clr)
-	begin
-	  	in_sep = in_sep - 1;
-		sep_clr <= 0;
-	end
-
-
-always @(posedge wr0_internal)	
-	begin
-// computing the output
-		if ((wr0_internal === 1'bx) || (in_hs>0))
-		  out_value = 1'bx;
-		else
-		  out_value = t_state;
-
-// transfering the result to the output
-		rd1 <= #(wr0_out_delay) out_value;
-		rd1 <= #(wr0_out_delay+2) 0;
-
-// clearing the internal state of T1 flip-flop
-		if(in_hs == 0)
-		  t_state  = 0;
-		else
-		  t_state = 1'bx;
-
-		wr0_internal <= 0;
-		last_wr0_time = $stime;
-	end
-
-
-endmodule
-
-
-  'module', 't1ff', '(', 't', 'wr0', 'out', 'rd1', ')', ';',
-     'input', 't', 'wr0', ';',
-      'output', 'out', 'rd1', ';',
-      'reg', 'out', 'rd1', ';',
-       'parameter',
-        't_separation', '=', '10',
-        'delay', '=', '8',
-        't_hold', '=', '7',
-        't_setup', '=', '6',
-        'rd1_delay', '=', '10',
-        'warning_file', '=', '3',
-        ';',
-       'reg',
-        't_internal',
-        'wr0_internal',
-        't_state',
-        'sep_clr',
-        'hs_clr',
-        ';',
-       'integer',
-        'data_delay',
-        'wr0_delay',
-        't_out_delay',
-        'wr0_out_delay',
-        'last_t_time',
-        'last_wr0_time',
-        'in_hs',
-        'in_sep',
-        'out_value',
-        ';',
-       'initial',
-         'begin',
-            'if',
-              '(', 't_hold', '<', '0', ')',
-               'begin',
-                 'data_delay', '=', '-', 't_hold', ';',
-                  'wr0_delay', '=', '0', ';',
-                'end',
-              'else',
-               'begin',
-                 'data_delay', '=', '0', ';',
-                  'wr0_delay', '=', 't_hold', ';',
-                'end',
-            't_out_delay', '=', 'delay', '-', 'data_delay', ';',
-            'wr0_out_delay', '=', 'rd1_delay', '-', 'wr0_delay', ';',
-            't_internal', '=', '0', ';',
-            'wr0_internal', '=', '0', ';',
-            't_state', '=', '0', ';',
-            'in_hs', '=', '0', ';',
-            'in_sep', '=', '0', ';',
-            'sep_clr', '=', '0', ';',
-            'hs_clr', '=', '0', ';',
-            'out', '=', '0', ';',
-            'rd1', '=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 't', ')',
-         't_internal', '<=', '#', '(', 'data_delay', ')', 't',
-          ';',
-       'always',
-        '@', '(', 'posedge', 'wr0', ')',
-         'wr0_internal', '<=', '#', '(', 'wr0_delay', ')', 'wr0',
-          ';',
-       'always',
-        '@', '(', 'posedge', 't_internal', ')',
-         'begin',
-            'if',
-              '(', 'in_sep', '>', '0', ')',
-               'begin',
-                 't_state', '=', "1 'b x", ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Violation of separation time in module %m.\\n"',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Input T pulses at %0d and at %0d.\\n"',
-                    'last_t_time',
-                    '$stime',
-                    '-',
-                    'data_delay',
-                    ')',
-                    ';',
-                'end',
-            'last_t_time', '<=', '$stime', '-', 'data_delay', ';',
-            'out', '<=', '#', 't_out_delay', 't_state', ';',
-              'out',
-                '<=',
-                '#', '(', 't_out_delay', '+', '2', ')',
-                '0',
-              ';',
-            't_state', '=', 't_state', '^', '1', ';',
-             'if',
-              '(', 't_internal', '===', '1', ')',
-               'begin',
-                 'in_sep', '=', 'in_sep', '+', '1', ';',
-                    'sep_clr',
-                      '<=',
-                      '#', '(', 't_separation', ')',
-                      '1',
-                    ';',
-                'end',
-              'else',
-              't_state', '=', "1 'b x", ';',
-             'if',
-              '(', 't_internal', '===', '1', ')',
-               'begin',
-                 'in_hs', '=', 'in_hs', '+', '1', ';',
-                    'hs_clr',
-                      '<=',
-                      '#', '(', 't_hold', '+', 't_setup', ')',
-                      '1',
-                    ';',
-                'end',
-              'else',
-              't_state', '=', "1 'b x", ';',
-            't_internal', '<=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'hs_clr', ')',
-         'begin',
-            'if',
-               '(',
-                '$stime',
-                '-',
-                'last_wr0_time',
-                '<',
-                't_hold',
-                '+',
-                't_setup',
-                ')',
-               'begin',
-                 't_state', '=', "1 'b x", ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Violation of hold/setup time in module %m.\\n"',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Input T pulse at %0d,"',
-                    '$stime',
-                    '-',
-                    'data_delay',
-                    '-',
-                    't_hold',
-                    '-',
-                    't_setup',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"\\tInput WRITE0 pulse at %0d.\\n"',
-                    'last_wr0_time',
-                    '-',
-                    'wr0_delay',
-                    ')',
-                    ';',
-                'end',
-            'in_hs', '=', 'in_hs', '-', '1', ';',
-            'hs_clr', '<=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'sep_clr', ')',
-         'begin',
-           'in_sep', '=', 'in_sep', '-', '1', ';',
-            'sep_clr', '<=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'wr0_internal', ')',
-         'begin',
-            'if',
-               '(',
-                '(',
-                'wr0_internal', '===', "1 'b x",
-                ')',
-                '||',
-                '(',
-                'in_hs', '>', '0',
-                ')',
-                ')',
-              'out_value', '=', "1 'b x", ';',
-              'else',
-              'out_value', '=', 't_state', ';',
-              'rd1',
-                '<=',
-                '#', '(', 'wr0_out_delay', ')',
-                'out_value',
-              ';',
-              'rd1',
-                '<=',
-                '#', '(', 'wr0_out_delay', '+', '2', ')',
-                '0',
-              ';',
-             'if',
-              '(', 'in_hs', '==', '0', ')',
-              't_state', '=', '0', ';',
-              'else',
-              't_state', '=', "1 'b x", ';',
-            'wr0_internal', '<=', '0', ';',
-            'last_wr0_time', '=', '$stime', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/testcase.v.parsed.txt Deleted

@@ -1,198 +0,0 @@
-`timescale 1ns/1ps
-
-module mult_piped_8x8_2sC (a, b, clk, reset, y);
-
-input7:0 a,b;
-input clk,reset;
-output15:0 y;
-
-  //--------------------------------------
-  // Function: always @ posedge clk       
-  //   y(t=0) = a(t-8) * b(t-8)           
-  //                                      
-  // Simulation: PASSED                   
-  // Synthesis: Needs re-timing feature in
-  //            synthesis tool            
-  //                                      
-  //--------------------------------------
-
-reg7:0 aR8:0;
-reg7:0 bR8:0;
-reg15:0 yR8:0;
-
-always @ (posedge clk) // pipeline_stages
-  begin
-   aR7 = aR6;  // pipeline things
-   bR7 = bR6;
-   yR7 = yR6;
-   aR6 = aR5;
-   bR6 = bR5;
-   yR6 = yR5;
-   aR5 = aR4;
-   bR5 = bR4;
-   yR5 = yR4;
-   aR4 = aR3;
-   bR4 = bR3;
-   yR4 = yR3;
-   aR3 = aR2;
-   bR3 = bR2;
-   yR3 = yR2;
-   aR2 = aR1;
-   bR2 = bR1;
-   yR2 = yR1;
-   aR1 = aR0;
-   bR1 = bR0;
-   yR1 = yR0;
-   aR0 = a;
-   bR0 = b;
-            // multiply result (a*b) appears after +clk
-   yR0 = multiply_8x8_2sC (aR0,bR0);
-  end
-
-function15:0 multiply_8x8_2sC;
-input7:0 a,b;
-reg7:0 a_mag,b_mag;
-reg14:0 y_mag;
-reg14:0 y_neg;
-begin
-  case (a7)
-   0: a_mag = a6:0;
-   1: a_mag = 128 - a6:0;        // max(a_mag) = 128, thus 8 bits
-  endcase
-  case (b7)
-    0: b_mag = b6:0;
-    1: b_mag = 128 - b6:0;
-  endcase
-  y_mag = a_mag * b_mag;            // max(y_mag) = 16384, thus 15 bits
-  if ((a7 ^ b7) & (y_mag != 0)) // if (a * b) is -ve AND non-zero
-  begin                             // y_mag >=1, <= 16256, thus need only 14 bits
-    y_neg = 32768 - y_mag13:0;    // max(y_neg) = 32767, thus need 15 bits
-    multiply_8x8_2sC = {1'b1,y_neg}; 
-  end
-  else
-   multiply_8x8_2sC = y_mag;
-end
-endfunction
-
-assign y = multiply_8x8_2sC (a,b); // un_pipelined_output
-assign y = yR7;
-
-endmodule
-
-
-   'module',
-      'mult_piped_8x8_2sC',
-      '(',
-      'a', 'b', 'clk', 'reset', 'y',
-      ')',
-      ';',
-     'input', '', '7', ':', '0', '', 'a', 'b', ';',
-      'input', 'clk', 'reset', ';',
-      'output', '', '15', ':', '0', '', 'y', ';',
-      'reg', '', '7', ':', '0', '', 'aR', '', '8', ':', '0', '', ';',
-      'reg', '', '7', ':', '0', '', 'bR', '', '8', ':', '0', '', ';',
-      'reg', '', '15', ':', '0', '', 'yR', '', '8', ':', '0', '', ';',
-       'always',
-        '@', '(', 'posedge', 'clk', ')',
-         'begin',
-           'aR', '', '7', '', '=', 'aR', '', '6', '', ';',
-            'bR', '', '7', '', '=', 'bR', '', '6', '', ';',
-            'yR', '', '7', '', '=', 'yR', '', '6', '', ';',
-            'aR', '', '6', '', '=', 'aR', '', '5', '', ';',
-            'bR', '', '6', '', '=', 'bR', '', '5', '', ';',
-            'yR', '', '6', '', '=', 'yR', '', '5', '', ';',
-            'aR', '', '5', '', '=', 'aR', '', '4', '', ';',
-            'bR', '', '5', '', '=', 'bR', '', '4', '', ';',
-            'yR', '', '5', '', '=', 'yR', '', '4', '', ';',
-            'aR', '', '4', '', '=', 'aR', '', '3', '', ';',
-            'bR', '', '4', '', '=', 'bR', '', '3', '', ';',
-            'yR', '', '4', '', '=', 'yR', '', '3', '', ';',
-            'aR', '', '3', '', '=', 'aR', '', '2', '', ';',
-            'bR', '', '3', '', '=', 'bR', '', '2', '', ';',
-            'yR', '', '3', '', '=', 'yR', '', '2', '', ';',
-            'aR', '', '2', '', '=', 'aR', '', '1', '', ';',
-            'bR', '', '2', '', '=', 'bR', '', '1', '', ';',
-            'yR', '', '2', '', '=', 'yR', '', '1', '', ';',
-            'aR', '', '1', '', '=', 'aR', '', '0', '', ';',
-            'bR', '', '1', '', '=', 'bR', '', '0', '', ';',
-            'yR', '', '1', '', '=', 'yR', '', '0', '', ';',
-            'aR', '', '0', '', '=', 'a', ';',
-            'bR', '', '0', '', '=', 'b', ';',
-              'yR', '', '0', '',
-                '=',
-                 'multiply_8x8_2sC',
-                  '(',
-                  'aR', '', '0', '',
-                  'bR', '', '0', '',
-                  ')',
-              ';',
-          'end',
-       'function',
-        '',
-        '15',
-        ':',
-        '0',
-        '',
-        'multiply_8x8_2sC',
-        ';',
-         'input', '', '7', ':', '0', '', 'a', 'b', ';',
-          'reg', '', '7', ':', '0', '', 'a_mag', 'b_mag', ';',
-          'reg', '', '14', ':', '0', '', 'y_mag', ';',
-          'reg', '', '14', ':', '0', '', 'y_neg', ';',
-          'begin',
-              'case',
-                '(',
-                'a', '', '7', '',
-                ')',
-                '0',
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-                '1',
-                ':',
-                 'a_mag', '=', '128', '-', 'a', '', '6', '0', '',
-                  ';',
-                'endcase',
-               'case',
-                '(',
-                'b', '', '7', '',
-                ')',
-                '0',
-                ':',
-                'b_mag', '=', 'b', '', '6', '0', '', ';',
-                '1',
-                ':',
-                 'b_mag', '=', '128', '-', 'b', '', '6', '0', '',
-                  ';',
-                'endcase',
-              'y_mag', '=', 'a_mag', '*', 'b_mag', ';',
-               'if',
-                 '(',
-                  '(',
-                  'a', '', '7', '', '^', 'b', '', '7', '',
-                  ')',
-                  '&',
-                  '(',
-                  'y_mag', '!=', '0',
-                  ')',
-                  ')',
-                 'begin',
-                     'y_neg',
-                        '=',
-                        '32768',
-                        '-',
-                        'y_mag', '', '13', '0', '',
-                      ';',
-                      'multiply_8x8_2sC',
-                        '=',
-                        '{', "1 'b 1", 'y_neg', '}',
-                      ';',
-                  'end',
-                'else',
-                'multiply_8x8_2sC', '=', 'y_mag', ';',
-            'end',
-        'endfunction',
-       'assign',
-        'y', '=', 'multiply_8x8_2sC', '(', 'a', 'b', ')',
-        ';',
-      'assign', 'y', '=', 'yR', '', '7', '', ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/testcase2.v.parsed.txt Deleted

@@ -1,506 +0,0 @@
-module tap_controller (tms,
-   tck,
-   trst,
-   sel,
-   enable,
-   test_logic_reset,
-   idle,
-   resetn,
-   shift_ir,
-   update_ir,
-   clock_ir,
-   shift_dr,
-   capture_dr,
-   clock_dr,
-   update_dr);
-
-input   tms;
-input   tck;
-input   trst;
-output  sel;
-output  enable;
-output  test_logic_reset;
-output  idle;
-output  resetn;
-output  shift_ir;
-output  update_ir;
-output  clock_ir;
-output  shift_dr;
-output  capture_dr;
-output  clock_dr;
-output  update_dr;
-wire    sel;
-reg     enable;
-wire    test_logic_reset;
-wire    idle;
-reg     resetn;
-reg     shift_ir;
-wire    update_ir;
-wire    clock_ir;
-reg     shift_dr;
-wire    capture_dr;
-wire    clock_dr;
-wire    update_dr;
-reg     D;
-reg     C;
-reg     B;
-reg     A;
-wire    NA;
-wire    NB;
-wire    NC;
-wire    ND;
-wire    GRST;
-wire    GENB;
-wire    GSIR;
-wire    GSDR;
-wire    tckd;
-wire    trsthi;
-wire    tmsbuf;
-wire    trstnbuf;
-
-initial 
-   begin
-   A = 'b 1;
-   end
-
-initial 
-   begin
-   B = 'b 1;
-   end
-
-initial 
-   begin
-   C = 'b 1;
-   end
-
-initial 
-   begin
-   D = 'b 1;
-   end
-
-always @(posedge trsthi or posedge tckd)
-   begin
-   if (trsthi == 'b 1)
-
-      resetn <= 'b 0; else if (tckd== 'b 1 ) resetn <=GRST; 
-	  
-   end 
-	  
-always @(posedge trsthi or posedge tckd) begin 
-      if (trsthi== 'b 1) enable <='b 0;
-
-      else if (tckd ==  'b 1 ) enable <=GENB; end 
-
-always @(posedge trsthi or posedge tckd) begin 
-      if (trsthi== 'b 1) shift_ir <='b 1;
-
-      else if (tckd ==  'b 1 ) shift_ir <=GSIR; end 
-	  
-
-always @(posedge trsthi or posedge tckd) begin 
-      if (trsthi== 'b 1) shift_dr <='b 1;
-
-      else if (tckd ==  'b 1 ) shift_dr <=GSDR; end 
-	  
-
-always @(posedge trsthi or posedge tck) begin 
-      if (trsthi== 'b 1) D <='b 1;
-
-      else if (tck ==  'b 1 ) D <=ND; end 
-
-always @(posedge trsthi or posedge tck) begin 
-      if (trsthi== 'b 1) C <='b 1;
-
-      else if (tck ==  'b 1 ) C <=NC; end 
-	  
-
-always @(posedge trsthi or posedge tck) begin 
-      if (trsthi== 'b 1) B <='b 1;
-
-      else if (tck ==  'b 1 ) B <=NB; end 
-	  
-
-always @(posedge trsthi or posedge tck) begin 
-      if (trsthi== 'b 1) A <='b 1;
-
-      else if (tck ==  'b 1 ) A <=NA; end 
-
-
-  assign trsthi=~trstnbuf; assign sel=D; assign tckd=~tck; 
-  assign clock_ir=~(~A & B & D & tckd); assign update_ir=A & ~B & C & D & tckd; 
-  assign clock_dr=~(~A & B & ~D & tckd); assign test_logic_reset=A & B & C & D; 
-  assign idle=~A & ~B & C & D; 
-  assign update_dr=A & ~B & C & ~D & tckd; 
-  assign capture_dr=~A & B & C & ~D; 
-  assign tmsbuf=tms; assign trstnbuf=trst; 
-  assign NA=~(~(~tmsbuf & ~C & A) & ~(tmsbuf & ~B) & ~(tmsbuf & ~A) & ~(tmsbuf & C & D)); 
-  assign NB=~(~(~tmsbuf & B & ~A) & ~(~tmsbuf & ~C) & ~(~tmsbuf & ~D & B) 
-       & ~(~tmsbuf & ~D & ~A) & ~(tmsbuf & C & ~B) & ~(tmsbuf & D & C & A)); 
-  assign NC=~(~(C & ~B) & ~(C & A) & ~(tmsbuf & ~B)); 
-  assign ND=~(~(D & ~C) & ~(D & B) & ~(~tmsbuf & C & ~B) & ~(~D & C & ~B & ~A)); 
-  assign GRST=~(A & B & C & D); assign GSIR=~A & B & ~C & D; 
-  assign GSDR=~A & B & ~C & ~D; assign GENB=GSIR | GSDR; 
-
-endmodule // module tap_controller 
-
-
-   'module',
-      'tap_controller',
-      '(',
-       'tms',
-        'tck',
-        'trst',
-        'sel',
-        'enable',
-        'test_logic_reset',
-        'idle',
-        'resetn',
-        'shift_ir',
-        'update_ir',
-        'clock_ir',
-        'shift_dr',
-        'capture_dr',
-        'clock_dr',
-        'update_dr',
-      ')',
-      ';',
-     'input', 'tms', ';',
-      'input', 'tck', ';',
-      'input', 'trst', ';',
-      'output', 'sel', ';',
-      'output', 'enable', ';',
-      'output', 'test_logic_reset', ';',
-      'output', 'idle', ';',
-      'output', 'resetn', ';',
-      'output', 'shift_ir', ';',
-      'output', 'update_ir', ';',
-      'output', 'clock_ir', ';',
-      'output', 'shift_dr', ';',
-      'output', 'capture_dr', ';',
-      'output', 'clock_dr', ';',
-      'output', 'update_dr', ';',
-      'wire', 'sel', ';',
-      'reg', 'enable', ';',
-      'wire', 'test_logic_reset', ';',
-      'wire', 'idle', ';',
-      'reg', 'resetn', ';',
-      'reg', 'shift_ir', ';',
-      'wire', 'update_ir', ';',
-      'wire', 'clock_ir', ';',
-      'reg', 'shift_dr', ';',
-      'wire', 'capture_dr', ';',
-      'wire', 'clock_dr', ';',
-      'wire', 'update_dr', ';',
-      'reg', 'D', ';',
-      'reg', 'C', ';',
-      'reg', 'B', ';',
-      'reg', 'A', ';',
-      'wire', 'NA', ';',
-      'wire', 'NB', ';',
-      'wire', 'NC', ';',
-      'wire', 'ND', ';',
-      'wire', 'GRST', ';',
-      'wire', 'GENB', ';',
-      'wire', 'GSIR', ';',
-      'wire', 'GSDR', ';',
-      'wire', 'tckd', ';',
-      'wire', 'trsthi', ';',
-      'wire', 'tmsbuf', ';',
-      'wire', 'trstnbuf', ';',
-      'initial', 'begin', 'A', '=', "'b 1", ';', 'end',
-      'initial', 'begin', 'B', '=', "'b 1", ';', 'end',
-      'initial', 'begin', 'C', '=', "'b 1", ';', 'end',
-      'initial', 'begin', 'D', '=', "'b 1", ';', 'end',
-       'always',
-        '@', '(', 'posedge', 'trsthi', 'posedge', 'tckd', ')',
-         'begin',
-            'if',
-              '(', 'trsthi', '==', "'b 1", ')',
-              'resetn', '<=', "'b 0", ';',
-              'else',
-               'if',
-                '(', 'tckd', '==', "'b 1", ')',
-                'resetn', '<=', 'GRST', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'trsthi', 'posedge', 'tckd', ')',
-         'begin',
-            'if',
-              '(', 'trsthi', '==', "'b 1", ')',
-              'enable', '<=', "'b 0", ';',
-              'else',
-               'if',
-                '(', 'tckd', '==', "'b 1", ')',
-                'enable', '<=', 'GENB', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'trsthi', 'posedge', 'tckd', ')',
-         'begin',
-            'if',
-              '(', 'trsthi', '==', "'b 1", ')',
-              'shift_ir', '<=', "'b 1", ';',
-              'else',
-               'if',
-                '(', 'tckd', '==', "'b 1", ')',
-                'shift_ir', '<=', 'GSIR', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'trsthi', 'posedge', 'tckd', ')',
-         'begin',
-            'if',
-              '(', 'trsthi', '==', "'b 1", ')',
-              'shift_dr', '<=', "'b 1", ';',
-              'else',
-               'if',
-                '(', 'tckd', '==', "'b 1", ')',
-                'shift_dr', '<=', 'GSDR', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'trsthi', 'posedge', 'tck', ')',
-         'begin',
-            'if',
-              '(', 'trsthi', '==', "'b 1", ')',
-              'D', '<=', "'b 1", ';',
-              'else',
-               'if',
-                '(', 'tck', '==', "'b 1", ')',
-                'D', '<=', 'ND', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'trsthi', 'posedge', 'tck', ')',
-         'begin',
-            'if',
-              '(', 'trsthi', '==', "'b 1", ')',
-              'C', '<=', "'b 1", ';',
-              'else',
-               'if',
-                '(', 'tck', '==', "'b 1", ')',
-                'C', '<=', 'NC', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'trsthi', 'posedge', 'tck', ')',
-         'begin',
-            'if',
-              '(', 'trsthi', '==', "'b 1", ')',
-              'B', '<=', "'b 1", ';',
-              'else',
-               'if',
-                '(', 'tck', '==', "'b 1", ')',
-                'B', '<=', 'NB', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'trsthi', 'posedge', 'tck', ')',
-         'begin',
-            'if',
-              '(', 'trsthi', '==', "'b 1", ')',
-              'A', '<=', "'b 1", ';',
-              'else',
-               'if',
-                '(', 'tck', '==', "'b 1", ')',
-                'A', '<=', 'NA', ';',
-          'end',
-      'assign', 'trsthi', '=', '~', 'trstnbuf', ';',
-      'assign', 'sel', '=', 'D', ';',
-      'assign', 'tckd', '=', '~', 'tck', ';',
-       'assign',
-         'clock_ir',
-          '=',
-          '~',
-          '(',
-          '~', 'A', '&', 'B', '&', 'D', '&', 'tckd',
-          ')',
-        ';',
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-          '=',
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-          '&',
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-          '(',
-          '~', 'A', '&', 'B', '&', '~', 'D', '&', 'tckd',
-          ')',
-        ';',
-       'assign',
-        'test_logic_reset', '=', 'A', '&', 'B', '&', 'C', '&', 'D',
-        ';',
-       'assign',
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-        ';',
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-            ')',
-            '&',
-            '~',
-            '(',
-            '~', 'tmsbuf', '&', 'C', '&', '~', 'B',
-            ')',
-            '&',
-            '~',
-            '(',
-            '~', 'D', '&', 'C', '&', '~', 'B', '&', '~', 'A',
-            ')',
-          ')',
-        ';',
-       'assign',
-         'GRST',
-          '=',
-          '~',
-          '(',
-          'A', '&', 'B', '&', 'C', '&', 'D',
-          ')',
-        ';',
-       'assign',
-        'GSIR', '=', '~', 'A', '&', 'B', '&', '~', 'C', '&', 'D',
-        ';',
-       'assign',
-         'GSDR',
-          '=',
-          '~',
-          'A',
-          '&',
-          'B',
-          '&',
-          '~',
-          'C',
-          '&',
-          '~',
-          'D',
-        ';',
-      'assign', 'GENB', '=', 'GSIR', '|', 'GSDR', ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/testcase3.v.parsed.txt Deleted

@@ -1,817 +0,0 @@
-// A Verilog example taken from comp.lang.verilog
-
-
-//-----------------------Cache Coherence Protocol-----------------------------
-// This finite-state machine (Melay type) reads bus 
-// per cycle and changes the state of each block in cache.
-
-module cache_coherence ( 
-	new_state, 
-	Cache_Sector_Fill, 
-	Invalidate,  
-	AdrRetry,
-	RMS, 
-	RME, 
-	WM, 
-	WH,  
-	SHR, 
-	SHW, 
-	state, 
-	READ_DONE, 
-	clk, 
-	reset, 
-	send_abort, 
-	write_back_done,
-	AllInvDone);
-
-input RMS, RME, WM, WH, SHR, SHW, READ_DONE, clk, 
-      reset, send_abort, write_back_done, AllInvDone;
-
-input 2:0 state;
-
-output 2:0 new_state;
-output Cache_Sector_Fill, Invalidate, AdrRetry;
-
-reg Cache_Sector_Fill, Invalidate, AdrRetry ;
-reg 2:0 new_state; 
-
-// The four possible states (symbolic names) for a sector 
-// in the cache plus 2 mandatory states
-
-parameter /*2:0*/ // synopsys enum state_info
-	INVALID = 3'b000,
-	SHARED_1 = 3'b001,
-	EXCLUSIVE = 3'b010,
-	MODIFIED = 3'b011,
-	Cache_Fill = 3'b100,
-	start_write_back = 3'b101,
-	/* start_write_back = 5, */
-	WaitUntilAllInv = 3'b110;
-
-// Declare current_state and next_state variable.
-reg 2:0 	/* synopsys enum state_info */	present_state;
-reg 2:0	/* synopsys enum state_info */	next_state;
-// synopsys state_vector present_state
-
-/* Combinational */
-always @(present_state or RMS or RME or WM or WH or SHW or READ_DONE 
-         or SHR or write_back_done or AllInvDone or send_abort or state or reset) 
-begin
-	Cache_Sector_Fill = 0; 	// Default values
-	Invalidate = 0; 
-	AdrRetry = 0; 
-	next_state = present_state; 
-	if (reset) next_state = state; else 
-	begin
-	case(present_state) 	// synopsys full_case
-		INVALID: 
-			// ReadMiss (shared/exclusive), Write Miss
-			if (RMS || RME || WM)  			 
-			begin
-				Cache_Sector_Fill = 1;
-				next_state = Cache_Fill ;
-			end
-			else 
-			begin 
-				next_state = INVALID;
-			end
-
-		Cache_Fill:	
-			/* During This State Cache is filled with the sector,
-			   But if any other processor have that copy in modified 
-			   state, it sends an abort signal. If no other cache has
-			   that copy in modified state. Requesting processor waits
-			   for the read from memory to be done.
-			*/
-			if (send_abort) 
-			begin 
-				next_state = INVALID;
-			end
-			else if (READ_DONE) 
-			begin
-				if (RMS) 
-				begin
-					next_state = SHARED_1;
-				end
-				else if (RME) 
-				begin 
-					next_state = EXCLUSIVE;	
-				end
-				else if (WM)
-				begin
-					Invalidate = 1;
-					next_state = WaitUntilAllInv;
-				end 
-				else 
-				begin 
-					next_state = Cache_Fill ;
-				end
-			end	
-			else 
-			begin 
-				next_state = Cache_Fill ;
-			end
-			
-		SHARED_1:	  
-			if (SHW) // Snoop Hit on a Write.
-			begin 
-				next_state = INVALID;		
-			end
-			else if (WH) // Write Hit				
-			begin
-				Invalidate = 1;
-				next_state = WaitUntilAllInv;
-			end 
-			else 
-			begin // Snoop Hit on a Read or Read Hit or any other
-				next_state = SHARED_1; 		
-			end
-
-		WaitUntilAllInv:
-			/* In this state Requesting Processor waits for the 
-			   all other processor's to invalidate its cache copy.
-			*/
-
-			if (AllInvDone) 
-			begin 
-				next_state = MODIFIED;
-			end
-			else 
-			begin 
-				next_state = WaitUntilAllInv;
-			end
-
-		EXCLUSIVE: 
-								
-			if (SHR) // Snoop Hit on a Read:
-			begin
-				AdrRetry = 0;
-				next_state = SHARED_1;  
-			end 					
-			else if (SHW) // Snoop Hit on a Write 
-			begin
-				next_state = INVALID;	
-			end
-			else if (WH) // Write Hit
-			begin
-				next_state = MODIFIED;	
-			end
-			else 
-			begin // Read Hit 
-				next_state = EXCLUSIVE;		
-			end
-
-		MODIFIED:  	
-			if (SHW) // Snoop Hit on a Write 
-			begin
-				next_state = INVALID;		
-			end
-			else if (SHR) // Snoop Hit on a Read 			
-			begin
-				AdrRetry = 1;
-				next_state = start_write_back;
-			end
-			else // Read Hit or Write Hit or anything else.
-			begin
-				next_state = MODIFIED; 		
-			end
-
-		start_write_back: 
-			/* In this state, Processor waits until other processor 
-			   has written back the modified copy.
-			*/
-			if (write_back_done) 
-			begin
-				next_state = SHARED_1; 
-			end
-			else
-			begin 
-				next_state = start_write_back;
-			end
-			
-	endcase
-	end
-	
-end
-
-/* Sequential */
-always @(posedge clk) 
-begin
-	present_state = next_state;
-	new_state = next_state;
-end
-endmodule
-
-
-//--------------Test File: Maintaining Cache coherence in 2-processor Systems------
-/* Test File for Maintaining Cache Coherence in 2-processor system */
-
-module cache;
-
-reg RMS, RME, WM, WH, RH, SHR, SHW, clk, READ_DONE , reset, send_abort, write_back_done, AllInvDone, PA, PB, countE;
-reg 2:0 state, SectorInCacheA, SectorInCacheB;
-reg 3:0 count;
-integer file1;
-
-parameter CYCLE = 10;
-
-wire 2:0 new_state;
-wire Cache_Sector_Fill, Invalidate;
-/*
-cache_coherence u1 (
-	new_state, 
-	Cache_Sector_Fill, 
-	Invalidate, 
-	AdrRetry, 
-	RMS, RME, 
-	WM, WH, 
-	SHR, SHW, 
-	state, READ_DONE, clk, reset, send_abort, write_back_done, AllInvDone); 
-*/
-initial
-begin
-	$display("Example: maintaining cache coherence in 2-processor system");
-
-	file1 = $fopen("cache.list");
-	$fdisplay(file1, "Example: maintaining cache coherence in 2-processor system");
-
-	/* The states of sector in both caches are initialized to Invalid (0). */
-	SectorInCacheA = 0; SectorInCacheB = 0;
- 
-	/* Signals set/rest by cache controller */
-	// Write Hit
-	WH = 0;
-
-	// ReadMiss (Shared)
-	RMS = 0;
-
-	// WriteMiss
-	WM  = 0;
-
-	// Snoop hit on read operation
-	SHR = 0;
-
-	// Snoop hit on write operation
-	SHW = 0;
-
-	// This signal is set/reset,
-	// when a cache controller starts or finish reading a sector from memory
-	READ_DONE = 0;
-
-	// This signal is set when all other cache controllers 
-	// invalidate their copy.
-	AllInvDone = 0;
-
-	// This signal is set when cache controller finishes updating memory.
-	write_back_done = 0;
-
-	// This signal is set when snoopy cache controller sends 
-	// AdrRetry Signal to retry the operation. 
-	send_abort = 0;
-
-	// Present State of the Sector is INVALID in PA's local cache.
-	// So, it puts the address of this sector on the bus and starts
-	// reading this sector from memory.
-
-	state = SectorInCacheA ; PA = 1; PB = 0; RME = 1; 
-	reset = 1; #6 reset = 0;
-
-	// After 15 time units Processor B will declare  
-	// Snoop Hit on the Read operation done by Processor A.
-	#40 PA = 0; PB = 1; RME = 0; RMS = 1; state = SectorInCacheB; 
-	reset = 1;#10 reset = 0;
-
-	#50 PB = 0; PA = 1; SHR = 1; state = SectorInCacheA; 
-	reset = 1; #10 reset = 0;
-	
-	#20 SHR = 0; WH = 1; state = SectorInCacheA; 
-	reset = 1; #10 reset = 0;
-
-	#50 PA = 0; PB = 1; RMS = 1; WH = 0; state = SectorInCacheB; 
-	reset = 1; #10 reset = 0;
-
-	#30 SHR = 1; RMS = 0; PA = 1; PB = 0; state = SectorInCacheA; 
-	reset = 1; #10 reset = 0;
-	
-	#20 PB = 1; PA = 0; SHR = 0; state = SectorInCacheB; 
-	reset = 1; #10 reset = 0;
-
-	// PA states writing back.
-	#20 PB = 0; PA = 1; state = SectorInCacheA; 
-	reset = 1; #10 reset = 0;
-
-	// This signal is broadcast on the bus to tell every body that 
-	// Processor B has written back its Modified data back to the Memory 
-	// to make everything consistent. After 5 time units it is set back to 
-	// Zero. 
-
-	#30 write_back_done = 1;
-	#10 write_back_done = 0;
-
-	// PB retry.
-	#10 PA = 0; PB = 1; RMS = 1; state = SectorInCacheB; 
-	reset = 1; #10 reset = 0;
-
-//	#100 $stop;
-//	#100 $finish;
-end
-
-always @(new_state)
-begin
-	if (PA == 1) SectorInCacheA = new_state ;
-	else if (PB == 1) SectorInCacheB = new_state ;
-end
-
-always @(posedge clk)
-begin
-	if (Invalidate)
-	begin	
-		#10 SectorInCacheB = 0;
-		#10 AllInvDone = 1;
-		#15 AllInvDone = 0;
-	end
-	else if (Cache_Sector_Fill)
-	begin
-		count = 0;
-		countE = 1;
-
-		// Intialize the Read_Done variable to 0; it 
-		// it will be set to 1 by this test file after
-		// some delay.
-		READ_DONE = 0;
-	end
-	else if (AdrRetry)
-	begin
-		countE = 0;
-		send_abort = 1;
-		#40 send_abort = 0;
-	end
-end
-
-always @(posedge clk)
-begin
-	if (READ_DONE == 1) READ_DONE = 0;
-	if (countE == 1)
-	begin
-		if ( count == 2 )
-		begin
-			READ_DONE = 1;
-			countE = 0;
-		end
-		else count = count + 1;
-	end
-$display("SHit %b Abort %b RD_DONE %b WB_DONE %b Cache_Sector_Fill %b Inv %b AllInvDone %b stateA %b stateB %b", SHR, send_abort, READ_DONE, write_back_done, Cache_Sector_Fill, Invalidate, AllInvDone, SectorInCacheA, SectorInCacheB);
-
-// Added for v2v testing
-
-$fdisplay(file1, $time,,"SHit %b Abort %b RD_DONE %b WB_DONE %b Cache_Sector_Fill %b Inv %b AllInvDone %b stateA %b stateB %b", SHR, send_abort, READ_DONE, write_back_done, Cache_Sector_Fill, Invalidate, AllInvDone, SectorInCacheA, SectorInCacheB);
-
-end
-
-initial clk = 0;
-
-always #(CYCLE/2) clk = ~clk ;
-
-endmodule 
-
-
-   'module',
-      'cache_coherence',
-      '(',
-       'new_state',
-        'Cache_Sector_Fill',
-        'Invalidate',
-        'AdrRetry',
-        'RMS',
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-        'WH',
-        'SHR',
-        'SHW',
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-        'AllInvDone',
-      ')',
-      ';',
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-       'parameter',
-        'INVALID', '=', "3 'b 000",
-        'SHARED_1', '=', "3 'b 001",
-        'EXCLUSIVE', '=', "3 'b 010",
-        'MODIFIED', '=', "3 'b 011",
-        'Cache_Fill', '=', "3 'b 100",
-        'start_write_back', '=', "3 'b 101",
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-         'begin',
-            'if',
-              '(', 'PA', '==', '1', ')',
-              'SectorInCacheA', '=', 'new_state', ';',
-              'else',
-               'if',
-                '(', 'PB', '==', '1', ')',
-                'SectorInCacheB', '=', 'new_state', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'clk', ')',
-         'begin',
-            'if',
-              '(', 'Invalidate', ')',
-               'begin',
-                 '#', '10', 'SectorInCacheB', '=', '0', ';',
-                  '#', '10', 'AllInvDone', '=', '1', ';',
-                  '#', '15', 'AllInvDone', '=', '0', ';',
-                'end',
-              'else',
-               'if',
-                '(', 'Cache_Sector_Fill', ')',
-                 'begin',
-                   'count', '=', '0', ';',
-                    'countE', '=', '1', ';',
-                    'READ_DONE', '=', '0', ';',
-                  'end',
-                'else',
-                 'if',
-                  '(', 'AdrRetry', ')',
-                   'begin',
-                     'countE', '=', '0', ';',
-                      'send_abort', '=', '1', ';',
-                      '#', '40', 'send_abort', '=', '0', ';',
-                    'end',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'clk', ')',
-         'begin',
-            'if',
-              '(', 'READ_DONE', '==', '1', ')',
-              'READ_DONE', '=', '0', ';',
-             'if',
-              '(', 'countE', '==', '1', ')',
-               'begin',
-                  'if',
-                    '(', 'count', '==', '2', ')',
-                     'begin',
-                       'READ_DONE', '=', '1', ';',
-                        'countE', '=', '0', ';',
-                      'end',
-                    'else',
-                    'count', '=', 'count', '+', '1', ';',
-                'end',
-             '$display',
-              '(',
-              '"SHit %b Abort %b RD_DONE %b WB_DONE %b Cache_Sector_Fill %b '
-              'Inv %b AllInvDone %b stateA %b stateB %b"',
-              'SHR',
-              'send_abort',
-              'READ_DONE',
-              'write_back_done',
-              'Cache_Sector_Fill',
-              'Invalidate',
-              'AllInvDone',
-              'SectorInCacheA',
-              'SectorInCacheB',
-              ')',
-              ';',
-             '$fdisplay',
-              '(',
-              'file1',
-              '$time',
-              '"SHit %b Abort %b RD_DONE %b WB_DONE %b Cache_Sector_Fill %b '
-              'Inv %b AllInvDone %b stateA %b stateB %b"',
-              'SHR',
-              'send_abort',
-              'READ_DONE',
-              'write_back_done',
-              'Cache_Sector_Fill',
-              'Invalidate',
-              'AllInvDone',
-              'SectorInCacheA',
-              'SectorInCacheB',
-              ')',
-              ';',
-          'end',
-      'initial', 'clk', '=', '0', ';',
-       'always',
-         '#', '(', 'CYCLE', '/', '2', ')',
-          'clk', '=', '~', 'clk', ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/testcase4.v.parsed.txt Deleted

@@ -1,237 +0,0 @@
-`timescale 1 ns/100 ps
-// Behavioral description of FIFO with:
-// active high write enable
-// active high read  enable
-// active low asynchronous clear
-// rising edge clock
-// active high full  flag
-// active low  empty flag
-
-module reg_fifo (Data, Q, Aclr, Clock, WE, RE, FF, EF);
-
-parameter width = 8;
-parameter depth = 8;
-parameter addr  = 3;
-
-input Clock, WE, RE, Aclr;
-input width-1:0 Data;
-output FF, EF; //Full & Empty Flags
-output width-1:0 Q;
-reg    width-1:0 Q;
-reg    width-1:0 mem_data depth-1:0;
-reg    addr -1:0 WAddress, RAddress;
-reg    FF, EF;
-
-// Write functional section
-always @ (posedge Clock or negedge Aclr)
-begin
-  if(!Aclr)
-    WAddress = #2 0;
-  else if(WE)
-    WAddress = #2 WAddress + 1;
-end
-
-// Write reg
-always @ (posedge Clock)
-begin
-  if(WE)
-    mem_dataWAddress = Data;
-end
-
-// Read functional section
-always @ (posedge Clock or negedge Aclr)
-begin
-  if(!Aclr)
-    RAddress = #1 0;
-  else if (RE)
-    RAddress = #1 RAddress + 1;
-end
-
-// Read reg
-always @ (posedge Clock)
-begin
-  if(RE)
-    Q = mem_dataRAddress;
-end
-
-// Full Flag
-always @ (posedge Clock or negedge Aclr)
-begin
-  if(!Aclr)
-    FF = #1 1'b0;
-  else if
-  (
-    (WE & !RE) && //Write operation
-      ( //Next cycle is full 
-        (WAddress == RAddress-1) || 
-        ( (WAddress == depth-1) && (RAddress == 1'b0) )
-      )
-  )
-    FF = #1 1'b1;
-  else
-    FF = #1 1'b0;
-end
-
-// Empty Flag
-always @ (posedge Clock or negedge Aclr)
-begin
-  if(!Aclr)
-    EF = #1 1'b0;
-  else if
-  (
-    (!WE & RE) && //Read operation
-      ( //Next cycle is empty 
-        (WAddress == RAddress+1) || 
-        ( (RAddress == depth-1) && (WAddress == 1'b0) )
-      )
-  )
-    EF = #1 1'b0;
-  else
-    EF = #1 1'b1;
-end
-
-endmodule
-
-
-
-   'module',
-      'reg_fifo',
-      '(',
-      'Data', 'Q', 'Aclr', 'Clock', 'WE', 'RE', 'FF', 'EF',
-      ')',
-      ';',
-     'parameter', 'width', '=', '8', ';',
-      'parameter', 'depth', '=', '8', ';',
-      'parameter', 'addr', '=', '3', ';',
-      'input', 'Clock', 'WE', 'RE', 'Aclr', ';',
-      'input', '', 'width', '-', '1', ':', '0', '', 'Data', ';',
-      'output', 'FF', 'EF', ';',
-      'output', '', 'width', '-', '1', ':', '0', '', 'Q', ';',
-      'reg', '', 'width', '-', '1', ':', '0', '', 'Q', ';',
-       'reg',
-        '',
-        'width',
-        '-',
-        '1',
-        ':',
-        '0',
-        '',
-        'mem_data', '', 'depth', '-', '1', ':', '0', '',
-        ';',
-       'reg',
-        '',
-        'addr',
-        '-',
-        '1',
-        ':',
-        '0',
-        '',
-        'WAddress',
-        'RAddress',
-        ';',
-      'reg', 'FF', 'EF', ';',
-       'always',
-        '@', '(', 'posedge', 'Clock', 'negedge', 'Aclr', ')',
-         'begin',
-            'if',
-              '(', '!', 'Aclr', ')',
-              'WAddress', '=', '#', '2', '0', ';',
-              'else',
-               'if',
-                '(', 'WE', ')',
-                 'WAddress', '=', '#', '2', 'WAddress', '+', '1',
-                  ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'Clock', ')',
-         'begin',
-            'if',
-              '(', 'WE', ')',
-              'mem_data', '', 'WAddress', '', '=', 'Data', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'Clock', 'negedge', 'Aclr', ')',
-         'begin',
-            'if',
-              '(', '!', 'Aclr', ')',
-              'RAddress', '=', '#', '1', '0', ';',
-              'else',
-               'if',
-                '(', 'RE', ')',
-                 'RAddress', '=', '#', '1', 'RAddress', '+', '1',
-                  ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'Clock', ')',
-         'begin',
-            'if',
-              '(', 'RE', ')',
-              'Q', '=', 'mem_data', '', 'RAddress', '', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'Clock', 'negedge', 'Aclr', ')',
-         'begin',
-            'if',
-              '(', '!', 'Aclr', ')',
-              'FF', '=', '#', '1', "1 'b 0", ';',
-              'else',
-               'if',
-                 '(',
-                  '(',
-                  'WE', '&', '!', 'RE',
-                  ')',
-                  '&&',
-                  '(',
-                   '(',
-                    'WAddress', '==', 'RAddress', '-', '1',
-                    ')',
-                    '||',
-                    '(',
-                     '(',
-                      'WAddress', '==', 'depth', '-', '1',
-                      ')',
-                      '&&',
-                      '(',
-                      'RAddress', '==', "1 'b 0",
-                      ')',
-                    ')',
-                  ')',
-                  ')',
-                'FF', '=', '#', '1', "1 'b 1", ';',
-                'else',
-                'FF', '=', '#', '1', "1 'b 0", ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'Clock', 'negedge', 'Aclr', ')',
-         'begin',
-            'if',
-              '(', '!', 'Aclr', ')',
-              'EF', '=', '#', '1', "1 'b 0", ';',
-              'else',
-               'if',
-                 '(',
-                  '(',
-                  '!', 'WE', '&', 'RE',
-                  ')',
-                  '&&',
-                  '(',
-                   '(',
-                    'WAddress', '==', 'RAddress', '+', '1',
-                    ')',
-                    '||',
-                    '(',
-                     '(',
-                      'RAddress', '==', 'depth', '-', '1',
-                      ')',
-                      '&&',
-                      '(',
-                      'WAddress', '==', "1 'b 0",
-                      ')',
-                    ')',
-                  ')',
-                  ')',
-                'EF', '=', '#', '1', "1 'b 0", ';',
-                'else',
-                'EF', '=', '#', '1', "1 'b 1", ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/testcase5.v.parsed.txt Deleted

@@ -1,95 +0,0 @@
-// basic demo which generates a clock 
-// and uses 3 ScriptSim programs to 
-// control the bus, act as memory, and monitor the bus 
-module Demo; 
-   wire clock; 
-   wire 1:0  #1 op; 
-   wire 15:0 #1 adr; 
-   wire 31:0 #1 data; 
-
-   reg clock_reg; 
-   reg 1:0  op_reg; 
-   reg 15:0 adr_reg; 
-   reg 31:0 data_read; 
-   reg 31:0 data_write; 
-
-   assign clock = clock_reg; 
-   assign op = op_reg; 
-   assign adr = adr_reg; 
-   assign data = data_write; 
-   assign data = data_read; 
-
-   initial begin: main_block 
-      clock_reg = 1; 
-      $scriptsim("monitor.pl", clock, op, adr, data); 
-      $scriptsim("master.pl",  clock, op_reg, adr_reg, data_write); 
-      $scriptsim("slave.pl",   clock, op, adr, data, data_read); 
-   end // block: main_block 
-
-   // generate a clock with 10ns period 
-   always begin: clock_gen 
-      #5 clock_reg = 1; 
-      #5 clock_reg = 0; 
-   end // block: clock_gen 
-
-endmodule // Demo 
-  
-
-
-  'module', 'Demo', ';',
-     'wire', 'clock', ';',
-      'wire', '', '1', ':', '0', '', '#', '1', 'op', ';',
-      'wire', '', '15', ':', '0', '', '#', '1', 'adr', ';',
-      'wire', '', '31', ':', '0', '', '#', '1', 'data', ';',
-      'reg', 'clock_reg', ';',
-      'reg', '', '1', ':', '0', '', 'op_reg', ';',
-      'reg', '', '15', ':', '0', '', 'adr_reg', ';',
-      'reg', '', '31', ':', '0', '', 'data_read', ';',
-      'reg', '', '31', ':', '0', '', 'data_write', ';',
-      'assign', 'clock', '=', 'clock_reg', ';',
-      'assign', 'op', '=', 'op_reg', ';',
-      'assign', 'adr', '=', 'adr_reg', ';',
-      'assign', 'data', '=', 'data_write', ';',
-      'assign', 'data', '=', 'data_read', ';',
-       'initial',
-         'begin',
-          ':',
-          'main_block',
-          'clock_reg', '=', '1', ';',
-           '$scriptsim',
-            '(',
-            '"monitor.pl"',
-            'clock',
-            'op',
-            'adr',
-            'data',
-            ')',
-            ';',
-           '$scriptsim',
-            '(',
-            '"master.pl"',
-            'clock',
-            'op_reg',
-            'adr_reg',
-            'data_write',
-            ')',
-            ';',
-           '$scriptsim',
-            '(',
-            '"slave.pl"',
-            'clock',
-            'op',
-            'adr',
-            'data',
-            'data_read',
-            ')',
-            ';',
-          'end',
-       'always',
-         'begin',
-          ':',
-          'clock_gen',
-          '#', '5', 'clock_reg', '=', '1', ';',
-          '#', '5', 'clock_reg', '=', '0', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/tff.v.parsed.txt Deleted

@@ -1,159 +0,0 @@
-// Verilog HDL for "gates.lib", "tff" "_functional"
-// Module T flip-flop
-module tff (in, out, nout);
-
-input
-	in;
-
-output
-	out, nout;
-reg 
-	out, nout;
-
-parameter
-	t_separation = 10,
-	delay=15,
-
-	warning_file=3;  // multichannel description of a warning file
-
-reg
-	t_state,  // internal state of T flip-flop
-	sep_clr; // signal marking the end of the min separation zone
-		 //  for the last pulse
-
-integer
-	last_t_time,    // time when the last t pulse appeared
-	in_sep;	 // number of pulses within an interval t_sep before 
-		 //  the last data pulse;
-
-initial 
-	begin
-// clear internal registers and the output signal
-	  t_state = 0;
-	  in_sep = 0;
-	  sep_clr = 0;
-	  out = 0;
-	  nout = 0;
-	end
-
-
-always @(posedge in)
-	begin
-	  out <= #delay (in_sep > 0) ? 1'bx : t_state;
-	  out <= #(delay+2) 0;
-	  nout <= #delay (in_sep > 0) ? 1'bx : ~t_state;
-	  nout <= #(delay+2) 0;
-
-	  if (in_sep == 0)
-	    t_state <= t_state ^ in;
-	  else
-	    begin
-	      t_state = 1'bx;
-
-	    // generating a warning
-	      $fwrite(warning_file, 
-	       "Violation of separation time in module %m.\n");
-	      $fwrite(warning_file,
-	       "Input T pulses at %0d and at %0d.\n", last_t_time, 
-	       $stime);
-	    end
-	  last_t_time <= $stime;
-
-	  in_sep <= in_sep + 1;
-	  sep_clr <= #(t_separation-1) 1;
-	end
-
-always @(posedge sep_clr)
-	begin
-	  in_sep <= in_sep - 1;
-	  sep_clr <= 0;
-	end
-
-
-endmodule
-
-
-  'module', 'tff', '(', 'in', 'out', 'nout', ')', ';',
-     'input', 'in', ';',
-      'output', 'out', 'nout', ';',
-      'reg', 'out', 'nout', ';',
-       'parameter',
-        't_separation', '=', '10',
-        'delay', '=', '15',
-        'warning_file', '=', '3',
-        ';',
-      'reg', 't_state', 'sep_clr', ';',
-      'integer', 'last_t_time', 'in_sep', ';',
-       'initial',
-         'begin',
-           't_state', '=', '0', ';',
-            'in_sep', '=', '0', ';',
-            'sep_clr', '=', '0', ';',
-            'out', '=', '0', ';',
-            'nout', '=', '0', ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'in', ')',
-         'begin',
-             'out',
-                '<=',
-                '#', 'delay',
-                '(',
-                'in_sep', '>', '0',
-                ')',
-                '?',
-                "1 'b x",
-                ':',
-                't_state',
-              ';',
-            'out', '<=', '#', '(', 'delay', '+', '2', ')', '0', ';',
-              'nout',
-                '<=',
-                '#', 'delay',
-                '(',
-                'in_sep', '>', '0',
-                ')',
-                '?',
-                "1 'b x",
-                ':',
-                '~',
-                't_state',
-              ';',
-             'nout', '<=', '#', '(', 'delay', '+', '2', ')', '0',
-              ';',
-             'if',
-              '(', 'in_sep', '==', '0', ')',
-              't_state', '<=', 't_state', '^', 'in', ';',
-              'else',
-               'begin',
-                 't_state', '=', "1 'b x", ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Violation of separation time in module %m.\\n"',
-                    ')',
-                    ';',
-                   '$fwrite',
-                    '(',
-                    'warning_file',
-                    '"Input T pulses at %0d and at %0d.\\n"',
-                    'last_t_time',
-                    '$stime',
-                    ')',
-                    ';',
-                'end',
-            'last_t_time', '<=', '$stime', ';',
-            'in_sep', '<=', 'in_sep', '+', '1', ';',
-              'sep_clr',
-                '<=',
-                '#', '(', 't_separation', '-', '1', ')',
-                '1',
-              ';',
-          'end',
-       'always',
-        '@', '(', 'posedge', 'sep_clr', ')',
-         'begin',
-           'in_sep', '<=', 'in_sep', '-', '1', ';',
-            'sep_clr', '<=', '0', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/timescale_info_test.v.parsed.txt Deleted

@@ -1,74 +0,0 @@
-/**********************************************************************
- * $timescale_info example -- Verilog test bench source code
- *
- * Verilog test bench to test the $timescale_info PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-  reg  a, b, ci, clk;
-  wire sum, co;
-
-  addbit i1 (a, b, ci, sum, co);
-
-  initial
-    begin
-      $timeformat(-6,1," ms",10);
-      #1 $timescale_info(i1);
-      #1 $finish;
-    end
-endmodule
-
-/*** A gate level 1 bit adder model ***/
-`timescale 1ns / 1ps
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci, sum, co,
-        n1, n2, n3;
-
-  xor    (n1, a, b);
-  xor #2 (sum, n1, ci);
-  and    (n2, a, b);
-  and    (n3, n1, ci);
-  or  #2 (co, n2, n3);
-
-endmodule
-/*********************************************************************/
-
-
-
-  'module', 'test', ';',
-     'reg', 'a', 'b', 'ci', 'clk', ';',
-      'wire', 'sum', 'co', ';',
-       'addbit',
-        'i1', '(', 'a', 'b', 'ci', 'sum', 'co', ')',
-        ';',
-       'initial',
-         'begin',
-           '$timeformat', '(', '-', '6', '1', '" ms"', '10', ')', ';',
-            '#', '1', '$timescale_info', '(', 'i1', ')', ';',
-            '#', '1', '$finish', ';',
-          'end',
-    'endmodule',
-    'module',
-      'addbit',
-      '(',
-      'a', 'b', 'ci', 'sum', 'co',
-      ')',
-      ';',
-     'input', 'a', 'b', 'ci', ';',
-      'output', 'sum', 'co', ';',
-      'wire', 'a', 'b', 'ci', 'sum', 'co', 'n1', 'n2', 'n3', ';',
-      'xor', '(', 'n1', 'a', 'b', ')', ';',
-      'xor', '#', '2', '(', 'sum', 'n1', 'ci', ')', ';',
-      'and', '(', 'n2', 'a', 'b', ')', ';',
-      'and', '(', 'n3', 'n1', 'ci', ')', ';',
-      'or', '#', '2', '(', 'co', 'n2', 'n3', ')', ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/usb.v.parsed.txt Deleted

@@ -1,746 +0,0 @@
-// Generated by vstruct v2.2.1
-
-`include "usb_defines.v"
-
-module usb (
-    // WISHBONE Interface
-    clk_i,
-    addr_i,
-    data_i,
-    data_o,
-    ack_o,
-    we_i,
-    stb_i,
-    cyc_i,
-    inta_o,
-    intb_o,
-    dma_req,
-    dma_ack,
-    rst_i,
-    resume_req_i,
-
-    // UTMI Interface
-    phy_clk,
-    DataOut,
-    TxReady,
-    RxValid,
-    RxActive,
-    RxError,
-    DataIn,
-    XcvSelect,
-    TermSel,
-    SuspendM,
-    LineState,
-    OpMode,
-    usb_vbus,
-    VStatus,                           // UTMI Vendor C/S bus
-    VControl,
-    VControl_Load,
-    TxValid,
-    phy_rst
-    );
-
-    // WISHBONE Interface
-    input           clk_i;
-    input    17:0 addr_i;
-    input    31:0 data_i;
-    output   31:0 data_o;
-    output          ack_o;
-    input           we_i;
-    input           stb_i;
-    input           cyc_i;
-    output          inta_o;
-    output          intb_o;
-    output   14:0 dma_req;
-    input    14:0 dma_ack;
-    input           rst_i;
-    input           resume_req_i;
-
-    // UTMI Interface
-    input           phy_clk;
-    output   7:0  DataOut;
-    input           TxReady;
-    input           RxValid;
-    input           RxActive;
-    input           RxError;
-    input    7:0  DataIn;
-    output          XcvSelect;
-    output          TermSel;
-    output          SuspendM;
-    input    1:0  LineState;
-    output   1:0  OpMode;
-    input           usb_vbus;
-    input    7:0  VStatus;           // UTMI Vendor C/S bus
-    output   3:0  VControl;
-    output          VControl_Load;
-    output          TxValid;
-    output          phy_rst;
-
-    ////////////////////////////////////////////////////////////////////////////
-    // wishbone_if                                                            //
-    ////////////////////////////////////////////////////////////////////////////
-    wire     14:0 wadr;
-    wire     31:0 wb2ma_d;
-    wire            wwe;
-    wire            wreq;
-    wire            re;
-    wire            we;
-    wire     31:0 wb2rf_d;
-
-    ////////////////////////////////////////////////////////////////////////////
-    // usb_trans_mac_if                                                       //
-    ////////////////////////////////////////////////////////////////////////////
-    wire            rst;
-    wire            tx_valid_out;
-    wire     7:0  rx_data;
-    wire            rx_valid;
-    wire            rx_active;
-    wire            rx_err;
-    wire            tx_ready;
-    wire            mode_hs;           // High Speed Mode
-    wire            usb_reset;         // USB Reset
-    wire            usb_suspend;       // USB Suspend
-    wire            usb_attached;      // Attached to USB
-    wire            resume_req;
-
-    ////////////////////////////////////////////////////////////////////////////
-    // protocol_layer                                                         //
-    ////////////////////////////////////////////////////////////////////////////
-    wire     7:0  tx_data;
-    wire            tx_valid;
-    wire            tx_valid_last;
-    wire            tx_first;
-    wire     14:0 madr;              // word address
-    wire     31:0 mdout;
-    wire            mwe;
-    wire            mreq;
-    wire     31:0 idin;              // Data Input
-    wire     3:0  ep_sel;            // Endpoint Number Input
-    wire            buf0_rl;           // Reload Buf 0 with original values
-    wire            buf0_set;          // Write to buf 0
-    wire            buf1_set;          // Write to buf 1
-    wire            uc_bsel_set;       // Write to the uc_bsel field
-    wire            uc_dpd_set;        // Write to the uc_dpd field
-    wire            int_buf1_set;      // Set buf1 full/empty interrupt
-    wire            int_buf0_set;      // Set buf0 full/empty interrupt
-    wire            int_upid_set;      // Set unsupported PID interrupt
-    wire            int_crc16_set;     // Set CRC16 error interrupt
-    wire            int_to_set;        // Set time out interrupt
-    wire            int_seqerr_set;    // Set PID sequence error interrupt
-    wire     31:0 frm_nat;
-    wire            pid_cs_err;        // pid checksum error
-    wire            nse_err;           // no such endpoint error
-    wire            crc5_err;          // crc5 error
-
-    ////////////////////////////////////////////////////////////////////////////
-    // memory_arbiter                                                         //
-    ////////////////////////////////////////////////////////////////////////////
-    wire     14:0 radr;
-    wire     31:0 arb2mem;
-    wire            rre;
-    wire            rwe;
-    wire     31:0 mdin;
-    wire            mack;
-    wire     31:0 ma2wb_d;
-    wire            wack;
-
-    ////////////////////////////////////////////////////////////////////////////
-    // buff_mem                                                               //
-    ////////////////////////////////////////////////////////////////////////////
-    wire     31:0 mem2arb;
-
-    ////////////////////////////////////////////////////////////////////////////
-    // reg_file                                                               //
-    ////////////////////////////////////////////////////////////////////////////
-    wire     31:0 rf2wb_d;
-    wire            match;             // Endpoint Matched
-    wire     31:0 csr;               // Internal CSR Output
-    wire     31:0 buf0;              // Internal Buf 0 Output
-    wire     31:0 buf1;              // Internal Buf 1 Output
-    wire     6:0  funct_adr;         // Function Address
-    wire            dma_in_buf_sz1;
-    wire            dma_out_buf_avail;
-    wire            rf_resume_req;
-
-    ///////////////////////////////////////////////////////////////////
-    //
-    // Misc Logic
-    //
-    assign TxValid = tx_valid_out;
-    assign rst = rst_i;
-    assign phy_rst = ~rst;
-    assign resume_req = resume_req_i | rf_resume_req;
-
-    wb wishbone_if (
-            // WISHBONE Interface
-            .clk               (clk_i),
-            .rst               (rst),
-            .addr_i            (addr_i),
-            .data_i            (data_i),
-            .data_o            (data_o),
-            .ack_o             (ack_o),
-            .we_i              (we_i),
-            .stb_i             (stb_i),
-            .cyc_i             (cyc_i),
-
-            // UTMI Interface
-            .phy_clk           (phy_clk),
-
-            // Memory Arbiter Interface
-            .wadr              (wadr),
-            .wdout             (wb2ma_d),
-            .wdin              (ma2wb_d),
-            .wwe               (wwe),
-            .wreq              (wreq),
-            .wack              (wack),
-
-            // Register File interface
-            .re                (re),
-            .we                (we),
-            .din               (rf2wb_d),
-            .dout              (wb2rf_d)
-        ); // wishbone_if
-
-    utmi_if usb_trans_mac_if (
-            // UTMI Interface (EXTERNAL)
-            .phy_clk           (phy_clk),
-            .rst               (rst),
-            .DataOut           (DataOut),
-            .TxValid           (tx_valid_out),
-            .TxReady           (TxReady),
-            .RxValid           (RxValid),
-            .RxActive          (RxActive),
-            .RxError           (RxError),
-            .DataIn            (DataIn),
-            .XcvSelect         (XcvSelect),
-            .TermSel           (TermSel),
-            .SuspendM          (SuspendM),
-            .LineState         (LineState),
-            .OpMode            (OpMode),
-            .usb_vbus          (usb_vbus),
-
-            // Internal Interface
-            .rx_data           (rx_data),
-            .rx_valid          (rx_valid),
-            .rx_active         (rx_active),
-            .rx_err            (rx_err),
-            .tx_data           (tx_data),
-            .tx_valid          (tx_valid),
-            .tx_valid_last     (tx_valid_last),
-            .tx_ready          (tx_ready),
-            .tx_first          (tx_first),
-
-            // Misc Interfaces
-            .mode_hs           (mode_hs),           // High Speed Mode
-            .usb_reset         (usb_reset),         // USB Reset
-            .usb_suspend       (usb_suspend),       // USB Suspend
-            .usb_attached      (usb_attached),      // Attached to USB
-            .resume_req        (resume_req)
-        ); // usb_trans_mac_if
-
-    pl protocol_layer (
-            // UTMI Interface
-            .clk               (phy_clk),
-            .rst               (rst),
-
-            // UTMI Interface
-            .rx_data           (rx_data),
-            .rx_valid          (rx_valid),
-            .rx_active         (rx_active),
-            .rx_err            (rx_err),
-            .tx_data           (tx_data),
-            .tx_valid          (tx_valid),
-            .tx_valid_last     (tx_valid_last),
-            .tx_ready          (tx_ready),
-            .tx_first          (tx_first),
-            .tx_valid_out      (tx_valid_out),
-            .mode_hs           (mode_hs),           // High Speed Mode
-            .usb_reset         (usb_reset),         // USB Reset
-            .usb_suspend       (usb_suspend),       // USB Suspend
-            .usb_attached      (usb_attached),      // Attached to USB
-
-            // memory interface
-            .madr              (madr),              // word address
-            .mdout             (mdout),
-            .mdin              (mdin),
-            .mwe               (mwe),
-            .mreq              (mreq),
-            .mack              (mack),
-
-            // Register File Interface
-            .fa                (funct_adr),         // Function Address (as set by the controller)
-            .idin              (idin),              // Data Input
-            .ep_sel            (ep_sel),            // Endpoint Number Input
-            .match             (match),             // Endpoint Matched
-            .dma_in_buf_sz1    (dma_in_buf_sz1),
-            .dma_out_buf_avail (dma_out_buf_avail),
-
-            .buf0_rl           (buf0_rl),           // Reload Buf 0 with original values
-            .buf0_set          (buf0_set),          // Write to buf 0
-            .buf1_set          (buf1_set),          // Write to buf 1
-            .uc_bsel_set       (uc_bsel_set),       // Write to the uc_bsel field
-            .uc_dpd_set        (uc_dpd_set),        // Write to the uc_dpd field
-
-            .int_buf1_set      (int_buf1_set),      // Set buf1 full/empty interrupt
-            .int_buf0_set      (int_buf0_set),      // Set buf0 full/empty interrupt
-            .int_upid_set      (int_upid_set),      // Set unsupported PID interrupt
-            .int_crc16_set     (int_crc16_set),     // Set CRC16 error interrupt
-            .int_to_set        (int_to_set),        // Set time out interrupt
-            .int_seqerr_set    (int_seqerr_set),    // Set PID sequence error interrupt
-
-            .csr               (csr),               // Internal CSR Output
-            .buf0              (buf0),              // Internal Buf 0 Output
-            .buf1              (buf1),              // Internal Buf 1 Output
-
-            // Misc
-            .frm_nat           (frm_nat),
-
-            // Misc
-            .pid_cs_err        (pid_cs_err),        // pid checksum error
-            .nse_err           (nse_err),           // no such endpoint error
-            .crc5_err          (crc5_err)           // crc5 error
-
-        ); // protocol_layer
-
-    mem_arb memory_arbiter (
-            .phy_clk           (phy_clk),
-            .wclk              (clk_i),
-            .rst               (rst),
-
-            // SSRAM Interface
-            .radr              (radr),
-            .rdin              (mem2arb),
-            .rdout             (arb2mem),
-            .rre               (rre),
-            .rwe               (rwe),
-
-            // IDMA Memory Interface
-            .madr              (madr),
-            .mdout             (mdin),
-            .mdin              (mdout),
-            .mwe               (mwe),
-            .mreq              (mreq),
-            .mack              (mack),
-
-            // WISHBONE Memory Interface
-            .wadr              (wadr),
-            .wdout             (ma2wb_d),
-            .wdin              (wb2ma_d),
-            .wwe               (wwe),
-            .wreq              (wreq),
-            .wack              (wack)
-
-        ); // memory_arbiter
-
-    ssram buff_mem (
-            .clk               (phy_clk),
-            .rst               (rst),
-            .radr              (radr),
-            .rdin              (arb2mem),
-            .rdout             (mem2arb),
-            .rre               (rre),
-            .rwe               (rwe)
-        ); // buff_mem
-
-    rf reg_file (
-            .clk               (phy_clk),
-            .wclk              (clk_i),
-            .rst               (rst),
-
-            // Wishbone Interface
-            .adr               (wadr6:0),
-            .re                (re),
-            .we                (we),
-            .din               (wb2rf_d),
-            .dout              (rf2wb_d),
-            .inta              (inta_o),
-            .intb              (intb_o),
-            .dma_req           (dma_req),
-            .dma_ack           (dma_ack),
-
-            // Internal Interface
-            .idin              (idin),              // Data Input
-            .ep_sel            (ep_sel),            // Endpoint Number Input
-            .match             (match),             // Endpoint Matched
-            .buf0_rl           (buf0_rl),           // Reload Buf 0 with original values
-
-            .buf0_set          (buf0_set),          // Write to buf 0
-            .buf1_set          (buf1_set),          // Write to buf 1
-            .uc_bsel_set       (uc_bsel_set),       // Write to the uc_bsel field
-            .uc_dpd_set        (uc_dpd_set),        // Write to the uc_dpd field
-
-            .int_buf1_set      (int_buf1_set),      // Set buf1 full/empty interrupt
-            .int_buf0_set      (int_buf0_set),      // Set buf0 full/empty interrupt
-            .int_upid_set      (int_upid_set),      // Set unsupported PID interrupt
-            .int_crc16_set     (int_crc16_set),     // Set CRC16 error interrupt
-            .int_to_set        (int_to_set),        // Set time out interrupt
-            .int_seqerr_set    (int_seqerr_set),    // Set PID Sequence Error Interrupt
-
-            .csr               (csr),               // Internal CSR Output
-            .buf0              (buf0),              // Internal Buf 0 Output
-            .buf1              (buf1),              // Internal Buf 1 Output
-            .funct_adr         (funct_adr),         // Function Address
-            .dma_in_buf_sz1    (dma_in_buf_sz1),
-            .dma_out_buf_avail (dma_out_buf_avail),
-
-            // Misc
-            .frm_nat           (frm_nat),
-
-            // UTMI Interface
-            .utmi_vend_stat    (VStatus),           // UTMI Vendor C/S bus
-            .utmi_vend_ctrl    (VControl),
-            .utmi_vend_wr      (VControl_Load),
-
-            .line_stat         (LineState),         // Below are signals for interrupt generation
-            .usb_attached      (usb_attached),
-            .mode_hs           (mode_hs),
-            .suspend           (usb_suspend),
-            .attached          (usb_attached),
-            .usb_reset         (usb_reset),
-            .pid_cs_err        (pid_cs_err),
-            .nse_err           (nse_err),
-            .crc5_err          (crc5_err),
-            .rx_err            (rx_err),
-            .rf_resume_req     (rf_resume_req)
-        ); // reg_file
-endmodule
-
-
-
-   'module',
-      'usb',
-      '(',
-       'clk_i',
-        'addr_i',
-        'data_i',
-        'data_o',
-        'ack_o',
-        'we_i',
-        'stb_i',
-        'cyc_i',
-        'inta_o',
-        'intb_o',
-        'dma_req',
-        'dma_ack',
-        'rst_i',
-        'resume_req_i',
-        'phy_clk',
-        'DataOut',
-        'TxReady',
-        'RxValid',
-        'RxActive',
-        'RxError',
-        'DataIn',
-        'XcvSelect',
-        'TermSel',
-        'SuspendM',
-        'LineState',
-        'OpMode',
-        'usb_vbus',
-        'VStatus',
-        'VControl',
-        'VControl_Load',
-        'TxValid',
-        'phy_rst',
-      ')',
-      ';',
-     'input', 'clk_i', ';',
-      'input', '', '17', ':', '0', '', 'addr_i', ';',
-      'input', '', '31', ':', '0', '', 'data_i', ';',
-      'output', '', '31', ':', '0', '', 'data_o', ';',
-      'output', 'ack_o', ';',
-      'input', 'we_i', ';',
-      'input', 'stb_i', ';',
-      'input', 'cyc_i', ';',
-      'output', 'inta_o', ';',
-      'output', 'intb_o', ';',
-      'output', '', '14', ':', '0', '', 'dma_req', ';',
-      'input', '', '14', ':', '0', '', 'dma_ack', ';',
-      'input', 'rst_i', ';',
-      'input', 'resume_req_i', ';',
-      'input', 'phy_clk', ';',
-      'output', '', '7', ':', '0', '', 'DataOut', ';',
-      'input', 'TxReady', ';',
-      'input', 'RxValid', ';',
-      'input', 'RxActive', ';',
-      'input', 'RxError', ';',
-      'input', '', '7', ':', '0', '', 'DataIn', ';',
-      'output', 'XcvSelect', ';',
-      'output', 'TermSel', ';',
-      'output', 'SuspendM', ';',
-      'input', '', '1', ':', '0', '', 'LineState', ';',
-      'output', '', '1', ':', '0', '', 'OpMode', ';',
-      'input', 'usb_vbus', ';',
-      'input', '', '7', ':', '0', '', 'VStatus', ';',
-      'output', '', '3', ':', '0', '', 'VControl', ';',
-      'output', 'VControl_Load', ';',
-      'output', 'TxValid', ';',
-      'output', 'phy_rst', ';',
-      'wire', '', '14', ':', '0', '', 'wadr', ';',
-      'wire', '', '31', ':', '0', '', 'wb2ma_d', ';',
-      'wire', 'wwe', ';',
-      'wire', 'wreq', ';',
-      'wire', 're', ';',
-      'wire', 'we', ';',
-      'wire', '', '31', ':', '0', '', 'wb2rf_d', ';',
-      'wire', 'rst', ';',
-      'wire', 'tx_valid_out', ';',
-      'wire', '', '7', ':', '0', '', 'rx_data', ';',
-      'wire', 'rx_valid', ';',
-      'wire', 'rx_active', ';',
-      'wire', 'rx_err', ';',
-      'wire', 'tx_ready', ';',
-      'wire', 'mode_hs', ';',
-      'wire', 'usb_reset', ';',
-      'wire', 'usb_suspend', ';',
-      'wire', 'usb_attached', ';',
-      'wire', 'resume_req', ';',
-      'wire', '', '7', ':', '0', '', 'tx_data', ';',
-      'wire', 'tx_valid', ';',
-      'wire', 'tx_valid_last', ';',
-      'wire', 'tx_first', ';',
-      'wire', '', '14', ':', '0', '', 'madr', ';',
-      'wire', '', '31', ':', '0', '', 'mdout', ';',
-      'wire', 'mwe', ';',
-      'wire', 'mreq', ';',
-      'wire', '', '31', ':', '0', '', 'idin', ';',
-      'wire', '', '3', ':', '0', '', 'ep_sel', ';',
-      'wire', 'buf0_rl', ';',
-      'wire', 'buf0_set', ';',
-      'wire', 'buf1_set', ';',
-      'wire', 'uc_bsel_set', ';',
-      'wire', 'uc_dpd_set', ';',
-      'wire', 'int_buf1_set', ';',
-      'wire', 'int_buf0_set', ';',
-      'wire', 'int_upid_set', ';',
-      'wire', 'int_crc16_set', ';',
-      'wire', 'int_to_set', ';',
-      'wire', 'int_seqerr_set', ';',
-      'wire', '', '31', ':', '0', '', 'frm_nat', ';',
-      'wire', 'pid_cs_err', ';',
-      'wire', 'nse_err', ';',
-      'wire', 'crc5_err', ';',
-      'wire', '', '14', ':', '0', '', 'radr', ';',
-      'wire', '', '31', ':', '0', '', 'arb2mem', ';',
-      'wire', 'rre', ';',
-      'wire', 'rwe', ';',
-      'wire', '', '31', ':', '0', '', 'mdin', ';',
-      'wire', 'mack', ';',
-      'wire', '', '31', ':', '0', '', 'ma2wb_d', ';',
-      'wire', 'wack', ';',
-      'wire', '', '31', ':', '0', '', 'mem2arb', ';',
-      'wire', '', '31', ':', '0', '', 'rf2wb_d', ';',
-      'wire', 'match', ';',
-      'wire', '', '31', ':', '0', '', 'csr', ';',
-      'wire', '', '31', ':', '0', '', 'buf0', ';',
-      'wire', '', '31', ':', '0', '', 'buf1', ';',
-      'wire', '', '6', ':', '0', '', 'funct_adr', ';',
-      'wire', 'dma_in_buf_sz1', ';',
-      'wire', 'dma_out_buf_avail', ';',
-      'wire', 'rf_resume_req', ';',
-      'assign', 'TxValid', '=', 'tx_valid_out', ';',
-      'assign', 'rst', '=', 'rst_i', ';',
-      'assign', 'phy_rst', '=', '~', 'rst', ';',
-       'assign',
-        'resume_req', '=', 'resume_req_i', '|', 'rf_resume_req',
-        ';',
-       'wb',
-         'wishbone_if',
-           '(',
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-            '.', 'addr_i', '(', 'addr_i', ')',
-            '.', 'data_i', '(', 'data_i', ')',
-            '.', 'data_o', '(', 'data_o', ')',
-            '.', 'ack_o', '(', 'ack_o', ')',
-            '.', 'we_i', '(', 'we_i', ')',
-            '.', 'stb_i', '(', 'stb_i', ')',
-            '.', 'cyc_i', '(', 'cyc_i', ')',
-            '.', 'phy_clk', '(', 'phy_clk', ')',
-            '.', 'wadr', '(', 'wadr', ')',
-            '.', 'wdout', '(', 'wb2ma_d', ')',
-            '.', 'wdin', '(', 'ma2wb_d', ')',
-            '.', 'wwe', '(', 'wwe', ')',
-            '.', 'wreq', '(', 'wreq', ')',
-            '.', 'wack', '(', 'wack', ')',
-            '.', 're', '(', 're', ')',
-            '.', 'we', '(', 'we', ')',
-            '.', 'din', '(', 'rf2wb_d', ')',
-            '.', 'dout', '(', 'wb2rf_d', ')',
-            ')',
-        ';',
-       'utmi_if',
-         'usb_trans_mac_if',
-           '(',
-            '.', 'phy_clk', '(', 'phy_clk', ')',
-            '.', 'rst', '(', 'rst', ')',
-            '.', 'DataOut', '(', 'DataOut', ')',
-            '.', 'TxValid', '(', 'tx_valid_out', ')',
-            '.', 'TxReady', '(', 'TxReady', ')',
-            '.', 'RxValid', '(', 'RxValid', ')',
-            '.', 'RxActive', '(', 'RxActive', ')',
-            '.', 'RxError', '(', 'RxError', ')',
-            '.', 'DataIn', '(', 'DataIn', ')',
-            '.', 'XcvSelect', '(', 'XcvSelect', ')',
-            '.', 'TermSel', '(', 'TermSel', ')',
-            '.', 'SuspendM', '(', 'SuspendM', ')',
-            '.', 'LineState', '(', 'LineState', ')',
-            '.', 'OpMode', '(', 'OpMode', ')',
-            '.', 'usb_vbus', '(', 'usb_vbus', ')',
-            '.', 'rx_data', '(', 'rx_data', ')',
-            '.', 'rx_valid', '(', 'rx_valid', ')',
-            '.', 'rx_active', '(', 'rx_active', ')',
-            '.', 'rx_err', '(', 'rx_err', ')',
-            '.', 'tx_data', '(', 'tx_data', ')',
-            '.', 'tx_valid', '(', 'tx_valid', ')',
-            '.', 'tx_valid_last', '(', 'tx_valid_last', ')',
-            '.', 'tx_ready', '(', 'tx_ready', ')',
-            '.', 'tx_first', '(', 'tx_first', ')',
-            '.', 'mode_hs', '(', 'mode_hs', ')',
-            '.', 'usb_reset', '(', 'usb_reset', ')',
-            '.', 'usb_suspend', '(', 'usb_suspend', ')',
-            '.', 'usb_attached', '(', 'usb_attached', ')',
-            '.', 'resume_req', '(', 'resume_req', ')',
-            ')',
-        ';',
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-            '.', 'rx_active', '(', 'rx_active', ')',
-            '.', 'rx_err', '(', 'rx_err', ')',
-            '.', 'tx_data', '(', 'tx_data', ')',
-            '.', 'tx_valid', '(', 'tx_valid', ')',
-            '.', 'tx_valid_last', '(', 'tx_valid_last', ')',
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-            '.', 'tx_first', '(', 'tx_first', ')',
-            '.', 'tx_valid_out', '(', 'tx_valid_out', ')',
-            '.', 'mode_hs', '(', 'mode_hs', ')',
-            '.', 'usb_reset', '(', 'usb_reset', ')',
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-            '.', 'usb_attached', '(', 'usb_attached', ')',
-            '.', 'madr', '(', 'madr', ')',
-            '.', 'mdout', '(', 'mdout', ')',
-            '.', 'mdin', '(', 'mdin', ')',
-            '.', 'mwe', '(', 'mwe', ')',
-            '.', 'mreq', '(', 'mreq', ')',
-            '.', 'mack', '(', 'mack', ')',
-            '.', 'fa', '(', 'funct_adr', ')',
-            '.', 'idin', '(', 'idin', ')',
-            '.', 'ep_sel', '(', 'ep_sel', ')',
-            '.', 'match', '(', 'match', ')',
-            '.', 'dma_in_buf_sz1', '(', 'dma_in_buf_sz1', ')',
-            '.', 'dma_out_buf_avail', '(', 'dma_out_buf_avail', ')',
-            '.', 'buf0_rl', '(', 'buf0_rl', ')',
-            '.', 'buf0_set', '(', 'buf0_set', ')',
-            '.', 'buf1_set', '(', 'buf1_set', ')',
-            '.', 'uc_bsel_set', '(', 'uc_bsel_set', ')',
-            '.', 'uc_dpd_set', '(', 'uc_dpd_set', ')',
-            '.', 'int_buf1_set', '(', 'int_buf1_set', ')',
-            '.', 'int_buf0_set', '(', 'int_buf0_set', ')',
-            '.', 'int_upid_set', '(', 'int_upid_set', ')',
-            '.', 'int_crc16_set', '(', 'int_crc16_set', ')',
-            '.', 'int_to_set', '(', 'int_to_set', ')',
-            '.', 'int_seqerr_set', '(', 'int_seqerr_set', ')',
-            '.', 'csr', '(', 'csr', ')',
-            '.', 'buf0', '(', 'buf0', ')',
-            '.', 'buf1', '(', 'buf1', ')',
-            '.', 'frm_nat', '(', 'frm_nat', ')',
-            '.', 'pid_cs_err', '(', 'pid_cs_err', ')',
-            '.', 'nse_err', '(', 'nse_err', ')',
-            '.', 'crc5_err', '(', 'crc5_err', ')',
-            ')',
-        ';',
-       'mem_arb',
-         'memory_arbiter',
-           '(',
-            '.', 'phy_clk', '(', 'phy_clk', ')',
-            '.', 'wclk', '(', 'clk_i', ')',
-            '.', 'rst', '(', 'rst', ')',
-            '.', 'radr', '(', 'radr', ')',
-            '.', 'rdin', '(', 'mem2arb', ')',
-            '.', 'rdout', '(', 'arb2mem', ')',
-            '.', 'rre', '(', 'rre', ')',
-            '.', 'rwe', '(', 'rwe', ')',
-            '.', 'madr', '(', 'madr', ')',
-            '.', 'mdout', '(', 'mdin', ')',
-            '.', 'mdin', '(', 'mdout', ')',
-            '.', 'mwe', '(', 'mwe', ')',
-            '.', 'mreq', '(', 'mreq', ')',
-            '.', 'mack', '(', 'mack', ')',
-            '.', 'wadr', '(', 'wadr', ')',
-            '.', 'wdout', '(', 'ma2wb_d', ')',
-            '.', 'wdin', '(', 'wb2ma_d', ')',
-            '.', 'wwe', '(', 'wwe', ')',
-            '.', 'wreq', '(', 'wreq', ')',
-            '.', 'wack', '(', 'wack', ')',
-            ')',
-        ';',
-       'ssram',
-         'buff_mem',
-           '(',
-            '.', 'clk', '(', 'phy_clk', ')',
-            '.', 'rst', '(', 'rst', ')',
-            '.', 'radr', '(', 'radr', ')',
-            '.', 'rdin', '(', 'arb2mem', ')',
-            '.', 'rdout', '(', 'mem2arb', ')',
-            '.', 'rre', '(', 'rre', ')',
-            '.', 'rwe', '(', 'rwe', ')',
-            ')',
-        ';',
-       'rf',
-         'reg_file',
-           '(',
-            '.', 'clk', '(', 'phy_clk', ')',
-            '.', 'wclk', '(', 'clk_i', ')',
-            '.', 'rst', '(', 'rst', ')',
-            '.', 'adr', '(', 'wadr', '', '6', '0', '', ')',
-            '.', 're', '(', 're', ')',
-            '.', 'we', '(', 'we', ')',
-            '.', 'din', '(', 'wb2rf_d', ')',
-            '.', 'dout', '(', 'rf2wb_d', ')',
-            '.', 'inta', '(', 'inta_o', ')',
-            '.', 'intb', '(', 'intb_o', ')',
-            '.', 'dma_req', '(', 'dma_req', ')',
-            '.', 'dma_ack', '(', 'dma_ack', ')',
-            '.', 'idin', '(', 'idin', ')',
-            '.', 'ep_sel', '(', 'ep_sel', ')',
-            '.', 'match', '(', 'match', ')',
-            '.', 'buf0_rl', '(', 'buf0_rl', ')',
-            '.', 'buf0_set', '(', 'buf0_set', ')',
-            '.', 'buf1_set', '(', 'buf1_set', ')',
-            '.', 'uc_bsel_set', '(', 'uc_bsel_set', ')',
-            '.', 'uc_dpd_set', '(', 'uc_dpd_set', ')',
-            '.', 'int_buf1_set', '(', 'int_buf1_set', ')',
-            '.', 'int_buf0_set', '(', 'int_buf0_set', ')',
-            '.', 'int_upid_set', '(', 'int_upid_set', ')',
-            '.', 'int_crc16_set', '(', 'int_crc16_set', ')',
-            '.', 'int_to_set', '(', 'int_to_set', ')',
-            '.', 'int_seqerr_set', '(', 'int_seqerr_set', ')',
-            '.', 'csr', '(', 'csr', ')',
-            '.', 'buf0', '(', 'buf0', ')',
-            '.', 'buf1', '(', 'buf1', ')',
-            '.', 'funct_adr', '(', 'funct_adr', ')',
-            '.', 'dma_in_buf_sz1', '(', 'dma_in_buf_sz1', ')',
-            '.', 'dma_out_buf_avail', '(', 'dma_out_buf_avail', ')',
-            '.', 'frm_nat', '(', 'frm_nat', ')',
-            '.', 'utmi_vend_stat', '(', 'VStatus', ')',
-            '.', 'utmi_vend_ctrl', '(', 'VControl', ')',
-            '.', 'utmi_vend_wr', '(', 'VControl_Load', ')',
-            '.', 'line_stat', '(', 'LineState', ')',
-            '.', 'usb_attached', '(', 'usb_attached', ')',
-            '.', 'mode_hs', '(', 'mode_hs', ')',
-            '.', 'suspend', '(', 'usb_suspend', ')',
-            '.', 'attached', '(', 'usb_attached', ')',
-            '.', 'usb_reset', '(', 'usb_reset', ')',
-            '.', 'pid_cs_err', '(', 'pid_cs_err', ')',
-            '.', 'nse_err', '(', 'nse_err', ')',
-            '.', 'crc5_err', '(', 'crc5_err', ')',
-            '.', 'rx_err', '(', 'rx_err', ')',
-            '.', 'rf_resume_req', '(', 'rf_resume_req', ')',
-            ')',
-        ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/use_workarea_test.v.parsed.txt Deleted

@@ -1,43 +0,0 @@
-/**********************************************************************
- * $test_vpiworkarea example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $test_vpiworkarea PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-
-  initial
-    begin
-      #1 repeat (2) $test_vpiworkarea(1);
-      #1 $test_vpiworkarea(2);
-      #1 $test_vpiworkarea(3);
-      #1 $test_vpiworkarea(4);
-      #1 $finish;
-    end
- 
-endmodule
-/*********************************************************************/
-
-
-
-  'module', 'test', ';',
-      'initial',
-         'begin',
-            '#', '1',
-               'repeat',
-                '(',
-                '2',
-                ')',
-                '$test_vpiworkarea', '(', '1', ')', ';',
-            '#', '1', '$test_vpiworkarea', '(', '2', ')', ';',
-            '#', '1', '$test_vpiworkarea', '(', '3', ')', ';',
-            '#', '1', '$test_vpiworkarea', '(', '4', ')', ';',
-            '#', '1', '$finish', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/utmi_if.v.parsed.txt Deleted

@@ -1,354 +0,0 @@
-/////////////////////////////////////////////////////////////////////
-////                                                             ////
-////  UTMI Interface                                             ////
-////                                                             ////
-////                                                             ////
-////  Author: Rudolf Usselmann                                   ////
-////          rudi@asics.ws                                      ////
-////                                                             ////
-////                                                             ////
-////  Downloaded from: http://www.opencores.org/cores/usb/       ////
-////                                                             ////
-/////////////////////////////////////////////////////////////////////
-////                                                             ////
-//// Copyright (C) 2000 Rudolf Usselmann                         ////
-////                    rudi@asics.ws                            ////
-////                                                             ////
-//// This source file may be used and distributed without        ////
-//// restriction provided that this copyright statement is not   ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer.////
-////                                                             ////
-////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
-//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
-//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
-//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
-//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
-//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
-//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
-//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
-//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
-//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
-//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
-//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
-//// POSSIBILITY OF SUCH DAMAGE.                                 ////
-////                                                             ////
-/////////////////////////////////////////////////////////////////////
-
-//  CVS Log
-//
-//  $Id: utmi_if.v,v 1.0 2001/03/07 09:17:12 rudi Exp $
-//
-//  $Date: 2001/03/07 09:17:12 $
-//  $Revision: 1.0 $
-//  $Author: rudi $
-//  $Locker:  $
-//  $State: Exp $
-//
-// Change History:
-//               $Log: utmi_if.v,v $
-//               Revision 1.0  2001/03/07 09:17:12  rudi
-//
-//
-//               Changed all revisions to revision 1.0. This is because OpenCores CVS
-//               interface could not handle the original '0.1' revision ....
-//
-//               Revision 0.2  2001/03/07 09:08:13  rudi
-//
-//               Added USB controll signaling (Line Status) block. Fixed some minor
-//               typos, added resume bit and signal.
-//
-//               Revision 0.1.0.1  2001/02/28 08:11:45  rudi
-//               Initial Release
-//
-//
-
-`include "usb_defines.v"
-
-module utmi_if( // UTMI Interface (EXTERNAL)
-        phy_clk, rst,
-        DataOut, TxValid, TxReady,
-        RxValid, RxActive, RxError, DataIn,
-        XcvSelect, TermSel, SuspendM, LineState,
-        OpMode, usb_vbus,
-
-        // Internal Interface
-        rx_data, rx_valid, rx_active, rx_err,
-        tx_data, tx_valid, tx_valid_last, tx_ready,
-        tx_first,
-
-        // Misc Interfaces
-        mode_hs, usb_reset, usb_suspend, usb_attached,
-        resume_req
-        );
-
-input       phy_clk;
-output      rst;
-output  7:0   DataOut;
-output      TxValid;
-input       TxReady;
-input   7:0   DataIn;
-input       RxValid;
-input       RxActive;
-input       RxError;
-output      XcvSelect;
-output      TermSel;
-output      SuspendM;
-input   1:0   LineState;
-output  1:0   OpMode;
-input       usb_vbus;
-
-output  7:0   rx_data;
-output      rx_valid, rx_active, rx_err;
-input   7:0   tx_data;
-input       tx_valid;
-input       tx_valid_last;
-output      tx_ready;
-input       tx_first;
-
-output      mode_hs;    // High Speed Mode
-output      usb_reset;  // USB Reset
-output      usb_suspend;    // USB Suspend
-output      usb_attached;   // Attached to USB
-input       resume_req;
-
-///////////////////////////////////////////////////////////////////
-//
-// Local Wires and Registers
-//
-reg 7:0   rx_data;
-reg     rx_valid, rx_active, rx_err;
-reg 7:0   DataOut;
-reg     tx_ready;
-reg     TxValid;
-wire        drive_k;
-
-///////////////////////////////////////////////////////////////////
-//
-// Misc Logic
-//
-
-
-///////////////////////////////////////////////////////////////////
-//
-// RX Interface Input registers
-//
-
-always @(posedge phy_clk)
-    if(!rst)    rx_valid <= #1 0;
-    else        rx_valid <= #1 RxValid;
-
-always @(posedge phy_clk)
-    if(!rst)    rx_active <= #1 0;
-    else        rx_active <= #1 RxActive;
-
-always @(posedge phy_clk)
-    if(!rst)    rx_err <= #1 0;
-    else        rx_err <= #1 RxError;
-
-always @(posedge phy_clk)
-        rx_data <= #1 DataIn;
-
-///////////////////////////////////////////////////////////////////
-//
-// TX Interface Output/Input registers
-//
-wire    tx_valid_sr;
-
-assign  tx_valid_sr = (!rst) ? 0 : tx_valid_last ? 1 : TxReady ? 0 : tx_valid_sr;
-
-always @(posedge phy_clk)
-    if(TxReady | tx_first)  DataOut <= #1 tx_data;
-    else
-    if(drive_k)     DataOut <= #1 8'hff;
-
-always @(posedge phy_clk)
-    tx_ready <= #1 TxReady;
-
-always @(posedge phy_clk)
-    TxValid <= #1 tx_valid | tx_valid_sr | drive_k;
-
-///////////////////////////////////////////////////////////////////
-//
-// Line Status Signaling & Speed Negotiation Block
-//
-
-utmi_ls u0(
-        .clk(       phy_clk     ),
-        .rst(       rst     ),
-        .resume_req(    resume_req  ),
-        .rx_active( rx_active   ),
-        .tx_ready(  tx_ready    ),
-        .drive_k(   drive_k     ),
-        .XcvSelect( XcvSelect   ),
-        .TermSel(   TermSel     ),
-        .SuspendM(  SuspendM    ),
-        .LineState( LineState   ),
-        .OpMode(    OpMode      ),
-        .usb_vbus(  usb_vbus    ),
-        .mode_hs(   mode_hs     ),
-        .usb_reset( usb_reset   ),
-        .usb_suspend(   usb_suspend ),
-        .usb_attached(  usb_attached    )
-        );
-
-endmodule
-
-
-
-   'module',
-      'utmi_if',
-      '(',
-       'phy_clk',
-        'rst',
-        'DataOut',
-        'TxValid',
-        'TxReady',
-        'RxValid',
-        'RxActive',
-        'RxError',
-        'DataIn',
-        'XcvSelect',
-        'TermSel',
-        'SuspendM',
-        'LineState',
-        'OpMode',
-        'usb_vbus',
-        'rx_data',
-        'rx_valid',
-        'rx_active',
-        'rx_err',
-        'tx_data',
-        'tx_valid',
-        'tx_valid_last',
-        'tx_ready',
-        'tx_first',
-        'mode_hs',
-        'usb_reset',
-        'usb_suspend',
-        'usb_attached',
-        'resume_req',
-      ')',
-      ';',
-     'input', 'phy_clk', ';',
-      'output', 'rst', ';',
-      'output', '', '7', ':', '0', '', 'DataOut', ';',
-      'output', 'TxValid', ';',
-      'input', 'TxReady', ';',
-      'input', '', '7', ':', '0', '', 'DataIn', ';',
-      'input', 'RxValid', ';',
-      'input', 'RxActive', ';',
-      'input', 'RxError', ';',
-      'output', 'XcvSelect', ';',
-      'output', 'TermSel', ';',
-      'output', 'SuspendM', ';',
-      'input', '', '1', ':', '0', '', 'LineState', ';',
-      'output', '', '1', ':', '0', '', 'OpMode', ';',
-      'input', 'usb_vbus', ';',
-      'output', '', '7', ':', '0', '', 'rx_data', ';',
-      'output', 'rx_valid', 'rx_active', 'rx_err', ';',
-      'input', '', '7', ':', '0', '', 'tx_data', ';',
-      'input', 'tx_valid', ';',
-      'input', 'tx_valid_last', ';',
-      'output', 'tx_ready', ';',
-      'input', 'tx_first', ';',
-      'output', 'mode_hs', ';',
-      'output', 'usb_reset', ';',
-      'output', 'usb_suspend', ';',
-      'output', 'usb_attached', ';',
-      'input', 'resume_req', ';',
-      'reg', '', '7', ':', '0', '', 'rx_data', ';',
-      'reg', 'rx_valid', 'rx_active', 'rx_err', ';',
-      'reg', '', '7', ':', '0', '', 'DataOut', ';',
-      'reg', 'tx_ready', ';',
-      'reg', 'TxValid', ';',
-      'wire', 'drive_k', ';',
-       'always',
-        '@', '(', 'posedge', 'phy_clk', ')',
-         'if',
-          '(', '!', 'rst', ')',
-          'rx_valid', '<=', '#', '1', '0', ';',
-          'else',
-          'rx_valid', '<=', '#', '1', 'RxValid', ';',
-       'always',
-        '@', '(', 'posedge', 'phy_clk', ')',
-         'if',
-          '(', '!', 'rst', ')',
-          'rx_active', '<=', '#', '1', '0', ';',
-          'else',
-          'rx_active', '<=', '#', '1', 'RxActive', ';',
-       'always',
-        '@', '(', 'posedge', 'phy_clk', ')',
-         'if',
-          '(', '!', 'rst', ')',
-          'rx_err', '<=', '#', '1', '0', ';',
-          'else',
-          'rx_err', '<=', '#', '1', 'RxError', ';',
-       'always',
-        '@', '(', 'posedge', 'phy_clk', ')',
-        'rx_data', '<=', '#', '1', 'DataIn', ';',
-      'wire', 'tx_valid_sr', ';',
-       'assign',
-         'tx_valid_sr',
-          '=',
-          '(',
-          '!', 'rst',
-          ')',
-          '?',
-          '0',
-          ':',
-          'tx_valid_last',
-          '?',
-          '1',
-          ':',
-          'TxReady',
-          '?',
-          '0',
-          ':',
-          'tx_valid_sr',
-        ';',
-       'always',
-        '@', '(', 'posedge', 'phy_clk', ')',
-         'if',
-          '(', 'TxReady', '|', 'tx_first', ')',
-          'DataOut', '<=', '#', '1', 'tx_data', ';',
-          'else',
-           'if',
-            '(', 'drive_k', ')',
-            'DataOut', '<=', '#', '1', "8 'h ff", ';',
-       'always',
-        '@', '(', 'posedge', 'phy_clk', ')',
-        'tx_ready', '<=', '#', '1', 'TxReady', ';',
-       'always',
-        '@', '(', 'posedge', 'phy_clk', ')',
-          'TxValid',
-            '<=',
-            '#', '1',
-            'tx_valid',
-            '|',
-            'tx_valid_sr',
-            '|',
-            'drive_k',
-          ';',
-       'utmi_ls',
-         'u0',
-           '(',
-            '.', 'clk', '(', 'phy_clk', ')',
-            '.', 'rst', '(', 'rst', ')',
-            '.', 'resume_req', '(', 'resume_req', ')',
-            '.', 'rx_active', '(', 'rx_active', ')',
-            '.', 'tx_ready', '(', 'tx_ready', ')',
-            '.', 'drive_k', '(', 'drive_k', ')',
-            '.', 'XcvSelect', '(', 'XcvSelect', ')',
-            '.', 'TermSel', '(', 'TermSel', ')',
-            '.', 'SuspendM', '(', 'SuspendM', ')',
-            '.', 'LineState', '(', 'LineState', ')',
-            '.', 'OpMode', '(', 'OpMode', ')',
-            '.', 'usb_vbus', '(', 'usb_vbus', ')',
-            '.', 'mode_hs', '(', 'mode_hs', ')',
-            '.', 'usb_reset', '(', 'usb_reset', ')',
-            '.', 'usb_suspend', '(', 'usb_suspend', ')',
-            '.', 'usb_attached', '(', 'usb_attached', ')',
-            ')',
-        ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/vpi_utilities_test.v.parsed.txt Deleted

@@ -1,87 +0,0 @@
-/**********************************************************************
- * $vpi_util_test example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the VPI utility applications. 
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-  reg  a, b, ci;
-  wire sum, co;
-  real r1;
-
-  addbit i1 (a, b, ci, sum, co);
-
-  initial
-    begin
-      a = 0; b = 1; ci = 1;
-      r1 = 0.5;
-      $vpi_util_test(i1, r1, ci, "Hello world", /*null arg*/ );
-      #1 $finish;
-    end
- 
- endmodule
-
-/*** A gate level 1 bit adder model ***/
-`timescale 1ns / 1ns
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci, sum, co,
-        n1, n2, n3;
-
-  xor    (n1, a, b);
-  xor #2 (sum, n1, ci);
-  and    (n2, a, b);
-  and    (n3, n1, ci);
-  or  #2 (co, n2, n3);
-
-endmodule
-/**********************************************************************/
-
-
-  'module', 'test', ';',
-     'reg', 'a', 'b', 'ci', ';',
-      'wire', 'sum', 'co', ';',
-      'real', 'r1', ';',
-       'addbit',
-        'i1', '(', 'a', 'b', 'ci', 'sum', 'co', ')',
-        ';',
-       'initial',
-         'begin',
-           'a', '=', '0', ';',
-            'b', '=', '1', ';',
-            'ci', '=', '1', ';',
-            'r1', '=', '0.5', ';',
-             '$vpi_util_test',
-              '(',
-              'i1',
-              'r1',
-              'ci',
-              '"Hello world"',
-              ')',
-              ';',
-            '#', '1', '$finish', ';',
-          'end',
-    'endmodule',
-    'module',
-      'addbit',
-      '(',
-      'a', 'b', 'ci', 'sum', 'co',
-      ')',
-      ';',
-     'input', 'a', 'b', 'ci', ';',
-      'output', 'sum', 'co', ';',
-      'wire', 'a', 'b', 'ci', 'sum', 'co', 'n1', 'n2', 'n3', ';',
-      'xor', '(', 'n1', 'a', 'b', ')', ';',
-      'xor', '#', '2', '(', 'sum', 'n1', 'ci', ')', ';',
-      'and', '(', 'n2', 'a', 'b', ')', ';',
-      'and', '(', 'n3', 'n1', 'ci', ')', ';',
-      'or', '#', '2', '(', 'co', 'n2', 'n3', ')', ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/wb.v.parsed.txt Deleted

@@ -1,296 +0,0 @@
-/////////////////////////////////////////////////////////////////////
-////                                                             ////
-////  WISHBONE Interface                                         ////
-////  This is the external bus interface, that is WISHBONE       ////
-////  SoC compliant.                                             ////
-////                                                             ////
-////                                                             ////
-////  Author: Rudolf Usselmann                                   ////
-////          rudi@asics.ws                                      ////
-////                                                             ////
-////                                                             ////
-////  Downloaded from: http://www.opencores.org/cores/usb/       ////
-////                                                             ////
-/////////////////////////////////////////////////////////////////////
-////                                                             ////
-//// Copyright (C) 2000 Rudolf Usselmann                         ////
-////                    rudi@asics.ws                            ////
-////                                                             ////
-//// This source file may be used and distributed without        ////
-//// restriction provided that this copyright statement is not   ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer.////
-////                                                             ////
-////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
-//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
-//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
-//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
-//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
-//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
-//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
-//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
-//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
-//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
-//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
-//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
-//// POSSIBILITY OF SUCH DAMAGE.                                 ////
-////                                                             ////
-/////////////////////////////////////////////////////////////////////
-
-//  CVS Log
-//
-//  $Id: wb.v,v 1.0 2001/03/07 09:17:12 rudi Exp $
-//
-//  $Date: 2001/03/07 09:17:12 $
-//  $Revision: 1.0 $
-//  $Author: rudi $
-//  $Locker:  $
-//  $State: Exp $
-//
-// Change History:
-//               $Log: wb.v,v $
-//               Revision 1.0  2001/03/07 09:17:12  rudi
-//
-//
-//               Changed all revisions to revision 1.0. This is because OpenCores CVS
-//               interface could not handle the original '0.1' revision ....
-//
-//               Revision 0.1.0.1  2001/02/28 08:11:47  rudi
-//               Initial Release
-//
-//
-
-`include "usb_defines.v"
-
-module wb(  // WISHBONE Interface
-        clk, rst, addr_i, data_i, data_o, 
-        ack_o, we_i, stb_i, cyc_i,
-
-        // UTMI Interface
-        phy_clk,
-
-        // Memory Arbiter Interface
-        wadr, wdout, wdin, wwe, wreq, wack,
-
-        // Register File interface
-        re, we, din, dout);
-
-input       clk;
-input       rst;
-input   17:0  addr_i;
-input   31:0  data_i;
-output  31:0  data_o;
-output      ack_o;
-input       we_i;
-input       stb_i;
-input       cyc_i;
-
-input       phy_clk;
-
-// Memory Arbiter Interface
-output  14:0  wadr;
-output  31:0  wdout;
-input   31:0  wdin;
-output      wwe;
-output      wreq;
-input       wack;
-
-// Register File interface
-output      re;
-output      we;
-input   31:0  din;
-output  31:0  dout;
-
-
-///////////////////////////////////////////////////////////////////
-//
-// Local Wires and Registers
-//
-
-reg     wack_r, wack_r2;
-wire        csm, csr;
-
-reg     ack_o;
-reg 31:0  data_o;
-wire        reg_ack_d;
-
-///////////////////////////////////////////////////////////////////
-//
-// Interface Logic
-//
-
-assign csm = stb_i & cyc_i &  addr_i17;   // Memory Chip Select
-assign csr = stb_i & cyc_i & !addr_i17;   // Register File Chip Select
-
-// Memory Buffer Interface
-assign wadr = addr_i16:2;
-assign wreq = csm;
-assign wwe  =  csm & we_i;
-assign wdout = data_i;
-
-assign  reg_ack_d = csr & !ack_o;
-
-always @(posedge phy_clk or posedge ack_o)
-    if(ack_o)   wack_r <= #1 0;
-    else        wack_r <= #1 wack | reg_ack_d;
-
-always @(posedge phy_clk or posedge ack_o)
-    if(ack_o)   wack_r2 <= #1 0;
-    else        wack_r2 <= #1 wack_r & (wack | reg_ack_d);
-
-// Register File Interface
-assign re = csr & !we_i;
-assign we = csr &  we_i;
-assign dout = data_i;
-
-// Shared Signals
-
-always @(posedge clk)
-    if(!rst | ack_o)                ack_o <= #1 0;
-    else
-    if(wack_r & wack_r2 & (wreq | reg_ack_d))   ack_o <= #1 1;
-
-always @(posedge clk)
-    if(!csm)                    data_o <= #1 din;
-    else
-    if(wack_r & wack_r2 & (reg_ack_d | wreq))   data_o <= #1 wdin;
-
-endmodule
-
-
-
-
-   'module',
-      'wb',
-      '(',
-       'clk',
-        'rst',
-        'addr_i',
-        'data_i',
-        'data_o',
-        'ack_o',
-        'we_i',
-        'stb_i',
-        'cyc_i',
-        'phy_clk',
-        'wadr',
-        'wdout',
-        'wdin',
-        'wwe',
-        'wreq',
-        'wack',
-        're',
-        'we',
-        'din',
-        'dout',
-      ')',
-      ';',
-     'input', 'clk', ';',
-      'input', 'rst', ';',
-      'input', '', '17', ':', '0', '', 'addr_i', ';',
-      'input', '', '31', ':', '0', '', 'data_i', ';',
-      'output', '', '31', ':', '0', '', 'data_o', ';',
-      'output', 'ack_o', ';',
-      'input', 'we_i', ';',
-      'input', 'stb_i', ';',
-      'input', 'cyc_i', ';',
-      'input', 'phy_clk', ';',
-      'output', '', '14', ':', '0', '', 'wadr', ';',
-      'output', '', '31', ':', '0', '', 'wdout', ';',
-      'input', '', '31', ':', '0', '', 'wdin', ';',
-      'output', 'wwe', ';',
-      'output', 'wreq', ';',
-      'input', 'wack', ';',
-      'output', 're', ';',
-      'output', 'we', ';',
-      'input', '', '31', ':', '0', '', 'din', ';',
-      'output', '', '31', ':', '0', '', 'dout', ';',
-      'reg', 'wack_r', 'wack_r2', ';',
-      'wire', 'csm', 'csr', ';',
-      'reg', 'ack_o', ';',
-      'reg', '', '31', ':', '0', '', 'data_o', ';',
-      'wire', 'reg_ack_d', ';',
-       'assign',
-         'csm',
-          '=',
-          'stb_i',
-          '&',
-          'cyc_i',
-          '&',
-          'addr_i', '', '17', '',
-        ';',
-       'assign',
-         'csr',
-          '=',
-          'stb_i',
-          '&',
-          'cyc_i',
-          '&',
-          '!',
-          'addr_i', '', '17', '',
-        ';',
-      'assign', 'wadr', '=', 'addr_i', '', '16', '2', '', ';',
-      'assign', 'wreq', '=', 'csm', ';',
-      'assign', 'wwe', '=', 'csm', '&', 'we_i', ';',
-      'assign', 'wdout', '=', 'data_i', ';',
-      'assign', 'reg_ack_d', '=', 'csr', '&', '!', 'ack_o', ';',
-       'always',
-        '@', '(', 'posedge', 'phy_clk', 'posedge', 'ack_o', ')',
-         'if',
-          '(', 'ack_o', ')',
-          'wack_r', '<=', '#', '1', '0', ';',
-          'else',
-          'wack_r', '<=', '#', '1', 'wack', '|', 'reg_ack_d', ';',
-       'always',
-        '@', '(', 'posedge', 'phy_clk', 'posedge', 'ack_o', ')',
-         'if',
-          '(', 'ack_o', ')',
-          'wack_r2', '<=', '#', '1', '0', ';',
-          'else',
-            'wack_r2',
-              '<=',
-              '#', '1',
-              'wack_r',
-              '&',
-              '(',
-              'wack', '|', 'reg_ack_d',
-              ')',
-            ';',
-      'assign', 're', '=', 'csr', '&', '!', 'we_i', ';',
-      'assign', 'we', '=', 'csr', '&', 'we_i', ';',
-      'assign', 'dout', '=', 'data_i', ';',
-       'always',
-        '@', '(', 'posedge', 'clk', ')',
-         'if',
-          '(', '!', 'rst', '|', 'ack_o', ')',
-          'ack_o', '<=', '#', '1', '0', ';',
-          'else',
-           'if',
-             '(',
-              'wack_r',
-              '&',
-              'wack_r2',
-              '&',
-              '(',
-              'wreq', '|', 'reg_ack_d',
-              ')',
-              ')',
-            'ack_o', '<=', '#', '1', '1', ';',
-       'always',
-        '@', '(', 'posedge', 'clk', ')',
-         'if',
-          '(', '!', 'csm', ')',
-          'data_o', '<=', '#', '1', 'din', ';',
-          'else',
-           'if',
-             '(',
-              'wack_r',
-              '&',
-              'wack_r2',
-              '&',
-              '(',
-              'reg_ack_d', '|', 'wreq',
-              ')',
-              ')',
-            'data_o', '<=', '#', '1', 'wdin', ';',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/wpulse.v.parsed.txt Deleted

@@ -1,359 +0,0 @@
-//
-// 
-//  This circuit generates WE pulses.  For example, if you have a chip that
-//  needs to access an asynchronous SRAM in a single cycle and you wanted
-//  generate the WE pulse synchronous with your system clock.
-//
-//  Every clk cycle, generate an active
-//  low WE pulse.  The delay from the clk rising edge to the falling edge of
-//  we is based on abits setting, which affects delay taps, etc.  Likewise,
-//  bbits controls the following rising edge of we.  The module contains
-//  two flip flops that generate two opposite poraity toggling levels.
-//  A delay chain is attached to each of these outputs.  The abits and bbits
-//  get the desired tap, and the final two delayed signals are XORed together
-//  to get the final we.  None of this is very tuned, you would look at your
-//  cycle time and pick a delay chain that makes sense for that.  But, this
-//  shows the effect.
-//
-//  The we pulse always occurs.  You will probably want to combine this with
-//  you write_enable signal.  This sort of circuit is, of course, highly dependent
-//  on post-layout timing, etc.  but that's why its programable.  You probably
-//  want more taps, too..
-//
-//
-module wpulse (
-   reset,
-   clk,
-   abits,
-   bbits,
-   we
-);
-
-input		clk;
-input		reset;
-input 3:0	abits; // bits to select which delay tap to use for first edge
-input 3:0	bbits; // bits to select which delay tap to use for pulse width
-output		we;
-
-reg 		p1, p2;
-
-wire		adel1out;
-wire		adel2out;
-wire		adel3out;
-wire		adel4out;
-wire		bdel1out;
-wire		bdel2out;
-wire		bdel3out;
-wire		bdel4out;
-
-wire		adelout;
-wire		bdelout;
-
-// 2 flip-flops that are opposite polarity.  Each flop toggles
-// every cycles.
-//
-always @(posedge clk)
-   p1 <= (reset) | (~reset & ~p1); // reset to 1
-always @(posedge clk)
-   p2 <= (~reset & ~p2);  // reset to 0
-
-// Delay chain off of the p1 flop.   
-delay4 adel1 (.a(p1),		.z(adel1out));
-delay4 adel2 (.a(adel1out),	.z(adel2out));
-delay4 adel3 (.a(adel2out),	.z(adel3out));
-delay4 adel4 (.a(adel3out),	.z(adel4out));
-
-// Delay chain off of the p2 flop.
-delay4 bdel1 (.a(p2),		.z(bdel1out));
-delay4 bdel2 (.a(bdel1out),	.z(bdel2out));
-delay4 bdel3 (.a(bdel2out),	.z(bdel3out));
-delay4 bdel4 (.a(bdel3out),	.z(bdel4out));
-
-// Select the tap of the p1 and p2 delay chains we want based on abits
-assign adelout =	abits3 & adel1out | 
-			abits2 & adel2out | 
-			abits1 & adel3out |
-			abits0 & adel4out;
-assign bdelout =	bbits3 & bdel1out | 
-			bbits2 & bdel2out | 
-			bbits1 & bdel3out |
-			bbits0 & bdel4out;
-
-// Final we pulse is just the XOR of the two chains.  
-assign we = adelout ^ bdelout;
-
-endmodule
-
-// This is our delay cell.  Pick whatever cell makes sense from your library.
-module delay4 (a, z);
-input a;
-output z;
-reg	z;
-always @(a)
-  z = #4 a;
-endmodule
-
-// synopsys translate_off
-module testwpulse;
-reg		clk;
-reg		reset;
-reg 3:0	abits; // bits to select which delay tap to use for first edge
-reg 3:0	bbits; // bits to select which delay tap to use for pulse width
-wire		we;
-
-wpulse wpulse_inst (
-   .reset	(reset),
-   .clk		(clk),
-   .abits	(abits),
-   .bbits	(bbits),
-   .we		(we)
-);
-
-initial begin
-   abits = 4'b1000; // Shortest pulse, earliest in cycle.
-   bbits = 4'b0100;
-   #200;
-
-   abits = 4'b0010; // Shortest pulse, latest in the cycle.
-   bbits = 4'b0001;
-   #200;
-
-   abits = 4'b0100; // Shortest pulse, middle of the cycle.
-   bbits = 4'b0010;
-   #200;
-
-   abits = 4'b1000; // Longest cycle
-   bbits = 4'b0001;
-   #200;
-
-   abits = 4'b1000; // Early in cycle, but not quite the longest.
-   bbits = 4'b0010;
-   #200;
-
-   $finish;
-end
-
-// Reset
-initial begin
-   reset = 0;
-   #5 reset = 1;
-   #100 reset = 0;
-end
-   
-// Generate the 50MHz clock
-initial begin
-   clk = 0;
-   forever begin
-      #10 clk = 1;
-      #10 clk = 0;
-   end
-end
-
-`define WAVES
-`ifdef WAVES
-initial begin
-   $dumpfile ("wpulse.vcd");
-   $dumpvars (0,testwpulse);   
-end
-`endif
-endmodule
-// synopsys translate_on
-
-
-   'module',
-      'wpulse',
-      '(',
-      'reset', 'clk', 'abits', 'bbits', 'we',
-      ')',
-      ';',
-     'input', 'clk', ';',
-      'input', 'reset', ';',
-      'input', '', '3', ':', '0', '', 'abits', ';',
-      'input', '', '3', ':', '0', '', 'bbits', ';',
-      'output', 'we', ';',
-      'reg', 'p1', 'p2', ';',
-      'wire', 'adel1out', ';',
-      'wire', 'adel2out', ';',
-      'wire', 'adel3out', ';',
-      'wire', 'adel4out', ';',
-      'wire', 'bdel1out', ';',
-      'wire', 'bdel2out', ';',
-      'wire', 'bdel3out', ';',
-      'wire', 'bdel4out', ';',
-      'wire', 'adelout', ';',
-      'wire', 'bdelout', ';',
-       'always',
-        '@', '(', 'posedge', 'clk', ')',
-          'p1',
-            '<=',
-            '(',
-            'reset',
-            ')',
-            '|',
-            '(',
-            '~', 'reset', '&', '~', 'p1',
-            ')',
-          ';',
-       'always',
-        '@', '(', 'posedge', 'clk', ')',
-        'p2', '<=', '(', '~', 'reset', '&', '~', 'p2', ')', ';',
-       'delay4',
-         'adel1',
-           '(',
-            '.', 'a', '(', 'p1', ')',
-            '.', 'z', '(', 'adel1out', ')',
-            ')',
-        ';',
-       'delay4',
-         'adel2',
-           '(',
-            '.', 'a', '(', 'adel1out', ')',
-            '.', 'z', '(', 'adel2out', ')',
-            ')',
-        ';',
-       'delay4',
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-           '(',
-            '.', 'a', '(', 'adel2out', ')',
-            '.', 'z', '(', 'adel3out', ')',
-            ')',
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-       'delay4',
-         'adel4',
-           '(',
-            '.', 'a', '(', 'adel3out', ')',
-            '.', 'z', '(', 'adel4out', ')',
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-       'delay4',
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-           '(',
-            '.', 'a', '(', 'p2', ')',
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-            ')',
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-       'delay4',
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-            '.', 'a', '(', 'bdel1out', ')',
-            '.', 'z', '(', 'bdel2out', ')',
-            ')',
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-            '.', 'a', '(', 'bdel2out', ')',
-            '.', 'z', '(', 'bdel3out', ')',
-            ')',
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-            '.', 'a', '(', 'bdel3out', ')',
-            '.', 'z', '(', 'bdel4out', ')',
-            ')',
-        ';',
-       'assign',
-         'adelout',
-          '=',
-          'abits', '', '3', '',
-          '&',
-          'adel1out',
-          '|',
-          'abits', '', '2', '',
-          '&',
-          'adel2out',
-          '|',
-          'abits', '', '1', '',
-          '&',
-          'adel3out',
-          '|',
-          'abits', '', '0', '',
-          '&',
-          'adel4out',
-        ';',
-       'assign',
-         'bdelout',
-          '=',
-          'bbits', '', '3', '',
-          '&',
-          'bdel1out',
-          '|',
-          'bbits', '', '2', '',
-          '&',
-          'bdel2out',
-          '|',
-          'bbits', '', '1', '',
-          '&',
-          'bdel3out',
-          '|',
-          'bbits', '', '0', '',
-          '&',
-          'bdel4out',
-        ';',
-      'assign', 'we', '=', 'adelout', '^', 'bdelout', ';',
-    'endmodule',
-   'module', 'delay4', '(', 'a', 'z', ')', ';',
-     'input', 'a', ';',
-      'output', 'z', ';',
-      'reg', 'z', ';',
-       'always',
-        '@', '(', 'a', ')',
-        'z', '=', '#', '4', 'a', ';',
-    'endmodule',
-   'module', 'testwpulse', ';',
-     'reg', 'clk', ';',
-      'reg', 'reset', ';',
-      'reg', '', '3', ':', '0', '', 'abits', ';',
-      'reg', '', '3', ':', '0', '', 'bbits', ';',
-      'wire', 'we', ';',
-       'wpulse',
-         'wpulse_inst',
-           '(',
-            '.', 'reset', '(', 'reset', ')',
-            '.', 'clk', '(', 'clk', ')',
-            '.', 'abits', '(', 'abits', ')',
-            '.', 'bbits', '(', 'bbits', ')',
-            '.', 'we', '(', 'we', ')',
-            ')',
-        ';',
-       'initial',
-         'begin',
-           'abits', '=', "4 'b 1000", ';',
-            'bbits', '=', "4 'b 0100", ';',
-            '#', '200', ';',
-            'abits', '=', "4 'b 0010", ';',
-            'bbits', '=', "4 'b 0001", ';',
-            '#', '200', ';',
-            'abits', '=', "4 'b 0100", ';',
-            'bbits', '=', "4 'b 0010", ';',
-            '#', '200', ';',
-            'abits', '=', "4 'b 1000", ';',
-            'bbits', '=', "4 'b 0001", ';',
-            '#', '200', ';',
-            'abits', '=', "4 'b 1000", ';',
-            'bbits', '=', "4 'b 0010", ';',
-            '#', '200', ';',
-            '$finish', ';',
-          'end',
-       'initial',
-         'begin',
-           'reset', '=', '0', ';',
-            '#', '5', 'reset', '=', '1', ';',
-            '#', '100', 'reset', '=', '0', ';',
-          'end',
-       'initial',
-         'begin',
-           'clk', '=', '0', ';',
-             'forever',
-               'begin',
-                 '#', '10', 'clk', '=', '1', ';',
-                  '#', '10', 'clk', '=', '0', ';',
-                'end',
-          'end',
-       'initial',
-         'begin',
-           '$dumpfile', '(', '"wpulse.vcd"', ')', ';',
-            '$dumpvars', '(', '0', 'testwpulse', ')', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/xor.v.parsed.txt Deleted

@@ -1,377 +0,0 @@
-// Verilog HDL for "gates.lib", "xor_gate" "_functional"
-// Module XOR gate
-module xor_gate (a, b, clk, out);
-
-input
-	a, b, clk;
-
-output
-	out;
-reg 
-	out;
-
-parameter
-	t_hold=5,
-	t_setup=10,
-	delay=15,
-
-	warning_file=3;  // multichannel description of a warning file
-
-reg
-	a_internal, b_internal, clk_internal,
-	a_state, b_state,          // internal state at inputs a and b
-	a_violation, b_violation,  // timing violation at inputs a and b
-	a_set, b_set;		   // signals determining the moment when
-				   // the state of the a,b inputs changes to "1"
-integer
-	data_delay, 	// delay between a (b) and a_internal (b_internal)
-	clk_delay, 	// delay between clk and clk_internal
-	out_delay, 	// delay between clk_internal and out
-	out_value,	// output value in a given clock cycle
-	last_clk_time;	// time when the last clock pulse appeared
-
-initial 
-	begin
-// define delays between inputs & outputs and the corresponding
-//  internal auxiliary registers
-	  	if(t_hold<0)
-		  begin
-	    		data_delay = -t_hold;
-	    	  	clk_delay = 0;
-		  	out_delay = delay;
-		  end
-	  	else
-		  begin
-	    	  	data_delay = 0;
-	    	  	clk_delay = t_hold;
-		  	out_delay=delay-t_hold;
-		  end
-
-// clear internal registers and the output signal
-		a_internal = 0;
-		b_internal = 0;
-		clk_internal = 0;
-		last_clk_time = 0;
-		a_state = 0;
-		b_state = 0;
-		a_violation = 0;
-		b_violation = 0;
-		a_set = 0;
-		b_set = 0;
-		out = 0;
-	end
-
-always @(posedge a) 	// Execute at positive edge of a
-	  a_internal <= #(data_delay) a;
-
-always @(posedge b) 	// Execute at positive edge of b
-	  b_internal <= #(data_delay) b;
-
-always @(posedge clk) 	// Execute at positive edge of clk
-	  clk_internal <= #(clk_delay) clk;
-
-always @(posedge a_internal)
-	begin
-// setting an internal state at the input a
-		a_violation = 1;
-		if (a_internal === 1)
-		  a_set <= #(t_hold+t_setup) 1;
-
-		a_internal <= 0;
-	end
-
-always @(posedge b_internal)
-	begin
-// setting an internal state at the input a
-		b_violation = 1;
-		if (b_internal === 1)
-		  b_set <= #(t_hold+t_setup) 1;
-
-		b_internal <= 0;
-	end
-
-always @(posedge a_set)
-	begin
-		if ($stime - last_clk_time >= t_hold+t_setup)
-			a_state = a_state^1;
-		else
-		  begin
-			a_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input A pulse at %0d,",
-			 $stime-data_delay-t_hold-t_setup);
-			$fwrite(warning_file,
-			"\tClock pulse at %0d.\n", last_clk_time-clk_delay);
-		  end
-
-		a_violation <= 0;
-		a_set <= 0;
-	end
-
-always @(posedge b_set)
-	begin
-		if ($stime - last_clk_time >= t_hold+t_setup)
-			b_state = b_state^1;
-		else
-		  begin
-			b_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input B pulse at %0d,",
-			 $stime-data_delay-t_hold-t_setup);
-			$fwrite(warning_file,
-			"\tClock pulse at %0d.\n", last_clk_time-clk_delay);
-		  end
-
-		b_violation <= 0;
-		b_set <= 0;
-	end
-
-
-always @(posedge clk_internal)	
-	begin
-// computing the output
-		if ((clk_internal === 1'bx) || (a_violation | b_violation))
-		  out_value = 1'bx;
-		else
-		  out_value = a_state ^ b_state;
-
-// transfering the result to the output
-		out <= #(out_delay) out_value;
-		out <= #(out_delay+2) 0;
-
-// clearing the internal state of A and B inputs
-		a_state  <= 0;
-		b_state  <= 0;
-
-		clk_internal <= 0;
-		last_clk_time = $stime;
-	end
-
-endmodule
-
-
-  'module', 'xor_gate', '(', 'a', 'b', 'clk', 'out', ')', ';',
-     'input', 'a', 'b', 'clk', ';',
-      'output', 'out', ';',
-      'reg', 'out', ';',
-       'parameter',
-        't_hold', '=', '5',
-        't_setup', '=', '10',
-        'delay', '=', '15',
-        'warning_file', '=', '3',
-        ';',
-       'reg',
-        'a_internal',
-        'b_internal',
-        'clk_internal',
-        'a_state',
-        'b_state',
-        'a_violation',
-        'b_violation',
-        'a_set',
-        'b_set',
-        ';',
-       'integer',
-        'data_delay',
-        'clk_delay',
-        'out_delay',
-        'out_value',
-        'last_clk_time',
-        ';',
-       'initial',
-         'begin',
-            'if',
-              '(', 't_hold', '<', '0', ')',
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-                  'out_delay', '=', 'delay', ';',
-                'end',
-              'else',
-               'begin',
-                 'data_delay', '=', '0', ';',
-                  'clk_delay', '=', 't_hold', ';',
-                  'out_delay', '=', 'delay', '-', 't_hold', ';',
-                'end',
-            'a_internal', '=', '0', ';',
-            'b_internal', '=', '0', ';',
-            'clk_internal', '=', '0', ';',
-            'last_clk_time', '=', '0', ';',
-            'a_state', '=', '0', ';',
-            'b_state', '=', '0', ';',
-            'a_violation', '=', '0', ';',
-            'b_violation', '=', '0', ';',
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-                    ')',
-                    ';',
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-               '(',
-                '(',
-                'clk_internal', '===', "1 'b x",
-                ')',
-                '||',
-                '(',
-                'a_violation', '|', 'b_violation',
-                ')',
-                ')',
-              'out_value', '=', "1 'b x", ';',
-              'else',
-              'out_value', '=', 'a_state', '^', 'b_state', ';',
-             'out', '<=', '#', '(', 'out_delay', ')', 'out_value',
-              ';',
-             'out', '<=', '#', '(', 'out_delay', '+', '2', ')', '0',
-              ';',
-            'a_state', '<=', '0', ';',
-            'b_state', '<=', '0', ';',
-            'clk_internal', '<=', '0', ';',
-            'last_clk_time', '=', '$stime', ';',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/parseOutput/zzzexample.v.parsed.txt Deleted

@@ -1,496 +0,0 @@
-
-module test ( a,b,d);
-	input 4:0 a;
-	input 20:0 b;
-	output d;
-
-   always @(a or b)
-   begin
-      if (a == 5'b00000)
-      begin
-         d = b2:0 ; 
-      end
-      else if (a == 5'b00001)
-      begin
-         d = b5:3 ; 
-      end
-      else if (a == 5'b00010)
-      begin
-         d = b8:6 ; 
-      end
-      else if (a == 5'b00011)
-      begin
-         d = b11:9 ; 
-      end
-      else if (a == 5'b00100)
-      begin
-         d = b14:12 ; 
-      end
-      else if (a == 5'b00101)
-      begin
-         d = b17:15 ; 
-      end
-      else if (a == 5'b00110)
-      begin
-         d = b20:18 ; 
-      end
-      else if (a == 5'b00111)
-      begin
-         d = b2:0 ; 
-      end
-      else if (a == 5'b01000)
-      begin
-         d = b5:3 ; 
-      end
-      else if (a == 5'b01001)
-      begin
-         d = b8:6 ; 
-      end
-      else if (a == 5'b01010)
-      begin
-         d = b11:9 ; 
-      end
-      else if (a == 5'b01011)
-      begin
-         d = b14:12 ; 
-      end
-      else if (a == 5'b01100)
-      begin
-         d = b17:15 ; 
-      end
-      else if (a == 5'b01101)
-      begin
-         d = b20:18 ; 
-      end
-      else if (a == 5'b01110)
-      begin
-         d = b2:0 ; 
-      end
-      else if (a == 5'b01111)
-      begin
-         d = b5:3 ; 
-      end
-      else if (a == 5'b10000)
-      begin
-         d = b8:6 ; 
-      end
-      else if (a == 5'b10001)
-      begin
-         d = b11:9 ; 
-      end
-      else if (a == 5'b10010)
-      begin
-         d = b14:12 ; 
-      end
-      else if (a == 5'b10011)
-      begin
-         d = b17:15 ; 
-      end
-      else if (a == 5'b10100)
-      begin
-         d = b20:18 ; 
-      end
-      else if (a == 5'b10101)
-      begin
-         d = b2:0 ; 
-      end
-      else if (a == 5'b10110)
-      begin
-         d = b5:3 ; 
-      end
-      else if (a == 5'b10111)
-      begin
-         d = b8:6 ; 
-      end
-      else if (a == 5'b11000)
-      begin
-         d = b11:9 ; 
-      end
-      else if (a == 5'b11001)
-      begin
-         d = b14:12 ; 
-      end
-      else if (a == 5'b11010)
-      begin
-         d = b17:15 ; 
-      end
-      else if (a == 5'b11011)
-      begin
-         d = b20:18 ; 
-      end
-      else if (a == 5'b11111)
-      begin
-         d = 3'b0; 
-      end
-      else
-      begin
-         d = {3{1'b0}} ; 
-      end 
-   end 
-endmodule
-
-
-  'module', 'test', '(', 'a', 'b', 'd', ')', ';',
-     'input', '', '4', ':', '0', '', 'a', ';',
-      'input', '', '20', ':', '0', '', 'b', ';',
-      'output', 'd', ';',
-       'always',
-        '@', '(', 'a', 'b', ')',
-         'begin',
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-               'begin',
-                'd', '=', 'b', '', '2', '0', '', ';',
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-               'if',
-                '(', 'a', '==', "5 'b 00001", ')',
-                 'begin',
-                  'd', '=', 'b', '', '5', '3', '', ';',
-                  'end',
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-                 'if',
-                  '(', 'a', '==', "5 'b 00010", ')',
-                   'begin',
-                    'd', '=', 'b', '', '8', '6', '', ';',
-                    'end',
-                  'else',
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-                      'd', '=', 'b', '', '11', '9', '', ';',
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-                       'begin',
-                        'd', '=', 'b', '', '14', '12', '', ';',
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-                         'begin',
-                          'd', '=', 'b', '', '17', '15', '', ';',
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-                         'if',
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-                                                                    '==',
-                                                                    "5 'b "
-                                                                    '11010',
-                                                                    ')',
-                                                                   'begin',
-                                                                       'd',
-                                                                          '=',
-                                                                           'b',
-                                                                             '',
-                                                                              '17',
-                                                                              '15',
-                                                                              '',
-                                                                        ';',
-                                                                    'end',
-                                                                  'else',
-                                                                   'if',
-                                                                     '(',
-                                                                      'a',
-                                                                      '==',
-                                                                      "5 'b "
-                                                                      '11011',
-                                                                      ')',
-                                                                     'begin',
-                                                                          'd',
-                                                                            '=',
-                                                                             'b',
-                                                                               '',
-                                                                                '20',
-                                                                                '18',
-                                                                                '',
-                                                                          ';',
-                                                                      'end',
-                                                                    'else',
-                                                                     'if',
-                                                                       '(',
-                                                                        'a',
-                                                                        '==',
-                                                                        "5 'b "
-                                                                        '11111',
-                                                                        ')',
-                                                                       'begin',
-                                                                            'd',
-                                                                              '=',
-                                                                              '3 '
-                                                                              "'b "
-                                                                              '0',
-                                                                            ';',
-                                                                        'end',
-                                                                      'else',
-                                                                       'begin',
-                                                                            'd',
-                                                                              '=',
-                                                                               '{',
-                                                                                '3',
-                                                                                 '{',
-                                                                                  '1 '
-                                                                                  "'b "
-                                                                                  '0',
-                                                                                  '}',
-                                                                                '}',
-                                                                            ';',
-                                                                        'end',
-          'end',
-    'endmodule'

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/pic.v Deleted

@@ -1,2247 +0,0 @@
-// 
-// SYNTHETIC PIC 2.0                                          4/23/98
-//
-//    This is a synthesizable Microchip 16C57 compatible
-//    microcontroller.  This core is not intended as a high fidelity model of
-//    the PIC, but simply a way to offer a simple processor core to people
-//    familiar with the PIC who also have PIC tools.  
-//
-//    pictest.v  -   top-level testbench (NOT SYNTHESIZABLE)
-//    piccpu.v   -   top-level synthesizable module
-//    picregs.v  -   register file instantiated under piccpu
-//    picalu.v   -   ALU instantiated under piccpu
-//    picidec.v  -   Instruction Decoder instantiated under piccpu
-//    hex2rom.c  -   C program used to translate MPLAB's INTEL HEX output
-//                   into the Verilog $readmemh compatible file
-//    test*.asm  -   (note the wildcard..) Several test programs used
-//                   to help debug the verilog.  I used MPLAB and the simulator
-//                   to develop these programs and get the expected results.
-//                   Then, I ran them on Verilog-XL where they appeared to
-//                   match.
-//
-//    Copyright, Tom Coonan, '97.
-//    Use freely, but not for resale as is.  You may use this in your
-//    own projects as desired.  Just don't try to sell it as is!
-//
-//
-module picalu (
-   op,
-   a,
-   b,
-   y,
-   cin,
-   cout,
-   zout
-);
-
-input  3:0	op;	// ALU Operation
-input  7:0	a;	// 8-bit Input a
-input  7:0	b;	// 8-bit Input b
-output 7:0	y;	// 8-bit Output
-input		cin;
-output		cout;
-output		zout;
-
-// Reg declarations for outputs
-reg		cout;
-reg		zout;
-reg 7:0	y;
-
-// Internal declarations
-reg		addercout; // Carry out straight from the adder itself.
- 
-parameter 3:0 ALUOP_ADD        = 4'b0000;
-parameter 3:0 ALUOP_SUB        = 4'b1000;
-parameter 3:0 ALUOP_AND        = 4'b0001;
-parameter 3:0 ALUOP_OR         = 4'b0010;
-parameter 3:0 ALUOP_XOR        = 4'b0011;
-parameter 3:0 ALUOP_COM        = 4'b0100;
-parameter 3:0 ALUOP_ROR        = 4'b0101;
-parameter 3:0 ALUOP_ROL        = 4'b0110;
-parameter 3:0 ALUOP_SWAP       = 4'b0111;
-
-always @(a or b or cin or op) begin
-   case (op) // synopsys full_case parallel_case
-      ALUOP_ADD:  {addercout,  y}  <= a + b;
-      ALUOP_SUB:  {addercout,  y}  <= a - b; // Carry out is really "borrow"
-      ALUOP_AND:  {addercout,  y}  <= {1'b0, a & b};
-      ALUOP_OR:   {addercout,  y}  <= {1'b0, a | b};
-      ALUOP_XOR:  {addercout,  y}  <= {1'b0, a ^ b};
-      ALUOP_COM:  {addercout,  y}  <= {1'b0, ~a};
-      ALUOP_ROR:  {addercout,  y}  <= {a0, cin, a7:1};
-      ALUOP_ROL:  {addercout,  y}  <= {a7, a6:0, cin};
-      ALUOP_SWAP: {addercout,  y}  <= {1'b0, a3:0, a7:4};
-      default:    {addercout,  y}  <= {1'b0, 8'h00};
-   endcase
-end
-
-always @(y)
-   zout <= (y == 8'h00);
-
-always @(addercout or op)
-   if (op == ALUOP_SUB) cout <= ~addercout; // Invert adder's carry to get borrow
-   else                 cout <=  addercout;
-      
-endmodule
-// 
-// SYNTHETIC PIC 2.0                                          4/23/98
-//
-//    This is a synthesizable Microchip 16C57 compatible
-//    microcontroller.  This core is not intended as a high fidelity model of
-//    the PIC, but simply a way to offer a simple processor core to people
-//    familiar with the PIC who also have PIC tools.  
-//
-//    pictest.v  -   top-level testbench (NOT SYNTHESIZABLE)
-//    piccpu.v   -   top-level synthesizable module
-//    picregs.v  -   register file instantiated under piccpu
-//    picalu.v   -   ALU instantiated under piccpu
-//    picidec.v  -   Instruction Decoder instantiated under piccpu
-//    hex2rom.c  -   C program used to translate MPLAB's INTEL HEX output
-//                   into the Verilog $readmemh compatible file
-//    test*.asm  -   (note the wildcard..) Several test programs used
-//                   to help debug the verilog.  I used MPLAB and the simulator
-//                   to develop these programs and get the expected results.
-//                   Then, I ran them on Verilog-XL where they appeared to
-//                   match.
-//
-//    Copyright, Tom Coonan, '97.
-//    Use freely, but not for resale as is.  You may use this in your
-//    own projects as desired.  Just don't try to sell it as is!
-//
-//
-module piccpu (
-   clk,
-   reset,
-   paddr,
-   pdata,
-   portain,
-   portbout,
-   portcout,
-   
-   debugw,
-   debugpc,
-   debuginst,
-   debugstatus
-);
-
-input		clk;
-input		reset;
-output 8:0	paddr;
-input  11:0	pdata;
-input  7:0	portain;
-output 7:0	portbout;
-output 7:0	portcout;
-
-output 7:0	debugw;
-output 8:0	debugpc;
-output 11:0	debuginst;
-output 7:0	debugstatus;
-
-// Register declarations for outputs
-reg 8:0	paddr;
-reg 7:0	portbout;
-reg 7:0	portcout;
-
-// This should be set to the ROM location where our restart vector is.
-// As set here, we have 512 words of program space.
-//
-parameter RESET_VECTOR = 9'h1FF;
-
-parameter	INDF_ADDRESS	= 3'h0,
-		TMR0_ADDRESS	= 3'h1,
-		PCL_ADDRESS	= 3'h2,
-		STATUS_ADDRESS	= 3'h3,
-		FSR_ADDRESS	= 3'h4,
-		PORTA_ADDRESS	= 3'h5,
-		PORTB_ADDRESS	= 3'h6,
-		PORTC_ADDRESS	= 3'h7;
-
-// Experimental custom peripheral, "Lil Adder (a 4-bit adder)" is at this address.
-//
-parameter	EXPADDRESS_LILADDER = 7'h7F;
-
-// *********  Special internal registers
-
-// Instruction Register
-reg  11:0	inst;
-
-// Program Counter
-reg  8:0	pc;
-reg  8:0	pcplus1; // Output of the pc incrementer.
-
-// Stack Registers and Stack "levels" register.
-reg  1:0	stacklevel;
-reg  8:0	stack1;
-reg  8:0	stack2;
-
-// W Register
-reg  7:0	w;
-
-// The STATUS register (#3) is 8 bits wide, however, we only currently use 2 bits
-// of it; the C and Z bit.
-//
-// bit 0  -  C
-// bit 2  -  Z
-//
-reg  7:0	status;
-
-// The FSR register is the pointer register used for Indirect addressing (e.g. using INDF).
-reg   7:0	fsr;
-
-// Timer 0
-reg   7:0	tmr0;
-reg   7:0	prescaler;
-
-// Option Register
-reg 7:0	option;
-
-// Tristate Control registers. We do not neccessarily support bidirectional ports, but
-//    will save a place for these registers and the TRIS instruction.  Use for debug.
-reg 7:0	trisa;
-reg 7:0	trisb;
-reg 7:0	trisc;
-
-// I/O Port registers
-//
-reg 7:0	porta;	// Input PORT
-reg 7:0	portb;	// Output PORT
-reg 7:0	portc;	// Output PORT
-
-// ********** Instruction Related signals ******
-
-reg 		skip;  // When HI force a NOP (all zeros) into inst
-
-reg  2:0	pcinsel;
-
-// Derive special sub signals from inst register
-wire  7:0	k;
-wire  4:0	fsel;
-wire  8:0	longk;
-wire		d;
-wire  2:0	b;
-
-// ********** File Address ************
-//
-// This is the 7-bit Data Address that includes the lower 5-bit fsel, the
-// FSR bits and any indirect addressing.
-// Use this bus to address the Register File as well as all special registers, etc.
-//
-reg 6:0	fileaddr;
-
-// Address Selects
-reg		specialsel;
-reg		regfilesel;
-reg		expsel;
-
-// ******  Instruction Decoder Outputs **************
-
-// Write enable for the actual ZERO and CARRY bits within the status register.
-// Generated by the Instruction Decoder.
-//
-wire 1:0	aluasel;
-wire 1:0	alubsel;
-wire 3:0	aluop;
-
-wire		zwe;
-wire		cwe;
-
-wire		isoption;
-wire		istris;
-
-wire		fwe;	// High if any "register" is being written to at all.
-wire		wwe;	// Write Enable for the W register.  Produced by Instruction Decoder.
-
-// *************  Internal Busses, mux connections, etc.  ********************
-
-// Bit decoder bits.  
-reg 7:0	bd;	// Final decoder value after any polarity inversion.
-reg 7:0	bdec;	// e.g. "Bit Decoded"
-
-// Data in and out of the and out of the register file
-//
-reg 7:0	regfilein;	// Input into Register File, is connected to the dbus.
-wire 7:0	regfileout;	// Path leaving the register file, goes to SBUS Mux
-reg		regfilewe;	// Write Enable
-reg		regfilere;	// Read Enable
-
-//
-// The dbus (Destination Bus) comes out of the ALU.  It is available to all
-// writable registers.
-//
-// The sbus (Source Bus) comes from all readable registers as well as the output
-// of the Register File.  It is one of the primary inputs into the ALU muxes.
-//
-// The ebus (Expansion Bus) comes from any of our custom modules.  They must
-// all coordinate to place whoever's data onto ebus.
-//
-reg  7:0	dbus;
-reg  7:0	sbus;
-reg  7:0	ebus;
-
-
-// ALU Signals
-//
-reg  7:0	alua;
-reg  7:0	alub;
-wire 7:0	aluout;
-wire 		alucin;
-wire		alucout;
-wire       	aluz;
-
-// ALU A and B mux selects.
-//
-parameter 1:0	ALUASEL_W	= 2'b00,
-		ALUASEL_SBUS	= 2'b01,
-		ALUASEL_K	= 2'b10,
-		ALUASEL_BD	= 2'b11;
-		
-parameter 1:0	ALUBSEL_W	= 2'b00,
-		ALUBSEL_SBUS	= 2'b01,
-		ALUBSEL_K	= 2'b10,
-		ALUBSEL_1	= 2'b11;
-
-// ALU Operation codes.
-//		
-parameter  3:0 ALUOP_ADD  = 4'b0000;
-parameter  3:0 ALUOP_SUB  = 4'b1000;
-parameter  3:0 ALUOP_AND  = 4'b0001;
-parameter  3:0 ALUOP_OR   = 4'b0010;
-parameter  3:0 ALUOP_XOR  = 4'b0011;
-parameter  3:0 ALUOP_COM  = 4'b0100;
-parameter  3:0 ALUOP_ROR  = 4'b0101;
-parameter  3:0 ALUOP_ROL  = 4'b0110;
-parameter  3:0 ALUOP_SWAP = 4'b0111;
-
-
-// Instantiate each of our subcomponents
-//
-picregs  regs (
-   .clk		(clk), 
-   .reset	(reset),
-   .we  	(regfilewe),
-   .re		(regfilere),
-   .bank	(fileaddr6:5), 
-   .location	(fileaddr4:0),
-   .din		(regfilein), 
-   .dout	(regfileout)
-);
-
-// Instatiate the ALU.
-//
-picalu   alu  (
-   .op         (aluop), 
-   .a          (alua), 
-   .b          (alub),
-   .y          (aluout),
-   .cin        (status0), 
-   .cout       (alucout), 
-   .zout       (aluz)
-);
-
-// Instantiate the Instruction Decoder.  This is really just a lookup table.
-// Given the instruction, generate all the signals we need.  
-//
-// For example, each instruction implies a specific ALU operation.  Some of
-// these are obvious such as the ADDW uses an ADD alu op.  Less obvious is
-// that a mov instruction uses an OR op which lets us do a simple copy.
-// 
-// Data has to funnel through the ALU, which sometimes makes for contrived
-// ALU ops.
-//
-picidec  idec (
-   .inst     (inst),
-   .aluasel  (aluasel),
-   .alubsel  (alubsel),
-   .aluop    (aluop),
-   .wwe      (wwe),
-   .fwe      (fwe),
-   .zwe      (zwe),
-   .cwe      (cwe),
-   .bdpol    (bdpol),
-   .option   (isoption),
-   .tris     (istris)
-);
-
-// *********** Debug ****************
-assign	debugw = w;
-assign	debugpc = pc;
-assign	debuginst = inst;
-assign	debugstatus = status;
-
-// *********** REGISTER FILE Addressing ****************
-//
-// We implement the following:
-//    - The 5-bit fsel address is within a "BANK" which is 32 bytes.
-//    - The FSR bits 6:5 are the BANK select, so there are 4 BANKS, a 
-//      total of 128 bytes.  Minus the 8 special registers, that's 
-//      really 120 bytes.
-//    - The INDF register is for indirect addressing.  Referencing INDF
-//      uses FSR as the pointer.  Therefore, using INDF/FSR you address
-//      7-bits of memory.
-// We DO NOT currently implement the PAGE for program (e.g. STATUS register
-// bits 6:5)
-//
-// The fsel address *may* be zero in which case, we are to do indirect
-// addressing, using FSR register as the 8-bit pointer.
-//
-// Otherwise, use the 5-bits of FSEL (from the Instruction itself) and 
-// 2 bank bits from the FSR register (bits 6:5).
-//
-always @(fsel or fsr) begin
-   if (fsel == INDF_ADDRESS) begin
-      // The INDEX register is addressed.  There really is no INDEX register.
-      // Use the FSR as an index, e.g. the FSR contents are the fsel.
-      //
-      fileaddr <= fsr6:0;
-   end
-   else begin
-      // Use FSEL field and status bank select bits
-      //
-      fileaddr <= {fsr6:5, fsel};
-   end
-end
-
-// Write Enable to Register File.  
-// Assert this when the general fwe (write enable to *any* register) is true AND Register File
-//    address range is specified.
-//  
-always @(regfilesel or fwe)
-   regfilewe <= regfilesel & fwe;
-
-// Read Enable (this if nothing else, helps in debug.)
-// Assert if Register File address range is specified AND the ALU is actually using some
-//    data off the SBUS.
-//   
-always @(regfilesel or aluasel or alubsel)
-   regfilere <= regfilesel & ((aluasel == ALUASEL_SBUS) | (alubsel == ALUBSEL_SBUS));
-
-// *********** Address Decodes **************
-//
-// Generate 3 selects: specialsel, regfilesel and expsel
-always @(fileaddr) begin
-   casex (fileaddr)
-      7'bXX00XXX: // The SPECIAL Registers are lower 8 addresses, in ALL BANKS
-         begin
-            specialsel	<= 1'b1;
-            regfilesel	<= 1'b0;
-            expsel	<= 1'b0;
-         end
-      7'b1111111: // EXPANSION Registers are the top (1) addresses
-         begin
-            specialsel	<= 1'b0;
-            regfilesel	<= 1'b0;
-            expsel	<= 1'b1;
-         end
-      default:  // Anything else must be in the Register File
-         begin
-            specialsel	<= 1'b0;
-            regfilesel	<= 1'b1;
-            expsel	<= 1'b0;
-         end
-   endcase
-end
-  
-// *********** SBUS **************
-// The sbus (Source Bus) is the output of a multiplexor that takes
-// inputs from the Register File, and all other special registers
-// and input ports.  The Source Bus then, one of the inputs to the ALU
-
-
-// First MUX selects from all the special regsiters
-//
-always @(fsel or fsr or tmr0 or pc or status
-         or porta or portb or portc or regfileout or ebus
-         or specialsel or regfilesel or expsel) begin
-         
-   // For our current mix of registers and peripherals, only the first 8 addresses
-   // are "special" registers (e.g. not in the Register File).  As more peripheral
-   // registers are added, they must be muxed into this MUX as well.
-   //
-   // We currently prohibit tristates.
-   //
-   //
-   if (specialsel) begin
-      // Special register
-      case (fsel2:0) // synopsys parallel_case full_case
-         3'h0:	sbus <= fsr;
-         3'h1:	sbus <= tmr0;
-         3'h2:	sbus <= pc7:0;
-         3'h3:	sbus <= status;
-         3'h4:	sbus <= fsr;
-         3'h5:	sbus <= porta; // PORTA is an input-only port
-         3'h6:	sbus <= portb; // PORTB is an output-only port
-         3'h7:	sbus <= portc; // PORTC is an output-only port
-      endcase
-   end
-   else begin
-      //
-      // Put whatever address equation is neccessary here.  Remember to remove unnecessary
-      // memory elements from Register File (picregs.v).  It'll still work, but they'd be
-      // wasted flip-flops.
-      //
-      if (expsel) begin
-         sbus <= ebus;
-      end
-      else begin
-         if (regfilesel) begin
-            // Final Priority is Choose the register file
-            sbus <= regfileout;
-         end
-         else begin
-            sbus <= 8'h00;
-         end
-      end
-   end
-end
-
-// ************** DBUS ******
-//  The Destination bus is just the output of the ALU.
-//
-always @(aluout)
-   dbus <= aluout;
-
-always @(dbus)
-   regfilein <= dbus;
-   
-// Drive the ROM address bus straight from the PC
-//
-always @(pc)
-   paddr = pc;
-
-
-// Define sub-signals out of inst
-//
-assign k =     inst7:0;
-assign fsel  = inst4:0;
-assign longk = inst8:0;
-assign d     = inst5;
-assign b     = inst7:5;
-
-// Bit Decoder.
-//
-// Simply take the 3-bit b field in the PIC instruction and create the
-// expanded 8-bit decoder field, which is used as a mask.
-//
-
-
-always @(b) begin
-   case (b)
-      3'b000: bdec <= 8'b00000001;
-      3'b001: bdec <= 8'b00000010;
-      3'b010: bdec <= 8'b00000100;
-      3'b011: bdec <= 8'b00001000;
-      3'b100: bdec <= 8'b00010000;
-      3'b101: bdec <= 8'b00100000;
-      3'b110: bdec <= 8'b01000000;
-      3'b111: bdec <= 8'b10000000;
-   endcase
-end
-
-always @(bdec or bdpol)
-   bd <= bdec ^ bdpol;
-
-// Instruction regsiter usually get the ROM data as its input, but
-// sometimes for branching, the skip signal must cause a NOP.
-//
-always @(posedge clk) begin
-   if (reset) begin
-      inst <= 12'h000;
-   end
-   else begin
-      if (skip == 1'b1) begin
-         inst <= 12'b000000000000; // FORCE NOP
-      end
-      else begin
-         inst <= pdata;
-      end
-   end
-end
-
-// SKIP signal.
-//
-// We want to insert the NOP instruction for the following conditions:
-//    GOTO,CALL and RETLW instructions (All have inst11:10 = 2'b10
-//    BTFSS instruction when aluz is HI  (
-//    BTFSC instruction when aluz is LO
-//
-always @(inst or aluz) begin
-   casex ({inst, aluz})
-      13'b10??_????_????_?:    // A GOTO, CALL or RETLW instructions
-         skip <= 1'b1;
-         
-      13'b0110_????_????_1:    // BTFSC instruction and aluz == 1
-         skip <= 1'b1;
-	
-      13'b0111_????_????_0:    // BTFSS instruction and aluz == 0
-         skip <= 1'b1;
-      
-      13'b0010_11??_????_1:    // DECFSZ instruction and aluz == 1
-         skip <= 1'b1;
-	
-      13'b0011_11??_????_1:    // INCFSZ instruction and aluz == 1
-         skip <= 1'b1;
-      default:
-         skip <= 1'b0;
-   endcase
-end
-
-// 4:1 Data MUX into alua
-//
-//
-always @(aluasel or w or sbus or k or bd) begin
-   case (aluasel)
-      2'b00: alua <= w;
-      2'b01: alua <= sbus;
-      2'b10: alua <= k;
-      2'b11: alua <= bd;
-   endcase
-end
-
-// 4:1 Data MUX into alub
-//
-//
-always @(alubsel or w or sbus or k) begin
-   case (alubsel)
-      2'b00: alub <= w;
-      2'b01: alub <= sbus;
-      2'b10: alub <= k;
-      2'b11: alub <= 8'b00000001;
-   endcase
-end
-
-// W Register
-always @(posedge clk) begin
-   if (reset) begin
-      w <= 8'h00;
-   end
-   else begin
-      if (wwe) begin
-         w <= dbus;
-      end
-   end   
-end
-
-// ************ Writes to various Special Registers (fsel between 0 and 7)
-
-// INDF Register (Register #0)
-//
-//    Not a real register.  This is the Indirect Addressing mode register.
-//    See the regfileaddr logic.
-
-// TMR0 Register (Register #1)
-//
-//    Timer0 is currently only a free-running timer clocked by the main system clock.
-//
-always @(posedge clk) begin
-   if (reset) begin
-      tmr0 <= 8'h00;
-   end
-   else begin
-      // See if the status register is actually being written to
-      if (fwe & specialsel & (fsel == TMR0_ADDRESS)) begin
-         // Yes, so just update the register from the dbus
-         tmr0 <= dbus;
-      end
-      else begin
-         // Mask off the prescaler value based on desired divide ratio.
-         // Whenever this is zero, then that is our divided pulse.  Increment
-         // the final timer value when it's zero.
-         //
-         case (option2:0) // synopsys parallel_case full_case
-            3'b000: if (~|(prescaler & 8'b00000001)) tmr0 <= tmr0 + 1;
-            3'b001: if (~|(prescaler & 8'b00000011)) tmr0 <= tmr0 + 1;
-            3'b010: if (~|(prescaler & 8'b00000111)) tmr0 <= tmr0 + 1;
-            3'b011: if (~|(prescaler & 8'b00001111)) tmr0 <= tmr0 + 1;
-            3'b100: if (~|(prescaler & 8'b00011111)) tmr0 <= tmr0 + 1;
-            3'b101: if (~|(prescaler & 8'b00111111)) tmr0 <= tmr0 + 1;
-            3'b110: if (~|(prescaler & 8'b01111111)) tmr0 <= tmr0 + 1;
-            3'b111: if (~|(prescaler & 8'b11111111)) tmr0 <= tmr0 + 1;
-         endcase            
-      end
-   end
-end
-
-// The prescaler is always counting from 00 to FF
-always @(posedge clk) begin
-   if (reset) begin
-      prescaler <= 8'h00;
-   end
-   else begin
-      // See if the status register is actually being written to
-      prescaler <= prescaler + 1;
-   end
-end
-
-
-// PCL Register (Register #2)
-//
-//    PC Lower 8 bits.  This is handled in the PC section below...
-
-
-// STATUS Register (Register #3)
-//
-always @(posedge clk) begin
-   if (reset) begin
-      status <= 8'h00;
-   end
-   else begin
-      // See if the status register is actually being written to
-      if (fwe & specialsel & (fsel == STATUS_ADDRESS)) begin
-         // Yes, so just update the register from the dbus
-         status <= dbus;
-      end
-      else begin
-         // Update status register on a bit-by-bit basis.
-         //
-         // For the carry and zero flags, each instruction has its own rule as
-         // to whether to update this flag or not.  The instruction decoder is
-         // providing us with an enable for C and Z.  Use this to decide whether
-         // to retain the existing value, or update with the new alu status output.
-         //
-         status <= {
-            status7,			// BIT 7: Undefined.. (maybe use for debugging)
-            status6,			// BIT 6: Program Page, HI bit
-            status5,			// BIT 5: Program Page, LO bit
-            status4,			// BIT 4: Time Out bit (not implemented at this time)
-            status3,			// BIT 3: Power Down bit (not implemented at this time)
-            (zwe) ? aluz : status2,	// BIT 2: Z
-            status1,			// BIT 1: DC
-            (cwe) ? alucout : status0	// BIT 0: C
-         };
-      end
-   end
-end
-
-// FSR Register  (Register #4)
-//            
-always @(posedge clk) begin
-   if (reset) begin
-      fsr <= 8'h00;
-   end
-   else begin
-      // See if the status register is actually being written to
-      if (fwe & specialsel & (fsel == FSR_ADDRESS)) begin
-         fsr <= dbus;
-      end
-   end
-end
-
-// OPTION Register
-//
-// The special OPTION instruction should move W into the OPTION register.
-always @(posedge clk) begin
-   if (reset) begin
-      option <= 8'h00;
-   end
-   else begin
-      if (isoption)
-         option <= dbus;
-   end   
-end
-
-// PORTA Input Port   (Register #5)
-//
-// Register anything on the module's porta input on every single clock.
-//
-always @(posedge clk) begin
-   if (reset) begin
-      porta <= 8'h00;
-   end
-   else begin
-      porta <= portain;
-   end   
-end
-
-// PORTB Output Port  (Register #6)
-always @(posedge clk) begin
-   if (reset) begin
-      portb <= 8'h00;
-   end
-   else begin
-      if (fwe & specialsel & (fsel == PORTB_ADDRESS) & ~istris) begin
-         portb <= dbus;
-      end
-   end   
-end
-
-// Connect the output ports to the register output.
-always @(portb)
-   portbout <= portb;
-   
-// PORTC Output Port  (Register #7)
-always @(posedge clk) begin
-   if (reset) begin
-      portc <= 8'h00;
-   end
-   else begin
-      if (fwe & specialsel & (fsel == PORTC_ADDRESS) & ~istris) begin
-         portc <= dbus;
-      end
-   end   
-end
-
-// Connect the output ports to the register output.
-always @(portc)
-   portcout <= portc;
- 
-// TRIS Registers
-always @(posedge clk) begin
-   if (reset) begin
-      trisa <= 8'hff; // Default is to tristate them
-   end
-   else begin
-      if (fwe & specialsel & (fsel == PORTA_ADDRESS) & istris) begin
-         trisa <= dbus;
-      end
-   end   
-end
-
-always @(posedge clk) begin
-   if (reset) begin
-      trisb <= 8'hff; // Default is to tristate them
-   end
-   else begin
-      if (fwe & specialsel & (fsel == PORTB_ADDRESS) & istris) begin
-         trisb <= dbus;
-      end
-   end   
-end
-
-always @(posedge clk) begin
-   if (reset) begin
-      trisc <= 8'hff; // Default is to tristate them
-   end
-   else begin
-      if (fwe & specialsel & (fsel == PORTC_ADDRESS) & istris) begin
-         trisc <= dbus;
-      end
-   end   
-end
-  
-
-// ********** PC AND STACK *************************
-//
-// There are 4 ways to change the PC.  They are:
-//    GOTO  101k_kkkk_kkkk
-//    CALL  1001_kkkk_kkkk
-//    RETLW 1000_kkkk_kkkk
-//    MOVF  0010_0010_0010  (e.g. a write to reg #2)
-//
-// Remember that the skip instructions work by inserting
-// a NOP instruction or not into program stream and don't
-// change the PC.
-//
-
-// We need pc + 1 in several places, so lets define this incrementor and
-// its output signal it in one place so that we never get redundant adders.
-//
-always @(pc)
-   pcplus1 <= pc + 1;
-   
-parameter	PC_SELECT_PCPLUS1	= 3'b000,
-		PC_SELECT_K             = 3'b001,
-		PC_SELECT_STACK1        = 3'b010,
-		PC_SELECT_STACK2        = 3'b011,
-		PC_SELECT_DBUS          = 3'b100,
-		PC_SELECT_RESET_VECTOR  = 3'b101;
-
-// 8:1 Data MUX into PC 
-always @(posedge clk) begin
-   case (pcinsel) // synopsys parallel_case full_case
-      3'b000:  pc <= pcplus1;
-      3'b001:  pc <= k;
-      3'b010:  pc <= stack1;
-      3'b011:  pc <= stack2;
-      3'b100:  pc <= dbus;
-      3'b101:  pc <= RESET_VECTOR;
-      
-      // Don't really carry about these...
-      3'b110:  pc <= pc;
-      3'b111:  pc <= pc;
-   endcase
-end
-
-// Select for the MUX going into the PC.
-//
-//
-always @(inst or stacklevel or reset) begin
-   if (reset == 1'b1) begin
-      pcinsel <= PC_SELECT_RESET_VECTOR;
-   end
-   else begin
-      casex ({inst, stacklevel})
-         14'b101?_????_????_??: pcinsel <= PC_SELECT_K;		// GOTO
-         14'b1001_????_????_??: pcinsel <= PC_SELECT_K;		// CALL
-         14'b1000_????_????_00: pcinsel <= PC_SELECT_STACK1;	// RETLW
-         14'b1000_????_????_01: pcinsel <= PC_SELECT_STACK1;	// RETLW
-         14'b1000_????_????_10: pcinsel <= PC_SELECT_STACK2;	// RETLW
-         14'b1000_????_????_11: pcinsel <= PC_SELECT_STACK2;	// RETLW
-         14'b0010_0010_0010_??: pcinsel <= PC_SELECT_DBUS;	// MOVF where f=PC
-         default:
-            pcinsel <= PC_SELECT_PCPLUS1;
-      endcase
-   end
-end
-
-
-// Implement STACK1 and STACK2 registers
-//
-// The Stack registers are only fed from the PC itself!
-//
-always @(posedge clk) begin
-   if (reset) begin
-      stack1 <= 9'h000;
-   end
-   else begin
-      // CALL instruction
-      if (inst11:8 == 4'b1001) begin
-         case (stacklevel)
-            2'b00:
-               // No previous CALLs 
-               begin
-                  stack1 <= pc;
-                  $display ("Write to STACK1: %0h", pc);
-               end
-            2'b01:
-               // ONE previous CALL 
-               begin
-                  stack2 <= pc;
-                  $display ("Write to STACK2: %0h", pc);
-               end
-            2'b10:
-               // TWO previous CALLs -- This is illegal on the 16C5X! 
-               begin
-                  $display ("Too many CALLs!!");
-               end
-            2'b11: 
-               begin
-                  $display ("Too many CALLs!!");
-               end
-         endcase
-      end
-   end
-end
-
-// Write to stacklevel
-//
-// The stacklevel register keeps track of the current stack depth.  On this
-// puny processor, there are only 2 levels (you could fiddle with this and
-// increase the stack depth).  There are two stack registers, stack1 and stack2.
-// The stack1 register is used first (e.g. the first time a call is performed),
-// then stack2.  As CALLs are done, stacklevel increments.  Conversely, as
-// RETs are done, stacklevel goes down. 
-
-always @(posedge clk) begin
-   if (reset == 1'b1) begin
-      stacklevel <= 2'b00;  // On reset, there should be no CALLs in progress
-   end
-   else begin
-      casex ({inst, stacklevel})
-         // Call instructions
-         14'b1001_????_????_00: stacklevel <= 2'b01;  // Record 1st CALL
-         14'b1001_????_????_01: stacklevel <= 2'b10;  // Record 2nd CALL
-         14'b1001_????_????_10: stacklevel <= 2'b10;  // Already 2! Ignore
-         14'b1001_????_????_11: stacklevel <= 2'b00;  // {shouldn't happen}
-
-         // Return instructions
-         14'b1000_????_????_00: stacklevel <= 2'b00;  // {shouldn't happen}
-         14'b1000_????_????_01: stacklevel <= 2'b00;  // Go back to no CALL in progress
-         14'b1000_????_????_10: stacklevel <= 2'b01;  // Go back to 1 CALL in progress
-         14'b1000_????_????_11: stacklevel <= 2'b10;  // {shouldn't happen} sort of like, Go back to 2 calls in progress
-         default:
-            stacklevel <= stacklevel;
-      endcase
-   end
-end
-
-
-
-// ************  EXPANSION  *************************
-//
-// The following is an example of customization.
-//
-// Example:  Create a read/write port located at address 7F.  It'll be 8-bits, where
-//           the upper 4 bits are outputs and the lower 4 bits are inputs.  
-//           Use indirect addressing to access it (INDF/FSR).  Just for fun, let's
-//           attach a special loop-back circuit between the outputs and inputs.
-//           Let's attach... say... a 4-bit adder.
-//
-
-reg 3:0	special_peripheral_writeable_bits;
-reg 3:0	special_peripheral_readeable_bits;
-
-// Implement the writeable bits.
-//
-always @(posedge clk) begin
-   if (reset) begin
-      special_peripheral_writeable_bits <= 4'b0000;
-   end
-   else begin
-      if (fwe & expsel & (fileaddr == EXPADDRESS_LILADDER)) begin
-         special_peripheral_writeable_bits <= dbus;
-      end
-   end
-end
-
-// Implement the special peripheral function (the 4-bit adder for this example).
-always @(special_peripheral_writeable_bits) begin
-   special_peripheral_readeable_bits <= special_peripheral_writeable_bits + 1;
-end
-
-// Drive the ebus.  With only one custom address, no more muxing needs to be
-// done, but if there are multiple custom circuits, everyone needs to cooperate
-// and drive ebus properly.
-//
-always @(fileaddr or special_peripheral_readeable_bits) begin
-   if (fileaddr == EXPADDRESS_LILADDER)
-      ebus <= special_peripheral_readeable_bits;
-   else
-      ebus <= 8'hff;
-end
-
-endmodule
-// 
-// SYNTHETIC PIC 2.0                                          4/23/98
-//
-//    This is a synthesizable Microchip 16C57 compatible
-//    microcontroller.  This core is not intended as a high fidelity model of
-//    the PIC, but simply a way to offer a simple processor core to people
-//    familiar with the PIC who also have PIC tools.  
-//
-//    pictest.v  -   top-level testbench (NOT SYNTHESIZABLE)
-//    piccpu.v   -   top-level synthesizable module
-//    picregs.v  -   register file instantiated under piccpu
-//    picalu.v   -   ALU instantiated under piccpu
-//    picidec.v  -   Instruction Decoder instantiated under piccpu
-//    hex2rom.c  -   C program used to translate MPLAB's INTEL HEX output
-//                   into the Verilog $readmemh compatible file
-//    test*.asm  -   (note the wildcard..) Several test programs used
-//                   to help debug the verilog.  I used MPLAB and the simulator
-//                   to develop these programs and get the expected results.
-//                   Then, I ran them on Verilog-XL where they appeared to
-//                   match.
-//
-//    Copyright, Tom Coonan, '97.
-//    Use freely, but not for resale as is.  You may use this in your
-//    own projects as desired.  Just don't try to sell it as is!
-//
-//
-// This is the PIC Instruction Decoder.
-//
-// The 12-bit PIC instruction must result in a set of control
-// signals to the ALU, register write enables and other wires.
-// This is purely combinatorial.  This can physically be
-// implemented as a ROM, or, in this implementation a Verilog
-// casex statement is used to directly synthesize the signals.
-// This approach is more portable, and hopefully much reduction
-// occurs in the equations.
-//
-// The Synthetic PIC Manual contains a table that better shows
-// all the required signals per instruction.  I basically
-// took that table and created the Verilog implementation below.
-//
-
-module picidec (
-	inst,
-	aluasel,
-	alubsel,
-	aluop,
-	wwe,
-	fwe,
-	zwe,
-	cwe,
-	bdpol,
-	option,
-	tris
-);
-
-input  11:0	inst;
-
-output 1:0	aluasel;
-output 1:0	alubsel;
-output 3:0	aluop;
-output		wwe;
-output		fwe;
-output		zwe;
-output		cwe;
-output		bdpol;
-output		option;
-output		tris;
-
-reg 14:0 decodes;
-
-// For reference, the ALU Op codes are:
-//
-//   ADD  0000
-//   SUB  1000
-//   AND  0001
-//   OR   0010
-//   XOR  0011
-//   COM  0100
-//   ROR  0101
-//   ROL  0110
-//   SWAP 0111
-
-assign {	aluasel,	// Select source for ALU A input. 00=W, 01=SBUS, 10=K, 11=BD
-		alubsel,	// Select source for ALU B input. 00=W, 01=SBUS, 10=K, 11="1"
-		aluop,		// ALU Operation (see comments above for these codes)
-		wwe,		// W register Write Enable
-		fwe,		// File Register Write Enable
-		zwe,		// Status register Z bit update
-		cwe,		// Status register Z bit update
-		bdpol,		// Polarity on bit decode vector (0=no inversion, 1=invert)
-		tris,		// Instruction is an TRIS instruction
-		option		// Instruction is an OPTION instruction
-	} = decodes;
-
-// This is a large combinatorial decoder.
-// I use the casex statement.
-
-always @(inst) begin
-	casex (inst)
-		// *** Byte-Oriented File Register Operations
-		//
-		//                                 A  A  ALU  W F Z C B T O
-		//                                 L  L   O   W W W W D R P
-		//                                 U  U   P   E E E E P I T
-		//                                 A  B               O S
-		//                                                    L
-		12'b0000_0000_0000: decodes <= 15'b00_00_0000_0_0_0_0_0_0_0; // NOP
-		12'b0000_001X_XXXX: decodes <= 15'b00_00_0010_0_1_0_0_0_0_0; // MOVWF
-		12'b0000_0100_0000: decodes <= 15'b00_00_0011_1_0_1_0_0_0_0; // CLRW
-		12'b0000_011X_XXXX: decodes <= 15'b00_00_0011_0_1_1_0_0_0_0; // CLRF
-		12'b0000_100X_XXXX: decodes <= 15'b01_00_1000_1_0_1_1_0_0_0; // SUBWF (d=0)
-		12'b0000_101X_XXXX: decodes <= 15'b01_00_1000_0_1_1_1_0_0_0; // SUBWF (d=1)
-		12'b0000_110X_XXXX: decodes <= 15'b01_11_1000_1_0_1_0_0_0_0; // DECF  (d=0)
-		12'b0000_111X_XXXX: decodes <= 15'b01_11_1000_0_1_1_0_0_0_0; // DECF  (d=1)
-		12'b0001_000X_XXXX: decodes <= 15'b00_01_0010_1_0_1_0_0_0_0; // IORWF (d=0)
-		12'b0001_001X_XXXX: decodes <= 15'b00_01_0010_0_1_1_0_0_0_0; // IORWF (d=1)
-		12'b0001_010X_XXXX: decodes <= 15'b00_01_0001_1_0_1_0_0_0_0; // ANDWF (d=0)
-		12'b0001_011X_XXXX: decodes <= 15'b00_01_0001_0_1_1_0_0_0_0; // ANDWF (d=1)
-		12'b0001_100X_XXXX: decodes <= 15'b00_01_0011_1_0_1_0_0_0_0; // XORWF (d=0)
-		12'b0001_101X_XXXX: decodes <= 15'b00_01_0011_0_1_1_0_0_0_0; // XORWF (d=1)
-		12'b0001_110X_XXXX: decodes <= 15'b00_01_0000_1_0_1_1_0_0_0; // ADDWF (d=0)
-		12'b0001_111X_XXXX: decodes <= 15'b00_01_0000_0_1_1_1_0_0_0; // ADDWF (d=1)
-		12'b0010_000X_XXXX: decodes <= 15'b01_01_0010_1_0_1_0_0_0_0; // MOVF  (d=0)
-		12'b0010_001X_XXXX: decodes <= 15'b01_01_0010_0_1_1_0_0_0_0; // MOVF  (d=1)
-		12'b0010_010X_XXXX: decodes <= 15'b01_01_0100_1_0_1_0_0_0_0; // COMF  (d=0)
-		12'b0010_011X_XXXX: decodes <= 15'b01_01_0100_0_1_1_0_0_0_0; // COMF  (d=1)
-		12'b0010_100X_XXXX: decodes <= 15'b01_11_0000_1_0_1_0_0_0_0; // INCF  (d=0)
-		12'b0010_101X_XXXX: decodes <= 15'b01_11_0000_0_1_1_0_0_0_0; // INCF  (d=1)
-		12'b0010_110X_XXXX: decodes <= 15'b01_11_1000_1_0_0_0_0_0_0; // DECFSZ(d=0)
-		12'b0010_111X_XXXX: decodes <= 15'b01_11_1000_0_1_0_0_0_0_0; // DECFSZ(d=1)
-		12'b0011_000X_XXXX: decodes <= 15'b01_01_0101_1_0_0_1_0_0_0; // RRF   (d=0)
-		12'b0011_001X_XXXX: decodes <= 15'b01_01_0101_0_1_0_1_0_0_0; // RRF   (d=1)
-		12'b0011_010X_XXXX: decodes <= 15'b01_01_0110_1_0_0_1_0_0_0; // RLF   (d=0)
-		12'b0011_011X_XXXX: decodes <= 15'b01_01_0110_0_1_0_1_0_0_0; // RLF   (d=1)
-		12'b0011_100X_XXXX: decodes <= 15'b01_01_0111_1_0_0_0_0_0_0; // SWAPF (d=0)
-		12'b0011_101X_XXXX: decodes <= 15'b01_01_0111_0_1_0_0_0_0_0; // SWAPF (d=1)
-		12'b0011_110X_XXXX: decodes <= 15'b01_11_0000_1_0_0_0_0_0_0; // INCFSZ(d=0)
-		12'b0011_111X_XXXX: decodes <= 15'b01_11_0000_0_1_0_0_0_0_0; // INCFSZ(d=1)
-
-		// *** Bit-Oriented File Register Operations
-                //
-		//                                 A  A  ALU  W F Z C B T O
-		//                                 L  L   O   W W W W D R P
-		//                                 U  U   P   E E E E P I T
-		//                                 A  B               O S
-		//                                                    L
-		12'b0100_XXXX_XXXX: decodes <= 15'b11_01_0001_0_1_0_0_1_0_0; // BCF
-		12'b0101_XXXX_XXXX: decodes <= 15'b11_01_0010_0_1_0_0_0_0_0; // BSF
-		12'b0110_XXXX_XXXX: decodes <= 15'b11_01_0001_0_0_0_0_0_0_0; // BTFSC
-		12'b0111_XXXX_XXXX: decodes <= 15'b11_01_0001_0_0_0_0_0_0_0; // BTFSS
-
-		// *** Literal and Control Operations
-                //
-		//                                 A  A  ALU  W F Z C B T O
-		//                                 L  L   O   W W W W D R P
-		//                                 U  U   P   E E E E P I T
-		//                                 A  B               O S
-		//                                                    L
-		12'b0000_0000_0010: decodes <= 15'b00_00_0010_0_1_0_0_0_0_1; // OPTION
-		12'b0000_0000_0011: decodes <= 15'b00_00_0000_0_0_0_0_0_0_0; // SLEEP
-		12'b0000_0000_0100: decodes <= 15'b00_00_0000_0_0_0_0_0_0_0; // CLRWDT
-		12'b0000_0000_0101: decodes <= 15'b00_00_0000_0_1_0_0_0_1_0; // TRIS 5
-		12'b0000_0000_0110: decodes <= 15'b00_00_0010_0_1_0_0_0_1_0; // TRIS 6
-		12'b0000_0000_0111: decodes <= 15'b00_00_0010_0_1_0_0_0_1_0; // TRIS 7
-                //
-		//                                 A  A  ALU  W F Z C B T O
-		//                                 L  L   O   W W W W D R P
-		//                                 U  U   P   E E E E P I T
-		//                                 A  B               O S
-		//                                                    L
-		12'b1000_XXXX_XXXX: decodes <= 15'b10_10_0010_1_0_0_0_0_0_0; // RETLW
-		12'b1001_XXXX_XXXX: decodes <= 15'b10_10_0010_0_0_0_0_0_0_0; // CALL
-		12'b101X_XXXX_XXXX: decodes <= 15'b10_10_0010_0_0_0_0_0_0_0; // GOTO
-		12'b1100_XXXX_XXXX: decodes <= 15'b10_10_0010_1_0_0_0_0_0_0; // MOVLW
-		12'b1101_XXXX_XXXX: decodes <= 15'b00_10_0010_1_0_1_0_0_0_0; // IORLW
-		12'b1110_XXXX_XXXX: decodes <= 15'b00_10_0001_1_0_1_0_0_0_0; // ANDLW
-		12'b1111_XXXX_XXXX: decodes <= 15'b00_10_0011_1_0_1_0_0_0_0; // XORLW
-
-		default:
-			decodes <= 15'b00_00_0000_0_0_0_0_0_0_0;
-	endcase
-end
-
-endmodule
-
-
-// 
-// SYNTHETIC PIC 2.0                                          4/23/98
-//
-//    This is a synthesizable Microchip 16C57 compatible
-//    microcontroller.  This core is not intended as a high fidelity model of
-//    the PIC, but simply a way to offer a simple processor core to people
-//    familiar with the PIC who also have PIC tools.  
-//
-//    pictest.v  -   top-level testbench (NOT SYNTHESIZABLE)
-//    piccpu.v   -   top-level synthesizable module
-//    picregs.v  -   register file instantiated under piccpu
-//    picalu.v   -   ALU instantiated under piccpu
-//    picidec.v  -   Instruction Decoder instantiated under piccpu
-//    hex2rom.c  -   C program used to translate MPLAB's INTEL HEX output
-//                   into the Verilog $readmemh compatible file
-//    test*.asm  -   (note the wildcard..) Several test programs used
-//                   to help debug the verilog.  I used MPLAB and the simulator
-//                   to develop these programs and get the expected results.
-//                   Then, I ran them on Verilog-XL where they appeared to
-//                   match.
-//
-//    Copyright, Tom Coonan, '97.
-//    Use freely, but not for resale as is.  You may use this in your
-//    own projects as desired.  Just don't try to sell it as is!
-//
-//
-
-//`define DEBUG_SHOWREADS
-//`define DEBUG_SHOWWRITES
-
-// Memory Map:
-//
-// PIC Data Memory addressing is complicated.  See the Data Book for full explanation..
-//
-// Basically, each BANK contains 32 locations.  The lowest 16 locations in ALL Banks
-// are really all mapped to the same bank (bank #0).  The first 8 locations are the Special
-// registers like the STATUS and PC registers.  The upper 16 words in each bank, really are
-// unique to each bank.  The smallest PIC (16C54) only has the one bank #0.
-//
-// So, as a programmer, what you get is this.  No matter what bank you are in (FSR6:5)
-// you always have access to your special registers and also to registers 8-15.  You can
-// change to a 1 of 4 banks by setting FSR6:5 and get 4 different sets of registers
-// 16-31.
-//
-// For numbering purposes, I've numbered the registers as if they are one linear memory
-// space, just like in the Data Book (see Figure 4-15 "Direct/Indirect Addressing").
-// So, the unique 16 registers in bank #1 are named r48 - r63 (I use decimal).  The
-// unique registers in bank #3 are therefore r112 - r127.  There is no r111 because,
-// remember, the lower 16 registers each each bank are all reall the same registers 0-15.
-// 
-// Confused?!  The Data Book explains it better than I can.
-//
-//   bank location 
-//     XX 00rrr  -  The special registers are not implemented in this register file.
-//     XX 01rrr  -  The 8 common words, just above the Special Regs, same for all Banks
-//     00 1rrrr  -  The 16 words unique to Bank #0
-//     01 1rrrr  -  The 16 words unique to Bank #1
-//     10 1rrrr  -  The 16 words unique to Bank #2
-//     11 1rrrr  -  The 16 words unique to Bank #3
-//
-//  So, 
-//     Special Regs are location4:3 == 00
-//     Common Regs are  location4:3 == 01
-//     Words in banks   location4   == 1
-// 
-//
-//  I had problems trying to use simple register file declarations that
-//  would always, always work right, were synthesizable and allowed
-//  me to easily remove locations from the memory space.  SOOOooo... I
-//  did the brute force thing and enumerated all the locations..
-//
-//  Much larger spaces will probably need a RAM and whatever I do would need
-//  custom hacking anyway..  I don't see an obvious solution to all this, but
-//  welcome suggestions..
-//
-module picregs (clk, reset, we, re, bank, location, din, dout);
-
-input		clk;
-input		reset;
-input		we;
-input		re;
-input  1:0	bank;		// Bank 0,1,2,3
-input  4:0	location;	// Location
-input  7:0	din;		// Input 
-output 7:0	dout;		// Output 
-
-//parameter	MAX_ADDRESS = 127;
-
-reg 7:0	dout;
-
-integer index;
-
-// Declare the major busses in and out of each block.
-//
-reg 7:0	commonblockout;	// Data Memory common across all banks
-reg 7:0	highblock0out;	// Upper 16 bytes in BANK #0
-reg 7:0	highblock1out;	// Upper 16 bytes in BANK #1
-reg 7:0	highblock2out;	// Upper 16 bytes in BANK #2
-reg 7:0	highblock3out;	// Upper 16 bytes in BANK #3
-
-reg 7:0	commonblockin;	// Data Memory common across all banks
-reg 7:0	highblock0in;	// Upper 16 bytes in BANK #0
-reg 7:0	highblock1in;	// Upper 16 bytes in BANK #1
-reg 7:0	highblock2in;	// Upper 16 bytes in BANK #2
-reg 7:0	highblock3in;	// Upper 16 bytes in BANK #3
-
-reg		commonblocksel;	// Select
-reg		highblock0sel;	// Select
-reg		highblock1sel;	// Select
-reg		highblock2sel;	// Select
-reg		highblock3sel;	// Select
-// synopsys translate_off
-integer cycle_counter;
-initial cycle_counter = 0;
-always @(negedge clk) begin
-   if (re) begin
-`ifdef DEBUG_SHOWREADS   
-      $display ("%0d Read:  data = %0h(hex), from bank #%0d(dec) location %0h", cycle_counter, dout, bank, location);
-`endif
-   end
-   if (we) begin
-`ifdef DEBUG_SHOWWRITES   
-      $display ("%0d Write: data = %0h(hex), to   bank #%0d(dec) location %0h", cycle_counter, din, bank, location);
-`endif
-   end
-   if (~reset) cycle_counter = cycle_counter + 1;
-end  
-// synopsys translate_on
-
-// READ the Register File
-//
-always @(bank or location or re
-		or commonblockout 
-		or highblock0out 
-		or highblock1out 
-		or highblock2out 
-		or highblock3out) begin
-   if (re) begin		
-      if (location4:3 == 2'b01) begin
-         // This is the lower 8 words, common to all banks, just above special registers
-         dout <= commonblockout;	// Access to first 8 locations past Special Registers 
-      end
-      else begin
-         if (location4) begin
-            // Address is in the upper 16 words on one of the 4 banks
-            case (bank) // synopsys full_case parallel_case
-               2'b00:  dout <= highblock0out;	// Upper 16 words of Bank #0
-               2'b01:  dout <= highblock1out;	// Upper 16 words of Bank #1
-               2'b10:  dout <= highblock2out;	// Upper 16 words of Bank #2
-               2'b11:  dout <= highblock3out;	// Upper 16 words of Bank #3
-            endcase
-         end
-         else begin
-            dout <= 8'hff;
-         end
-      end
-   end
-   else begin
-      dout <= 8'hff;
-   end
-end
-
-// Initial Write logic.
-//
-// Generate the specific write enables based on the PIC's bank/location rules.
-// The individual memory blocks will do the actual synchronous write.
-//
-always @(we or bank or location or reset) begin
-   if (reset) begin
-      commonblocksel <= 1'b0;
-      highblock0sel  <= 1'b0;
-      highblock1sel  <= 1'b0;
-      highblock2sel  <= 1'b0;
-      highblock3sel  <= 1'b0;
-   end
-   else begin
-      if (we) begin
-         if (location4:3 == 2'b01) begin
-            // This is the lower 8 words, common to all banks, just above special registers
-            commonblocksel <= 1'b1;
-            highblock0sel  <= 1'b0;
-            highblock1sel  <= 1'b0;
-            highblock2sel  <= 1'b0;
-            highblock3sel  <= 1'b0;
-         end
-         else begin
-            if (location4) begin
-               // Address is in the upper 16 words on one of the 4 banks
-               commonblocksel <= 1'b0;
-               case (bank) // synopsys full_case parallel_case
-                  2'b00:  {highblock0sel, highblock1sel, highblock2sel, highblock3sel} <= 4'b1000; // Upper 16 words of Bank #0
-                  2'b01:  {highblock0sel, highblock1sel, highblock2sel, highblock3sel} <= 4'b0100; // Upper 16 words of Bank #1
-                  2'b10:  {highblock0sel, highblock1sel, highblock2sel, highblock3sel} <= 4'b0010; // Upper 16 words of Bank #2
-                  2'b11:  {highblock0sel, highblock1sel, highblock2sel, highblock3sel} <= 4'b0001; // Upper 16 words of Bank #3
-               endcase
-            end
-            else begin
-               commonblocksel <= 1'b0;
-               highblock0sel  <= 1'b0;
-               highblock1sel  <= 1'b0;
-               highblock2sel  <= 1'b0;
-               highblock3sel  <= 1'b0;
-            end
-         end
-      end
-      else begin
-         commonblocksel <= 1'b0;
-         highblock0sel  <= 1'b0;
-         highblock1sel  <= 1'b0;
-         highblock2sel  <= 1'b0;
-         highblock3sel  <= 1'b0;
-      end
-   end
-end
-
-// *** Buses feeding the memory blocks are driven directly from din.
-
-always @(din)
-   commonblockin <= din;
-
-always @(din)
-   highblock0in <= din;
-
-always @(din)
-   highblock1in <= din;
-
-always @(din)
-   highblock2in <= din;
-
-always @(din)
-   highblock3in <= din;
-
-// ****************** Common Block *************
-
-reg 7:0	r8, r9, r10, r11, r12, r13, r14, r15;
-
-// Read from common block
-always @(location or
-		r8 or r9 or r10 or r11 or r12 or r13 or r14 or r15) begin
-   case (location2:0)
-      3'h0: commonblockout <= r8;
-      3'h1: commonblockout <= r9;
-      3'h2: commonblockout <= r10;
-      3'h3: commonblockout <= r11;
-      3'h4: commonblockout <= r12;
-      3'h5: commonblockout <= r13;
-      3'h6: commonblockout <= r14;
-      3'h7: commonblockout <= r15;
-   endcase
-end
-      
-// Write to common block
-always @(posedge clk) begin
-   if (we & commonblocksel) begin
-      case (location2:0)
-         3'h0: r8  <= commonblockin;
-         3'h1: r9  <= commonblockin;
-         3'h2: r10 <= commonblockin;
-         3'h3: r11 <= commonblockin;
-         3'h4: r12 <= commonblockin;
-         3'h5: r13 <= commonblockin;
-         3'h6: r14 <= commonblockin;
-         3'h7: r15 <= commonblockin;
-      endcase
-   end
-end
-
-// **************** Highblock0 ****************
-
-reg 7:0	r16, r17, r18, r19, r20, r21, r22, r23;
-reg 7:0	r24, r25, r26, r27, r28, r29, r30, r31;
-
-// Read from high block bank0
-always @(location or
-		r16 or r17 or r18 or r19 or r20 or r21 or r22 or r23 or
-		r24 or r25 or r26 or r27 or r28 or r29 or r30 or r31
-) begin
-   case (location3:0)
-      4'h0: highblock0out <= r16;
-      4'h1: highblock0out <= r17;
-      4'h2: highblock0out <= r18;
-      4'h3: highblock0out <= r19;
-      4'h4: highblock0out <= r20;
-      4'h5: highblock0out <= r21;
-      4'h6: highblock0out <= r22;
-      4'h7: highblock0out <= r23;
-      4'h8: highblock0out <= r24;
-      4'h9: highblock0out <= r25;
-      4'hA: highblock0out <= r26;
-      4'hB: highblock0out <= r27;
-      4'hC: highblock0out <= r28;
-      4'hD: highblock0out <= r29;
-      4'hE: highblock0out <= r30;
-      4'hF: highblock0out <= r31;
-   endcase
-end
-      
-// Write to high block bank 0
-always @(posedge clk) begin
-   if (we & highblock0sel) begin
-      case (location3:0)
-         4'h0: r16 <= highblock0in;
-         4'h1: r17 <= highblock0in;
-         4'h2: r18 <= highblock0in;
-         4'h3: r19 <= highblock0in;
-         4'h4: r20 <= highblock0in;
-         4'h5: r21 <= highblock0in;
-         4'h6: r22 <= highblock0in;
-         4'h7: r23 <= highblock0in;
-         4'h8: r24 <= highblock0in;
-         4'h9: r25 <= highblock0in;
-         4'hA: r26 <= highblock0in;
-         4'hB: r27 <= highblock0in;
-         4'hC: r28 <= highblock0in;
-         4'hD: r29 <= highblock0in;
-         4'hE: r30 <= highblock0in;
-         4'hF: r31 <= highblock0in;
-      endcase
-   end
-end
-
-// **************** Highblock1 ****************
-
-reg 7:0	r48, r49, r50, r51, r52, r53, r54, r55;
-reg 7:0	r56, r57, r58, r59, r60, r61, r62, r63;
-
-// Read
-always @(location or
-		r48 or r49 or r50 or r51 or r52 or r53 or r54 or r55 or
-		r56 or r57 or r58 or r59 or r60 or r61 or r62 or r63
-) begin
-   case (location3:0)
-      4'h0: highblock1out <= r48;
-      4'h1: highblock1out <= r49;
-      4'h2: highblock1out <= r50;
-      4'h3: highblock1out <= r51;
-      4'h4: highblock1out <= r52;
-      4'h5: highblock1out <= r53;
-      4'h6: highblock1out <= r54;
-      4'h7: highblock1out <= r55;
-      4'h8: highblock1out <= r56;
-      4'h9: highblock1out <= r57;
-      4'hA: highblock1out <= r58;
-      4'hB: highblock1out <= r59;
-      4'hC: highblock1out <= r60;
-      4'hD: highblock1out <= r61;
-      4'hE: highblock1out <= r62;
-      4'hF: highblock1out <= r63;
-   endcase
-end
-
-// Write
-always @(posedge clk) begin
-   if (we & highblock1sel) begin
-      case (location3:0)
-         4'h0: r48 <= highblock1in;
-         4'h1: r49 <= highblock1in;
-         4'h2: r50 <= highblock1in;
-         4'h3: r51 <= highblock1in;
-         4'h4: r52 <= highblock1in;
-         4'h5: r53 <= highblock1in;
-         4'h6: r54 <= highblock1in;
-         4'h7: r55 <= highblock1in;
-         4'h8: r56 <= highblock1in;
-         4'h9: r57 <= highblock1in;
-         4'hA: r58 <= highblock1in;
-         4'hB: r59 <= highblock1in;
-         4'hC: r60 <= highblock1in;
-         4'hD: r61 <= highblock1in;
-         4'hE: r62 <= highblock1in;
-         4'hF: r63 <= highblock1in;
-      endcase
-   end
-end
-      
-
-// **************** Highblock2 ****************
-
-reg 7:0	r80, r81, r82, r83, r84, r85, r86, r87;
-reg 7:0	r88, r89, r90, r91, r92, r93, r94, r95;
-
-// Read
-always @(location or
-		r80 or r81 or r82 or r83 or r84 or r85 or r86 or r87 or
-		r88 or r89 or r90 or r91 or r92 or r93 or r94 or r95
-) begin
-   case (location3:0)
-      4'h0: highblock2out <= r80;
-      4'h1: highblock2out <= r81;
-      4'h2: highblock2out <= r82;
-      4'h3: highblock2out <= r83;
-      4'h4: highblock2out <= r84;
-      4'h5: highblock2out <= r85;
-      4'h6: highblock2out <= r86;
-      4'h7: highblock2out <= r87;
-      4'h8: highblock2out <= r88;
-      4'h9: highblock2out <= r89;
-      4'hA: highblock2out <= r90;
-      4'hB: highblock2out <= r91;
-      4'hC: highblock2out <= r92;
-      4'hD: highblock2out <= r93;
-      4'hE: highblock2out <= r94;
-      4'hF: highblock2out <= r95;
-   endcase
-end
-
-// Write
-always @(posedge clk) begin
-   if (we & highblock2sel) begin
-      case (location3:0)
-         4'h0: r80 <= highblock2in;
-         4'h1: r81 <= highblock2in;
-         4'h2: r82 <= highblock2in;
-         4'h3: r83 <= highblock2in;
-         4'h4: r84 <= highblock2in;
-         4'h5: r85 <= highblock2in;
-         4'h6: r86 <= highblock2in;
-         4'h7: r87 <= highblock2in;
-         4'h8: r88 <= highblock2in;
-         4'h9: r89 <= highblock2in;
-         4'hA: r90 <= highblock2in;
-         4'hB: r91 <= highblock2in;
-         4'hC: r92 <= highblock2in;
-         4'hD: r93 <= highblock2in;
-         4'hE: r94 <= highblock2in;
-         4'hF: r95 <= highblock2in;
-      endcase
-   end
-end
-
-// **************** Highblock3 ****************
-
-// *** The Following Registers are removed because of CUSTOM Hardware (see piccpu.v) **
-//
-//    r129 (or 7E)
-//
-// **********
-reg 7:0	r112, r113, r114, r115, r116, r117, r118, r119;
-reg 7:0	r120, r121, r122, r123, r124, r125, r126 ;// /*, r127*/ ;
-
-// Read
-always @(location or
-		r112 or r113 or r114 or r115 or r116 or r117 or r118 or r119 or
-		r120 or r121 or r122 or r123 or r124 or r125 or r126 // /* or r127 */
-) begin
-   case (location3:0)
-      4'h0: highblock3out <= r112;
-      4'h1: highblock3out <= r113;
-      4'h2: highblock3out <= r114;
-      4'h3: highblock3out <= r115;
-      4'h4: highblock3out <= r116;
-      4'h5: highblock3out <= r117;
-      4'h6: highblock3out <= r118;
-      4'h7: highblock3out <= r119;
-      4'h8: highblock3out <= r120;
-      4'h9: highblock3out <= r121;
-      4'hA: highblock3out <= r122;
-      4'hB: highblock3out <= r123;
-      4'hC: highblock3out <= r124;
-      4'hD: highblock3out <= r125;
-      4'hE: highblock3out <= r126;
-      4'hF: highblock3out <= 8'hff ;// /* r127*/ ;
-   endcase
-end
-
-// Write
-always @(posedge clk) begin
-   if (we & highblock3sel) begin
-      case (location3:0)
-         4'h0: r112 <= highblock3in;
-         4'h1: r113 <= highblock3in;
-         4'h2: r114 <= highblock3in;
-         4'h3: r115 <= highblock3in;
-         4'h4: r116 <= highblock3in;
-         4'h5: r117 <= highblock3in;
-         4'h6: r118 <= highblock3in;
-         4'h7: r119 <= highblock3in;
-         4'h8: r120 <= highblock3in;
-         4'h9: r121 <= highblock3in;
-         4'hA: r122 <= highblock3in;
-         4'hB: r123 <= highblock3in;
-         4'hC: r124 <= highblock3in;
-         4'hD: r125 <= highblock3in;
-         4'hE: r126 <= highblock3in;
-         4'hF: ; // /* r127 <= highblock3in */;
-      endcase
-   end
-end
-
-// synopsys translate_off
-`define CLEAR_MEMORY
-`ifdef CLEAR_MEMORY
-initial
-begin
-   $display ("Clearing SRAM.");
-   clear_memory;
-end
-task clear_memory;
-begin
-   // Common registers
-   r8  = 0;
-   r9  = 0;
-   r10 = 0;
-   r11 = 0;
-   r12 = 0;
-   r13 = 0;
-   r14 = 0;
-   r15 = 0;
-
-   // Bank #0
-   r16 = 0;
-   r17 = 0;
-   r18 = 0;
-   r19 = 0;
-   r20 = 0;
-   r21 = 0;
-   r22 = 0;
-   r23 = 0;
-   r24 = 0;
-   r25 = 0;
-   r26 = 0;
-   r27 = 0;
-   r28 = 0;
-   r29 = 0;
-   r30 = 0;
-   r31 = 0;
-
-   // Bank #1
-   r48 = 0;
-   r49 = 0;
-   r50 = 0;
-   r51 = 0;
-   r52 = 0;
-   r53 = 0;
-   r54 = 0;
-   r55 = 0;
-   r56 = 0;
-   r57 = 0;
-   r58 = 0;
-   r59 = 0;
-   r60 = 0;
-   r61 = 0;
-   r62 = 0;
-   r63 = 0;
-
-   // Bank #2
-   r80 = 0;
-   r94 = 0;
-
-   // Bank #3
-   r112 = 0;
-   r126 = 0;
-  
-end
-endtask
-`endif
-// synopsys translate_on 
-endmodule
-// 
-// SYNTHETIC PIC 2.0                                          4/23/98
-//
-//    This is a synthesizable Microchip 16C57 compatible
-//    microcontroller.  This core is not intended as a high fidelity model of
-//    the PIC, but simply a way to offer a simple processor core to people
-//    familiar with the PIC who also have PIC tools.  
-//
-//    pictest.v  -   top-level testbench (NOT SYNTHESIZABLE)
-//    piccpu.v   -   top-level synthesizable module
-//    picregs.v  -   register file instantiated under piccpu
-//    picalu.v   -   ALU instantiated under piccpu
-//    picidec.v  -   Instruction Decoder instantiated under piccpu
-//    hex2rom.c  -   C program used to translate MPLAB's INTEL HEX output
-//                   into the Verilog $readmemh compatible file
-//    test*.asm  -   (note the wildcard..) Several test programs used
-//                   to help debug the verilog.  I used MPLAB and the simulator
-//                   to develop these programs and get the expected results.
-//                   Then, I ran them on Verilog-XL where they appeared to
-//                   match.
-//
-//    Copyright, Tom Coonan, '97.
-//    Use freely, but not for resale as is.  You may use this in your
-//    own projects as desired.  Just don't try to sell it as is!
-//
-//
-`timescale 1ns / 10ps
-
-module pictest;
-
-// Select which test to run HERE..
-parameter	TEST_NUMBER = 9;
-
-// *** Testing variables
-// Debug flags.
-integer		dbg_showporta;	// Are set in an 'initial' for default values, 
-integer		dbg_showportb;	//    override in specific tests...
-integer		dbg_showportc;	// Setting to 1 will cause variable to be displayed.
-integer		dbg_showinst;
-integer		dbg_showrom;
-integer		dbg_showw;
-integer		dbg_showpc;
-
-// cycles counter variables
-integer		dbg_showcycles;	// Set to 1 to see cycles
-integer		dbg_limitcycles;// Set to one to enable maxcycles check
-integer		dbg_maxcycles;	// Limit simulation to some number of cycles.
-integer		cycles;		// Cycles counter.
-
-
-
-// *** Interface to the PICCPU
-reg		clk;
-reg		reset;
-reg  7:0	porta;
-wire 7:0	portb;
-wire 7:0	portc;
-
-reg  11:0	rom0:511;
-wire 8:0	romaddr;
-reg  11:0	romdata;
-
-// ROM Interface
-always @(romaddr) begin
-   romdata = romromaddr;
-end
-
-reg 7:0	last_debugw;
-reg 8:0	last_debugpc;
-reg 11:0	last_debuginst;
-reg 7:0	last_debugstatus;
-wire 7:0	debugw;
-wire 8:0	debugpc;
-wire 11:0	debuginst;
-wire 7:0	debugstatus;
-
-// Instantiate one PICCPU to be tested.
-piccpu piccpu_inst (
-   .clk		(clk),
-   .reset	(reset),
-   .paddr	(romaddr),
-   .pdata	(romdata),
-   .portain	(porta),
-   .portbout	(portb),
-   .portcout	(portc),
-   .debugw	(debugw),
-   .debugpc	(debugpc),
-   .debuginst	(debuginst),
-   .debugstatus	(debugstatus)
-);
-
-// Capture some data
-initial begin
-   $dumpfile ("pic.vcd");
-   $dumpvars (0, pictest);
-end
-
-// Reset
-initial begin
-   reset = 1;
-   #200;
-   reset = 0;
-end
-
-  
-// Drive the clock input
-initial begin
-   clk  = 0;
-   forever begin
-      #50 clk = 1;
-      #50 clk = 0;
-   end
-end
-
-// Debug defaults.  Override in individual test tasks.
-//
-initial begin
-   dbg_showporta  = 0;
-   dbg_showportb  = 0;
-   dbg_showportc  = 0;
-   dbg_showinst   = 0;
-   dbg_showrom    = 0;
-   dbg_showw      = 0;
-   dbg_showpc     = 0;
-   dbg_showcycles = 0;
-   
-   dbg_limitcycles = 1;
-   dbg_maxcycles   = 50000;
-end
-
-// Call the appropriate test task based on the TEST_NUMBER parameter set at top.
-//
-initial begin
-   case (TEST_NUMBER)
-      1: test1;
-      2: test2;
-      3: test3;
-      4: test4;
-      5: test5;
-      6: test6;
-      7: test7;
-      8: test8;
-      9: test9;
-      default: 
-         begin
-            $display ("ERROR: Unknown Test Number: %0d", TEST_NUMBER);
-            $finish;
-         end
-   endcase
-end
-
-task test1;
-begin
-   $display ("SYNTHETIC PIC 2.0.  This is TEST #1");
-   #1;
-   
-   // Only Watch Port B
-   dbg_showportb  = 1;
-   dbg_showcycles = 1;
-
-   $readmemh ("TEST1.ROM", rom);
-   dbg_limitcycles = 1;
-   dbg_maxcycles   = 500;
-end
-endtask
-
-task test2;
-begin
-   $display ("SYNTHETIC PIC 2.0.  This is TEST #2");
-   #1;
-
-   // Only Watch Port B
-   dbg_showportb = 1;
-
-   $readmemh ("TEST2.ROM", rom);
-   dbg_limitcycles = 1;
-   dbg_maxcycles = 500;
-end
-endtask
-
-task test3;
-begin
-   $display ("SYNTHETIC PIC 2.0.  This is TEST #3");
-   #1;
-
-   // Only Watch Port B
-   dbg_showportb = 1;
-
-   $readmemh ("TEST3.ROM", rom);
-   dbg_limitcycles = 1;
-   dbg_maxcycles = 500;
-end
-endtask
-
-task test4;
-begin
-   $display ("SYNTHETIC PIC 2.0.  This is TEST #4");
-   #1;
-
-   // Only Watch Port B
-   dbg_showportb = 1;
-
-   $readmemh ("TEST4.ROM", rom);
-   dbg_limitcycles = 1;
-   dbg_maxcycles = 500;
-end
-endtask
-
-task test5;
-begin
-   $display ("SYNTHETIC PIC 2.0.  This is TEST #5");
-   #1;
-
-   // Only Watch Port B
-   dbg_showportb = 1;
-
-   $readmemh ("TEST5.ROM", rom);
-   dbg_limitcycles = 1;
-   dbg_maxcycles = 500;
-end
-endtask
-
-task test6;
-begin
-   $display ("SYNTHETIC PIC 2.0.  This is TEST #6");
-   #1;
-
-   // Watch Port B and C
-   dbg_showportb = 1;
-   dbg_showportc = 1;
-   dbg_limitcycles = 0;
-
-   $readmemh ("TEST6.ROM", rom);
-   #200;
-   
-   repeat (20) begin
-      porta = $random;
-      #10000;
-   end
-   
-   $finish;
-end
-endtask
-
-task test7;
-begin
-   $display ("SYNTHETIC PIC 2.0.  This is TEST #7");
-   #1;
-
-   // Only Watch Port B
-   dbg_showportb = 1;
-
-   $readmemh ("TEST7.ROM", rom);
-   dbg_limitcycles = 1;
-   dbg_maxcycles = 500;
-end
-endtask
-
-task test8;
-begin
-   $display ("SYNTHETIC PIC 2.0.  This is TEST #8");
-   #1;
-
-   // Watch All ports
-   dbg_showporta = 1;
-   dbg_showportb = 1;
-   dbg_showportc = 1;
-
-   $readmemh ("TEST8.ROM", rom);
-   dbg_limitcycles = 1;
-   dbg_maxcycles = 500;
-end
-endtask
-
-task test9;
-begin
-   $display ("SYNTHETIC PIC 2.0.  This is TEST #9");
-   #1;
-
-   // Watch All ports
-   dbg_showportb = 1;
-   dbg_showportc = 1;
-
-   $readmemh ("TEST9.ROM", rom);
-   dbg_limitcycles = 1;
-   dbg_maxcycles = 2000;
-end
-endtask
-
-// ******** END Of TEST TASKS
-
-// Cycles counter
-//
-initial begin
-   cycles = 0;
-   #1;
-   // Don't start counting until after reset.
-   @(negedge reset);
-   
-   forever begin
-      @(posedge clk);
-      cycles = cycles + 1;
-      if ((cycles % 256) == 0) begin
-         if (dbg_showcycles) begin
-            $display ("#Cycles = %0d", cycles);
-         end
-      end
-   
-      if (dbg_limitcycles) begin
-         if (cycles > dbg_maxcycles) begin
-            $display ("Maximum cycles (%0d) Exceeded.  Halting simulation.", dbg_maxcycles);
-            $finish;
-         end
-      end
-   end
-end
-
-always @(romaddr) begin
-   if (dbg_showrom) 
-      $display ("ROM Address = %h, Data = %h", romaddr, romdata);
-end
-
-always @(porta) begin
-   if (dbg_showporta)
-      $display ("porta changes to: %h", porta);
-end
-
-always @(portb) begin
-   if (dbg_showportb)
-      $display ("portb changes to: %h", portb);
-end
-
-always @(portc) begin
-   if (dbg_showportc)
-      $display ("portc changes to: %h", portc);
-end
-
-initial begin
-   if (dbg_showw) begin
-      forever begin
-         @(negedge clk);
-         if (debugw != last_debugw) begin
-            $display ("W = %0h", debugw);
-         end
-         last_debugw = debugw;
-      end
-   end
-end
-
-initial begin
-   if (dbg_showpc) begin
-      forever begin
-         @(negedge clk);
-         $display ("PC = %0h", debugpc);
-      end
-   end
-end
-
-
-
-reg 11:0 last_pc;
-
-always @(posedge clk) begin
-   last_pc = debugpc;
-end
-
-initial begin
-   if (dbg_showinst) begin
-      forever begin
-        @(negedge clk);
-
-	if (debuginst11:0 == 12'b0000_0000_0000) begin
-		$display ("%h NOP", last_pc);
-	end
-	else if (debuginst11:5 == 7'b0000_001) begin
-		$display ("%h MOVWF  f=0x%0h", last_pc, debuginst4:0);
-	end
-	else if (debuginst == 12'b0000_0100_0000) begin
-		$display ("%h CLRW", last_pc);
-	end
-	else if (debuginst11:5 == 7'b0000_011) begin
-		$display ("%h CLRF  f=0x%0h", last_pc, debuginst4:0);
-	end
-	else if (debuginst11:6 == 7'b0000_10) begin
-		if (piccpu_inst.d == 0)	$display ("%h SUBWF  f=0x%0h, W", last_pc, debuginst4:0);
-		else       	$display ("%h SUBWF  f=0x%0h, f", last_pc, debuginst4:0);
-	end
-
-	else if (debuginst11:6 == 7'b0000_11) begin
-		if (piccpu_inst.d == 0)	$display ("%h DECF  f=0x%0h, W", last_pc, debuginst4:0);
-		else       	$display ("%h DECF  f=0x%0h, f", last_pc, debuginst4:0);
-	end
-	else if (debuginst11:6 == 7'b0001_00) begin
-		if (piccpu_inst.d == 0)	$display ("%h IORWF  f=0x%0h, W", last_pc, debuginst4:0);
-		else       	$display ("%h IORWF  f=0x%0h, f", last_pc, debuginst4:0);
-	end
-	else if (debuginst11:6 == 7'b0001_01) begin
-		if (piccpu_inst.d == 0)	$display ("%h ANDWF  f=0x%0h, W", last_pc, debuginst4:0);
-		else       	$display ("%h ANDWF  f=0x%0h, f", last_pc, debuginst4:0);
-	end
-	else if (debuginst11:6 == 7'b0001_10) begin
-		if (piccpu_inst.d == 0)	$display ("XORWF  f=0x%0h, W", last_pc, debuginst4:0);
-		else       	$display ("%h XORWF  f=0x%0h, f", last_pc, debuginst4:0);
-	end
-	else if (debuginst11:6 == 7'b0001_11) begin
-		if (piccpu_inst.d == 0)	$display ("%h ADDWF  f=0x%0h, W", last_pc, debuginst4:0);
-		else       	$display ("%h ADDWF  f=0x%0h, f", last_pc, debuginst4:0);
-	end
-	else if (debuginst11:6 == 7'b0010_00) begin
-		if (piccpu_inst.d == 0)	$display ("%h MOVF  f=0x%0h, W", last_pc, debuginst4:0);
-		else       	$display ("%h MOVF  f=0x%0h, f", last_pc, debuginst4:0);
-	end
-	else if (debuginst11:6 == 7'b0010_01) begin
-		if (piccpu_inst.d == 0)	$display ("%h COMF  f=0x%0h, W", last_pc, debuginst4:0);
-		else       	$display ("%h COMF  f=0x%0h, f", last_pc, debuginst4:0);
-	end
-	else if (debuginst11:6 == 7'b0010_10) begin
-		if (piccpu_inst.d == 0)	$display ("%h INCF  f=0x%0h, W", last_pc, debuginst4:0);
-		else       	$display ("%h INCF  f=0x%0h, f", last_pc, debuginst4:0);
-	end
-	else if (debuginst11:6 == 7'b0010_11) begin
-		if (piccpu_inst.d == 0)	$display ("%h DECFSZ  f=0x%0h, W", last_pc, debuginst4:0);
-		else       	$display ("%h DECFSZ  f=0x%0h, f", last_pc, debuginst4:0);
-	end
-	else if (debuginst11:6 == 7'b0011_00) begin
-		if (piccpu_inst.d == 0)	$display ("%h RRF  f=0x%0h, W", last_pc, debuginst4:0);
-		else       	$display ("%h RRF  f=0x%0h, f", last_pc, debuginst4:0);
-	end
-	else if (debuginst11:6 == 7'b0011_01) begin
-		if (piccpu_inst.d == 0)	$display ("%h RLF  f=0x%0h, W", last_pc, debuginst4:0);
-		else       	$display ("%h RLF  f=0x%0h, f", last_pc, debuginst4:0);
-	end
-	else if (debuginst11:6 == 7'b0011_10) begin
-		if (piccpu_inst.d == 0)	$display ("%h SWAPF  f=0x%0h, W", last_pc, debuginst4:0);
-		else       	$display ("%h SWAPF  f=0x%0h, f", last_pc, debuginst4:0);
-	end
-	else if (debuginst11:6 == 7'b0011_11) begin
-		if (piccpu_inst.d == 0)	$display ("%h INCFSZ  f=0x%0h, W", last_pc, debuginst4:0);
-		else       	$display ("%h INCFSZ  f=0x%0h, f", last_pc, debuginst4:0);
-	end
-
-	// Bit-Oriented File Register Operations
-	else if (debuginst11:8 == 4'b0100) begin
-		$display ("%h BCF  f=0x%0h, bit=%0d", last_pc, debuginst4:0, piccpu_inst.b);
-	end
-	else if (debuginst11:8 == 4'b0101) begin
-		$display ("%h BCF  f=0x%0h, bit=%0d", last_pc, debuginst4:0, piccpu_inst.b);
-	end
-	else if (debuginst11:8 == 4'b0110) begin
-		if (piccpu_inst.skip) $display ("%h BTFSC  f=0x%0h, bit=%0d  {Will Skip..}", last_pc, debuginst4:0, piccpu_inst.b);
-		else      $display ("%h BTFSC  f=0x%0h, bit=%0d  {Will NOT Skip..}", last_pc, debuginst4:0, piccpu_inst.b);
-	end
-	else if (debuginst11:8 == 4'b0111) begin
-		if (piccpu_inst.skip) $display ("%h BTFSS  f=0x%0h, bit=%0d  {Will Skip..}", last_pc, debuginst4:0, piccpu_inst.b);
-		else      $display ("%h BTFSS  f=0x%0h, bit=%0d  {Will NOT Skip..}", last_pc, debuginst4:0, piccpu_inst.b);
-	end
-
-	// Literal and Control Operations
-	else if (debuginst11:0 == 16'b0000_0000_0010) begin
-		$display ("%h OPTION", last_pc);
-	end
-	else if (debuginst11:0 == 16'b0000_0000_0011) begin
-		$display ("%h SLEEP", last_pc);
-	end
-	else if (debuginst11:0 == 16'b0000_0000_0100) begin
-		$display ("%h CLRWDT", last_pc);
-	end
-	else if (debuginst11:3 == 13'b0000_0000_0) begin
-		$display ("%h TRIS,  f=0x%0h", last_pc, debuginst2:0);
-	end
-	else if (debuginst11:8 == 4'b1000) begin
-		$display ("%h RETLW,  k=0x%0h", last_pc, debuginst7:0);
-	end
-	else if (debuginst11:8 == 4'b1001) begin
-		$display ("%h CALL,  k=0x%0h", last_pc, debuginst7:0);
-	end
-	else if (debuginst11:9 == 3'b101) begin
-		$display ("%h GOTO,  k=0x%0h", last_pc, debuginst8:0);
-	end
-	else if (debuginst11:8 == 4'b1100) begin
-		$display ("%h MOVLW,  k=0x%0h", last_pc, debuginst7:0);
-	end
-	else if (debuginst11:8 == 4'b1101) begin
-		$display ("%h IORLW,  k=0x%0h", last_pc, debuginst7:0);
-	end
-	else if (debuginst11:8 == 4'b1110) begin
-		$display ("%h ANDLW,  k=0x%0h", last_pc, debuginst7:0);
-	end
-	else if (debuginst11:8 == 4'b1111) begin
-		$display ("%h XORLW,  k=0x%0h", last_pc, debuginst7:0);
-	end
-	else begin
-		$display ("Hmmm!  instruction not recognized?! %0h", debuginst);
-	end
-      end
-   end
-end
-
-
-endmodule
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/pipe1.v Deleted

@@ -1,173 +0,0 @@
-// pipe1.v      Verilog version using modules in this file
-//              basic five stage pipeline of just Instruction Register
-//              The 411 course pipeline has the same five stages
-//              IF Instruction Fetch includes PC and instruction memory
-//              ID Instruction Decode and registers
-//              EX Execution including the ALU Arithmetic Logic Unit
-//              MEM data Memory
-//              WB Write Back into registers
-//
-// This self contained Verilog file defines:
-//
-//     a 32 bit adder module using behavioral code
-//     a 32 bit register module with clock and clear inputs
-//     an instruction memory module using behavioral code
-//
-//     a top level module, pipe1, test bench
-//     the wires for interconnecting the entities
-//     the modules instantiated to connect the wires
-//     printout that shows the registers in the pipeline each clock
-//
-
-`timescale 1ps/1ps // times in pico seconds
-
-module add32(a, b, cin, sum, cout);
-  parameter n=31;
-  input  n:0 a;     // a input
-  input  n:0 b;     // b input
-  input        cin;   // carry-in
-  output n:0 sum;   // sum output
-  output       cout;  // carry-out
-  assign #250 {cout, sum} = a + b + cin;
-endmodule // add32
-
-module register_32(clk, clear, inp, out);
-  input         clk;    // accept  inp  on posedge
-  input         clear;  // clear when high
-  input  31:0 inp;    // input data
-  output 31:0 out;    // output of register
-  wire   31:0 inp;
-  wire   31:0 out;
-  reg    31:0 stored;        // temporary variable
-
-  initial stored = 32'h00000000;
-
-  assign out = stored;  // set output wire
-
-  always @(posedge clk)
-    begin  // behavior
-      #200 stored <= inp;
-    end
-endmodule // register_32
-
-module instruction_memory(addr, inst);
-  input 31:0 addr;
-  output 31:0 inst;
-  integer word_addr;
-  reg 31:0 memory 0:6;
-  reg 31:0 inst_word;
-
-  assign inst = inst_word;
-
-  function 31:0 to_integer;
-    input 31:0 argument;
-    to_integer = argument;
-  endfunction // to_integer
-
-  initial
-    begin
-      memory0 = 32'h00000001;
-      memory1 = 32'h00000002;
-      memory2 = 32'h00000003;
-      memory3 = 32'h00000004;
-      memory4 = 32'h00000005;
-      memory5 = 32'h00000006;
-      memory6 = 32'h00000007;
-    end
-
-  always @(addr)
-    begin  // behavior
-      word_addr = to_integer(addr)/4;
-      #250 inst_word = memoryword_addr;
-    end
-endmodule // instruction_memory
-
-
-module pipe1;  // test bench
-  // signals used in test bench (the interconnections)
-  
-  reg 31:0 zero_32; // = 32'h00000000;   // 32 bit zero
-  reg        zero;    // = 0;              // one bit zero
-  reg 31:0 four_32; // = 32'h00000004;   // four
-
-  reg        clear;   // = 1;    // one shot clear
-  reg        clk;     // = 0;    // master clock
-  integer    counter; // = 0;    // master clock counter, raising edge
-  wire       nc1;                // a No-Connection for unused output
-
-  wire 31:0 IF_PC_next;        // next value of PC 
-  wire 31:0 IF_PC;             // Program Counter
-  wire 31:0 inst;              // instruction fetched
-  wire 31:0 ID_IR;             // ID Instruction Register
-  wire 31:0 EX_IR;             // EX Instruction Register
-  wire 31:0 MEM_IR;            // MEM Instruction Register
-  wire 31:0 WB_IR;             // WB Instruction Register
-
-  function 31:0 to_integer;
-    input 31:0 argument;
-    to_integer = argument;
-  endfunction // to_integer
-  
-  initial
-    begin
-      zero_32 = 32'h00000000;   // 32 bit zero
-      zero    = 0;              // one bit zero
-      four_32 = 32'h00000004;   // four
-      clear   = 1;              // one shot clear
-      clk     = 0;              // master clock
-      counter = 0;              // master clock counter, raising edge
-      #200 clear = 0;           // clear time finished
-      forever #5000 clk = ~clk; // run clock 10ns period
-    end
-
-  initial #60000 $finish; // stop after 60 ns
-
-  // schematic of pipe1, behavior and test bench
-
-  // IF, Instruction Fetch pipeline stage
-  register_32 PC_reg(clk, clear, IF_PC_next, IF_PC);
-  add32 PC_incr(IF_PC, four_32, zero, IF_PC_next, nc1);
-  instruction_memory inst_mem(IF_PC, inst);
-
-  // ID, Instruction Decode and register stack pipeline stage
-  register_32 ID_IR_reg(clk, clear, inst, ID_IR);
-
-  // EX, Execute pipeline stage
-  register_32 EX_IR_reg(clk, clear, ID_IR, EX_IR);
-
-  // MEM Data Memory pipeline stage
-  register_32 MEM_IR_reg(clk, clear, EX_IR, MEM_IR);
-
-  // WB, Write Back pipeline stage
-  register_32 WB_IR_reg(clk, clear, MEM_IR, WB_IR);
-
-  always @(posedge clk) // to show state of registers in pipeline
-    begin
-      $write("at clock ");
-      $write("%0d", counter);
-      $write("  PC=");
-      $write("%h", IF_PC);
-      $write("\n");
-      $write("IF  stage inst=");
-      $write("%h", inst);
-      $write("\n");
-      $write("IF_PC_next    =");
-      $write("%h", IF_PC_next);
-      $write("\n");
-      $write("ID  stage   IR=");
-      $write("%h", ID_IR);
-      $write("\n");
-      $write("EX  stage   IR=");
-      $write("%h", EX_IR);
-      $write("\n");
-      $write("MEM stage   IR=");
-      $write("%h", MEM_IR);
-      $write("\n");
-      $write("WB  stage   IR=");
-      $write("%h", WB_IR);
-      $write("\n");
-      $write("\n");         // blank line
-      counter = counter+1;
-    end
-
-endmodule // pipe1

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/pipe2.v Deleted

@@ -1,461 +0,0 @@
-// pipe2.v      Verilog version using modules in this file
-//              basic five stage pipeline of just Instruction Register
-//              The 411 course pipeline has the same five stages
-//              IF Instruction Fetch includes PC and instruction memory
-//              ID Instruction Decode and registers
-//              EX Execution including the ALU Arithmetic Logic Unit
-//              MEM data Memory
-//              WB Write Back into registers
-//
-// This self contained Verilog file defines:
-//
-//     a 32 bit adder module using behavioral code
-//     32 and 5 bit register module with clock and clear inputs
-//     an instruction memory module using behavioral code
-//     a data memory module using behavioral code
-//     a general register module using behavioral code
-//     32 and 5 bit multiplexor module using behavioral code
-//
-//     a top level module, pipe2, test bench
-//     the wires for interconnecting the entities
-//     the modules instantiated to connect the wires
-//     printout that shows the registers in the pipeline each clock
-//
-
-`timescale 1ps/1ps // times in pico seconds
-
-module add32(a, b, cin, sum, cout);
-  parameter n=31;
-  input  n:0 a;     // a input
-  input  n:0 b;     // b input
-  input        cin;   // carry-in
-  output n:0 sum;   // sum output
-  output       cout;  // carry-out
-  assign #250 {cout, sum} = a + b + cin;
-endmodule // add32
-
-
-module register_32(clk, clear, inp, out);
-  input         clk;    // accept  inp  on posedge
-  input         clear;  // clear when high
-  input  31:0 inp;    // input data
-  output 31:0 out;    // output of register
-  wire   31:0 inp;
-  wire   31:0 out;
-  reg    31:0 stored;        // temporary variable
-
-  initial stored = 32'h00000000;
-
-  assign out = stored;  // set output wire
-
-  always @(posedge clk) #200 stored <= inp;
-endmodule // register_32
-
-
-module register_5(clk, clear, inp, out);
-  input        clk;    // accept  inp  on posedge
-  input        clear;  // clear when high
-  input  4:0 inp;    // input data
-  output 4:0 out;    // output of register
-  wire   4:0 out;
-  reg    4:0 stored;        // temporary variable
-
-  initial stored = 5'b00000;
-
-  assign out = stored;  // set output wire
-
-  always @(posedge clk) #200 stored <= inp;
-endmodule // register_5
-
-
-module instruction_memory(addr, inst);
-  input 31:0 addr;
-  output 31:0 inst;
-  integer word_addr;
-  reg 31:0 memory 0:15;
-  reg 31:0 inst_word;
-
-  assign inst = inst_word;
-
-  function 31:0 to_integer;
-    input 31:0 argument;
-    to_integer = argument;
-  endfunction // to_integer
-
-  initial
-    begin
-      memory0 = 32'b10001100000000010000000000000100;  // lw
-      memory1 = 32'b10001100000000100000000000001000;  // lw
-      memory2 = 32'b00000000000000000000000000000000;  // nop
-      memory3 = 32'b00000000000000000000000000000000;  // nop
-      memory4 = 32'b00000000001000100001100000100000;  // add
-      memory5 = 32'b00000000011000100010000000100010;  // sub
-      memory6 = 32'b00000000000000010010101111000001;  // sll
-      memory7 = 32'b00000000000000100011010000000010;  // srl
-      memory8 = 32'b00000000000000110011100000000100;  // cmpl
-      memory9 = 32'b10101100000000010000000000001000;  // sw
-      memory10= 32'b00000000000000000000000000000000;  // nop
-      memory11= 32'b00000000000000000000000000000000;  // nop
-      memory12= 32'b00000000000000000000000000000000;  // nop
-      memory13= 32'b00000000000000000000000000000000;  // nop
-      memory14= 32'b00000000000000000000000000000000;  // nop
-      memory15= 32'b00000000000000000000000000000000;  // nop
-    end
-
-  always @(addr)
-    begin  // behavior
-      word_addr = to_integer(addr)/4;
-      #250 inst_word = memoryword_addr;
-    end
-endmodule // instruction_memory
-
-
-module data_memory(address, write_data, read_enable, write_enable,
-                   write_clk, read_data);
-  input  31:0 address;
-  input  31:0 write_data;
-  input         read_enable;
-  input         write_enable;
-  input         write_clk;
-  output 31:0 read_data;
-  wire   31:0 read_data;
-
-  integer word_addr;
-  integer write_addr;
-  reg 31:0 memory 0:1000;
-  reg 31:0 data_word;
-
-  assign read_data = data_word;
-
-  function 31:0 to_integer;
-    input 31:0 argument;
-    to_integer = argument;
-  endfunction // to_integer
-
-  initial
-    begin
-      memory0 = 32'b00010001000100010001000100010001; // h0
-      memory1 = 32'b00100010001000100010001000100010; // h4
-      memory2 = 32'b00110011001100110011001100110011; // h8
-    end // rest is XXXXXXXXXX
-
-  always @(address or posedge read_enable)
-    begin  // behavior
-      word_addr = to_integer(address)/4;
-      if(read_enable==1)
-        #250 data_word <= memoryword_addr;
-    end
-
-  always @(negedge read_enable)
-         #200 data_word = 32'b00000000000000000000000000000000;
-
-  always @(posedge write_clk)
-    begin
-      if(write_enable==1)
-        begin
-          write_addr = to_integer(address)/4;
-          memorywrite_addr = write_data;
-        end
-    end
-endmodule // data_memory
-
-
-module registers(read_reg_1, read_reg_2, write_reg,
-                 write_data, write_enable, write_clk,
-                 read_data_1, read_data_2);
-  input   4:0 read_reg_1;    // 5 bit register address to read data 1
-  input   4:0 read_reg_2;    // 5 bit register address to read data 2
-  input   4:0 write_reg;     // 5 bit register address to write
-  input  31:0 write_data;    // 32 bit word to write into register
-  input         write_enable;  // rising clock and enable
-  input         write_clk;     // required to write
-  output 31:0 read_data_1;   // register content of read_reg_1
-  output 31:0 read_data_2;   // register content of read_reg_2
-  wire   31:0 read_data_1;
-  wire   31:0 read_data_2;
-
-  integer reg_addr_1;
-  integer reg_addr_2;
-  integer write_addr;
-  integer i;
-  reg 31:0 memory 0:31;
-  reg 31:0 reg_word_1;
-  reg 31:0 reg_word_2;
-
-  assign read_data_1 = reg_word_1;
-  assign read_data_2 = reg_word_2;
-
-  function 5:0 to_integer;
-    input 5:0 argument;
-    to_integer = argument;
-  endfunction // to_integer
-
-  initial
-    begin
-      for(i=0; i<32; i=i+1) memoryi = 32'h00000000;
-      reg_word_1 = 32'h00000000;
-      reg_word_2 = 32'h00000000;
-    end
-
-  always @(read_reg_1)
-    begin
-      reg_addr_1 = to_integer(read_reg_1);
-      #50 reg_word_1 <= memoryreg_addr_1;
-    end
-
-  always @(read_reg_2)
-    begin
-      reg_addr_2 = to_integer(read_reg_2);
-      #50 reg_word_2 <= memoryreg_addr_2;
-    end
-
-  always @(posedge write_clk)
-    begin  // behavior
-      write_addr = to_integer(write_reg);
-      if(write_enable==1)
-        begin
-          #100 memorywrite_addr = write_data;
-          if(write_reg==read_reg_1) reg_word_1 = write_data;
-          if(write_reg==read_reg_2) reg_word_2 = write_data;
-        end
-    end
-endmodule // registers
-
-
-module mux_32(in0, in1, ctl, result);
-  parameter n=31;
-  input  n:0 in0;     // 0 input
-  input  n:0 in1;     // 1 input
-  input        ctl;     // control
-  output n:0 result;  // output
-  assign result = (ctl==0) ? in0 : in1;
-endmodule // mux_32
-
-
-module mux_5(in0, in1, ctl, result);
-  parameter n=4;
-  input  n:0 in0;     // 0 input
-  input  n:0 in1;     // 1 input
-  input        ctl;     // control
-  output n:0 result;  // output
-  assign result = (ctl==0) ? in0 : in1;
-endmodule // mux_5
-
-module alu_32(inA, inB, inst, result);
-  input  31:0 inA;
-  input  31:0 inB;
-  input  31:0 inst;
-  output 31:0 result;
-  wire   31:0 result;
-  reg           cin; //=0
-  wire          cout;
-
-  initial cin=0;
-
-  add32 adder(inA, inB, cin, result, cout);
-
-endmodule // alu_32
-
- 
-module pipe2;  // test bench
-  // signals used in test bench (the interconnections)
-  
-  reg 31:0 zero_32; // = 32'h00000000;   // 32 bit zero
-  reg        zero;    // = 0;              // one bit zero
-  reg 31:0 four_32; // = 32'h00000004;   // four
-
-  reg        clear;   // = 1;    // one shot clear
-  reg        clk;     // = 0;    // master clock
-  wire       clk_bar;            // split phase for mem write
-  integer    counter; // = 0;    // master clock counter, raising edge
-  wire       nc1;                // a No-Connection for unused output
-
-  wire 31:0 PC_next;        // next value of PC 
-  wire 31:0 PC;             // Program Counter
-  wire 31:0 inst;              // instruction fetched
-
-
-  wire 31:0 ID_IR;             // ID Instruction Register
-  wire 31:0 ID_read_data_1;    // ID Register read data 1
-  wire 31:0 ID_read_data_2;    // ID Register read data 2
-  wire 31:0 ID_sign_ext;       // ID sign extension
-  wire  4:0 ID_rd;             // ID register destination
-  wire 15:0 ID_addr;           // ID_IR15:0 address
-  wire        RegDst; //=0       // ID selects destination register
-  wire        S;                 // ID for sign extend
-
-  wire 31:0 EX_IR;             // EX Instruction Register
-  wire 31:0 EX_A;              // EX data A
-  wire 31:0 EX_B;              // EX data B
-  wire 31:0 EX_C;              // EX data C
-  wire  4:0 EX_rd;             // EX register destination
-  wire 31:0 EX_aluB;           // EX into ALU B
-  wire        ALUSrc; //=1       // EX ALU B side source control
-  wire 31:0 EX_result;         // EX ALU output
-
-
-  wire 31:0 MEM_IR;            // MEM Instruction Register
-  wire 31:0 MEM_addr;          // MEM address
-  wire 31:0 MEM_data;          // MEM write data
-  wire 31:0 MEM_read_data;     // MEM read data
-  wire  4:0 MEM_rd;            // MEM register destination
-  wire        MEMRead;           // MEM enable read
-  wire        MEMWrite; //=0;    // MEM enable write
-
-  wire 31:0 WB_IR;             // WB Instruction Register
-  wire 31:0 WB_read;           // WB read data
-  wire 31:0 WB_pass;           // WB pass data
-  wire  4:0 WB_rd;             // WB register destination
-  wire        MemtoReg;          // WB mux control
-  wire 31:0 WB_result;         // WB mux output
-  wire        WB_write_enb; //=1 // WB enable register write
-
-  function 31:0 to_integer;
-    input 31:0 argument;
-    to_integer = argument;
-  endfunction // to_integer
-  
-  initial
-    begin
-      zero_32 = 32'h00000000;    // 32 bit zero
-      zero    = 0;               // one bit zero
-      four_32 = 32'h00000004;    // four
-      clear   = 1;               // one shot clear
-      clk     = 0;               // master clock
-      counter = 0;               // master clock counter, raising edge
-      #200 clear = 0;            // clear time finished
-      forever #5000 clk = ~clk;  // run clock 10ns period
-    end
-
-  initial #140000 $finish;       // stop after 140 ns
-
-  assign ALUSrc = 1;             // change to correct expression
-  assign RegDst = 0;             // change to correct expression
-  assign MEMWrite = 0;           // change to correct expression
-  assign WB_write_enb = 1;       // change to correct expression
-
-  // schematic of pipe2, behavior and test bench
-  assign  clk_bar = ~clk;        // for split phase registers
-
-  // IF, Instruction Fetch pipeline stage
-  register_32 PC_reg(clk, clear, PC_next, PC);
-  add32 PC_incr(PC, four_32, zero, PC_next, nc1);
-  instruction_memory inst_mem(PC, inst);
-
-  // ID, Instruction Decode and register stack pipeline stage
-  register_32 ID_IR_reg(clk, clear, inst, ID_IR);
-  registers ID_regs(.read_reg_1(ID_IR25:21),
-                    .read_reg_2(ID_IR20:16),
-                    .write_reg(WB_rd),
-                    .write_data(WB_result),
-                    .write_enable(WB_write_enb),
-                    .write_clk(clk_bar),
-                    .read_data_1(ID_read_data_1),
-                    .read_data_2(ID_read_data_2));
-  mux_5 ID_mux_rd(.in0(ID_IR20:16),
-                  .in1(ID_IR15:11),
-                  .ctl(RegDst),
-                  .result(ID_rd));
-             assign ID_sign_ext15:0 = ID_IR15:0;  // just wiring
-             assign ID_sign_ext31:16 =
-                    {S,S,S,S,S,S,S,S,S,S,S,S,S,S,S,S};
-             assign S = ID_IR15;
-  // EX, Execute pipeline stage
-  register_32 EX_IR_reg(clk, clear, ID_IR, EX_IR);
-  register_32 EX_A_reg(clk, clear, ID_read_data_1, EX_A);
-  register_32 EX_B_reg(clk, clear, ID_read_data_2, EX_B);
-  register_32 EX_C_reg(clk, clear, ID_sign_ext, EX_C);
-  register_5  EX_rd_reg(clk, clear, ID_rd, EX_rd);
-  mux_32 EX_mux1(.in0(EX_B), .in1(EX_C), .ctl(ALUSrc), .result(EX_aluB));
-  alu_32 ALU(.inA(EX_A),
-             .inB(EX_aluB),
-             .inst(EX_IR),
-             .result(EX_result));
-
-  // MEM Data Memory pipeline stage
-  register_32 MEM_IR_reg(clk, clear, EX_IR, MEM_IR);
-  register_32 MEM_addr_reg(clk, clear, EX_result, MEM_addr);
-  register_32 MEM_data_reg(clk, clear, EX_B, MEM_data);
-  register_5  MEM_rd_reg(clk, clear, EX_rd, MEM_rd);
-              assign MEMRead = (MEM_IR31:26 == 6'b100011 );
-  data_memory data_mem(.address(MEM_addr),
-                       .write_data(MEM_data),
-                       .read_enable(MEMRead),
-                       .write_enable(MEMWrite),
-                       .write_clk(clk_bar),
-                       .read_data(MEM_read_data));
-
-  // WB, Write Back pipeline stage
-  register_32 WB_IR_reg(clk, clear, MEM_IR, WB_IR);
-  register_32 WB_read_reg(clk, clear, MEM_read_data, WB_read);
-  register_32 WB_pass_reg(clk, clear, MEM_addr, WB_pass);
-  register_5  WB_rd_reg(clk, clear, MEM_rd, WB_rd);
-              assign MemtoReg = (WB_IR31:26 == 6'b100011 );
-  mux_32 WB_mux(.in0(WB_pass),
-                .in1(WB_read),
-                .ctl(MemtoReg),
-                .result(WB_result));
-
-             
-
-
-             
-
-  always @(posedge clk) // to show state of registers in pipeline
-    begin
-      $write("clock %0d", counter);
-      $write("  inst=%h", inst);
-      $write("  PC   =%h", PC);
-      $write(" PCnext=%h", PC_next);
-      $write("\n");
-      $write("ID  stage  IR=%h", ID_IR);
-      if((WB_write_enb==1)&&(WB_rd!=5'b00000))
-        begin
-          $write("  write=%h", WB_result);
-          $write("  into =000000%h", {3'b000,WB_rd});
-          $write("               ");
-        end
-      else
-        $write("                                               ");
-
-      $write("  rd=%b", ID_rd);
-      $write("\n");
-      $write("EX  stage  IR=%h", EX_IR);
-      $write("  EX_A =%h", EX_A);
-      $write("  EX_B =%h", EX_B);
-      $write("  EX_C =%h", EX_C);
-      $write(" rd=%b", EX_rd);
-      $write("\n");
-      $write("EX  stage             ");
-      $write("EX_aluB=%h", EX_aluB);
-      $write(" EX_res=%h", EX_result);
-      $write("\n");
-      $write("MEM stage  IR=%h", MEM_IR);
-      $write("  addr =%h", MEM_addr);
-      $write("  data =%h", MEM_data);
-      if(MEMRead==1)
-        $write("  read =%h", MEM_read_data);
-      else if(MEMWrite==1)
-        $write("  wrote=%h", MEM_data);
-      else
-        $write("                ");
-
-      $write(" rd=%b", MEM_rd);
-      $write("\n");
-      $write("WB  stage  IR=%h", WB_IR);
-      $write("  read =%h", WB_read);
-      $write("  pass =%h", WB_pass);
-      $write(" result=%h", WB_result);
-      $write(" rd=%b", WB_rd);
-      $write("\n");
-      $write("control RegDst=%b", RegDst);
-      $write("  ALUSrc=%b", ALUSrc);
-      $write("  MemtoReg=%b", MemtoReg);
-      $write("  MEMRead=%b", MEMRead);
-      $write("  MEMWrite=%b", MEMWrite);
-      $write("  WB_write_enb=%b", WB_write_enb);
-      $write("\n");
-      $write("\n");         // blank line
-      counter = counter+1;
-    end
-endmodule // pipe2

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/pl.v Deleted

@@ -1,434 +0,0 @@
-/////////////////////////////////////////////////////////////////////
-////                                                             ////
-////  Protocol Layer                                             ////
-////  This block is typically referred to as the SEI in USB      ////
-////  Specification. It encapsulates the Packet Assembler,       ////
-////  disassembler, protocol engine and internal DMA             ////
-////                                                             ////
-////  Author: Rudolf Usselmann                                   ////
-////          rudi@asics.ws                                      ////
-////                                                             ////
-////                                                             ////
-////  Downloaded from: http://www.opencores.org/cores/usb/       ////
-////                                                             ////
-/////////////////////////////////////////////////////////////////////
-////                                                             ////
-//// Copyright (C) 2000 Rudolf Usselmann                         ////
-////                    rudi@asics.ws                            ////
-////                                                             ////
-//// This source file may be used and distributed without        ////
-//// restriction provided that this copyright statement is not   ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer.////
-////                                                             ////
-////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
-//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
-//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
-//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
-//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
-//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
-//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
-//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
-//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
-//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
-//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
-//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
-//// POSSIBILITY OF SUCH DAMAGE.                                 ////
-////                                                             ////
-/////////////////////////////////////////////////////////////////////
-
-//  CVS Log
-//
-//  $Id: pl.v,v 1.0 2001/03/07 09:17:12 rudi Exp $
-//
-//  $Date: 2001/03/07 09:17:12 $
-//  $Revision: 1.0 $
-//  $Author: rudi $
-//  $Locker:  $
-//  $State: Exp $
-//
-// Change History:
-//               $Log: pl.v,v $
-//               Revision 1.0  2001/03/07 09:17:12  rudi
-//
-//
-//               Changed all revisions to revision 1.0. This is because OpenCores CVS
-//               interface could not handle the original '0.1' revision ....
-//
-//               Revision 0.1.0.1  2001/02/28 08:11:11  rudi
-//               Initial Release
-//
-//
-
-`include "usb_defines.v"
-
-module pl(  clk, rst,
-
-        // UTMI Interface
-        rx_data, rx_valid, rx_active, rx_err,
-        tx_data, tx_valid, tx_valid_last, tx_ready,
-        tx_first, tx_valid_out,
-        mode_hs, usb_reset, usb_suspend, usb_attached,
-
-        // memory interface
-        madr, mdout, mdin, mwe, mreq, mack,
-
-        // Register File Interface
-        fa, idin,
-        ep_sel, match,
-        dma_in_buf_sz1, dma_out_buf_avail,
-        buf0_rl, buf0_set, buf1_set,
-        uc_bsel_set, uc_dpd_set,
-
-        int_buf1_set, int_buf0_set, int_upid_set,
-        int_crc16_set, int_to_set, int_seqerr_set,
-
-        csr, buf0, buf1,
-
-        // Misc
-        frm_nat,
-        pid_cs_err, nse_err,
-        crc5_err
-
-        );
-
-// UTMI Interface
-input       clk, rst;
-input   7:0   rx_data;
-input       rx_valid, rx_active, rx_err;
-output  7:0   tx_data;
-output      tx_valid;
-output      tx_valid_last;
-input       tx_ready;
-output      tx_first;
-input       tx_valid_out;
-input       mode_hs;    // High Speed Mode
-input       usb_reset;  // USB Reset
-input       usb_suspend;    // USB Suspend
-input       usb_attached;   // Attached to USB
-
-
-// Memory Arbiter Interface
-output  14:0  madr;       // word address
-output  31:0  mdout;
-input   31:0  mdin;
-output      mwe;
-output      mreq;
-input       mack;
-
-
-// Register File interface
-input   6:0   fa;     // Function Address (as set by the controller)
-output  31:0  idin;       // Data Input
-output  3:0   ep_sel;     // Endpoint Number Input
-input       match;      // Endpoint Matched
-input       dma_in_buf_sz1;
-input       dma_out_buf_avail;
-output      nse_err;    // no such endpoint error
-
-output      buf0_rl;    // Reload Buf 0 with original values
-output      buf0_set;   // Write to buf 0
-output      buf1_set;   // Write to buf 1
-output      uc_bsel_set;    // Write to the uc_bsel field
-output      uc_dpd_set; // Write to the uc_dpd field
-output      int_buf1_set;   // Set buf1 full/empty interrupt
-output      int_buf0_set;   // Set buf0 full/empty interrupt
-output      int_upid_set;   // Set unsupported PID interrupt
-output      int_crc16_set;  // Set CRC16 error interrupt
-output      int_to_set; // Set time out interrupt
-output      int_seqerr_set; // Set PID sequence error interrupt
-
-input   31:0  csr;        // Internal CSR Output
-input   31:0  buf0;       // Internal Buf 0 Output
-input   31:0  buf1;       // Internal Buf 1 Output
-
-// Misc
-output      pid_cs_err; // pid checksum error
-output      crc5_err;   // crc5 error
-output  31:0  frm_nat;
-
-
-///////////////////////////////////////////////////////////////////
-//
-// Local Wires and Registers
-//
-
-// Packet Disassembler Interface
-wire        clk, rst;
-wire    7:0   rx_data;
-wire        rx_valid, rx_active, rx_err;
-wire        pid_OUT, pid_IN, pid_SOF, pid_SETUP;
-wire        pid_DATA0, pid_DATA1, pid_DATA2, pid_MDATA;
-wire        pid_ACK, pid_NACK, pid_STALL, pid_NYET;
-wire        pid_PRE, pid_ERR, pid_SPLIT, pid_PING;
-wire    6:0   token_fadr;
-wire        token_valid;
-wire        crc5_err;
-wire    11:0  frame_no;
-wire    7:0   rx_data_st;
-wire        rx_data_valid;
-wire        rx_data_done;
-wire        crc16_err;
-wire        rx_seq_err;
-
-// Packet Assembler Interface
-wire        send_token;
-wire    1:0   token_pid_sel;
-wire        send_data;
-wire    1:0   data_pid_sel;
-wire    7:0   tx_data_st;
-wire        rd_next;
-
-// IDMA Interface
-wire        rx_dma_en;  // Allows the data to be stored
-wire        tx_dma_en;  // Allows for data to be retrieved
-wire        abort;      // Abort Transfer (time_out, crc_err or rx_error)
-wire        idma_done;  // DMA is done
-wire    16:0  adr;        // Byte Address
-wire    13:0  size;       // Size in bytes
-wire    10:0  sizu_c;     // Up and Down counting size registers, used
-                // to update
-wire    13:0  buf_size;   // Actual buffer size
-wire        dma_en;     // external dma enabled
-
-// Memory Arbiter Interface
-wire    14:0  madr;       // word address
-wire    31:0  mdout;
-wire    31:0  mdin;
-wire        mwe;
-wire        mreq;
-wire        mack;
-
-// Local signals
-wire        pid_bad, pid_bad1, pid_bad2;
-
-reg     hms_clk;    // 0.5 Micro Second Clock
-reg 4:0   hms_cnt;
-
-reg 11:0  frame_no_r; // Current Frame Number register
-wire        frame_no_we;
-reg     frame_no_same;  // Indicates current and prev. frame numbers
-                // are equal
-reg 3:0   mfm_cnt;    // Micro Frame Counter
-reg 11:0  sof_time;   // Time since last sof
-reg     clr_sof_time;
-
-wire        fsel;       // This Function is selected
-
-wire        match_o;
-
-///////////////////////////////////////////////////////////////////
-//
-// Misc Logic
-//
-
-
-// PIDs we should never receive
-assign pid_bad1 = pid_ACK | pid_NACK | pid_STALL | pid_NYET | pid_PRE |
-            pid_ERR | pid_SPLIT;
-
-// PIDs we should never get in full speed mode (high speed mode only)
-assign pid_bad2 = !mode_hs & pid_PING;
-
-// All bad pids
-assign pid_bad = pid_bad1 | pid_bad2;
-
-assign match_o = !pid_bad & match & token_valid & !crc5_err;
-
-// Frame Number (from SOF token)
-reg frame_no_we_r;
-
-assign frame_no_we = token_valid & !crc5_err & pid_SOF;
-
-always @(posedge clk)
-    frame_no_we_r <= #1 frame_no_we;
-
-always @(posedge clk)
-    if(!rst)    frame_no_r <= #1 0;
-    else
-    if(frame_no_we) frame_no_r <= #1 frame_no;
-
-// Micro Frame Counter
-always @(posedge clk)
-    frame_no_same <= #1 frame_no_we & (frame_no_r == frame_no);
-
-always @(posedge clk)
-    if(!rst)        mfm_cnt <= #1 0;
-    else
-    if(frame_no_we & !frame_no_same)
-                mfm_cnt <= #1 0;
-    else
-    if(frame_no_same)   mfm_cnt <= #1 mfm_cnt + 1;
-
-//SOF delay counter
-always @(posedge clk)
-    clr_sof_time <= #1 frame_no_we;
-
-always @(posedge clk)
-    if(clr_sof_time)    sof_time <= #1 0;
-    else
-    if(hms_clk)     sof_time <= #1 sof_time + 1;
-
-assign frm_nat = {mfm_cnt, frame_no_r, 4'h0, sof_time};
-
-
-// 0.5 Micro Seconds Clock Generator
-always @(posedge clk)
-    if(!rst | hms_clk | frame_no_we)    hms_cnt <= #1 0;
-    else                    hms_cnt <= #1 hms_cnt + 1;
-
-//always @(posedge clk)
-//    hms_clk <= #1 (hms_cnt == `HMS_DEL);
-
-///////////////////////////////////////////////////////////////////
-
-// This function is addressed
-assign fsel = (token_fadr == fa);
-
-///////////////////////////////////////////////////////////////////
-//
-// Module Instantiations
-//
-
-//Packet Decoder
-pd  u0( .clk(       clk     ),
-        .rst(       rst     ),
-        .rx_data(   rx_data     ),
-        .rx_valid(  rx_valid    ),
-        .rx_active( rx_active   ),
-        .rx_err(    rx_err      ),
-        .pid_OUT(   pid_OUT     ),
-        .pid_IN(    pid_IN      ),
-        .pid_SOF(   pid_SOF     ),
-        .pid_SETUP( pid_SETUP   ),
-        .pid_DATA0( pid_DATA0   ),
-        .pid_DATA1( pid_DATA1   ),
-        .pid_DATA2( pid_DATA2   ),
-        .pid_MDATA( pid_MDATA   ),
-        .pid_ACK(   pid_ACK     ),
-        .pid_NACK(  pid_NACK    ),
-        .pid_STALL( pid_STALL   ),
-        .pid_NYET(  pid_NYET    ),
-        .pid_PRE(   pid_PRE     ),
-        .pid_ERR(   pid_ERR     ),
-        .pid_SPLIT( pid_SPLIT   ),
-        .pid_PING(  pid_PING    ),
-        .pid_cks_err(   pid_cs_err  ),
-        .token_fadr(    token_fadr  ),
-        .token_endp(    ep_sel      ),
-        .token_valid(   token_valid ),
-        .crc5_err(  crc5_err    ),
-        .frame_no(  frame_no    ),
-        .rx_data_st(    rx_data_st  ),
-        .rx_data_valid( rx_data_valid   ),
-        .rx_data_done(  rx_data_done    ),
-        .crc16_err( crc16_err   ),
-        .seq_err(   rx_seq_err  )
-        );
-
-// Packet Assembler
-pa  u1( .clk(       clk     ),
-        .rst(       rst     ),
-        .tx_data(   tx_data     ),
-        .tx_valid(  tx_valid    ),
-        .tx_valid_last( tx_valid_last   ),
-        .tx_ready(  tx_ready    ),
-        .tx_first(  tx_first    ),
-        .send_token(    send_token  ),
-        .token_pid_sel( token_pid_sel   ),
-        .send_data( send_data   ),
-        .data_pid_sel(  data_pid_sel    ),
-        .tx_data_st(    tx_data_st  ),
-        .rd_next(   rd_next     )
-        );
-
-// Internal DMA / Memory Arbiter Interface
-idma    u2( .clk(       clk     ),
-        .rst(       rst     ),
-        .rx_data_st(    rx_data_st  ),
-        .rx_data_valid( rx_data_valid   ),
-        .rx_data_done(  rx_data_done    ),
-        .send_data( send_data   ),
-        .tx_data_st(    tx_data_st  ),
-        .rd_next(   rd_next     ),
-        .rx_dma_en( rx_dma_en   ),
-        .tx_dma_en( tx_dma_en   ),
-        .abort(     abort       ),
-        .idma_done( idma_done   ),
-        .adr(       adr     ),
-        .size(      size        ),
-        .buf_size(  buf_size    ),
-        .dma_en(    dma_en      ),
-        .madr(      madr        ),
-        .sizu_c(    sizu_c      ),
-        .mdout(     mdout       ),
-        .mdin(      mdin        ),
-        .mwe(       mwe     ),
-        .mreq(      mreq        ),
-        .mack(      mack        )
-        );
-
-// Protocol Engine
-pe  u3( .clk(           clk         ),
-        .rst(           rst         ),
-        .tx_valid(      tx_valid_out        ),
-        .rx_active(     rx_active       ),
-        .pid_OUT(       pid_OUT         ),
-        .pid_IN(        pid_IN          ),
-        .pid_SOF(       pid_SOF         ),
-        .pid_SETUP(     pid_SETUP       ),
-        .pid_DATA0(     pid_DATA0       ),
-        .pid_DATA1(     pid_DATA1       ),
-        .pid_DATA2(     pid_DATA2       ),
-        .pid_MDATA(     pid_MDATA       ),
-        .pid_ACK(       pid_ACK         ),
-        .pid_NACK(      pid_NACK        ),
-        .pid_STALL(     pid_STALL       ),
-        .pid_NYET(      pid_NYET        ),
-        .pid_PRE(       pid_PRE         ),
-        .pid_ERR(       pid_ERR         ),
-        .pid_SPLIT(     pid_SPLIT       ),
-        .pid_PING(      pid_PING        ),
-        .mode_hs(       mode_hs         ),
-        .token_valid(       token_valid     ),
-        .crc5_err(      crc5_err        ),
-        .rx_data_valid(     rx_data_valid       ),
-        .rx_data_done(      rx_data_done        ),
-        .crc16_err(     crc16_err       ),
-        .send_token(        send_token      ),
-        .token_pid_sel(     token_pid_sel       ),
-        .data_pid_sel(      data_pid_sel        ),
-        .rx_dma_en(     rx_dma_en       ),
-        .tx_dma_en(     tx_dma_en       ),
-        .abort(         abort           ),
-        .idma_done(     idma_done       ),
-        .adr(           adr         ),
-        .size(          size            ),
-        .buf_size(      buf_size        ),
-        .sizu_c(        sizu_c          ),
-        .dma_en(        dma_en          ),
-        .fsel(          fsel            ),
-        .idin(          idin            ),
-        .ep_sel(        ep_sel          ),
-        .match(         match_o         ),
-        .dma_in_buf_sz1(    dma_in_buf_sz1      ),
-        .dma_out_buf_avail( dma_out_buf_avail   ),
-        .nse_err(       nse_err         ),
-        .buf0_rl(       buf0_rl         ),
-        .buf0_set(      buf0_set        ),
-        .buf1_set(      buf1_set        ),
-        .uc_bsel_set(       uc_bsel_set     ),
-        .uc_dpd_set(        uc_dpd_set      ),
-        .int_buf1_set(      int_buf1_set        ),
-        .int_buf0_set(      int_buf0_set        ),
-        .int_upid_set(      int_upid_set        ),
-        .int_crc16_set(     int_crc16_set       ),
-        .int_to_set(        int_to_set      ),
-        .int_seqerr_set(    int_seqerr_set      ),
-        .csr(           csr         ),
-        .buf0(          buf0            ),
-        .buf1(          buf1            )
-        );
-
-endmodule
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/pli_handbook_examples_pc.zip Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/port_info_test.v Deleted

@@ -1,42 +0,0 @@
-/**********************************************************************
- * $port_info example -- Verilog test bench source code
- *
- * Verilog test bench to test the $port_info PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-  reg  a, b, ci, clk;
-  wire sum, co;
-
-  addbit i1 (a, b, ci, sum, co);
-
-  initial
-    begin
-      #10 $port_info(i1);
-      #10 $finish;
-    end
-endmodule
-
-/*** A gate level 1 bit adder model ***/
-`timescale 1ns / 1ns
-module addbit (a, b, ci, sum, co, foo);
-  input  a, b, ci;
-  output sum, co;
-  output 3:0 foo;
-
-  wire  a, b, ci;
-  reg   sum, co;
-  wand  scalared 3:0 foo;
-
-  always @(a or b or ci)
-    {co,sum} = a + b + ci;
-
-endmodule
-/*********************************************************************/
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/pow_test.v Deleted

@@ -1,41 +0,0 @@
-/**********************************************************************
- * $pow example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $pow PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-  reg  32:0 result;
-  reg         a, b;
-
-  buf i1 (c,a);
-  initial
-    begin
-      a = 1;
-      b = 0;
-      /* Test $pow with invalid arguments */
-      /* These invalid calls will need to be commented out to use */
-      /* the valid calls to $pow in simulation */
-//      #1 result = $pow;
-//      #1 result = $pow();
-//      #1 result = $pow(1);
-//      #1 result = $pow(2,i1);
-//      #1 result = $pow(1,2,3);
-
-      /* Test $pow with valid values */
-      #1 $display("$pow(2,3) returns %d", $pow(2,3));
-      #1 result = $pow(a,b);
-      #1 $display("$pow(a,b) returns %d (a=%d b=%d)", result, a, b);
-      #1 $stop;
-      $finish;
-    end
-
-endmodule
-/*********************************************************************/
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/primitives.v Deleted

@@ -1,100 +0,0 @@
-/////////////////////////////////////////////////////////////////////
-////                                                             ////
-////  USB function core primitives                               ////
-////  This file contains all technology dependent primitives     ////
-////  such as SSRAMs.                                            ////
-////                                                             ////
-////  Author: Rudolf Usselmann                                   ////
-////          rudi@asics.ws                                      ////
-////                                                             ////
-////                                                             ////
-////  Downloaded from: http://www.opencores.org/cores/usb/       ////
-////                                                             ////
-/////////////////////////////////////////////////////////////////////
-////                                                             ////
-//// Copyright (C) 2000 Rudolf Usselmann                         ////
-////                    rudi@asics.ws                            ////
-////                                                             ////
-//// This source file may be used and distributed without        ////
-//// restriction provided that this copyright statement is not   ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer.////
-////                                                             ////
-////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
-//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
-//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
-//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
-//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
-//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
-//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
-//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
-//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
-//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
-//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
-//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
-//// POSSIBILITY OF SUCH DAMAGE.                                 ////
-////                                                             ////
-/////////////////////////////////////////////////////////////////////
-
-//  CVS Log
-//
-//  $Id: primitives.v,v 1.0 2001/03/07 09:17:12 rudi Exp $
-//
-//  $Date: 2001/03/07 09:17:12 $
-//  $Revision: 1.0 $
-//  $Author: rudi $
-//  $Locker:  $
-//  $State: Exp $
-//
-// Change History:
-//               $Log: primitives.v,v $
-//               Revision 1.0  2001/03/07 09:17:12  rudi
-//
-//
-//               Changed all revisions to revision 1.0. This is because OpenCores CVS
-//               interface could not handle the original '0.1' revision ....
-//
-//               Revision 0.1.0.1  2001/02/28 08:11:11  rudi
-//               Initial Release
-//
-//
-
-`include "usb_defines.v"
-
-///////////////////////////////////////////////////////////////////
-//
-// SSRAM Model
-//
-///////////////////////////////////////////////////////////////////
-module ssram(	clk, rst,
-		radr, rdin, rdout, rre, rwe
-		);
-
-input		clk, rst;
-input	14:0	radr;
-input	31:0	rdin;
-output	31:0	rdout;
-input		rre, rwe;
-
-///////////////////////////////////////////////////////////////////
-//
-// Local Wires and Registers
-//
-
-reg	31:0	mem0:8192;
-reg	31:0	rdout;
-wire	11:0	adr_i = radr11:0;
-
-///////////////////////////////////////////////////////////////////
-//
-// Memory Logic
-//
-
-//always @(posedge clk)
-//	if(rst & rwe)	memadr_i <= #1 rdin;
-
-always @(posedge clk)
-	if(rst & rre)	rdout <= #1 memadr_i;
-
-endmodule
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/propagatep_test.v Deleted

@@ -1,46 +0,0 @@
-/**********************************************************************
- * $propagatep_test example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $propagatep_test PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-  reg  7:0 reg1;
-  real       real1;
-  reg  7:0 mem1 0:3;
-
-  initial
-    begin
-      $monitor("\nAt time %0d in test bench: reg1=%h  real1=%2.1f  mem10=%h\n",
-               $stime, reg1, real1, mem10);
-      reg1  = 1'b0;
-      real1 = 0.0;
-
-      #1 $display("Calling $propagatep_test(reg1)...");
-         $propagatep_test(reg1);
-
-      #1 $display("Calling $propagatep_test(real1)...");
-         $propagatep_test(real1);
-
-      #1 $display("Calling $propagatep_test(reg12)...");
-         $propagatep_test(reg12);
-
-      #1 $display("Calling $propagatep_test(reg17:4)...");
-         $propagatep_test(reg17:4);
-
-      #1 $display("Calling $propagatep_test(mem10)...");
-         $propagatep_test(mem10);
-
-      #1 $finish;
-    end
-
-endmodule
-
-/**********************************************************************/
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/psr1.v Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/psr1_conf.v Deleted

@@ -1,116 +0,0 @@
-// Verilog HDL for "RSFQ.lib", "psr1_conf" "_functional"
-
-// Module CONFLUENCE BUFFER
-module psr1_conf (in1, in2, out);
-
-input
-	in1, in2;
-
-output
-	out;
-reg 
-	out;
-
-parameter
-	t_separation = 10,
-	delay=15,
-
-// multichannel description of a warning file
-	warning_file=2,  
-// multichannel description of a delay file
-	delay_file = warning_file<<1;
-
-reg
-	sep_clr; // signal marking the end of the min separation zone
-		 //  for the last pulse
-
-integer
-	last_in_time,    // time when the last t pulse appeared
-	in_sep,	 // number of pulses within an interval t_sep before 
-		 //  the last data pulse;
-	vdelay;		 // variable delay
-
-
-`include "INIT"
-
-`ifdef RANDOM_DELAYS
- `include "RANDOM_GATE"
-`endif
-
-
-initial 
-	begin
-		vdelay = delay;
-
-`ifdef RANDOM_DELAYS
-		delay_dev = psr1_conf_variation*delay;
-		vdelay = $dist_normal(psr1_conf_seed, delay, delay_dev);
-`endif
-
-		#1 $fdisplay(delay_file, "module=%m, nom_delay=%0d, delay=%0d", delay, vdelay);
-
-// clear internal registers and the output signal
-		last_in_time = 0;
-		in_sep = 0;
-		sep_clr = 0;
-		out = 0;
-	end
-
-always @(posedge in1)
-	begin
-		out <= #vdelay ((in_sep > 0) || (in2 == 1)) ? 1'bx : 1;
-		out <= #(vdelay+2) 0;
-		
-		if((in_sep>0) || (in2 == 1))
-	          begin
-	        // generating a warning
-	            $fwrite(warning_file, 
-	            "Violation of separation time in module %m.\n");
-	            $fwrite(warning_file,
-	            "Input pulses at ");
-		    if(in_sep>0)
-			$fwrite(warning_file,
-			"%0d and at %0d.\n", last_in_time, $stime);
-		    else
-			$fwrite(warning_file,
-			"%0d and at %0d.\n", $stime, $stime);
-	    	  end
-	  	last_in_time <= $stime;
-
-		in_sep <= in_sep + 1;
-		sep_clr <= #(t_separation-1) 1;
-	end
-
-always @(posedge in2)
-	begin
-		out <= #vdelay ((in_sep > 0) || (in1 == 1)) ? 1'bx : 1;
-		out <= #(vdelay+2) 0;
-
-		if((in_sep>0) || (in1 == 1))
-	          begin
-	        // generating a warning
-	            $fwrite(warning_file, 
-	            "Violation of separation time in module %m.\n");
-	            $fwrite(warning_file,
-	            "Input pulses at ");
-		    if(in_sep>0)
-			$fwrite(warning_file,
-			"%0d and at %0d.\n", last_in_time, $stime);
-		    else
-			$fwrite(warning_file,
-			"%0d and at %0d.\n", $stime, $stime);
-	    	  end
-	  	last_in_time <= $stime;
-
-		in_sep <= in_sep + 1;
-		sep_clr <= #(t_separation-1) 1;
-	end
-
-always @(posedge sep_clr)
-	begin
-	  	in_sep <= in_sep - 1;
-		sep_clr <= 0;
-	end
-
-
-endmodule

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/psr1_dro.v Deleted

@@ -1,153 +0,0 @@
-// Verilog HDL for "RSFQ.lib", "psr1_dro" "_functional"
-
-// Module DRO cell
-module psr1_dro (d, clk, out);
-
-input
-	d, clk;
-
-output
-	out;
-reg 
-	out;
-
-parameter
-	t_hold	= 1,
-	t_setup	= 8,
-	delay	= 10,
-
-// multichannel description of a warning file
-	warning_file=2,  
-// multichannel description of a delay file
-	delay_file = warning_file<<1;
-
-reg
-	d_internal, clk_internal,
-	d_state,          	   // internal state at the input d
-	d_set;		   	   // signal determining the moment when
-				   // the state of the d input changes to "1"
-
-integer
-	data_delay,  // delay between d and d_internal
-	clk_delay,   // delay between clk and clk_internal
-	out_delay,   // delay between clk_internal and out
-	out_value,   // output value in a given clock cycle
-	last_clk_time,	// time when the last clock pulse appeared
-	vt_hold,	// variable hold
-	vt_setup,	// variable setup
-	vdelay;		 // variable delay
-
-
-`include "INIT"
-
-`ifdef RANDOM_DELAYS
- `include "RANDOM_GATE"
-`endif
-
-
-initial 
-	begin
-		vt_hold = t_hold;
-		vt_setup = t_setup;
-		vdelay = delay;
-
-`ifdef RANDOM_DELAYS
-		delay_dev = psr1_dro_variation*delay;
-		vdelay = $dist_normal(psr1_dro_seed, delay, delay_dev);
-		vt_hold = $dist_normal(psr1_dro_seed, t_hold, 
-                                       psr1_dro_hs_dev);
-		vt_setup = t_setup + (t_hold - vt_hold);
-
-`endif
-
-		#1 $fdisplay(delay_file, "module=%m, nom_delay=%0d, delay=%0d", delay, vdelay);
-		#1 $fdisplay(delay_file, "module=%m, nom_hold=%0d, hold=%0d", t_hold, vt_hold);
-		#1 $fdisplay(delay_file, "module=%m, nom_setup=%0d, setup=%0d", t_setup, vt_setup);
-
-
-
-// define delays between inputs & outputs and the corresponding
-//  internal auxiliary registers
-	  	if(vt_hold<0)
-		  begin
-	    	  	data_delay = -vt_hold;
-	    		clk_delay  = 0;
-			out_delay  = vdelay;
-		  end
-	  	else
-		  begin
-	   	  	data_delay = 0;
-	    		clk_delay  = vt_hold;
-		  	out_delay  = vdelay-vt_hold;
-		  end
-
-// clear internal registers and the output signal
-		d_internal = 0;
-		clk_internal = 0;
-		last_clk_time = 0;
-		d_state = 0;
-		d_set = 0;
-		out = 0;
-	end
-
-
-
-always @(posedge d) 	// Execute at positive edge of d
-	  d_internal <= #(data_delay) d;
-
-always @(posedge clk)  // Execute at positive edge of clk
-	  clk_internal <= #(clk_delay) clk;
-
-
-always @(posedge d_internal)
-	begin
-// setting the state of the d input
-                d_state <= d_state | 1'bx;
-		if (d_internal === 1)
-		  d_set <= #(vt_hold+vt_setup) 1;
-
-		d_internal <= 0;
-	end
-
-always @(posedge d_set)
-	begin
-		if ($stime - last_clk_time >= vt_hold+vt_setup)
-			d_state = 1;
-		else
-		  begin
-			d_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input D pulse at %0d,",
-			 $stime-data_delay-vt_hold-vt_setup);
-			$fwrite(warning_file,
-			"\tClock pulse at %0d.\n", last_clk_time-clk_delay);
-		  end
-
-		d_set <= 0;
-	end
-
-
-always @(posedge clk_internal)	
-	begin
-// computing the output
-		if (clk_internal === 1'bx)
-		  out_value = 1'bx;
-		else
-		  out_value = d_state;
-
-// transfering the result to the output
-		out <= #(out_delay) out_value;
-		out <= #(out_delay+2) 0;
-
-// clearing the internal state of the DRO
-		d_state  <= 0;
-
-		clk_internal <= 0;
-		last_clk_time = $stime;
-	end
-
-endmodule

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/psr1_split.v Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/psr2.v Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/psr2_and.v Deleted

@@ -1,185 +0,0 @@
-// Verilog HDL for "RSFQ.lib", "and_gate" "_functional"
-
-// Module AND gate
-module psr2_and (a, b, clk, out);
-
-input
-	a, b, clk;
-
-output
-	out;
-reg 
-	out;
-
-parameter
-	t_hold	= 14,
-	t_setup	= -3,
-	delay	= 21,
-
-// multichannel description of a warning file
-	warning_file=2,  
-// multichannel description of a delay file
-	delay_file = warning_file<<1;
-
-reg
-	a_internal, b_internal, clk_internal,
-	a_state, b_state,          // internal state at inputs a and b
-	a_set, b_set;		   // signals determining the moment when
-				   // the state of the a,b inputs changes to "1"
-integer
-	data_delay, 	// delay between a (b) and a_internal (b_internal)
-	clk_delay, 	// delay between clk and clk_internal
-	out_delay, 	// delay between clk_internal and out
-	out_value,	// output value in a given clock cycle
-	last_clk_time,	// time when the last clock pulse appeared
-	vt_hold,	// variable hold
-	vt_setup,	// variable setup
-	vdelay;		// variable delay
-
-
-`include "INIT"
-
-`ifdef RANDOM_DELAYS
- `include "RANDOM_GATE"
-`endif
-
-
-initial 
-	begin
-		vt_hold = t_hold;
-		vt_setup = t_setup;
-		vdelay = delay;
-
-`ifdef RANDOM_DELAYS
-		delay_dev = psr2_and_variation*delay;
-		vdelay = $dist_normal(psr2_and_seed, delay, delay_dev);
-		vt_hold = $dist_normal(psr2_and_seed, t_hold, 
-                                         psr2_and_hs_dev);
-		vt_setup = t_setup + (t_hold - vt_hold);
-`endif
-
-		#1 $fdisplay(delay_file, "module=%m, nom_delay=%0d, delay=%0d", delay, vdelay);
-		#1 $fdisplay(delay_file, "module=%m, nom_hold=%0d, hold=%0d", t_hold, vt_hold);
-		#1 $fdisplay(delay_file, "module=%m, nom_setup=%0d, setup=%0d", t_setup, vt_setup);
-
-
-// define delays between inputs & outputs and the corresponding
-//  internal auxiliary registers
-	  	if(vt_hold<0)
-		  begin
-	    		data_delay = -vt_hold;
-	    	  	clk_delay = 0;
-		  	out_delay = vdelay;
-		  end
-	  	else
-		  begin
-	    	  	data_delay = 0;
-	    	  	clk_delay = vt_hold;
-		  	out_delay=vdelay-vt_hold;
-		  end
-
-// clear internal registers and the output signal
-		a_internal = 0;
-		b_internal = 0;
-		clk_internal = 0;
-		last_clk_time = 0;
-		a_state = 0;
-		b_state = 0;
-		a_set = 0;
-		b_set = 0;
-		out = 0;
-	end
-
-always @(posedge a) 	// Execute at positive edge of a
-	  a_internal <= #(data_delay) a;
-
-always @(posedge b) 	// Execute at positive edge of b
-	  b_internal <= #(data_delay) b;
-
-always @(posedge clk) 	// Execute at positive edge of clk
-	  clk_internal <= #(clk_delay) clk;
-
-always @(posedge a_internal)
-	begin
-// setting an internal state at the input a
-                a_state <= a_state | 1'bx;
-		if (a_internal === 1)
-		  a_set <= #(vt_hold+vt_setup) 1;
-
-		a_internal <= 0;
-	end
-
-always @(posedge b_internal)
-	begin
-// setting an internal state at the input a
-                b_state <= b_state | 1'bx;
-		if (b_internal === 1)
-		  b_set <= #(vt_hold+vt_setup) 1;
-
-		b_internal <= 0;
-	end
-
-always @(posedge a_set)
-	begin
-		if ($stime - last_clk_time >= vt_hold+vt_setup)
-			a_state = 1;
-		else
-		  begin
-			a_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input A pulse at %0d,",
-			 $stime-data_delay-vt_hold-vt_setup);
-			$fwrite(warning_file,
-			"\tClock pulse at %0d.\n", last_clk_time-clk_delay);
-		  end
-
-		a_set <= 0;
-	end
-
-always @(posedge b_set)
-	begin
-		if ($stime - last_clk_time >= vt_hold+vt_setup)
-			b_state = 1;
-		else
-		  begin
-			b_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input B pulse at %0d,",
-			 $stime-data_delay-vt_hold-vt_setup);
-			$fwrite(warning_file,
-			"\tClock pulse at %0d.\n", last_clk_time-clk_delay);
-		  end
-
-		b_set <= 0;
-	end
-
-
-always @(posedge clk_internal)	
-	begin
-// computing the output
-		if (clk_internal === 1'bx)
-		  out_value = 1'bx;
-		else
-		  out_value = a_state & b_state;
-
-// transfering the result to the output
-		out <= #(out_delay) out_value;
-		out <= #(out_delay+2) 0;
-
-// clearing the internal state of A and B inputs
-		a_state  <= 0;
-		b_state  <= 0;
-
-		clk_internal <= 0;
-		last_clk_time = $stime;
-	end
-
-endmodule

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/psr2_split.v Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/read_4state_value_test.v Deleted

@@ -1,40 +0,0 @@
-/**********************************************************************
- * $read_4state_value example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $read_4state_value PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-  reg        reg1;
-  reg 31:0 reg2;
-  reg 0:51 reg3;
-  real       r1;
-
-  initial
-    begin
-      reg1 = 1'b0;
-      reg2 = 32'hF0F0F0F0;
-      reg3 = {13{4'b01zx}};
-      r1   = 3.1415;
-
-      #1 $read_4state_value("Hello world");
-      #1 $read_4state_value(r1);
-      #1 $read_4state_value(reg1);
-      #1 $read_4state_value(reg2);
-      #1 $read_4state_value(reg3);
-      #1 $read_4state_value(reg31);
-      #1 $read_4state_value(reg34:48);
-
-      #1 $finish;
-    end
-
-endmodule
-
-/**********************************************************************/
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/read_attribute_test.v Deleted

@@ -1,50 +0,0 @@
-/**********************************************************************
- * $read_attribute example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $read_attribute PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-  reg  a, b, ci, clk;
-  wire sum, co;
-
-  addbit i1 (a, b, ci, sum, co);
-
-  initial
-    begin
-      #1 $read_attribute(i1, "InputLoad$");
-      #1 $read_attribute(i1, "Foo$");
-      #1 $finish;
-    end
-endmodule
-
-/*** A gate level 1 bit adder model ***/
-`timescale 1ns / 1ns
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci, sum, co,
-        n1, n2, n3;
-
-  xor    (n1, a, b);
-  xor #2 (sum, n1, ci);
-  and    (n2, a, b);
-  and    (n3, n1, ci);
-  or  #2 (co, n2, n3);
-  
-  specify
-    specparam InputLoad$a = 1.1;
-    specparam InputLoad$b = 2.2;
-    specparam InputLoad$  = 3.3;
-  endspecify
-
-endmodule
-/*********************************************************************/
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/read_delays_test.v Deleted

@@ -1,48 +0,0 @@
-/**********************************************************************
- * $list_delays example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $list_delays PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-  reg  a, b, ci, clk;
-  wire sum, co;
-
-  addbit i1 (a, b, ci, sum, co);
-
-  initial
-    begin
-      #1 $read_delays(i1);
-      #1 $finish;
-    end
-endmodule
-
-/*** A gate level 1 bit adder model ***/
-`timescale 1ns / 1ns
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci, sum, co,
-        n1, n2, n3;
-
-  xor    (n1, a, b);
-  xor #2 (sum, n1, ci);
-  and    (n2, a, b);
-  and    (n3, n1, ci);
-  or  #2 (co, n2, n3);
-  
-  specify
-    (a *> sum) = (3, 5);
-    (b *> sum, co) = (1.3, 2.2);
-  endspecify
-
-endmodule
-/*********************************************************************/
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/read_stimulus_short_test.v Deleted

@@ -1,65 +0,0 @@
-/**********************************************************************
- * $read_stimulus_short example -- Verilog test bench source code
- *
- * Verilog test bench to test the $read_stimulus_short PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-  reg   8:0 input_vector;
-  wire  3:0 a, b, sum;
-  wire        ci, co;
-
-  add4 i1 (a, b, ci, sum, co);
-
-  assign {ci, a, b} = input_vector;
-  
-  initial
-    begin
-      $timeformat(-9,0," ns",10);
-      $monitor("%t:  a=%b  b=%b  ci=%b  sum=%b  co=%b",
-               $time, a, b, ci, sum, co);
-      $read_stimulus_short("read_stimulus.pat", input_vector);
-      #500 $finish;
-    end
-endmodule
-
-/*** A netlist level 4-bit adder model ***/
-`timescale 1ns / 1ns
-module add4 (a, b, ci, sum, co);
-  input  3:0 a, b;
-  input        ci;
-  output 3:0 sum;
-  output       co;
-
-  wire   3:0 a, b, sum;
-  wire         ci, c0, c1, c2, co;
-
-  addbit u0 (a0, b0, ci, sum0, c0);
-  addbit u1 (a1, b1, c0, sum1, c1);
-  addbit u2 (a2, b2, c1, sum2, c2);
-  addbit u3 (a3, b3, c2, sum3, co);
-
-endmodule
-
-/*** A gate level 1-bit adder model ***/
-`timescale 1ns / 1ns
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci, sum, co,
-        n1, n2, n3;
-
-  xor    (n1, a, b);
-  xor #2 (sum, n1, ci);
-  and    (n2, a, b);
-  and    (n3, n1, ci);
-  or  #2 (co, n2, n3);
-endmodule
-/**********************************************************************/

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/read_stimulus_test.v Deleted

@@ -1,68 +0,0 @@
-/**********************************************************************
- * $read_stimulus_ba example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $read_stimulus_ba PLI application.
- * NOTE: this test uses a data file called "read_stimulus_test.pat",
- * which has several 9-bit binary test vector values (represented in 
- * ASCII) and the simulation time in which each value is to be applied.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-
-module test;
-  reg   8:0 input_vector;
-  wire  3:0 a, b, sum;
-  wire        ci, co;
-
-  add4 i1 (a, b, ci, sum, co);
-
-  assign {ci, a, b} = input_vector;
-  
-  initial
-    begin
-      $timeformat(-9,0," ns",10);
-      $monitor("%t:  a=%b  b=%b  ci=%b  sum=%b  co=%b",
-               $time, a, b, ci, sum, co);
-      $read_stimulus_ba("read_stimulus_test.pat", input_vector);
-    end
-endmodule
-
-/*** A netlist level 4-bit adder model ***/
-`timescale 1ns / 1ns
-module add4 (a, b, ci, sum, co);
-  input  3:0 a, b;
-  input        ci;
-  output 3:0 sum;
-  output       co;
-
-  wire   3:0 a, b, sum;
-  wire         ci, c0, c1, c2, co;
-
-  addbit u0 (a0, b0, ci, sum0, c0);
-  addbit u1 (a1, b1, c0, sum1, c1);
-  addbit u2 (a2, b2, c1, sum2, c2);
-  addbit u3 (a3, b3, c2, sum3, co);
-
-endmodule
-
-/*** A gate level 1-bit adder model ***/
-`timescale 1ns / 1ns
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci, sum, co,
-        n1, n2, n3;
-
-  xor    (n1, a, b);
-  xor #2 (sum, n1, ci);
-  and    (n2, a, b);
-  and    (n3, n1, ci);
-  or  #2 (co, n2, n3);
-endmodule
-/**********************************************************************/

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/read_strengthval_test.v Deleted

@@ -1,43 +0,0 @@
-/**********************************************************************
- * $read_strengthval example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $read_strengthval PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-  wire a = 1'b0;
-  wire b = 1'b1;
-  wire c = 1'bz;
-  wire d = 1'bx;
-  wire e;
-  assign (pull0, pull1) e = 1'b1;  /* wired logic on e */
-  assign (pull1, pull0) e = 1'b0;
-  
-  wire f;
-  bufif1 (f, 1'b0, 1'bx); /* ambiguous output 'L' */
-  
-  wire g;
-  notif1 (g, 1'b0, 1'bx); /* ambiguous output 'H' */
-  
-  initial
-    begin
-      #1 
-      $read_strengthval(a);
-      $read_strengthval(b);
-      $read_strengthval(c);
-      $read_strengthval(d);
-      $read_strengthval(e);
-      $read_strengthval(f);
-      $read_strengthval(g);
-      #1 $finish;
-    end
-endmodule
-
-/*********************************************************************/
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/read_test_vector_test.v Deleted

@@ -1,36 +0,0 @@
-/**********************************************************************
- * $read_test_vector example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $read_test_vector PLI application.
- * NOTE: this test uses two data file, "read_vector_test1.pat" and
- * "read_vector_test2.pat".  Each file has several 8-bit binary test
- * vector values (represented in ASCII).
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-
-  reg 7:0 vector;
-  reg       clk;
-
-  initial
-    begin
-      $monitor("at %d: clk = %b  vector = %b", $stime, clk, vector);
-      clk = 0;
-      forever #10 clk = ~clk;
-    end
-
-  always @(posedge clk)
-    $read_test_vector("read_vector_test1.pat", vector);
- 
-  always @(negedge clk)
-    $read_test_vector("read_vector_test2.pat", vector);
- 
- endmodule
-/**********************************************************************/
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/read_timeval_test.v Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/read_vector_test.v Deleted

@@ -1,36 +0,0 @@
-/**********************************************************************
- * $read_test_vector example -- Verilog test bench source code
- *
- * Verilog test bench to test the $read_test_vector PLI application.
- * NOTE: this test uses two data file, "read_vector_test1.pat" and
- * "read_vector_test2.pat".  Each file has several 8-bit binary values
- * (represented in ASCII).
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-
-  reg 7:0 vector;
-  reg       clk;
-
-  initial
-    begin
-      $monitor("at %d: clk = %b  vector = %b", $stime, clk, vector);
-      clk = 0;
-      forever #10 clk = ~clk;
-    end
-
-  always @(posedge clk)
-    $read_test_vector("read_vector_test1.pat", vector);
- 
-  always @(negedge clk)
-    $read_test_vector("read_vector_test2.pat", vector);
- 
- endmodule
-/**********************************************************************/
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/read_vecval_test.v Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/realpow_test.v Deleted

@@ -1,32 +0,0 @@
-/**********************************************************************
- * $realpow example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $realpow PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-  integer i;
-  real    m, n;
-
-  initial
-    begin
-      i = 0;
-      m = 1.5;
-      n = 0.5;
-      #1 $display("$realpow(1.5, 3) returns %2.2f",
-                   $realpow(1.5, 3));
-      #1 $display("$realpow(4.0, n) returns %2.2f (n=%2.2f)",
-                   $realpow(4.0, n), n);
-      #1 $display("$realpow(m, i)   returns %2.2f (m=%2.2f i=%0d)",
-                   $realpow(m, i), m, i);
-    end
-
-endmodule
-
-/*********************************************************************/

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/rf.v Deleted

@@ -1,938 +0,0 @@
-/////////////////////////////////////////////////////////////////////
-////                                                             ////
-////  Register File                                              ////
-////  This module contains all top level registers and           ////
-////  instantiates the register files for endpoints              ////
-////                                                             ////
-////  Author: Rudolf Usselmann                                   ////
-////          rudi@asics.ws                                      ////
-////                                                             ////
-////                                                             ////
-////  Downloaded from: http://www.opencores.org/cores/usb/       ////
-////                                                             ////
-/////////////////////////////////////////////////////////////////////
-////                                                             ////
-//// Copyright (C) 2000 Rudolf Usselmann                         ////
-////                    rudi@asics.ws                            ////
-////                                                             ////
-//// This source file may be used and distributed without        ////
-//// restriction provided that this copyright statement is not   ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer.////
-////                                                             ////
-////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
-//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
-//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
-//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
-//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
-//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
-//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
-//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
-//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
-//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
-//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
-//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
-//// POSSIBILITY OF SUCH DAMAGE.                                 ////
-////                                                             ////
-/////////////////////////////////////////////////////////////////////
-
-//  CVS Log
-//
-//  $Id: rf.v,v 1.0 2001/03/07 09:17:12 rudi Exp $
-//
-//  $Date: 2001/03/07 09:17:12 $
-//  $Revision: 1.0 $
-//  $Author: rudi $
-//  $Locker:  $
-//  $State: Exp $
-//
-// Change History:
-//               $Log: rf.v,v $
-//               Revision 1.0  2001/03/07 09:17:12  rudi
-//
-//
-//               Changed all revisions to revision 1.0. This is because OpenCores CVS
-//               interface could not handle the original '0.1' revision ....
-//
-//               Revision 0.2  2001/03/07 09:08:13  rudi
-//
-//               Added USB controll signaling (Line Status) block. Fixed some minor
-//               typos, added resume bit and signal.
-//
-//               Revision 0.1.0.1  2001/02/28 08:11:32  rudi
-//               Initial Release
-//
-//
-
-`include "usb_defines.v"
-
-// Endpoint register File
-module rf(  clk, wclk, rst,
-
-        // Wishbone Interface
-        adr, re, we, din, dout, inta, intb,
-        dma_req, dma_ack,
-
-        // Internal Interface
-        idin,
-        ep_sel, match,
-        buf0_rl, buf0_set, buf1_set,
-        uc_bsel_set, uc_dpd_set,
-
-        int_buf1_set, int_buf0_set, int_upid_set,
-        int_crc16_set, int_to_set, int_seqerr_set,
-
-        csr, buf0, buf1,
-        funct_adr,
-        dma_in_buf_sz1, dma_out_buf_avail,
-
-        // Misc
-        frm_nat,
-        
-        // UTMI Interface
-        utmi_vend_stat, utmi_vend_ctrl, utmi_vend_wr,
-        
-        line_stat, usb_attached, mode_hs, suspend,
-        attached, usb_reset, pid_cs_err, nse_err,
-        crc5_err, rx_err, rf_resume_req
-        );
-
-input       clk, wclk, rst;
-input   6:0   adr;
-input       re;
-input       we;
-input   31:0  din;
-output  31:0  dout;
-output      inta, intb;
-output  14:0  dma_req;
-input   14:0  dma_ack;
-
-input   31:0  idin;       // Data Input
-input   3:0   ep_sel;     // Endpoint Number Input
-output      match;      // Endpoint Matched
-input       buf0_rl;    // Reload Buf 0 with original values
-
-input       buf0_set;   // Write to buf 0
-input       buf1_set;   // Write to buf 1
-input       uc_bsel_set;    // Write to the uc_bsel field
-input       uc_dpd_set; // Write to the uc_dpd field
-input       int_buf1_set;   // Set buf1 full/empty interrupt
-input       int_buf0_set;   // Set buf0 full/empty interrupt
-input       int_upid_set;   // Set unsupported PID interrupt
-input       int_crc16_set;  // Set CRC16 error interrupt
-input       int_to_set; // Set time out interrupt
-input       int_seqerr_set; // Set PID Sequence Error Interrupt
-
-output  31:0  csr;        // Internal CSR Output
-output  31:0  buf0;       // Internal Buf 0 Output
-output  31:0  buf1;       // Internal Buf 1 Output
-output  6:0   funct_adr;  // Function Address
-output      dma_in_buf_sz1, dma_out_buf_avail;
-
-input   31:0  frm_nat;
-
-input   7:0   utmi_vend_stat; // UTMI Vendor C/S bus
-output  3:0   utmi_vend_ctrl;
-output      utmi_vend_wr;
-
-input   1:0   line_stat;  // Below are signals for interrupt generation
-input       usb_attached;
-input       mode_hs;
-input       suspend;
-input       attached;
-input       usb_reset;
-input       nse_err;
-input       pid_cs_err;
-input       crc5_err;
-input       rx_err;
-output      rf_resume_req;
-
-///////////////////////////////////////////////////////////////////
-//
-// Local Wires and Registers
-//
-
-wire    31:0  ep0_dout, ep1_dout, ep2_dout, ep3_dout;
-wire    31:0  ep4_dout, ep5_dout, ep6_dout, ep7_dout;
-wire    31:0  ep8_dout, ep9_dout, ep10_dout, ep11_dout;
-wire    31:0  ep12_dout, ep13_dout, ep14_dout, ep15_dout;
-
-wire        ep0_re, ep1_re, ep2_re, ep3_re;
-wire        ep4_re, ep5_re, ep6_re, ep7_re;
-wire        ep8_re, ep9_re, ep10_re, ep11_re;
-wire        ep12_re, ep13_re, ep14_re, ep15_re;
-
-wire        ep0_we, ep1_we, ep2_we, ep3_we;
-wire        ep4_we, ep5_we, ep6_we, ep7_we;
-wire        ep8_we, ep9_we, ep10_we, ep11_we;
-wire        ep12_we, ep13_we, ep14_we, ep15_we;
-
-wire        ep0_inta, ep1_inta, ep2_inta, ep3_inta;
-wire        ep4_inta, ep5_inta, ep6_inta, ep7_inta;
-wire        ep8_inta, ep9_inta, ep10_inta, ep11_inta;
-wire        ep12_inta, ep13_inta, ep14_inta, ep15_inta;
-
-wire        ep0_intb, ep1_intb, ep2_intb, ep3_intb;
-wire        ep4_intb, ep5_intb, ep6_intb, ep7_intb;
-wire        ep8_intb, ep9_intb, ep10_intb, ep11_intb;
-wire        ep12_intb, ep13_intb, ep14_intb, ep15_intb;
-
-wire        ep0_match, ep1_match, ep2_match, ep3_match;
-wire        ep4_match, ep5_match, ep6_match, ep7_match;
-wire        ep8_match, ep9_match, ep10_match, ep11_match;
-wire        ep12_match, ep13_match, ep14_match, ep15_match;
-
-wire    31:0  ep0_csr, ep1_csr, ep2_csr, ep3_csr;
-wire    31:0  ep4_csr, ep5_csr, ep6_csr, ep7_csr;
-wire    31:0  ep8_csr, ep9_csr, ep10_csr, ep11_csr;
-wire    31:0  ep12_csr, ep13_csr, ep14_csr, ep15_csr;
-
-wire    31:0  ep0_buf0, ep1_buf0, ep2_buf0, ep3_buf0;
-wire    31:0  ep4_buf0, ep5_buf0, ep6_buf0, ep7_buf0;
-wire    31:0  ep8_buf0, ep9_buf0, ep10_buf0, ep11_buf0;
-wire    31:0  ep12_buf0, ep13_buf0, ep14_buf0, ep15_buf0;
-
-wire    31:0  ep0_buf1, ep1_buf1, ep2_buf1, ep3_buf1;
-wire    31:0  ep4_buf1, ep5_buf1, ep6_buf1, ep7_buf1;
-wire    31:0  ep8_buf1, ep9_buf1, ep10_buf1, ep11_buf1;
-wire    31:0  ep12_buf1, ep13_buf1, ep14_buf1, ep15_buf1;
-
-wire        ep0_dma_in_buf_sz1, ep1_dma_in_buf_sz1;
-wire        ep2_dma_in_buf_sz1, ep3_dma_in_buf_sz1;
-wire        ep4_dma_in_buf_sz1, ep5_dma_in_buf_sz1;
-wire        ep6_dma_in_buf_sz1, ep7_dma_in_buf_sz1;
-wire        ep8_dma_in_buf_sz1, ep9_dma_in_buf_sz1;
-wire        ep10_dma_in_buf_sz1, ep11_dma_in_buf_sz1;
-wire        ep12_dma_in_buf_sz1, ep13_dma_in_buf_sz1;
-wire        ep14_dma_in_buf_sz1, ep15_dma_in_buf_sz1;
-
-wire        ep0_dma_out_buf_avail, ep1_dma_out_buf_avail;
-wire        ep2_dma_out_buf_avail, ep3_dma_out_buf_avail;
-wire        ep4_dma_out_buf_avail, ep5_dma_out_buf_avail;
-wire        ep6_dma_out_buf_avail, ep7_dma_out_buf_avail;
-wire        ep8_dma_out_buf_avail, ep9_dma_out_buf_avail;
-wire        ep10_dma_out_buf_avail, ep11_dma_out_buf_avail;
-wire        ep12_dma_out_buf_avail, ep13_dma_out_buf_avail;
-wire        ep14_dma_out_buf_avail, ep15_dma_out_buf_avail;
-
-reg     dma_in_buf_sz1;
-reg     dma_out_buf_avail;
-
-reg 31:0  dtmp;
-reg 31:0  dout;
-
-wire    31:0  main_csr;
-reg 6:0   funct_adr;
-reg 8:0   intb_msk, inta_msk;
-
-reg     match_r1, match_r2;
-reg 31:0  csr;
-reg 31:0  buf0;
-reg 31:0  buf1;
-
-reg 3:0   utmi_vend_ctrl;
-reg     utmi_vend_wr;
-reg 7:0   utmi_vend_stat_r;
-
-reg     int_src_re;
-reg 8:0   int_srcb;
-reg 15:0  int_srca;
-reg     attach_r, attach_r1;
-wire        attach, deattach;
-reg     suspend_r, suspend_r1;
-wire        suspend_start, suspend_end;
-reg     usb_reset_r;
-reg     rx_err_r;
-reg     nse_err_r;
-reg     pid_cs_err_r;
-reg     crc5_err_r;
-
-reg     rf_resume_req_r, rf_resume_req;
-
-///////////////////////////////////////////////////////////////////
-//
-// WISHBONE Access
-//
-
-// Main CSR Alias
-assign main_csr = {28'h0, line_stat, usb_attached, mode_hs, suspend};
-
-// Read Registers Logic
-always @(adr or main_csr or funct_adr or inta_msk or intb_msk or int_srca
-    or int_srcb or frm_nat or utmi_vend_stat_r)
-    case(adr2:0)      // synopsys full_case parallel_case
-       0: dtmp = main_csr;
-       1: dtmp = { 25'h0, funct_adr};
-       2: dtmp = {7'h0, intb_msk, 7'h0, inta_msk};
-       3: dtmp = {3'h0, int_srcb, 4'h0, int_srca};
-       4: dtmp = frm_nat;
-       5: dtmp = {24'h0, utmi_vend_stat_r};
-    endcase
-
-// Interrupt Source Read Register
-always @(posedge wclk)
-    int_src_re <= #1 adr6:0 == 3 & re;
-
-// UTMI Vendor Control Stuff
-always @(posedge wclk)
-    utmi_vend_stat_r <= #1 utmi_vend_stat;
-
-always @(posedge wclk)
-    utmi_vend_wr <= #1 adr6:0 == 5 & we;
-
-always @(posedge wclk)
-    if(adr6:0 == 5 & we)  utmi_vend_ctrl <= #1 din3:0;
-
-// Resume Request
-always @(posedge wclk)
-    if(!rst)        rf_resume_req_r <= #1 0;
-    else
-    if(adr6:0 == 0 & we)  rf_resume_req_r <= #1 din5;
-    else
-    if(rf_resume_req)   rf_resume_req_r <= #1 0;
-
-always @(posedge clk)
-    rf_resume_req <= #1 rf_resume_req_r;
-
-// Function Address Register
-always @(posedge wclk)
-    if(!rst)        funct_adr <= #1 0;
-    else
-    if(adr6:0 == 1 & we)  funct_adr <= #1 din6:0;
-
-// Interrup Mask Register
-always @(posedge wclk)
-    if(!rst)
-       begin
-        inta_msk <= #1 0;
-        intb_msk <= #1 0;
-       end
-    else
-    if(adr6:0 == 2 & we)
-       begin
-        intb_msk <= #1 din24:16;
-        inta_msk <= #1 din08:00;
-       end
-
-always @(posedge wclk)
-    case(adr6:2)      // synopsys full_case parallel_case
-       0: dout <= #1 dtmp;  // Addr: 0h
-       1: dout <= #1 dtmp;
-       2: dout <= #1 32'h0;
-       3: dout <= #1 32'h0;
-       4: dout <= #1 ep0_dout;  // Addr: 010h
-       5: dout <= #1 ep1_dout;
-       6: dout <= #1 ep2_dout;
-       7: dout <= #1 ep3_dout;
-       8: dout <= #1 ep4_dout;  // Addr: 020h
-       9: dout <= #1 ep5_dout;
-      10: dout <= #1 ep6_dout;
-      11: dout <= #1 ep7_dout;
-      12: dout <= #1 ep8_dout;  // Addr: 030h
-      13: dout <= #1 ep9_dout;
-      14: dout <= #1 ep10_dout;
-      15: dout <= #1 ep11_dout;
-      16: dout <= #1 ep12_dout;
-      17: dout <= #1 ep13_dout;
-      18: dout <= #1 ep14_dout;
-      19: dout <= #1 ep15_dout; // Addr: 04ch
-    endcase
-
-assign ep0_re  = (adr6:2 ==  4) & re;
-assign ep1_re  = (adr6:2 ==  5) & re;
-assign ep2_re  = (adr6:2 ==  6) & re;
-assign ep3_re  = (adr6:2 ==  7) & re;
-assign ep4_re  = (adr6:2 ==  8) & re;
-assign ep5_re  = (adr6:2 ==  9) & re;
-assign ep6_re  = (adr6:2 == 10) & re;
-assign ep7_re  = (adr6:2 == 11) & re;
-assign ep8_re  = (adr6:2 == 12) & re;
-assign ep9_re  = (adr6:2 == 13) & re;
-assign ep10_re = (adr6:2 == 14) & re;
-assign ep11_re = (adr6:2 == 15) & re;
-assign ep12_re = (adr6:2 == 16) & re;
-assign ep13_re = (adr6:2 == 17) & re;
-assign ep14_re = (adr6:2 == 18) & re;
-assign ep15_re = (adr6:2 == 19) & re;
-
-assign ep0_we  = (adr6:2 ==  4) & we;
-assign ep1_we  = (adr6:2 ==  5) & we;
-assign ep2_we  = (adr6:2 ==  6) & we;
-assign ep3_we  = (adr6:2 ==  7) & we;
-assign ep4_we  = (adr6:2 ==  8) & we;
-assign ep5_we  = (adr6:2 ==  9) & we;
-assign ep6_we  = (adr6:2 == 10) & we;
-assign ep7_we  = (adr6:2 == 11) & we;
-assign ep8_we  = (adr6:2 == 12) & we;
-assign ep9_we  = (adr6:2 == 13) & we;
-assign ep10_we = (adr6:2 == 14) & we;
-assign ep11_we = (adr6:2 == 15) & we;
-assign ep12_we = (adr6:2 == 16) & we;
-assign ep13_we = (adr6:2 == 17) & we;
-assign ep14_we = (adr6:2 == 18) & we;
-assign ep15_we = (adr6:2 == 19) & we;
-
-///////////////////////////////////////////////////////////////////
-//
-// Internal Access
-//
-
-assign match = match_r1;
-
-always @(posedge clk)
-    match_r2 <= #1 match_r1;
-
-always @(posedge clk)
-    match_r1 <= #1  ep0_match | ep1_match | ep2_match | ep3_match |
-            ep4_match | ep5_match | ep6_match | ep7_match |
-            ep8_match | ep9_match | ep10_match | ep11_match |
-            ep12_match | ep13_match | ep14_match | ep15_match;
-
-always @(posedge clk)
-    if(ep0_match)   csr <= #1 ep0_csr;
-    else
-    if(ep1_match)   csr <= #1 ep1_csr;
-    else
-    if(ep2_match)   csr <= #1 ep2_csr;
-    else
-    if(ep3_match)   csr <= #1 ep3_csr;
-    else
-    if(ep4_match)   csr <= #1 ep4_csr;
-    else
-    if(ep5_match)   csr <= #1 ep5_csr;
-    else
-    if(ep6_match)   csr <= #1 ep6_csr;
-    else
-    if(ep7_match)   csr <= #1 ep7_csr;
-    else
-    if(ep8_match)   csr <= #1 ep8_csr;
-    else
-    if(ep9_match)   csr <= #1 ep9_csr;
-    else
-    if(ep10_match)  csr <= #1 ep10_csr;
-    else
-    if(ep11_match)  csr <= #1 ep11_csr;
-    else
-    if(ep12_match)  csr <= #1 ep12_csr;
-    else
-    if(ep13_match)  csr <= #1 ep13_csr;
-    else
-    if(ep14_match)  csr <= #1 ep14_csr;
-    else
-    if(ep15_match)  csr <= #1 ep15_csr;
-
-always @(posedge clk)
-    if(ep0_match)   buf0 <= #1 ep0_buf0;
-    else
-    if(ep1_match)   buf0 <= #1 ep1_buf0;
-    else
-    if(ep2_match)   buf0 <= #1 ep2_buf0;
-    else
-    if(ep3_match)   buf0 <= #1 ep3_buf0;
-    else
-    if(ep4_match)   buf0 <= #1 ep4_buf0;
-    else
-    if(ep5_match)   buf0 <= #1 ep5_buf0;
-    else
-    if(ep6_match)   buf0 <= #1 ep6_buf0;
-    else
-    if(ep7_match)   buf0 <= #1 ep7_buf0;
-    else
-    if(ep8_match)   buf0 <= #1 ep8_buf0;
-    else
-    if(ep9_match)   buf0 <= #1 ep9_buf0;
-    else
-    if(ep10_match)  buf0 <= #1 ep10_buf0;
-    else
-    if(ep11_match)  buf0 <= #1 ep11_buf0;
-    else
-    if(ep12_match)  buf0 <= #1 ep12_buf0;
-    else
-    if(ep13_match)  buf0 <= #1 ep13_buf0;
-    else
-    if(ep14_match)  buf0 <= #1 ep14_buf0;
-    else
-    if(ep15_match)  buf0 <= #1 ep15_buf0;
-
-always @(posedge clk)
-    if(ep0_match)   buf1 <= #1 ep0_buf1;
-    else
-    if(ep1_match)   buf1 <= #1 ep1_buf1;
-    else
-    if(ep2_match)   buf1 <= #1 ep2_buf1;
-    else
-    if(ep3_match)   buf1 <= #1 ep3_buf1;
-    else
-    if(ep4_match)   buf1 <= #1 ep4_buf1;
-    else
-    if(ep5_match)   buf1 <= #1 ep5_buf1;
-    else
-    if(ep6_match)   buf1 <= #1 ep6_buf1;
-    else
-    if(ep7_match)   buf1 <= #1 ep7_buf1;
-    else
-    if(ep8_match)   buf1 <= #1 ep8_buf1;
-    else
-    if(ep9_match)   buf1 <= #1 ep9_buf1;
-    else
-    if(ep10_match)  buf1 <= #1 ep10_buf1;
-    else
-    if(ep11_match)  buf1 <= #1 ep11_buf1;
-    else
-    if(ep12_match)  buf1 <= #1 ep12_buf1;
-    else
-    if(ep13_match)  buf1 <= #1 ep13_buf1;
-    else
-    if(ep14_match)  buf1 <= #1 ep14_buf1;
-    else
-    if(ep15_match)  buf1 <= #1 ep15_buf1;
-
-always @(posedge clk)
-    if(ep0_match)   dma_in_buf_sz1 <= #1 ep0_dma_in_buf_sz1;
-    else
-    if(ep1_match)   dma_in_buf_sz1 <= #1 ep1_dma_in_buf_sz1;
-    else
-    if(ep2_match)   dma_in_buf_sz1 <= #1 ep2_dma_in_buf_sz1;
-    else
-    if(ep3_match)   dma_in_buf_sz1 <= #1 ep3_dma_in_buf_sz1;
-    else
-    if(ep4_match)   dma_in_buf_sz1 <= #1 ep4_dma_in_buf_sz1;
-    else
-    if(ep5_match)   dma_in_buf_sz1 <= #1 ep5_dma_in_buf_sz1;
-    else
-    if(ep6_match)   dma_in_buf_sz1 <= #1 ep6_dma_in_buf_sz1;
-    else
-    if(ep7_match)   dma_in_buf_sz1 <= #1 ep7_dma_in_buf_sz1;
-    else
-    if(ep8_match)   dma_in_buf_sz1 <= #1 ep8_dma_in_buf_sz1;
-    else
-    if(ep9_match)   dma_in_buf_sz1 <= #1 ep9_dma_in_buf_sz1;
-    else
-    if(ep10_match)  dma_in_buf_sz1 <= #1 ep10_dma_in_buf_sz1;
-    else
-    if(ep11_match)  dma_in_buf_sz1 <= #1 ep11_dma_in_buf_sz1;
-    else
-    if(ep12_match)  dma_in_buf_sz1 <= #1 ep12_dma_in_buf_sz1;
-    else
-    if(ep13_match)  dma_in_buf_sz1 <= #1 ep13_dma_in_buf_sz1;
-    else
-    if(ep14_match)  dma_in_buf_sz1 <= #1 ep14_dma_in_buf_sz1;
-    else
-    if(ep15_match)  dma_in_buf_sz1 <= #1 ep15_dma_in_buf_sz1;
-
-always @(posedge clk)
-    if(ep0_match)   dma_out_buf_avail <= #1 ep0_dma_out_buf_avail;
-    else
-    if(ep1_match)   dma_out_buf_avail <= #1 ep1_dma_out_buf_avail;
-    else
-    if(ep2_match)   dma_out_buf_avail <= #1 ep2_dma_out_buf_avail;
-    else
-    if(ep3_match)   dma_out_buf_avail <= #1 ep3_dma_out_buf_avail;
-    else
-    if(ep4_match)   dma_out_buf_avail <= #1 ep4_dma_out_buf_avail;
-    else
-    if(ep5_match)   dma_out_buf_avail <= #1 ep5_dma_out_buf_avail;
-    else
-    if(ep6_match)   dma_out_buf_avail <= #1 ep6_dma_out_buf_avail;
-    else
-    if(ep7_match)   dma_out_buf_avail <= #1 ep7_dma_out_buf_avail;
-    else
-    if(ep8_match)   dma_out_buf_avail <= #1 ep8_dma_out_buf_avail;
-    else
-    if(ep9_match)   dma_out_buf_avail <= #1 ep9_dma_out_buf_avail;
-    else
-    if(ep10_match)  dma_out_buf_avail <= #1 ep10_dma_out_buf_avail;
-    else
-    if(ep11_match)  dma_out_buf_avail <= #1 ep11_dma_out_buf_avail;
-    else
-    if(ep12_match)  dma_out_buf_avail <= #1 ep12_dma_out_buf_avail;
-    else
-    if(ep13_match)  dma_out_buf_avail <= #1 ep13_dma_out_buf_avail;
-    else
-    if(ep14_match)  dma_out_buf_avail <= #1 ep14_dma_out_buf_avail;
-    else
-    if(ep15_match)  dma_out_buf_avail <= #1 ep15_dma_out_buf_avail;
-
-
-///////////////////////////////////////////////////////////////////
-//
-// Interrupt Generation
-//
-
-always @(posedge wclk)
-    attach_r <= usb_attached;
-
-always @(posedge wclk)
-    attach_r1 <= attach_r;
-
-always @(posedge wclk)
-    suspend_r <= suspend;
-
-always @(posedge wclk)
-    suspend_r1 <= suspend_r;
-
-always @(posedge wclk)
-    usb_reset_r <= #1 usb_reset;
-
-always @(posedge wclk)
-    rx_err_r <= #1 rx_err;
-
-always @(posedge wclk)
-    nse_err_r <= #1 nse_err;
-
-always @(posedge wclk)
-    pid_cs_err_r <= #1 pid_cs_err;
-
-always @(posedge wclk)
-    crc5_err_r <= #1 crc5_err;
-
-assign  attach = !attach_r1 & attach_r;
-assign  deattach = attach_r1 & !attach_r;
-assign  suspend_start = !suspend_r1 & suspend_r;
-assign  suspend_end   = suspend_r1 & !suspend_r;
-
-always @(posedge wclk)
-    if(!rst | int_src_re)   int_srcb8 <= #1 0;
-    else
-    if(usb_reset_r)     int_srcb8 <= #1 1;
-
-always @(posedge wclk)
-    if(!rst | int_src_re)   int_srcb7 <= #1 0;
-    else
-    if(rx_err_r)        int_srcb7 <= #1 1;
-
-always @(posedge wclk)
-    if(!rst | int_src_re)   int_srcb6 <= #1 0;
-    else
-    if(deattach)        int_srcb6 <= #1 1;
-
-always @(posedge wclk)
-    if(!rst | int_src_re)   int_srcb5 <= #1 0;
-    else
-    if(attach)      int_srcb5 <= #1 1;
-
-always @(posedge wclk)
-    if(!rst | int_src_re)   int_srcb4 <= #1 0;
-    else
-    if(suspend_end)     int_srcb4 <= #1 1;
-
-always @(posedge wclk)
-    if(!rst | int_src_re)   int_srcb3 <= #1 0;
-    else
-    if(suspend_start)   int_srcb3 <= #1 1;
-
-always @(posedge wclk)
-    if(!rst | int_src_re)   int_srcb2 <= #1 0;
-    else
-    if(nse_err_r)       int_srcb2 <= #1 1;
-
-always @(posedge wclk)
-    if(!rst | int_src_re)   int_srcb1 <= #1 0;
-    else
-    if(pid_cs_err_r)    int_srcb1 <= #1 1;
-
-always @(posedge wclk)
-    if(!rst | int_src_re)   int_srcb0 <= #1 0;
-    else
-    if(crc5_err_r)      int_srcb0 <= #1 1;
-
-always @(posedge wclk)
-   begin
-    int_srca15 <= #1 ep15_inta | ep15_intb;
-    int_srca14 <= #1 ep14_inta | ep14_intb;
-    int_srca13 <= #1 ep13_inta | ep13_intb;
-    int_srca12 <= #1 ep12_inta | ep12_intb;
-    int_srca11 <= #1 ep11_inta | ep11_intb;
-    int_srca10 <= #1 ep10_inta | ep10_intb;
-    int_srca09 <= #1 ep9_inta | ep9_intb;
-    int_srca08 <= #1 ep8_inta | ep8_intb;
-    int_srca07 <= #1 ep7_inta | ep7_intb;
-    int_srca06 <= #1 ep6_inta | ep6_intb;
-    int_srca05 <= #1 ep5_inta | ep5_intb;
-    int_srca04 <= #1 ep4_inta | ep4_intb;
-    int_srca03 <= #1 ep3_inta | ep3_intb;
-    int_srca02 <= #1 ep2_inta | ep2_intb;
-    int_srca01 <= #1 ep1_inta | ep1_intb;
-    int_srca00 <= #1 ep0_inta | ep0_intb;
-   end
-
-///////////////////////////////////////////////////////////////////
-//
-// Endpoint Register Files
-//
-
-ep_rf   u0( .clk(           clk         ),
-        .wclk(          wclk            ),
-        .rst(           rst         ),
-        .adr(           adr1:0        ),
-        .re(            ep0_re          ),
-        .we(            ep0_we          ),
-        .din(           din         ),
-        .dout(          ep0_dout        ),
-        .inta(          ep0_inta        ),
-        .intb(          ep0_intb        ),
-        .dma_req(       dma_req0      ),
-        .dma_ack(       dma_ack0      ),
-        .idin(          idin            ),
-        .ep_sel(        ep_sel          ),
-        .ep_match(      ep0_match       ),
-        .buf0_rl(       buf0_rl         ),
-        .buf0_set(      buf0_set        ),
-        .buf1_set(      buf1_set        ),
-        .uc_bsel_set(       uc_bsel_set     ),
-        .uc_dpd_set(        uc_dpd_set      ),
-        .int_buf1_set(      int_buf1_set        ),
-        .int_buf0_set(      int_buf0_set        ),
-        .int_upid_set(      int_upid_set        ),
-        .int_crc16_set(     int_crc16_set       ),
-        .int_to_set(        int_to_set      ),
-        .int_seqerr_set(    int_seqerr_set      ),
-        .csr(           ep0_csr         ),
-        .buf0(          ep0_buf0        ),
-        .buf1(          ep0_buf1        ),
-        .dma_in_buf_sz1(    ep0_dma_in_buf_sz1  ),
-        .dma_out_buf_avail( ep0_dma_out_buf_avail   )
-        );
-
-ep_rf   u1( .clk(           clk         ),
-        .wclk(          wclk            ),
-        .rst(           rst         ),
-        .adr(           adr1:0        ),
-        .re(            ep1_re          ),
-        .we(            ep1_we          ),
-        .din(           din         ),
-        .dout(          ep1_dout        ),
-        .inta(          ep1_inta        ),
-        .intb(          ep1_intb        ),
-        .dma_req(       dma_req1      ),
-        .dma_ack(       dma_ack1      ),
-        .idin(          idin            ),
-        .ep_sel(        ep_sel          ),
-        .ep_match(      ep1_match       ),
-        .buf0_rl(       buf0_rl         ),
-        .buf0_set(      buf0_set        ),
-        .buf1_set(      buf1_set        ),
-        .uc_bsel_set(       uc_bsel_set     ),
-        .uc_dpd_set(        uc_dpd_set      ),
-        .int_buf1_set(      int_buf1_set        ),
-        .int_buf0_set(      int_buf0_set        ),
-        .int_upid_set(      int_upid_set        ),
-        .int_crc16_set(     int_crc16_set       ),
-        .int_to_set(        int_to_set      ),
-        .int_seqerr_set(    int_seqerr_set      ),
-        .csr(           ep1_csr         ),
-        .buf0(          ep1_buf0        ),
-        .buf1(          ep1_buf1        ),
-        .dma_in_buf_sz1(    ep1_dma_in_buf_sz1  ),
-        .dma_out_buf_avail( ep1_dma_out_buf_avail   )
-        );
-
-ep_rf   u2( .clk(           clk         ),
-        .wclk(          wclk            ),
-        .rst(           rst         ),
-        .adr(           adr1:0        ),
-        .re(            ep2_re          ),
-        .we(            ep2_we          ),
-        .din(           din         ),
-        .dout(          ep2_dout        ),
-        .inta(          ep2_inta        ),
-        .intb(          ep2_intb        ),
-        .dma_req(       dma_req2      ),
-        .dma_ack(       dma_ack2      ),
-        .idin(          idin            ),
-        .ep_sel(        ep_sel          ),
-        .ep_match(      ep2_match       ),
-        .buf0_rl(       buf0_rl         ),
-        .buf0_set(      buf0_set        ),
-        .buf1_set(      buf1_set        ),
-        .uc_bsel_set(       uc_bsel_set     ),
-        .uc_dpd_set(        uc_dpd_set      ),
-        .int_buf1_set(      int_buf1_set        ),
-        .int_buf0_set(      int_buf0_set        ),
-        .int_upid_set(      int_upid_set        ),
-        .int_crc16_set(     int_crc16_set       ),
-        .int_to_set(        int_to_set      ),
-        .int_seqerr_set(    int_seqerr_set      ),
-        .csr(           ep2_csr         ),
-        .buf0(          ep2_buf0        ),
-        .buf1(          ep2_buf1        ),
-        .dma_in_buf_sz1(    ep2_dma_in_buf_sz1  ),
-        .dma_out_buf_avail( ep2_dma_out_buf_avail   )
-        );
-
-ep_rf   u3( .clk(           clk         ),
-        .wclk(          wclk            ),
-        .rst(           rst         ),
-        .adr(           adr1:0        ),
-        .re(            ep3_re          ),
-        .we(            ep3_we          ),
-        .din(           din         ),
-        .dout(          ep3_dout        ),
-        .inta(          ep3_inta        ),
-        .intb(          ep3_intb        ),
-        .dma_req(       dma_req3      ),
-        .dma_ack(       dma_ack3      ),
-        .idin(          idin            ),
-        .ep_sel(        ep_sel          ),
-        .ep_match(      ep3_match       ),
-        .buf0_rl(       buf0_rl         ),
-        .buf0_set(      buf0_set        ),
-        .buf1_set(      buf1_set        ),
-        .uc_bsel_set(       uc_bsel_set     ),
-        .uc_dpd_set(        uc_dpd_set      ),
-        .int_buf1_set(      int_buf1_set        ),
-        .int_buf0_set(      int_buf0_set        ),
-        .int_upid_set(      int_upid_set        ),
-        .int_crc16_set(     int_crc16_set       ),
-        .int_to_set(        int_to_set      ),
-        .int_seqerr_set(    int_seqerr_set      ),
-        .csr(           ep3_csr         ),
-        .buf0(          ep3_buf0        ),
-        .buf1(          ep3_buf1        ),
-        .dma_in_buf_sz1(    ep3_dma_in_buf_sz1  ),
-        .dma_out_buf_avail( ep3_dma_out_buf_avail   )
-        );
-
-ep_rf   u4( .clk(           clk         ),
-        .wclk(          wclk            ),
-        .rst(           rst         ),
-        .adr(           adr1:0        ),
-        .re(            ep4_re          ),
-        .we(            ep4_we          ),
-        .din(           din         ),
-        .dout(          ep4_dout        ),
-        .inta(          ep4_inta        ),
-        .intb(          ep4_intb        ),
-        .dma_req(       dma_req4      ),
-        .dma_ack(       dma_ack4      ),
-        .idin(          idin            ),
-        .ep_sel(        ep_sel          ),
-        .ep_match(      ep4_match       ),
-        .buf0_rl(       buf0_rl         ),
-        .buf0_set(      buf0_set        ),
-        .buf1_set(      buf1_set        ),
-        .uc_bsel_set(       uc_bsel_set     ),
-        .uc_dpd_set(        uc_dpd_set      ),
-        .int_buf1_set(      int_buf1_set        ),
-        .int_buf0_set(      int_buf0_set        ),
-        .int_upid_set(      int_upid_set        ),
-        .int_crc16_set(     int_crc16_set       ),
-        .int_to_set(        int_to_set      ),
-        .int_seqerr_set(    int_seqerr_set      ),
-        .csr(           ep4_csr         ),
-        .buf0(          ep4_buf0        ),
-        .buf1(          ep4_buf1        ),
-        .dma_in_buf_sz1(    ep4_dma_in_buf_sz1  ),
-        .dma_out_buf_avail( ep4_dma_out_buf_avail   )
-        );
-
-ep_rf   u5( .clk(           clk         ),
-        .wclk(          wclk            ),
-        .rst(           rst         ),
-        .adr(           adr1:0        ),
-        .re(            ep5_re          ),
-        .we(            ep5_we          ),
-        .din(           din         ),
-        .dout(          ep5_dout        ),
-        .inta(          ep5_inta        ),
-        .intb(          ep5_intb        ),
-        .dma_req(       dma_req5      ),
-        .dma_ack(       dma_ack5      ),
-        .idin(          idin            ),
-        .ep_sel(        ep_sel          ),
-        .ep_match(      ep5_match       ),
-        .buf0_rl(       buf0_rl         ),
-        .buf0_set(      buf0_set        ),
-        .buf1_set(      buf1_set        ),
-        .uc_bsel_set(       uc_bsel_set     ),
-        .uc_dpd_set(        uc_dpd_set      ),
-        .int_buf1_set(      int_buf1_set        ),
-        .int_buf0_set(      int_buf0_set        ),
-        .int_upid_set(      int_upid_set        ),
-        .int_crc16_set(     int_crc16_set       ),
-        .int_to_set(        int_to_set      ),
-        .int_seqerr_set(    int_seqerr_set      ),
-        .csr(           ep5_csr         ),
-        .buf0(          ep5_buf0        ),
-        .buf1(          ep5_buf1        ),
-        .dma_in_buf_sz1(    ep5_dma_in_buf_sz1  ),
-        .dma_out_buf_avail( ep5_dma_out_buf_avail   )
-        );
-
-ep_rf   u6( .clk(           clk         ),
-        .wclk(          wclk            ),
-        .rst(           rst         ),
-        .adr(           adr1:0        ),
-        .re(            ep6_re          ),
-        .we(            ep6_we          ),
-        .din(           din         ),
-        .dout(          ep6_dout        ),
-        .inta(          ep6_inta        ),
-        .intb(          ep6_intb        ),
-        .dma_req(       dma_req6      ),
-        .dma_ack(       dma_ack6      ),
-        .idin(          idin            ),
-        .ep_sel(        ep_sel          ),
-        .ep_match(      ep6_match       ),
-        .buf0_rl(       buf0_rl         ),
-        .buf0_set(      buf0_set        ),
-        .buf1_set(      buf1_set        ),
-        .uc_bsel_set(       uc_bsel_set     ),
-        .uc_dpd_set(        uc_dpd_set      ),
-        .int_buf1_set(      int_buf1_set        ),
-        .int_buf0_set(      int_buf0_set        ),
-        .int_upid_set(      int_upid_set        ),
-        .int_crc16_set(     int_crc16_set       ),
-        .int_to_set(        int_to_set      ),
-        .int_seqerr_set(    int_seqerr_set      ),
-        .csr(           ep6_csr         ),
-        .buf0(          ep6_buf0        ),
-        .buf1(          ep6_buf1        ),
-        .dma_in_buf_sz1(    ep6_dma_in_buf_sz1  ),
-        .dma_out_buf_avail( ep6_dma_out_buf_avail   )
-        );
-
-ep_rf   u7( .clk(           clk         ),
-        .wclk(          wclk            ),
-        .rst(           rst         ),
-        .adr(           adr1:0        ),
-        .re(            ep7_re          ),
-        .we(            ep7_we          ),
-        .din(           din         ),
-        .dout(          ep7_dout        ),
-        .inta(          ep7_inta        ),
-        .intb(          ep7_intb        ),
-        .dma_req(       dma_req7      ),
-        .dma_ack(       dma_ack7      ),
-        .idin(          idin            ),
-        .ep_sel(        ep_sel          ),
-        .ep_match(      ep7_match       ),
-        .buf0_rl(       buf0_rl         ),
-        .buf0_set(      buf0_set        ),
-        .buf1_set(      buf1_set        ),
-        .uc_bsel_set(       uc_bsel_set     ),
-        .uc_dpd_set(        uc_dpd_set      ),
-        .int_buf1_set(      int_buf1_set        ),
-        .int_buf0_set(      int_buf0_set        ),
-        .int_upid_set(      int_upid_set        ),
-        .int_crc16_set(     int_crc16_set       ),
-        .int_to_set(        int_to_set      ),
-        .int_seqerr_set(    int_seqerr_set      ),
-        .csr(           ep7_csr         ),
-        .buf0(          ep7_buf0        ),
-        .buf1(          ep7_buf1        ),
-        .dma_in_buf_sz1(    ep7_dma_in_buf_sz1  ),
-        .dma_out_buf_avail( ep7_dma_out_buf_avail   )
-        );
-
-assign ep8_match = 0;
-assign ep9_match = 0;
-assign ep10_match = 0;
-assign ep11_match = 0;
-assign ep12_match = 0;
-assign ep13_match = 0;
-assign ep14_match = 0;
-assign ep15_match = 0;
-
-endmodule
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/sci_alu_comb_calltf_shell.v Deleted

@@ -1,40 +0,0 @@
-/**********************************************************************
- * $scientific_alu example -- Verilog HDL shell module
- *
- * Scientific ALU C model, combinational logic version.
- *
- * Note: The Verilog language does not permit floating point numbers
- * to be connected to module ports.  However, the language provides
- * built-in system functions which convert real numbers to 64-bit
- * vectors, and vice-versa, so the real values can be passed through
- * a module the port connection. These built-in system functions are
- * $realtobits() and $bitstoreal().
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module scientific_alu(a_in, b_in, opcode,
-                      result_out, exception, error);
-  input  63:0 a_in, b_in;
-  input   3:0 opcode;
-  output 63:0 result_out;
-  output        exception, error;
-
-  real          a, b, result; // real variables used in this module
-  reg           exception, error;
-
-  // convert real numbers to/from 64-bit vector port connections
-  assign result_out = $realtobits(result);
-  always @(a_in) a  = $bitstoreal(a_in);
-  always @(b_in) b  = $bitstoreal(b_in);
-
-  //call the PLI application which interfaces to the C model
-  //using combinational logic input sensitivity  
-  always @(a or b or opcode)
-    $scientific_alu(a, b, opcode, result, exception, error);
-
-endmodule

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/sci_alu_comb_calltf_test.v Deleted

@@ -1,48 +0,0 @@
-/**********************************************************************
- * $scientific_alu example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $scientific_alu C model PLI 
- * application.  This test uses the Scientific Alu as a combinational
- * logic device.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-
-`include "sci_alu_comb_calltf_shell.v"
-
-`timescale 1ns / 1ns
-module test;
-
-  reg   4:0 opcode;
-  wire        excep, err;
-  real        a, b, result;
-  wire 63:0 a_in, b_in, result_out;
-
-  // convert real numbers to/from 64-bit vector port connections
-  always @(result_out) result = $bitstoreal(result_out);
-  assign a_in = $realtobits(a);
-  assign b_in = $realtobits(b);
-
-  scientific_alu i1 (a_in, b_in, opcode3:0, result_out, excep, err);
-
-  initial
-    begin
-      $timeformat(-9,0," ns",7);
-      $monitor("At %t: result=%.2f \t excep=%b  err=%b  a=%.1f  b=%.1f  opcode=%h",
-               $time, result, excep, err, a, b, opcode3:0);
-      a = 16.0;
-      b =  2.0;
-      for (opcode=0; opcode<=15; opcode=opcode+1)
-        #1 ;
-      
-      #10 $display("\n");
-      $finish;
-    end
-
-endmodule
-
-/*********************************************************************/

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/sci_alu_comb_misctf_shell.v Deleted

@@ -1,39 +0,0 @@
-/**********************************************************************
- * $scientific_alu example -- Verilog HDL shell module
- *
- * Scientific ALU C model, combinational logic version.
- *
- * Note: The Verilog language does not permit floating point numbers
- * to be connected to module ports.  However, the language provides
- * built-in system functions which convert real numbers to 64-bit
- * vectors, and vice-versa, so the real values can be passed through
- * a module the port connection. These built-in system functions are
- * $realtobits() and $bitstoreal().
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module scientific_alu(a_in, b_in, opcode,
-                      result_out, exception, error);
-  input  63:0 a_in, b_in;
-  input   3:0 opcode;
-  output 63:0 result_out;
-  output        exception, error;
-
-  real          a, b, result; // real variables used in this module
-  reg           exception, error;
-
-  // convert real numbers to/from 64-bit vector port connections
-  assign result_out = $realtobits(result);
-  always @(a_in) a  = $bitstoreal(a_in);
-  always @(b_in) b  = $bitstoreal(b_in);
-
-  //call the PLI application which interfaces to the C model  
-  initial
-    $scientific_alu(a, b, opcode, result, exception, error);
-
-endmodule

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/sci_alu_comb_misctf_test.v Deleted

@@ -1,48 +0,0 @@
-/**********************************************************************
- * $scientific_alu example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $scientific_alu C model PLI 
- * application.  This test uses the Scientific Alu as a combinational
- * logic device.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-
-`include "sci_alu_comb_misctf_shell.v"
-
-`timescale 1ns / 1ns
-module test;
-
-  reg   4:0 opcode;
-  wire        excep, err;
-  real        a, b, result;
-  wire 63:0 a_in, b_in, result_out;
-
-  // convert real numbers to/from 64-bit vector port connections
-  always @(result_out) result = $bitstoreal(result_out);
-  assign a_in = $realtobits(a);
-  assign b_in = $realtobits(b);
-
-  scientific_alu i1 (a_in, b_in, opcode3:0, result_out, excep, err);
-
-  initial
-    begin
-      $timeformat(-9,0," ns",7);
-      $monitor("At %t: result=%.2f \t excep=%b  err=%b  a=%.1f  b=%.1f  opcode=%h",
-               $time, result, excep, err, a, b, opcode3:0);
-      a = 16.0;
-      b =  2.0;
-      for (opcode=0; opcode<=15; opcode=opcode+1)
-        #1 ;
-      
-      #10 $display("\n");
-      $finish;
-    end
-
-endmodule
-
-/*********************************************************************/

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/sci_alu_combinational_shell.v Deleted

@@ -1,39 +0,0 @@
-/**********************************************************************
- * $scientific_alu example -- Verilog HDL shell module
- *
- * Scientific ALU C model, combinational logic version.
- *
- * Note: The Verilog language does not permit floating point numbers
- * to be connected to module ports.  However, the language provides
- * built-in system functions which convert real numbers to 64-bit
- * vectors, and vice-versa, so the real values can be passed through
- * a module the port connection. These built-in system functions are
- * $realtobits() and $bitstoreal().
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module scientific_alu(a_in, b_in, opcode,
-                      result_out, exception, error);
-  input  63:0 a_in, b_in;
-  input   3:0 opcode;
-  output 63:0 result_out;
-  output        exception, error;
-
-  real          a, b, result; // real variables used in this module
-  reg           exception, error;
-
-  // convert real numbers to/from 64-bit vector port connections
-  assign result_out = $realtobits(result);
-  always @(a_in) a  = $bitstoreal(a_in);
-  always @(b_in) b  = $bitstoreal(b_in);
-
-  //call the PLI application which interfaces to the C model
-  initial
-    $scientific_alu(a, b, opcode, result, exception, error);
-
-endmodule

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/sci_alu_combinational_test.v Deleted

@@ -1,48 +0,0 @@
-/**********************************************************************
- * $scientific_alu example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $scientific_alu C model PLI 
- * application.  This test uses the Scientific Alu as a combinational
- * logic device.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-
-`include "sci_alu_combinational_shell.v"
-
-`timescale 1ns / 1ns
-module test;
-
-  reg   4:0 opcode;
-  wire        excep, err;
-  real        a, b, result;
-  wire 63:0 a_in, b_in, result_out;
-
-  // convert real numbers to/from 64-bit vector port connections
-  always @(result_out) result = $bitstoreal(result_out);
-  assign a_in = $realtobits(a);
-  assign b_in = $realtobits(b);
-
-  scientific_alu i1 (a_in, b_in, opcode3:0, result_out, excep, err);
-
-  initial
-    begin
-      $timeformat(-9,0," ns",7);
-      $monitor("At %t: result=%.2f \t excep=%b  err=%b  a=%.1f  b=%.1f  opcode=%h",
-               $time, result, excep, err, a, b, opcode3:0);
-      a = 16.0;
-      b =  2.0;
-      for (opcode=0; opcode<=15; opcode=opcode+1)
-        #1 ;
-      
-      #10 $display("\n");
-      $finish;
-    end
-
-endmodule
-
-/*********************************************************************/

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/sci_alu_latched_shell.v Deleted

@@ -1,40 +0,0 @@
-/**********************************************************************
- * $scientific_alu example -- Verilog HDL shell module
- *
- * Scientific ALU C model, latched logic version.
- *
- * Note: The Verilog language does not permit floating point numbers
- * to be connected to module ports.  However, the language provides
- * built-in system functions which convert real numbers to 64-bit
- * vectors, and vice-versa, so the real values can be passed through
- * a module the port connection. These built-in system functions are
- * $realtobits() and $bitstoreal().
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module scientific_alu(enable, a_in, b_in, opcode,
-                      result_out, exception, error);
-  input         enable;
-  input  63:0 a_in, b_in;
-  input   3:0 opcode;
-  output 63:0 result_out;
-  output        exception, error;
-
-  real          a, b, result; // real variables used in this module
-  reg           exception, error;
-
-  // convert real numbers to/from 64-bit vector port connections
-  assign result_out = $realtobits(result);
-  always @(a_in) a  = $bitstoreal(a_in);
-  always @(b_in) b  = $bitstoreal(b_in);
-
-  //call the PLI application which interfaces to the C model  
-  initial
-    $scientific_alu(enable, a, b, opcode, result, exception, error);
-
-endmodule

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/sci_alu_latched_test.v Deleted

@@ -1,55 +0,0 @@
-/**********************************************************************
- * $scientific_alu example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $scientific_alu C model PLI 
- * application.  This test uses the Scientific Alu as a latched
- * logic device.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
- 
-`include "sci_alu_latched_shell.v"
-
-`timescale 1ns / 1ns
-module test;
-
-  reg   4:0 opcode;
-  reg         enable;
-  wire        excep, err;
-  real        a, b, result1, result2;
-  wire 63:0 a_in, b_in, result_out1, result_out2;
-
-  // convert real numbers to/from 64-bit vector port connections
-  always @(result_out1) result1 = $bitstoreal(result_out1);
-  always @(result_out2) result2 = $bitstoreal(result_out2);
-  assign a_in = $realtobits(a);
-  assign b_in = $realtobits(b);
-
-  scientific_alu i1 (enable, a_in, b_in,  opcode3:0, result_out1, excep, err);
-  scientific_alu i2 (enable, a_in, b_in, ~opcode3:0, result_out2, excep, err);
-
-  initial
-    begin
-      $timeformat(-9,0," ns",7);
-      $monitor("At %t: result1=%.2f \tresult2=%.2f \t  excep=%b  err=%b  a=%.1f  b=%.1f  opcode=%h, enable=%b",
-               $time, result1, result2, excep, err, a, b, opcode3:0, enable);
-      enable = 1;
-      a = 16.0;
-      b =  2.0;
-      for (opcode=0; opcode<=15; opcode=opcode+1)
-        #1 ;
-      
-      #10 $display("");
-      enable = 0;
-
-      #10 $display("\n");
-      $finish;
-    end
-
-endmodule
-
-/*********************************************************************/

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/sci_alu_sequential_shell.v Deleted

@@ -1,40 +0,0 @@
-/**********************************************************************
- * $scientific_alu example -- Verilog HDL shell module
- *
- * Scientific ALU C model, sequential logic version.
- *
- * Note: The Verilog language does not permit floating point numbers
- * to be connected to module ports.  However, the language provides
- * built-in system functions which convert real numbers to 64-bit
- * vectors, and vice-versa, so the real values can be passed through
- * a module the port connection. These built-in system functions are
- * $realtobits() and $bitstoreal().
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module scientific_alu(clock, a_in, b_in, opcode,
-                      result_out, exception, error);
-  input         clock;
-  input  63:0 a_in, b_in;
-  input   3:0 opcode;
-  output 63:0 result_out;
-  output        exception, error;
-
-  real          a, b, result; // real variables used in this module
-  reg           exception, error;
-
-  // convert real numbers to/from 64-bit vector port connections
-  assign result_out = $realtobits(result);
-  always @(a_in) a  = $bitstoreal(a_in);
-  always @(b_in) b  = $bitstoreal(b_in);
-
-  //call the PLI application which interfaces to the C model  
-  initial
-    $scientific_alu(clock, a, b, opcode, result, exception, error);
-
-endmodule

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/sci_alu_sequential_test.v Deleted

@@ -1,52 +0,0 @@
-/**********************************************************************
- * $scientific_alu example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $scientific_alu C model PLI 
- * application.  This test uses the Scientific Alu as a sequential
- * logic device.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
- 
-`include "sci_alu_sequential_shell.v"
-
-`timescale 1ns / 1ns
-module test;
-
-  reg   4:0 opcode;
-  reg         clk;
-  wire        excep, err;
-  real        a, b, result;
-  wire 63:0 a_in, b_in, result_out;
-
-  // convert real numbers to/from 64-bit vector port connections
-  always @(result_out) result = $bitstoreal(result_out);
-  assign a_in = $realtobits(a);
-  assign b_in = $realtobits(b);
-
-  scientific_alu i1 (clk, a_in, b_in, opcode3:0, result_out, excep, err);
-
-  always #5 clk = ~clk;
-  
-  initial
-    begin
-      $timeformat(-9,0," ns",7);
-      $monitor("At %t: result=%.2f \t excep=%b  err=%b  a=%.1f  b=%.1f  opcode=%h",
-               $time, result, excep, err, a, b, opcode3:0);
-      clk = 0;
-      a = 16.0;
-      b =  2.0;
-      for (opcode=0; opcode<=15; opcode=opcode+1)
-        @(negedge clk) ;
-      
-      #10 $display("\n");
-     $finish;
-    end
-
-endmodule
-
-/*********************************************************************/

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/sci_alu_synchronized_shell.v Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/sci_alu_synchronized_test.v Deleted

@@ -1,50 +0,0 @@
-/**********************************************************************
- * $scientific_alu example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $scientific_alu C model PLI 
- * application.  This test uses the Scientific Alu as a combinational
- * logic device.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
- 
-`include "sci_alu_synchronized_shell.v"
-
-`timescale 1ns / 1ns
-module test;
-
-  reg   4:0 opcode;
-  wire        excep, err;
-  real        a, b, result1, result2;
-  wire 63:0 a_in, b_in, result_out1, result_out2;
-
-  // convert real numbers to/from 64-bit vector port connections
-  always @(result_out1) result1 = $bitstoreal(result_out1);
-  always @(result_out2) result2 = $bitstoreal(result_out2);
-  assign a_in = $realtobits(a);
-  assign b_in = $realtobits(b);
-
-  scientific_alu i1 (a_in, b_in,  opcode3:0, result_out1, excep, err);
-  scientific_alu i2 (a_in, b_in, ~opcode3:0, result_out2, excep, err);
-
-  initial
-    begin
-      $timeformat(-9,0," ns",7);
-      $monitor("At %t: result1=%.2f \tresult2=%.2f \t  excep=%b  err=%b  a=%.1f  b=%.1f  opcode=%h",
-               $time, result1, result2, excep, err, a, b, opcode3:0);
-      a = 16.0;
-      b =  2.0;
-      for (opcode=0; opcode<=15; opcode=opcode+1)
-        #1 ;
-      
-      #10 $display("\n");
-     $finish;
-    end
-
-endmodule
-
-/*********************************************************************/

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/sci_alu_with_delays_shell.v Deleted

@@ -1,76 +0,0 @@
-/**********************************************************************
- * $scientific_alu example -- Verilog HDL shell module
- *
- * Scientific ALU C model, combinational logic version with pin-to-pin
- * path delays.  The path delays are represented using a Verilog 
- * specify block.
- *
- * NOTES:
- * - Note: The Verilog language does not permit floating point numbers
- *   to be connected to module ports.  However, the language provides
- *   built-in system functions which convert real numbers to 64-bit
- *   vectors, and vice-versa, so the real values can be passed through
- *   a module the port connection. These built-in system functions are
- *   $realtobits() and $bitstoreal().
- *
- * - Some Verilog simulators require that path delays to be used with
- *   models where all ports are connected to uni-directional
- *   primitives with nets data types connected to the inputs an outputs
- *   of the primitives.  This model satisfies this restriction by
- *   adding buffers to all input and output ports.
- *
- * - This shell module uses the array of instances from the IEEE 1364
- *   Verilog standard.  Some simulators do not support this construct,
- *   and may require using a separate instance statement for each bit
- *   of a vector.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 100ps
-module scientific_alu(a_in, b_in, opcode_in,
-                      result_out, exception, error);
-  output 63:0 result_out;
-  output        exception, error;
-  input  63:0 a_in, b_in;
-  input   3:0 opcode_in;
-
-  wire   63:0 result_out, result_vector;
-  wire   63:0 a_in, a_vector;
-  wire   63:0 b_in, b_vector;
-  wire    3:0 opcode_in, opcode_vector;
-  wire          exception, error;
-
-  reg           exception_reg, error_reg;
-  real          a, b, result; // real variables used in this module
-
-  // convert real numbers to/from 64-bit vector port connections
-  assign result_vector = $realtobits(result);
-  always @(a_vector)  a = $bitstoreal(a_vector);
-  always @(b_vector)  b = $bitstoreal(b_vector);
-
-  //call the PLI application which interfaces to the C model  
-  initial
-    $scientific_alu(a, b, opcode_vector,
-                    result, exception_reg, error_reg);
-
-  specify
-    (a_in, b_in *> result_out, exception, error) = (5.6, 4.7);
-    (opcode_in  *> result_out, exception, error) = (3.4, 3.8);
-  endspecify
-
-  // add buffers to all ports, with nets connected to each buffer
-  // (this example uses the array of instance syntax in the
-  // from the IEEE 1364-1995 Verilog standard
-  buf result_buf63:0 (result_out, result_vector);
-  buf excep_buf        (exception,  exception_reg);
-  buf error_buf        (error,      error_reg);
-
-  buf a_buf63:0      (a_vector, a_in);
-  buf b_buf63:0      (b_vector, b_in);
-  buf opcode_buf3:0  (opcode_vector, opcode_in);
-
-endmodule

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/sci_alu_with_delays_test.v Deleted

@@ -1,48 +0,0 @@
-/**********************************************************************
- * $scientific_alu example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $scientific_alu C model PLI 
- * application.  This test uses the Scientific Alu as a combinational
- * logic device.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-
-`include "sci_alu_with_delays_shell.v"
-
-`timescale 1ns / 1ns
-module test;
-
-  reg   4:0 opcode;
-  wire        excep, err;
-  real        a, b, result;
-  wire 63:0 a_in, b_in, result_out;
-
-  // convert real numbers to/from 64-bit vector port connections
-  always @(result_out) result = $bitstoreal(result_out);
-  assign a_in = $realtobits(a);
-  assign b_in = $realtobits(b);
-
-  scientific_alu i1 (a_in, b_in, opcode3:0, result_out, excep, err);
-
-  initial
-    begin
-      $timeformat(-9,0," ns",7);
-      $monitor("At %t: result=%.2f \t excep=%b  err=%b  a=%.1f  b=%.1f  opcode=%h",
-               $time, result, excep, err, a, b, opcode3:0);
-      a = 16.0;
-      b =  2.0;
-      for (opcode=0; opcode<=15; opcode=opcode+1)
-        #10 ;
-      
-      #10 $display("\n");
-      $finish;
-    end
-
-endmodule
-
-/*********************************************************************/

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/set_mipd_delays_test.v Deleted

@@ -1,52 +0,0 @@
-/**********************************************************************
- * $set_mipd_delays example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $set_mipd_delays PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 10ps
-module test;
-  reg  a, b, ci, clk;
-  wire sum, co;
-
-  addbit i1 (a, b, ci, sum, co);
-
-  initial
-    begin
-      $set_mipd_delays(i1.a, 2.3, 2.4, 2.5);
-      a = 0; b = 0; ci = 0;
-      #10 a = 1;
-      #10 b = 1;
-      #10 a = 0;
-      #1 $finish;
-    end
-    
-  initial
-    $monitor("At %0.2f: a=%d b=%d ci%d sum=%d co=%d",
-             $realtime, a, b, ci, sum, co);
-    
-endmodule
-
-/*** A gate level 1 bit adder model ***/
-`timescale 1ns / 10ps
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci, sum, co,
-        n1, n2, n3;
-
-  xor  (n1, a, b);
-  xor  (sum, n1, ci);
-  and  (n2, a, b);
-  and  (n3, n1, ci);
-  or   (co, n2, n3);
-  
-endmodule
-/*********************************************************************/
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/show_all_nets_test.v Deleted

@@ -1,49 +0,0 @@
-/**********************************************************************
- * $show_all_nets example -- Verilog test bench source code
- *
- * Verilog test bench to test the $show_all_nets PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module top;
-  reg  2:0 test;
-  tri  1:0 results;
-
-  addbit i1 (test0, test1, test2, results0, results1);
-
-  initial
-    begin
-      test = 3'b000;
-      #10 test = 3'b001;
-
-      #10 $show_all_nets(top);
-      #10 $show_all_nets(i1);
-
-      #10 $stop;
-      #10 $finish;
-    end
-endmodule
-
-/*** A gate level 1 bit adder model ***/
-`timescale 1ns / 1ns
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci, sum, co,
-        n1, n2, n3;
-
-  xor    (n1, a, b);
-  xor #2 (sum, n1, ci);
-  and    (n2, a, b);
-  and    (n3, n1, ci);
-  or  #2 (co, n2, n3);
-
-endmodule
-/*********************************************************************/
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/show_all_signals1_test.v Deleted

@@ -1,47 +0,0 @@
-/**********************************************************************
- * $show_all_signals example -- Verilog test bench source code
- *
- * Verilog test bench to test the $show_all_signals PLI application on
- * a 1-bit adder modeled using RTL code.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module top;
-  integer    test;
-  tri  1:0 results;
-
-  addbit i1 (test0, test1, test2, results0, results1);
-
-  initial
-    begin
-      test = 3'b000;
-      #10 test = 3'b001;
-
-      #10 $show_all_signals1(top);
-      #10 $show_all_signals1(i1);
-
-      #10 $stop;
-      #10 $finish;
-    end
-endmodule
-
-/*** An RTL level 1 bit adder model ***/
-`timescale 1ns / 1ns
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci;
-  reg   sum, co;
-
-  always @(a or b or ci)
-    {co, sum} = a + b + ci;
-
-endmodule
-/*********************************************************************/
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/show_all_signals2_test.v Deleted

@@ -1,49 +0,0 @@
-/**********************************************************************
- * $show_all_signals example -- Verilog test bench source code
- *
- * Verilog test bench to test the $show_all_signals PLI application on
- * a 1-bit adder modeled using RTL code.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module top;
-  integer    test;
-  tri  1:0 results;
-
-  addbit i1 (test0, test1, test2, results0, results1);
-
-  initial
-    begin
-      test = 3'b000;
-      #10 test = 3'b001;
-
-      #10 $show_all_signals2();
-      #10 $show_all_signals2(top.i1);
-
-//      #10 $stop;
-      #10 $finish;
-    end
-endmodule
-
-/*** An RTL level 1 bit adder model ***/
-`timescale 1ns / 1ns
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci;
-  reg   sum, co;
-
-  always @(a or b or ci)
-    {co, sum} = a + b + ci;
-
-  always @(sum)
-    $show_all_signals2;
-
-endmodule
-/*********************************************************************/

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/show_all_signals3_test.v Deleted

@@ -1,49 +0,0 @@
-/**********************************************************************
- * $show_all_signals example -- Verilog test bench source code
- *
- * Verilog test bench to test the $show_all_signals PLI application on
- * a 1-bit adder modeled using RTL code.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module top;
-  integer    test;
-  tri  1:0 results;
-
-  addbit i1 (test0, test1, test2, results0, results1);
-
-  initial
-    begin
-      test = 3'b000;
-      #10 test = 3'b001;
-
-      #10 $show_all_signals3(top.i1, ); /* second arg is null */
-
-//      #10 $stop;
-      #10 $finish;
-    end
-endmodule
-
-/*** An RTL level 1 bit adder model ***/
-`timescale 1ns / 1ns
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci;
-  reg   sum, co;
-
-  always @(a or b or ci)
-    {co, sum} = a + b + ci;
-
-  always @(sum)
-    $show_all_signals3;
-
-endmodule
-/*********************************************************************/
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/show_all_signals_1_test.v Deleted

@@ -1,56 +0,0 @@
-/**********************************************************************
- * $show_all_signals example 1 -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $show_all_signals PLI application on
- * a 1-bit adder modeled using gate primitives.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module top;
-  tri  1:0 results;
-  integer    test;
-  real       foo;
-  time       bar;
-
-  addbit i1 (test0, test1, test2, results0, results1);
-
-  initial
-    begin
-      test = 3'b000;
-      foo = 3.14;
-      bar = 0;
-      bar63:60 = 4'hF;
-      bar35:32 = 4'hA;
-      bar31:28 = 4'hC;
-      bar03:00 = 4'hE;
-      
-      #1 test = 3'b011;
-
-      #1 $show_all_signals(top);
-      #1 $show_all_signals(i1);
-
-      #1 $stop;
-      #1 $finish;
-    end
-endmodule
-
-/*** An RTL level 1 bit adder model ***/
-`timescale 1ns / 1ns
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci;
-  reg   sum, co;
-
-  always @(a or b or ci)
-    {co, sum} = a + b + ci;
-
-endmodule
-/*********************************************************************/
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/show_all_signals_2_test.v Deleted

@@ -1,51 +0,0 @@
-/**********************************************************************
- * $show_all_signals example 2 -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $show_all_signals PLI application on
- * a 1-bit adder modeled using gate primitives.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module top;
-  integer    test;
-  tri  1:0 results;
-
-  addbit i1 (test0, test1, test2, results0, results1);
-
-  initial
-    begin: local
-      reg foobar;
-      test = 3'b000;
-      #1 test = 3'b011;
-
-      #1 $show_all_signals;
-      #1 $show_all_signals(top.i1);
-
-//      #1 $stop;
-      #1 $finish;
-    end
-endmodule
-
-/*** An RTL level 1 bit adder model ***/
-`timescale 1ns / 1ns
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci;
-  reg   sum, co;
-
-  always @(a or b or ci)
-    {co, sum} = a + b + ci;
-
-  always @(sum)
-    $show_all_signals();
-
-endmodule
-/*********************************************************************/
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/show_all_signals_3_test.v Deleted

@@ -1,49 +0,0 @@
-/**********************************************************************
- * $show_all_signals example 3 -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $show_all_signals PLI application on
- * a 1-bit adder modeled using gate primitives.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module top;
-  integer    test;
-  tri  1:0 results;
-
-  addbit i1 (test0, test1, test2, results0, results1);
-
-  initial
-    begin
-      test = 3'b000;
-      #1 test = 3'b001;
-
-      #1 $show_all_signals(top.i1, ,top); /* second arg is null */
-
-//      #1 $stop;
-      #1 $finish;
-    end
-endmodule
-
-/*** An RTL level 1 bit adder model ***/
-`timescale 1ns / 1ns
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci;
-  reg   sum, co;
-
-  always @(a or b or ci)
-    {co, sum} = a + b + ci;
-
-  always @(sum)
-    $show_all_signals;
-
-endmodule
-/*********************************************************************/
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/show_value_test.v Deleted

@@ -1,57 +0,0 @@
-/**********************************************************************
- * $show_value example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the $show_value PLI application on a 
- * 1-bit adder modeled using gate primitives.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-  reg  a, b, ci, clk;
-  wire sum, co;
-
-  addbit i1 (a, b, ci, sum, co);
-
-  initial
-    begin
-//      $monitor("At %0d: \t a=%b  b=%b  ci=%b  sum=%b  co=%b",
-//               $time, a, b, ci, sum, co);
-      clk = 0;
-      a = 0;
-      b = 0;
-      ci = 0;
-      #10 a = 1;
-      #10 b = 1;
-
-      $show_value(sum);
-      $show_value(co);
-      $show_value(i1.n3);
-
-      #10 $stop;
-      $finish;
-    end
-endmodule
-
-/*** A gate level 1 bit adder model ***/
-`timescale 1ns / 1ns
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci, sum, co,
-        n1, n2, n3;
-
-  xor    (n1, a, b);
-  xor #2 (sum, n1, ci);
-  and    (n2, a, b);
-  and    (n3, n1, ci);
-  or  #2 (co, n2, n3);
-
-endmodule
-/**********************************************************************/
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/sig_gen.v Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/simple_core.v Deleted

@@ -1,125 +0,0 @@
-/* simple_core */
-// Author Andrew Laffely
-// Last modified: 12 Feb 03
-
-module adder_core (reset, hold, in_ready, out_ready, data_in, data_out, read, write, in_addr, out_addr);
-input reset, hold;                // External control signals
-input 2:0 in_ready, out_ready;  // Input and Output port ready registers
-input 31:0 data_in;             // Input data
-
-output read, write;               // Read and Write signals
-output 31:0 data_out;
-output 1:0 in_addr, out_addr;   // Port addresses.
-reg read, write; 
-reg 31:0 data_out;
-reg 1:0 in_addr, out_addr;   
-
-reg 31:0 opA, opB;
-reg 31:0 res;
-reg ops_ready, res_ready; //Internal flow conrol
-reg stall, go;
-  
-reg lclock;
-initial
-begin
-	#3 lclock = 1'b0;
-	forever #47 lclock = ~lclock;  // Use 10 or 20 or 40 or 80 etc.
-end
-
-/*********************** READ DATA *****************************/
-always @ (posedge lclock)
-  begin
-	#1 if(((!ops_ready)||(!stall))&&(!hold)&&(!reset))  
-	// Do not read anymore if full and stalled
-		if(in_readyin_addr)  // check port
-			read = 1;
-  end
-
-always @ (negedge lclock)
-  begin
-	read = 0;
-  end
-
-always @ (negedge read)
-  begin
-    if (!reset)
-      begin
-	if ((in_addr0)&&(!hold))
-	  begin
-		opB=data_in;
-		ops_ready=1;
-	  end
-	else
-	  begin
-		opA=data_in;
-	  end
-	$display("In Core=%h addr=%b ops_ready=%b",data_in, in_addr, ops_ready);
-	#1 in_addr0=~in_addr0;   // next data	
-      end
-  end
-/********************* End READ DATA ***************************/
-
-/*********************** Write DATA ****************************/
-always @ (posedge lclock)
-  begin
-	if((res_ready)&&(!hold)&&(!reset)) // wait until the pipe is full
-		if(out_readyout_addr)  // check port
-			write = 1;
-  end
-
-always @ (negedge lclock)
-  begin
-	write = 0;
-  end
-
-always @ (negedge write)
-  begin
-	if(!reset)
-	  begin
-		data_out=res;
-		$display("Out Core=%h out_addr=%b ops_ready=%b",data_out, out_addr, ops_ready);
-	res_ready=0;
-	  end
-  end
-/******************** End Write DATA ***************************/
-
-/************************ Reset ********************************/
-always @ (reset)
-  begin
-	read=0;
-	write=0;
-	in_addr=0;
-	out_addr=0;
-	ops_ready=0;
-	res_ready=0;
-	stall = 0;
-  end
-/*********************** End Reset *****************************/
-
-/******************* Core flow Control *************************/
-// stall tells the pipeline to stop adding and stop taking in data
-always @ (posedge lclock)
-  begin
-	if(!out_readyout_addr)
-		stall = 1;
-  end
-
-always @ (posedge out_readyout_addr)
-  begin
-	stall=0;
-  end
-/******************* End flow Control *************************/
-
-/************************ Proccessing *************************/
-always @ (posedge lclock)
-  begin
-	if((ops_ready)&&(!stall)&&(!hold))
-	  begin
-		res=opA+opB;  //Wow this 32 bit adder is fast
-		res_ready=1;
-		ops_ready=0;
-		
-	  end
-  end
-/********************* End Proccessing *************************/
-endmodule

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/splitter.v Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/sqrt32.v Deleted

@@ -1,400 +0,0 @@
-// sqrt32.v unsigned integer sqrt 32-bits computing unsigned integer 16-bits
-//   sqrt(00000000000000000000000000000100) = 0000000000000010   sqrt(4)=2
-//   sqrt(00000000000000000000000001000000) = 0000000000001000   sqrt(64)=8
-
-`timescale 1ns/1ns
-
-module Sm(x, y, b, u, d, bo);  // subtractor multiplexor 
-  input  x;
-  input  y;
-  input  b;
-  input  u;
-  output d;
-  output bo;
-
-  wire t011, t111, t010, t001, t100, td;
-  wire x_, y_, b_, u_, if_td, if_x;
-
-  // circuits of Sm
-  not notx(x_, x);
-  not noty(y_, y);
-  not notb(b_, b);
-  and a011(t011, x_, y,  b );
-  and a111(t111, x,  y,  b );
-  and a010(t010, x_, y,  b_);
-  and a001(t001, x_, y_, b );
-  and a100(t100, x,  y_, b_);
-  or  #1 or1(bo, t011, t111, t010, t001);
-  or  or2(td, t100, t001, t010, t111);
-  not notu(u_, u);  // four gate mux
-  and atd(if_td, td, u); 
-  and ax (if_x,   x, u_);
-  or  #1 or3(d, if_td, if_x);
-endmodule  // Sm
-
-module Sb(x, y, b, bo);  // subtractor multiplexor stage b 
-  input  x;
-  input  y;
-  input  b;
-  output bo;
-
-  wire t011, t111, t010, t001;
-  wire x_, y_, b_;
-
-  // circuits of Sb
-  not n01(x_, x);
-  not n02(y_, y);
-  not n03(b_, b);
-  and a011(t011, x_, y,  b);
-  and a111(t111, x,  y,  b);
-  and a010(t010, x_, y,  b_);
-  and a001(t001, x_, y_,  b);
-  or #1 bor(bo, t011, t111, t010, t001);
-endmodule  // Sb
-
-module S1(x, b, u, d, bo);  // subtractor multiplexor stage 1
-  input  x;
-  input  b;
-  input  u;
-  output d;
-  output bo;
-
-  wire t100, t001, td;
-  wire x_, b_, u_, if_td, if_x;
-
-  // circuits of S1
-  not not1(x_, x);
-  not not2(b_, b);
-  and a011(t001, x_,  b);
-  and a100(t100, x,   b_);
-  buf #1 buf1(bo, t001);
-  or or1(td, t100, t001);
-  not notu(u_, u);  // four gate mux
-  and atd(if_td, td, u); 
-  and ax (if_x,   x, u_);
-  or  #1 or3(d, if_td, if_x);
-endmodule  //  S1
-
-module S0(x, u, d, bo);    // subtractor multiplexor stage 0
-  input  x;
-  input  u;
-  output d;
-  output bo;
-
-  wire u_, if_bo, if_x;
-
-  // circuits of S0
-  not #1 n1(bo, x);
-  not notu(u_, u);  // four gate mux
-  and atd(if_bo, bo, u); 
-  and ax (if_x,   x, u_);
-  or  #1 or3(d, if_bo, if_x);
-endmodule  //  S0
-
-module Sn(x, b, bo); // subtractor multiplexor stage n 
-  input  x;
-  input  b;
-  output bo;
-
-  wire x_;
-
-  // circuits of Sn, complemented
-  not  n00(x_, x);
-  nand #1 n01(bo, x_, b);
-endmodule  //  Sn
-
-module S0b(x, bo);   // subtractor multiplexor stage 0b
-  input  x;
-  output bo;
-
-  // circuits of S0b
-  not #1 n0(bo, x);
-endmodule  //  S0b
-
-module S1b(x, b, bo);     // subtractor multiplexor stage 1b
-  input  x;
-  input  b;
-  output bo;
-
-  wire x_;
-
-  // circuits of S1b
-  not n00(x_, x);
-  and #1 n01(bo, x_, b);
-endmodule  //  S1b
-
-
-module sqrt32(P, U);
-  input 31:0 P;
-  output 15:0 U;
-
-  wire b0000, b0001, b0002, b0003, b0004, b0005, b0006, b0007, b0008,
-       b0009, b0010, b0011, b0012, b0013, b0014, b0015, b0016, b0017;  
-  wire x0102, x0103, x0104, x0105, x0106, x0107, x0108, x0109, x0110,
-       x0111, x0112, x0113, x0114, x0115, x0116, x0117;  
-  wire b0102, b0103, b0104, b0105, b0106, b0107, b0108, b0109, b0110,
-       b0111, b0112, b0113, b0114, b0115, b0116, b0117, b0118;
-  wire x0204, x0205, x0206, x0207, x0208, x0209, x0210, x0211, x0212,
-       x0213, x0214, x0215, x0216, x0217, x0218;  
-  wire b0204, b0205, b0206, b0207, b0208, b0209, b0210, b0211, b0212,
-       b0213, b0214, b0215, b0216, b0217, b0218, b0219;  
-  wire x0306, x0307, x0308, x0309, x0310, x0311, x0312, x0313, x0314,
-       x0315, x0316, x0317, x0318, x0319;  
-  wire b0306, b0307, b0308, b0309, b0310, b0311, b0312, b0313, b0314,
-       b0315, b0316, b0317, b0318, b0319, b0320;  
-  wire x0408, x0409, x0410, x0411, x0412, x0413, x0414, x0415, x0416,
-       x0417, x0418, x0419, x0420;  
-  wire b0408, b0409, b0410, b0411, b0412, b0413, b0414, b0415, b0416,
-       b0417, b0418, b0419, b0420, b0421;  
-  wire x0510, x0511, x0512, x0513, x0514, x0515, x0516, x0517, x0518,
-       x0519, x0520, x0521;  
-  wire b0510, b0511, b0512, b0513, b0514, b0515, b0516, b0517, b0518,
-       b0519, b0520, b0521, b0522;  
-  wire x0612, x0613, x0614, x0615, x0616, x0617, x0618, x0619, x0620,
-       x0621, x0622;  
-  wire b0612, b0613, b0614, b0615, b0616, b0617, b0618, b0619, b0620,
-       b0621, b0622, b0623;  
-  wire x0714, x0715, x0716, x0717, x0718, x0719, x0720, x0721, x0722,
-       x0723;  
-  wire b0714, b0715, b0716, b0717, b0718, b0719, b0720, b0721, b0722,
-       b0723, b0724;  
-  wire x0816, x0817, x0818, x0819, x0820, x0821, x0822, x0823, x0824;  
-  wire b0816, b0817, b0818, b0819, b0820, b0821, b0822, b0823, b0824,
-       b0825;  
-  wire x0918, x0919, x0920, x0921, x0922, x0923, x0924, x0925;  
-  wire b0918, b0919, b0920, b0921, b0922, b0923, b0924, b0925, b0926;  
-  wire x1020, x1021, x1022, x1023, x1024, x1025, x1026;  
-  wire b1020, b1021, b1022, b1023, b1024, b1025, b1026, b1027;  
-  wire x1122, x1123, x1124, x1125, x1126, x1127;  
-  wire b1122, b1123, b1124, b1125, b1126, b1127, b1128;  
-  wire x1224, x1225, x1226, x1227, x1228;  
-  wire b1224, b1225, b1226, b1227, b1228, b1229;  
-  wire x1326, x1327, x1328, x1329;  
-  wire b1326, b1327, b1328, b1329, b1330;  
-  wire x1428, x1429, x1430;  
-  wire b1428, b1429, b1430, b1431;  
-  wire x1530, x1531;  
-  wire b1530, b1531, bxx;  
-
-  //                              x      y      b      u      d      bo
-  S0 s1530(P30,               b1531, x1530, b1530);
-  S1 s1531(P31,        b1530, b1531, x1531, bxx );
-  not n1(b1531, bxx);
-
-  S0 s1428(P28,               b1431, x1428, b1428);
-  S1 s1429(P29,        b1428, b1431, x1429, b1429);
-  Sm s1430(x1530, b1531, b1429, b1431, x1430, b1430);
-  Sn s1431(x1531,        b1430,               b1431);
-  
-  S0 s1326(P26,               b1330, x1326, b1326);
-  S1 s1327(P27,        b1326, b1330, x1327, b1327);
-  Sm s1328(x1428, b1431, b1327, b1330, x1328, b1328);
-  Sm s1329(x1429, b1531, b1328, b1330, x1329, b1329);
-  Sn s1330(x1430,        b1329,               b1330);
-
-  S0 s1224(P24,               b1229, x1224, b1224);
-  S1 s1225(P25,        b1224, b1229, x1225, b1225);
-  Sm s1226(x1326, b1330, b1225, b1229, x1226, b1226);
-  Sm s1227(x1327, b1431, b1226, b1229, x1227, b1227);
-  Sm s1228(x1328, b1531, b1227, b1229, x1228, b1228);
-  Sn s1229(x1329,        b1228,               b1229);
-
-  S0 s1122(P22,               b1128, x1122, b1122);
-  S1 s1123(P23,        b1122, b1128, x1123, b1123);
-  Sm s1124(x1224, b1229, b1123, b1128, x1124, b1124);
-  Sm s1125(x1225, b1330, b1124, b1128, x1125, b1125);
-  Sm s1126(x1226, b1431, b1125, b1128, x1126, b1126);
-  Sm s1127(x1227, b1531, b1126, b1128, x1127, b1127);
-  Sn s1128(x1228,        b1127,               b1128);
-
-  S0 s1020(P20,               b1027, x1020, b1020);
-  S1 s1021(P21,        b1020, b1027, x1021, b1021);
-  Sm s1022(x1122, b1128, b1021, b1027, x1022, b1022);
-  Sm s1023(x1123, b1229, b1022, b1027, x1023, b1023);
-  Sm s1024(x1124, b1330, b1023, b1027, x1024, b1024);
-  Sm s1025(x1125, b1431, b1024, b1027, x1025, b1025);
-  Sm s1026(x1126, b1531, b1025, b1027, x1026, b1026);
-  Sn s1027(x1127,        b1026,               b1027);
-
-  S0 s0918(P18,               b0926, x0918, b0918);
-  S1 s0919(P19,        b0918, b0926, x0919, b0919);
-  Sm s0920(x1020, b1027, b0919, b0926, x0920, b0920);
-  Sm s0921(x1021, b1128, b0920, b0926, x0921, b0921);
-  Sm s0922(x1022, b1229, b0921, b0926, x0922, b0922);
-  Sm s0923(x1023, b1330, b0922, b0926, x0923, b0923);
-  Sm s0924(x1024, b1431, b0923, b0926, x0924, b0924);
-  Sm s0925(x1025, b1531, b0924, b0926, x0925, b0925);
-  Sn s0926(x1026,        b0925,               b0926);
-
-  S0 s0816(P16,               b0825, x0816, b0816);
-  S1 s0817(P17,        b0816, b0825, x0817, b0817);
-  Sm s0818(x0918, b0926, b0817, b0825, x0818, b0818);
-  Sm s0819(x0919, b1027, b0818, b0825, x0819, b0819);
-  Sm s0820(x0920, b1128, b0819, b0825, x0820, b0820);
-  Sm s0821(x0921, b1229, b0820, b0825, x0821, b0821);
-  Sm s0822(x0922, b1330, b0821, b0825, x0822, b0822);
-  Sm s0823(x0923, b1431, b0822, b0825, x0823, b0823);
-  Sm s0824(x0924, b1531, b0823, b0825, x0824, b0824);
-  Sn s0825(x0925,        b0824,               b0825);
-
-  S0 s0714(P14,               b0724, x0714, b0714);
-  S1 s0715(P15,        b0714, b0724, x0715, b0715);
-  Sm s0716(x0816, b0825, b0715, b0724, x0716, b0716);
-  Sm s0717(x0817, b0926, b0716, b0724, x0717, b0717);
-  Sm s0718(x0818, b1027, b0717, b0724, x0718, b0718);
-  Sm s0719(x0819, b1128, b0718, b0724, x0719, b0719);
-  Sm s0720(x0820, b1229, b0719, b0724, x0720, b0720);
-  Sm s0721(x0821, b1330, b0720, b0724, x0721, b0721);
-  Sm s0722(x0822, b1431, b0721, b0724, x0722, b0722);
-  Sm s0723(x0823, b1531, b0722, b0724, x0723, b0723);
-  Sn s0724(x0824,        b0723,               b0724);
- 
-  S0 s0612(P12,               b0623, x0612, b0612);
-  S1 s0613(P13,        b0612, b0623, x0613, b0613);
-  Sm s0614(x0714, b0724, b0613, b0623, x0614, b0614);
-  Sm s0615(x0715, b0825, b0614, b0623, x0615, b0615);
-  Sm s0616(x0716, b0926, b0615, b0623, x0616, b0616);
-  Sm s0617(x0717, b1027, b0616, b0623, x0617, b0617);
-  Sm s0618(x0718, b1128, b0617, b0623, x0618, b0618);
-  Sm s0619(x0719, b1229, b0618, b0623, x0619, b0619);
-  Sm s0620(x0720, b1330, b0619, b0623, x0620, b0620);
-  Sm s0621(x0721, b1431, b0620, b0623, x0621, b0621);
-  Sm s0622(x0722, b1531, b0621, b0623, x0622, b0622);
-  Sn s0623(x0723,        b0622,               b0623);
-  
-  S0 s0510(P10,               b0522, x0510, b0510);
-  S1 s0511(P11,        b0510, b0522, x0511, b0511);
-  Sm s0512(x0612, b0622, b0511, b0522, x0512, b0512);
-  Sm s0513(x0613, b0723, b0512, b0522, x0513, b0513);
-  Sm s0514(x0614, b0825, b0513, b0522, x0514, b0514);
-  Sm s0515(x0615, b0926, b0514, b0522, x0515, b0515);
-  Sm s0516(x0616, b1027, b0515, b0522, x0516, b0516);
-  Sm s0517(x0617, b1128, b0516, b0522, x0517, b0517);
-  Sm s0518(x0618, b1229, b0517, b0522, x0518, b0518);
-  Sm s0519(x0619, b1330, b0518, b0522, x0519, b0519);
-  Sm s0520(x0620, b1431, b0519, b0522, x0520, b0520);
-  Sm s0521(x0621, b1531, b0520, b0522, x0521, b0521);
-  Sn s0522(x0622,        b0521,               b0522);
-
-  S0 s0408(P8,                b0421, x0408, b0408);
-  S1 s0409(P9,         b0408, b0421, x0409, b0409);
-  Sm s0410(x0510, b0522, b0409, b0421, x0410, b0410);
-  Sm s0411(x0511, b0623, b0410, b0421, x0411, b0411);
-  Sm s0412(x0512, b0724, b0411, b0421, x0412, b0412);
-  Sm s0413(x0513, b0825, b0412, b0421, x0413, b0413);
-  Sm s0414(x0514, b0926, b0413, b0421, x0414, b0414);
-  Sm s0415(x0515, b1027, b0414, b0421, x0415, b0415);
-  Sm s0416(x0516, b1128, b0415, b0421, x0416, b0416);
-  Sm s0417(x0517, b1229, b0416, b0421, x0417, b0417);
-  Sm s0418(x0518, b1330, b0417, b0421, x0418, b0418);
-  Sm s0419(x0519, b1431, b0418, b0421, x0419, b0419);
-  Sm s0420(x0520, b1531, b0419, b0421, x0420, b0420);
-  Sn s0421(x0521,        b0420,               b0421);
-
-  S0 s0306(P6,                b0320, x0306, b0306);
-  S1 s0307(P7,         b0306, b0320, x0307, b0307);
-  Sm s0308(x0408, b0421, b0307, b0320, x0308, b0308);
-  Sm s0309(x0409, b0522, b0308, b0320, x0309, b0309);
-  Sm s0310(x0410, b0623, b0309, b0320, x0310, b0310);
-  Sm s0311(x0411, b0724, b0310, b0320, x0311, b0311);
-  Sm s0312(x0412, b0825, b0311, b0320, x0312, b0312);
-  Sm s0313(x0413, b0926, b0312, b0320, x0313, b0313);
-  Sm s0314(x0414, b1027, b0313, b0320, x0314, b0314);
-  Sm s0315(x0415, b1128, b0314, b0320, x0315, b0315);
-  Sm s0316(x0416, b1229, b0315, b0320, x0316, b0316);
-  Sm s0317(x0417, b1330, b0316, b0320, x0317, b0317);
-  Sm s0318(x0418, b1431, b0317, b0320, x0318, b0318);
-  Sm s0319(x0419, b1531, b0318, b0320, x0319, b0319);
-  Sn s0320(x0420,        b0319,               b0320);
-
-  S0 s0204(P4,                b0219, x0204, b0204);
-  S1 s0205(P5,         b0204, b0219, x0205, b0205);
-  Sm s0206(x0306, b0320, b0205, b0219, x0206, b0206);
-  Sm s0207(x0307, b0421, b0206, b0219, x0207, b0207);
-  Sm s0208(x0308, b0522, b0207, b0219, x0208, b0208);
-  Sm s0209(x0309, b0623, b0208, b0219, x0209, b0209);
-  Sm s0210(x0310, b0724, b0209, b0219, x0210, b0210);
-  Sm s0211(x0311, b0825, b0210, b0219, x0211, b0211);
-  Sm s0212(x0312, b0926, b0211, b0219, x0212, b0212);
-  Sm s0213(x0313, b1027, b0212, b0219, x0213, b0213);
-  Sm s0214(x0314, b1128, b0213, b0219, x0214, b0214);
-  Sm s0215(x0315, b1229, b0214, b0219, x0215, b0215);
-  Sm s0216(x0316, b1330, b0215, b0219, x0216, b0216);
-  Sm s0217(x0317, b1431, b0216, b0219, x0217, b0217);
-  Sm s0218(x0318, b1531, b0217, b0219, x0218, b0218);
-  Sn s0219(x0319,        b0218,               b0219);
-
-  S0 s0102(P2,                b0118, x0102, b0102);
-  S1 s0103(P3,         b0102, b0118, x0103, b0103);
-  Sm s0104(x0204, b0219, b0103, b0118, x0104, b0104);
-  Sm s0105(x0205, b0320, b0104, b0118, x0105, b0105);
-  Sm s0106(x0206, b0421, b0105, b0118, x0106, b0106);
-  Sm s0107(x0207, b0522, b0106, b0118, x0107, b0107);
-  Sm s0108(x0208, b0623, b0107, b0118, x0108, b0108);
-  Sm s0109(x0209, b0724, b0108, b0118, x0109, b0109);
-  Sm s0110(x0210, b0825, b0109, b0118, x0110, b0110);
-  Sm s0111(x0211, b0926, b0110, b0118, x0111, b0111);
-  Sm s0112(x0212, b1027, b0111, b0118, x0112, b0112);
-  Sm s0113(x0213, b1128, b0112, b0118, x0113, b0113);
-  Sm s0114(x0214, b1229, b0113, b0118, x0114, b0114);
-  Sm s0115(x0215, b1330, b0114, b0118, x0115, b0115);
-  Sm s0116(x0216, b1431, b0115, b0118, x0116, b0116);
-  Sm s0117(x0217, b1531, b0116, b0118, x0117, b0117);
-  Sn s0118(x0218,        b0117,               b0118);
-
-  S0b s0000(P0,                              b0000);
-  S1b s0001(P1,         b0000,               b0001);
-  Sb s0002(x0102, b0118, b0001,               b0002);
-  Sb s0003(x0103, b0219, b0002,               b0003);
-  Sb s0004(x0104, b0320, b0003,               b0004);
-  Sb s0005(x0105, b0421, b0004,               b0005);
-  Sb s0006(x0106, b0522, b0005,               b0006);
-  Sb s0007(x0107, b0623, b0006,               b0007);
-  Sb s0008(x0108, b0724, b0007,               b0008);
-  Sb s0009(x0109, b0825, b0008,               b0009);
-  Sb s0010(x0110, b0926, b0009,               b0010);
-  Sb s0011(x0111, b1027, b0010,               b0011);
-  Sb s0012(x0112, b1128, b0011,               b0012);
-  Sb s0013(x0113, b1229, b0012,               b0013);
-  Sb s0014(x0114, b1330, b0013,               b0014);
-  Sb s0015(x0115, b1431, b0014,               b0015);
-  Sb s0016(x0116, b1531, b0015,               b0016);
-  Sn s0017(x0117,        b0016,               b0017);
-
-  buf b0 (U0,  b0017); // set output bits
-  buf b1 (U1,  b0118);
-  buf b2 (U2,  b0219);
-  buf b3 (U3,  b0320);
-  buf b4 (U4,  b0421);
-  buf b5 (U5,  b0522);
-  buf b6 (U6,  b0623);
-  buf b7 (U7,  b0724);
-  buf b8 (U8,  b0825);
-  buf b9 (U9,  b0926);
-  buf b10(U10, b1027);
-  buf b11(U11, b1128);
-  buf b12(U12, b1229);
-  buf b13(U13, b1330);
-  buf b14(U14, b1431);
-  buf b15(U15, b1531);        
-endmodule  //  sqrt32
-
-
-module tsqrt32;  // test driver
-  reg 31:0 P;
-  wire 15:0 U;
-  reg 7:0 temp;
-  integer i;
-  
-  // test of sqrt32
-  sqrt32 s1(P, U);    // instantiate module
-  initial
-    begin  // test cases
-      for(i=0; i<256; i=i+1)
-        begin
-          temp = i;
-          P = {temp,temp,temp,temp};
-          #257 $display("sqrt( %b )= %b", P, U);
-        end
-    end
-endmodule  //  tsqrt32

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/sqrt8m.v Deleted

@@ -1,186 +0,0 @@
-// sqrt8m.v     unsigned integer sqrt 8-bits computing unsigned integer 4-bits
-//             sqrt(00000100) = 0010   sqrt(4)=2
-//             sqrt(01000000) = 1000   sqrt(64)=8
-
-`timescale 1ns/1ns
-
-module Sm(x, y, b, u, d, bo);  // subtractor multiplexor 
-  input  x;
-  input  y;
-  input  b;
-  input  u;
-  output d;
-  output bo;
-
-  wire t011, t111, t010, t001, t100, td;
-  wire x_, y_, b_, u_, if_td, if_x;
-
-  // circuits of Sm
-  not notx(x_, x);
-  not noty(y_, y);
-  not notb(b_, b);
-  and a011(t011, x_, y,  b );
-  and a111(t111, x,  y,  b );
-  and a010(t010, x_, y,  b_);
-  and a001(t001, x_, y_, b );
-  and a100(t100, x,  y_, b_);
-  or  #1 or1(bo, t011, t111, t010, t001);
-  or  or2(td, t100, t001, t010, t111);
-  not notu(u_, u);  // four gate mux
-  and atd(if_td, td, u); 
-  and ax (if_x,   x, u_);
-  or  #1 or3(d, if_td, if_x);
-endmodule  // Sm
-
-
-module Sb(x, y, b, bo);  // subtractor multiplexor stage b 
-  input  x;
-  input  y;
-  input  b;
-  output bo;
-
-  wire t011, t111, t010, t001;
-  wire x_, y_, b_;
-
-  // circuits of Sb
-  not n01(x_, x);
-  not n02(y_, y);
-  not n03(b_, b);
-  and a011(t011, x_, y,  b);
-  and a111(t111, x,  y,  b);
-  and a010(t010, x_, y,  b_);
-  and a001(t001, x_, y_,  b);
-  or #1 bor(bo, t011, t111, t010, t001);
-endmodule  // Sb
-
-module S1(x, b, u, d, bo);  // subtractor multiplexor stage 1
-  input  x;
-  input  b;
-  input  u;
-  output d;
-  output bo;
-
-  wire t100, t001, td;
-  wire x_, b_, u_, if_td, if_x;
-
-  // circuits of S1
-  not not1(x_, x);
-  not not2(b_, b);
-  and a011(t001, x_,  b);
-  and a100(t100, x,   b_);
-  buf #1 buf1(bo, t001);
-  or or1(td, t100, t001);
-  not notu(u_, u);  // four gate mux
-  and atd(if_td, td, u); 
-  and ax (if_x,   x, u_);
-  or  #1 or3(d, if_td, if_x);
-endmodule  //  S1
-
-module S0(x, u, d, bo);    // subtractor multiplexor stage 0
-  input  x;
-  input  u;
-  output d;
-  output bo;
-
-  wire u_, if_bo, if_x;
-
-  // circuits of S0
-  not #1 n1(bo, x);
-  not notu(u_, u);  // four gate mux
-  and atd(if_bo, bo, u); 
-  and ax (if_x,   x, u_);
-  or  #1 or3(d, if_bo, if_x);
-endmodule  //  S0
-
-module Sn(x, b, bo); // subtractor multiplexor stage n 
-  input  x;
-  input  b;
-  output bo;
-
-  wire x_;
-
-  // circuits of Sn, complemented
-  not  n00(x_, x);
-  nand #1 n01(bo, x_, b);
-endmodule  //  Sn
-
-module S0b(x, bo);   // subtractor multiplexor stage 0b
-  input  x;
-  output bo;
-
-  // circuits of S0b
-  not #1 n0(bo, x);
-endmodule  //  S0b
-
-module S1b(x, b, bo);     // subtractor multiplexor stage 1b
-  input  x;
-  input  b;
-  output bo;
-
-  wire x_;
-
-  // circuits of S1b
-  not n00(x_, x);
-  and #1 n01(bo, x_, b);
-endmodule  //  S1b
-
-
-module psqrt(P, U);
-  input 7:0 P;
-  output 3:0 U;
-
-  wire b00, b01, b02, b03, b04, b05;  
-  wire x12, x13, x14, x15;  
-  wire b12, b13, b14, b15, b16;  
-  wire x24, x25, x26;  
-  wire b24, b25, b26, b27;  
-  wire x36, x37, bxx;  
-  wire b36, b37;  
-
-  // circuits of psqrt
-  //       x     y    b    u    d    bo
-  S0  s36(P6,           b37, x36, b36);
-  S1  s37(P7,      b36, b37, x37, bxx);
-  not t37(b37,  bxx);
-
-  S0  s24(P4,           b27, x24, b24);
-  S1  s25(P5,      b24, b27, x25, b25);
-  Sm  s26(x36 , b37, b25, b27, x26, b26);
-  Sn  s27(x37 ,      b26,           b27);
-
-  S0  s12(P2,           b16, x12, b12);
-  S1  s13(P3,      b12, b16, x13, b13);
-  Sm  s14(x24 , b27, b13, b16, x14, b14);
-  Sm  s15(x25 , b37, b14, b16, x15, b15);
-  Sn  s16(x26 ,      b15,           b16);
-
-  S0b s00(P0,                     b00);
-  S1b s01(P1,      b00,           b01);
-  Sb  s02(x12 , b16, b01,           b02);
-  Sb  s03(x13 , b27, b02,           b03);
-  Sb  s04(x14 , b37, b03,           b04);
-  Sn  s05(x15 ,      b04,           b05);
-  buf buf1(U0, b05);
-  buf buf2(U1, b16);
-  buf buf3(U2, b27);
-  buf buf4(U3, b37);
-
-endmodule  // psqrt
-
-module sqrt8m;  // test driver
-  reg 7:0 P;
-  wire 3:0 U;
-  integer i;
-  
-  // test of sqrt8m
-  psqrt s1(P, U);    // instantiate module
-  initial
-    begin  // test cases
-      for(i=0; i<256; i=i+1)
-        begin
-          P = i;
-          #40 $display("sqrt( %b )= %b", P, U);
-        end
-    end
-endmodule  //  sqrt8m
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/sr_nv_ctf.v Deleted

@@ -1,124 +0,0 @@
-
-// Module counterflow shift register cell
-module sr_nv_ctf (din, cin, dout, cout);
-
-input
-	din, cin;
-
-output
-	dout, cout;
-reg 
-	dout, cout;
-
-parameter
-	t_hold	= -3,
-	t_setup	= 8,
-	delay = 9,        // delay between cin and dout
-	delay_clk = 14,   // delay between cin and cout
-
-	warning_file=3;   // multichannel description of a warning file
-
-reg
-	dinternal, cinternal,
-	d_state,          	   // internal state at the input d
-	d_set;		   	   // signal determining the moment when
-				   // the state of the d input changes to "1"
-
-integer
-	data_delay,  // delay between d and dinternal
-	clk_delay,   // delay between clk and cinternal
-	out_delay,   // delay between cinternal and out
-	out_value,   // output value in a given clock cycle
-	last_clk_time;	// time when the last clock pulse appeared
-
-initial 
-	begin
-// define delays between inputs & outputs and the corresponding
-//  internal auxiliary registers
-	  	if(t_hold<0)
-		  begin
-	    	  	data_delay = -t_hold;
-	    		clk_delay  = 0;
-			out_delay  = delay;
-		  end
-	  	else
-		  begin
-	   	  	data_delay = 0;
-	    		clk_delay  = t_hold;
-		  	out_delay  = delay-t_hold;
-		  end
-
-// clear internal registers and the output signal
-		dinternal = 0;
-		cinternal = 0;
-		last_clk_time = 0;
-		d_state = 0;
-		d_set = 0;
-		dout = 0;
-		cout = 0;
-	end
-
-
-
-always @(posedge din) 	// Execute at positive edge of din
-	  dinternal <= #(data_delay) din;
-
-always @(posedge cin)  // Execute at positive edge of cin
-	  cinternal <= #(clk_delay) cin;
-
-
-always @(posedge dinternal)
-	begin
-// setting the state of the d input
-                d_state <= d_state | 1'bx;
-		if (dinternal === 1)
-		  d_set <= #(t_hold+t_setup) 1;
-
-		dinternal <= 0;
-	end
-
-always @(posedge d_set)
-	begin
-		if ($stime - last_clk_time >= t_hold+t_setup)
-			d_state = 1;
-		else
-		  begin
-			d_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input D pulse at %0d,",
-			 $stime-data_delay-t_hold-t_setup);
-			$fwrite(warning_file,
-			"\tClock pulse at %0d.\n", last_clk_time-clk_delay);
-		  end
-
-		d_set <= 0;
-	end
-
-
-always @(posedge cinternal)	
-	begin
-// computing the output
-		if (cinternal === 1'bx)
-		  out_value = 1'bx;
-		else
-		  out_value = d_state;
-
-// transfering the result to the output
-		dout <= #(out_delay) out_value;
-		dout <= #(out_delay+2) 0;
-
-		cout <= #(delay_clk-clk_delay) cinternal;
-		cout <= #(delay_clk-clk_delay+2) 0;
-
-// clearing the internal state of the DRO
-		d_state  <= 0;
-
-		cinternal <= 0;
-		last_clk_time = $stime;
-	end
-
-endmodule

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/srcnt.v Deleted

@@ -1,125 +0,0 @@
-// Verilog HDL for "RSFQ.lib", "srcnt" "_functional"
-
-// Module counterflow shift register cell
-module srcnt (din, clkin, dout, clkout);
-
-input
-	din, clkin;
-
-output
-	dout, clkout;
-reg 
-	dout, clkout;
-
-parameter
-	t_hold	= -3,
-	t_setup	= 8,
-	delay = 9,        // delay between clkin and dout
-	delay_clk = 12,   // delay between clkin and clkout
-
-	warning_file=3;   // multichannel description of a warning file
-
-reg
-	dinternal, clkinternal,
-	d_state,          	   // internal state at the input d
-	d_set;		   	   // signal determining the moment when
-				   // the state of the d input changes to "1"
-
-integer
-	data_delay,  // delay between d and dinternal
-	clk_delay,   // delay between clk and clkinternal
-	out_delay,   // delay between clkinternal and out
-	out_value,   // output value in a given clock cycle
-	last_clk_time;	// time when the last clock pulse appeared
-
-initial 
-	begin
-// define delays between inputs & outputs and the corresponding
-//  internal auxiliary registers
-	  	if(t_hold<0)
-		  begin
-	    	  	data_delay = -t_hold;
-	    		clk_delay  = 0;
-			out_delay  = delay;
-		  end
-	  	else
-		  begin
-	   	  	data_delay = 0;
-	    		clk_delay  = t_hold;
-		  	out_delay  = delay-t_hold;
-		  end
-
-// clear internal registers and the output signal
-		dinternal = 0;
-		clkinternal = 0;
-		last_clk_time = 0;
-		d_state = 0;
-		d_set = 0;
-		dout = 0;
-		clkout = 0;
-	end
-
-
-
-always @(posedge din) 	// Execute at positive edge of din
-	  dinternal <= #(data_delay) din;
-
-always @(posedge clkin)  // Execute at positive edge of clkin
-	  clkinternal <= #(clk_delay) clkin;
-
-
-always @(posedge dinternal)
-	begin
-// setting the state of the d input
-                d_state <= d_state | 1'bx;
-		if (dinternal === 1)
-		  d_set <= #(t_hold+t_setup) 1;
-
-		dinternal <= 0;
-	end
-
-always @(posedge d_set)
-	begin
-		if ($stime - last_clk_time >= t_hold+t_setup)
-			d_state = 1;
-		else
-		  begin
-			d_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input D pulse at %0d,",
-			 $stime-data_delay-t_hold-t_setup);
-			$fwrite(warning_file,
-			"\tClock pulse at %0d.\n", last_clk_time-clk_delay);
-		  end
-
-		d_set <= 0;
-	end
-
-
-always @(posedge clkinternal)	
-	begin
-// computing the output
-		if (clkinternal === 1'bx)
-		  out_value = 1'bx;
-		else
-		  out_value = d_state;
-
-// transfering the result to the output
-		dout <= #(out_delay) out_value;
-		dout <= #(out_delay+2) 0;
-
-		clkout <= #(delay_clk-clk_delay) clkinternal;
-		clkout <= #(delay_clk-clk_delay+2) 0;
-
-// clearing the internal state of the DRO
-		d_state  <= 0;
-
-		clkinternal <= 0;
-		last_clk_time = $stime;
-	end
-
-endmodule

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/string.v Deleted

@@ -1,66 +0,0 @@
-//
-// Demonstrate how to display strings for a particular signal.
-// This allows you to see a text string for a bus, which at times, might
-// help out in debugging.  This is not intended for synthesis, of course.
-// Keep these funny "string" signals seperate so we can disable them
-// at synthesis time and so they never impact the circuit.
-//
-//
-module test;
-
-// Declare a register with enough bits for the ASCII string.
-// synopsys translate_off
-reg 9*8-1:0 string_signal; // **** FOR TESTING
-// synopsys translate_on
-
-// Here's the *real* circuit signal
-reg 3:0 shift_register;
-
-reg clk, reset;
-
-// Here's the real circuit
-always @(posedge clk)
-   if (reset) shift_register <= 4'b0001;
-   else       shift_register <= {shift_register2:0, shift_register3};
-
-// Now we assign to our string signal based on the real signal.
-// Disable this code when synthesizing.
-//   
-// synopsys translate_off
-always @(shift_register)
-   case (shift_register)
-      4'b0001: string_signal <= "BIT  ZERO";
-      4'b0010: string_signal <= "BIT   ONE";
-      4'b0100: string_signal <= "BIT   TWO";
-      4'b1000: string_signal <= "BIT THREE";
-      default: string_signal <= "?????????";                  
-   endcase
-// synopsys translate_on
-
-initial begin
-   clk =  0;
-   forever begin
-      #10 clk = ~clk;
-   end
-end
-
-initial begin
-   reset = 0;
-   #2 reset = 1;  
-   #13 reset = 0;
-   #200;
-   $finish;
-end
-
-// Generate VCD file for viewing.
-//
-// Once we are in the Waveform Viewer, just set the format of 'string_signal'
-// to ASCII!
-//
-initial begin
-   $dumpfile ("test_string_signal.vcd");
-   $dumpvars (0,test);   
-end
-
-   
-endmodule

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/t1ff.v Deleted

@@ -1,169 +0,0 @@
-// Verilog HDL for "gates.lib", "t1ff" "_functional"
-// Module T1 flip-flop
-module t1ff (t, wr0, out, rd1);
-
-input
-	t, wr0;
-
-output
-	out, rd1;
-reg 
-	out, rd1;
-
-parameter
-	t_separation = 10,
-	delay=8,
-	t_hold = 7,
-	t_setup = 6,
-	rd1_delay=10,
-
-	warning_file=3;  // multichannel description of a warning file
-
-reg
-	t_internal, wr0_internal, // signals at inputs after i/o stage
-	t_state,  // internal state of T flip-flop
-	sep_clr,  // signal marking the end of the separation zone
-	hs_clr;	  // signal marking the end of the hold/setup zone
-
-
-integer
-	data_delay, 	// delay between t and t_internal
-	wr0_delay, 	// delay between rd and rd_internal
-	t_out_delay, 	// delay between t_internal and out
-	wr0_out_delay,  // delay between rd_internal and out
-	last_t_time,    // time when the last t pulse appeared
-	last_wr0_time,  // time when the last wr0 pulse appeared
-	in_hs,    // number of t pulses in hold/setup zone
-	in_sep,	 // number of pulses within an interval t_sep before 
-		 //  the last data pulse;
-	out_value; // value at the output;
-
-initial 
-	begin
-// define delays between inputs & outputs and the corresponding
-//  internal auxiliary registers
-	  	if(t_hold<0)
-		  begin
-	    	  	data_delay = -t_hold;
-	    		wr0_delay  = 0;
-		  end
-	  	else
-		  begin
-	   	  	data_delay = 0;
-	    		wr0_delay  = t_hold;
-		  end
-		t_out_delay  = delay-data_delay;
-		wr0_out_delay = rd1_delay-wr0_delay;
-
-// clear internal registers and the output signal
-		t_internal = 0;
-		wr0_internal = 0;
-		t_state = 0;
-		in_hs = 0;
-		in_sep = 0;
-		sep_clr = 0;
-		hs_clr = 0;
-		out = 0;
-		rd1 = 0;
-	end
-
-
-always @(posedge t) 	// Execute at positive edge of t
-	  t_internal <= #(data_delay) t;
-
-always @(posedge wr0) 	// Execute at positive edge of t
-	  wr0_internal <= #(wr0_delay) wr0;
-
-
-always @(posedge t_internal)
-	begin
-	  if (in_sep>0)
-	    begin
-	      t_state = 1'bx;
-
-	    // generating a warning
-	      $fwrite(warning_file, 
-	       "Violation of separation time in module %m.\n");
-	      $fwrite(warning_file,
-	       "Input T pulses at %0d and at %0d.\n", last_t_time, 
-	       $stime-data_delay);
-	    end
-	  last_t_time <= $stime-data_delay;
-
-	  out <= #t_out_delay t_state;
-	  out <= #(t_out_delay+2) 0;
-
-	  t_state = t_state ^ 1;
-	  if (t_internal === 1)
-	    begin
-	      in_sep = in_sep + 1;
-	      sep_clr <= #(t_separation) 1;
-	    end
-	  else
-	    t_state = 1'bx;
-
-// setting the state of the t input
-	  if (t_internal === 1)
-	    begin
-	      in_hs = in_hs+1;
-	      hs_clr <= #(t_hold+t_setup) 1;
-	    end
-	  else
-	    t_state = 1'bx;
-
-	  t_internal <= 0;
-	end
-
-
-always @(posedge hs_clr)
-	begin
-		if ($stime - last_wr0_time < t_hold+t_setup)
-		  begin
-			t_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input T pulse at %0d,",
-			 $stime-data_delay-t_hold-t_setup);
-			$fwrite(warning_file,
-			"\tInput WRITE0 pulse at %0d.\n",
-			 last_wr0_time-wr0_delay);
-		  end
-
-		in_hs = in_hs-1;
-		hs_clr <= 0;
-	end
-
-always @(posedge sep_clr)
-	begin
-	  	in_sep = in_sep - 1;
-		sep_clr <= 0;
-	end
-
-
-always @(posedge wr0_internal)	
-	begin
-// computing the output
-		if ((wr0_internal === 1'bx) || (in_hs>0))
-		  out_value = 1'bx;
-		else
-		  out_value = t_state;
-
-// transfering the result to the output
-		rd1 <= #(wr0_out_delay) out_value;
-		rd1 <= #(wr0_out_delay+2) 0;
-
-// clearing the internal state of T1 flip-flop
-		if(in_hs == 0)
-		  t_state  = 0;
-		else
-		  t_state = 1'bx;
-
-		wr0_internal <= 0;
-		last_wr0_time = $stime;
-	end
-
-
-endmodule

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/testcase.v Deleted

@@ -1,80 +0,0 @@
-`timescale 1ns/1ps
-
-module mult_piped_8x8_2sC (a, b, clk, reset, y);
-
-input7:0 a,b;
-input clk,reset;
-output15:0 y;
-
-  //--------------------------------------
-  // Function: always @ posedge clk       
-  //   y(t=0) = a(t-8) * b(t-8)           
-  //                                      
-  // Simulation: PASSED                   
-  // Synthesis: Needs re-timing feature in
-  //            synthesis tool            
-  //                                      
-  //--------------------------------------
-
-reg7:0 aR8:0;
-reg7:0 bR8:0;
-reg15:0 yR8:0;
-
-always @ (posedge clk) // pipeline_stages
-  begin
-   aR7 = aR6;  // pipeline things
-   bR7 = bR6;
-   yR7 = yR6;
-   aR6 = aR5;
-   bR6 = bR5;
-   yR6 = yR5;
-   aR5 = aR4;
-   bR5 = bR4;
-   yR5 = yR4;
-   aR4 = aR3;
-   bR4 = bR3;
-   yR4 = yR3;
-   aR3 = aR2;
-   bR3 = bR2;
-   yR3 = yR2;
-   aR2 = aR1;
-   bR2 = bR1;
-   yR2 = yR1;
-   aR1 = aR0;
-   bR1 = bR0;
-   yR1 = yR0;
-   aR0 = a;
-   bR0 = b;
-            // multiply result (a*b) appears after +clk
-   yR0 = multiply_8x8_2sC (aR0,bR0);
-  end
-
-function15:0 multiply_8x8_2sC;
-input7:0 a,b;
-reg7:0 a_mag,b_mag;
-reg14:0 y_mag;
-reg14:0 y_neg;
-begin
-  case (a7)
-   0: a_mag = a6:0;
-   1: a_mag = 128 - a6:0;        // max(a_mag) = 128, thus 8 bits
-  endcase
-  case (b7)
-    0: b_mag = b6:0;
-    1: b_mag = 128 - b6:0;
-  endcase
-  y_mag = a_mag * b_mag;            // max(y_mag) = 16384, thus 15 bits
-  if ((a7 ^ b7) & (y_mag != 0)) // if (a * b) is -ve AND non-zero
-  begin                             // y_mag >=1, <= 16256, thus need only 14 bits
-    y_neg = 32768 - y_mag13:0;    // max(y_neg) = 32767, thus need 15 bits
-    multiply_8x8_2sC = {1'b1,y_neg}; 
-  end
-  else
-   multiply_8x8_2sC = y_mag;
-end
-endfunction
-
-assign y = multiply_8x8_2sC (a,b); // un_pipelined_output
-assign y = yR7;
-
-endmodule

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/testcase2.v Deleted

@@ -1,144 +0,0 @@
-module tap_controller (tms,
-   tck,
-   trst,
-   sel,
-   enable,
-   test_logic_reset,
-   idle,
-   resetn,
-   shift_ir,
-   update_ir,
-   clock_ir,
-   shift_dr,
-   capture_dr,
-   clock_dr,
-   update_dr);
-
-input   tms;
-input   tck;
-input   trst;
-output  sel;
-output  enable;
-output  test_logic_reset;
-output  idle;
-output  resetn;
-output  shift_ir;
-output  update_ir;
-output  clock_ir;
-output  shift_dr;
-output  capture_dr;
-output  clock_dr;
-output  update_dr;
-wire    sel;
-reg     enable;
-wire    test_logic_reset;
-wire    idle;
-reg     resetn;
-reg     shift_ir;
-wire    update_ir;
-wire    clock_ir;
-reg     shift_dr;
-wire    capture_dr;
-wire    clock_dr;
-wire    update_dr;
-reg     D;
-reg     C;
-reg     B;
-reg     A;
-wire    NA;
-wire    NB;
-wire    NC;
-wire    ND;
-wire    GRST;
-wire    GENB;
-wire    GSIR;
-wire    GSDR;
-wire    tckd;
-wire    trsthi;
-wire    tmsbuf;
-wire    trstnbuf;
-
-initial 
-   begin
-   A = 'b 1;
-   end
-
-initial 
-   begin
-   B = 'b 1;
-   end
-
-initial 
-   begin
-   C = 'b 1;
-   end
-
-initial 
-   begin
-   D = 'b 1;
-   end
-
-always @(posedge trsthi or posedge tckd)
-   begin
-   if (trsthi == 'b 1)
-
-      resetn <= 'b 0; else if (tckd== 'b 1 ) resetn <=GRST; 
-	  
-   end 
-	  
-always @(posedge trsthi or posedge tckd) begin 
-      if (trsthi== 'b 1) enable <='b 0;
-
-      else if (tckd ==  'b 1 ) enable <=GENB; end 
-
-always @(posedge trsthi or posedge tckd) begin 
-      if (trsthi== 'b 1) shift_ir <='b 1;
-
-      else if (tckd ==  'b 1 ) shift_ir <=GSIR; end 
-	  
-
-always @(posedge trsthi or posedge tckd) begin 
-      if (trsthi== 'b 1) shift_dr <='b 1;
-
-      else if (tckd ==  'b 1 ) shift_dr <=GSDR; end 
-	  
-
-always @(posedge trsthi or posedge tck) begin 
-      if (trsthi== 'b 1) D <='b 1;
-
-      else if (tck ==  'b 1 ) D <=ND; end 
-
-always @(posedge trsthi or posedge tck) begin 
-      if (trsthi== 'b 1) C <='b 1;
-
-      else if (tck ==  'b 1 ) C <=NC; end 
-	  
-
-always @(posedge trsthi or posedge tck) begin 
-      if (trsthi== 'b 1) B <='b 1;
-
-      else if (tck ==  'b 1 ) B <=NB; end 
-	  
-
-always @(posedge trsthi or posedge tck) begin 
-      if (trsthi== 'b 1) A <='b 1;
-
-      else if (tck ==  'b 1 ) A <=NA; end 
-
-
-  assign trsthi=~trstnbuf; assign sel=D; assign tckd=~tck; 
-  assign clock_ir=~(~A & B & D & tckd); assign update_ir=A & ~B & C & D & tckd; 
-  assign clock_dr=~(~A & B & ~D & tckd); assign test_logic_reset=A & B & C & D; 
-  assign idle=~A & ~B & C & D; 
-  assign update_dr=A & ~B & C & ~D & tckd; 
-  assign capture_dr=~A & B & C & ~D; 
-  assign tmsbuf=tms; assign trstnbuf=trst; 
-  assign NA=~(~(~tmsbuf & ~C & A) & ~(tmsbuf & ~B) & ~(tmsbuf & ~A) & ~(tmsbuf & C & D)); 
-  assign NB=~(~(~tmsbuf & B & ~A) & ~(~tmsbuf & ~C) & ~(~tmsbuf & ~D & B) 
-       & ~(~tmsbuf & ~D & ~A) & ~(tmsbuf & C & ~B) & ~(tmsbuf & D & C & A)); 
-  assign NC=~(~(C & ~B) & ~(C & A) & ~(tmsbuf & ~B)); 
-  assign ND=~(~(D & ~C) & ~(D & B) & ~(~tmsbuf & C & ~B) & ~(~D & C & ~B & ~A)); 
-  assign GRST=~(A & B & C & D); assign GSIR=~A & B & ~C & D; 
-  assign GSDR=~A & B & ~C & ~D; assign GENB=GSIR | GSDR; 
-
-endmodule // module tap_controller

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/testcase3.v Deleted

@@ -1,375 +0,0 @@
-// A Verilog example taken from comp.lang.verilog
-
-
-//-----------------------Cache Coherence Protocol-----------------------------
-// This finite-state machine (Melay type) reads bus 
-// per cycle and changes the state of each block in cache.
-
-module cache_coherence ( 
-	new_state, 
-	Cache_Sector_Fill, 
-	Invalidate,  
-	AdrRetry,
-	RMS, 
-	RME, 
-	WM, 
-	WH,  
-	SHR, 
-	SHW, 
-	state, 
-	READ_DONE, 
-	clk, 
-	reset, 
-	send_abort, 
-	write_back_done,
-	AllInvDone);
-
-input RMS, RME, WM, WH, SHR, SHW, READ_DONE, clk, 
-      reset, send_abort, write_back_done, AllInvDone;
-
-input 2:0 state;
-
-output 2:0 new_state;
-output Cache_Sector_Fill, Invalidate, AdrRetry;
-
-reg Cache_Sector_Fill, Invalidate, AdrRetry ;
-reg 2:0 new_state; 
-
-// The four possible states (symbolic names) for a sector 
-// in the cache plus 2 mandatory states
-
-parameter /*2:0*/ // synopsys enum state_info
-	INVALID = 3'b000,
-	SHARED_1 = 3'b001,
-	EXCLUSIVE = 3'b010,
-	MODIFIED = 3'b011,
-	Cache_Fill = 3'b100,
-	start_write_back = 3'b101,
-	/* start_write_back = 5, */
-	WaitUntilAllInv = 3'b110;
-
-// Declare current_state and next_state variable.
-reg 2:0 	/* synopsys enum state_info */	present_state;
-reg 2:0	/* synopsys enum state_info */	next_state;
-// synopsys state_vector present_state
-
-/* Combinational */
-always @(present_state or RMS or RME or WM or WH or SHW or READ_DONE 
-         or SHR or write_back_done or AllInvDone or send_abort or state or reset) 
-begin
-	Cache_Sector_Fill = 0; 	// Default values
-	Invalidate = 0; 
-	AdrRetry = 0; 
-	next_state = present_state; 
-	if (reset) next_state = state; else 
-	begin
-	case(present_state) 	// synopsys full_case
-		INVALID: 
-			// ReadMiss (shared/exclusive), Write Miss
-			if (RMS || RME || WM)  			 
-			begin
-				Cache_Sector_Fill = 1;
-				next_state = Cache_Fill ;
-			end
-			else 
-			begin 
-				next_state = INVALID;
-			end
-
-		Cache_Fill:	
-			/* During This State Cache is filled with the sector,
-			   But if any other processor have that copy in modified 
-			   state, it sends an abort signal. If no other cache has
-			   that copy in modified state. Requesting processor waits
-			   for the read from memory to be done.
-			*/
-			if (send_abort) 
-			begin 
-				next_state = INVALID;
-			end
-			else if (READ_DONE) 
-			begin
-				if (RMS) 
-				begin
-					next_state = SHARED_1;
-				end
-				else if (RME) 
-				begin 
-					next_state = EXCLUSIVE;	
-				end
-				else if (WM)
-				begin
-					Invalidate = 1;
-					next_state = WaitUntilAllInv;
-				end 
-				else 
-				begin 
-					next_state = Cache_Fill ;
-				end
-			end	
-			else 
-			begin 
-				next_state = Cache_Fill ;
-			end
-			
-		SHARED_1:	  
-			if (SHW) // Snoop Hit on a Write.
-			begin 
-				next_state = INVALID;		
-			end
-			else if (WH) // Write Hit				
-			begin
-				Invalidate = 1;
-				next_state = WaitUntilAllInv;
-			end 
-			else 
-			begin // Snoop Hit on a Read or Read Hit or any other
-				next_state = SHARED_1; 		
-			end
-
-		WaitUntilAllInv:
-			/* In this state Requesting Processor waits for the 
-			   all other processor's to invalidate its cache copy.
-			*/
-
-			if (AllInvDone) 
-			begin 
-				next_state = MODIFIED;
-			end
-			else 
-			begin 
-				next_state = WaitUntilAllInv;
-			end
-
-		EXCLUSIVE: 
-								
-			if (SHR) // Snoop Hit on a Read:
-			begin
-				AdrRetry = 0;
-				next_state = SHARED_1;  
-			end 					
-			else if (SHW) // Snoop Hit on a Write 
-			begin
-				next_state = INVALID;	
-			end
-			else if (WH) // Write Hit
-			begin
-				next_state = MODIFIED;	
-			end
-			else 
-			begin // Read Hit 
-				next_state = EXCLUSIVE;		
-			end
-
-		MODIFIED:  	
-			if (SHW) // Snoop Hit on a Write 
-			begin
-				next_state = INVALID;		
-			end
-			else if (SHR) // Snoop Hit on a Read 			
-			begin
-				AdrRetry = 1;
-				next_state = start_write_back;
-			end
-			else // Read Hit or Write Hit or anything else.
-			begin
-				next_state = MODIFIED; 		
-			end
-
-		start_write_back: 
-			/* In this state, Processor waits until other processor 
-			   has written back the modified copy.
-			*/
-			if (write_back_done) 
-			begin
-				next_state = SHARED_1; 
-			end
-			else
-			begin 
-				next_state = start_write_back;
-			end
-			
-	endcase
-	end
-	
-end
-
-/* Sequential */
-always @(posedge clk) 
-begin
-	present_state = next_state;
-	new_state = next_state;
-end
-endmodule
-
-
-//--------------Test File: Maintaining Cache coherence in 2-processor Systems------
-/* Test File for Maintaining Cache Coherence in 2-processor system */
-
-module cache;
-
-reg RMS, RME, WM, WH, RH, SHR, SHW, clk, READ_DONE , reset, send_abort, write_back_done, AllInvDone, PA, PB, countE;
-reg 2:0 state, SectorInCacheA, SectorInCacheB;
-reg 3:0 count;
-integer file1;
-
-parameter CYCLE = 10;
-
-wire 2:0 new_state;
-wire Cache_Sector_Fill, Invalidate;
-/*
-cache_coherence u1 (
-	new_state, 
-	Cache_Sector_Fill, 
-	Invalidate, 
-	AdrRetry, 
-	RMS, RME, 
-	WM, WH, 
-	SHR, SHW, 
-	state, READ_DONE, clk, reset, send_abort, write_back_done, AllInvDone); 
-*/
-initial
-begin
-	$display("Example: maintaining cache coherence in 2-processor system");
-
-	file1 = $fopen("cache.list");
-	$fdisplay(file1, "Example: maintaining cache coherence in 2-processor system");
-
-	/* The states of sector in both caches are initialized to Invalid (0). */
-	SectorInCacheA = 0; SectorInCacheB = 0;
- 
-	/* Signals set/rest by cache controller */
-	// Write Hit
-	WH = 0;
-
-	// ReadMiss (Shared)
-	RMS = 0;
-
-	// WriteMiss
-	WM  = 0;
-
-	// Snoop hit on read operation
-	SHR = 0;
-
-	// Snoop hit on write operation
-	SHW = 0;
-
-	// This signal is set/reset,
-	// when a cache controller starts or finish reading a sector from memory
-	READ_DONE = 0;
-
-	// This signal is set when all other cache controllers 
-	// invalidate their copy.
-	AllInvDone = 0;
-
-	// This signal is set when cache controller finishes updating memory.
-	write_back_done = 0;
-
-	// This signal is set when snoopy cache controller sends 
-	// AdrRetry Signal to retry the operation. 
-	send_abort = 0;
-
-	// Present State of the Sector is INVALID in PA's local cache.
-	// So, it puts the address of this sector on the bus and starts
-	// reading this sector from memory.
-
-	state = SectorInCacheA ; PA = 1; PB = 0; RME = 1; 
-	reset = 1; #6 reset = 0;
-
-	// After 15 time units Processor B will declare  
-	// Snoop Hit on the Read operation done by Processor A.
-	#40 PA = 0; PB = 1; RME = 0; RMS = 1; state = SectorInCacheB; 
-	reset = 1;#10 reset = 0;
-
-	#50 PB = 0; PA = 1; SHR = 1; state = SectorInCacheA; 
-	reset = 1; #10 reset = 0;
-	
-	#20 SHR = 0; WH = 1; state = SectorInCacheA; 
-	reset = 1; #10 reset = 0;
-
-	#50 PA = 0; PB = 1; RMS = 1; WH = 0; state = SectorInCacheB; 
-	reset = 1; #10 reset = 0;
-
-	#30 SHR = 1; RMS = 0; PA = 1; PB = 0; state = SectorInCacheA; 
-	reset = 1; #10 reset = 0;
-	
-	#20 PB = 1; PA = 0; SHR = 0; state = SectorInCacheB; 
-	reset = 1; #10 reset = 0;
-
-	// PA states writing back.
-	#20 PB = 0; PA = 1; state = SectorInCacheA; 
-	reset = 1; #10 reset = 0;
-
-	// This signal is broadcast on the bus to tell every body that 
-	// Processor B has written back its Modified data back to the Memory 
-	// to make everything consistent. After 5 time units it is set back to 
-	// Zero. 
-
-	#30 write_back_done = 1;
-	#10 write_back_done = 0;
-
-	// PB retry.
-	#10 PA = 0; PB = 1; RMS = 1; state = SectorInCacheB; 
-	reset = 1; #10 reset = 0;
-
-//	#100 $stop;
-//	#100 $finish;
-end
-
-always @(new_state)
-begin
-	if (PA == 1) SectorInCacheA = new_state ;
-	else if (PB == 1) SectorInCacheB = new_state ;
-end
-
-always @(posedge clk)
-begin
-	if (Invalidate)
-	begin	
-		#10 SectorInCacheB = 0;
-		#10 AllInvDone = 1;
-		#15 AllInvDone = 0;
-	end
-	else if (Cache_Sector_Fill)
-	begin
-		count = 0;
-		countE = 1;
-
-		// Intialize the Read_Done variable to 0; it 
-		// it will be set to 1 by this test file after
-		// some delay.
-		READ_DONE = 0;
-	end
-	else if (AdrRetry)
-	begin
-		countE = 0;
-		send_abort = 1;
-		#40 send_abort = 0;
-	end
-end
-
-always @(posedge clk)
-begin
-	if (READ_DONE == 1) READ_DONE = 0;
-	if (countE == 1)
-	begin
-		if ( count == 2 )
-		begin
-			READ_DONE = 1;
-			countE = 0;
-		end
-		else count = count + 1;
-	end
-$display("SHit %b Abort %b RD_DONE %b WB_DONE %b Cache_Sector_Fill %b Inv %b AllInvDone %b stateA %b stateB %b", SHR, send_abort, READ_DONE, write_back_done, Cache_Sector_Fill, Invalidate, AllInvDone, SectorInCacheA, SectorInCacheB);
-
-// Added for v2v testing
-
-$fdisplay(file1, $time,,"SHit %b Abort %b RD_DONE %b WB_DONE %b Cache_Sector_Fill %b Inv %b AllInvDone %b stateA %b stateB %b", SHR, send_abort, READ_DONE, write_back_done, Cache_Sector_Fill, Invalidate, AllInvDone, SectorInCacheA, SectorInCacheB);
-
-end
-
-initial clk = 0;
-
-always #(CYCLE/2) clk = ~clk ;
-
-endmodule

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/testcase4.v Deleted

@@ -1,94 +0,0 @@
-`timescale 1 ns/100 ps
-// Behavioral description of FIFO with:
-// active high write enable
-// active high read  enable
-// active low asynchronous clear
-// rising edge clock
-// active high full  flag
-// active low  empty flag
-
-module reg_fifo (Data, Q, Aclr, Clock, WE, RE, FF, EF);
-
-parameter width = 8;
-parameter depth = 8;
-parameter addr  = 3;
-
-input Clock, WE, RE, Aclr;
-input width-1:0 Data;
-output FF, EF; //Full & Empty Flags
-output width-1:0 Q;
-reg    width-1:0 Q;
-reg    width-1:0 mem_data depth-1:0;
-reg    addr -1:0 WAddress, RAddress;
-reg    FF, EF;
-
-// Write functional section
-always @ (posedge Clock or negedge Aclr)
-begin
-  if(!Aclr)
-    WAddress = #2 0;
-  else if(WE)
-    WAddress = #2 WAddress + 1;
-end
-
-// Write reg
-always @ (posedge Clock)
-begin
-  if(WE)
-    mem_dataWAddress = Data;
-end
-
-// Read functional section
-always @ (posedge Clock or negedge Aclr)
-begin
-  if(!Aclr)
-    RAddress = #1 0;
-  else if (RE)
-    RAddress = #1 RAddress + 1;
-end
-
-// Read reg
-always @ (posedge Clock)
-begin
-  if(RE)
-    Q = mem_dataRAddress;
-end
-
-// Full Flag
-always @ (posedge Clock or negedge Aclr)
-begin
-  if(!Aclr)
-    FF = #1 1'b0;
-  else if
-  (
-    (WE & !RE) && //Write operation
-      ( //Next cycle is full 
-        (WAddress == RAddress-1) || 
-        ( (WAddress == depth-1) && (RAddress == 1'b0) )
-      )
-  )
-    FF = #1 1'b1;
-  else
-    FF = #1 1'b0;
-end
-
-// Empty Flag
-always @ (posedge Clock or negedge Aclr)
-begin
-  if(!Aclr)
-    EF = #1 1'b0;
-  else if
-  (
-    (!WE & RE) && //Read operation
-      ( //Next cycle is empty 
-        (WAddress == RAddress+1) || 
-        ( (RAddress == depth-1) && (WAddress == 1'b0) )
-      )
-  )
-    EF = #1 1'b0;
-  else
-    EF = #1 1'b1;
-end
-
-endmodule
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/testcase5.v Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/tff.v Deleted

@@ -1,73 +0,0 @@
-// Verilog HDL for "gates.lib", "tff" "_functional"
-// Module T flip-flop
-module tff (in, out, nout);
-
-input
-	in;
-
-output
-	out, nout;
-reg 
-	out, nout;
-
-parameter
-	t_separation = 10,
-	delay=15,
-
-	warning_file=3;  // multichannel description of a warning file
-
-reg
-	t_state,  // internal state of T flip-flop
-	sep_clr; // signal marking the end of the min separation zone
-		 //  for the last pulse
-
-integer
-	last_t_time,    // time when the last t pulse appeared
-	in_sep;	 // number of pulses within an interval t_sep before 
-		 //  the last data pulse;
-
-initial 
-	begin
-// clear internal registers and the output signal
-	  t_state = 0;
-	  in_sep = 0;
-	  sep_clr = 0;
-	  out = 0;
-	  nout = 0;
-	end
-
-
-always @(posedge in)
-	begin
-	  out <= #delay (in_sep > 0) ? 1'bx : t_state;
-	  out <= #(delay+2) 0;
-	  nout <= #delay (in_sep > 0) ? 1'bx : ~t_state;
-	  nout <= #(delay+2) 0;
-
-	  if (in_sep == 0)
-	    t_state <= t_state ^ in;
-	  else
-	    begin
-	      t_state = 1'bx;
-
-	    // generating a warning
-	      $fwrite(warning_file, 
-	       "Violation of separation time in module %m.\n");
-	      $fwrite(warning_file,
-	       "Input T pulses at %0d and at %0d.\n", last_t_time, 
-	       $stime);
-	    end
-	  last_t_time <= $stime;
-
-	  in_sep <= in_sep + 1;
-	  sep_clr <= #(t_separation-1) 1;
-	end
-
-always @(posedge sep_clr)
-	begin
-	  in_sep <= in_sep - 1;
-	  sep_clr <= 0;
-	end
-
-
-endmodule

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/timescale_info_test.v Deleted

@@ -1,44 +0,0 @@
-/**********************************************************************
- * $timescale_info example -- Verilog test bench source code
- *
- * Verilog test bench to test the $timescale_info PLI application.
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-  reg  a, b, ci, clk;
-  wire sum, co;
-
-  addbit i1 (a, b, ci, sum, co);
-
-  initial
-    begin
-      $timeformat(-6,1," ms",10);
-      #1 $timescale_info(i1);
-      #1 $finish;
-    end
-endmodule
-
-/*** A gate level 1 bit adder model ***/
-`timescale 1ns / 1ps
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci, sum, co,
-        n1, n2, n3;
-
-  xor    (n1, a, b);
-  xor #2 (sum, n1, ci);
-  and    (n2, a, b);
-  and    (n3, n1, ci);
-  or  #2 (co, n2, n3);
-
-endmodule
-/*********************************************************************/
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/usb.v Deleted

@@ -1,407 +0,0 @@
-// Generated by vstruct v2.2.1
-
-`include "usb_defines.v"
-
-module usb (
-    // WISHBONE Interface
-    clk_i,
-    addr_i,
-    data_i,
-    data_o,
-    ack_o,
-    we_i,
-    stb_i,
-    cyc_i,
-    inta_o,
-    intb_o,
-    dma_req,
-    dma_ack,
-    rst_i,
-    resume_req_i,
-
-    // UTMI Interface
-    phy_clk,
-    DataOut,
-    TxReady,
-    RxValid,
-    RxActive,
-    RxError,
-    DataIn,
-    XcvSelect,
-    TermSel,
-    SuspendM,
-    LineState,
-    OpMode,
-    usb_vbus,
-    VStatus,                           // UTMI Vendor C/S bus
-    VControl,
-    VControl_Load,
-    TxValid,
-    phy_rst
-    );
-
-    // WISHBONE Interface
-    input           clk_i;
-    input    17:0 addr_i;
-    input    31:0 data_i;
-    output   31:0 data_o;
-    output          ack_o;
-    input           we_i;
-    input           stb_i;
-    input           cyc_i;
-    output          inta_o;
-    output          intb_o;
-    output   14:0 dma_req;
-    input    14:0 dma_ack;
-    input           rst_i;
-    input           resume_req_i;
-
-    // UTMI Interface
-    input           phy_clk;
-    output   7:0  DataOut;
-    input           TxReady;
-    input           RxValid;
-    input           RxActive;
-    input           RxError;
-    input    7:0  DataIn;
-    output          XcvSelect;
-    output          TermSel;
-    output          SuspendM;
-    input    1:0  LineState;
-    output   1:0  OpMode;
-    input           usb_vbus;
-    input    7:0  VStatus;           // UTMI Vendor C/S bus
-    output   3:0  VControl;
-    output          VControl_Load;
-    output          TxValid;
-    output          phy_rst;
-
-    ////////////////////////////////////////////////////////////////////////////
-    // wishbone_if                                                            //
-    ////////////////////////////////////////////////////////////////////////////
-    wire     14:0 wadr;
-    wire     31:0 wb2ma_d;
-    wire            wwe;
-    wire            wreq;
-    wire            re;
-    wire            we;
-    wire     31:0 wb2rf_d;
-
-    ////////////////////////////////////////////////////////////////////////////
-    // usb_trans_mac_if                                                       //
-    ////////////////////////////////////////////////////////////////////////////
-    wire            rst;
-    wire            tx_valid_out;
-    wire     7:0  rx_data;
-    wire            rx_valid;
-    wire            rx_active;
-    wire            rx_err;
-    wire            tx_ready;
-    wire            mode_hs;           // High Speed Mode
-    wire            usb_reset;         // USB Reset
-    wire            usb_suspend;       // USB Suspend
-    wire            usb_attached;      // Attached to USB
-    wire            resume_req;
-
-    ////////////////////////////////////////////////////////////////////////////
-    // protocol_layer                                                         //
-    ////////////////////////////////////////////////////////////////////////////
-    wire     7:0  tx_data;
-    wire            tx_valid;
-    wire            tx_valid_last;
-    wire            tx_first;
-    wire     14:0 madr;              // word address
-    wire     31:0 mdout;
-    wire            mwe;
-    wire            mreq;
-    wire     31:0 idin;              // Data Input
-    wire     3:0  ep_sel;            // Endpoint Number Input
-    wire            buf0_rl;           // Reload Buf 0 with original values
-    wire            buf0_set;          // Write to buf 0
-    wire            buf1_set;          // Write to buf 1
-    wire            uc_bsel_set;       // Write to the uc_bsel field
-    wire            uc_dpd_set;        // Write to the uc_dpd field
-    wire            int_buf1_set;      // Set buf1 full/empty interrupt
-    wire            int_buf0_set;      // Set buf0 full/empty interrupt
-    wire            int_upid_set;      // Set unsupported PID interrupt
-    wire            int_crc16_set;     // Set CRC16 error interrupt
-    wire            int_to_set;        // Set time out interrupt
-    wire            int_seqerr_set;    // Set PID sequence error interrupt
-    wire     31:0 frm_nat;
-    wire            pid_cs_err;        // pid checksum error
-    wire            nse_err;           // no such endpoint error
-    wire            crc5_err;          // crc5 error
-
-    ////////////////////////////////////////////////////////////////////////////
-    // memory_arbiter                                                         //
-    ////////////////////////////////////////////////////////////////////////////
-    wire     14:0 radr;
-    wire     31:0 arb2mem;
-    wire            rre;
-    wire            rwe;
-    wire     31:0 mdin;
-    wire            mack;
-    wire     31:0 ma2wb_d;
-    wire            wack;
-
-    ////////////////////////////////////////////////////////////////////////////
-    // buff_mem                                                               //
-    ////////////////////////////////////////////////////////////////////////////
-    wire     31:0 mem2arb;
-
-    ////////////////////////////////////////////////////////////////////////////
-    // reg_file                                                               //
-    ////////////////////////////////////////////////////////////////////////////
-    wire     31:0 rf2wb_d;
-    wire            match;             // Endpoint Matched
-    wire     31:0 csr;               // Internal CSR Output
-    wire     31:0 buf0;              // Internal Buf 0 Output
-    wire     31:0 buf1;              // Internal Buf 1 Output
-    wire     6:0  funct_adr;         // Function Address
-    wire            dma_in_buf_sz1;
-    wire            dma_out_buf_avail;
-    wire            rf_resume_req;
-
-    ///////////////////////////////////////////////////////////////////
-    //
-    // Misc Logic
-    //
-    assign TxValid = tx_valid_out;
-    assign rst = rst_i;
-    assign phy_rst = ~rst;
-    assign resume_req = resume_req_i | rf_resume_req;
-
-    wb wishbone_if (
-            // WISHBONE Interface
-            .clk               (clk_i),
-            .rst               (rst),
-            .addr_i            (addr_i),
-            .data_i            (data_i),
-            .data_o            (data_o),
-            .ack_o             (ack_o),
-            .we_i              (we_i),
-            .stb_i             (stb_i),
-            .cyc_i             (cyc_i),
-
-            // UTMI Interface
-            .phy_clk           (phy_clk),
-
-            // Memory Arbiter Interface
-            .wadr              (wadr),
-            .wdout             (wb2ma_d),
-            .wdin              (ma2wb_d),
-            .wwe               (wwe),
-            .wreq              (wreq),
-            .wack              (wack),
-
-            // Register File interface
-            .re                (re),
-            .we                (we),
-            .din               (rf2wb_d),
-            .dout              (wb2rf_d)
-        ); // wishbone_if
-
-    utmi_if usb_trans_mac_if (
-            // UTMI Interface (EXTERNAL)
-            .phy_clk           (phy_clk),
-            .rst               (rst),
-            .DataOut           (DataOut),
-            .TxValid           (tx_valid_out),
-            .TxReady           (TxReady),
-            .RxValid           (RxValid),
-            .RxActive          (RxActive),
-            .RxError           (RxError),
-            .DataIn            (DataIn),
-            .XcvSelect         (XcvSelect),
-            .TermSel           (TermSel),
-            .SuspendM          (SuspendM),
-            .LineState         (LineState),
-            .OpMode            (OpMode),
-            .usb_vbus          (usb_vbus),
-
-            // Internal Interface
-            .rx_data           (rx_data),
-            .rx_valid          (rx_valid),
-            .rx_active         (rx_active),
-            .rx_err            (rx_err),
-            .tx_data           (tx_data),
-            .tx_valid          (tx_valid),
-            .tx_valid_last     (tx_valid_last),
-            .tx_ready          (tx_ready),
-            .tx_first          (tx_first),
-
-            // Misc Interfaces
-            .mode_hs           (mode_hs),           // High Speed Mode
-            .usb_reset         (usb_reset),         // USB Reset
-            .usb_suspend       (usb_suspend),       // USB Suspend
-            .usb_attached      (usb_attached),      // Attached to USB
-            .resume_req        (resume_req)
-        ); // usb_trans_mac_if
-
-    pl protocol_layer (
-            // UTMI Interface
-            .clk               (phy_clk),
-            .rst               (rst),
-
-            // UTMI Interface
-            .rx_data           (rx_data),
-            .rx_valid          (rx_valid),
-            .rx_active         (rx_active),
-            .rx_err            (rx_err),
-            .tx_data           (tx_data),
-            .tx_valid          (tx_valid),
-            .tx_valid_last     (tx_valid_last),
-            .tx_ready          (tx_ready),
-            .tx_first          (tx_first),
-            .tx_valid_out      (tx_valid_out),
-            .mode_hs           (mode_hs),           // High Speed Mode
-            .usb_reset         (usb_reset),         // USB Reset
-            .usb_suspend       (usb_suspend),       // USB Suspend
-            .usb_attached      (usb_attached),      // Attached to USB
-
-            // memory interface
-            .madr              (madr),              // word address
-            .mdout             (mdout),
-            .mdin              (mdin),
-            .mwe               (mwe),
-            .mreq              (mreq),
-            .mack              (mack),
-
-            // Register File Interface
-            .fa                (funct_adr),         // Function Address (as set by the controller)
-            .idin              (idin),              // Data Input
-            .ep_sel            (ep_sel),            // Endpoint Number Input
-            .match             (match),             // Endpoint Matched
-            .dma_in_buf_sz1    (dma_in_buf_sz1),
-            .dma_out_buf_avail (dma_out_buf_avail),
-
-            .buf0_rl           (buf0_rl),           // Reload Buf 0 with original values
-            .buf0_set          (buf0_set),          // Write to buf 0
-            .buf1_set          (buf1_set),          // Write to buf 1
-            .uc_bsel_set       (uc_bsel_set),       // Write to the uc_bsel field
-            .uc_dpd_set        (uc_dpd_set),        // Write to the uc_dpd field
-
-            .int_buf1_set      (int_buf1_set),      // Set buf1 full/empty interrupt
-            .int_buf0_set      (int_buf0_set),      // Set buf0 full/empty interrupt
-            .int_upid_set      (int_upid_set),      // Set unsupported PID interrupt
-            .int_crc16_set     (int_crc16_set),     // Set CRC16 error interrupt
-            .int_to_set        (int_to_set),        // Set time out interrupt
-            .int_seqerr_set    (int_seqerr_set),    // Set PID sequence error interrupt
-
-            .csr               (csr),               // Internal CSR Output
-            .buf0              (buf0),              // Internal Buf 0 Output
-            .buf1              (buf1),              // Internal Buf 1 Output
-
-            // Misc
-            .frm_nat           (frm_nat),
-
-            // Misc
-            .pid_cs_err        (pid_cs_err),        // pid checksum error
-            .nse_err           (nse_err),           // no such endpoint error
-            .crc5_err          (crc5_err)           // crc5 error
-
-        ); // protocol_layer
-
-    mem_arb memory_arbiter (
-            .phy_clk           (phy_clk),
-            .wclk              (clk_i),
-            .rst               (rst),
-
-            // SSRAM Interface
-            .radr              (radr),
-            .rdin              (mem2arb),
-            .rdout             (arb2mem),
-            .rre               (rre),
-            .rwe               (rwe),
-
-            // IDMA Memory Interface
-            .madr              (madr),
-            .mdout             (mdin),
-            .mdin              (mdout),
-            .mwe               (mwe),
-            .mreq              (mreq),
-            .mack              (mack),
-
-            // WISHBONE Memory Interface
-            .wadr              (wadr),
-            .wdout             (ma2wb_d),
-            .wdin              (wb2ma_d),
-            .wwe               (wwe),
-            .wreq              (wreq),
-            .wack              (wack)
-
-        ); // memory_arbiter
-
-    ssram buff_mem (
-            .clk               (phy_clk),
-            .rst               (rst),
-            .radr              (radr),
-            .rdin              (arb2mem),
-            .rdout             (mem2arb),
-            .rre               (rre),
-            .rwe               (rwe)
-        ); // buff_mem
-
-    rf reg_file (
-            .clk               (phy_clk),
-            .wclk              (clk_i),
-            .rst               (rst),
-
-            // Wishbone Interface
-            .adr               (wadr6:0),
-            .re                (re),
-            .we                (we),
-            .din               (wb2rf_d),
-            .dout              (rf2wb_d),
-            .inta              (inta_o),
-            .intb              (intb_o),
-            .dma_req           (dma_req),
-            .dma_ack           (dma_ack),
-
-            // Internal Interface
-            .idin              (idin),              // Data Input
-            .ep_sel            (ep_sel),            // Endpoint Number Input
-            .match             (match),             // Endpoint Matched
-            .buf0_rl           (buf0_rl),           // Reload Buf 0 with original values
-
-            .buf0_set          (buf0_set),          // Write to buf 0
-            .buf1_set          (buf1_set),          // Write to buf 1
-            .uc_bsel_set       (uc_bsel_set),       // Write to the uc_bsel field
-            .uc_dpd_set        (uc_dpd_set),        // Write to the uc_dpd field
-
-            .int_buf1_set      (int_buf1_set),      // Set buf1 full/empty interrupt
-            .int_buf0_set      (int_buf0_set),      // Set buf0 full/empty interrupt
-            .int_upid_set      (int_upid_set),      // Set unsupported PID interrupt
-            .int_crc16_set     (int_crc16_set),     // Set CRC16 error interrupt
-            .int_to_set        (int_to_set),        // Set time out interrupt
-            .int_seqerr_set    (int_seqerr_set),    // Set PID Sequence Error Interrupt
-
-            .csr               (csr),               // Internal CSR Output
-            .buf0              (buf0),              // Internal Buf 0 Output
-            .buf1              (buf1),              // Internal Buf 1 Output
-            .funct_adr         (funct_adr),         // Function Address
-            .dma_in_buf_sz1    (dma_in_buf_sz1),
-            .dma_out_buf_avail (dma_out_buf_avail),
-
-            // Misc
-            .frm_nat           (frm_nat),
-
-            // UTMI Interface
-            .utmi_vend_stat    (VStatus),           // UTMI Vendor C/S bus
-            .utmi_vend_ctrl    (VControl),
-            .utmi_vend_wr      (VControl_Load),
-
-            .line_stat         (LineState),         // Below are signals for interrupt generation
-            .usb_attached      (usb_attached),
-            .mode_hs           (mode_hs),
-            .suspend           (usb_suspend),
-            .attached          (usb_attached),
-            .usb_reset         (usb_reset),
-            .pid_cs_err        (pid_cs_err),
-            .nse_err           (nse_err),
-            .crc5_err          (crc5_err),
-            .rx_err            (rx_err),
-            .rf_resume_req     (rf_resume_req)
-        ); // reg_file
-endmodule
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/use_workarea_test.v Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/utmi_if.v Deleted

@@ -1,196 +0,0 @@
-/////////////////////////////////////////////////////////////////////
-////                                                             ////
-////  UTMI Interface                                             ////
-////                                                             ////
-////                                                             ////
-////  Author: Rudolf Usselmann                                   ////
-////          rudi@asics.ws                                      ////
-////                                                             ////
-////                                                             ////
-////  Downloaded from: http://www.opencores.org/cores/usb/       ////
-////                                                             ////
-/////////////////////////////////////////////////////////////////////
-////                                                             ////
-//// Copyright (C) 2000 Rudolf Usselmann                         ////
-////                    rudi@asics.ws                            ////
-////                                                             ////
-//// This source file may be used and distributed without        ////
-//// restriction provided that this copyright statement is not   ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer.////
-////                                                             ////
-////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
-//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
-//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
-//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
-//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
-//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
-//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
-//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
-//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
-//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
-//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
-//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
-//// POSSIBILITY OF SUCH DAMAGE.                                 ////
-////                                                             ////
-/////////////////////////////////////////////////////////////////////
-
-//  CVS Log
-//
-//  $Id: utmi_if.v,v 1.0 2001/03/07 09:17:12 rudi Exp $
-//
-//  $Date: 2001/03/07 09:17:12 $
-//  $Revision: 1.0 $
-//  $Author: rudi $
-//  $Locker:  $
-//  $State: Exp $
-//
-// Change History:
-//               $Log: utmi_if.v,v $
-//               Revision 1.0  2001/03/07 09:17:12  rudi
-//
-//
-//               Changed all revisions to revision 1.0. This is because OpenCores CVS
-//               interface could not handle the original '0.1' revision ....
-//
-//               Revision 0.2  2001/03/07 09:08:13  rudi
-//
-//               Added USB controll signaling (Line Status) block. Fixed some minor
-//               typos, added resume bit and signal.
-//
-//               Revision 0.1.0.1  2001/02/28 08:11:45  rudi
-//               Initial Release
-//
-//
-
-`include "usb_defines.v"
-
-module utmi_if( // UTMI Interface (EXTERNAL)
-        phy_clk, rst,
-        DataOut, TxValid, TxReady,
-        RxValid, RxActive, RxError, DataIn,
-        XcvSelect, TermSel, SuspendM, LineState,
-        OpMode, usb_vbus,
-
-        // Internal Interface
-        rx_data, rx_valid, rx_active, rx_err,
-        tx_data, tx_valid, tx_valid_last, tx_ready,
-        tx_first,
-
-        // Misc Interfaces
-        mode_hs, usb_reset, usb_suspend, usb_attached,
-        resume_req
-        );
-
-input       phy_clk;
-output      rst;
-output  7:0   DataOut;
-output      TxValid;
-input       TxReady;
-input   7:0   DataIn;
-input       RxValid;
-input       RxActive;
-input       RxError;
-output      XcvSelect;
-output      TermSel;
-output      SuspendM;
-input   1:0   LineState;
-output  1:0   OpMode;
-input       usb_vbus;
-
-output  7:0   rx_data;
-output      rx_valid, rx_active, rx_err;
-input   7:0   tx_data;
-input       tx_valid;
-input       tx_valid_last;
-output      tx_ready;
-input       tx_first;
-
-output      mode_hs;    // High Speed Mode
-output      usb_reset;  // USB Reset
-output      usb_suspend;    // USB Suspend
-output      usb_attached;   // Attached to USB
-input       resume_req;
-
-///////////////////////////////////////////////////////////////////
-//
-// Local Wires and Registers
-//
-reg 7:0   rx_data;
-reg     rx_valid, rx_active, rx_err;
-reg 7:0   DataOut;
-reg     tx_ready;
-reg     TxValid;
-wire        drive_k;
-
-///////////////////////////////////////////////////////////////////
-//
-// Misc Logic
-//
-
-
-///////////////////////////////////////////////////////////////////
-//
-// RX Interface Input registers
-//
-
-always @(posedge phy_clk)
-    if(!rst)    rx_valid <= #1 0;
-    else        rx_valid <= #1 RxValid;
-
-always @(posedge phy_clk)
-    if(!rst)    rx_active <= #1 0;
-    else        rx_active <= #1 RxActive;
-
-always @(posedge phy_clk)
-    if(!rst)    rx_err <= #1 0;
-    else        rx_err <= #1 RxError;
-
-always @(posedge phy_clk)
-        rx_data <= #1 DataIn;
-
-///////////////////////////////////////////////////////////////////
-//
-// TX Interface Output/Input registers
-//
-wire    tx_valid_sr;
-
-assign  tx_valid_sr = (!rst) ? 0 : tx_valid_last ? 1 : TxReady ? 0 : tx_valid_sr;
-
-always @(posedge phy_clk)
-    if(TxReady | tx_first)  DataOut <= #1 tx_data;
-    else
-    if(drive_k)     DataOut <= #1 8'hff;
-
-always @(posedge phy_clk)
-    tx_ready <= #1 TxReady;
-
-always @(posedge phy_clk)
-    TxValid <= #1 tx_valid | tx_valid_sr | drive_k;
-
-///////////////////////////////////////////////////////////////////
-//
-// Line Status Signaling & Speed Negotiation Block
-//
-
-utmi_ls u0(
-        .clk(       phy_clk     ),
-        .rst(       rst     ),
-        .resume_req(    resume_req  ),
-        .rx_active( rx_active   ),
-        .tx_ready(  tx_ready    ),
-        .drive_k(   drive_k     ),
-        .XcvSelect( XcvSelect   ),
-        .TermSel(   TermSel     ),
-        .SuspendM(  SuspendM    ),
-        .LineState( LineState   ),
-        .OpMode(    OpMode      ),
-        .usb_vbus(  usb_vbus    ),
-        .mode_hs(   mode_hs     ),
-        .usb_reset( usb_reset   ),
-        .usb_suspend(   usb_suspend ),
-        .usb_attached(  usb_attached    )
-        );
-
-endmodule
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/vpi_utilities_test.v Deleted

@@ -1,46 +0,0 @@
-/**********************************************************************
- * $vpi_util_test example -- Verilog HDL test bench.
- *
- * Verilog test bench to test the VPI utility applications. 
- *
- * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
- *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
- *   Contact: www.wkap.il
- *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
- *   Contact: www.sutherland.com or (503) 692-0898
- *********************************************************************/
-`timescale 1ns / 1ns
-module test;
-  reg  a, b, ci;
-  wire sum, co;
-  real r1;
-
-  addbit i1 (a, b, ci, sum, co);
-
-  initial
-    begin
-      a = 0; b = 1; ci = 1;
-      r1 = 0.5;
-      $vpi_util_test(i1, r1, ci, "Hello world", /*null arg*/ );
-      #1 $finish;
-    end
- 
- endmodule
-
-/*** A gate level 1 bit adder model ***/
-`timescale 1ns / 1ns
-module addbit (a, b, ci, sum, co);
-  input  a, b, ci;
-  output sum, co;
-
-  wire  a, b, ci, sum, co,
-        n1, n2, n3;
-
-  xor    (n1, a, b);
-  xor #2 (sum, n1, ci);
-  and    (n2, a, b);
-  and    (n3, n1, ci);
-  or  #2 (co, n2, n3);
-
-endmodule
-/**********************************************************************/

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/wb.v Deleted

@@ -1,160 +0,0 @@
-/////////////////////////////////////////////////////////////////////
-////                                                             ////
-////  WISHBONE Interface                                         ////
-////  This is the external bus interface, that is WISHBONE       ////
-////  SoC compliant.                                             ////
-////                                                             ////
-////                                                             ////
-////  Author: Rudolf Usselmann                                   ////
-////          rudi@asics.ws                                      ////
-////                                                             ////
-////                                                             ////
-////  Downloaded from: http://www.opencores.org/cores/usb/       ////
-////                                                             ////
-/////////////////////////////////////////////////////////////////////
-////                                                             ////
-//// Copyright (C) 2000 Rudolf Usselmann                         ////
-////                    rudi@asics.ws                            ////
-////                                                             ////
-//// This source file may be used and distributed without        ////
-//// restriction provided that this copyright statement is not   ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer.////
-////                                                             ////
-////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
-//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
-//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
-//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
-//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
-//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
-//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
-//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
-//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
-//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
-//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
-//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
-//// POSSIBILITY OF SUCH DAMAGE.                                 ////
-////                                                             ////
-/////////////////////////////////////////////////////////////////////
-
-//  CVS Log
-//
-//  $Id: wb.v,v 1.0 2001/03/07 09:17:12 rudi Exp $
-//
-//  $Date: 2001/03/07 09:17:12 $
-//  $Revision: 1.0 $
-//  $Author: rudi $
-//  $Locker:  $
-//  $State: Exp $
-//
-// Change History:
-//               $Log: wb.v,v $
-//               Revision 1.0  2001/03/07 09:17:12  rudi
-//
-//
-//               Changed all revisions to revision 1.0. This is because OpenCores CVS
-//               interface could not handle the original '0.1' revision ....
-//
-//               Revision 0.1.0.1  2001/02/28 08:11:47  rudi
-//               Initial Release
-//
-//
-
-`include "usb_defines.v"
-
-module wb(  // WISHBONE Interface
-        clk, rst, addr_i, data_i, data_o, 
-        ack_o, we_i, stb_i, cyc_i,
-
-        // UTMI Interface
-        phy_clk,
-
-        // Memory Arbiter Interface
-        wadr, wdout, wdin, wwe, wreq, wack,
-
-        // Register File interface
-        re, we, din, dout);
-
-input       clk;
-input       rst;
-input   17:0  addr_i;
-input   31:0  data_i;
-output  31:0  data_o;
-output      ack_o;
-input       we_i;
-input       stb_i;
-input       cyc_i;
-
-input       phy_clk;
-
-// Memory Arbiter Interface
-output  14:0  wadr;
-output  31:0  wdout;
-input   31:0  wdin;
-output      wwe;
-output      wreq;
-input       wack;
-
-// Register File interface
-output      re;
-output      we;
-input   31:0  din;
-output  31:0  dout;
-
-
-///////////////////////////////////////////////////////////////////
-//
-// Local Wires and Registers
-//
-
-reg     wack_r, wack_r2;
-wire        csm, csr;
-
-reg     ack_o;
-reg 31:0  data_o;
-wire        reg_ack_d;
-
-///////////////////////////////////////////////////////////////////
-//
-// Interface Logic
-//
-
-assign csm = stb_i & cyc_i &  addr_i17;   // Memory Chip Select
-assign csr = stb_i & cyc_i & !addr_i17;   // Register File Chip Select
-
-// Memory Buffer Interface
-assign wadr = addr_i16:2;
-assign wreq = csm;
-assign wwe  =  csm & we_i;
-assign wdout = data_i;
-
-assign  reg_ack_d = csr & !ack_o;
-
-always @(posedge phy_clk or posedge ack_o)
-    if(ack_o)   wack_r <= #1 0;
-    else        wack_r <= #1 wack | reg_ack_d;
-
-always @(posedge phy_clk or posedge ack_o)
-    if(ack_o)   wack_r2 <= #1 0;
-    else        wack_r2 <= #1 wack_r & (wack | reg_ack_d);
-
-// Register File Interface
-assign re = csr & !we_i;
-assign we = csr &  we_i;
-assign dout = data_i;
-
-// Shared Signals
-
-always @(posedge clk)
-    if(!rst | ack_o)                ack_o <= #1 0;
-    else
-    if(wack_r & wack_r2 & (wreq | reg_ack_d))   ack_o <= #1 1;
-
-always @(posedge clk)
-    if(!csm)                    data_o <= #1 din;
-    else
-    if(wack_r & wack_r2 & (reg_ack_d | wreq))   data_o <= #1 wdin;
-
-endmodule
-
-

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/wpulse.v Deleted

@@ -1,160 +0,0 @@
-//
-// 
-//  This circuit generates WE pulses.  For example, if you have a chip that
-//  needs to access an asynchronous SRAM in a single cycle and you wanted
-//  generate the WE pulse synchronous with your system clock.
-//
-//  Every clk cycle, generate an active
-//  low WE pulse.  The delay from the clk rising edge to the falling edge of
-//  we is based on abits setting, which affects delay taps, etc.  Likewise,
-//  bbits controls the following rising edge of we.  The module contains
-//  two flip flops that generate two opposite poraity toggling levels.
-//  A delay chain is attached to each of these outputs.  The abits and bbits
-//  get the desired tap, and the final two delayed signals are XORed together
-//  to get the final we.  None of this is very tuned, you would look at your
-//  cycle time and pick a delay chain that makes sense for that.  But, this
-//  shows the effect.
-//
-//  The we pulse always occurs.  You will probably want to combine this with
-//  you write_enable signal.  This sort of circuit is, of course, highly dependent
-//  on post-layout timing, etc.  but that's why its programable.  You probably
-//  want more taps, too..
-//
-//
-module wpulse (
-   reset,
-   clk,
-   abits,
-   bbits,
-   we
-);
-
-input		clk;
-input		reset;
-input 3:0	abits; // bits to select which delay tap to use for first edge
-input 3:0	bbits; // bits to select which delay tap to use for pulse width
-output		we;
-
-reg 		p1, p2;
-
-wire		adel1out;
-wire		adel2out;
-wire		adel3out;
-wire		adel4out;
-wire		bdel1out;
-wire		bdel2out;
-wire		bdel3out;
-wire		bdel4out;
-
-wire		adelout;
-wire		bdelout;
-
-// 2 flip-flops that are opposite polarity.  Each flop toggles
-// every cycles.
-//
-always @(posedge clk)
-   p1 <= (reset) | (~reset & ~p1); // reset to 1
-always @(posedge clk)
-   p2 <= (~reset & ~p2);  // reset to 0
-
-// Delay chain off of the p1 flop.   
-delay4 adel1 (.a(p1),		.z(adel1out));
-delay4 adel2 (.a(adel1out),	.z(adel2out));
-delay4 adel3 (.a(adel2out),	.z(adel3out));
-delay4 adel4 (.a(adel3out),	.z(adel4out));
-
-// Delay chain off of the p2 flop.
-delay4 bdel1 (.a(p2),		.z(bdel1out));
-delay4 bdel2 (.a(bdel1out),	.z(bdel2out));
-delay4 bdel3 (.a(bdel2out),	.z(bdel3out));
-delay4 bdel4 (.a(bdel3out),	.z(bdel4out));
-
-// Select the tap of the p1 and p2 delay chains we want based on abits
-assign adelout =	abits3 & adel1out | 
-			abits2 & adel2out | 
-			abits1 & adel3out |
-			abits0 & adel4out;
-assign bdelout =	bbits3 & bdel1out | 
-			bbits2 & bdel2out | 
-			bbits1 & bdel3out |
-			bbits0 & bdel4out;
-
-// Final we pulse is just the XOR of the two chains.  
-assign we = adelout ^ bdelout;
-
-endmodule
-
-// This is our delay cell.  Pick whatever cell makes sense from your library.
-module delay4 (a, z);
-input a;
-output z;
-reg	z;
-always @(a)
-  z = #4 a;
-endmodule
-
-// synopsys translate_off
-module testwpulse;
-reg		clk;
-reg		reset;
-reg 3:0	abits; // bits to select which delay tap to use for first edge
-reg 3:0	bbits; // bits to select which delay tap to use for pulse width
-wire		we;
-
-wpulse wpulse_inst (
-   .reset	(reset),
-   .clk		(clk),
-   .abits	(abits),
-   .bbits	(bbits),
-   .we		(we)
-);
-
-initial begin
-   abits = 4'b1000; // Shortest pulse, earliest in cycle.
-   bbits = 4'b0100;
-   #200;
-
-   abits = 4'b0010; // Shortest pulse, latest in the cycle.
-   bbits = 4'b0001;
-   #200;
-
-   abits = 4'b0100; // Shortest pulse, middle of the cycle.
-   bbits = 4'b0010;
-   #200;
-
-   abits = 4'b1000; // Longest cycle
-   bbits = 4'b0001;
-   #200;
-
-   abits = 4'b1000; // Early in cycle, but not quite the longest.
-   bbits = 4'b0010;
-   #200;
-
-   $finish;
-end
-
-// Reset
-initial begin
-   reset = 0;
-   #5 reset = 1;
-   #100 reset = 0;
-end
-   
-// Generate the 50MHz clock
-initial begin
-   clk = 0;
-   forever begin
-      #10 clk = 1;
-      #10 clk = 0;
-   end
-end
-
-`define WAVES
-`ifdef WAVES
-initial begin
-   $dumpfile ("wpulse.vcd");
-   $dumpvars (0,testwpulse);   
-end
-`endif
-endmodule
-// synopsys translate_on

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/xor.v Deleted

@@ -1,158 +0,0 @@
-// Verilog HDL for "gates.lib", "xor_gate" "_functional"
-// Module XOR gate
-module xor_gate (a, b, clk, out);
-
-input
-	a, b, clk;
-
-output
-	out;
-reg 
-	out;
-
-parameter
-	t_hold=5,
-	t_setup=10,
-	delay=15,
-
-	warning_file=3;  // multichannel description of a warning file
-
-reg
-	a_internal, b_internal, clk_internal,
-	a_state, b_state,          // internal state at inputs a and b
-	a_violation, b_violation,  // timing violation at inputs a and b
-	a_set, b_set;		   // signals determining the moment when
-				   // the state of the a,b inputs changes to "1"
-integer
-	data_delay, 	// delay between a (b) and a_internal (b_internal)
-	clk_delay, 	// delay between clk and clk_internal
-	out_delay, 	// delay between clk_internal and out
-	out_value,	// output value in a given clock cycle
-	last_clk_time;	// time when the last clock pulse appeared
-
-initial 
-	begin
-// define delays between inputs & outputs and the corresponding
-//  internal auxiliary registers
-	  	if(t_hold<0)
-		  begin
-	    		data_delay = -t_hold;
-	    	  	clk_delay = 0;
-		  	out_delay = delay;
-		  end
-	  	else
-		  begin
-	    	  	data_delay = 0;
-	    	  	clk_delay = t_hold;
-		  	out_delay=delay-t_hold;
-		  end
-
-// clear internal registers and the output signal
-		a_internal = 0;
-		b_internal = 0;
-		clk_internal = 0;
-		last_clk_time = 0;
-		a_state = 0;
-		b_state = 0;
-		a_violation = 0;
-		b_violation = 0;
-		a_set = 0;
-		b_set = 0;
-		out = 0;
-	end
-
-always @(posedge a) 	// Execute at positive edge of a
-	  a_internal <= #(data_delay) a;
-
-always @(posedge b) 	// Execute at positive edge of b
-	  b_internal <= #(data_delay) b;
-
-always @(posedge clk) 	// Execute at positive edge of clk
-	  clk_internal <= #(clk_delay) clk;
-
-always @(posedge a_internal)
-	begin
-// setting an internal state at the input a
-		a_violation = 1;
-		if (a_internal === 1)
-		  a_set <= #(t_hold+t_setup) 1;
-
-		a_internal <= 0;
-	end
-
-always @(posedge b_internal)
-	begin
-// setting an internal state at the input a
-		b_violation = 1;
-		if (b_internal === 1)
-		  b_set <= #(t_hold+t_setup) 1;
-
-		b_internal <= 0;
-	end
-
-always @(posedge a_set)
-	begin
-		if ($stime - last_clk_time >= t_hold+t_setup)
-			a_state = a_state^1;
-		else
-		  begin
-			a_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input A pulse at %0d,",
-			 $stime-data_delay-t_hold-t_setup);
-			$fwrite(warning_file,
-			"\tClock pulse at %0d.\n", last_clk_time-clk_delay);
-		  end
-
-		a_violation <= 0;
-		a_set <= 0;
-	end
-
-always @(posedge b_set)
-	begin
-		if ($stime - last_clk_time >= t_hold+t_setup)
-			b_state = b_state^1;
-		else
-		  begin
-			b_state = 1'bx;
-
-		  // generating a warning
-		  	$fwrite(warning_file, 
-			 "Violation of hold/setup time in module %m.\n");
-			$fwrite(warning_file,
-			"Input B pulse at %0d,",
-			 $stime-data_delay-t_hold-t_setup);
-			$fwrite(warning_file,
-			"\tClock pulse at %0d.\n", last_clk_time-clk_delay);
-		  end
-
-		b_violation <= 0;
-		b_set <= 0;
-	end
-
-
-always @(posedge clk_internal)	
-	begin
-// computing the output
-		if ((clk_internal === 1'bx) || (a_violation | b_violation))
-		  out_value = 1'bx;
-		else
-		  out_value = a_state ^ b_state;
-
-// transfering the result to the output
-		out <= #(out_delay) out_value;
-		out <= #(out_delay+2) 0;
-
-// clearing the internal state of A and B inputs
-		a_state  <= 0;
-		b_state  <= 0;
-
-		clk_internal <= 0;
-		last_clk_time = $stime;
-	end
-
-endmodule

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilog/zzzexample.v Deleted

@@ -1,130 +0,0 @@
-
-module test ( a,b,d);
-	input 4:0 a;
-	input 20:0 b;
-	output d;
-
-   always @(a or b)
-   begin
-      if (a == 5'b00000)
-      begin
-         d = b2:0 ; 
-      end
-      else if (a == 5'b00001)
-      begin
-         d = b5:3 ; 
-      end
-      else if (a == 5'b00010)
-      begin
-         d = b8:6 ; 
-      end
-      else if (a == 5'b00011)
-      begin
-         d = b11:9 ; 
-      end
-      else if (a == 5'b00100)
-      begin
-         d = b14:12 ; 
-      end
-      else if (a == 5'b00101)
-      begin
-         d = b17:15 ; 
-      end
-      else if (a == 5'b00110)
-      begin
-         d = b20:18 ; 
-      end
-      else if (a == 5'b00111)
-      begin
-         d = b2:0 ; 
-      end
-      else if (a == 5'b01000)
-      begin
-         d = b5:3 ; 
-      end
-      else if (a == 5'b01001)
-      begin
-         d = b8:6 ; 
-      end
-      else if (a == 5'b01010)
-      begin
-         d = b11:9 ; 
-      end
-      else if (a == 5'b01011)
-      begin
-         d = b14:12 ; 
-      end
-      else if (a == 5'b01100)
-      begin
-         d = b17:15 ; 
-      end
-      else if (a == 5'b01101)
-      begin
-         d = b20:18 ; 
-      end
-      else if (a == 5'b01110)
-      begin
-         d = b2:0 ; 
-      end
-      else if (a == 5'b01111)
-      begin
-         d = b5:3 ; 
-      end
-      else if (a == 5'b10000)
-      begin
-         d = b8:6 ; 
-      end
-      else if (a == 5'b10001)
-      begin
-         d = b11:9 ; 
-      end
-      else if (a == 5'b10010)
-      begin
-         d = b14:12 ; 
-      end
-      else if (a == 5'b10011)
-      begin
-         d = b17:15 ; 
-      end
-      else if (a == 5'b10100)
-      begin
-         d = b20:18 ; 
-      end
-      else if (a == 5'b10101)
-      begin
-         d = b2:0 ; 
-      end
-      else if (a == 5'b10110)
-      begin
-         d = b5:3 ; 
-      end
-      else if (a == 5'b10111)
-      begin
-         d = b8:6 ; 
-      end
-      else if (a == 5'b11000)
-      begin
-         d = b11:9 ; 
-      end
-      else if (a == 5'b11001)
-      begin
-         d = b14:12 ; 
-      end
-      else if (a == 5'b11010)
-      begin
-         d = b17:15 ; 
-      end
-      else if (a == 5'b11011)
-      begin
-         d = b20:18 ; 
-      end
-      else if (a == 5'b11111)
-      begin
-         d = 3'b0; 
-      end
-      else
-      begin
-         d = {3{1'b0}} ; 
-      end 
-   end 
-endmodule

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/verilogParse.py Deleted

@@ -1,973 +0,0 @@
-#
-# verilogParse.py
-#
-# an example of using the pyparsing module to be able to process Verilog files
-# uses BNF defined at http://www.verilog.com/VerilogBNF.html
-#
-#    Copyright (c) 2004-2011 Paul T. McGuire.  All rights reserved.
-#
-# Permission is hereby granted, free of charge, to any person obtaining
-# a copy of this software and associated documentation files (the
-# "Software"), to deal in the Software without restriction, including
-# without limitation the rights to use, copy, modify, merge, publish,
-# distribute, sublicense, and/or sell copies of the Software, and to
-# permit persons to whom the Software is furnished to do so, subject to
-# the following conditions:
-#
-# The above copyright notice and this permission notice shall be
-# included in all copies or substantial portions of the Software.
-#
-# If you find this software to be useful, please make a donation to one
-# of the following charities:
-# - the Red Cross (https://www.redcross.org/)
-# - Hospice Austin (https://www.hospiceaustin.org/)
-#
-#    DISCLAIMER:
-#    THIS SOFTWARE IS PROVIDED BY PAUL T. McGUIRE ``AS IS'' AND ANY EXPRESS OR
-#    IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-#    MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO
-#    EVENT SHALL PAUL T. McGUIRE OR CO-CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-#    INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-#    BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OFUSE,
-#    DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
-#    OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-#    NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-#    EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-#    For questions or inquiries regarding this license, or commercial use of
-#    this software, contact the author via e-mail: ptmcg@users.sourceforge.net
-#
-# Todo:
-#  - add pre-process pass to implement compilerDirectives (ifdef, include, etc.)
-#
-# Revision History:
-#
-#   1.0   - Initial release
-#   1.0.1 - Fixed grammar errors:
-#           . real declaration was incorrect
-#           . tolerant of '=>' for '*>' operator
-#           . tolerant of '?' as hex character
-#           . proper handling of mintypmax_expr within path delays
-#   1.0.2 - Performance tuning (requires pyparsing 1.3)
-#   1.0.3 - Performance updates, using Regex (requires pyparsing 1.4)
-#   1.0.4 - Performance updates, enable packrat parsing (requires pyparsing 1.4.2)
-#   1.0.5 - Converted keyword Literals to Keywords, added more use of Group to
-#           group parsed results tokens
-#   1.0.6 - Added support for module header with no ports list (thanks, Thomas Dejanovic!)
-#   1.0.7 - Fixed erroneous '<<' Forward definition in timCheckCond, omitting ()'s
-#   1.0.8 - Re-released under MIT license
-#   1.0.9 - Enhanced udpInstance to handle identifiers with leading '\' and subscripting
-#   1.0.10 - Fixed change added in 1.0.9 to work for all identifiers, not just those used
-#           for udpInstance.
-#   1.0.11 - Fixed bug in inst_args, content alternatives were reversed
-#
-import time
-import pprint
-import sys
-
-__version__ = "1.0.11"
-
-from pyparsing import (
-    Literal,
-    Keyword,
-    Word,
-    OneOrMore,
-    ZeroOrMore,
-    Forward,
-    delimitedList,
-    Group,
-    Optional,
-    Combine,
-    alphas,
-    nums,
-    restOfLine,
-    alphanums,
-    dblQuotedString,
-    empty,
-    ParseException,
-    oneOf,
-    StringEnd,
-    FollowedBy,
-    ParserElement,
-    Regex,
-    cppStyleComment,
-)
-import pyparsing
-
-usePackrat = False
-
-packratOn = False
-
-if usePackrat:
-    try:
-        ParserElement.enablePackrat()
-    except Exception:
-        pass
-    else:
-        packratOn = True
-
-
-def dumpTokens(s, l, t):
-    import pprint
-
-    pprint.pprint(t.asList())
-
-
-verilogbnf = None
-
-
-def Verilog_BNF():
-    global verilogbnf
-
-    if verilogbnf is None:
-
-        # compiler directives
-        compilerDirective = Combine(
-            "`"
-            + oneOf(
-                "define undef ifdef else endif default_nettype "
-                "include resetall timescale unconnected_drive "
-                "nounconnected_drive celldefine endcelldefine"
-            )
-            + restOfLine
-        ).setName("compilerDirective")
-
-        # primitives
-        SEMI, COLON, LPAR, RPAR, LBRACE, RBRACE, LBRACK, RBRACK, DOT, COMMA, EQ = map(
-            Literal, ";:(){}.,="
-        )
-
-        identLead = alphas + "$_"
-        identBody = alphanums + "$_"
-        identifier1 = Regex(
-            r"\.?"
-            + identLead
-            + ""
-            + identBody
-            + r"*(\."
-            + identLead
-            + ""
-            + identBody
-            + "*)*"
-        ).setName("baseIdent")
-        identifier2 = (
-            Regex(r"\\\S+").setParseAction(lambda t: t01:).setName("escapedIdent")
-        )  # .setDebug()
-        identifier = identifier1 | identifier2
-        assert identifier2 == r"\abc"
-
-        hexnums = nums + "abcdefABCDEF" + "_?"
-        base = Regex("'bBoOdDhH").setName("base")
-        basedNumber = Combine(
-            Optional(Word(nums + "_")) + base + Word(hexnums + "xXzZ"),
-            joinString=" ",
-            adjacent=False,
-        ).setName("basedNumber")
-        # ~ number = ( basedNumber | Combine( Word( "+-"+spacedNums, spacedNums ) +
-        # ~ Optional( DOT + Optional( Word( spacedNums ) ) ) +
-        # ~ Optional( e + Word( "+-"+spacedNums, spacedNums ) ) ).setName("numeric") )
-        number = (
-            basedNumber | Regex(r"+-?0-9_+(\.0-9_*)?(Ee+-?0-9_+)?")
-        ).setName("numeric")
-        # ~ decnums = nums + "_"
-        # ~ octnums = "01234567" + "_"
-        expr = Forward().setName("expr")
-        concat = Group(LBRACE + delimitedList(expr) + RBRACE)
-        multiConcat = Group("{" + expr + concat + "}").setName("multiConcat")
-        funcCall = Group(
-            identifier + LPAR + Optional(delimitedList(expr)) + RPAR
-        ).setName("funcCall")
-
-        subscrRef = Group(LBRACK + delimitedList(expr, COLON) + RBRACK)
-        subscrIdentifier = Group(identifier + Optional(subscrRef))
-        # ~ scalarConst = "0" | (( FollowedBy('1') + oneOf("1'b0 1'b1 1'bx 1'bX 1'B0 1'B1 1'Bx 1'BX 1") ))
-        scalarConst = Regex("0|1('Bb01xX)?")
-        mintypmaxExpr = Group(expr + COLON + expr + COLON + expr).setName("mintypmax")
-        primary = (
-            number
-            | (LPAR + mintypmaxExpr + RPAR)
-            | (LPAR + Group(expr) + RPAR).setName("nestedExpr")
-            | multiConcat
-            | concat
-            | dblQuotedString
-            | funcCall
-            | subscrIdentifier
-        )
-
-        unop = oneOf("+  -  !  ~  &  ~&  |  ^|  ^  ~^").setName("unop")
-        binop = oneOf(
-            "+  -  *  /  %  ==  !=  ===  !==  &&  "
-            "||  <  <=  >  >=  &  |  ^  ^~  >>  << ** <<< >>>"
-        ).setName("binop")
-
-        expr << (
-            (unop + expr)
-            | (primary + "?" + expr + COLON + expr)  # must be first!
-            | (primary + Optional(binop + expr))
-        )
-
-        lvalue = subscrIdentifier | concat
-
-        # keywords
-        if_ = Keyword("if")
-        else_ = Keyword("else")
-        edge = Keyword("edge")
-        posedge = Keyword("posedge")
-        negedge = Keyword("negedge")
-        specify = Keyword("specify")
-        endspecify = Keyword("endspecify")
-        fork = Keyword("fork")
-        join = Keyword("join")
-        begin = Keyword("begin")
-        end = Keyword("end")
-        default = Keyword("default")
-        forever = Keyword("forever")
-        repeat = Keyword("repeat")
-        while_ = Keyword("while")
-        for_ = Keyword("for")
-        case = oneOf("case casez casex")
-        endcase = Keyword("endcase")
-        wait = Keyword("wait")
-        disable = Keyword("disable")
-        deassign = Keyword("deassign")
-        force = Keyword("force")
-        release = Keyword("release")
-        assign = Keyword("assign")
-
-        eventExpr = Forward()
-        eventTerm = (
-            (posedge + expr) | (negedge + expr) | expr | (LPAR + eventExpr + RPAR)
-        )
-        eventExpr << (Group(delimitedList(eventTerm, Keyword("or"))))
-        eventControl = Group(
-            "@" + ((LPAR + eventExpr + RPAR) | identifier | "*")
-        ).setName("eventCtrl")
-
-        delayArg = (
-            number
-            | Word(alphanums + "$_")
-            | (LPAR + Group(delimitedList(mintypmaxExpr | expr)) + RPAR)  # identifier |
-        ).setName(
-            "delayArg"
-        )  # .setDebug()
-        delay = Group("#" + delayArg).setName("delay")  # .setDebug()
-        delayOrEventControl = delay | eventControl
-
-        assgnmt = Group(lvalue + EQ + Optional(delayOrEventControl) + expr).setName(
-            "assgnmt"
-        )
-        nbAssgnmt = Group(
-            (lvalue + "<=" + Optional(delay) + expr)
-            | (lvalue + "<=" + Optional(eventControl) + expr)
-        ).setName("nbassgnmt")
-
-        range = LBRACK + expr + COLON + expr + RBRACK
-
-        paramAssgnmt = Group(identifier + EQ + expr).setName("paramAssgnmt")
-        parameterDecl = Group(
-            "parameter" + Optional(range) + delimitedList(paramAssgnmt) + SEMI
-        ).setName("paramDecl")
-
-        inputDecl = Group("input" + Optional(range) + delimitedList(identifier) + SEMI)
-        outputDecl = Group(
-            "output" + Optional(range) + delimitedList(identifier) + SEMI
-        )
-        inoutDecl = Group("inout" + Optional(range) + delimitedList(identifier) + SEMI)
-
-        regIdentifier = Group(
-            identifier + Optional(LBRACK + expr + COLON + expr + RBRACK)
-        )
-        regDecl = Group(
-            "reg"
-            + Optional("signed")
-            + Optional(range)
-            + delimitedList(regIdentifier)
-            + SEMI
-        ).setName("regDecl")
-        timeDecl = Group("time" + delimitedList(regIdentifier) + SEMI)
-        integerDecl = Group("integer" + delimitedList(regIdentifier) + SEMI)
-
-        strength0 = oneOf("supply0  strong0  pull0  weak0  highz0")
-        strength1 = oneOf("supply1  strong1  pull1  weak1  highz1")
-        driveStrength = Group(
-            LPAR
-            + ((strength0 + COMMA + strength1) | (strength1 + COMMA + strength0))
-            + RPAR
-        ).setName("driveStrength")
-        nettype = oneOf(
-            "wire  tri  tri1  supply0  wand  triand  tri0  supply1  wor  trior  trireg"
-        )
-        expandRange = Optional(oneOf("scalared vectored")) + range
-        realDecl = Group("real" + delimitedList(identifier) + SEMI)
-
-        eventDecl = Group("event" + delimitedList(identifier) + SEMI)
-
-        blockDecl = (
-            parameterDecl | regDecl | integerDecl | realDecl | timeDecl | eventDecl
-        )
-
-        stmt = Forward().setName("stmt")  # .setDebug()
-        stmtOrNull = stmt | SEMI
-        caseItem = (delimitedList(expr) + COLON + stmtOrNull) | (
-            default + Optional(":") + stmtOrNull
-        )
-        stmt << Group(
-            (begin + Group(ZeroOrMore(stmt)) + end).setName("begin-end")
-            | (
-                if_
-                + Group(LPAR + expr + RPAR)
-                + stmtOrNull
-                + Optional(else_ + stmtOrNull)
-            ).setName("if")
-            | (delayOrEventControl + stmtOrNull)
-            | (case + LPAR + expr + RPAR + OneOrMore(caseItem) + endcase)
-            | (forever + stmt)
-            | (repeat + LPAR + expr + RPAR + stmt)
-            | (while_ + LPAR + expr + RPAR + stmt)
-            | (
-                for_
-                + LPAR
-                + assgnmt
-                + SEMI
-                + Group(expr)
-                + SEMI
-                + assgnmt
-                + RPAR
-                + stmt
-            )
-            | (fork + ZeroOrMore(stmt) + join)
-            | (
-                fork
-                + COLON
-                + identifier
-                + ZeroOrMore(blockDecl)
-                + ZeroOrMore(stmt)
-                + end
-            )
-            | (wait + LPAR + expr + RPAR + stmtOrNull)
-            | ("->" + identifier + SEMI)
-            | (disable + identifier + SEMI)
-            | (assign + assgnmt + SEMI)
-            | (deassign + lvalue + SEMI)
-            | (force + assgnmt + SEMI)
-            | (release + lvalue + SEMI)
-            | (
-                begin
-                + COLON
-                + identifier
-                + ZeroOrMore(blockDecl)
-                + ZeroOrMore(stmt)
-                + end
-            ).setName("begin:label-end")
-            |
-            # these  *have* to go at the end of the list!!!
-            (assgnmt + SEMI)
-            | (nbAssgnmt + SEMI)
-            | (
-                Combine(Optional("$") + identifier)
-                + Optional(LPAR + delimitedList(expr | empty) + RPAR)
-                + SEMI
-            )
-        ).setName("stmtBody")
-        """
-        x::=<blocking_assignment> ;
-        x||= <non_blocking_assignment> ;
-        x||= if ( <expression> ) <statement_or_null>
-        x||= if ( <expression> ) <statement_or_null> else <statement_or_null>
-        x||= case ( <expression> ) <case_item>+ endcase
-        x||= casez ( <expression> ) <case_item>+ endcase
-        x||= casex ( <expression> ) <case_item>+ endcase
-        x||= forever <statement>
-        x||= repeat ( <expression> ) <statement>
-        x||= while ( <expression> ) <statement>
-        x||= for ( <assignment> ; <expression> ; <assignment> ) <statement>
-        x||= <delay_or_event_control> <statement_or_null>
-        x||= wait ( <expression> ) <statement_or_null>
-        x||= -> <name_of_event> ;
-        x||= <seq_block>
-        x||= <par_block>
-        x||= <task_enable>
-        x||= <system_task_enable>
-        x||= disable <name_of_task> ;
-        x||= disable <name_of_block> ;
-        x||= assign <assignment> ;
-        x||= deassign <lvalue> ;
-        x||= force <assignment> ;
-        x||= release <lvalue> ;
-        """
-        alwaysStmt = Group("always" + Optional(eventControl) + stmt).setName(
-            "alwaysStmt"
-        )
-        initialStmt = Group("initial" + stmt).setName("initialStmt")
-
-        chargeStrength = Group(LPAR + oneOf("small medium large") + RPAR).setName(
-            "chargeStrength"
-        )
-
-        continuousAssign = Group(
-            assign
-            + Optional(driveStrength)
-            + Optional(delay)
-            + delimitedList(assgnmt)
-            + SEMI
-        ).setName("continuousAssign")
-
-        tfDecl = (
-            parameterDecl
-            | inputDecl
-            | outputDecl
-            | inoutDecl
-            | regDecl
-            | timeDecl
-            | integerDecl
-            | realDecl
-        )
-
-        functionDecl = Group(
-            "function"
-            + Optional(range | "integer" | "real")
-            + identifier
-            + SEMI
-            + Group(OneOrMore(tfDecl))
-            + Group(ZeroOrMore(stmt))
-            + "endfunction"
-        )
-
-        inputOutput = oneOf("input output")
-        netDecl1Arg = (
-            nettype
-            + Optional(expandRange)
-            + Optional(delay)
-            + Group(delimitedList(~inputOutput + identifier))
-        )
-        netDecl2Arg = (
-            "trireg"
-            + Optional(chargeStrength)
-            + Optional(expandRange)
-            + Optional(delay)
-            + Group(delimitedList(~inputOutput + identifier))
-        )
-        netDecl3Arg = (
-            nettype
-            + Optional(driveStrength)
-            + Optional(expandRange)
-            + Optional(delay)
-            + Group(delimitedList(assgnmt))
-        )
-        netDecl1 = Group(netDecl1Arg + SEMI).setName("netDecl1")
-        netDecl2 = Group(netDecl2Arg + SEMI).setName("netDecl2")
-        netDecl3 = Group(netDecl3Arg + SEMI).setName("netDecl3")
-
-        gateType = oneOf(
-            "and  nand  or  nor xor  xnor buf  bufif0 bufif1 "
-            "not  notif0 notif1  pulldown pullup nmos  rnmos "
-            "pmos rpmos cmos rcmos   tran rtran  tranif0  "
-            "rtranif0  tranif1 rtranif1"
-        )
-        gateInstance = (
-            Optional(Group(identifier + Optional(range)))
-            + LPAR
-            + Group(delimitedList(expr))
-            + RPAR
-        )
-        gateDecl = Group(
-            gateType
-            + Optional(driveStrength)
-            + Optional(delay)
-            + delimitedList(gateInstance)
-            + SEMI
-        )
-
-        udpInstance = Group(
-            Group(identifier + Optional(range | subscrRef))
-            + LPAR
-            + Group(delimitedList(expr))
-            + RPAR
-        )
-        udpInstantiation = Group(
-            identifier
-            - Optional(driveStrength)
-            + Optional(delay)
-            + delimitedList(udpInstance)
-            + SEMI
-        ).setName("udpInstantiation")
-
-        parameterValueAssignment = Group(
-            Literal("#") + LPAR + Group(delimitedList(expr)) + RPAR
-        )
-        namedPortConnection = Group(DOT + identifier + LPAR + expr + RPAR).setName(
-            "namedPortConnection"
-        )  # .setDebug()
-        assert r".\abc (abc )" == namedPortConnection
-        modulePortConnection = expr | empty
-        # ~ moduleInstance = Group( Group ( identifier + Optional(range) ) +
-        # ~ ( delimitedList( modulePortConnection ) |
-        # ~ delimitedList( namedPortConnection ) ) )
-        inst_args = Group(
-            LPAR
-            + (delimitedList(namedPortConnection) | delimitedList(modulePortConnection))
-            + RPAR
-        ).setName("inst_args")
-        moduleInstance = Group(Group(identifier + Optional(range)) + inst_args).setName(
-            "moduleInstance"
-        )  # .setDebug()
-
-        moduleInstantiation = Group(
-            identifier
-            + Optional(parameterValueAssignment)
-            + delimitedList(moduleInstance).setName("moduleInstanceList")
-            + SEMI
-        ).setName("moduleInstantiation")
-
-        parameterOverride = Group("defparam" + delimitedList(paramAssgnmt) + SEMI)
-        task = Group(
-            "task" + identifier + SEMI + ZeroOrMore(tfDecl) + stmtOrNull + "endtask"
-        )
-
-        specparamDecl = Group("specparam" + delimitedList(paramAssgnmt) + SEMI)
-
-        pathDescr1 = Group(LPAR + subscrIdentifier + "=>" + subscrIdentifier + RPAR)
-        pathDescr2 = Group(
-            LPAR
-            + Group(delimitedList(subscrIdentifier))
-            + "*>"
-            + Group(delimitedList(subscrIdentifier))
-            + RPAR
-        )
-        pathDescr3 = Group(
-            LPAR
-            + Group(delimitedList(subscrIdentifier))
-            + "=>"
-            + Group(delimitedList(subscrIdentifier))
-            + RPAR
-        )
-        pathDelayValue = Group(
-            (LPAR + Group(delimitedList(mintypmaxExpr | expr)) + RPAR)
-            | mintypmaxExpr
-            | expr
-        )
-        pathDecl = Group(
-            (pathDescr1 | pathDescr2 | pathDescr3) + EQ + pathDelayValue + SEMI
-        ).setName("pathDecl")
-
-        portConditionExpr = Forward()
-        portConditionTerm = Optional(unop) + subscrIdentifier
-        portConditionExpr << portConditionTerm + Optional(binop + portConditionExpr)
-        polarityOp = oneOf("+ -")
-        levelSensitivePathDecl1 = Group(
-            if_
-            + Group(LPAR + portConditionExpr + RPAR)
-            + subscrIdentifier
-            + Optional(polarityOp)
-            + "=>"
-            + subscrIdentifier
-            + EQ
-            + pathDelayValue
-            + SEMI
-        )
-        levelSensitivePathDecl2 = Group(
-            if_
-            + Group(LPAR + portConditionExpr + RPAR)
-            + LPAR
-            + Group(delimitedList(subscrIdentifier))
-            + Optional(polarityOp)
-            + "*>"
-            + Group(delimitedList(subscrIdentifier))
-            + RPAR
-            + EQ
-            + pathDelayValue
-            + SEMI
-        )
-        levelSensitivePathDecl = levelSensitivePathDecl1 | levelSensitivePathDecl2
-
-        edgeIdentifier = posedge | negedge
-        edgeSensitivePathDecl1 = Group(
-            Optional(if_ + Group(LPAR + expr + RPAR))
-            + LPAR
-            + Optional(edgeIdentifier)
-            + subscrIdentifier
-            + "=>"
-            + LPAR
-            + subscrIdentifier
-            + Optional(polarityOp)
-            + COLON
-            + expr
-            + RPAR
-            + RPAR
-            + EQ
-            + pathDelayValue
-            + SEMI
-        )
-        edgeSensitivePathDecl2 = Group(
-            Optional(if_ + Group(LPAR + expr + RPAR))
-            + LPAR
-            + Optional(edgeIdentifier)
-            + subscrIdentifier
-            + "*>"
-            + LPAR
-            + delimitedList(subscrIdentifier)
-            + Optional(polarityOp)
-            + COLON
-            + expr
-            + RPAR
-            + RPAR
-            + EQ
-            + pathDelayValue
-            + SEMI
-        )
-        edgeSensitivePathDecl = edgeSensitivePathDecl1 | edgeSensitivePathDecl2
-
-        edgeDescr = oneOf("01 10 0x x1 1x x0").setName("edgeDescr")
-
-        timCheckEventControl = Group(
-            posedge | negedge | (edge + LBRACK + delimitedList(edgeDescr) + RBRACK)
-        )
-        timCheckCond = Forward()
-        timCondBinop = oneOf("== === != !==")
-        timCheckCondTerm = (expr + timCondBinop + scalarConst) | (Optional("~") + expr)
-        timCheckCond << ((LPAR + timCheckCond + RPAR) | timCheckCondTerm)
-        timCheckEvent = Group(
-            Optional(timCheckEventControl)
-            + subscrIdentifier
-            + Optional("&&&" + timCheckCond)
-        )
-        timCheckLimit = expr
-        controlledTimingCheckEvent = Group(
-            timCheckEventControl + subscrIdentifier + Optional("&&&" + timCheckCond)
-        )
-        notifyRegister = identifier
-
-        systemTimingCheck1 = Group(
-            "$setup"
-            + LPAR
-            + timCheckEvent
-            + COMMA
-            + timCheckEvent
-            + COMMA
-            + timCheckLimit
-            + Optional(COMMA + notifyRegister)
-            + RPAR
-            + SEMI
-        )
-        systemTimingCheck2 = Group(
-            "$hold"
-            + LPAR
-            + timCheckEvent
-            + COMMA
-            + timCheckEvent
-            + COMMA
-            + timCheckLimit
-            + Optional(COMMA + notifyRegister)
-            + RPAR
-            + SEMI
-        )
-        systemTimingCheck3 = Group(
-            "$period"
-            + LPAR
-            + controlledTimingCheckEvent
-            + COMMA
-            + timCheckLimit
-            + Optional(COMMA + notifyRegister)
-            + RPAR
-            + SEMI
-        )
-        systemTimingCheck4 = Group(
-            "$width"
-            + LPAR
-            + controlledTimingCheckEvent
-            + COMMA
-            + timCheckLimit
-            + Optional(COMMA + expr + COMMA + notifyRegister)
-            + RPAR
-            + SEMI
-        )
-        systemTimingCheck5 = Group(
-            "$skew"
-            + LPAR
-            + timCheckEvent
-            + COMMA
-            + timCheckEvent
-            + COMMA
-            + timCheckLimit
-            + Optional(COMMA + notifyRegister)
-            + RPAR
-            + SEMI
-        )
-        systemTimingCheck6 = Group(
-            "$recovery"
-            + LPAR
-            + controlledTimingCheckEvent
-            + COMMA
-            + timCheckEvent
-            + COMMA
-            + timCheckLimit
-            + Optional(COMMA + notifyRegister)
-            + RPAR
-            + SEMI
-        )
-        systemTimingCheck7 = Group(
-            "$setuphold"
-            + LPAR
-            + timCheckEvent
-            + COMMA
-            + timCheckEvent
-            + COMMA
-            + timCheckLimit
-            + COMMA
-            + timCheckLimit
-            + Optional(COMMA + notifyRegister)
-            + RPAR
-            + SEMI
-        )
-        systemTimingCheck = (
-            FollowedBy("$")
-            + (
-                systemTimingCheck1
-                | systemTimingCheck2
-                | systemTimingCheck3
-                | systemTimingCheck4
-                | systemTimingCheck5
-                | systemTimingCheck6
-                | systemTimingCheck7
-            )
-        ).setName("systemTimingCheck")
-        sdpd = (
-            if_
-            + Group(LPAR + expr + RPAR)
-            + (pathDescr1 | pathDescr2)
-            + EQ
-            + pathDelayValue
-            + SEMI
-        )
-
-        specifyItem = ~Keyword("endspecify") + (
-            specparamDecl
-            | pathDecl
-            | levelSensitivePathDecl
-            | edgeSensitivePathDecl
-            | systemTimingCheck
-            | sdpd
-        )
-        """
-        x::= <specparam_declaration>
-        x||= <path_declaration>
-        x||= <level_sensitive_path_declaration>
-        x||= <edge_sensitive_path_declaration>
-        x||= <system_timing_check>
-        x||= <sdpd>
-        """
-        specifyBlock = Group(
-            "specify" + ZeroOrMore(specifyItem) + "endspecify"
-        ).setName("specifyBlock")
-
-        moduleItem = ~Keyword("endmodule") + (
-            parameterDecl
-            | inputDecl
-            | outputDecl
-            | inoutDecl
-            | regDecl
-            | netDecl3
-            | netDecl1
-            | netDecl2
-            | timeDecl
-            | integerDecl
-            | realDecl
-            | eventDecl
-            | gateDecl
-            | parameterOverride
-            | continuousAssign
-            | specifyBlock
-            | initialStmt
-            | alwaysStmt
-            | task
-            | functionDecl
-            |
-            # these have to be at the end - they start with identifiers
-            moduleInstantiation
-            | udpInstantiation
-        )
-        """  All possible moduleItems, from Verilog grammar spec
-        x::= <parameter_declaration>
-        x||= <input_declaration>
-        x||= <output_declaration>
-        x||= <inout_declaration>
-        ?||= <net_declaration>  (spec does not seem consistent for this item)
-        x||= <reg_declaration>
-        x||= <time_declaration>
-        x||= <integer_declaration>
-        x||= <real_declaration>
-        x||= <event_declaration>
-        x||= <gate_declaration>
-        x||= <UDP_instantiation>
-        x||= <module_instantiation>
-        x||= <parameter_override>
-        x||= <continuous_assign>
-        x||= <specify_block>
-        x||= <initial_statement>
-        x||= <always_statement>
-        x||= <task>
-        x||= <function>
-        """
-        portRef = subscrIdentifier
-        portExpr = portRef | Group(LBRACE + delimitedList(portRef) + RBRACE)
-        port = portExpr | Group(DOT + identifier + LPAR + portExpr + RPAR)
-
-        moduleHdr = Group(
-            oneOf("module macromodule")
-            + identifier
-            + Optional(
-                LPAR
-                + Group(
-                    Optional(
-                        delimitedList(
-                            Group(
-                                oneOf("input output")
-                                + (netDecl1Arg | netDecl2Arg | netDecl3Arg)
-                            )
-                            | port
-                        )
-                    )
-                )
-                + RPAR
-            )
-            + SEMI
-        ).setName("moduleHdr")
-
-        module = Group(moduleHdr + Group(ZeroOrMore(moduleItem)) + "endmodule").setName(
-            "module"
-        )  # .setDebug()
-
-        udpDecl = outputDecl | inputDecl | regDecl
-        # ~ udpInitVal = oneOf("1'b0 1'b1 1'bx 1'bX 1'B0 1'B1 1'Bx 1'BX 1 0 x X")
-        udpInitVal = (Regex("1'bB01xX") | Regex("01xX")).setName("udpInitVal")
-        udpInitialStmt = Group("initial" + identifier + EQ + udpInitVal + SEMI).setName(
-            "udpInitialStmt"
-        )
-
-        levelSymbol = oneOf("0   1   x   X   ?   b   B")
-        levelInputList = Group(OneOrMore(levelSymbol).setName("levelInpList"))
-        outputSymbol = oneOf("0   1   x   X")
-        combEntry = Group(levelInputList + COLON + outputSymbol + SEMI)
-        edgeSymbol = oneOf("r   R   f   F   p   P   n   N   *")
-        edge = Group(LPAR + levelSymbol + levelSymbol + RPAR) | Group(edgeSymbol)
-        edgeInputList = Group(ZeroOrMore(levelSymbol) + edge + ZeroOrMore(levelSymbol))
-        inputList = levelInputList | edgeInputList
-        seqEntry = Group(
-            inputList + COLON + levelSymbol + COLON + (outputSymbol | "-") + SEMI
-        ).setName("seqEntry")
-        udpTableDefn = Group(
-            "table" + OneOrMore(combEntry | seqEntry) + "endtable"
-        ).setName("table")
-
-        """
-        <UDP>
-        ::= primitive <name_of_UDP> ( <name_of_variable> <,<name_of_variable>>* ) ;
-                <UDP_declaration>+
-                <UDP_initial_statement>?
-                <table_definition>
-                endprimitive
-        """
-        udp = Group(
-            "primitive"
-            + identifier
-            + LPAR
-            + Group(delimitedList(identifier))
-            + RPAR
-            + SEMI
-            + OneOrMore(udpDecl)
-            + Optional(udpInitialStmt)
-            + udpTableDefn
-            + "endprimitive"
-        )
-
-        verilogbnf = OneOrMore(module | udp) + StringEnd()
-
-        verilogbnf.ignore(cppStyleComment)
-        verilogbnf.ignore(compilerDirective)
-
-    return verilogbnf
-
-
-def test(strng):
-    tokens = 
-    try:
-        tokens = Verilog_BNF().parseString(strng)
-    except ParseException as err:
-        print(err.line)
-        print(" " * (err.column - 1) + "^")
-        print(err)
-    return tokens
-
-
-if __name__ == "__main__":
-
-    def main():
-        import sys
-
-        sys.setrecursionlimit(5000)
-        print("Verilog parser test (V %s)" % __version__)
-        print(" - using pyparsing version", pyparsing.__version__)
-        print(" - using Python version", sys.version)
-        if packratOn:
-            print(" - using packrat parsing")
-        print()
-
-        import os
-        import gc
-
-        failCount = 0
-        Verilog_BNF()
-        numlines = 0
-        startTime = time.time()
-        fileDir = "verilog"
-        # ~ fileDir = "verilog/new2"
-        # ~ fileDir = "verilog/new3"
-        allFiles = f for f in os.listdir(fileDir) if f.endswith(".v")
-        # ~ allFiles =  "list_path_delays_test.v" 
-        # ~ allFiles =  "escapedIdent.v" 
-        # ~ allFiles = filter( lambda f : f.startswith("a") and f.endswith(".v"), os.listdir(fileDir) )
-        # ~ allFiles = filter( lambda f : f.startswith("c") and f.endswith(".v"), os.listdir(fileDir) )
-        # ~ allFiles =  "ff.v" 
-
-        pp = pprint.PrettyPrinter(indent=2)
-        totalTime = 0
-        for vfile in allFiles:
-            gc.collect()
-            fnam = fileDir + "/" + vfile
-            infile = open(fnam)
-            filelines = infile.readlines()
-            infile.close()
-            print(fnam, len(filelines), end=" ")
-            numlines += len(filelines)
-            teststr = "".join(filelines)
-            time1 = time.time()
-            tokens = test(teststr)
-            time2 = time.time()
-            elapsed = time2 - time1
-            totalTime += elapsed
-            if len(tokens):
-                print("OK", elapsed)
-
-                ofnam = fileDir + "/parseOutput/" + vfile + ".parsed.txt"
-                with open(ofnam, "w") as outfile:
-                    outfile.write(teststr)
-                    outfile.write("\n\n")
-                    outfile.write(pp.pformat(tokens.asList()))
-                    outfile.write("\n")
-            else:
-                print("failed", elapsed)
-                failCount += 1
-                for i, line in enumerate(filelines, 1):
-                    print("%4d: %s" % (i, line.rstrip()))
-        endTime = time.time()
-        print("Total parse time:", totalTime)
-        print("Total source lines:", numlines)
-        print("Average lines/sec:", ("%.1f" % (float(numlines) / (totalTime + 0.05))))
-        if failCount:
-            print("FAIL - %d files failed to parse" % failCount)
-        else:
-            print("SUCCESS - all files parsed")
-
-        return 0
-
-    main()

_service:tar_scm:pyparsing-3.0.9.tar.gz/pyparsing_archive.py Deleted

@@ -1,7815 +0,0 @@
-# -*- coding: utf-8 -*-
-# module pyparsing.py
-#
-# Copyright (c) 2003-2019  Paul T. McGuire
-#
-# Permission is hereby granted, free of charge, to any person obtaining
-# a copy of this software and associated documentation files (the
-# "Software"), to deal in the Software without restriction, including
-# without limitation the rights to use, copy, modify, merge, publish,
-# distribute, sublicense, and/or sell copies of the Software, and to
-# permit persons to whom the Software is furnished to do so, subject to
-# the following conditions:
-#
-# The above copyright notice and this permission notice shall be
-# included in all copies or substantial portions of the Software.
-#
-# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-# IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-# CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-# TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-# SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-#
-
-__doc__ = """
-pyparsing module - Classes and methods to define and execute parsing grammars
-=============================================================================
-
-The pyparsing module is an alternative approach to creating and
-executing simple grammars, vs. the traditional lex/yacc approach, or the
-use of regular expressions.  With pyparsing, you don't need to learn
-a new syntax for defining grammars or matching expressions - the parsing
-module provides a library of classes that you use to construct the
-grammar directly in Python.
-
-Here is a program to parse "Hello, World!" (or any greeting of the form
-``"<salutation>, <addressee>!"``), built up using :class:`Word`,
-:class:`Literal`, and :class:`And` elements
-(the :class:`'+'<ParserElement.__add__>` operators create :class:`And` expressions,
-and the strings are auto-converted to :class:`Literal` expressions)::
-
-    from pyparsing import Word, alphas
-
-    # define grammar of a greeting
-    greet = Word(alphas) + "," + Word(alphas) + "!"
-
-    hello = "Hello, World!"
-    print(hello, "->", greet.parseString(hello))
-
-The program outputs the following::
-
-    Hello, World! -> 'Hello', ',', 'World', '!'
-
-The Python representation of the grammar is quite readable, owing to the
-self-explanatory class names, and the use of '+', '|' and '^' operators.
-
-The :class:`ParseResults` object returned from
-:class:`ParserElement.parseString` can be
-accessed as a nested list, a dictionary, or an object with named
-attributes.
-
-The pyparsing module handles some of the problems that are typically
-vexing when writing text parsers:
-
-  - extra or missing whitespace (the above program will also handle
-    "Hello,World!", "Hello  ,  World  !", etc.)
-  - quoted strings
-  - embedded comments
-
-
-Getting Started -
------------------
-Visit the classes :class:`ParserElement` and :class:`ParseResults` to
-see the base classes that most other pyparsing
-classes inherit from. Use the docstrings for examples of how to:
-
- - construct literal match expressions from :class:`Literal` and
-   :class:`CaselessLiteral` classes
- - construct character word-group expressions using the :class:`Word`
-   class
- - see how to create repetitive expressions using :class:`ZeroOrMore`
-   and :class:`OneOrMore` classes
- - use :class:`'+'<And>`, :class:`'|'<MatchFirst>`, :class:`'^'<Or>`,
-   and :class:`'&'<Each>` operators to combine simple expressions into
-   more complex ones
- - associate names with your parsed results using
-   :class:`ParserElement.setResultsName`
- - access the parsed data, which is returned as a :class:`ParseResults`
-   object
- - find some helpful expression short-cuts like :class:`delimitedList`
-   and :class:`oneOf`
- - find more useful common expressions in the :class:`pyparsing_common`
-   namespace class
-"""
-
-__version__ = "3.0.0a1"
-__versionTime__ = "13 Oct 2019 05:49 UTC"
-__author__ = "Paul McGuire <ptmcg@users.sourceforge.net>"
-
-import string
-from weakref import ref as wkref
-import copy
-import sys
-import warnings
-import re
-import sre_constants
-import collections
-from collections.abc import Iterable, MutableMapping, Mapping
-import pprint
-import traceback
-import types
-from datetime import datetime
-from operator import itemgetter
-import itertools
-from functools import wraps
-from itertools import filterfalse
-from threading import RLock
-from contextlib import contextmanager
-import unittest
-
-
-class __config_flags:
-    """Internal class for defining compatibility and debugging flags"""
-
-    _all_names = 
-    _fixed_names = 
-    _type_desc = "configuration"
-
-    @classmethod
-    def _set(cls, dname, value):
-        if dname in cls._fixed_names:
-            warnings.warn(
-                "{}.{} {} is {} and cannot be overridden".format(
-                    cls.__name__,
-                    dname,
-                    cls._type_desc,
-                    str(getattr(cls, dname)).upper(),
-                )
-            )
-            return
-        if dname in cls._all_names:
-            setattr(cls, dname, value)
-        else:
-            raise ValueError("no such {} {!r}".format(cls._type_desc, dname))
-
-    enable = classmethod(lambda cls, name: cls._set(name, True))
-    disable = classmethod(lambda cls, name: cls._set(name, False))
-
-
-class __compat__(__config_flags):
-    """
-    A cross-version compatibility configuration for pyparsing features that will be
-    released in a future version. By setting values in this configuration to True,
-    those features can be enabled in prior versions for compatibility development
-    and testing.
-
-     - collect_all_And_tokens - flag to enable fix for Issue #63 that fixes erroneous grouping
-       of results names when an And expression is nested within an Or or MatchFirst;
-       maintained for compatibility, but setting to False no longer restores pre-2.3.1
-       behavior
-    """
-
-    _type_desc = "compatibility"
-
-    collect_all_And_tokens = True
-
-    _all_names = __ for __ in locals() if not __.startswith("_")
-    _fixed_names = """
-        collect_all_And_tokens
-        """.split()
-
-
-class __diag__(__config_flags):
-    """
-    Diagnostic configuration (all default to False)
-     - warn_multiple_tokens_in_named_alternation - flag to enable warnings when a results
-       name is defined on a MatchFirst or Or expression with one or more And subexpressions
-     - warn_ungrouped_named_tokens_in_collection - flag to enable warnings when a results
-       name is defined on a containing expression with ungrouped subexpressions that also
-       have results names
-     - warn_name_set_on_empty_Forward - flag to enable warnings when a Forward is defined
-       with a results name, but has no contents defined
-     - warn_on_multiple_string_args_to_oneof - flag to enable warnings when oneOf is
-       incorrectly called with multiple str arguments
-     - enable_debug_on_named_expressions - flag to auto-enable debug on all subsequent
-       calls to ParserElement.setName()
-    """
-
-    _type_desc = "diagnostic"
-
-    warn_multiple_tokens_in_named_alternation = False
-    warn_ungrouped_named_tokens_in_collection = False
-    warn_name_set_on_empty_Forward = False
-    warn_on_multiple_string_args_to_oneof = False
-    enable_debug_on_named_expressions = False
-
-    _all_names = __ for __ in locals() if not __.startswith("_")
-    _warning_names = name for name in _all_names if name.startswith("warn")
-    _debug_names = name for name in _all_names if name.startswith("enable_debug")
-
-    @classmethod
-    def enable_all_warnings(cls):
-        for name in cls._warning_names:
-            cls.enable(name)
-
-
-# hide abstract class
-del __config_flags
-
-
-# ~ sys.stderr.write("testing pyparsing module, version %s, %s\n" % (__version__, __versionTime__))
-
-__all__ = 
-    "__version__",
-    "__versionTime__",
-    "__author__",
-    "__compat__",
-    "__diag__",
-    "And",
-    "CaselessKeyword",
-    "CaselessLiteral",
-    "CharsNotIn",
-    "Combine",
-    "Dict",
-    "Each",
-    "Empty",
-    "FollowedBy",
-    "Forward",
-    "GoToColumn",
-    "Group",
-    "Keyword",
-    "LineEnd",
-    "LineStart",
-    "Literal",
-    "PrecededBy",
-    "MatchFirst",
-    "NoMatch",
-    "NotAny",
-    "OneOrMore",
-    "OnlyOnce",
-    "Optional",
-    "Or",
-    "ParseBaseException",
-    "ParseElementEnhance",
-    "ParseException",
-    "ParseExpression",
-    "ParseFatalException",
-    "ParseResults",
-    "ParseSyntaxException",
-    "ParserElement",
-    "QuotedString",
-    "RecursiveGrammarException",
-    "Regex",
-    "SkipTo",
-    "StringEnd",
-    "StringStart",
-    "Suppress",
-    "Token",
-    "TokenConverter",
-    "White",
-    "Word",
-    "WordEnd",
-    "WordStart",
-    "ZeroOrMore",
-    "Char",
-    "alphanums",
-    "alphas",
-    "alphas8bit",
-    "anyCloseTag",
-    "anyOpenTag",
-    "cStyleComment",
-    "col",
-    "commonHTMLEntity",
-    "countedArray",
-    "cppStyleComment",
-    "dblQuotedString",
-    "dblSlashComment",
-    "delimitedList",
-    "dictOf",
-    "empty",
-    "hexnums",
-    "htmlComment",
-    "javaStyleComment",
-    "line",
-    "lineEnd",
-    "lineStart",
-    "lineno",
-    "makeHTMLTags",
-    "makeXMLTags",
-    "matchOnlyAtCol",
-    "matchPreviousExpr",
-    "matchPreviousLiteral",
-    "nestedExpr",
-    "nullDebugAction",
-    "nums",
-    "oneOf",
-    "opAssoc",
-    "printables",
-    "punc8bit",
-    "pythonStyleComment",
-    "quotedString",
-    "removeQuotes",
-    "replaceHTMLEntity",
-    "replaceWith",
-    "restOfLine",
-    "sglQuotedString",
-    "srange",
-    "stringEnd",
-    "stringStart",
-    "traceParseAction",
-    "unicodeString",
-    "withAttribute",
-    "indentedBlock",
-    "originalTextFor",
-    "ungroup",
-    "infixNotation",
-    "locatedExpr",
-    "withClass",
-    "CloseMatch",
-    "tokenMap",
-    "pyparsing_common",
-    "pyparsing_unicode",
-    "unicode_set",
-    "conditionAsParseAction",
-    "pyparsing_test",
-    "re",
-
-
-system_version = tuple(sys.version_info):3
-_MAX_INT = sys.maxsize
-str_type = (str, bytes)
-
-# build list of single arg builtins, that can be used as parse actions
-singleArgBuiltins = sum, len, sorted, reversed, list, tuple, set, any, all, min, max
-
-_generatorType = types.GeneratorType
-
-alphas = string.ascii_uppercase + string.ascii_lowercase
-nums = "0123456789"
-hexnums = nums + "ABCDEFabcdef"
-alphanums = alphas + nums
-_bslash = chr(92)
-printables = "".join(c for c in string.printable if c not in string.whitespace)
-
-
-def conditionAsParseAction(fn, message=None, fatal=False):
-    """
-    Function to convert a simple predicate function that returns True or False
-    into a parse action. Can be used in places when a parse action is required
-    and ParserElement.addCondition cannot be used (such as when adding a condition
-    to an operator level in infixNotation).
-
-    Optional keyword arguments:
-    - message = define a custom message to be used in the raised exception
-    - fatal = if True, will raise ParseFatalException to stop parsing immediately; otherwise will raise ParseException
-    """
-    msg = message if message is not None else "failed user-defined condition"
-    exc_type = ParseFatalException if fatal else ParseException
-    fn = _trim_arity(fn)
-
-    @wraps(fn)
-    def pa(s, l, t):
-        if not bool(fn(s, l, t)):
-            raise exc_type(s, l, msg)
-
-    return pa
-
-
-class ParseBaseException(Exception):
-    """base exception class for all parsing runtime exceptions"""
-
-    # Performance tuning: we construct a *lot* of these, so keep this
-    # constructor as small and fast as possible
-    def __init__(self, pstr, loc=0, msg=None, elem=None):
-        self.loc = loc
-        if msg is None:
-            self.msg = pstr
-            self.pstr = ""
-        else:
-            self.msg = msg
-            self.pstr = pstr
-        self.parserElement = elem
-        self.args = (pstr, loc, msg)
-
-    @classmethod
-    def _from_exception(cls, pe):
-        """
-        internal factory method to simplify creating one type of ParseException
-        from another - avoids having __init__ signature conflicts among subclasses
-        """
-        return cls(pe.pstr, pe.loc, pe.msg, pe.parserElement)
-
-    def __getattr__(self, aname):
-        """supported attributes by name are:
-           - lineno - returns the line number of the exception text
-           - col - returns the column number of the exception text
-           - line - returns the line containing the exception text
-        """
-        if aname == "lineno":
-            return lineno(self.loc, self.pstr)
-        elif aname in ("col", "column"):
-            return col(self.loc, self.pstr)
-        elif aname == "line":
-            return line(self.loc, self.pstr)
-        else:
-            raise AttributeError(aname)
-
-    def __str__(self):
-        if self.pstr:
-            if self.loc >= len(self.pstr):
-                foundstr = ", found end of text"
-            else:
-                foundstr = (", found %r" % self.pstrself.loc : self.loc + 1).replace(
-                    r"\\", "\\"
-                )
-        else:
-            foundstr = ""
-        return "%s%s  (at char %d), (line:%d, col:%d)" % (
-            self.msg,
-            foundstr,
-            self.loc,
-            self.lineno,
-            self.column,
-        )
-
-    def __repr__(self):
-        return str(self)
-
-    def markInputline(self, markerString=">!<"):
-        """Extracts the exception line from the input string, and marks
-           the location of the exception with a special symbol.
-        """
-        line_str = self.line
-        line_column = self.column - 1
-        if markerString:
-            line_str = "".join(
-                (line_str:line_column, markerString, line_strline_column:)
-            )
-        return line_str.strip()
-
-    def __dir__(self):
-        return "lineno col line".split() + dir(type(self))
-
-
-class ParseException(ParseBaseException):
-    """
-    Exception thrown when parse expressions don't match class;
-    supported attributes by name are:
-    - lineno - returns the line number of the exception text
-    - col - returns the column number of the exception text
-    - line - returns the line containing the exception text
-
-    Example::
-
-        try:
-            Word(nums).setName("integer").parseString("ABC")
-        except ParseException as pe:
-            print(pe)
-            print("column: {}".format(pe.col))
-
-    prints::
-
-       Expected integer (at char 0), (line:1, col:1)
-        column: 1
-
-    """
-
-    @staticmethod
-    def explain(exc, depth=16):
-        """
-        Method to take an exception and translate the Python internal traceback into a list
-        of the pyparsing expressions that caused the exception to be raised.
-
-        Parameters:
-
-         - exc - exception raised during parsing (need not be a ParseException, in support
-           of Python exceptions that might be raised in a parse action)
-         - depth (default=16) - number of levels back in the stack trace to list expression
-           and function names; if None, the full stack trace names will be listed; if 0, only
-           the failing input line, marker, and exception string will be shown
-
-        Returns a multi-line string listing the ParserElements and/or function names in the
-        exception's stack trace.
-
-        Note: the diagnostic output will include string representations of the expressions
-        that failed to parse. These representations will be more helpful if you use `setName` to
-        give identifiable names to your expressions. Otherwise they will use the default string
-        forms, which may be cryptic to read.
-
-        explain() is only supported under Python 3.
-        """
-        import inspect
-
-        if depth is None:
-            depth = sys.getrecursionlimit()
-        ret = 
-        if isinstance(exc, ParseBaseException):
-            ret.append(exc.line)
-            ret.append(" " * (exc.col - 1) + "^")
-        ret.append("{}: {}".format(type(exc).__name__, exc))
-
-        if depth > 0:
-            callers = inspect.getinnerframes(exc.__traceback__, context=depth)
-            seen = set()
-            for i, ff in enumerate(callers-depth:):
-                frm = ff0
-
-                f_self = frm.f_locals.get("self", None)
-                if isinstance(f_self, ParserElement):
-                    if frm.f_code.co_name not in ("parseImpl", "_parseNoCache"):
-                        continue
-                    if f_self in seen:
-                        continue
-                    seen.add(f_self)
-
-                    self_type = type(f_self)
-                    ret.append(
-                        "{}.{} - {}".format(
-                            self_type.__module__, self_type.__name__, f_self
-                        )
-                    )
-
-                elif f_self is not None:
-                    self_type = type(f_self)
-                    ret.append("{}.{}".format(self_type.__module__, self_type.__name__))
-
-                else:
-                    code = frm.f_code
-                    if code.co_name in ("wrapper", "<module>"):
-                        continue
-
-                    ret.append("{}".format(code.co_name))
-
-                depth -= 1
-                if not depth:
-                    break
-
-        return "\n".join(ret)
-
-
-class ParseFatalException(ParseBaseException):
-    """user-throwable exception thrown when inconsistent parse content
-       is found; stops all parsing immediately"""
-
-    pass
-
-
-class ParseSyntaxException(ParseFatalException):
-    """just like :class:`ParseFatalException`, but thrown internally
-    when an :class:`ErrorStop<And._ErrorStop>` ('-' operator) indicates
-    that parsing is to stop immediately because an unbacktrackable
-    syntax error has been found.
-    """
-
-    pass
-
-
-# ~ class ReparseException(ParseBaseException):
-# ~ """Experimental class - parse actions can raise this exception to cause
-# ~ pyparsing to reparse the input string:
-# ~ - with a modified input string, and/or
-# ~ - with a modified start location
-# ~ Set the values of the ReparseException in the constructor, and raise the
-# ~ exception in a parse action to cause pyparsing to use the new string/location.
-# ~ Setting the values as None causes no change to be made.
-# ~ """
-# ~ def __init_( self, newstring, restartLoc ):
-# ~ self.newParseText = newstring
-# ~ self.reparseLoc = restartLoc
-
-
-class RecursiveGrammarException(Exception):
-    """exception thrown by :class:`ParserElement.validate` if the
-    grammar could be improperly recursive
-    """
-
-    def __init__(self, parseElementList):
-        self.parseElementTrace = parseElementList
-
-    def __str__(self):
-        return "RecursiveGrammarException: %s" % self.parseElementTrace
-
-
-class _ParseResultsWithOffset(object):
-    def __init__(self, p1, p2):
-        self.tup = (p1, p2)
-
-    def __getitem__(self, i):
-        return self.tupi
-
-    def __repr__(self):
-        return repr(self.tup0)
-
-    def setOffset(self, i):
-        self.tup = (self.tup0, i)
-
-
-class ParseResults(object):
-    """Structured parse results, to provide multiple means of access to
-    the parsed data:
-
-       - as a list (``len(results)``)
-       - by list index (``results0, results1``, etc.)
-       - by attribute (``results.<resultsName>`` - see :class:`ParserElement.setResultsName`)
-
-    Example::
-
-        integer = Word(nums)
-        date_str = (integer.setResultsName("year") + '/'
-                        + integer.setResultsName("month") + '/'
-                        + integer.setResultsName("day"))
-        # equivalent form:
-        # date_str = integer("year") + '/' + integer("month") + '/' + integer("day")
-
-        # parseString returns a ParseResults object
-        result = date_str.parseString("1999/12/31")
-
-        def test(s, fn=repr):
-            print("%s -> %s" % (s, fn(eval(s))))
-        test("list(result)")
-        test("result0")
-        test("result'month'")
-        test("result.day")
-        test("'month' in result")
-        test("'minutes' in result")
-        test("result.dump()", str)
-
-    prints::
-
-        list(result) -> '1999', '/', '12', '/', '31'
-        result0 -> '1999'
-        result'month' -> '12'
-        result.day -> '31'
-        'month' in result -> True
-        'minutes' in result -> False
-        result.dump() -> '1999', '/', '12', '/', '31'
-        - day: 31
-        - month: 12
-        - year: 1999
-    """
-
-    def __new__(cls, toklist=None, name=None, asList=True, modal=True):
-        if isinstance(toklist, ParseResults):
-            return toklist
-        retobj = object.__new__(cls)
-        retobj.__doinit = True
-        return retobj
-
-    # Performance tuning: we construct a *lot* of these, so keep this
-    # constructor as small and fast as possible
-    def __init__(
-        self, toklist=None, name=None, asList=True, modal=True, isinstance=isinstance
-    ):
-        if self.__doinit:
-            self.__doinit = False
-            self.__name = None
-            self.__parent = None
-            self.__accumNames = {}
-            self.__asList = asList
-            self.__modal = modal
-            if toklist is None:
-                toklist = 
-            if isinstance(toklist, list):
-                self.__toklist = toklist:
-            elif isinstance(toklist, _generatorType):
-                self.__toklist = list(toklist)
-            else:
-                self.__toklist = toklist
-            self.__tokdict = dict()
-
-        if name is not None and name:
-            if not modal:
-                self.__accumNamesname = 0
-            if isinstance(name, int):
-                name = str(name)
-            self.__name = name
-            if not (
-                isinstance(toklist, (type(None), *str_type, list))
-                and toklist in (None, "", )
-            ):
-                if isinstance(toklist, str_type):
-                    toklist = toklist
-                if asList:
-                    if isinstance(toklist, ParseResults):
-                        selfname = _ParseResultsWithOffset(
-                            ParseResults(toklist.__toklist), 0
-                        )
-                    else:
-                        selfname = _ParseResultsWithOffset(
-                            ParseResults(toklist0), 0
-                        )
-                    selfname.__name = name
-                else:
-                    try:
-                        selfname = toklist0
-                    except (KeyError, TypeError, IndexError):
-                        selfname = toklist
-
-    def __getitem__(self, i):
-        if isinstance(i, (int, slice)):
-            return self.__toklisti
-        else:
-            if i not in self.__accumNames:
-                return self.__tokdicti-10
-            else:
-                return ParseResults(v0 for v in self.__tokdicti)
-
-    def __setitem__(self, k, v, isinstance=isinstance):
-        if isinstance(v, _ParseResultsWithOffset):
-            self.__tokdictk = self.__tokdict.get(k, list()) + v
-            sub = v0
-        elif isinstance(k, (int, slice)):
-            self.__toklistk = v
-            sub = v
-        else:
-            self.__tokdictk = self.__tokdict.get(k, list()) + 
-                _ParseResultsWithOffset(v, 0)
-            
-            sub = v
-        if isinstance(sub, ParseResults):
-            sub.__parent = wkref(self)
-
-    def __delitem__(self, i):
-        if isinstance(i, (int, slice)):
-            mylen = len(self.__toklist)
-            del self.__toklisti
-
-            # convert int to slice
-            if isinstance(i, int):
-                if i < 0:
-                    i += mylen
-                i = slice(i, i + 1)
-            # get removed indices
-            removed = list(range(*i.indices(mylen)))
-            removed.reverse()
-            # fixup indices in token dictionary
-            for name, occurrences in self.__tokdict.items():
-                for j in removed:
-                    for k, (value, position) in enumerate(occurrences):
-                        occurrencesk = _ParseResultsWithOffset(
-                            value, position - (position > j)
-                        )
-        else:
-            del self.__tokdicti
-
-    def __contains__(self, k):
-        return k in self.__tokdict
-
-    def __len__(self):
-        return len(self.__toklist)
-
-    def __bool__(self):
-        return not not self.__toklist
-
-    def __iter__(self):
-        return iter(self.__toklist)
-
-    def __reversed__(self):
-        return iter(self.__toklist::-1)
-
-    def keys(self):
-        return iter(self.__tokdict)
-
-    def values(self):
-        return (selfk for k in self.keys())
-
-    def items(self):
-        return ((k, selfk) for k in self.keys())
-
-    def haskeys(self):
-        """Since keys() returns an iterator, this method is helpful in bypassing
-           code that looks for the existence of any defined results names."""
-        return bool(self.__tokdict)
-
-    def pop(self, *args, **kwargs):
-        """
-        Removes and returns item at specified index (default= ``last``).
-        Supports both ``list`` and ``dict`` semantics for ``pop()``. If
-        passed no argument or an integer argument, it will use ``list``
-        semantics and pop tokens from the list of parsed tokens. If passed
-        a non-integer argument (most likely a string), it will use ``dict``
-        semantics and pop the corresponding value from any defined results
-        names. A second default return value argument is supported, just as in
-        ``dict.pop()``.
-
-        Example::
-
-            def remove_first(tokens):
-                tokens.pop(0)
-            print(OneOrMore(Word(nums)).parseString("0 123 321")) # -> '0', '123', '321'
-            print(OneOrMore(Word(nums)).addParseAction(remove_first).parseString("0 123 321")) # -> '123', '321'
-
-            label = Word(alphas)
-            patt = label("LABEL") + OneOrMore(Word(nums))
-            print(patt.parseString("AAB 123 321").dump())
-
-            # Use pop() in a parse action to remove named result (note that corresponding value is not
-            # removed from list form of results)
-            def remove_LABEL(tokens):
-                tokens.pop("LABEL")
-                return tokens
-            patt.addParseAction(remove_LABEL)
-            print(patt.parseString("AAB 123 321").dump())
-
-        prints::
-
-            'AAB', '123', '321'
-            - LABEL: AAB
-
-            'AAB', '123', '321'
-        """
-        if not args:
-            args = -1
-        for k, v in kwargs.items():
-            if k == "default":
-                args = (args0, v)
-            else:
-                raise TypeError("pop() got an unexpected keyword argument '%s'" % k)
-        if isinstance(args0, int) or len(args) == 1 or args0 in self:
-            index = args0
-            ret = selfindex
-            del selfindex
-            return ret
-        else:
-            defaultvalue = args1
-            return defaultvalue
-
-    def get(self, key, defaultValue=None):
-        """
-        Returns named result matching the given key, or if there is no
-        such name, then returns the given ``defaultValue`` or ``None`` if no
-        ``defaultValue`` is specified.
-
-        Similar to ``dict.get()``.
-
-        Example::
-
-            integer = Word(nums)
-            date_str = integer("year") + '/' + integer("month") + '/' + integer("day")
-
-            result = date_str.parseString("1999/12/31")
-            print(result.get("year")) # -> '1999'
-            print(result.get("hour", "not specified")) # -> 'not specified'
-            print(result.get("hour")) # -> None
-        """
-        if key in self:
-            return selfkey
-        else:
-            return defaultValue
-
-    def insert(self, index, insStr):
-        """
-        Inserts new element at location index in the list of parsed tokens.
-
-        Similar to ``list.insert()``.
-
-        Example::
-
-            print(OneOrMore(Word(nums)).parseString("0 123 321")) # -> '0', '123', '321'
-
-            # use a parse action to insert the parse location in the front of the parsed results
-            def insert_locn(locn, tokens):
-                tokens.insert(0, locn)
-            print(OneOrMore(Word(nums)).addParseAction(insert_locn).parseString("0 123 321")) # -> 0, '0', '123', '321'
-        """
-        self.__toklist.insert(index, insStr)
-        # fixup indices in token dictionary
-        for name, occurrences in self.__tokdict.items():
-            for k, (value, position) in enumerate(occurrences):
-                occurrencesk = _ParseResultsWithOffset(
-                    value, position + (position > index)
-                )
-
-    def append(self, item):
-        """
-        Add single element to end of ParseResults list of elements.
-
-        Example::
-
-            print(OneOrMore(Word(nums)).parseString("0 123 321")) # -> '0', '123', '321'
-
-            # use a parse action to compute the sum of the parsed integers, and add it to the end
-            def append_sum(tokens):
-                tokens.append(sum(map(int, tokens)))
-            print(OneOrMore(Word(nums)).addParseAction(append_sum).parseString("0 123 321")) # -> '0', '123', '321', 444
-        """
-        self.__toklist.append(item)
-
-    def extend(self, itemseq):
-        """
-        Add sequence of elements to end of ParseResults list of elements.
-
-        Example::
-
-            patt = OneOrMore(Word(alphas))
-
-            # use a parse action to append the reverse of the matched strings, to make a palindrome
-            def make_palindrome(tokens):
-                tokens.extend(reversed(t::-1 for t in tokens))
-                return ''.join(tokens)
-            print(patt.addParseAction(make_palindrome).parseString("lskdj sdlkjf lksd")) # -> 'lskdjsdlkjflksddsklfjkldsjdksl'
-        """
-        if isinstance(itemseq, ParseResults):
-            self.__iadd__(itemseq)
-        else:
-            self.__toklist.extend(itemseq)
-
-    def clear(self):
-        """
-        Clear all elements and results names.
-        """
-        del self.__toklist:
-        self.__tokdict.clear()
-
-    def __getattr__(self, name):
-        try:
-            return selfname
-        except KeyError:
-            return ""
-
-    def __add__(self, other):
-        ret = self.copy()
-        ret += other
-        return ret
-
-    def __iadd__(self, other):
-        if other.__tokdict:
-            offset = len(self.__toklist)
-            addoffset = lambda a: offset if a < 0 else a + offset
-            otheritems = other.__tokdict.items()
-            otherdictitems = 
-                (k, _ParseResultsWithOffset(v0, addoffset(v1)))
-                for k, vlist in otheritems
-                for v in vlist
-            
-            for k, v in otherdictitems:
-                selfk = v
-                if isinstance(v0, ParseResults):
-                    v0.__parent = wkref(self)
-
-        self.__toklist += other.__toklist
-        self.__accumNames.update(other.__accumNames)
-        return self
-
-    def __radd__(self, other):
-        if isinstance(other, int) and other == 0:
-            # useful for merging many ParseResults using sum() builtin
-            return self.copy()
-        else:
-            # this may raise a TypeError - so be it
-            return other + self
-
-    def __repr__(self):
-        return "(%s, %s)" % (repr(self.__toklist), repr(self.__tokdict))
-
-    def __str__(self):
-        return (
-            ""
-            + ", ".join(
-                str(i) if isinstance(i, ParseResults) else repr(i)
-                for i in self.__toklist
-            )
-            + ""
-        )
-
-    def _asStringList(self, sep=""):
-        out = 
-        for item in self.__toklist:
-            if out and sep:
-                out.append(sep)
-            if isinstance(item, ParseResults):
-                out += item._asStringList()
-            else:
-                out.append(str(item))
-        return out
-
-    def asList(self):
-        """
-        Returns the parse results as a nested list of matching tokens, all converted to strings.
-
-        Example::
-
-            patt = OneOrMore(Word(alphas))
-            result = patt.parseString("sldkj lsdkj sldkj")
-            # even though the result prints in string-like form, it is actually a pyparsing ParseResults
-            print(type(result), result) # -> <class 'pyparsing.ParseResults'> 'sldkj', 'lsdkj', 'sldkj'
-
-            # Use asList() to create an actual list
-            result_list = result.asList()
-            print(type(result_list), result_list) # -> <class 'list'> 'sldkj', 'lsdkj', 'sldkj'
-        """
-        return 
-            res.asList() if isinstance(res, ParseResults) else res
-            for res in self.__toklist
-        
-
-    def asDict(self):
-        """
-        Returns the named parse results as a nested dictionary.
-
-        Example::
-
-            integer = Word(nums)
-            date_str = integer("year") + '/' + integer("month") + '/' + integer("day")
-
-            result = date_str.parseString('12/31/1999')
-            print(type(result), repr(result)) # -> <class 'pyparsing.ParseResults'> ('12', '/', '31', '/', '1999', {'day': ('1999', 4), 'year': ('12', 0), 'month': ('31', 2)})
-
-            result_dict = result.asDict()
-            print(type(result_dict), repr(result_dict)) # -> <class 'dict'> {'day': '1999', 'year': '12', 'month': '31'}
-
-            # even though a ParseResults supports dict-like access, sometime you just need to have a dict
-            import json
-            print(json.dumps(result)) # -> Exception: TypeError: ... is not JSON serializable
-            print(json.dumps(result.asDict())) # -> {"month": "31", "day": "1999", "year": "12"}
-        """
-
-        def to_item(obj):
-            if isinstance(obj, ParseResults):
-                return obj.asDict() if obj.haskeys() else to_item(v) for v in obj
-            else:
-                return obj
-
-        return dict((k, to_item(v)) for k, v in self.items())
-
-    def copy(self):
-        """
-        Returns a new copy of a :class:`ParseResults` object.
-        """
-        ret = ParseResults(self.__toklist)
-        ret.__tokdict = dict(self.__tokdict.items())
-        ret.__parent = self.__parent
-        ret.__accumNames.update(self.__accumNames)
-        ret.__name = self.__name
-        return ret
-
-    def getName(self):
-        r"""
-        Returns the results name for this token expression. Useful when several
-        different expressions might match at a particular location.
-
-        Example::
-
-            integer = Word(nums)
-            ssn_expr = Regex(r"\d\d\d-\d\d-\d\d\d\d")
-            house_number_expr = Suppress('#') + Word(nums, alphanums)
-            user_data = (Group(house_number_expr)("house_number")
-                        | Group(ssn_expr)("ssn")
-                        | Group(integer)("age"))
-            user_info = OneOrMore(user_data)
-
-            result = user_info.parseString("22 111-22-3333 #221B")
-            for item in result:
-                print(item.getName(), ':', item0)
-
-        prints::
-
-            age : 22
-            ssn : 111-22-3333
-            house_number : 221B
-        """
-        if self.__name:
-            return self.__name
-        elif self.__parent:
-            par = self.__parent()
-
-            def lookup(self, sub):
-                return next(
-                    (
-                        k
-                        for k, vlist in par.__tokdict.items()
-                        for v, loc in vlist
-                        if sub is v
-                    ),
-                    None,
-                )
-
-            return lookup(self) if par else None
-        elif (
-            len(self) == 1
-            and len(self.__tokdict) == 1
-            and next(iter(self.__tokdict.values()))01 in (0, -1)
-        ):
-            return next(iter(self.__tokdict.keys()))
-        else:
-            return None
-
-    def dump(self, indent="", full=True, include_list=True, _depth=0):
-        """
-        Diagnostic method for listing out the contents of
-        a :class:`ParseResults`. Accepts an optional ``indent`` argument so
-        that this string can be embedded in a nested display of other data.
-
-        Example::
-
-            integer = Word(nums)
-            date_str = integer("year") + '/' + integer("month") + '/' + integer("day")
-
-            result = date_str.parseString('12/31/1999')
-            print(result.dump())
-
-        prints::
-
-            '12', '/', '31', '/', '1999'
-            - day: 1999
-            - month: 31
-            - year: 12
-        """
-        out = 
-        NL = "\n"
-        out.append(indent + str(self.asList()) if include_list else "")
-
-        if full:
-            if self.haskeys():
-                items = sorted((str(k), v) for k, v in self.items())
-                for k, v in items:
-                    if out:
-                        out.append(NL)
-                    out.append("%s%s- %s: " % (indent, ("  " * _depth), k))
-                    if isinstance(v, ParseResults):
-                        if v:
-                            out.append(
-                                v.dump(
-                                    indent=indent,
-                                    full=full,
-                                    include_list=include_list,
-                                    _depth=_depth + 1,
-                                )
-                            )
-                        else:
-                            out.append(str(v))
-                    else:
-                        out.append(repr(v))
-            elif any(isinstance(vv, ParseResults) for vv in self):
-                v = self
-                for i, vv in enumerate(v):
-                    if isinstance(vv, ParseResults):
-                        out.append(
-                            "\n%s%s%d:\n%s%s%s"
-                            % (
-                                indent,
-                                ("  " * (_depth)),
-                                i,
-                                indent,
-                                ("  " * (_depth + 1)),
-                                vv.dump(
-                                    indent=indent,
-                                    full=full,
-                                    include_list=include_list,
-                                    _depth=_depth + 1,
-                                ),
-                            )
-                        )
-                    else:
-                        out.append(
-                            "\n%s%s%d:\n%s%s%s"
-                            % (
-                                indent,
-                                ("  " * (_depth)),
-                                i,
-                                indent,
-                                ("  " * (_depth + 1)),
-                                str(vv),
-                            )
-                        )
-
-        return "".join(out)
-
-    def pprint(self, *args, **kwargs):
-        """
-        Pretty-printer for parsed results as a list, using the
-        `pprint <https://docs.python.org/3/library/pprint.html>`_ module.
-        Accepts additional positional or keyword args as defined for
-        `pprint.pprint <https://docs.python.org/3/library/pprint.html#pprint.pprint>`_ .
-
-        Example::
-
-            ident = Word(alphas, alphanums)
-            num = Word(nums)
-            func = Forward()
-            term = ident | num | Group('(' + func + ')')
-            func <<= ident + Group(Optional(delimitedList(term)))
-            result = func.parseString("fna a,b,(fnb c,d,200),100")
-            result.pprint(width=40)
-
-        prints::
-
-            'fna',
-             'a',
-              'b',
-              '(', 'fnb', 'c', 'd', '200', ')',
-              '100'
-        """
-        pprint.pprint(self.asList(), *args, **kwargs)
-
-    # add support for pickle protocol
-    def __getstate__(self):
-        return (
-            self.__toklist,
-            (
-                self.__tokdict.copy(),
-                self.__parent is not None and self.__parent() or None,
-                self.__accumNames,
-                self.__name,
-            ),
-        )
-
-    def __setstate__(self, state):
-        self.__toklist = state0
-        self.__tokdict, par, inAccumNames, self.__name = state1
-        self.__accumNames = {}
-        self.__accumNames.update(inAccumNames)
-        if par is not None:
-            self.__parent = wkref(par)
-        else:
-            self.__parent = None
-
-    def __getnewargs__(self):
-        return self.__toklist, self.__name, self.__asList, self.__modal
-
-    def __dir__(self):
-        return dir(type(self)) + list(self.keys())
-
-    @classmethod
-    def from_dict(cls, other, name=None):
-        """
-        Helper classmethod to construct a ParseResults from a dict, preserving the
-        name-value relations as results names. If an optional 'name' argument is
-        given, a nested ParseResults will be returned
-        """
-
-        def is_iterable(obj):
-            try:
-                iter(obj)
-            except Exception:
-                return False
-            else:
-                return not isinstance(obj, str_type)
-
-        ret = cls()
-        for k, v in other.items():
-            if isinstance(v, Mapping):
-                ret += cls.from_dict(v, name=k)
-            else:
-                ret += cls(v, name=k, asList=is_iterable(v))
-        if name is not None:
-            ret = cls(ret, name=name)
-        return ret
-
-
-MutableMapping.register(ParseResults)
-
-
-def col(loc, strg):
-    """Returns current column within a string, counting newlines as line separators.
-   The first column is number 1.
-
-   Note: the default parsing behavior is to expand tabs in the input string
-   before starting the parsing process.  See
-   :class:`ParserElement.parseString` for more
-   information on parsing strings containing ``<TAB>`` s, and suggested
-   methods to maintain a consistent view of the parsed string, the parse
-   location, and line and column positions within the parsed string.
-   """
-    s = strg
-    return 1 if 0 < loc < len(s) and sloc - 1 == "\n" else loc - s.rfind("\n", 0, loc)
-
-
-def lineno(loc, strg):
-    """Returns current line number within a string, counting newlines as line separators.
-    The first line is number 1.
-
-    Note - the default parsing behavior is to expand tabs in the input string
-    before starting the parsing process.  See :class:`ParserElement.parseString`
-    for more information on parsing strings containing ``<TAB>`` s, and
-    suggested methods to maintain a consistent view of the parsed string, the
-    parse location, and line and column positions within the parsed string.
-    """
-    return strg.count("\n", 0, loc) + 1
-
-
-def line(loc, strg):
-    """Returns the line of text containing loc within a string, counting newlines as line separators.
-       """
-    lastCR = strg.rfind("\n", 0, loc)
-    nextCR = strg.find("\n", loc)
-    return strglastCR + 1 : nextCR if nextCR >= 0 else strglastCR + 1 :
-
-
-def _defaultStartDebugAction(instring, loc, expr):
-    print(
-        (
-            "Match "
-            + str(expr)
-            + " at loc "
-            + str(loc)
-            + "(%d,%d)" % (lineno(loc, instring), col(loc, instring))
-        )
-    )
-
-
-def _defaultSuccessDebugAction(instring, startloc, endloc, expr, toks):
-    print("Matched " + str(expr) + " -> " + str(toks.asList()))
-
-
-def _defaultExceptionDebugAction(instring, loc, expr, exc):
-    print("Exception raised:" + str(exc))
-
-
-def nullDebugAction(*args):
-    """'Do-nothing' debug action, to suppress debugging output during parsing."""
-    pass
-
-
-def _trim_arity(func, maxargs=2):
-    "decorator to trim function calls to match the arity of the target"
-
-    if func in singleArgBuiltins:
-        return lambda s, l, t: func(t)
-
-    limit = 0
-    found_arity = False
-
-    # traceback return data structure changed in Py3.5 - normalize back to plain tuples
-    def extract_stack(limit=0):
-        # special handling for Python 3.5.0 - extra deep call stack by 1
-        offset = -3 if system_version == (3, 5, 0) else -2
-        frame_summary = traceback.extract_stack(limit=-offset + limit - 1)offset
-        return frame_summary:2
-
-    def extract_tb(tb, limit=0):
-        frames = traceback.extract_tb(tb, limit=limit)
-        frame_summary = frames-1
-        return frame_summary:2
-
-    # synthesize what would be returned by traceback.extract_stack at the call to
-    # user's parse action 'func', so that we don't incur call penalty at parse time
-
-    LINE_DIFF = 7
-    # IF ANY CODE CHANGES, EVEN JUST COMMENTS OR BLANK LINES, BETWEEN THE NEXT LINE AND
-    # THE CALL TO FUNC INSIDE WRAPPER, LINE_DIFF MUST BE MODIFIED!!!!
-    this_line = extract_stack(limit=2)-1
-    pa_call_line_synth = (this_line0, this_line1 + LINE_DIFF)
-
-    def wrapper(*args):
-        nonlocal found_arity, limit
-        while 1:
-            try:
-                ret = func(*argslimit:)
-                found_arity = True
-                return ret
-            except TypeError:
-                # re-raise TypeErrors if they did not come from our arity testing
-                if found_arity:
-                    raise
-                else:
-                    try:
-                        tb = sys.exc_info()-1
-                        if not extract_tb(tb, limit=2)-1:2 == pa_call_line_synth:
-                            raise
-                    finally:
-                        try:
-                            del tb
-                        except NameError:
-                            pass
-
-                if limit <= maxargs:
-                    limit += 1
-                    continue
-                raise
-
-    # copy func name to wrapper for sensible debug output
-    func_name = "<parse action>"
-    try:
-        func_name = getattr(func, "__name__", getattr(func, "__class__").__name__)
-    except Exception:
-        func_name = str(func)
-    wrapper.__name__ = func_name
-
-    return wrapper
-
-
-class ParserElement(object):
-    """Abstract base level parser element class."""
-
-    DEFAULT_WHITE_CHARS = " \n\t\r"
-    verbose_stacktrace = False
-
-    @staticmethod
-    def setDefaultWhitespaceChars(chars):
-        r"""
-        Overrides the default whitespace chars
-
-        Example::
-
-            # default whitespace chars are space, <TAB> and newline
-            OneOrMore(Word(alphas)).parseString("abc def\nghi jkl")  # -> 'abc', 'def', 'ghi', 'jkl'
-
-            # change to just treat newline as significant
-            ParserElement.setDefaultWhitespaceChars(" \t")
-            OneOrMore(Word(alphas)).parseString("abc def\nghi jkl")  # -> 'abc', 'def'
-        """
-        ParserElement.DEFAULT_WHITE_CHARS = chars
-
-        # update whitespace all parse expressions defined in this module
-        for expr in _builtin_exprs:
-            if expr.copyDefaultWhiteChars:
-                expr.whiteChars = chars
-
-    @staticmethod
-    def inlineLiteralsUsing(cls):
-        """
-        Set class to be used for inclusion of string literals into a parser.
-
-        Example::
-
-            # default literal class used is Literal
-            integer = Word(nums)
-            date_str = integer("year") + '/' + integer("month") + '/' + integer("day")
-
-            date_str.parseString("1999/12/31")  # -> '1999', '/', '12', '/', '31'
-
-
-            # change to Suppress
-            ParserElement.inlineLiteralsUsing(Suppress)
-            date_str = integer("year") + '/' + integer("month") + '/' + integer("day")
-
-            date_str.parseString("1999/12/31")  # -> '1999', '12', '31'
-        """
-        ParserElement._literalStringClass = cls
-
-    def __init__(self, savelist=False):
-        self.parseAction = list()
-        self.failAction = None
-        # ~ self.name = "<unknown>"  # don't define self.name, let subclasses try/except upcall
-        self.strRepr = None
-        self.resultsName = None
-        self.saveAsList = savelist
-        self.skipWhitespace = True
-        self.whiteChars = set(ParserElement.DEFAULT_WHITE_CHARS)
-        self.copyDefaultWhiteChars = True
-        self.mayReturnEmpty = False  # used when checking for left-recursion
-        self.keepTabs = False
-        self.ignoreExprs = list()
-        self.debug = False
-        self.streamlined = False
-        self.mayIndexError = True  # used to optimize exception handling for subclasses that don't advance parse index
-        self.errmsg = ""
-        self.modalResults = True  # used to mark results names as modal (report only last) or cumulative (list all)
-        self.debugActions = (None, None, None)  # custom debug actions
-        self.re = None
-        self.callPreparse = True  # used to avoid redundant calls to preParse
-        self.callDuringTry = False
-
-    def copy(self):
-        """
-        Make a copy of this :class:`ParserElement`.  Useful for defining
-        different parse actions for the same parsing pattern, using copies of
-        the original parse element.
-
-        Example::
-
-            integer = Word(nums).setParseAction(lambda toks: int(toks0))
-            integerK = integer.copy().addParseAction(lambda toks: toks0 * 1024) + Suppress("K")
-            integerM = integer.copy().addParseAction(lambda toks: toks0 * 1024 * 1024) + Suppress("M")
-
-            print(OneOrMore(integerK | integerM | integer).parseString("5K 100 640K 256M"))
-
-        prints::
-
-            5120, 100, 655360, 268435456
-
-        Equivalent form of ``expr.copy()`` is just ``expr()``::
-
-            integerM = integer().addParseAction(lambda toks: toks0 * 1024 * 1024) + Suppress("M")
-        """
-        cpy = copy.copy(self)
-        cpy.parseAction = self.parseAction:
-        cpy.ignoreExprs = self.ignoreExprs:
-        if self.copyDefaultWhiteChars:
-            cpy.whiteChars = ParserElement.DEFAULT_WHITE_CHARS
-        return cpy
-
-    def setName(self, name):
-        """
-        Define name for this expression, makes debugging and exception messages clearer.
-
-        Example::
-
-            Word(nums).parseString("ABC")  # -> Exception: Expected W:(0123...) (at char 0), (line:1, col:1)
-            Word(nums).setName("integer").parseString("ABC")  # -> Exception: Expected integer (at char 0), (line:1, col:1)
-        """
-        self.name = name
-        self.errmsg = "Expected " + self.name
-        if __diag__.enable_debug_on_named_expressions:
-            self.setDebug()
-        return self
-
-    def setResultsName(self, name, listAllMatches=False):
-        """
-        Define name for referencing matching tokens as a nested attribute
-        of the returned parse results.
-        NOTE: this returns a *copy* of the original :class:`ParserElement` object;
-        this is so that the client can define a basic element, such as an
-        integer, and reference it in multiple places with different names.
-
-        You can also set results names using the abbreviated syntax,
-        ``expr("name")`` in place of ``expr.setResultsName("name")``
-        - see :class:`__call__`.
-
-        Example::
-
-            date_str = (integer.setResultsName("year") + '/'
-                        + integer.setResultsName("month") + '/'
-                        + integer.setResultsName("day"))
-
-            # equivalent form:
-            date_str = integer("year") + '/' + integer("month") + '/' + integer("day")
-        """
-        return self._setResultsName(name, listAllMatches)
-
-    def _setResultsName(self, name, listAllMatches=False):
-        newself = self.copy()
-        if name.endswith("*"):
-            name = name:-1
-            listAllMatches = True
-        newself.resultsName = name
-        newself.modalResults = not listAllMatches
-        return newself
-
-    def setBreak(self, breakFlag=True):
-        """Method to invoke the Python pdb debugger when this element is
-           about to be parsed. Set ``breakFlag`` to True to enable, False to
-           disable.
-        """
-        if breakFlag:
-            _parseMethod = self._parse
-
-            def breaker(instring, loc, doActions=True, callPreParse=True):
-                import pdb
-
-                # this call to pdb.set_trace() is intentional, not a checkin error
-                pdb.set_trace()
-                return _parseMethod(instring, loc, doActions, callPreParse)
-
-            breaker._originalParseMethod = _parseMethod
-            self._parse = breaker
-        else:
-            if hasattr(self._parse, "_originalParseMethod"):
-                self._parse = self._parse._originalParseMethod
-        return self
-
-    def setParseAction(self, *fns, **kwargs):
-        """
-        Define one or more actions to perform when successfully matching parse element definition.
-        Parse action fn is a callable method with 0-3 arguments, called as ``fn(s, loc, toks)`` ,
-        ``fn(loc, toks)`` , ``fn(toks)`` , or just ``fn()`` , where:
-
-        - s   = the original string being parsed (see note below)
-        - loc = the location of the matching substring
-        - toks = a list of the matched tokens, packaged as a :class:`ParseResults` object
-
-        If the functions in fns modify the tokens, they can return them as the return
-        value from fn, and the modified list of tokens will replace the original.
-        Otherwise, fn does not need to return any value.
-
-        If None is passed as the parse action, all previously added parse actions for this
-        expression are cleared.
-
-        Optional keyword arguments:
-        - callDuringTry = (default= ``False``) indicate if parse action should be run during lookaheads and alternate testing
-
-        Note: the default parsing behavior is to expand tabs in the input string
-        before starting the parsing process.  See :class:`parseString for more
-        information on parsing strings containing ``<TAB>`` s, and suggested
-        methods to maintain a consistent view of the parsed string, the parse
-        location, and line and column positions within the parsed string.
-
-        Example::
-
-            integer = Word(nums)
-            date_str = integer + '/' + integer + '/' + integer
-
-            date_str.parseString("1999/12/31")  # -> '1999', '/', '12', '/', '31'
-
-            # use parse action to convert to ints at parse time
-            integer = Word(nums).setParseAction(lambda toks: int(toks0))
-            date_str = integer + '/' + integer + '/' + integer
-
-            # note that integer fields are now ints, not strings
-            date_str.parseString("1999/12/31")  # -> 1999, '/', 12, '/', 31
-        """
-        if list(fns) == 
-            None,
-        :
-            self.parseAction = 
-        else:
-            if not all(callable(fn) for fn in fns):
-                raise TypeError("parse actions must be callable")
-            self.parseAction = list(map(_trim_arity, list(fns)))
-            self.callDuringTry = kwargs.get("callDuringTry", False)
-        return self
-
-    def addParseAction(self, *fns, **kwargs):
-        """
-        Add one or more parse actions to expression's list of parse actions. See :class:`setParseAction`.
-
-        See examples in :class:`copy`.
-        """
-        self.parseAction += list(map(_trim_arity, list(fns)))
-        self.callDuringTry = self.callDuringTry or kwargs.get("callDuringTry", False)
-        return self
-
-    def addCondition(self, *fns, **kwargs):
-        """Add a boolean predicate function to expression's list of parse actions. See
-        :class:`setParseAction` for function call signatures. Unlike ``setParseAction``,
-        functions passed to ``addCondition`` need to return boolean success/fail of the condition.
-
-        Optional keyword arguments:
-        - message = define a custom message to be used in the raised exception
-        - fatal = if True, will raise ParseFatalException to stop parsing immediately; otherwise will raise
-          ParseException
-        - callDuringTry = boolean to indicate if this method should be called during internal tryParse calls,
-          default=False
-
-        Example::
-
-            integer = Word(nums).setParseAction(lambda toks: int(toks0))
-            year_int = integer.copy()
-            year_int.addCondition(lambda toks: toks0 >= 2000, message="Only support years 2000 and later")
-            date_str = year_int + '/' + integer + '/' + integer
-
-            result = date_str.parseString("1999/12/31")  # -> Exception: Only support years 2000 and later (at char 0),
-                                                                         (line:1, col:1)
-        """
-        for fn in fns:
-            self.parseAction.append(
-                conditionAsParseAction(
-                    fn, message=kwargs.get("message"), fatal=kwargs.get("fatal", False)
-                )
-            )
-
-        self.callDuringTry = self.callDuringTry or kwargs.get("callDuringTry", False)
-        return self
-
-    def setFailAction(self, fn):
-        """Define action to perform if parsing fails at this expression.
-           Fail acton fn is a callable function that takes the arguments
-           ``fn(s, loc, expr, err)`` where:
-           - s = string being parsed
-           - loc = location where expression match was attempted and failed
-           - expr = the parse expression that failed
-           - err = the exception thrown
-           The function returns no value.  It may throw :class:`ParseFatalException`
-           if it is desired to stop parsing immediately."""
-        self.failAction = fn
-        return self
-
-    def _skipIgnorables(self, instring, loc):
-        exprsFound = True
-        while exprsFound:
-            exprsFound = False
-            for e in self.ignoreExprs:
-                try:
-                    while 1:
-                        loc, dummy = e._parse(instring, loc)
-                        exprsFound = True
-                except ParseException:
-                    pass
-        return loc
-
-    def preParse(self, instring, loc):
-        if self.ignoreExprs:
-            loc = self._skipIgnorables(instring, loc)
-
-        if self.skipWhitespace:
-            wt = self.whiteChars
-            instrlen = len(instring)
-            while loc < instrlen and instringloc in wt:
-                loc += 1
-
-        return loc
-
-    def parseImpl(self, instring, loc, doActions=True):
-        return loc, 
-
-    def postParse(self, instring, loc, tokenlist):
-        return tokenlist
-
-    # ~ @profile
-    def _parseNoCache(self, instring, loc, doActions=True, callPreParse=True):
-        TRY, MATCH, FAIL = 0, 1, 2
-        debugging = self.debug  # and doActions)
-
-        if debugging or self.failAction:
-            # ~ print("Match", self, "at loc", loc, "(%d, %d)" % (lineno(loc, instring), col(loc, instring)))
-            if self.debugActionsTRY:
-                self.debugActionsTRY(instring, loc, self)
-            try:
-                if callPreParse and self.callPreparse:
-                    preloc = self.preParse(instring, loc)
-                else:
-                    preloc = loc
-                tokensStart = preloc
-                if self.mayIndexError or preloc >= len(instring):
-                    try:
-                        loc, tokens = self.parseImpl(instring, preloc, doActions)
-                    except IndexError:
-                        raise ParseException(instring, len(instring), self.errmsg, self)
-                else:
-                    loc, tokens = self.parseImpl(instring, preloc, doActions)
-            except Exception as err:
-                # ~ print("Exception raised:", err)
-                if self.debugActionsFAIL:
-                    self.debugActionsFAIL(instring, tokensStart, self, err)
-                if self.failAction:
-                    self.failAction(instring, tokensStart, self, err)
-                raise
-        else:
-            if callPreParse and self.callPreparse:
-                preloc = self.preParse(instring, loc)
-            else:
-                preloc = loc
-            tokensStart = preloc
-            if self.mayIndexError or preloc >= len(instring):
-                try:
-                    loc, tokens = self.parseImpl(instring, preloc, doActions)
-                except IndexError:
-                    raise ParseException(instring, len(instring), self.errmsg, self)
-            else:
-                loc, tokens = self.parseImpl(instring, preloc, doActions)
-
-        tokens = self.postParse(instring, loc, tokens)
-
-        retTokens = ParseResults(
-            tokens, self.resultsName, asList=self.saveAsList, modal=self.modalResults
-        )
-        if self.parseAction and (doActions or self.callDuringTry):
-            if debugging:
-                try:
-                    for fn in self.parseAction:
-                        try:
-                            tokens = fn(instring, tokensStart, retTokens)
-                        except IndexError as parse_action_exc:
-                            exc = ParseException("exception raised in parse action")
-                            exc.__cause__ = parse_action_exc
-                            raise exc
-
-                        if tokens is not None and tokens is not retTokens:
-                            retTokens = ParseResults(
-                                tokens,
-                                self.resultsName,
-                                asList=self.saveAsList
-                                and isinstance(tokens, (ParseResults, list)),
-                                modal=self.modalResults,
-                            )
-                except Exception as err:
-                    # ~ print "Exception raised in user parse action:", err
-                    if self.debugActionsFAIL:
-                        self.debugActionsFAIL(instring, tokensStart, self, err)
-                    raise
-            else:
-                for fn in self.parseAction:
-                    try:
-                        tokens = fn(instring, tokensStart, retTokens)
-                    except IndexError as parse_action_exc:
-                        exc = ParseException("exception raised in parse action")
-                        exc.__cause__ = parse_action_exc
-                        raise exc
-
-                    if tokens is not None and tokens is not retTokens:
-                        retTokens = ParseResults(
-                            tokens,
-                            self.resultsName,
-                            asList=self.saveAsList
-                            and isinstance(tokens, (ParseResults, list)),
-                            modal=self.modalResults,
-                        )
-        if debugging:
-            # ~ print("Matched", self, "->", retTokens.asList())
-            if self.debugActionsMATCH:
-                self.debugActionsMATCH(instring, tokensStart, loc, self, retTokens)
-
-        return loc, retTokens
-
-    def tryParse(self, instring, loc, raise_fatal=False):
-        try:
-            return self._parse(instring, loc, doActions=False)0
-        except ParseFatalException:
-            if raise_fatal:
-                raise
-            raise ParseException(instring, loc, self.errmsg, self)
-
-    def canParseNext(self, instring, loc):
-        try:
-            self.tryParse(instring, loc)
-        except (ParseException, IndexError):
-            return False
-        else:
-            return True
-
-    class _UnboundedCache(object):
-        def __init__(self):
-            cache = {}
-            self.not_in_cache = not_in_cache = object()
-
-            def get(self, key):
-                return cache.get(key, not_in_cache)
-
-            def set(self, key, value):
-                cachekey = value
-
-            def clear(self):
-                cache.clear()
-
-            def cache_len(self):
-                return len(cache)
-
-            self.get = types.MethodType(get, self)
-            self.set = types.MethodType(set, self)
-            self.clear = types.MethodType(clear, self)
-            self.__len__ = types.MethodType(cache_len, self)
-
-    class _FifoCache(object):
-        def __init__(self, size):
-            self.not_in_cache = not_in_cache = object()
-            cache = collections.OrderedDict()
-
-            def get(self, key):
-                return cache.get(key, not_in_cache)
-
-            def set(self, key, value):
-                cachekey = value
-                while len(cache) > size:
-                    try:
-                        cache.popitem(False)
-                    except KeyError:
-                        pass
-
-            def clear(self):
-                cache.clear()
-
-            def cache_len(self):
-                return len(cache)
-
-            self.get = types.MethodType(get, self)
-            self.set = types.MethodType(set, self)
-            self.clear = types.MethodType(clear, self)
-            self.__len__ = types.MethodType(cache_len, self)
-
-    # argument cache for optimizing repeated calls when backtracking through recursive expressions
-    packrat_cache = (
-        {}
-    )  # this is set later by enabledPackrat(); this is here so that resetCache() doesn't fail
-    packrat_cache_lock = RLock()
-    packrat_cache_stats = 0, 0
-
-    # this method gets repeatedly called during backtracking with the same arguments -
-    # we can cache these arguments and save ourselves the trouble of re-parsing the contained expression
-    def _parseCache(self, instring, loc, doActions=True, callPreParse=True):
-        HIT, MISS = 0, 1
-        lookup = (self, instring, loc, callPreParse, doActions)
-        with ParserElement.packrat_cache_lock:
-            cache = ParserElement.packrat_cache
-            value = cache.get(lookup)
-            if value is cache.not_in_cache:
-                ParserElement.packrat_cache_statsMISS += 1
-                try:
-                    value = self._parseNoCache(instring, loc, doActions, callPreParse)
-                except ParseBaseException as pe:
-                    # cache a copy of the exception, without the traceback
-                    cache.set(lookup, pe.__class__(*pe.args))
-                    raise
-                else:
-                    cache.set(lookup, (value0, value1.copy()))
-                    return value
-            else:
-                ParserElement.packrat_cache_statsHIT += 1
-                if isinstance(value, Exception):
-                    raise value
-                return value0, value1.copy()
-
-    _parse = _parseNoCache
-
-    @staticmethod
-    def resetCache():
-        ParserElement.packrat_cache.clear()
-        ParserElement.packrat_cache_stats: = 0 * len(
-            ParserElement.packrat_cache_stats
-        )
-
-    _packratEnabled = False
-
-    @staticmethod
-    def enablePackrat(cache_size_limit=128):
-        """Enables "packrat" parsing, which adds memoizing to the parsing logic.
-           Repeated parse attempts at the same string location (which happens
-           often in many complex grammars) can immediately return a cached value,
-           instead of re-executing parsing/validating code.  Memoizing is done of
-           both valid results and parsing exceptions.
-
-           Parameters:
-
-           - cache_size_limit - (default= ``128``) - if an integer value is provided
-             will limit the size of the packrat cache; if None is passed, then
-             the cache size will be unbounded; if 0 is passed, the cache will
-             be effectively disabled.
-
-           This speedup may break existing programs that use parse actions that
-           have side-effects.  For this reason, packrat parsing is disabled when
-           you first import pyparsing.  To activate the packrat feature, your
-           program must call the class method :class:`ParserElement.enablePackrat`.
-           For best results, call ``enablePackrat()`` immediately after
-           importing pyparsing.
-
-           Example::
-
-               import pyparsing
-               pyparsing.ParserElement.enablePackrat()
-        """
-        if not ParserElement._packratEnabled:
-            ParserElement._packratEnabled = True
-            if cache_size_limit is None:
-                ParserElement.packrat_cache = ParserElement._UnboundedCache()
-            else:
-                ParserElement.packrat_cache = ParserElement._FifoCache(cache_size_limit)
-            ParserElement._parse = ParserElement._parseCache
-
-    def parseString(self, instring, parseAll=False):
-        """
-        Parse a string with respect to the parser definition. This function is intended as the primary interface to the
-        client code.
-
-        :param instring: The input string to be parsed.
-        :param parseAll: If set, the entire input string must match the grammar.
-        :raises ParseException: Raised if ``parseAll`` is set and the input string does not match the whole grammar.
-        :returns: the parsed data as a :class:`ParseResults` object, which may be accessed as a `list`, a `dict`, or
-          an object with attributes if the given parser includes results names.
-
-        If the input string is required to match the entire grammar, ``parseAll`` flag must be set to True. This
-        is also equivalent to ending the grammar with ``StringEnd()``.
-
-        To report proper column numbers, ``parseString`` operates on a copy of the input string where all tabs are
-        converted to spaces (8 spaces per tab, as per the default in ``string.expandtabs``). If the input string
-        contains tabs and the grammar uses parse actions that use the ``loc`` argument to index into the string
-        being parsed, one can ensure a consistent view of the input string by doing one of the following:
-
-        - calling ``parseWithTabs`` on your grammar before calling ``parseString`` (see :class:`parseWithTabs`),
-        - define your parse action using the full ``(s,loc,toks)`` signature, and reference the input string using the
-          parse action's ``s`` argument, or
-        - explicitly expand the tabs in your input string before calling ``parseString``.
-
-        Examples:
-
-        By default, partial matches are OK.
-
-        >>> res = Word('a').parseString('aaaaabaaa')
-        >>> print(res)
-        'aaaaa'
-
-        The parsing behavior varies by the inheriting class of this abstract class. Please refer to the children
-        directly to see more examples.
-
-        It raises an exception if parseAll flag is set and instring does not match the whole grammar.
-
-        >>> res = Word('a').parseString('aaaaabaaa', parseAll=True)
-        Traceback (most recent call last):
-        ...
-        pyparsing.ParseException: Expected end of text, found 'b'  (at char 5), (line:1, col:6)
-        """
-
-        ParserElement.resetCache()
-        if not self.streamlined:
-            self.streamline()
-            # ~ self.saveAsList = True
-        for e in self.ignoreExprs:
-            e.streamline()
-        if not self.keepTabs:
-            instring = instring.expandtabs()
-        try:
-            loc, tokens = self._parse(instring, 0)
-            if parseAll:
-                loc = self.preParse(instring, loc)
-                se = Empty() + StringEnd()
-                se._parse(instring, loc)
-        except ParseBaseException as exc:
-            if ParserElement.verbose_stacktrace:
-                raise
-            else:
-                # catch and re-raise exception from here, clears out pyparsing internal stack trace
-                raise exc
-        else:
-            return tokens
-
-    def scanString(self, instring, maxMatches=_MAX_INT, overlap=False):
-        """
-        Scan the input string for expression matches.  Each match will return the
-        matching tokens, start location, and end location.  May be called with optional
-        ``maxMatches`` argument, to clip scanning after 'n' matches are found.  If
-        ``overlap`` is specified, then overlapping matches will be reported.
-
-        Note that the start and end locations are reported relative to the string
-        being parsed.  See :class:`parseString` for more information on parsing
-        strings with embedded tabs.
-
-        Example::
-
-            source = "sldjf123lsdjjkf345sldkjf879lkjsfd987"
-            print(source)
-            for tokens, start, end in Word(alphas).scanString(source):
-                print(' '*start + '^'*(end-start))
-                print(' '*start + tokens0)
-
-        prints::
-
-            sldjf123lsdjjkf345sldkjf879lkjsfd987
-            ^^^^^
-            sldjf
-                    ^^^^^^^
-                    lsdjjkf
-                              ^^^^^^
-                              sldkjf
-                                       ^^^^^^
-                                       lkjsfd
-        """
-        if not self.streamlined:
-            self.streamline()
-        for e in self.ignoreExprs:
-            e.streamline()
-
-        if not self.keepTabs:
-            instring = str(instring).expandtabs()
-        instrlen = len(instring)
-        loc = 0
-        preparseFn = self.preParse
-        parseFn = self._parse
-        ParserElement.resetCache()
-        matches = 0
-        try:
-            while loc <= instrlen and matches < maxMatches:
-                try:
-                    preloc = preparseFn(instring, loc)
-                    nextLoc, tokens = parseFn(instring, preloc, callPreParse=False)
-                except ParseException:
-                    loc = preloc + 1
-                else:
-                    if nextLoc > loc:
-                        matches += 1
-                        yield tokens, preloc, nextLoc
-                        if overlap:
-                            nextloc = preparseFn(instring, loc)
-                            if nextloc > loc:
-                                loc = nextLoc
-                            else:
-                                loc += 1
-                        else:
-                            loc = nextLoc
-                    else:
-                        loc = preloc + 1
-        except ParseBaseException as exc:
-            if ParserElement.verbose_stacktrace:
-                raise
-            else:
-                # catch and re-raise exception from here, clears out pyparsing internal stack trace
-                raise exc
-
-    def transformString(self, instring):
-        """
-        Extension to :class:`scanString`, to modify matching text with modified tokens that may
-        be returned from a parse action.  To use ``transformString``, define a grammar and
-        attach a parse action to it that modifies the returned token list.
-        Invoking ``transformString()`` on a target string will then scan for matches,
-        and replace the matched text patterns according to the logic in the parse
-        action.  ``transformString()`` returns the resulting transformed string.
-
-        Example::
-
-            wd = Word(alphas)
-            wd.setParseAction(lambda toks: toks0.title())
-
-            print(wd.transformString("now is the winter of our discontent made glorious summer by this sun of york."))
-
-        prints::
-
-            Now Is The Winter Of Our Discontent Made Glorious Summer By This Sun Of York.
-        """
-        out = 
-        lastE = 0
-        # force preservation of <TAB>s, to minimize unwanted transformation of string, and to
-        # keep string locs straight between transformString and scanString
-        self.keepTabs = True
-        try:
-            for t, s, e in self.scanString(instring):
-                out.append(instringlastE:s)
-                if t:
-                    if isinstance(t, ParseResults):
-                        out += t.asList()
-                    elif isinstance(t, list):
-                        out += t
-                    else:
-                        out.append(t)
-                lastE = e
-            out.append(instringlastE:)
-            out = o for o in out if o
-            return "".join(map(str, _flatten(out)))
-        except ParseBaseException as exc:
-            if ParserElement.verbose_stacktrace:
-                raise
-            else:
-                # catch and re-raise exception from here, clears out pyparsing internal stack trace
-                raise exc
-
-    def searchString(self, instring, maxMatches=_MAX_INT):
-        """
-        Another extension to :class:`scanString`, simplifying the access to the tokens found
-        to match the given parse expression.  May be called with optional
-        ``maxMatches`` argument, to clip searching after 'n' matches are found.
-
-        Example::
-
-            # a capitalized word starts with an uppercase letter, followed by zero or more lowercase letters
-            cap_word = Word(alphas.upper(), alphas.lower())
-
-            print(cap_word.searchString("More than Iron, more than Lead, more than Gold I need Electricity"))
-
-            # the sum() builtin can be used to merge results into a single ParseResults object
-            print(sum(cap_word.searchString("More than Iron, more than Lead, more than Gold I need Electricity")))
-
-        prints::
-
-            'More', 'Iron', 'Lead', 'Gold', 'I', 'Electricity'
-            'More', 'Iron', 'Lead', 'Gold', 'I', 'Electricity'
-        """
-        try:
-            return ParseResults(
-                t for t, s, e in self.scanString(instring, maxMatches)
-            )
-        except ParseBaseException as exc:
-            if ParserElement.verbose_stacktrace:
-                raise
-            else:
-                # catch and re-raise exception from here, clears out pyparsing internal stack trace
-                raise exc
-
-    def split(self, instring, maxsplit=_MAX_INT, includeSeparators=False):
-        """
-        Generator method to split a string using the given expression as a separator.
-        May be called with optional ``maxsplit`` argument, to limit the number of splits;
-        and the optional ``includeSeparators`` argument (default= ``False``), if the separating
-        matching text should be included in the split results.
-
-        Example::
-
-            punc = oneOf(list(".,;:/-!?"))
-            print(list(punc.split("This, this?, this sentence, is badly punctuated!")))
-
-        prints::
-
-            'This', ' this', '', ' this sentence', ' is badly punctuated', ''
-        """
-        splits = 0
-        last = 0
-        for t, s, e in self.scanString(instring, maxMatches=maxsplit):
-            yield instringlast:s
-            if includeSeparators:
-                yield t0
-            last = e
-        yield instringlast:
-
-    def __add__(self, other):
-        """
-        Implementation of + operator - returns :class:`And`. Adding strings to a ParserElement
-        converts them to :class:`Literal`s by default.
-
-        Example::
-
-            greet = Word(alphas) + "," + Word(alphas) + "!"
-            hello = "Hello, World!"
-            print(hello, "->", greet.parseString(hello))
-
-        prints::
-
-            Hello, World! -> 'Hello', ',', 'World', '!'
-
-        ``...`` may be used as a parse expression as a short form of :class:`SkipTo`.
-
-            Literal('start') + ... + Literal('end')
-
-        is equivalent to:
-
-            Literal('start') + SkipTo('end')("_skipped*") + Literal('end')
-
-        Note that the skipped text is returned with '_skipped' as a results name,
-        and to support having multiple skips in the same parser, the value returned is
-        a list of all skipped text.
-        """
-        if other is Ellipsis:
-            return _PendingSkip(self)
-
-        if isinstance(other, str_type):
-            other = self._literalStringClass(other)
-        if not isinstance(other, ParserElement):
-            warnings.warn(
-                "Cannot combine element of type %s with ParserElement" % type(other),
-                SyntaxWarning,
-                stacklevel=2,
-            )
-            return None
-        return And(self, other)
-
-    def __radd__(self, other):
-        """
-        Implementation of + operator when left operand is not a :class:`ParserElement`
-        """
-        if other is Ellipsis:
-            return SkipTo(self)("_skipped*") + self
-
-        if isinstance(other, str_type):
-            other = self._literalStringClass(other)
-        if not isinstance(other, ParserElement):
-            warnings.warn(
-                "Cannot combine element of type %s with ParserElement" % type(other),
-                SyntaxWarning,
-                stacklevel=2,
-            )
-            return None
-        return other + self
-
-    def __sub__(self, other):
-        """
-        Implementation of - operator, returns :class:`And` with error stop
-        """
-        if isinstance(other, str_type):
-            other = self._literalStringClass(other)
-        if not isinstance(other, ParserElement):
-            warnings.warn(
-                "Cannot combine element of type %s with ParserElement" % type(other),
-                SyntaxWarning,
-                stacklevel=2,
-            )
-            return None
-        return self + And._ErrorStop() + other
-
-    def __rsub__(self, other):
-        """
-        Implementation of - operator when left operand is not a :class:`ParserElement`
-        """
-        if isinstance(other, str_type):
-            other = self._literalStringClass(other)
-        if not isinstance(other, ParserElement):
-            warnings.warn(
-                "Cannot combine element of type %s with ParserElement" % type(other),
-                SyntaxWarning,
-                stacklevel=2,
-            )
-            return None
-        return other - self
-
-    def __mul__(self, other):
-        """
-        Implementation of * operator, allows use of ``expr * 3`` in place of
-        ``expr + expr + expr``.  Expressions may also me multiplied by a 2-integer
-        tuple, similar to ``{min, max}`` multipliers in regular expressions.  Tuples
-        may also include ``None`` as in:
-         - ``expr*(n, None)`` or ``expr*(n, )`` is equivalent
-              to ``expr*n + ZeroOrMore(expr)``
-              (read as "at least n instances of ``expr``")
-         - ``expr*(None, n)`` is equivalent to ``expr*(0, n)``
-              (read as "0 to n instances of ``expr``")
-         - ``expr*(None, None)`` is equivalent to ``ZeroOrMore(expr)``
-         - ``expr*(1, None)`` is equivalent to ``OneOrMore(expr)``
-
-        Note that ``expr*(None, n)`` does not raise an exception if
-        more than n exprs exist in the input stream; that is,
-        ``expr*(None, n)`` does not enforce a maximum number of expr
-        occurrences.  If this behavior is desired, then write
-        ``expr*(None, n) + ~expr``
-        """
-        if other is Ellipsis:
-            other = (0, None)
-        elif isinstance(other, tuple) and other:1 == (Ellipsis,):
-            other = ((0,) + other1: + (None,)):2
-
-        if isinstance(other, int):
-            minElements, optElements = other, 0
-        elif isinstance(other, tuple):
-            other = tuple(o if o is not Ellipsis else None for o in other)
-            other = (other + (None, None)):2
-            if other0 is None:
-                other = (0, other1)
-            if isinstance(other0, int) and other1 is None:
-                if other0 == 0:
-                    return ZeroOrMore(self)
-                if other0 == 1:
-                    return OneOrMore(self)
-                else:
-                    return self * other0 + ZeroOrMore(self)
-            elif isinstance(other0, int) and isinstance(other1, int):
-                minElements, optElements = other
-                optElements -= minElements
-            else:
-                raise TypeError(
-                    "cannot multiply 'ParserElement' and ('%s', '%s') objects",
-                    type(other0),
-                    type(other1),
-                )
-        else:
-            raise TypeError(
-                "cannot multiply 'ParserElement' and '%s' objects", type(other)
-            )
-
-        if minElements < 0:
-            raise ValueError("cannot multiply ParserElement by negative value")
-        if optElements < 0:
-            raise ValueError(
-                "second tuple value must be greater or equal to first tuple value"
-            )
-        if minElements == optElements == 0:
-            raise ValueError("cannot multiply ParserElement by 0 or (0, 0)")
-
-        if optElements:
-
-            def makeOptionalList(n):
-                if n > 1:
-                    return Optional(self + makeOptionalList(n - 1))
-                else:
-                    return Optional(self)
-
-            if minElements:
-                if minElements == 1:
-                    ret = self + makeOptionalList(optElements)
-                else:
-                    ret = And(self * minElements) + makeOptionalList(optElements)
-            else:
-                ret = makeOptionalList(optElements)
-        else:
-            if minElements == 1:
-                ret = self
-            else:
-                ret = And(self * minElements)
-        return ret
-
-    def __rmul__(self, other):
-        return self.__mul__(other)
-
-    def __or__(self, other):
-        """
-        Implementation of | operator - returns :class:`MatchFirst`
-        """
-        if other is Ellipsis:
-            return _PendingSkip(self, must_skip=True)
-
-        if isinstance(other, str_type):
-            other = self._literalStringClass(other)
-        if not isinstance(other, ParserElement):
-            warnings.warn(
-                "Cannot combine element of type %s with ParserElement" % type(other),
-                SyntaxWarning,
-                stacklevel=2,
-            )
-            return None
-        return MatchFirst(self, other)
-
-    def __ror__(self, other):
-        """
-        Implementation of | operator when left operand is not a :class:`ParserElement`
-        """
-        if isinstance(other, str_type):
-            other = self._literalStringClass(other)
-        if not isinstance(other, ParserElement):
-            warnings.warn(
-                "Cannot combine element of type %s with ParserElement" % type(other),
-                SyntaxWarning,
-                stacklevel=2,
-            )
-            return None
-        return other | self
-
-    def __xor__(self, other):
-        """
-        Implementation of ^ operator - returns :class:`Or`
-        """
-        if isinstance(other, str_type):
-            other = self._literalStringClass(other)
-        if not isinstance(other, ParserElement):
-            warnings.warn(
-                "Cannot combine element of type %s with ParserElement" % type(other),
-                SyntaxWarning,
-                stacklevel=2,
-            )
-            return None
-        return Or(self, other)
-
-    def __rxor__(self, other):
-        """
-        Implementation of ^ operator when left operand is not a :class:`ParserElement`
-        """
-        if isinstance(other, str_type):
-            other = self._literalStringClass(other)
-        if not isinstance(other, ParserElement):
-            warnings.warn(
-                "Cannot combine element of type %s with ParserElement" % type(other),
-                SyntaxWarning,
-                stacklevel=2,
-            )
-            return None
-        return other ^ self
-
-    def __and__(self, other):
-        """
-        Implementation of & operator - returns :class:`Each`
-        """
-        if isinstance(other, str_type):
-            other = self._literalStringClass(other)
-        if not isinstance(other, ParserElement):
-            warnings.warn(
-                "Cannot combine element of type %s with ParserElement" % type(other),
-                SyntaxWarning,
-                stacklevel=2,
-            )
-            return None
-        return Each(self, other)
-
-    def __rand__(self, other):
-        """
-        Implementation of & operator when left operand is not a :class:`ParserElement`
-        """
-        if isinstance(other, str_type):
-            other = self._literalStringClass(other)
-        if not isinstance(other, ParserElement):
-            warnings.warn(
-                "Cannot combine element of type %s with ParserElement" % type(other),
-                SyntaxWarning,
-                stacklevel=2,
-            )
-            return None
-        return other & self
-
-    def __invert__(self):
-        """
-        Implementation of ~ operator - returns :class:`NotAny`
-        """
-        return NotAny(self)
-
-    def __iter__(self):
-        # must implement __iter__ to override legacy use of sequential access to __getitem__ to
-        # iterate over a sequence
-        raise TypeError("%r object is not iterable" % self.__class__.__name__)
-
-    def __getitem__(self, key):
-        """
-        use ```` indexing notation as a short form for expression repetition:
-         - ``exprn`` is equivalent to ``expr*n``
-         - ``exprm, n`` is equivalent to ``expr*(m, n)``
-         - ``exprn, ...`` or ``exprn,`` is equivalent
-              to ``expr*n + ZeroOrMore(expr)``
-              (read as "at least n instances of ``expr``")
-         - ``expr..., n`` is equivalent to ``expr*(0, n)``
-              (read as "0 to n instances of ``expr``")
-         - ``expr...`` and ``expr0, ...`` are equivalent to ``ZeroOrMore(expr)``
-         - ``expr1, ...`` is equivalent to ``OneOrMore(expr)``
-         ``None`` may be used in place of ``...``.
-
-        Note that ``expr..., n`` and ``exprm, n``do not raise an exception
-        if more than ``n`` ``expr``s exist in the input stream.  If this behavior is
-        desired, then write ``expr..., n + ~expr``.
-       """
-
-        # convert single arg keys to tuples
-        try:
-            if isinstance(key, str_type):
-                key = (key,)
-            iter(key)
-        except TypeError:
-            key = (key, key)
-
-        if len(key) > 2:
-            warnings.warn(
-                "only 1 or 2 index arguments supported ({}{})".format(
-                    key:5, "... {}".format(len(key)) if len(key) > 5 else ""
-                )
-            )
-
-        # clip to 2 elements
-        ret = self * tuple(key:2)
-        return ret
-
-    def __call__(self, name=None):
-        """
-        Shortcut for :class:`setResultsName`, with ``listAllMatches=False``.
-
-        If ``name`` is given with a trailing ``'*'`` character, then ``listAllMatches`` will be
-        passed as ``True``.
-
-        If ``name` is omitted, same as calling :class:`copy`.
-
-        Example::
-
-            # these are equivalent
-            userdata = Word(alphas).setResultsName("name") + Word(nums + "-").setResultsName("socsecno")
-            userdata = Word(alphas)("name") + Word(nums + "-")("socsecno")
-        """
-        if name is not None:
-            return self._setResultsName(name)
-        else:
-            return self.copy()
-
-    def suppress(self):
-        """
-        Suppresses the output of this :class:`ParserElement`; useful to keep punctuation from
-        cluttering up returned output.
-        """
-        return Suppress(self)
-
-    def leaveWhitespace(self):
-        """
-        Disables the skipping of whitespace before matching the characters in the
-        :class:`ParserElement`'s defined pattern.  This is normally only used internally by
-        the pyparsing module, but may be needed in some whitespace-sensitive grammars.
-        """
-        self.skipWhitespace = False
-        return self
-
-    def setWhitespaceChars(self, chars, copy_defaults=False):
-        """
-        Overrides the default whitespace chars
-        """
-        self.skipWhitespace = True
-        self.whiteChars = chars
-        self.copyDefaultWhiteChars = copy_defaults
-        return self
-
-    def parseWithTabs(self):
-        """
-        Overrides default behavior to expand ``<TAB>``s to spaces before parsing the input string.
-        Must be called before ``parseString`` when the input grammar contains elements that
-        match ``<TAB>`` characters.
-        """
-        self.keepTabs = True
-        return self
-
-    def ignore(self, other):
-        """
-        Define expression to be ignored (e.g., comments) while doing pattern
-        matching; may be called repeatedly, to define multiple comment or other
-        ignorable patterns.
-
-        Example::
-
-            patt = OneOrMore(Word(alphas))
-            patt.parseString('ablaj /* comment */ lskjd') # -> 'ablaj'
-
-            patt.ignore(cStyleComment)
-            patt.parseString('ablaj /* comment */ lskjd') # -> 'ablaj', 'lskjd'
-        """
-        if isinstance(other, str_type):
-            other = Suppress(other)
-
-        if isinstance(other, Suppress):
-            if other not in self.ignoreExprs:
-                self.ignoreExprs.append(other)
-        else:
-            self.ignoreExprs.append(Suppress(other.copy()))
-        return self
-
-    def setDebugActions(self, startAction, successAction, exceptionAction):
-        """
-        Enable display of debugging messages while doing pattern matching.
-        """
-        self.debugActions = (
-            startAction or _defaultStartDebugAction,
-            successAction or _defaultSuccessDebugAction,
-            exceptionAction or _defaultExceptionDebugAction,
-        )
-        self.debug = True
-        return self
-
-    def setDebug(self, flag=True):
-        """
-        Enable display of debugging messages while doing pattern matching.
-        Set ``flag`` to True to enable, False to disable.
-
-        Example::
-
-            wd = Word(alphas).setName("alphaword")
-            integer = Word(nums).setName("numword")
-            term = wd | integer
-
-            # turn on debugging for wd
-            wd.setDebug()
-
-            OneOrMore(term).parseString("abc 123 xyz 890")
-
-        prints::
-
-            Match alphaword at loc 0(1,1)
-            Matched alphaword -> 'abc'
-            Match alphaword at loc 3(1,4)
-            Exception raised:Expected alphaword (at char 4), (line:1, col:5)
-            Match alphaword at loc 7(1,8)
-            Matched alphaword -> 'xyz'
-            Match alphaword at loc 11(1,12)
-            Exception raised:Expected alphaword (at char 12), (line:1, col:13)
-            Match alphaword at loc 15(1,16)
-            Exception raised:Expected alphaword (at char 15), (line:1, col:16)
-
-        The output shown is that produced by the default debug actions - custom debug actions can be
-        specified using :class:`setDebugActions`. Prior to attempting
-        to match the ``wd`` expression, the debugging message ``"Match <exprname> at loc <n>(<line>,<col>)"``
-        is shown. Then if the parse succeeds, a ``"Matched"`` message is shown, or an ``"Exception raised"``
-        message is shown. Also note the use of :class:`setName` to assign a human-readable name to the expression,
-        which makes debugging and exception messages easier to understand - for instance, the default
-        name created for the :class:`Word` expression without calling ``setName`` is ``"W:(ABCD...)"``.
-        """
-        if flag:
-            self.setDebugActions(
-                _defaultStartDebugAction,
-                _defaultSuccessDebugAction,
-                _defaultExceptionDebugAction,
-            )
-        else:
-            self.debug = False
-        return self
-
-    def __str__(self):
-        return self.name
-
-    def __repr__(self):
-        return str(self)
-
-    def streamline(self):
-        self.streamlined = True
-        self.strRepr = None
-        return self
-
-    def checkRecursion(self, parseElementList):
-        pass
-
-    def validate(self, validateTrace=None):
-        """
-        Check defined expressions for valid structure, check for infinite recursive definitions.
-        """
-        self.checkRecursion()
-
-    def parseFile(self, file_or_filename, parseAll=False):
-        """
-        Execute the parse expression on the given file or filename.
-        If a filename is specified (instead of a file object),
-        the entire file is opened, read, and closed before parsing.
-        """
-        try:
-            file_contents = file_or_filename.read()
-        except AttributeError:
-            with open(file_or_filename, "r") as f:
-                file_contents = f.read()
-        try:
-            return self.parseString(file_contents, parseAll)
-        except ParseBaseException as exc:
-            if ParserElement.verbose_stacktrace:
-                raise
-            else:
-                # catch and re-raise exception from here, clears out pyparsing internal stack trace
-                raise exc
-
-    def __eq__(self, other):
-        if self is other:
-            return True
-        elif isinstance(other, str_type):
-            return self.matches(other)
-        elif isinstance(other, ParserElement):
-            return vars(self) == vars(other)
-        return False
-
-    def __hash__(self):
-        return id(self)
-
-    def __req__(self, other):
-        return self == other
-
-    def __rne__(self, other):
-        return not (self == other)
-
-    def matches(self, testString, parseAll=True):
-        """
-        Method for quick testing of a parser against a test string. Good for simple
-        inline microtests of sub expressions while building up larger parser.
-
-        Parameters:
-         - testString - to test against this expression for a match
-         - parseAll - (default= ``True``) - flag to pass to :class:`parseString` when running tests
-
-        Example::
-
-            expr = Word(nums)
-            assert expr.matches("100")
-        """
-        try:
-            self.parseString(str(testString), parseAll=parseAll)
-            return True
-        except ParseBaseException:
-            return False
-
-    def runTests(
-        self,
-        tests,
-        parseAll=True,
-        comment="#",
-        fullDump=True,
-        printResults=True,
-        failureTests=False,
-        postParse=None,
-        file=None,
-    ):
-        """
-        Execute the parse expression on a series of test strings, showing each
-        test, the parsed results or where the parse failed. Quick and easy way to
-        run a parse expression against a list of sample strings.
-
-        Parameters:
-         - tests - a list of separate test strings, or a multiline string of test strings
-         - parseAll - (default= ``True``) - flag to pass to :class:`parseString` when running tests
-         - comment - (default= ``'#'``) - expression for indicating embedded comments in the test
-              string; pass None to disable comment filtering
-         - fullDump - (default= ``True``) - dump results as list followed by results names in nested outline;
-              if False, only dump nested list
-         - printResults - (default= ``True``) prints test output to stdout
-         - failureTests - (default= ``False``) indicates if these tests are expected to fail parsing
-         - postParse - (default= ``None``) optional callback for successful parse results; called as
-              `fn(test_string, parse_results)` and returns a string to be added to the test output
-         - file - (default=``None``) optional file-like object to which test output will be written;
-              if None, will default to ``sys.stdout``
-
-        Returns: a (success, results) tuple, where success indicates that all tests succeeded
-        (or failed if ``failureTests`` is True), and the results contain a list of lines of each
-        test's output
-
-        Example::
-
-            number_expr = pyparsing_common.number.copy()
-
-            result = number_expr.runTests('''
-                # unsigned integer
-                100
-                # negative integer
-                -100
-                # float with scientific notation
-                6.02e23
-                # integer with scientific notation
-                1e-12
-                ''')
-            print("Success" if result0 else "Failed!")
-
-            result = number_expr.runTests('''
-                # stray character
-                100Z
-                # missing leading digit before '.'
-                -.100
-                # too many '.'
-                3.14.159
-                ''', failureTests=True)
-            print("Success" if result0 else "Failed!")
-
-        prints::
-
-            # unsigned integer
-            100
-            100
-
-            # negative integer
-            -100
-            -100
-
-            # float with scientific notation
-            6.02e23
-            6.02e+23
-
-            # integer with scientific notation
-            1e-12
-            1e-12
-
-            Success
-
-            # stray character
-            100Z
-               ^
-            FAIL: Expected end of text (at char 3), (line:1, col:4)
-
-            # missing leading digit before '.'
-            -.100
-            ^
-            FAIL: Expected {real number with scientific notation | real number | signed integer} (at char 0), (line:1, col:1)
-
-            # too many '.'
-            3.14.159
-                ^
-            FAIL: Expected end of text (at char 4), (line:1, col:5)
-
-            Success
-
-        Each test string must be on a single line. If you want to test a string that spans multiple
-        lines, create a test like this::
-
-            expr.runTest(r"this is a test\\n of strings that spans \\n 3 lines")
-
-        (Note that this is a raw string literal, you must include the leading 'r'.)
-        """
-        if isinstance(tests, str_type):
-            tests = list(map(type(tests).strip, tests.rstrip().splitlines()))
-        if isinstance(comment, str_type):
-            comment = Literal(comment)
-        if file is None:
-            file = sys.stdout
-        print_ = file.write
-
-        allResults = 
-        comments = 
-        success = True
-        NL = Literal(r"\n").addParseAction(replaceWith("\n")).ignore(quotedString)
-        BOM = "\ufeff"
-        for t in tests:
-            if comment is not None and comment.matches(t, False) or comments and not t:
-                comments.append(t)
-                continue
-            if not t:
-                continue
-            out = "\n".join(comments), t
-            comments = 
-            try:
-                # convert newline marks to actual newlines, and strip leading BOM if present
-                t = NL.transformString(t.lstrip(BOM))
-                result = self.parseString(t, parseAll=parseAll)
-            except ParseBaseException as pe:
-                fatal = "(FATAL)" if isinstance(pe, ParseFatalException) else ""
-                if "\n" in t:
-                    out.append(line(pe.loc, t))
-                    out.append(" " * (col(pe.loc, t) - 1) + "^" + fatal)
-                else:
-                    out.append(" " * pe.loc + "^" + fatal)
-                out.append("FAIL: " + str(pe))
-                success = success and failureTests
-                result = pe
-            except Exception as exc:
-                out.append("FAIL-EXCEPTION: " + str(exc))
-                success = success and failureTests
-                result = exc
-            else:
-                success = success and not failureTests
-                if postParse is not None:
-                    try:
-                        pp_value = postParse(t, result)
-                        if pp_value is not None:
-                            if isinstance(pp_value, ParseResults):
-                                out.append(pp_value.dump())
-                            else:
-                                out.append(str(pp_value))
-                        else:
-                            out.append(result.dump())
-                    except Exception as e:
-                        out.append(result.dump(full=fullDump))
-                        out.append(
-                            "{} failed: {}: {}".format(
-                                postParse.__name__, type(e).__name__, e
-                            )
-                        )
-                else:
-                    out.append(result.dump(full=fullDump))
-                out.append("")
-
-            if printResults:
-                print_("\n".join(out))
-
-            allResults.append((t, result))
-
-        return success, allResults
-
-
-class _PendingSkip(ParserElement):
-    # internal placeholder class to hold a place were '...' is added to a parser element,
-    # once another ParserElement is added, this placeholder will be replaced with a SkipTo
-    def __init__(self, expr, must_skip=False):
-        super().__init__()
-        self.strRepr = str(expr + Empty()).replace("Empty", "...")
-        self.name = self.strRepr
-        self.anchor = expr
-        self.must_skip = must_skip
-
-    def __add__(self, other):
-        skipper = SkipTo(other).setName("...")("_skipped*")
-        if self.must_skip:
-
-            def must_skip(t):
-                if not t._skipped or t._skipped.asList() == "":
-                    del t0
-                    t.pop("_skipped", None)
-
-            def show_skip(t):
-                if t._skipped.asList()-1: == "":
-                    skipped = t.pop("_skipped")
-                    t"_skipped" = "missing <" + repr(self.anchor) + ">"
-
-            return (
-                self.anchor + skipper().addParseAction(must_skip)
-                | skipper().addParseAction(show_skip)
-            ) + other
-
-        return self.anchor + skipper + other
-
-    def __repr__(self):
-        return self.strRepr
-
-    def parseImpl(self, *args):
-        raise Exception(
-            "use of `...` expression without following SkipTo target expression"
-        )
-
-
-class Token(ParserElement):
-    """Abstract :class:`ParserElement` subclass, for defining atomic
-    matching patterns.
-    """
-
-    def __init__(self):
-        super().__init__(savelist=False)
-
-
-class Empty(Token):
-    """An empty token, will always match.
-    """
-
-    def __init__(self):
-        super().__init__()
-        self.name = "Empty"
-        self.mayReturnEmpty = True
-        self.mayIndexError = False
-
-
-class NoMatch(Token):
-    """A token that will never match.
-    """
-
-    def __init__(self):
-        super().__init__()
-        self.name = "NoMatch"
-        self.mayReturnEmpty = True
-        self.mayIndexError = False
-        self.errmsg = "Unmatchable token"
-
-    def parseImpl(self, instring, loc, doActions=True):
-        raise ParseException(instring, loc, self.errmsg, self)
-
-
-class Literal(Token):
-    """Token to exactly match a specified string.
-
-    Example::
-
-        Literal('blah').parseString('blah')  # -> 'blah'
-        Literal('blah').parseString('blahfooblah')  # -> 'blah'
-        Literal('blah').parseString('bla')  # -> Exception: Expected "blah"
-
-    For case-insensitive matching, use :class:`CaselessLiteral`.
-
-    For keyword matching (force word break before and after the matched string),
-    use :class:`Keyword` or :class:`CaselessKeyword`.
-    """
-
-    def __init__(self, matchString):
-        super().__init__()
-        self.match = matchString
-        self.matchLen = len(matchString)
-        try:
-            self.firstMatchChar = matchString0
-        except IndexError:
-            warnings.warn(
-                "null string passed to Literal; use Empty() instead",
-                SyntaxWarning,
-                stacklevel=2,
-            )
-            self.__class__ = Empty
-        self.name = '"%s"' % str(self.match)
-        self.errmsg = "Expected " + self.name
-        self.mayReturnEmpty = False
-        self.mayIndexError = False
-
-        # Performance tuning: modify __class__ to select
-        # a parseImpl optimized for single-character check
-        if self.matchLen == 1 and type(self) is Literal:
-            self.__class__ = _SingleCharLiteral
-
-    def parseImpl(self, instring, loc, doActions=True):
-        if instringloc == self.firstMatchChar and instring.startswith(
-            self.match, loc
-        ):
-            return loc + self.matchLen, self.match
-        raise ParseException(instring, loc, self.errmsg, self)
-
-
-class _SingleCharLiteral(Literal):
-    def parseImpl(self, instring, loc, doActions=True):
-        if instringloc == self.firstMatchChar:
-            return loc + 1, self.match
-        raise ParseException(instring, loc, self.errmsg, self)
-
-
-_L = Literal
-ParserElement._literalStringClass = Literal
-
-
-class Keyword(Token):
-    """Token to exactly match a specified string as a keyword, that is,
-    it must be immediately followed by a non-keyword character.  Compare
-    with :class:`Literal`:
-
-     - ``Literal("if")`` will match the leading ``'if'`` in
-       ``'ifAndOnlyIf'``.
-     - ``Keyword("if")`` will not; it will only match the leading
-       ``'if'`` in ``'if x=1'``, or ``'if(y==2)'``
-
-    Accepts two optional constructor arguments in addition to the
-    keyword string:
-
-     - ``identChars`` is a string of characters that would be valid
-       identifier characters, defaulting to all alphanumerics + "_" and
-       "$"
-     - ``caseless`` allows case-insensitive matching, default is ``False``.
-
-    Example::
-
-        Keyword("start").parseString("start")  # -> 'start'
-        Keyword("start").parseString("starting")  # -> Exception
-
-    For case-insensitive matching, use :class:`CaselessKeyword`.
-    """
-
-    DEFAULT_KEYWORD_CHARS = alphanums + "_$"
-
-    def __init__(self, matchString, identChars=None, caseless=False):
-        super().__init__()
-        if identChars is None:
-            identChars = Keyword.DEFAULT_KEYWORD_CHARS
-        self.match = matchString
-        self.matchLen = len(matchString)
-        try:
-            self.firstMatchChar = matchString0
-        except IndexError:
-            warnings.warn(
-                "null string passed to Keyword; use Empty() instead",
-                SyntaxWarning,
-                stacklevel=2,
-            )
-        self.name = '"%s"' % self.match
-        self.errmsg = "Expected " + self.name
-        self.mayReturnEmpty = False
-        self.mayIndexError = False
-        self.caseless = caseless
-        if caseless:
-            self.caselessmatch = matchString.upper()
-            identChars = identChars.upper()
-        self.identChars = set(identChars)
-
-    def parseImpl(self, instring, loc, doActions=True):
-        if self.caseless:
-            if (
-                (instringloc : loc + self.matchLen.upper() == self.caselessmatch)
-                and (
-                    loc >= len(instring) - self.matchLen
-                    or instringloc + self.matchLen.upper() not in self.identChars
-                )
-                and (loc == 0 or instringloc - 1.upper() not in self.identChars)
-            ):
-                return loc + self.matchLen, self.match
-
-        else:
-            if instringloc == self.firstMatchChar:
-                if (
-                    (self.matchLen == 1 or instring.startswith(self.match, loc))
-                    and (
-                        loc >= len(instring) - self.matchLen
-                        or instringloc + self.matchLen not in self.identChars
-                    )
-                    and (loc == 0 or instringloc - 1 not in self.identChars)
-                ):
-                    return loc + self.matchLen, self.match
-
-        raise ParseException(instring, loc, self.errmsg, self)
-
-    def copy(self):
-        c = super().copy()
-        c.identChars = Keyword.DEFAULT_KEYWORD_CHARS
-        return c
-
-    @staticmethod
-    def setDefaultKeywordChars(chars):
-        """Overrides the default Keyword chars
-        """
-        Keyword.DEFAULT_KEYWORD_CHARS = chars
-
-
-class CaselessLiteral(Literal):
-    """Token to match a specified string, ignoring case of letters.
-    Note: the matched results will always be in the case of the given
-    match string, NOT the case of the input text.
-
-    Example::
-
-        OneOrMore(CaselessLiteral("CMD")).parseString("cmd CMD Cmd10") # -> 'CMD', 'CMD', 'CMD'
-
-    (Contrast with example for :class:`CaselessKeyword`.)
-    """
-
-    def __init__(self, matchString):
-        super().__init__(matchString.upper())
-        # Preserve the defining literal.
-        self.returnString = matchString
-        self.name = "'%s'" % self.returnString
-        self.errmsg = "Expected " + self.name
-
-    def parseImpl(self, instring, loc, doActions=True):
-        if instringloc : loc + self.matchLen.upper() == self.match:
-            return loc + self.matchLen, self.returnString
-        raise ParseException(instring, loc, self.errmsg, self)
-
-
-class CaselessKeyword(Keyword):
-    """
-    Caseless version of :class:`Keyword`.
-
-    Example::
-
-        OneOrMore(CaselessKeyword("CMD")).parseString("cmd CMD Cmd10") # -> 'CMD', 'CMD'
-
-    (Contrast with example for :class:`CaselessLiteral`.)
-    """
-
-    def __init__(self, matchString, identChars=None):
-        super().__init__(matchString, identChars, caseless=True)
-
-
-class CloseMatch(Token):
-    """A variation on :class:`Literal` which matches "close" matches,
-    that is, strings with at most 'n' mismatching characters.
-    :class:`CloseMatch` takes parameters:
-
-     - ``match_string`` - string to be matched
-     - ``maxMismatches`` - (``default=1``) maximum number of
-       mismatches allowed to count as a match
-
-    The results from a successful parse will contain the matched text
-    from the input string and the following named results:
-
-     - ``mismatches`` - a list of the positions within the
-       match_string where mismatches were found
-     - ``original`` - the original match_string used to compare
-       against the input string
-
-    If ``mismatches`` is an empty list, then the match was an exact
-    match.
-
-    Example::
-
-        patt = CloseMatch("ATCATCGAATGGA")
-        patt.parseString("ATCATCGAAXGGA") # -> ('ATCATCGAAXGGA', {'mismatches': 9, 'original': 'ATCATCGAATGGA'})
-        patt.parseString("ATCAXCGAAXGGA") # -> Exception: Expected 'ATCATCGAATGGA' (with up to 1 mismatches) (at char 0), (line:1, col:1)
-
-        # exact match
-        patt.parseString("ATCATCGAATGGA") # -> ('ATCATCGAATGGA', {'mismatches': , 'original': 'ATCATCGAATGGA'})
-
-        # close match allowing up to 2 mismatches
-        patt = CloseMatch("ATCATCGAATGGA", maxMismatches=2)
-        patt.parseString("ATCAXCGAAXGGA") # -> ('ATCAXCGAAXGGA', {'mismatches': 4, 9, 'original': 'ATCATCGAATGGA'})
-    """
-
-    def __init__(self, match_string, maxMismatches=1):
-        super().__init__()
-        self.name = match_string
-        self.match_string = match_string
-        self.maxMismatches = maxMismatches
-        self.errmsg = "Expected %r (with up to %d mismatches)" % (
-            self.match_string,
-            self.maxMismatches,
-        )
-        self.mayIndexError = False
-        self.mayReturnEmpty = False
-
-    def parseImpl(self, instring, loc, doActions=True):
-        start = loc
-        instrlen = len(instring)
-        maxloc = start + len(self.match_string)
-
-        if maxloc <= instrlen:
-            match_string = self.match_string
-            match_stringloc = 0
-            mismatches = 
-            maxMismatches = self.maxMismatches
-
-            for match_stringloc, s_m in enumerate(
-                zip(instringloc:maxloc, match_string)
-            ):
-                src, mat = s_m
-                if src != mat:
-                    mismatches.append(match_stringloc)
-                    if len(mismatches) > maxMismatches:
-                        break
-            else:
-                loc = start + match_stringloc + 1
-                results = ParseResults(instringstart:loc)
-                results"original" = match_string
-                results"mismatches" = mismatches
-                return loc, results
-
-        raise ParseException(instring, loc, self.errmsg, self)
-
-
-class Word(Token):
-    """Token for matching words composed of allowed character sets.
-    Defined with string containing all allowed initial characters, an
-    optional string containing allowed body characters (if omitted,
-    defaults to the initial character set), and an optional minimum,
-    maximum, and/or exact length.  The default value for ``min`` is
-    1 (a minimum value < 1 is not valid); the default values for
-    ``max`` and ``exact`` are 0, meaning no maximum or exact
-    length restriction. An optional ``excludeChars`` parameter can
-    list characters that might be found in the input ``bodyChars``
-    string; useful to define a word of all printables except for one or
-    two characters, for instance.
-
-    :class:`srange` is useful for defining custom character set strings
-    for defining ``Word`` expressions, using range notation from
-    regular expression character sets.
-
-    A common mistake is to use :class:`Word` to match a specific literal
-    string, as in ``Word("Address")``. Remember that :class:`Word`
-    uses the string argument to define *sets* of matchable characters.
-    This expression would match "Add", "AAA", "dAred", or any other word
-    made up of the characters 'A', 'd', 'r', 'e', and 's'. To match an
-    exact literal string, use :class:`Literal` or :class:`Keyword`.
-
-    pyparsing includes helper strings for building Words:
-
-     - :class:`alphas`
-     - :class:`nums`
-     - :class:`alphanums`
-     - :class:`hexnums`
-     - :class:`alphas8bit` (alphabetic characters in ASCII range 128-255
-       - accented, tilded, umlauted, etc.)
-     - :class:`punc8bit` (non-alphabetic characters in ASCII range
-       128-255 - currency, symbols, superscripts, diacriticals, etc.)
-     - :class:`printables` (any non-whitespace character)
-
-    Example::
-
-        # a word composed of digits
-        integer = Word(nums) # equivalent to Word("0123456789") or Word(srange("0-9"))
-
-        # a word with a leading capital, and zero or more lowercase
-        capital_word = Word(alphas.upper(), alphas.lower())
-
-        # hostnames are alphanumeric, with leading alpha, and '-'
-        hostname = Word(alphas, alphanums + '-')
-
-        # roman numeral (not a strict parser, accepts invalid mix of characters)
-        roman = Word("IVXLCDM")
-
-        # any string of non-whitespace characters, except for ','
-        csv_value = Word(printables, excludeChars=",")
-    """
-
-    def __init__(
-        self,
-        initChars,
-        bodyChars=None,
-        min=1,
-        max=0,
-        exact=0,
-        asKeyword=False,
-        excludeChars=None,
-    ):
-        super().__init__()
-        if excludeChars:
-            excludeChars = set(excludeChars)
-            initChars = "".join(c for c in initChars if c not in excludeChars)
-            if bodyChars:
-                bodyChars = "".join(c for c in bodyChars if c not in excludeChars)
-        self.initCharsOrig = initChars
-        self.initChars = set(initChars)
-        if bodyChars:
-            self.bodyCharsOrig = bodyChars
-            self.bodyChars = set(bodyChars)
-        else:
-            self.bodyCharsOrig = initChars
-            self.bodyChars = set(initChars)
-
-        self.maxSpecified = max > 0
-
-        if min < 1:
-            raise ValueError(
-                "cannot specify a minimum length < 1; use Optional(Word()) if zero-length word is permitted"
-            )
-
-        self.minLen = min
-
-        if max > 0:
-            self.maxLen = max
-        else:
-            self.maxLen = _MAX_INT
-
-        if exact > 0:
-            self.maxLen = exact
-            self.minLen = exact
-
-        self.name = str(self)
-        self.errmsg = "Expected " + self.name
-        self.mayIndexError = False
-        self.asKeyword = asKeyword
-
-        if " " not in self.initCharsOrig + self.bodyCharsOrig and (
-            min == 1 and max == 0 and exact == 0
-        ):
-            if self.bodyCharsOrig == self.initCharsOrig:
-                self.reString = "%s+" % _collapseAndEscapeRegexRangeChars(
-                    self.initCharsOrig
-                )
-            elif len(self.initCharsOrig) == 1:
-                self.reString = "%s%s*" % (
-                    re.escape(self.initCharsOrig),
-                    _collapseAndEscapeRegexRangeChars(self.bodyCharsOrig),
-                )
-            else:
-                self.reString = "%s%s*" % (
-                    _collapseAndEscapeRegexRangeChars(self.initCharsOrig),
-                    _collapseAndEscapeRegexRangeChars(self.bodyCharsOrig),
-                )
-            if self.asKeyword:
-                self.reString = r"\b" + self.reString + r"\b"
-
-            try:
-                self.re = re.compile(self.reString)
-            except Exception:
-                self.re = None
-            else:
-                self.re_match = self.re.match
-                self.__class__ = _WordRegex
-
-    def parseImpl(self, instring, loc, doActions=True):
-        if instringloc not in self.initChars:
-            raise ParseException(instring, loc, self.errmsg, self)
-
-        start = loc
-        loc += 1
-        instrlen = len(instring)
-        bodychars = self.bodyChars
-        maxloc = start + self.maxLen
-        maxloc = min(maxloc, instrlen)
-        while loc < maxloc and instringloc in bodychars:
-            loc += 1
-
-        throwException = False
-        if loc - start < self.minLen:
-            throwException = True
-        elif self.maxSpecified and loc < instrlen and instringloc in bodychars:
-            throwException = True
-        elif self.asKeyword:
-            if (
-                start > 0
-                and instringstart - 1 in bodychars
-                or loc < instrlen
-                and instringloc in bodychars
-            ):
-                throwException = True
-
-        if throwException:
-            raise ParseException(instring, loc, self.errmsg, self)
-
-        return loc, instringstart:loc
-
-    def __str__(self):
-        try:
-            return super().__str__()
-        except Exception:
-            pass
-
-        if self.strRepr is None:
-
-            def charsAsStr(s):
-                if len(s) > 4:
-                    return s:4 + "..."
-                else:
-                    return s
-
-            if self.initCharsOrig != self.bodyCharsOrig:
-                self.strRepr = "W:(%s, %s)" % (
-                    charsAsStr(self.initCharsOrig),
-                    charsAsStr(self.bodyCharsOrig),
-                )
-            else:
-                self.strRepr = "W:(%s)" % charsAsStr(self.initCharsOrig)
-
-        return self.strRepr
-
-
-class _WordRegex(Word):
-    def parseImpl(self, instring, loc, doActions=True):
-        result = self.re_match(instring, loc)
-        if not result:
-            raise ParseException(instring, loc, self.errmsg, self)
-
-        loc = result.end()
-        return loc, result.group()
-
-
-class Char(_WordRegex):
-    """A short-cut class for defining ``Word(characters, exact=1)``,
-    when defining a match of any single character in a string of
-    characters.
-    """
-
-    def __init__(self, charset, asKeyword=False, excludeChars=None):
-        super().__init__(
-            charset, exact=1, asKeyword=asKeyword, excludeChars=excludeChars
-        )
-        self.reString = "%s" % _collapseAndEscapeRegexRangeChars(self.initChars)
-        if asKeyword:
-            self.reString = r"\b%s\b" % self.reString
-        self.re = re.compile(self.reString)
-        self.re_match = self.re.match
-
-
-class Regex(Token):
-    r"""Token for matching strings that match a given regular
-    expression. Defined with string specifying the regular expression in
-    a form recognized by the stdlib Python  `re module <https://docs.python.org/3/library/re.html>`_.
-    If the given regex contains named groups (defined using ``(?P<name>...)``),
-    these will be preserved as named parse results.
-
-    If instead of the Python stdlib re module you wish to use a different RE module
-    (such as the `regex` module), you can replace it by either building your
-    Regex object with a compiled RE that was compiled using regex, or by replacing
-    the imported `re` module in pyparsing with the `regex` module:
-
-
-    Example::
-
-        realnum = Regex(r"+-?\d+\.\d*")
-        date = Regex(r'(?P<year>\d{4})-(?P<month>\d\d?)-(?P<day>\d\d?)')
-        # ref: https://stackoverflow.com/questions/267399/how-do-you-match-only-valid-roman-numerals-with-a-regular-expression
-        roman = Regex(r"M{0,4}(CM|CD|D?{0,3})(XC|XL|L?X{0,3})(IX|IV|V?I{0,3})")
-
-        import regex
-        parser = pp.Regex(regex.compile(r'0-9'))
-
-        # or
-
-        import pyparsing
-        pyparsing.re = regex
-
-        # both of these will use the regex module to compile their internal re's
-        parser = pp.Regex(r'0-9')
-        parser = pp.Word(pp.nums)
-
-    """
-
-    def __init__(self, pattern, flags=0, asGroupList=False, asMatch=False):
-        """The parameters ``pattern`` and ``flags`` are passed
-        to the ``re.compile()`` function as-is. See the Python
-        `re module <https://docs.python.org/3/library/re.html>`_ module for an
-        explanation of the acceptable patterns and flags.
-        """
-        super().__init__()
-
-        if isinstance(pattern, str_type):
-            if not pattern:
-                warnings.warn(
-                    "null string passed to Regex; use Empty() instead",
-                    SyntaxWarning,
-                    stacklevel=2,
-                )
-
-            self.pattern = pattern
-            self.flags = flags
-
-            try:
-                self.re = re.compile(self.pattern, self.flags)
-                self.reString = self.pattern
-            except sre_constants.error:
-                warnings.warn(
-                    "invalid pattern (%s) passed to Regex" % pattern,
-                    SyntaxWarning,
-                    stacklevel=2,
-                )
-                raise
-
-        elif hasattr(pattern, "pattern") and hasattr(pattern, "match"):
-            self.re = pattern
-            self.pattern = self.reString = pattern.pattern
-            self.flags = flags
-
-        else:
-            raise TypeError(
-                "Regex may only be constructed with a string or a compiled RE object"
-            )
-
-        self.re_match = self.re.match
-
-        self.name = str(self)
-        self.errmsg = "Expected " + self.name
-        self.mayIndexError = False
-        self.mayReturnEmpty = True
-        self.asGroupList = asGroupList
-        self.asMatch = asMatch
-        if self.asGroupList:
-            self.parseImpl = self.parseImplAsGroupList
-        if self.asMatch:
-            self.parseImpl = self.parseImplAsMatch
-
-    def parseImpl(self, instring, loc, doActions=True):
-        result = self.re_match(instring, loc)
-        if not result:
-            raise ParseException(instring, loc, self.errmsg, self)
-
-        loc = result.end()
-        ret = ParseResults(result.group())
-        d = result.groupdict()
-        if d:
-            for k, v in d.items():
-                retk = v
-        return loc, ret
-
-    def parseImplAsGroupList(self, instring, loc, doActions=True):
-        result = self.re_match(instring, loc)
-        if not result:
-            raise ParseException(instring, loc, self.errmsg, self)
-
-        loc = result.end()
-        ret = result.groups()
-        return loc, ret
-
-    def parseImplAsMatch(self, instring, loc, doActions=True):
-        result = self.re_match(instring, loc)
-        if not result:
-            raise ParseException(instring, loc, self.errmsg, self)
-
-        loc = result.end()
-        ret = result
-        return loc, ret
-
-    def __str__(self):
-        try:
-            return super().__str__()
-        except Exception:
-            pass
-
-        if self.strRepr is None:
-            self.strRepr = "Re:(%s)" % repr(self.pattern)
-
-        return self.strRepr
-
-    def sub(self, repl):
-        r"""
-        Return Regex with an attached parse action to transform the parsed
-        result as if called using `re.sub(expr, repl, string) <https://docs.python.org/3/library/re.html#re.sub>`_.
-
-        Example::
-
-            make_html = Regex(r"(\w+):(.*?):").sub(r"<\1>\2</\1>")
-            print(make_html.transformString("h1:main title:"))
-            # prints "<h1>main title</h1>"
-        """
-        if self.asGroupList:
-            warnings.warn(
-                "cannot use sub() with Regex(asGroupList=True)",
-                SyntaxWarning,
-                stacklevel=2,
-            )
-            raise SyntaxError()
-
-        if self.asMatch and callable(repl):
-            warnings.warn(
-                "cannot use sub() with a callable with Regex(asMatch=True)",
-                SyntaxWarning,
-                stacklevel=2,
-            )
-            raise SyntaxError()
-
-        if self.asMatch:
-
-            def pa(tokens):
-                return tokens0.expand(repl)
-
-        else:
-
-            def pa(tokens):
-                return self.re.sub(repl, tokens0)
-
-        return self.addParseAction(pa)
-
-
-class QuotedString(Token):
-    r"""
-    Token for matching strings that are delimited by quoting characters.
-
-    Defined with the following parameters:
-
-        - quoteChar - string of one or more characters defining the
-          quote delimiting string
-        - escChar - character to escape quotes, typically backslash
-          (default= ``None``)
-        - escQuote - special quote sequence to escape an embedded quote
-          string (such as SQL's ``""`` to escape an embedded ``"``)
-          (default= ``None``)
-        - multiline - boolean indicating whether quotes can span
-          multiple lines (default= ``False``)
-        - unquoteResults - boolean indicating whether the matched text
-          should be unquoted (default= ``True``)
-        - endQuoteChar - string of one or more characters defining the
-          end of the quote delimited string (default= ``None``  => same as
-          quoteChar)
-        - convertWhitespaceEscapes - convert escaped whitespace
-          (``'\t'``, ``'\n'``, etc.) to actual whitespace
-          (default= ``True``)
-
-    Example::
-
-        qs = QuotedString('"')
-        print(qs.searchString('lsjdf "This is the quote" sldjf'))
-        complex_qs = QuotedString('{{', endQuoteChar='}}')
-        print(complex_qs.searchString('lsjdf {{This is the "quote"}} sldjf'))
-        sql_qs = QuotedString('"', escQuote='""')
-        print(sql_qs.searchString('lsjdf "This is the quote with ""embedded"" quotes" sldjf'))
-
-    prints::
-
-        'This is the quote'
-        'This is the "quote"'
-        'This is the quote with "embedded" quotes'
-    """
-
-    def __init__(
-        self,
-        quoteChar,
-        escChar=None,
-        escQuote=None,
-        multiline=False,
-        unquoteResults=True,
-        endQuoteChar=None,
-        convertWhitespaceEscapes=True,
-    ):
-        super().__init__()
-
-        # remove white space from quote chars - wont work anyway
-        quoteChar = quoteChar.strip()
-        if not quoteChar:
-            warnings.warn(
-                "quoteChar cannot be the empty string", SyntaxWarning, stacklevel=2
-            )
-            raise SyntaxError()
-
-        if endQuoteChar is None:
-            endQuoteChar = quoteChar
-        else:
-            endQuoteChar = endQuoteChar.strip()
-            if not endQuoteChar:
-                warnings.warn(
-                    "endQuoteChar cannot be the empty string",
-                    SyntaxWarning,
-                    stacklevel=2,
-                )
-                raise SyntaxError()
-
-        self.quoteChar = quoteChar
-        self.quoteCharLen = len(quoteChar)
-        self.firstQuoteChar = quoteChar0
-        self.endQuoteChar = endQuoteChar
-        self.endQuoteCharLen = len(endQuoteChar)
-        self.escChar = escChar
-        self.escQuote = escQuote
-        self.unquoteResults = unquoteResults
-        self.convertWhitespaceEscapes = convertWhitespaceEscapes
-
-        if multiline:
-            self.flags = re.MULTILINE | re.DOTALL
-            self.pattern = r"%s(?:^%s%s" % (
-                re.escape(self.quoteChar),
-                _escapeRegexRangeChars(self.endQuoteChar0),
-                (escChar is not None and _escapeRegexRangeChars(escChar) or ""),
-            )
-        else:
-            self.flags = 0
-            self.pattern = r"%s(?:^%s\n\r%s" % (
-                re.escape(self.quoteChar),
-                _escapeRegexRangeChars(self.endQuoteChar0),
-                (escChar is not None and _escapeRegexRangeChars(escChar) or ""),
-            )
-        if len(self.endQuoteChar) > 1:
-            self.pattern += (
-                "|(?:"
-                + ")|(?:".join(
-                    "%s^%s"
-                    % (
-                        re.escape(self.endQuoteChar:i),
-                        _escapeRegexRangeChars(self.endQuoteChari),
-                    )
-                    for i in range(len(self.endQuoteChar) - 1, 0, -1)
-                )
-                + ")"
-            )
-
-        if escQuote:
-            self.pattern += r"|(?:%s)" % re.escape(escQuote)
-        if escChar:
-            self.pattern += r"|(?:%s.)" % re.escape(escChar)
-            self.escCharReplacePattern = re.escape(self.escChar) + "(.)"
-        self.pattern += r")*%s" % re.escape(self.endQuoteChar)
-
-        try:
-            self.re = re.compile(self.pattern, self.flags)
-            self.reString = self.pattern
-            self.re_match = self.re.match
-        except sre_constants.error:
-            warnings.warn(
-                "invalid pattern (%s) passed to Regex" % self.pattern,
-                SyntaxWarning,
-                stacklevel=2,
-            )
-            raise
-
-        self.name = str(self)
-        self.errmsg = "Expected " + self.name
-        self.mayIndexError = False
-        self.mayReturnEmpty = True
-
-    def parseImpl(self, instring, loc, doActions=True):
-        result = (
-            instringloc == self.firstQuoteChar
-            and self.re_match(instring, loc)
-            or None
-        )
-        if not result:
-            raise ParseException(instring, loc, self.errmsg, self)
-
-        loc = result.end()
-        ret = result.group()
-
-        if self.unquoteResults:
-
-            # strip off quotes
-            ret = retself.quoteCharLen : -self.endQuoteCharLen
-
-            if isinstance(ret, str_type):
-                # replace escaped whitespace
-                if "\\" in ret and self.convertWhitespaceEscapes:
-                    ws_map = {
-                        r"\t": "\t",
-                        r"\n": "\n",
-                        r"\f": "\f",
-                        r"\r": "\r",
-                    }
-                    for wslit, wschar in ws_map.items():
-                        ret = ret.replace(wslit, wschar)
-
-                # replace escaped characters
-                if self.escChar:
-                    ret = re.sub(self.escCharReplacePattern, r"\g<1>", ret)
-
-                # replace escaped quotes
-                if self.escQuote:
-                    ret = ret.replace(self.escQuote, self.endQuoteChar)
-
-        return loc, ret
-
-    def __str__(self):
-        try:
-            return super().__str__()
-        except Exception:
-            pass
-
-        if self.strRepr is None:
-            self.strRepr = "quoted string, starting with %s ending with %s" % (
-                self.quoteChar,
-                self.endQuoteChar,
-            )
-
-        return self.strRepr
-
-
-class CharsNotIn(Token):
-    """Token for matching words composed of characters *not* in a given
-    set (will include whitespace in matched characters if not listed in
-    the provided exclusion set - see example). Defined with string
-    containing all disallowed characters, and an optional minimum,
-    maximum, and/or exact length.  The default value for ``min`` is
-    1 (a minimum value < 1 is not valid); the default values for
-    ``max`` and ``exact`` are 0, meaning no maximum or exact
-    length restriction.
-
-    Example::
-
-        # define a comma-separated-value as anything that is not a ','
-        csv_value = CharsNotIn(',')
-        print(delimitedList(csv_value).parseString("dkls,lsdkjf,s12 34,@!#,213"))
-
-    prints::
-
-        'dkls', 'lsdkjf', 's12 34', '@!#', '213'
-    """
-
-    def __init__(self, notChars, min=1, max=0, exact=0):
-        super().__init__()
-        self.skipWhitespace = False
-        self.notChars = notChars
-
-        if min < 1:
-            raise ValueError(
-                "cannot specify a minimum length < 1; use "
-                "Optional(CharsNotIn()) if zero-length char group is permitted"
-            )
-
-        self.minLen = min
-
-        if max > 0:
-            self.maxLen = max
-        else:
-            self.maxLen = _MAX_INT
-
-        if exact > 0:
-            self.maxLen = exact
-            self.minLen = exact
-
-        self.name = str(self)
-        self.errmsg = "Expected " + self.name
-        self.mayReturnEmpty = self.minLen == 0
-        self.mayIndexError = False
-
-    def parseImpl(self, instring, loc, doActions=True):
-        if instringloc in self.notChars:
-            raise ParseException(instring, loc, self.errmsg, self)
-
-        start = loc
-        loc += 1
-        notchars = self.notChars
-        maxlen = min(start + self.maxLen, len(instring))
-        while loc < maxlen and instringloc not in notchars:
-            loc += 1
-
-        if loc - start < self.minLen:
-            raise ParseException(instring, loc, self.errmsg, self)
-
-        return loc, instringstart:loc
-
-    def __str__(self):
-        try:
-            return super().__str__()
-        except Exception:
-            pass
-
-        if self.strRepr is None:
-            if len(self.notChars) > 4:
-                self.strRepr = "!W:(%s...)" % self.notChars:4
-            else:
-                self.strRepr = "!W:(%s)" % self.notChars
-
-        return self.strRepr
-
-
-class White(Token):
-    """Special matching class for matching whitespace.  Normally,
-    whitespace is ignored by pyparsing grammars.  This class is included
-    when some whitespace structures are significant.  Define with
-    a string containing the whitespace characters to be matched; default
-    is ``" \\t\\r\\n"``.  Also takes optional ``min``,
-    ``max``, and ``exact`` arguments, as defined for the
-    :class:`Word` class.
-    """
-
-    whiteStrs = {
-        " ": "<SP>",
-        "\t": "<TAB>",
-        "\n": "<LF>",
-        "\r": "<CR>",
-        "\f": "<FF>",
-        "u\00A0": "<NBSP>",
-        "u\1680": "<OGHAM_SPACE_MARK>",
-        "u\180E": "<MONGOLIAN_VOWEL_SEPARATOR>",
-        "u\2000": "<EN_QUAD>",
-        "u\2001": "<EM_QUAD>",
-        "u\2002": "<EN_SPACE>",
-        "u\2003": "<EM_SPACE>",
-        "u\2004": "<THREE-PER-EM_SPACE>",
-        "u\2005": "<FOUR-PER-EM_SPACE>",
-        "u\2006": "<SIX-PER-EM_SPACE>",
-        "u\2007": "<FIGURE_SPACE>",
-        "u\2008": "<PUNCTUATION_SPACE>",
-        "u\2009": "<THIN_SPACE>",
-        "u\200A": "<HAIR_SPACE>",
-        "u\200B": "<ZERO_WIDTH_SPACE>",
-        "u\202F": "<NNBSP>",
-        "u\205F": "<MMSP>",
-        "u\3000": "<IDEOGRAPHIC_SPACE>",
-    }
-
-    def __init__(self, ws=" \t\r\n", min=1, max=0, exact=0):
-        super().__init__()
-        self.matchWhite = ws
-        self.setWhitespaceChars(
-            "".join(c for c in self.whiteChars if c not in self.matchWhite),
-            copy_defaults=True,
-        )
-        # ~ self.leaveWhitespace()
-        self.name = "".join(White.whiteStrsc for c in self.matchWhite)
-        self.mayReturnEmpty = True
-        self.errmsg = "Expected " + self.name
-
-        self.minLen = min
-
-        if max > 0:
-            self.maxLen = max
-        else:
-            self.maxLen = _MAX_INT
-
-        if exact > 0:
-            self.maxLen = exact
-            self.minLen = exact
-
-    def parseImpl(self, instring, loc, doActions=True):
-        if instringloc not in self.matchWhite:
-            raise ParseException(instring, loc, self.errmsg, self)
-        start = loc
-        loc += 1
-        maxloc = start + self.maxLen
-        maxloc = min(maxloc, len(instring))
-        while loc < maxloc and instringloc in self.matchWhite:
-            loc += 1
-
-        if loc - start < self.minLen:
-            raise ParseException(instring, loc, self.errmsg, self)
-
-        return loc, instringstart:loc
-
-
-class _PositionToken(Token):
-    def __init__(self):
-        super().__init__()
-        self.name = self.__class__.__name__
-        self.mayReturnEmpty = True
-        self.mayIndexError = False
-
-
-class GoToColumn(_PositionToken):
-    """Token to advance to a specific column of input text; useful for
-    tabular report scraping.
-    """
-
-    def __init__(self, colno):
-        super().__init__()
-        self.col = colno
-
-    def preParse(self, instring, loc):
-        if col(loc, instring) != self.col:
-            instrlen = len(instring)
-            if self.ignoreExprs:
-                loc = self._skipIgnorables(instring, loc)
-            while (
-                loc < instrlen
-                and instringloc.isspace()
-                and col(loc, instring) != self.col
-            ):
-                loc += 1
-        return loc
-
-    def parseImpl(self, instring, loc, doActions=True):
-        thiscol = col(loc, instring)
-        if thiscol > self.col:
-            raise ParseException(instring, loc, "Text not in expected column", self)
-        newloc = loc + self.col - thiscol
-        ret = instringloc:newloc
-        return newloc, ret
-
-
-class LineStart(_PositionToken):
-    r"""Matches if current position is at the beginning of a line within
-    the parse string
-
-    Example::
-
-        test = '''\
-        AAA this line
-        AAA and this line
-          AAA but not this one
-        B AAA and definitely not this one
-        '''
-
-        for t in (LineStart() + 'AAA' + restOfLine).searchString(test):
-            print(t)
-
-    prints::
-
-        'AAA', ' this line'
-        'AAA', ' and this line'
-
-    """
-
-    def __init__(self):
-        super().__init__()
-        self.errmsg = "Expected start of line"
-
-    def parseImpl(self, instring, loc, doActions=True):
-        if col(loc, instring) == 1:
-            return loc, 
-        raise ParseException(instring, loc, self.errmsg, self)
-
-
-class LineEnd(_PositionToken):
-    """Matches if current position is at the end of a line within the
-    parse string
-    """
-
-    def __init__(self):
-        super().__init__()
-        self.setWhitespaceChars(
-            ParserElement.DEFAULT_WHITE_CHARS.replace("\n", ""), copy_defaults=False
-        )
-        self.errmsg = "Expected end of line"
-
-    def parseImpl(self, instring, loc, doActions=True):
-        if loc < len(instring):
-            if instringloc == "\n":
-                return loc + 1, "\n"
-            else:
-                raise ParseException(instring, loc, self.errmsg, self)
-        elif loc == len(instring):
-            return loc + 1, 
-        else:
-            raise ParseException(instring, loc, self.errmsg, self)
-
-
-class StringStart(_PositionToken):
-    """Matches if current position is at the beginning of the parse
-    string
-    """
-
-    def __init__(self):
-        super().__init__()
-        self.errmsg = "Expected start of text"
-
-    def parseImpl(self, instring, loc, doActions=True):
-        if loc != 0:
-            # see if entire string up to here is just whitespace and ignoreables
-            if loc != self.preParse(instring, 0):
-                raise ParseException(instring, loc, self.errmsg, self)
-        return loc, 
-
-
-class StringEnd(_PositionToken):
-    """Matches if current position is at the end of the parse string
-    """
-
-    def __init__(self):
-        super().__init__()
-        self.errmsg = "Expected end of text"
-
-    def parseImpl(self, instring, loc, doActions=True):
-        if loc < len(instring):
-            raise ParseException(instring, loc, self.errmsg, self)
-        elif loc == len(instring):
-            return loc + 1, 
-        elif loc > len(instring):
-            return loc, 
-        else:
-            raise ParseException(instring, loc, self.errmsg, self)
-
-
-class WordStart(_PositionToken):
-    """Matches if the current position is at the beginning of a Word,
-    and is not preceded by any character in a given set of
-    ``wordChars`` (default= ``printables``). To emulate the
-    ``\b`` behavior of regular expressions, use
-    ``WordStart(alphanums)``. ``WordStart`` will also match at
-    the beginning of the string being parsed, or at the beginning of
-    a line.
-    """
-
-    def __init__(self, wordChars=printables):
-        super().__init__()
-        self.wordChars = set(wordChars)
-        self.errmsg = "Not at the start of a word"
-
-    def parseImpl(self, instring, loc, doActions=True):
-        if loc != 0:
-            if (
-                instringloc - 1 in self.wordChars
-                or instringloc not in self.wordChars
-            ):
-                raise ParseException(instring, loc, self.errmsg, self)
-        return loc, 
-
-
-class WordEnd(_PositionToken):
-    """Matches if the current position is at the end of a Word, and is
-    not followed by any character in a given set of ``wordChars``
-    (default= ``printables``). To emulate the ``\b`` behavior of
-    regular expressions, use ``WordEnd(alphanums)``. ``WordEnd``
-    will also match at the end of the string being parsed, or at the end
-    of a line.
-    """
-
-    def __init__(self, wordChars=printables):
-        super().__init__()
-        self.wordChars = set(wordChars)
-        self.skipWhitespace = False
-        self.errmsg = "Not at the end of a word"
-
-    def parseImpl(self, instring, loc, doActions=True):
-        instrlen = len(instring)
-        if instrlen > 0 and loc < instrlen:
-            if (
-                instringloc in self.wordChars
-                or instringloc - 1 not in self.wordChars
-            ):
-                raise ParseException(instring, loc, self.errmsg, self)
-        return loc, 
-
-
-class ParseExpression(ParserElement):
-    """Abstract subclass of ParserElement, for combining and
-    post-processing parsed tokens.
-    """
-
-    def __init__(self, exprs, savelist=False):
-        super().__init__(savelist)
-        if isinstance(exprs, _generatorType):
-            exprs = list(exprs)
-
-        if isinstance(exprs, str_type):
-            self.exprs = self._literalStringClass(exprs)
-        elif isinstance(exprs, ParserElement):
-            self.exprs = exprs
-        elif isinstance(exprs, Iterable):
-            exprs = list(exprs)
-            # if sequence of strings provided, wrap with Literal
-            if any(isinstance(expr, str_type) for expr in exprs):
-                exprs = (
-                    self._literalStringClass(e) if isinstance(e, str_type) else e
-                    for e in exprs
-                )
-            self.exprs = list(exprs)
-        else:
-            try:
-                self.exprs = list(exprs)
-            except TypeError:
-                self.exprs = exprs
-        self.callPreparse = False
-
-    def append(self, other):
-        self.exprs.append(other)
-        self.strRepr = None
-        return self
-
-    def leaveWhitespace(self):
-        """Extends ``leaveWhitespace`` defined in base class, and also invokes ``leaveWhitespace`` on
-           all contained expressions."""
-        self.skipWhitespace = False
-        self.exprs = e.copy() for e in self.exprs
-        for e in self.exprs:
-            e.leaveWhitespace()
-        return self
-
-    def ignore(self, other):
-        if isinstance(other, Suppress):
-            if other not in self.ignoreExprs:
-                super().ignore(other)
-                for e in self.exprs:
-                    e.ignore(self.ignoreExprs-1)
-        else:
-            super().ignore(other)
-            for e in self.exprs:
-                e.ignore(self.ignoreExprs-1)
-        return self
-
-    def __str__(self):
-        try:
-            return super().__str__()
-        except Exception:
-            pass
-
-        if self.strRepr is None:
-            self.strRepr = "%s:(%s)" % (self.__class__.__name__, str(self.exprs))
-        return self.strRepr
-
-    def streamline(self):
-        super().streamline()
-
-        for e in self.exprs:
-            e.streamline()
-
-        # collapse nested And's of the form And(And(And(a, b), c), d) to And(a, b, c, d)
-        # but only if there are no parse actions or resultsNames on the nested And's
-        # (likewise for Or's and MatchFirst's)
-        if len(self.exprs) == 2:
-            other = self.exprs0
-            if (
-                isinstance(other, self.__class__)
-                and not other.parseAction
-                and other.resultsName is None
-                and not other.debug
-            ):
-                self.exprs = other.exprs: + self.exprs1
-                self.strRepr = None
-                self.mayReturnEmpty |= other.mayReturnEmpty
-                self.mayIndexError |= other.mayIndexError
-
-            other = self.exprs-1
-            if (
-                isinstance(other, self.__class__)
-                and not other.parseAction
-                and other.resultsName is None
-                and not other.debug
-            ):
-                self.exprs = self.exprs:-1 + other.exprs:
-                self.strRepr = None
-                self.mayReturnEmpty |= other.mayReturnEmpty
-                self.mayIndexError |= other.mayIndexError
-
-        self.errmsg = "Expected " + str(self)
-
-        return self
-
-    def validate(self, validateTrace=None):
-        tmp = (validateTrace if validateTrace is not None else ): + self
-        for e in self.exprs:
-            e.validate(tmp)
-        self.checkRecursion()
-
-    def copy(self):
-        ret = super().copy()
-        ret.exprs = e.copy() for e in self.exprs
-        return ret
-
-    def _setResultsName(self, name, listAllMatches=False):
-        if __diag__.warn_ungrouped_named_tokens_in_collection:
-            for e in self.exprs:
-                if isinstance(e, ParserElement) and e.resultsName:
-                    warnings.warn(
-                        "{}: setting results name {!r} on {} expression "
-                        "collides with {!r} on contained expression".format(
-                            "warn_ungrouped_named_tokens_in_collection",
-                            name,
-                            type(self).__name__,
-                            e.resultsName,
-                        ),
-                        stacklevel=3,
-                    )
-
-        return super()._setResultsName(name, listAllMatches)
-
-
-class And(ParseExpression):
-    """
-    Requires all given :class:`ParseExpression` s to be found in the given order.
-    Expressions may be separated by whitespace.
-    May be constructed using the ``'+'`` operator.
-    May also be constructed using the ``'-'`` operator, which will
-    suppress backtracking.
-
-    Example::
-
-        integer = Word(nums)
-        name_expr = OneOrMore(Word(alphas))
-
-        expr = And(integer("id"), name_expr("name"), integer("age"))
-        # more easily written as:
-        expr = integer("id") + name_expr("name") + integer("age")
-    """
-
-    class _ErrorStop(Empty):
-        def __init__(self, *args, **kwargs):
-            super().__init__(*args, **kwargs)
-            self.name = "-"
-            self.leaveWhitespace()
-
-    def __init__(self, exprs, savelist=True):
-        if exprs and Ellipsis in exprs:
-            tmp = 
-            for i, expr in enumerate(exprs):
-                if expr is Ellipsis:
-                    if i < len(exprs) - 1:
-                        skipto_arg = (Empty() + exprsi + 1).exprs-1
-                        tmp.append(SkipTo(skipto_arg)("_skipped*"))
-                    else:
-                        raise Exception(
-                            "cannot construct And with sequence ending in ..."
-                        )
-                else:
-                    tmp.append(expr)
-            exprs: = tmp
-        super().__init__(exprs, savelist)
-        self.mayReturnEmpty = all(e.mayReturnEmpty for e in self.exprs)
-        self.setWhitespaceChars(
-            self.exprs0.whiteChars, copy_defaults=self.exprs0.copyDefaultWhiteChars
-        )
-        self.skipWhitespace = self.exprs0.skipWhitespace
-        self.callPreparse = True
-
-    def streamline(self):
-        # collapse any _PendingSkip's
-        if self.exprs:
-            if any(
-                isinstance(e, ParseExpression)
-                and e.exprs
-                and isinstance(e.exprs-1, _PendingSkip)
-                for e in self.exprs:-1
-            ):
-                for i, e in enumerate(self.exprs:-1):
-                    if e is None:
-                        continue
-                    if (
-                        isinstance(e, ParseExpression)
-                        and e.exprs
-                        and isinstance(e.exprs-1, _PendingSkip)
-                    ):
-                        e.exprs-1 = e.exprs-1 + self.exprsi + 1
-                        self.exprsi + 1 = None
-                self.exprs = e for e in self.exprs if e is not None
-
-        super().streamline()
-        self.mayReturnEmpty = all(e.mayReturnEmpty for e in self.exprs)
-        return self
-
-    def parseImpl(self, instring, loc, doActions=True):
-        # pass False as last arg to _parse for first element, since we already
-        # pre-parsed the string as part of our And pre-parsing
-        loc, resultlist = self.exprs0._parse(
-            instring, loc, doActions, callPreParse=False
-        )
-        errorStop = False
-        for e in self.exprs1::
-            if isinstance(e, And._ErrorStop):
-                errorStop = True
-                continue
-            if errorStop:
-                try:
-                    loc, exprtokens = e._parse(instring, loc, doActions)
-                except ParseSyntaxException:
-                    raise
-                except ParseBaseException as pe:
-                    pe.__traceback__ = None
-                    raise ParseSyntaxException._from_exception(pe)
-                except IndexError:
-                    raise ParseSyntaxException(
-                        instring, len(instring), self.errmsg, self
-                    )
-            else:
-                loc, exprtokens = e._parse(instring, loc, doActions)
-            if exprtokens or exprtokens.haskeys():
-                resultlist += exprtokens
-        return loc, resultlist
-
-    def __iadd__(self, other):
-        if isinstance(other, str_type):
-            other = self._literalStringClass(other)
-        return self.append(other)  # And(self, other)
-
-    def checkRecursion(self, parseElementList):
-        subRecCheckList = parseElementList: + self
-        for e in self.exprs:
-            e.checkRecursion(subRecCheckList)
-            if not e.mayReturnEmpty:
-                break
-
-    def __str__(self):
-        if hasattr(self, "name"):
-            return self.name
-
-        if self.strRepr is None:
-            self.strRepr = "{" + " ".join(str(e) for e in self.exprs) + "}"
-
-        return self.strRepr
-
-
-class Or(ParseExpression):
-    """Requires that at least one :class:`ParseExpression` is found. If
-    two expressions match, the expression that matches the longest
-    string will be used. May be constructed using the ``'^'``
-    operator.
-
-    Example::
-
-        # construct Or using '^' operator
-
-        number = Word(nums) ^ Combine(Word(nums) + '.' + Word(nums))
-        print(number.searchString("123 3.1416 789"))
-
-    prints::
-
-        '123', '3.1416', '789'
-    """
-
-    def __init__(self, exprs, savelist=False):
-        super().__init__(exprs, savelist)
-        if self.exprs:
-            self.mayReturnEmpty = any(e.mayReturnEmpty for e in self.exprs)
-        else:
-            self.mayReturnEmpty = True
-
-    def streamline(self):
-        super().streamline()
-        self.saveAsList = any(e.saveAsList for e in self.exprs)
-        return self
-
-    def parseImpl(self, instring, loc, doActions=True):
-        maxExcLoc = -1
-        maxException = None
-        matches = 
-        fatals = 
-        for e in self.exprs:
-            try:
-                loc2 = e.tryParse(instring, loc, raise_fatal=True)
-            except ParseFatalException as pfe:
-                pfe.__traceback__ = None
-                pfe.parserElement = e
-                fatals.append(pfe)
-                maxException = None
-                maxExcLoc = -1
-            except ParseException as err:
-                if not fatals:
-                    err.__traceback__ = None
-                    if err.loc > maxExcLoc:
-                        maxException = err
-                        maxExcLoc = err.loc
-            except IndexError:
-                if len(instring) > maxExcLoc:
-                    maxException = ParseException(
-                        instring, len(instring), e.errmsg, self
-                    )
-                    maxExcLoc = len(instring)
-            else:
-                # save match among all matches, to retry longest to shortest
-                matches.append((loc2, e))
-
-        if matches:
-            # re-evaluate all matches in descending order of length of match, in case attached actions
-            # might change whether or how much they match of the input.
-            matches.sort(key=itemgetter(0), reverse=True)
-
-            if not doActions:
-                # no further conditions or parse actions to change the selection of
-                # alternative, so the first match will be the best match
-                best_expr = matches01
-                return best_expr._parse(instring, loc, doActions)
-
-            longest = -1, None
-            for loc1, expr1 in matches:
-                if loc1 <= longest0:
-                    # already have a longer match than this one will deliver, we are done
-                    return longest
-
-                try:
-                    loc2, toks = expr1._parse(instring, loc, doActions)
-                except ParseException as err:
-                    err.__traceback__ = None
-                    if err.loc > maxExcLoc:
-                        maxException = err
-                        maxExcLoc = err.loc
-                else:
-                    if loc2 >= loc1:
-                        return loc2, toks
-                    # didn't match as much as before
-                    elif loc2 > longest0:
-                        longest = loc2, toks
-
-            if longest != (-1, None):
-                return longest
-
-        if fatals:
-            if len(fatals) > 1:
-                fatals.sort(key=lambda e: -e.loc)
-                if fatals0.loc == fatals1.loc:
-                    fatals.sort(key=lambda e: (-e.loc, -len(str(e.parserElement))))
-            max_fatal = fatals0
-            raise max_fatal
-
-        if maxException is not None:
-            maxException.msg = self.errmsg
-            raise maxException
-        else:
-            raise ParseException(
-                instring, loc, "no defined alternatives to match", self
-            )
-
-    def __ixor__(self, other):
-        if isinstance(other, str_type):
-            other = self._literalStringClass(other)
-        return self.append(other)  # Or(self, other)
-
-    def __str__(self):
-        if hasattr(self, "name"):
-            return self.name
-
-        if self.strRepr is None:
-            self.strRepr = "{" + " ^ ".join(str(e) for e in self.exprs) + "}"
-
-        return self.strRepr
-
-    def checkRecursion(self, parseElementList):
-        subRecCheckList = parseElementList: + self
-        for e in self.exprs:
-            e.checkRecursion(subRecCheckList)
-
-    def _setResultsName(self, name, listAllMatches=False):
-        if __diag__.warn_multiple_tokens_in_named_alternation:
-            if any(isinstance(e, And) for e in self.exprs):
-                warnings.warn(
-                    "{}: setting results name {!r} on {} expression "
-                    "will return a list of all parsed tokens in an And alternative, "
-                    "in prior versions only the first token was returned".format(
-                        "warn_multiple_tokens_in_named_alternation",
-                        name,
-                        type(self).__name__,
-                    ),
-                    stacklevel=3,
-                )
-
-        return super()._setResultsName(name, listAllMatches)
-
-
-class MatchFirst(ParseExpression):
-    """Requires that at least one :class:`ParseExpression` is found. If
-    two expressions match, the first one listed is the one that will
-    match. May be constructed using the ``'|'`` operator.
-
-    Example::
-
-        # construct MatchFirst using '|' operator
-
-        # watch the order of expressions to match
-        number = Word(nums) | Combine(Word(nums) + '.' + Word(nums))
-        print(number.searchString("123 3.1416 789")) #  Fail! -> '123', '3', '1416', '789'
-
-        # put more selective expression first
-        number = Combine(Word(nums) + '.' + Word(nums)) | Word(nums)
-        print(number.searchString("123 3.1416 789")) #  Better -> '123', '3.1416', '789'
-    """
-
-    def __init__(self, exprs, savelist=False):
-        super().__init__(exprs, savelist)
-        if self.exprs:
-            self.mayReturnEmpty = any(e.mayReturnEmpty for e in self.exprs)
-        else:
-            self.mayReturnEmpty = True
-
-    def streamline(self):
-        super().streamline()
-        self.saveAsList = any(e.saveAsList for e in self.exprs)
-        return self
-
-    def parseImpl(self, instring, loc, doActions=True):
-        maxExcLoc = -1
-        maxException = None
-        fatals = 
-        for e in self.exprs:
-            try:
-                ret = e._parse(instring, loc, doActions)
-                return ret
-            except ParseFatalException as pfe:
-                pfe.__traceback__ = None
-                pfe.parserElement = e
-                fatals.append(pfe)
-                maxException = None
-            except ParseException as err:
-                if not fatals and err.loc > maxExcLoc:
-                    maxException = err
-                    maxExcLoc = err.loc
-            except IndexError:
-                if len(instring) > maxExcLoc:
-                    maxException = ParseException(
-                        instring, len(instring), e.errmsg, self
-                    )
-                    maxExcLoc = len(instring)
-
-        # only got here if no expression matched, raise exception for match that made it the furthest
-        if fatals:
-            if len(fatals) > 1:
-                fatals.sort(key=lambda e: -e.loc)
-                if fatals0.loc == fatals1.loc:
-                    fatals.sort(key=lambda e: (-e.loc, -len(str(e.parserElement))))
-            max_fatal = fatals0
-            raise max_fatal
-
-        if maxException is not None:
-            maxException.msg = self.errmsg
-            raise maxException
-        else:
-            raise ParseException(
-                instring, loc, "no defined alternatives to match", self
-            )
-
-    def __ior__(self, other):
-        if isinstance(other, str_type):
-            other = self._literalStringClass(other)
-        return self.append(other)  # MatchFirst(self, other)
-
-    def __str__(self):
-        if hasattr(self, "name"):
-            return self.name
-
-        if self.strRepr is None:
-            self.strRepr = "{" + " | ".join(str(e) for e in self.exprs) + "}"
-
-        return self.strRepr
-
-    def checkRecursion(self, parseElementList):
-        subRecCheckList = parseElementList: + self
-        for e in self.exprs:
-            e.checkRecursion(subRecCheckList)
-
-    def _setResultsName(self, name, listAllMatches=False):
-        if __diag__.warn_multiple_tokens_in_named_alternation:
-            if any(isinstance(e, And) for e in self.exprs):
-                warnings.warn(
-                    "{}: setting results name {!r} on {} expression "
-                    "may only return a single token for an And alternative, "
-                    "in future will return the full list of tokens".format(
-                        "warn_multiple_tokens_in_named_alternation",
-                        name,
-                        type(self).__name__,
-                    ),
-                    stacklevel=3,
-                )
-
-        return super()._setResultsName(name, listAllMatches)
-
-
-class Each(ParseExpression):
-    """Requires all given :class:`ParseExpression` s to be found, but in
-    any order. Expressions may be separated by whitespace.
-
-    May be constructed using the ``'&'`` operator.
-
-    Example::
-
-        color = oneOf("RED ORANGE YELLOW GREEN BLUE PURPLE BLACK WHITE BROWN")
-        shape_type = oneOf("SQUARE CIRCLE TRIANGLE STAR HEXAGON OCTAGON")
-        integer = Word(nums)
-        shape_attr = "shape:" + shape_type("shape")
-        posn_attr = "posn:" + Group(integer("x") + ',' + integer("y"))("posn")
-        color_attr = "color:" + color("color")
-        size_attr = "size:" + integer("size")
-
-        # use Each (using operator '&') to accept attributes in any order
-        # (shape and posn are required, color and size are optional)
-        shape_spec = shape_attr & posn_attr & Optional(color_attr) & Optional(size_attr)
-
-        shape_spec.runTests('''
-            shape: SQUARE color: BLACK posn: 100, 120
-            shape: CIRCLE size: 50 color: BLUE posn: 50,80
-            color:GREEN size:20 shape:TRIANGLE posn:20,40
-            '''
-            )
-
-    prints::
-
-        shape: SQUARE color: BLACK posn: 100, 120
-        'shape:', 'SQUARE', 'color:', 'BLACK', 'posn:', '100', ',', '120'
-        - color: BLACK
-        - posn: '100', ',', '120'
-          - x: 100
-          - y: 120
-        - shape: SQUARE
-
-
-        shape: CIRCLE size: 50 color: BLUE posn: 50,80
-        'shape:', 'CIRCLE', 'size:', '50', 'color:', 'BLUE', 'posn:', '50', ',', '80'
-        - color: BLUE
-        - posn: '50', ',', '80'
-          - x: 50
-          - y: 80
-        - shape: CIRCLE
-        - size: 50
-
-
-        color: GREEN size: 20 shape: TRIANGLE posn: 20,40
-        'color:', 'GREEN', 'size:', '20', 'shape:', 'TRIANGLE', 'posn:', '20', ',', '40'
-        - color: GREEN
-        - posn: '20', ',', '40'
-          - x: 20
-          - y: 40
-        - shape: TRIANGLE
-        - size: 20
-    """
-
-    def __init__(self, exprs, savelist=True):
-        super().__init__(exprs, savelist)
-        self.mayReturnEmpty = all(e.mayReturnEmpty for e in self.exprs)
-        self.skipWhitespace = True
-        self.initExprGroups = True
-        self.saveAsList = True
-
-    def streamline(self):
-        super().streamline()
-        self.mayReturnEmpty = all(e.mayReturnEmpty for e in self.exprs)
-        return self
-
-    def parseImpl(self, instring, loc, doActions=True):
-        if self.initExprGroups:
-            self.opt1map = dict(
-                (id(e.expr), e) for e in self.exprs if isinstance(e, Optional)
-            )
-            opt1 = e.expr for e in self.exprs if isinstance(e, Optional)
-            opt2 = 
-                e
-                for e in self.exprs
-                if e.mayReturnEmpty and not isinstance(e, Optional)
-            
-            self.optionals = opt1 + opt2
-            self.multioptionals = 
-                e.expr for e in self.exprs if isinstance(e, ZeroOrMore)
-            
-            self.multirequired = 
-                e.expr for e in self.exprs if isinstance(e, OneOrMore)
-            
-            self.required = 
-                e
-                for e in self.exprs
-                if not isinstance(e, (Optional, ZeroOrMore, OneOrMore))
-            
-            self.required += self.multirequired
-            self.initExprGroups = False
-        tmpLoc = loc
-        tmpReqd = self.required:
-        tmpOpt = self.optionals:
-        matchOrder = 
-
-        keepMatching = True
-        failed = 
-        fatals = 
-        while keepMatching:
-            tmpExprs = tmpReqd + tmpOpt + self.multioptionals + self.multirequired
-            failed.clear()
-            fatals.clear()
-            for e in tmpExprs:
-                try:
-                    tmpLoc = e.tryParse(instring, tmpLoc, raise_fatal=True)
-                except ParseFatalException as pfe:
-                    pfe.__traceback__ = None
-                    pfe.parserElement = e
-                    fatals.append(pfe)
-                    failed.append(e)
-                except ParseException:
-                    failed.append(e)
-                else:
-                    matchOrder.append(self.opt1map.get(id(e), e))
-                    if e in tmpReqd:
-                        tmpReqd.remove(e)
-                    elif e in tmpOpt:
-                        tmpOpt.remove(e)
-            if len(failed) == len(tmpExprs):
-                keepMatching = False
-
-        # look for any ParseFatalExceptions
-        if fatals:
-            if len(fatals) > 1:
-                fatals.sort(key=lambda e: -e.loc)
-                if fatals0.loc == fatals1.loc:
-                    fatals.sort(key=lambda e: (-e.loc, -len(str(e.parserElement))))
-            max_fatal = fatals0
-            raise max_fatal
-
-        if tmpReqd:
-            missing = ", ".join(str(e) for e in tmpReqd)
-            raise ParseException(
-                instring, loc, "Missing one or more required elements (%s)" % missing
-            )
-
-        # add any unmatched Optionals, in case they have default values defined
-        matchOrder += 
-            e for e in self.exprs if isinstance(e, Optional) and e.expr in tmpOpt
-        
-
-        resultlist = 
-        for e in matchOrder:
-            loc, results = e._parse(instring, loc, doActions)
-            resultlist.append(results)
-
-        finalResults = sum(resultlist, ParseResults())
-        return loc, finalResults
-
-    def __str__(self):
-        if hasattr(self, "name"):
-            return self.name
-
-        if self.strRepr is None:
-            self.strRepr = "{" + " & ".join(str(e) for e in self.exprs) + "}"
-
-        return self.strRepr
-
-    def checkRecursion(self, parseElementList):
-        subRecCheckList = parseElementList: + self
-        for e in self.exprs:
-            e.checkRecursion(subRecCheckList)
-
-
-class ParseElementEnhance(ParserElement):
-    """Abstract subclass of :class:`ParserElement`, for combining and
-    post-processing parsed tokens.
-    """
-
-    def __init__(self, expr, savelist=False):
-        super().__init__(savelist)
-        if isinstance(expr, str_type):
-            if issubclass(self._literalStringClass, Token):
-                expr = self._literalStringClass(expr)
-            elif issubclass(type(self), self._literalStringClass):
-                expr = Literal(expr)
-            else:
-                expr = self._literalStringClass(Literal(expr))
-        self.expr = expr
-        self.strRepr = None
-        if expr is not None:
-            self.mayIndexError = expr.mayIndexError
-            self.mayReturnEmpty = expr.mayReturnEmpty
-            self.setWhitespaceChars(
-                expr.whiteChars, copy_defaults=expr.copyDefaultWhiteChars
-            )
-            self.skipWhitespace = expr.skipWhitespace
-            self.saveAsList = expr.saveAsList
-            self.callPreparse = expr.callPreparse
-            self.ignoreExprs.extend(expr.ignoreExprs)
-
-    def parseImpl(self, instring, loc, doActions=True):
-        if self.expr is not None:
-            return self.expr._parse(instring, loc, doActions, callPreParse=False)
-        else:
-            raise ParseException("", loc, self.errmsg, self)
-
-    def leaveWhitespace(self):
-        self.skipWhitespace = False
-        self.expr = self.expr.copy()
-        if self.expr is not None:
-            self.expr.leaveWhitespace()
-        return self
-
-    def ignore(self, other):
-        if isinstance(other, Suppress):
-            if other not in self.ignoreExprs:
-                super().ignore(other)
-                if self.expr is not None:
-                    self.expr.ignore(self.ignoreExprs-1)
-        else:
-            super().ignore(other)
-            if self.expr is not None:
-                self.expr.ignore(self.ignoreExprs-1)
-        return self
-
-    def streamline(self):
-        super().streamline()
-        if self.expr is not None:
-            self.expr.streamline()
-        return self
-
-    def checkRecursion(self, parseElementList):
-        if self in parseElementList:
-            raise RecursiveGrammarException(parseElementList + self)
-        subRecCheckList = parseElementList: + self
-        if self.expr is not None:
-            self.expr.checkRecursion(subRecCheckList)
-
-    def validate(self, validateTrace=None):
-        if validateTrace is None:
-            validateTrace = 
-        tmp = validateTrace: + self
-        if self.expr is not None:
-            self.expr.validate(tmp)
-        self.checkRecursion()
-
-    def __str__(self):
-        try:
-            return super().__str__()
-        except Exception:
-            pass
-
-        if self.strRepr is None and self.expr is not None:
-            self.strRepr = "%s:(%s)" % (self.__class__.__name__, str(self.expr))
-        return self.strRepr
-
-
-class FollowedBy(ParseElementEnhance):
-    """Lookahead matching of the given parse expression.
-    ``FollowedBy`` does *not* advance the parsing position within
-    the input string, it only verifies that the specified parse
-    expression matches at the current position.  ``FollowedBy``
-    always returns a null token list. If any results names are defined
-    in the lookahead expression, those *will* be returned for access by
-    name.
-
-    Example::
-
-        # use FollowedBy to match a label only if it is followed by a ':'
-        data_word = Word(alphas)
-        label = data_word + FollowedBy(':')
-        attr_expr = Group(label + Suppress(':') + OneOrMore(data_word, stopOn=label).setParseAction(' '.join))
-
-        OneOrMore(attr_expr).parseString("shape: SQUARE color: BLACK posn: upper left").pprint()
-
-    prints::
-
-        'shape', 'SQUARE', 'color', 'BLACK', 'posn', 'upper left'
-    """
-
-    def __init__(self, expr):
-        super().__init__(expr)
-        self.mayReturnEmpty = True
-
-    def parseImpl(self, instring, loc, doActions=True):
-        # by using self._expr.parse and deleting the contents of the returned ParseResults list
-        # we keep any named results that were defined in the FollowedBy expression
-        _, ret = self.expr._parse(instring, loc, doActions=doActions)
-        del ret:
-
-        return loc, ret
-
-
-class PrecededBy(ParseElementEnhance):
-    """Lookbehind matching of the given parse expression.
-    ``PrecededBy`` does not advance the parsing position within the
-    input string, it only verifies that the specified parse expression
-    matches prior to the current position.  ``PrecededBy`` always
-    returns a null token list, but if a results name is defined on the
-    given expression, it is returned.
-
-    Parameters:
-
-     - expr - expression that must match prior to the current parse
-       location
-     - retreat - (default= ``None``) - (int) maximum number of characters
-       to lookbehind prior to the current parse location
-
-    If the lookbehind expression is a string, Literal, Keyword, or
-    a Word or CharsNotIn with a specified exact or maximum length, then
-    the retreat parameter is not required. Otherwise, retreat must be
-    specified to give a maximum number of characters to look back from
-    the current parse position for a lookbehind match.
-
-    Example::
-
-        # VB-style variable names with type prefixes
-        int_var = PrecededBy("#") + pyparsing_common.identifier
-        str_var = PrecededBy("$") + pyparsing_common.identifier
-
-    """
-
-    def __init__(self, expr, retreat=None):
-        super().__init__(expr)
-        self.expr = self.expr().leaveWhitespace()
-        self.mayReturnEmpty = True
-        self.mayIndexError = False
-        self.exact = False
-        if isinstance(expr, str_type):
-            retreat = len(expr)
-            self.exact = True
-        elif isinstance(expr, (Literal, Keyword)):
-            retreat = expr.matchLen
-            self.exact = True
-        elif isinstance(expr, (Word, CharsNotIn)) and expr.maxLen != _MAX_INT:
-            retreat = expr.maxLen
-            self.exact = True
-        elif isinstance(expr, _PositionToken):
-            retreat = 0
-            self.exact = True
-        self.retreat = retreat
-        self.errmsg = "not preceded by " + str(expr)
-        self.skipWhitespace = False
-        self.parseAction.append(lambda s, l, t: t.__delitem__(slice(None, None)))
-
-    def parseImpl(self, instring, loc=0, doActions=True):
-        if self.exact:
-            if loc < self.retreat:
-                raise ParseException(instring, loc, self.errmsg)
-            start = loc - self.retreat
-            _, ret = self.expr._parse(instring, start)
-        else:
-            # retreat specified a maximum lookbehind window, iterate
-            test_expr = self.expr + StringEnd()
-            instring_slice = instringmax(0, loc - self.retreat) : loc
-            last_expr = ParseException(instring, loc, self.errmsg)
-            for offset in range(1, min(loc, self.retreat + 1) + 1):
-                try:
-                    # print('trying', offset, instring_slice, repr(instring_sliceloc - offset:))
-                    _, ret = test_expr._parse(
-                        instring_slice, len(instring_slice) - offset
-                    )
-                except ParseBaseException as pbe:
-                    last_expr = pbe
-                else:
-                    break
-            else:
-                raise last_expr
-        return loc, ret
-
-
-class NotAny(ParseElementEnhance):
-    """Lookahead to disallow matching with the given parse expression.
-    ``NotAny`` does *not* advance the parsing position within the
-    input string, it only verifies that the specified parse expression
-    does *not* match at the current position.  Also, ``NotAny`` does
-    *not* skip over leading whitespace. ``NotAny`` always returns
-    a null token list.  May be constructed using the '~' operator.
-
-    Example::
-
-        AND, OR, NOT = map(CaselessKeyword, "AND OR NOT".split())
-
-        # take care not to mistake keywords for identifiers
-        ident = ~(AND | OR | NOT) + Word(alphas)
-        boolean_term = Optional(NOT) + ident
-
-        # very crude boolean expression - to support parenthesis groups and
-        # operation hierarchy, use infixNotation
-        boolean_expr = boolean_term + ZeroOrMore((AND | OR) + boolean_term)
-
-        # integers that are followed by "." are actually floats
-        integer = Word(nums) + ~Char(".")
-    """
-
-    def __init__(self, expr):
-        super().__init__(expr)
-        # ~ self.leaveWhitespace()
-        self.skipWhitespace = (
-            False  # do NOT use self.leaveWhitespace(), don't want to propagate to exprs
-        )
-        self.mayReturnEmpty = True
-        self.errmsg = "Found unwanted token, " + str(self.expr)
-
-    def parseImpl(self, instring, loc, doActions=True):
-        if self.expr.canParseNext(instring, loc):
-            raise ParseException(instring, loc, self.errmsg, self)
-        return loc, 
-
-    def __str__(self):
-        if hasattr(self, "name"):
-            return self.name
-
-        if self.strRepr is None:
-            self.strRepr = "~{" + str(self.expr) + "}"
-
-        return self.strRepr
-
-
-class _MultipleMatch(ParseElementEnhance):
-    def __init__(self, expr, stopOn=None):
-        super().__init__(expr)
-        self.saveAsList = True
-        ender = stopOn
-        if isinstance(ender, str_type):
-            ender = self._literalStringClass(ender)
-        self.stopOn(ender)
-
-    def stopOn(self, ender):
-        if isinstance(ender, str_type):
-            ender = self._literalStringClass(ender)
-        self.not_ender = ~ender if ender is not None else None
-        return self
-
-    def parseImpl(self, instring, loc, doActions=True):
-        self_expr_parse = self.expr._parse
-        self_skip_ignorables = self._skipIgnorables
-        check_ender = self.not_ender is not None
-        if check_ender:
-            try_not_ender = self.not_ender.tryParse
-
-        # must be at least one (but first see if we are the stopOn sentinel;
-        # if so, fail)
-        if check_ender:
-            try_not_ender(instring, loc)
-        loc, tokens = self_expr_parse(instring, loc, doActions, callPreParse=False)
-        try:
-            hasIgnoreExprs = not not self.ignoreExprs
-            while 1:
-                if check_ender:
-                    try_not_ender(instring, loc)
-                if hasIgnoreExprs:
-                    preloc = self_skip_ignorables(instring, loc)
-                else:
-                    preloc = loc
-                loc, tmptokens = self_expr_parse(instring, preloc, doActions)
-                if tmptokens or tmptokens.haskeys():
-                    tokens += tmptokens
-        except (ParseException, IndexError):
-            pass
-
-        return loc, tokens
-
-    def _setResultsName(self, name, listAllMatches=False):
-        if __diag__.warn_ungrouped_named_tokens_in_collection:
-            for e in self.expr + getattr(self.expr, "exprs", ):
-                if isinstance(e, ParserElement) and e.resultsName:
-                    warnings.warn(
-                        "{}: setting results name {!r} on {} expression "
-                        "collides with {!r} on contained expression".format(
-                            "warn_ungrouped_named_tokens_in_collection",
-                            name,
-                            type(self).__name__,
-                            e.resultsName,
-                        ),
-                        stacklevel=3,
-                    )
-
-        return super()._setResultsName(name, listAllMatches)
-
-
-class OneOrMore(_MultipleMatch):
-    """Repetition of one or more of the given expression.
-
-    Parameters:
-     - expr - expression that must match one or more times
-     - stopOn - (default= ``None``) - expression for a terminating sentinel
-          (only required if the sentinel would ordinarily match the repetition
-          expression)
-
-    Example::
-
-        data_word = Word(alphas)
-        label = data_word + FollowedBy(':')
-        attr_expr = Group(label + Suppress(':') + OneOrMore(data_word).setParseAction(' '.join))
-
-        text = "shape: SQUARE posn: upper left color: BLACK"
-        OneOrMore(attr_expr).parseString(text).pprint()  # Fail! read 'color' as data instead of next label -> 'shape', 'SQUARE color'
-
-        # use stopOn attribute for OneOrMore to avoid reading label string as part of the data
-        attr_expr = Group(label + Suppress(':') + OneOrMore(data_word, stopOn=label).setParseAction(' '.join))
-        OneOrMore(attr_expr).parseString(text).pprint() # Better -> 'shape', 'SQUARE', 'posn', 'upper left', 'color', 'BLACK'
-
-        # could also be written as
-        (attr_expr * (1,)).parseString(text).pprint()
-    """
-
-    def __str__(self):
-        if hasattr(self, "name"):
-            return self.name
-
-        if self.strRepr is None:
-            self.strRepr = "{" + str(self.expr) + "}..."
-
-        return self.strRepr
-
-
-class ZeroOrMore(_MultipleMatch):
-    """Optional repetition of zero or more of the given expression.
-
-    Parameters:
-     - expr - expression that must match zero or more times
-     - stopOn - (default= ``None``) - expression for a terminating sentinel
-          (only required if the sentinel would ordinarily match the repetition
-          expression)
-
-    Example: similar to :class:`OneOrMore`
-    """
-
-    def __init__(self, expr, stopOn=None):
-        super().__init__(expr, stopOn=stopOn)
-        self.mayReturnEmpty = True
-
-    def parseImpl(self, instring, loc, doActions=True):
-        try:
-            return super().parseImpl(instring, loc, doActions)
-        except (ParseException, IndexError):
-            return loc, ParseResults(, name=self.resultsName)
-
-    def __str__(self):
-        if hasattr(self, "name"):
-            return self.name
-
-        if self.strRepr is None:
-            self.strRepr = "" + str(self.expr) + "..."
-
-        return self.strRepr
-
-
-class _NullToken(object):
-    def __bool__(self):
-        return False
-
-    def __str__(self):
-        return ""
-
-
-class Optional(ParseElementEnhance):
-    """Optional matching of the given expression.
-
-    Parameters:
-     - expr - expression that must match zero or more times
-     - default (optional) - value to be returned if the optional expression is not found.
-
-    Example::
-
-        # US postal code can be a 5-digit zip, plus optional 4-digit qualifier
-        zip = Combine(Word(nums, exact=5) + Optional('-' + Word(nums, exact=4)))
-        zip.runTests('''
-            # traditional ZIP code
-            12345
-
-            # ZIP+4 form
-            12101-0001
-
-            # invalid ZIP
-            98765-
-            ''')
-
-    prints::
-
-        # traditional ZIP code
-        12345
-        '12345'
-
-        # ZIP+4 form
-        12101-0001
-        '12101-0001'
-
-        # invalid ZIP
-        98765-
-             ^
-        FAIL: Expected end of text (at char 5), (line:1, col:6)
-    """
-
-    __optionalNotMatched = _NullToken()
-
-    def __init__(self, expr, default=__optionalNotMatched):
-        super().__init__(expr, savelist=False)
-        self.saveAsList = self.expr.saveAsList
-        self.defaultValue = default
-        self.mayReturnEmpty = True
-
-    def parseImpl(self, instring, loc, doActions=True):
-        try:
-            loc, tokens = self.expr._parse(instring, loc, doActions, callPreParse=False)
-        except (ParseException, IndexError):
-            if self.defaultValue is not self.__optionalNotMatched:
-                if self.expr.resultsName:
-                    tokens = ParseResults(self.defaultValue)
-                    tokensself.expr.resultsName = self.defaultValue
-                else:
-                    tokens = self.defaultValue
-            else:
-                tokens = 
-        return loc, tokens
-
-    def __str__(self):
-        if hasattr(self, "name"):
-            return self.name
-
-        if self.strRepr is None:
-            self.strRepr = "" + str(self.expr) + ""
-
-        return self.strRepr
-
-
-class SkipTo(ParseElementEnhance):
-    """Token for skipping over all undefined text until the matched
-    expression is found.
-
-    Parameters:
-     - expr - target expression marking the end of the data to be skipped
-     - include - (default= ``False``) if True, the target expression is also parsed
-          (the skipped text and target expression are returned as a 2-element list).
-     - ignore - (default= ``None``) used to define grammars (typically quoted strings and
-          comments) that might contain false matches to the target expression
-     - failOn - (default= ``None``) define expressions that are not allowed to be
-          included in the skipped test; if found before the target expression is found,
-          the SkipTo is not a match
-
-    Example::
-
-        report = '''
-            Outstanding Issues Report - 1 Jan 2000
-
-               # | Severity | Description                               |  Days Open
-            -----+----------+-------------------------------------------+-----------
-             101 | Critical | Intermittent system crash                 |          6
-              94 | Cosmetic | Spelling error on Login ('log|n')         |         14
-              79 | Minor    | System slow when running too many reports |         47
-            '''
-        integer = Word(nums)
-        SEP = Suppress('|')
-        # use SkipTo to simply match everything up until the next SEP
-        # - ignore quoted strings, so that a '|' character inside a quoted string does not match
-        # - parse action will call token.strip() for each matched token, i.e., the description body
-        string_data = SkipTo(SEP, ignore=quotedString)
-        string_data.setParseAction(tokenMap(str.strip))
-        ticket_expr = (integer("issue_num") + SEP
-                      + string_data("sev") + SEP
-                      + string_data("desc") + SEP
-                      + integer("days_open"))
-
-        for tkt in ticket_expr.searchString(report):
-            print tkt.dump()
-
-    prints::
-
-        '101', 'Critical', 'Intermittent system crash', '6'
-        - days_open: 6
-        - desc: Intermittent system crash
-        - issue_num: 101
-        - sev: Critical
-        '94', 'Cosmetic', "Spelling error on Login ('log|n')", '14'
-        - days_open: 14
-        - desc: Spelling error on Login ('log|n')
-        - issue_num: 94
-        - sev: Cosmetic
-        '79', 'Minor', 'System slow when running too many reports', '47'
-        - days_open: 47
-        - desc: System slow when running too many reports
-        - issue_num: 79
-        - sev: Minor
-    """
-
-    def __init__(self, other, include=False, ignore=None, failOn=None):
-        super().__init__(other)
-        self.ignoreExpr = ignore
-        self.mayReturnEmpty = True
-        self.mayIndexError = False
-        self.includeMatch = include
-        self.saveAsList = False
-        if isinstance(failOn, str_type):
-            self.failOn = self._literalStringClass(failOn)
-        else:
-            self.failOn = failOn
-        self.errmsg = "No match found for " + str(self.expr)
-
-    def parseImpl(self, instring, loc, doActions=True):
-        startloc = loc
-        instrlen = len(instring)
-        expr = self.expr
-        expr_parse = self.expr._parse
-        self_failOn_canParseNext = (
-            self.failOn.canParseNext if self.failOn is not None else None
-        )
-        self_ignoreExpr_tryParse = (
-            self.ignoreExpr.tryParse if self.ignoreExpr is not None else None
-        )
-
-        tmploc = loc
-        while tmploc <= instrlen:
-            if self_failOn_canParseNext is not None:
-                # break if failOn expression matches
-                if self_failOn_canParseNext(instring, tmploc):
-                    break
-
-            if self_ignoreExpr_tryParse is not None:
-                # advance past ignore expressions
-                while 1:
-                    try:
-                        tmploc = self_ignoreExpr_tryParse(instring, tmploc)
-                    except ParseBaseException:
-                        break
-
-            try:
-                expr_parse(instring, tmploc, doActions=False, callPreParse=False)
-            except (ParseException, IndexError):
-                # no match, advance loc in string
-                tmploc += 1
-            else:
-                # matched skipto expr, done
-                break
-
-        else:
-            # ran off the end of the input string without matching skipto expr, fail
-            raise ParseException(instring, loc, self.errmsg, self)
-
-        # build up return values
-        loc = tmploc
-        skiptext = instringstartloc:loc
-        skipresult = ParseResults(skiptext)
-
-        if self.includeMatch:
-            loc, mat = expr_parse(instring, loc, doActions, callPreParse=False)
-            skipresult += mat
-
-        return loc, skipresult
-
-
-class Forward(ParseElementEnhance):
-    """Forward declaration of an expression to be defined later -
-    used for recursive grammars, such as algebraic infix notation.
-    When the expression is known, it is assigned to the ``Forward``
-    variable using the '<<' operator.
-
-    Note: take care when assigning to ``Forward`` not to overlook
-    precedence of operators.
-
-    Specifically, '|' has a lower precedence than '<<', so that::
-
-        fwdExpr << a | b | c
-
-    will actually be evaluated as::
-
-        (fwdExpr << a) | b | c
-
-    thereby leaving b and c out as parseable alternatives.  It is recommended that you
-    explicitly group the values inserted into the ``Forward``::
-
-        fwdExpr << (a | b | c)
-
-    Converting to use the '<<=' operator instead will avoid this problem.
-
-    See :class:`ParseResults.pprint` for an example of a recursive
-    parser created using ``Forward``.
-    """
-
-    def __init__(self, other=None):
-        super().__init__(other, savelist=False)
-
-    def __lshift__(self, other):
-        if isinstance(other, str_type):
-            other = self._literalStringClass(other)
-        self.expr = other
-        self.strRepr = None
-        self.mayIndexError = self.expr.mayIndexError
-        self.mayReturnEmpty = self.expr.mayReturnEmpty
-        self.setWhitespaceChars(
-            self.expr.whiteChars, copy_defaults=self.expr.copyDefaultWhiteChars
-        )
-        self.skipWhitespace = self.expr.skipWhitespace
-        self.saveAsList = self.expr.saveAsList
-        self.ignoreExprs.extend(self.expr.ignoreExprs)
-        return self
-
-    def __ilshift__(self, other):
-        return self << other
-
-    def leaveWhitespace(self):
-        self.skipWhitespace = False
-        return self
-
-    def streamline(self):
-        if not self.streamlined:
-            self.streamlined = True
-            if self.expr is not None:
-                self.expr.streamline()
-        return self
-
-    def validate(self, validateTrace=None):
-        if validateTrace is None:
-            validateTrace = 
-
-        if self not in validateTrace:
-            tmp = validateTrace: + self
-            if self.expr is not None:
-                self.expr.validate(tmp)
-        self.checkRecursion()
-
-    def __str__(self):
-        if hasattr(self, "name"):
-            return self.name
-        if self.strRepr is not None:
-            return self.strRepr
-
-        # Avoid infinite recursion by setting a temporary strRepr
-        self.strRepr = ": ..."
-
-        # Use the string representation of main expression.
-        retString = "..."
-        try:
-            if self.expr is not None:
-                retString = str(self.expr):1000
-            else:
-                retString = "None"
-        finally:
-            self.strRepr = self.__class__.__name__ + ": " + retString
-        return self.strRepr
-
-    def copy(self):
-        if self.expr is not None:
-            return super().copy()
-        else:
-            ret = Forward()
-            ret <<= self
-            return ret
-
-    def _setResultsName(self, name, listAllMatches=False):
-        if __diag__.warn_name_set_on_empty_Forward:
-            if self.expr is None:
-                warnings.warn(
-                    "{}: setting results name {!r} on {} expression "
-                    "that has no contained expression".format(
-                        "warn_name_set_on_empty_Forward", name, type(self).__name__
-                    ),
-                    stacklevel=3,
-                )
-
-        return super()._setResultsName(name, listAllMatches)
-
-
-class TokenConverter(ParseElementEnhance):
-    """
-    Abstract subclass of :class:`ParseExpression`, for converting parsed results.
-    """
-
-    def __init__(self, expr, savelist=False):
-        super().__init__(expr)  # , savelist)
-        self.saveAsList = False
-
-
-class Combine(TokenConverter):
-    """Converter to concatenate all matching tokens to a single string.
-    By default, the matching patterns must also be contiguous in the
-    input string; this can be disabled by specifying
-    ``'adjacent=False'`` in the constructor.
-
-    Example::
-
-        real = Word(nums) + '.' + Word(nums)
-        print(real.parseString('3.1416')) # -> '3', '.', '1416'
-        # will also erroneously match the following
-        print(real.parseString('3. 1416')) # -> '3', '.', '1416'
-
-        real = Combine(Word(nums) + '.' + Word(nums))
-        print(real.parseString('3.1416')) # -> '3.1416'
-        # no match when there are internal spaces
-        print(real.parseString('3. 1416')) # -> Exception: Expected W:(0123...)
-    """
-
-    def __init__(self, expr, joinString="", adjacent=True):
-        super().__init__(expr)
-        # suppress whitespace-stripping in contained parse expressions, but re-enable it on the Combine itself
-        if adjacent:
-            self.leaveWhitespace()
-        self.adjacent = adjacent
-        self.skipWhitespace = True
-        self.joinString = joinString
-        self.callPreparse = True
-
-    def ignore(self, other):
-        if self.adjacent:
-            ParserElement.ignore(self, other)
-        else:
-            super().ignore(other)
-        return self
-
-    def postParse(self, instring, loc, tokenlist):
-        retToks = tokenlist.copy()
-        del retToks:
-        retToks += ParseResults(
-            "".join(tokenlist._asStringList(self.joinString)), modal=self.modalResults
-        )
-
-        if self.resultsName and retToks.haskeys():
-            return retToks
-        else:
-            return retToks
-
-
-class Group(TokenConverter):
-    """Converter to return the matched tokens as a list - useful for
-    returning tokens of :class:`ZeroOrMore` and :class:`OneOrMore` expressions.
-
-    Example::
-
-        ident = Word(alphas)
-        num = Word(nums)
-        term = ident | num
-        func = ident + Optional(delimitedList(term))
-        print(func.parseString("fn a, b, 100"))  # -> 'fn', 'a', 'b', '100'
-
-        func = ident + Group(Optional(delimitedList(term)))
-        print(func.parseString("fn a, b, 100"))  # -> 'fn', 'a', 'b', '100'
-    """
-
-    def __init__(self, expr):
-        super().__init__(expr)
-        self.saveAsList = True
-
-    def postParse(self, instring, loc, tokenlist):
-        return tokenlist
-
-
-class Dict(TokenConverter):
-    """Converter to return a repetitive expression as a list, but also
-    as a dictionary. Each element can also be referenced using the first
-    token in the expression as its key. Useful for tabular report
-    scraping when the first column can be used as a item key.
-
-    Example::
-
-        data_word = Word(alphas)
-        label = data_word + FollowedBy(':')
-        attr_expr = Group(label + Suppress(':') + OneOrMore(data_word).setParseAction(' '.join))
-
-        text = "shape: SQUARE posn: upper left color: light blue texture: burlap"
-        attr_expr = (label + Suppress(':') + OneOrMore(data_word, stopOn=label).setParseAction(' '.join))
-
-        # print attributes as plain groups
-        print(OneOrMore(attr_expr).parseString(text).dump())
-
-        # instead of OneOrMore(expr), parse using Dict(OneOrMore(Group(expr))) - Dict will auto-assign names
-        result = Dict(OneOrMore(Group(attr_expr))).parseString(text)
-        print(result.dump())
-
-        # access named fields as dict entries, or output as dict
-        print(result'shape')
-        print(result.asDict())
-
-    prints::
-
-        'shape', 'SQUARE', 'posn', 'upper left', 'color', 'light blue', 'texture', 'burlap'
-        'shape', 'SQUARE', 'posn', 'upper left', 'color', 'light blue', 'texture', 'burlap'
-        - color: light blue
-        - posn: upper left
-        - shape: SQUARE
-        - texture: burlap
-        SQUARE
-        {'color': 'light blue', 'posn': 'upper left', 'texture': 'burlap', 'shape': 'SQUARE'}
-
-    See more examples at :class:`ParseResults` of accessing fields by results name.
-    """
-
-    def __init__(self, expr):
-        super().__init__(expr)
-        self.saveAsList = True
-
-    def postParse(self, instring, loc, tokenlist):
-        for i, tok in enumerate(tokenlist):
-            if len(tok) == 0:
-                continue
-            ikey = tok0
-            if isinstance(ikey, int):
-                ikey = str(tok0).strip()
-            if len(tok) == 1:
-                tokenlistikey = _ParseResultsWithOffset("", i)
-            elif len(tok) == 2 and not isinstance(tok1, ParseResults):
-                tokenlistikey = _ParseResultsWithOffset(tok1, i)
-            else:
-                dictvalue = tok.copy()  # ParseResults(i)
-                del dictvalue0
-                if len(dictvalue) != 1 or (
-                    isinstance(dictvalue, ParseResults) and dictvalue.haskeys()
-                ):
-                    tokenlistikey = _ParseResultsWithOffset(dictvalue, i)
-                else:
-                    tokenlistikey = _ParseResultsWithOffset(dictvalue0, i)
-
-        if self.resultsName:
-            return tokenlist
-        else:
-            return tokenlist
-
-
-class Suppress(TokenConverter):
-    """Converter for ignoring the results of a parsed expression.
-
-    Example::
-
-        source = "a, b, c,d"
-        wd = Word(alphas)
-        wd_list1 = wd + ZeroOrMore(',' + wd)
-        print(wd_list1.parseString(source))
-
-        # often, delimiters that are useful during parsing are just in the
-        # way afterward - use Suppress to keep them out of the parsed output
-        wd_list2 = wd + ZeroOrMore(Suppress(',') + wd)
-        print(wd_list2.parseString(source))
-
-    prints::
-
-        'a', ',', 'b', ',', 'c', ',', 'd'
-        'a', 'b', 'c', 'd'
-
-    (See also :class:`delimitedList`.)
-    """
-
-    def postParse(self, instring, loc, tokenlist):
-        return 
-
-    def suppress(self):
-        return self
-
-
-class OnlyOnce(object):
-    """Wrapper for parse actions, to ensure they are only called once.
-    """
-
-    def __init__(self, methodCall):
-        self.callable = _trim_arity(methodCall)
-        self.called = False
-
-    def __call__(self, s, l, t):
-        if not self.called:
-            results = self.callable(s, l, t)
-            self.called = True
-            return results
-        raise ParseException(s, l, "")
-
-    def reset(self):
-        self.called = False
-
-
-def traceParseAction(f):
-    """Decorator for debugging parse actions.
-
-    When the parse action is called, this decorator will print
-    ``">> entering method-name(line:<current_source_line>, <parse_location>, <matched_tokens>)"``.
-    When the parse action completes, the decorator will print
-    ``"<<"`` followed by the returned value, or any exception that the parse action raised.
-
-    Example::
-
-        wd = Word(alphas)
-
-        @traceParseAction
-        def remove_duplicate_chars(tokens):
-            return ''.join(sorted(set(''.join(tokens))))
-
-        wds = OneOrMore(wd).setParseAction(remove_duplicate_chars)
-        print(wds.parseString("slkdjs sld sldd sdlf sdljf"))
-
-    prints::
-
-        >>entering remove_duplicate_chars(line: 'slkdjs sld sldd sdlf sdljf', 0, ('slkdjs', 'sld', 'sldd', 'sdlf', 'sdljf', {}))
-        <<leaving remove_duplicate_chars (ret: 'dfjkls')
-        'dfjkls'
-    """
-    f = _trim_arity(f)
-
-    def z(*paArgs):
-        thisFunc = f.__name__
-        s, l, t = paArgs-3:
-        if len(paArgs) > 3:
-            thisFunc = paArgs0.__class__.__name__ + "." + thisFunc
-        sys.stderr.write(
-            ">>entering %s(line: '%s', %d, %r)\n" % (thisFunc, line(l, s), l, t)
-        )
-        try:
-            ret = f(*paArgs)
-        except Exception as exc:
-            sys.stderr.write("<<leaving %s (exception: %s)\n" % (thisFunc, exc))
-            raise
-        sys.stderr.write("<<leaving %s (ret: %r)\n" % (thisFunc, ret))
-        return ret
-
-    try:
-        z.__name__ = f.__name__
-    except AttributeError:
-        pass
-    return z
-
-
-#
-# global helpers
-#
-def delimitedList(expr, delim=",", combine=False):
-    """Helper to define a delimited list of expressions - the delimiter
-    defaults to ','. By default, the list elements and delimiters can
-    have intervening whitespace, and comments, but this can be
-    overridden by passing ``combine=True`` in the constructor. If
-    ``combine`` is set to ``True``, the matching tokens are
-    returned as a single token string, with the delimiters included;
-    otherwise, the matching tokens are returned as a list of tokens,
-    with the delimiters suppressed.
-
-    Example::
-
-        delimitedList(Word(alphas)).parseString("aa,bb,cc") # -> 'aa', 'bb', 'cc'
-        delimitedList(Word(hexnums), delim=':', combine=True).parseString("AA:BB:CC:DD:EE") # -> 'AA:BB:CC:DD:EE'
-    """
-    dlName = str(expr) + " " + str(delim) + " " + str(expr) + "..."
-    if combine:
-        return Combine(expr + ZeroOrMore(delim + expr)).setName(dlName)
-    else:
-        return (expr + ZeroOrMore(Suppress(delim) + expr)).setName(dlName)
-
-
-def countedArray(expr, intExpr=None):
-    """Helper to define a counted list of expressions.
-
-    This helper defines a pattern of the form::
-
-        integer expr expr expr...
-
-    where the leading integer tells how many expr expressions follow.
-    The matched tokens returns the array of expr tokens as a list - the
-    leading count token is suppressed.
-
-    If ``intExpr`` is specified, it should be a pyparsing expression
-    that produces an integer value.
-
-    Example::
-
-        countedArray(Word(alphas)).parseString('2 ab cd ef')  # -> 'ab', 'cd'
-
-        # in this parser, the leading integer value is given in binary,
-        # '10' indicating that 2 values are in the array
-        binaryConstant = Word('01').setParseAction(lambda t: int(t0, 2))
-        countedArray(Word(alphas), intExpr=binaryConstant).parseString('10 ab cd ef')  # -> 'ab', 'cd'
-    """
-    arrayExpr = Forward()
-
-    def countFieldParseAction(s, l, t):
-        n = t0
-        arrayExpr << (n and Group(And(expr * n)) or Group(empty))
-        return 
-
-    if intExpr is None:
-        intExpr = Word(nums).setParseAction(lambda t: int(t0))
-    else:
-        intExpr = intExpr.copy()
-    intExpr.setName("arrayLen")
-    intExpr.addParseAction(countFieldParseAction, callDuringTry=True)
-    return (intExpr + arrayExpr).setName("(len) " + str(expr) + "...")
-
-
-def _flatten(L):
-    ret = 
-    for i in L:
-        if isinstance(i, list):
-            ret.extend(_flatten(i))
-        else:
-            ret.append(i)
-    return ret
-
-
-def matchPreviousLiteral(expr):
-    """Helper to define an expression that is indirectly defined from
-    the tokens matched in a previous expression, that is, it looks for
-    a 'repeat' of a previous expression.  For example::
-
-        first = Word(nums)
-        second = matchPreviousLiteral(first)
-        matchExpr = first + ":" + second
-
-    will match ``"1:1"``, but not ``"1:2"``.  Because this
-    matches a previous literal, will also match the leading
-    ``"1:1"`` in ``"1:10"``. If this is not desired, use
-    :class:`matchPreviousExpr`. Do *not* use with packrat parsing
-    enabled.
-    """
-    rep = Forward()
-
-    def copyTokenToRepeater(s, l, t):
-        if t:
-            if len(t) == 1:
-                rep << t0
-            else:
-                # flatten t tokens
-                tflat = _flatten(t.asList())
-                rep << And(Literal(tt) for tt in tflat)
-        else:
-            rep << Empty()
-
-    expr.addParseAction(copyTokenToRepeater, callDuringTry=True)
-    rep.setName("(prev) " + str(expr))
-    return rep
-
-
-def matchPreviousExpr(expr):
-    """Helper to define an expression that is indirectly defined from
-    the tokens matched in a previous expression, that is, it looks for
-    a 'repeat' of a previous expression.  For example::
-
-        first = Word(nums)
-        second = matchPreviousExpr(first)
-        matchExpr = first + ":" + second
-
-    will match ``"1:1"``, but not ``"1:2"``.  Because this
-    matches by expressions, will *not* match the leading ``"1:1"``
-    in ``"1:10"``; the expressions are evaluated first, and then
-    compared, so ``"1"`` is compared with ``"10"``. Do *not* use
-    with packrat parsing enabled.
-    """
-    rep = Forward()
-    e2 = expr.copy()
-    rep <<= e2
-
-    def copyTokenToRepeater(s, l, t):
-        matchTokens = _flatten(t.asList())
-
-        def mustMatchTheseTokens(s, l, t):
-            theseTokens = _flatten(t.asList())
-            if theseTokens != matchTokens:
-                raise ParseException("", 0, "")
-
-        rep.setParseAction(mustMatchTheseTokens, callDuringTry=True)
-
-    expr.addParseAction(copyTokenToRepeater, callDuringTry=True)
-    rep.setName("(prev) " + str(expr))
-    return rep
-
-
-def _escapeRegexRangeChars(s):
-    # ~  escape these chars: ^-
-    for c in r"\^-":
-        s = s.replace(c, _bslash + c)
-    s = s.replace("\n", r"\n")
-    s = s.replace("\t", r"\t")
-    return str(s)
-
-
-def _collapseAndEscapeRegexRangeChars(s):
-    def is_consecutive(c):
-        c_int = ord(c)
-        is_consecutive.prev, prev = c_int, is_consecutive.prev
-        if c_int - prev > 1:
-            is_consecutive.value = next(is_consecutive.counter)
-        return is_consecutive.value
-
-    is_consecutive.prev = 0
-    is_consecutive.counter = itertools.count()
-    is_consecutive.value = -1
-
-    def escape_re_range_char(c):
-        return "\\" + c if c in r"\^-" else c
-
-    ret = 
-    for _, chars in itertools.groupby(sorted(s), key=is_consecutive):
-        first = last = next(chars)
-        for c in chars:
-            last = c
-        if first == last:
-            ret.append(escape_re_range_char(first))
-        else:
-            ret.append(
-                "{}-{}".format(escape_re_range_char(first), escape_re_range_char(last))
-            )
-    return "".join(ret)
-
-
-def oneOf(strs, caseless=False, useRegex=True, asKeyword=False):
-    """Helper to quickly define a set of alternative Literals, and makes
-    sure to do longest-first testing when there is a conflict,
-    regardless of the input order, but returns
-    a :class:`MatchFirst` for best performance.
-
-    Parameters:
-
-     - strs - a string of space-delimited literals, or a collection of
-       string literals
-     - caseless - (default= ``False``) - treat all literals as
-       caseless
-     - useRegex - (default= ``True``) - as an optimization, will
-       generate a Regex object; otherwise, will generate
-       a :class:`MatchFirst` object (if ``caseless=True`` or ``asKeyword=True``, or if
-       creating a :class:`Regex` raises an exception)
-     - asKeyword - (default=``False``) - enforce Keyword-style matching on the
-       generated expressions
-
-    Example::
-
-        comp_oper = oneOf("< = > <= >= !=")
-        var = Word(alphas)
-        number = Word(nums)
-        term = var | number
-        comparison_expr = term + comp_oper + term
-        print(comparison_expr.searchString("B = 12  AA=23 B<=AA AA>12"))
-
-    prints::
-
-        'B', '=', '12', 'AA', '=', '23', 'B', '<=', 'AA', 'AA', '>', '12'
-    """
-    if isinstance(caseless, str_type):
-        warnings.warn(
-            "More than one string argument passed to oneOf, pass "
-            "choices as a list or space-delimited string",
-            stacklevel=2,
-        )
-
-    if caseless:
-        isequal = lambda a, b: a.upper() == b.upper()
-        masks = lambda a, b: b.upper().startswith(a.upper())
-        parseElementClass = CaselessKeyword if asKeyword else CaselessLiteral
-    else:
-        isequal = lambda a, b: a == b
-        masks = lambda a, b: b.startswith(a)
-        parseElementClass = Keyword if asKeyword else Literal
-
-    symbols = 
-    if isinstance(strs, str_type):
-        symbols = strs.split()
-    elif isinstance(strs, Iterable):
-        symbols = list(strs)
-    else:
-        warnings.warn(
-            "Invalid argument to oneOf, expected string or iterable",
-            SyntaxWarning,
-            stacklevel=2,
-        )
-    if not symbols:
-        return NoMatch()
-
-    if not asKeyword:
-        # if not producing keywords, need to reorder to take care to avoid masking
-        # longer choices with shorter ones
-        i = 0
-        while i < len(symbols) - 1:
-            cur = symbolsi
-            for j, other in enumerate(symbolsi + 1 :):
-                if isequal(other, cur):
-                    del symbolsi + j + 1
-                    break
-                elif masks(cur, other):
-                    del symbolsi + j + 1
-                    symbols.insert(i, other)
-                    break
-            else:
-                i += 1
-
-    if not (caseless or asKeyword) and useRegex:
-        # ~ print(strs, "->", "|".join(_escapeRegexChars(sym) for sym in symbols))
-        try:
-            if len(symbols) == len("".join(symbols)):
-                return Regex(
-                    "%s" % "".join(_escapeRegexRangeChars(sym) for sym in symbols)
-                ).setName(" | ".join(symbols))
-            else:
-                return Regex("|".join(re.escape(sym) for sym in symbols)).setName(
-                    " | ".join(symbols)
-                )
-        except Exception:
-            warnings.warn(
-                "Exception creating Regex for oneOf, building MatchFirst",
-                SyntaxWarning,
-                stacklevel=2,
-            )
-
-    # last resort, just use MatchFirst
-    return MatchFirst(parseElementClass(sym) for sym in symbols).setName(
-        " | ".join(symbols)
-    )
-
-
-def dictOf(key, value):
-    """Helper to easily and clearly define a dictionary by specifying
-    the respective patterns for the key and value.  Takes care of
-    defining the :class:`Dict`, :class:`ZeroOrMore`, and
-    :class:`Group` tokens in the proper order.  The key pattern
-    can include delimiting markers or punctuation, as long as they are
-    suppressed, thereby leaving the significant key text.  The value
-    pattern can include named results, so that the :class:`Dict` results
-    can include named token fields.
-
-    Example::
-
-        text = "shape: SQUARE posn: upper left color: light blue texture: burlap"
-        attr_expr = (label + Suppress(':') + OneOrMore(data_word, stopOn=label).setParseAction(' '.join))
-        print(OneOrMore(attr_expr).parseString(text).dump())
-
-        attr_label = label
-        attr_value = Suppress(':') + OneOrMore(data_word, stopOn=label).setParseAction(' '.join)
-
-        # similar to Dict, but simpler call format
-        result = dictOf(attr_label, attr_value).parseString(text)
-        print(result.dump())
-        print(result'shape')
-        print(result.shape)  # object attribute access works too
-        print(result.asDict())
-
-    prints::
-
-        'shape', 'SQUARE', 'posn', 'upper left', 'color', 'light blue', 'texture', 'burlap'
-        - color: light blue
-        - posn: upper left
-        - shape: SQUARE
-        - texture: burlap
-        SQUARE
-        SQUARE
-        {'color': 'light blue', 'shape': 'SQUARE', 'posn': 'upper left', 'texture': 'burlap'}
-    """
-    return Dict(OneOrMore(Group(key + value)))
-
-
-def originalTextFor(expr, asString=True):
-    """Helper to return the original, untokenized text for a given
-    expression.  Useful to restore the parsed fields of an HTML start
-    tag into the raw tag text itself, or to revert separate tokens with
-    intervening whitespace back to the original matching input text. By
-    default, returns astring containing the original parsed text.
-
-    If the optional ``asString`` argument is passed as
-    ``False``, then the return value is
-    a :class:`ParseResults` containing any results names that
-    were originally matched, and a single token containing the original
-    matched text from the input string.  So if the expression passed to
-    :class:`originalTextFor` contains expressions with defined
-    results names, you must set ``asString`` to ``False`` if you
-    want to preserve those results name values.
-
-    Example::
-
-        src = "this is test <b> bold <i>text</i> </b> normal text "
-        for tag in ("b", "i"):
-            opener, closer = makeHTMLTags(tag)
-            patt = originalTextFor(opener + SkipTo(closer) + closer)
-            print(patt.searchString(src)0)
-
-    prints::
-
-        '<b> bold <i>text</i> </b>'
-        '<i>text</i>'
-    """
-    locMarker = Empty().setParseAction(lambda s, loc, t: loc)
-    endlocMarker = locMarker.copy()
-    endlocMarker.callPreparse = False
-    matchExpr = locMarker("_original_start") + expr + endlocMarker("_original_end")
-    if asString:
-        extractText = lambda s, l, t: st._original_start : t._original_end
-    else:
-
-        def extractText(s, l, t):
-            t: = st.pop("_original_start") : t.pop("_original_end")
-
-    matchExpr.setParseAction(extractText)
-    matchExpr.ignoreExprs = expr.ignoreExprs
-    return matchExpr
-
-
-def ungroup(expr):
-    """Helper to undo pyparsing's default grouping of And expressions,
-    even if all but one are non-empty.
-    """
-    return TokenConverter(expr).addParseAction(lambda t: t0)
-
-
-def locatedExpr(expr):
-    """Helper to decorate a returned token with its starting and ending
-    locations in the input string.
-
-    This helper adds the following results names:
-
-     - locn_start = location where matched expression begins
-     - locn_end = location where matched expression ends
-     - value = the actual parsed results
-
-    Be careful if the input text contains ``<TAB>`` characters, you
-    may want to call :class:`ParserElement.parseWithTabs`
-
-    Example::
-
-        wd = Word(alphas)
-        for match in locatedExpr(wd).searchString("ljsdf123lksdjjf123lkkjj1222"):
-            print(match)
-
-    prints::
-
-        0, 'ljsdf', 5
-        8, 'lksdjjf', 15
-        18, 'lkkjj', 23
-    """
-    locator = Empty().setParseAction(lambda s, l, t: l)
-    return Group(
-        locator("locn_start")
-        + expr("value")
-        + locator.copy().leaveWhitespace()("locn_end")
-    )
-
-
-# convenience constants for positional expressions
-empty = Empty().setName("empty")
-lineStart = LineStart().setName("lineStart")
-lineEnd = LineEnd().setName("lineEnd")
-stringStart = StringStart().setName("stringStart")
-stringEnd = StringEnd().setName("stringEnd")
-
-_escapedPunc = Word(_bslash, r"\-*.$+^?()~ ", exact=2).setParseAction(
-    lambda s, l, t: t01
-)
-_escapedHexChar = Regex(r"\\0?xX0-9a-fA-F+").setParseAction(
-    lambda s, l, t: chr(int(t0.lstrip(r"\0x"), 16))
-)
-_escapedOctChar = Regex(r"\\00-7+").setParseAction(
-    lambda s, l, t: chr(int(t01:, 8))
-)
-_singleChar = (
-    _escapedPunc | _escapedHexChar | _escapedOctChar | CharsNotIn(r"\", exact=1)
-)
-_charRange = Group(_singleChar + Suppress("-") + _singleChar)
-_reBracketExpr = (
-    Literal("")
-    + Optional("^").setResultsName("negate")
-    + Group(OneOrMore(_charRange | _singleChar)).setResultsName("body")
-    + ""
-)
-
-
-def srange(s):
-    r"""Helper to easily define string ranges for use in Word
-    construction. Borrows syntax from regexp '' string range
-    definitions::
-
-        srange("0-9")   -> "0123456789"
-        srange("a-z")   -> "abcdefghijklmnopqrstuvwxyz"
-        srange("a-z$_") -> "abcdefghijklmnopqrstuvwxyz$_"
-
-    The input string must be enclosed in 's, and the returned string
-    is the expanded character set joined into a single string. The
-    values enclosed in the 's may be:
-
-     - a single character
-     - an escaped character with a leading backslash (such as ``\-``
-       or ``\``)
-     - an escaped hex character with a leading ``'\x'``
-       (``\x21``, which is a ``'!'`` character) (``\0x##``
-       is also supported for backwards compatibility)
-     - an escaped octal character with a leading ``'\0'``
-       (``\041``, which is a ``'!'`` character)
-     - a range of any of the above, separated by a dash (``'a-z'``,
-       etc.)
-     - any combination of the above (``'aeiouy'``,
-       ``'a-zA-Z0-9_$'``, etc.)
-    """
-    _expanded = (
-        lambda p: p
-        if not isinstance(p, ParseResults)
-        else "".join(chr(c) for c in range(ord(p0), ord(p1) + 1))
-    )
-    try:
-        return "".join(_expanded(part) for part in _reBracketExpr.parseString(s).body)
-    except Exception:
-        return ""
-
-
-def matchOnlyAtCol(n):
-    """Helper method for defining parse actions that require matching at
-    a specific column in the input text.
-    """
-
-    def verifyCol(strg, locn, toks):
-        if col(locn, strg) != n:
-            raise ParseException(strg, locn, "matched token not at column %d" % n)
-
-    return verifyCol
-
-
-def replaceWith(replStr):
-    """Helper method for common parse actions that simply return
-    a literal value.  Especially useful when used with
-    :class:`transformString<ParserElement.transformString>` ().
-
-    Example::
-
-        num = Word(nums).setParseAction(lambda toks: int(toks0))
-        na = oneOf("N/A NA").setParseAction(replaceWith(math.nan))
-        term = na | num
-
-        OneOrMore(term).parseString("324 234 N/A 234") # -> 324, 234, nan, 234
-    """
-    return lambda s, l, t: replStr
-
-
-def removeQuotes(s, l, t):
-    """Helper parse action for removing quotation marks from parsed
-    quoted strings.
-
-    Example::
-
-        # by default, quotation marks are included in parsed results
-        quotedString.parseString("'Now is the Winter of our Discontent'") # -> "'Now is the Winter of our Discontent'"
-
-        # use removeQuotes to strip quotation marks from parsed results
-        quotedString.setParseAction(removeQuotes)
-        quotedString.parseString("'Now is the Winter of our Discontent'") # -> "Now is the Winter of our Discontent"
-    """
-    return t01:-1
-
-
-def tokenMap(func, *args):
-    """Helper to define a parse action by mapping a function to all
-    elements of a ParseResults list. If any additional args are passed,
-    they are forwarded to the given function as additional arguments
-    after the token, as in
-    ``hex_integer = Word(hexnums).setParseAction(tokenMap(int, 16))``,
-    which will convert the parsed data to an integer using base 16.
-
-    Example (compare the last to example in :class:`ParserElement.transformString`::
-
-        hex_ints = OneOrMore(Word(hexnums)).setParseAction(tokenMap(int, 16))
-        hex_ints.runTests('''
-            00 11 22 aa FF 0a 0d 1a
-            ''')
-
-        upperword = Word(alphas).setParseAction(tokenMap(str.upper))
-        OneOrMore(upperword).runTests('''
-            my kingdom for a horse
-            ''')
-
-        wd = Word(alphas).setParseAction(tokenMap(str.title))
-        OneOrMore(wd).setParseAction(' '.join).runTests('''
-            now is the winter of our discontent made glorious summer by this sun of york
-            ''')
-
-    prints::
-
-        00 11 22 aa FF 0a 0d 1a
-        0, 17, 34, 170, 255, 10, 13, 26
-
-        my kingdom for a horse
-        'MY', 'KINGDOM', 'FOR', 'A', 'HORSE'
-
-        now is the winter of our discontent made glorious summer by this sun of york
-        'Now Is The Winter Of Our Discontent Made Glorious Summer By This Sun Of York'
-    """
-
-    def pa(s, l, t):
-        return func(tokn, *args) for tokn in t
-
-    try:
-        func_name = getattr(func, "__name__", getattr(func, "__class__").__name__)
-    except Exception:
-        func_name = str(func)
-    pa.__name__ = func_name
-
-    return pa
-
-
-def _makeTags(tagStr, xml, suppress_LT=Suppress("<"), suppress_GT=Suppress(">")):
-    """Internal helper to construct opening and closing tag expressions, given a tag name"""
-    if isinstance(tagStr, str_type):
-        resname = tagStr
-        tagStr = Keyword(tagStr, caseless=not xml)
-    else:
-        resname = tagStr.name
-
-    tagAttrName = Word(alphas, alphanums + "_-:")
-    if xml:
-        tagAttrValue = dblQuotedString.copy().setParseAction(removeQuotes)
-        openTag = (
-            suppress_LT
-            + tagStr("tag")
-            + Dict(ZeroOrMore(Group(tagAttrName + Suppress("=") + tagAttrValue)))
-            + Optional("/", default=False)("empty").setParseAction(
-                lambda s, l, t: t0 == "/"
-            )
-            + suppress_GT
-        )
-    else:
-        tagAttrValue = quotedString.copy().setParseAction(removeQuotes) | Word(
-            printables, excludeChars=">"
-        )
-        openTag = (
-            suppress_LT
-            + tagStr("tag")
-            + Dict(
-                ZeroOrMore(
-                    Group(
-                        tagAttrName.setParseAction(lambda t: t0.lower())
-                        + Optional(Suppress("=") + tagAttrValue)
-                    )
-                )
-            )
-            + Optional("/", default=False)("empty").setParseAction(
-                lambda s, l, t: t0 == "/"
-            )
-            + suppress_GT
-        )
-    closeTag = Combine(_L("</") + tagStr + ">", adjacent=False)
-
-    openTag.setName("<%s>" % resname)
-    # add start<tagname> results name in parse action now that ungrouped names are not reported at two levels
-    openTag.addParseAction(
-        lambda t: t.__setitem__(
-            "start" + "".join(resname.replace(":", " ").title().split()), t.copy()
-        )
-    )
-    closeTag = closeTag(
-        "end" + "".join(resname.replace(":", " ").title().split())
-    ).setName("</%s>" % resname)
-    openTag.tag = resname
-    closeTag.tag = resname
-    openTag.tag_body = SkipTo(closeTag())
-    return openTag, closeTag
-
-
-def makeHTMLTags(tagStr):
-    """Helper to construct opening and closing tag expressions for HTML,
-    given a tag name. Matches tags in either upper or lower case,
-    attributes with namespaces and with quoted or unquoted values.
-
-    Example::
-
-        text = '<td>More info at the <a href="https://github.com/pyparsing/pyparsing/wiki">pyparsing</a> wiki page</td>'
-        # makeHTMLTags returns pyparsing expressions for the opening and
-        # closing tags as a 2-tuple
-        a, a_end = makeHTMLTags("A")
-        link_expr = a + SkipTo(a_end)("link_text") + a_end
-
-        for link in link_expr.searchString(text):
-            # attributes in the <A> tag (like "href" shown here) are
-            # also accessible as named results
-            print(link.link_text, '->', link.href)
-
-    prints::
-
-        pyparsing -> https://github.com/pyparsing/pyparsing/wiki
-    """
-    return _makeTags(tagStr, False)
-
-
-def makeXMLTags(tagStr):
-    """Helper to construct opening and closing tag expressions for XML,
-    given a tag name. Matches tags only in the given upper/lower case.
-
-    Example: similar to :class:`makeHTMLTags`
-    """
-    return _makeTags(tagStr, True)
-
-
-def withAttribute(*args, **attrDict):
-    """Helper to create a validating parse action to be used with start
-    tags created with :class:`makeXMLTags` or
-    :class:`makeHTMLTags`. Use ``withAttribute`` to qualify
-    a starting tag with a required attribute value, to avoid false
-    matches on common tags such as ``<TD>`` or ``<DIV>``.
-
-    Call ``withAttribute`` with a series of attribute names and
-    values. Specify the list of filter attributes names and values as:
-
-     - keyword arguments, as in ``(align="right")``, or
-     - as an explicit dict with ``**`` operator, when an attribute
-       name is also a Python reserved word, as in ``**{"class":"Customer", "align":"right"}``
-     - a list of name-value tuples, as in ``(("ns1:class", "Customer"), ("ns2:align", "right"))``
-
-    For attribute names with a namespace prefix, you must use the second
-    form.  Attribute names are matched insensitive to upper/lower case.
-
-    If just testing for ``class`` (with or without a namespace), use
-    :class:`withClass`.
-
-    To verify that the attribute exists, but without specifying a value,
-    pass ``withAttribute.ANY_VALUE`` as the value.
-
-    Example::
-
-        html = '''
-            <div>
-            Some text
-            <div type="grid">1 4 0 1 0</div>
-            <div type="graph">1,3 2,3 1,1</div>
-            <div>this has no type</div>
-            </div>
-
-        '''
-        div,div_end = makeHTMLTags("div")
-
-        # only match div tag having a type attribute with value "grid"
-        div_grid = div().setParseAction(withAttribute(type="grid"))
-        grid_expr = div_grid + SkipTo(div | div_end)("body")
-        for grid_header in grid_expr.searchString(html):
-            print(grid_header.body)
-
-        # construct a match with any div tag having a type attribute, regardless of the value
-        div_any_type = div().setParseAction(withAttribute(type=withAttribute.ANY_VALUE))
-        div_expr = div_any_type + SkipTo(div | div_end)("body")
-        for div_header in div_expr.searchString(html):
-            print(div_header.body)
-
-    prints::
-
-        1 4 0 1 0
-
-        1 4 0 1 0
-        1,3 2,3 1,1
-    """
-    if args:
-        attrs = args:
-    else:
-        attrs = attrDict.items()
-    attrs = (k, v) for k, v in attrs
-
-    def pa(s, l, tokens):
-        for attrName, attrValue in attrs:
-            if attrName not in tokens:
-                raise ParseException(s, l, "no matching attribute " + attrName)
-            if attrValue != withAttribute.ANY_VALUE and tokensattrName != attrValue:
-                raise ParseException(
-                    s,
-                    l,
-                    "attribute '%s' has value '%s', must be '%s'"
-                    % (attrName, tokensattrName, attrValue),
-                )
-
-    return pa
-
-
-withAttribute.ANY_VALUE = object()
-
-
-def withClass(classname, namespace=""):
-    """Simplified version of :class:`withAttribute` when
-    matching on a div class - made difficult because ``class`` is
-    a reserved word in Python.
-
-    Example::
-
-        html = '''
-            <div>
-            Some text
-            <div class="grid">1 4 0 1 0</div>
-            <div class="graph">1,3 2,3 1,1</div>
-            <div>this &lt;div&gt; has no class</div>
-            </div>
-
-        '''
-        div,div_end = makeHTMLTags("div")
-        div_grid = div().setParseAction(withClass("grid"))
-
-        grid_expr = div_grid + SkipTo(div | div_end)("body")
-        for grid_header in grid_expr.searchString(html):
-            print(grid_header.body)
-
-        div_any_type = div().setParseAction(withClass(withAttribute.ANY_VALUE))
-        div_expr = div_any_type + SkipTo(div | div_end)("body")
-        for div_header in div_expr.searchString(html):
-            print(div_header.body)
-
-    prints::
-
-        1 4 0 1 0
-
-        1 4 0 1 0
-        1,3 2,3 1,1
-    """
-    classattr = "%s:class" % namespace if namespace else "class"
-    return withAttribute(**{classattr: classname})
-
-
-opAssoc = types.SimpleNamespace()
-opAssoc.LEFT = object()
-opAssoc.RIGHT = object()
-
-
-def infixNotation(baseExpr, opList, lpar=Suppress("("), rpar=Suppress(")")):
-    """Helper method for constructing grammars of expressions made up of
-    operators working in a precedence hierarchy.  Operators may be unary
-    or binary, left- or right-associative.  Parse actions can also be
-    attached to operator expressions. The generated parser will also
-    recognize the use of parentheses to override operator precedences
-    (see example below).
-
-    Note: if you define a deep operator list, you may see performance
-    issues when using infixNotation. See
-    :class:`ParserElement.enablePackrat` for a mechanism to potentially
-    improve your parser performance.
-
-    Parameters:
-     - baseExpr - expression representing the most basic element for the
-       nested
-     - opList - list of tuples, one for each operator precedence level
-       in the expression grammar; each tuple is of the form ``(opExpr,
-       numTerms, rightLeftAssoc, parseAction)``, where:
-
-       - opExpr is the pyparsing expression for the operator; may also
-         be a string, which will be converted to a Literal; if numTerms
-         is 3, opExpr is a tuple of two expressions, for the two
-         operators separating the 3 terms
-       - numTerms is the number of terms for this operator (must be 1,
-         2, or 3)
-       - rightLeftAssoc is the indicator whether the operator is right
-         or left associative, using the pyparsing-defined constants
-         ``opAssoc.RIGHT`` and ``opAssoc.LEFT``.
-       - parseAction is the parse action to be associated with
-         expressions matching this operator expression (the parse action
-         tuple member may be omitted); if the parse action is passed
-         a tuple or list of functions, this is equivalent to calling
-         ``setParseAction(*fn)``
-         (:class:`ParserElement.setParseAction`)
-     - lpar - expression for matching left-parentheses
-       (default= ``Suppress('(')``)
-     - rpar - expression for matching right-parentheses
-       (default= ``Suppress(')')``)
-
-    Example::
-
-        # simple example of four-function arithmetic with ints and
-        # variable names
-        integer = pyparsing_common.signed_integer
-        varname = pyparsing_common.identifier
-
-        arith_expr = infixNotation(integer | varname,
-            
-            ('-', 1, opAssoc.RIGHT),
-            (oneOf('* /'), 2, opAssoc.LEFT),
-            (oneOf('+ -'), 2, opAssoc.LEFT),
-            )
-
-        arith_expr.runTests('''
-            5+3*6
-            (5+3)*6
-            -2--11
-            ''', fullDump=False)
-
-    prints::
-
-        5+3*6
-        5, '+', 3, '*', 6
-
-        (5+3)*6
-        5, '+', 3, '*', 6
-
-        -2--11
-        '-', 2, '-', '-', 11
-    """
-    # captive version of FollowedBy that does not do parse actions or capture results names
-    class _FB(FollowedBy):
-        def parseImpl(self, instring, loc, doActions=True):
-            self.expr.tryParse(instring, loc)
-            return loc, 
-
-    ret = Forward()
-    lastExpr = baseExpr | (lpar + ret + rpar)
-    for i, operDef in enumerate(opList):
-        opExpr, arity, rightLeftAssoc, pa = (operDef + (None,)):4
-        termName = "%s term" % opExpr if arity < 3 else "%s%s term" % opExpr
-        if arity == 3:
-            if opExpr is None or len(opExpr) != 2:
-                raise ValueError(
-                    "if numterms=3, opExpr must be a tuple or list of two expressions"
-                )
-            opExpr1, opExpr2 = opExpr
-        thisExpr = Forward().setName(termName)
-        if rightLeftAssoc == opAssoc.LEFT:
-            if arity == 1:
-                matchExpr = _FB(lastExpr + opExpr) + Group(lastExpr + OneOrMore(opExpr))
-            elif arity == 2:
-                if opExpr is not None:
-                    matchExpr = _FB(lastExpr + opExpr + lastExpr) + Group(
-                        lastExpr + OneOrMore(opExpr + lastExpr)
-                    )
-                else:
-                    matchExpr = _FB(lastExpr + lastExpr) + Group(
-                        lastExpr + OneOrMore(lastExpr)
-                    )
-            elif arity == 3:
-                matchExpr = _FB(
-                    lastExpr + opExpr1 + lastExpr + opExpr2 + lastExpr
-                ) + Group(lastExpr + opExpr1 + lastExpr + opExpr2 + lastExpr)
-            else:
-                raise ValueError(
-                    "operator must be unary (1), binary (2), or ternary (3)"
-                )
-        elif rightLeftAssoc == opAssoc.RIGHT:
-            if arity == 1:
-                # try to avoid LR with this extra test
-                if not isinstance(opExpr, Optional):
-                    opExpr = Optional(opExpr)
-                matchExpr = _FB(opExpr.expr + thisExpr) + Group(opExpr + thisExpr)
-            elif arity == 2:
-                if opExpr is not None:
-                    matchExpr = _FB(lastExpr + opExpr + thisExpr) + Group(
-                        lastExpr + OneOrMore(opExpr + thisExpr)
-                    )
-                else:
-                    matchExpr = _FB(lastExpr + thisExpr) + Group(
-                        lastExpr + OneOrMore(thisExpr)
-                    )
-            elif arity == 3:
-                matchExpr = _FB(
-                    lastExpr + opExpr1 + thisExpr + opExpr2 + thisExpr
-                ) + Group(lastExpr + opExpr1 + thisExpr + opExpr2 + thisExpr)
-            else:
-                raise ValueError(
-                    "operator must be unary (1), binary (2), or ternary (3)"
-                )
-        else:
-            raise ValueError("operator must indicate right or left associativity")
-        if pa:
-            if isinstance(pa, (tuple, list)):
-                matchExpr.setParseAction(*pa)
-            else:
-                matchExpr.setParseAction(pa)
-        thisExpr <<= matchExpr.setName(termName) | lastExpr
-        lastExpr = thisExpr
-    ret <<= lastExpr
-    return ret
-
-
-dblQuotedString = Combine(
-    Regex(r'"(?:^"\n\r\\|(?:"")|(?:\\(?:^x|x0-9a-fA-F+)))*') + '"'
-).setName("string enclosed in double quotes")
-sglQuotedString = Combine(
-    Regex(r"'(?:^'\n\r\\|(?:'')|(?:\\(?:^x|x0-9a-fA-F+)))*") + "'"
-).setName("string enclosed in single quotes")
-quotedString = Combine(
-    Regex(r'"(?:^"\n\r\\|(?:"")|(?:\\(?:^x|x0-9a-fA-F+)))*') + '"'
-    | Regex(r"'(?:^'\n\r\\|(?:'')|(?:\\(?:^x|x0-9a-fA-F+)))*") + "'"
-).setName("quotedString using single or double quotes")
-unicodeString = Combine(_L("u") + quotedString.copy()).setName("unicode string literal")
-
-
-def nestedExpr(opener="(", closer=")", content=None, ignoreExpr=quotedString.copy()):
-    """Helper method for defining nested lists enclosed in opening and
-    closing delimiters ("(" and ")" are the default).
-
-    Parameters:
-     - opener - opening character for a nested list
-       (default= ``"("``); can also be a pyparsing expression
-     - closer - closing character for a nested list
-       (default= ``")"``); can also be a pyparsing expression
-     - content - expression for items within the nested lists
-       (default= ``None``)
-     - ignoreExpr - expression for ignoring opening and closing
-       delimiters (default= :class:`quotedString`)
-
-    If an expression is not provided for the content argument, the
-    nested expression will capture all whitespace-delimited content
-    between delimiters as a list of separate values.
-
-    Use the ``ignoreExpr`` argument to define expressions that may
-    contain opening or closing characters that should not be treated as
-    opening or closing characters for nesting, such as quotedString or
-    a comment expression.  Specify multiple expressions using an
-    :class:`Or` or :class:`MatchFirst`. The default is
-    :class:`quotedString`, but if no expressions are to be ignored, then
-    pass ``None`` for this argument.
-
-    Example::
-
-        data_type = oneOf("void int short long char float double")
-        decl_data_type = Combine(data_type + Optional(Word('*')))
-        ident = Word(alphas+'_', alphanums+'_')
-        number = pyparsing_common.number
-        arg = Group(decl_data_type + ident)
-        LPAR, RPAR = map(Suppress, "()")
-
-        code_body = nestedExpr('{', '}', ignoreExpr=(quotedString | cStyleComment))
-
-        c_function = (decl_data_type("type")
-                      + ident("name")
-                      + LPAR + Optional(delimitedList(arg), )("args") + RPAR
-                      + code_body("body"))
-        c_function.ignore(cStyleComment)
-
-        source_code = '''
-            int is_odd(int x) {
-                return (x%2);
-            }
-
-            int dec_to_hex(char hchar) {
-                if (hchar >= '0' && hchar <= '9') {
-                    return (ord(hchar)-ord('0'));
-                } else {
-                    return (10+ord(hchar)-ord('A'));
-                }
-            }
-        '''
-        for func in c_function.searchString(source_code):
-            print("%(name)s (%(type)s) args: %(args)s" % func)
-
-
-    prints::
-
-        is_odd (int) args: 'int', 'x'
-        dec_to_hex (int) args: 'char', 'hchar'
-    """
-    if opener == closer:
-        raise ValueError("opening and closing strings cannot be the same")
-    if content is None:
-        if isinstance(opener, str_type) and isinstance(closer, str_type):
-            if len(opener) == 1 and len(closer) == 1:
-                if ignoreExpr is not None:
-                    content = Combine(
-                        OneOrMore(
-                            ~ignoreExpr
-                            + CharsNotIn(
-                                opener + closer + ParserElement.DEFAULT_WHITE_CHARS,
-                                exact=1,
-                            )
-                        )
-                    ).setParseAction(lambda t: t0.strip())
-                else:
-                    content = empty.copy() + CharsNotIn(
-                        opener + closer + ParserElement.DEFAULT_WHITE_CHARS
-                    ).setParseAction(lambda t: t0.strip())
-            else:
-                if ignoreExpr is not None:
-                    content = Combine(
-                        OneOrMore(
-                            ~ignoreExpr
-                            + ~Literal(opener)
-                            + ~Literal(closer)
-                            + CharsNotIn(ParserElement.DEFAULT_WHITE_CHARS, exact=1)
-                        )
-                    ).setParseAction(lambda t: t0.strip())
-                else:
-                    content = Combine(
-                        OneOrMore(
-                            ~Literal(opener)
-                            + ~Literal(closer)
-                            + CharsNotIn(ParserElement.DEFAULT_WHITE_CHARS, exact=1)
-                        )
-                    ).setParseAction(lambda t: t0.strip())
-        else:
-            raise ValueError(
-                "opening and closing arguments must be strings if no content expression is given"
-            )
-    ret = Forward()
-    if ignoreExpr is not None:
-        ret <<= Group(
-            Suppress(opener) + ZeroOrMore(ignoreExpr | ret | content) + Suppress(closer)
-        )
-    else:
-        ret <<= Group(Suppress(opener) + ZeroOrMore(ret | content) + Suppress(closer))
-    ret.setName("nested %s%s expression" % (opener, closer))
-    return ret
-
-
-def indentedBlock(blockStatementExpr, indentStack, indent=True, backup_stacks=):
-    """Helper method for defining space-delimited indentation blocks,
-    such as those used to define block statements in Python source code.
-
-    Parameters:
-
-     - blockStatementExpr - expression defining syntax of statement that
-       is repeated within the indented block
-     - indentStack - list created by caller to manage indentation stack
-       (multiple statementWithIndentedBlock expressions within a single
-       grammar should share a common indentStack)
-     - indent - boolean indicating whether block must be indented beyond
-       the current level; set to False for block of left-most
-       statements (default= ``True``)
-
-    A valid block must contain at least one ``blockStatement``.
-
-    Example::
-
-        data = '''
-        def A(z):
-          A1
-          B = 100
-          G = A2
-          A2
-          A3
-        B
-        def BB(a,b,c):
-          BB1
-          def BBA():
-            bba1
-            bba2
-            bba3
-        C
-        D
-        def spam(x,y):
-             def eggs(z):
-                 pass
-        '''
-
-
-        indentStack = 1
-        stmt = Forward()
-
-        identifier = Word(alphas, alphanums)
-        funcDecl = ("def" + identifier + Group("(" + Optional(delimitedList(identifier)) + ")") + ":")
-        func_body = indentedBlock(stmt, indentStack)
-        funcDef = Group(funcDecl + func_body)
-
-        rvalue = Forward()
-        funcCall = Group(identifier + "(" + Optional(delimitedList(rvalue)) + ")")
-        rvalue << (funcCall | identifier | Word(nums))
-        assignment = Group(identifier + "=" + rvalue)
-        stmt << (funcDef | assignment | identifier)
-
-        module_body = OneOrMore(stmt)
-
-        parseTree = module_body.parseString(data)
-        parseTree.pprint()
-
-    prints::
-
-        'def',
-          'A',
-          '(', 'z', ')',
-          ':',
-          'A1', 'B', '=', '100', 'G', '=', 'A2', 'A2', 'A3',
-         'B',
-         'def',
-          'BB',
-          '(', 'a', 'b', 'c', ')',
-          ':',
-          'BB1', 'def', 'BBA', '(', ')', ':', 'bba1', 'bba2', 'bba3',
-         'C',
-         'D',
-         'def',
-          'spam',
-          '(', 'x', 'y', ')',
-          ':',
-          'def', 'eggs', '(', 'z', ')', ':', 'pass'
-    """
-    backup_stacks.append(indentStack:)
-
-    def reset_stack():
-        indentStack: = backup_stacks-1
-
-    def checkPeerIndent(s, l, t):
-        if l >= len(s):
-            return
-        curCol = col(l, s)
-        if curCol != indentStack-1:
-            if curCol > indentStack-1:
-                raise ParseException(s, l, "illegal nesting")
-            raise ParseException(s, l, "not a peer entry")
-
-    def checkSubIndent(s, l, t):
-        curCol = col(l, s)
-        if curCol > indentStack-1:
-            indentStack.append(curCol)
-        else:
-            raise ParseException(s, l, "not a subentry")
-
-    def checkUnindent(s, l, t):
-        if l >= len(s):
-            return
-        curCol = col(l, s)
-        if not (indentStack and curCol in indentStack):
-            raise ParseException(s, l, "not an unindent")
-        if curCol < indentStack-1:
-            indentStack.pop()
-
-    NL = OneOrMore(LineEnd().setWhitespaceChars("\t ").suppress())
-    INDENT = (Empty() + Empty().setParseAction(checkSubIndent)).setName("INDENT")
-    PEER = Empty().setParseAction(checkPeerIndent).setName("")
-    UNDENT = Empty().setParseAction(checkUnindent).setName("UNINDENT")
-    if indent:
-        smExpr = Group(
-            Optional(NL)
-            + INDENT
-            + OneOrMore(PEER + Group(blockStatementExpr) + Optional(NL))
-            + UNDENT
-        )
-    else:
-        smExpr = Group(
-            Optional(NL)
-            + OneOrMore(PEER + Group(blockStatementExpr) + Optional(NL))
-            + Optional(UNDENT)
-        )
-
-    # add a parse action to remove backup_stack from list of backups
-    smExpr.addParseAction(
-        lambda: backup_stacks.pop(-1) and None if backup_stacks else None
-    )
-    smExpr.setFailAction(lambda a, b, c, d: reset_stack())
-    blockStatementExpr.ignore(_bslash + LineEnd())
-    return smExpr.setName("indented block")
-
-
-alphas8bit = srange(r"\0xc0-\0xd6\0xd8-\0xf6\0xf8-\0xff")
-punc8bit = srange(r"\0xa1-\0xbf\0xd7\0xf7")
-
-anyOpenTag, anyCloseTag = makeHTMLTags(
-    Word(alphas, alphanums + "_:").setName("any tag")
-)
-_htmlEntityMap = dict(zip("gt lt amp nbsp quot apos".split(), "><& \"'"))
-commonHTMLEntity = Regex(
-    "&(?P<entity>" + "|".join(_htmlEntityMap.keys()) + ");"
-).setName("common HTML entity")
-
-
-def replaceHTMLEntity(t):
-    """Helper parser action to replace common HTML entities with their special characters"""
-    return _htmlEntityMap.get(t.entity)
-
-
-# it's easy to get these comment structures wrong - they're very common, so may as well make them available
-cStyleComment = Combine(Regex(r"/\*(?:^*|\*(?!/))*") + "*/").setName(
-    "C style comment"
-)
-"Comment of the form ``/* ... */``"
-
-htmlComment = Regex(r"").setName("HTML comment")
-"Comment of the form ````"
-
-restOfLine = Regex(r".*").leaveWhitespace().setName("rest of line")
-dblSlashComment = Regex(r"//(?:\\\n|^\n)*").setName("// comment")
-"Comment of the form ``// ... (to end of line)``"
-
-cppStyleComment = Combine(
-    Regex(r"/\*(?:^*|\*(?!/))*") + "*/" | dblSlashComment
-).setName("C++ style comment")
-"Comment of either form :class:`cStyleComment` or :class:`dblSlashComment`"
-
-javaStyleComment = cppStyleComment
-"Same as :class:`cppStyleComment`"
-
-pythonStyleComment = Regex(r"#.*").setName("Python style comment")
-"Comment of the form ``# ... (to end of line)``"
-
-# some other useful expressions - using lower-case class name since we are really using this as a namespace
-class pyparsing_common:
-    """Here are some common low-level expressions that may be useful in
-    jump-starting parser development:
-
-     - numeric forms (:class:`integers<integer>`, :class:`reals<real>`,
-       :class:`scientific notation<sci_real>`)
-     - common :class:`programming identifiers<identifier>`
-     - network addresses (:class:`MAC<mac_address>`,
-       :class:`IPv4<ipv4_address>`, :class:`IPv6<ipv6_address>`)
-     - ISO8601 :class:`dates<iso8601_date>` and
-       :class:`datetime<iso8601_datetime>`
-     - :class:`UUID<uuid>`
-     - :class:`comma-separated list<comma_separated_list>`
-
-    Parse actions:
-
-     - :class:`convertToInteger`
-     - :class:`convertToFloat`
-     - :class:`convertToDate`
-     - :class:`convertToDatetime`
-     - :class:`stripHTMLTags`
-     - :class:`upcaseTokens`
-     - :class:`downcaseTokens`
-
-    Example::
-
-        pyparsing_common.number.runTests('''
-            # any int or real number, returned as the appropriate type
-            100
-            -100
-            +100
-            3.14159
-            6.02e23
-            1e-12
-            ''')
-
-        pyparsing_common.fnumber.runTests('''
-            # any int or real number, returned as float
-            100
-            -100
-            +100
-            3.14159
-            6.02e23
-            1e-12
-            ''')
-
-        pyparsing_common.hex_integer.runTests('''
-            # hex numbers
-            100
-            FF
-            ''')
-
-        pyparsing_common.fraction.runTests('''
-            # fractions
-            1/2
-            -3/4
-            ''')
-
-        pyparsing_common.mixed_integer.runTests('''
-            # mixed fractions
-            1
-            1/2
-            -3/4
-            1-3/4
-            ''')
-
-        import uuid
-        pyparsing_common.uuid.setParseAction(tokenMap(uuid.UUID))
-        pyparsing_common.uuid.runTests('''
-            # uuid
-            12345678-1234-5678-1234-567812345678
-            ''')
-
-    prints::
-
-        # any int or real number, returned as the appropriate type
-        100
-        100
-
-        -100
-        -100
-
-        +100
-        100
-
-        3.14159
-        3.14159
-
-        6.02e23
-        6.02e+23
-
-        1e-12
-        1e-12
-
-        # any int or real number, returned as float
-        100
-        100.0
-
-        -100
-        -100.0
-
-        +100
-        100.0
-
-        3.14159
-        3.14159
-
-        6.02e23
-        6.02e+23
-
-        1e-12
-        1e-12
-
-        # hex numbers
-        100
-        256
-
-        FF
-        255
-
-        # fractions
-        1/2
-        0.5
-
-        -3/4
-        -0.75
-
-        # mixed fractions
-        1
-        1
-
-        1/2
-        0.5
-
-        -3/4
-        -0.75
-
-        1-3/4
-        1.75
-
-        # uuid
-        12345678-1234-5678-1234-567812345678
-        UUID('12345678-1234-5678-1234-567812345678')
-    """
-
-    convertToInteger = tokenMap(int)
-    """
-    Parse action for converting parsed integers to Python int
-    """
-
-    convertToFloat = tokenMap(float)
-    """
-    Parse action for converting parsed numbers to Python float
-    """
-
-    integer = Word(nums).setName("integer").setParseAction(convertToInteger)
-    """expression that parses an unsigned integer, returns an int"""
-
-    hex_integer = Word(hexnums).setName("hex integer").setParseAction(tokenMap(int, 16))
-    """expression that parses a hexadecimal integer, returns an int"""
-
-    signed_integer = (
-        Regex(r"+-?\d+").setName("signed integer").setParseAction(convertToInteger)
-    )
-    """expression that parses an integer with optional leading sign, returns an int"""
-
-    fraction = (
-        signed_integer().setParseAction(convertToFloat)
-        + "/"
-        + signed_integer().setParseAction(convertToFloat)
-    ).setName("fraction")
-    """fractional expression of an integer divided by an integer, returns a float"""
-    fraction.addParseAction(lambda t: t0 / t-1)
-
-    mixed_integer = (
-        fraction | signed_integer + Optional(Optional("-").suppress() + fraction)
-    ).setName("fraction or mixed integer-fraction")
-    """mixed integer of the form 'integer - fraction', with optional leading integer, returns float"""
-    mixed_integer.addParseAction(sum)
-
-    real = (
-        Regex(r"+-?(:?\d+\.\d*|\.\d+)")
-        .setName("real number")
-        .setParseAction(convertToFloat)
-    )
-    """expression that parses a floating point number and returns a float"""
-
-    sci_real = (
-        Regex(r"+-?(:?\d+(:?eE+-?\d+)|(:?\d+\.\d*|\.\d+)(:?eE+-?\d+)?)")
-        .setName("real number with scientific notation")
-        .setParseAction(convertToFloat)
-    )
-    """expression that parses a floating point number with optional
-    scientific notation and returns a float"""
-
-    # streamlining this expression makes the docs nicer-looking
-    number = (sci_real | real | signed_integer).streamline()
-    """any numeric expression, returns the corresponding Python type"""
-
-    fnumber = (
-        Regex(r"+-?\d+\.?\d*(eE+-?\d+)?")
-        .setName("fnumber")
-        .setParseAction(convertToFloat)
-    )
-    """any int or real number, returned as float"""
-
-    identifier = Word(alphas + "_", alphanums + "_").setName("identifier")
-    """typical code identifier (leading alpha or '_', followed by 0 or more alphas, nums, or '_')"""
-
-    ipv4_address = Regex(
-        r"(250-5|20-40-9|1?0-9{1,2})(\.(250-5|20-40-9|1?0-9{1,2})){3}"
-    ).setName("IPv4 address")
-    "IPv4 address (``0.0.0.0 - 255.255.255.255``)"
-
-    _ipv6_part = Regex(r"0-9a-fA-F{1,4}").setName("hex_integer")
-    _full_ipv6_address = (_ipv6_part + (":" + _ipv6_part) * 7).setName(
-        "full IPv6 address"
-    )
-    _short_ipv6_address = (
-        Optional(_ipv6_part + (":" + _ipv6_part) * (0, 6))
-        + "::"
-        + Optional(_ipv6_part + (":" + _ipv6_part) * (0, 6))
-    ).setName("short IPv6 address")
-    _short_ipv6_address.addCondition(
-        lambda t: sum(1 for tt in t if pyparsing_common._ipv6_part.matches(tt)) < 8
-    )
-    _mixed_ipv6_address = ("::ffff:" + ipv4_address).setName("mixed IPv6 address")
-    ipv6_address = Combine(
-        (_full_ipv6_address | _mixed_ipv6_address | _short_ipv6_address).setName(
-            "IPv6 address"
-        )
-    ).setName("IPv6 address")
-    "IPv6 address (long, short, or mixed form)"
-
-    mac_address = Regex(
-        r"0-9a-fA-F{2}(:.-)0-9a-fA-F{2}(?:\10-9a-fA-F{2}){4}"
-    ).setName("MAC address")
-    "MAC address xx:xx:xx:xx:xx (may also have '-' or '.' delimiters)"
-
-    @staticmethod
-    def convertToDate(fmt="%Y-%m-%d"):
-        """
-        Helper to create a parse action for converting parsed date string to Python datetime.date
-
-        Params -
-         - fmt - format to be passed to datetime.strptime (default= ``"%Y-%m-%d"``)
-
-        Example::
-
-            date_expr = pyparsing_common.iso8601_date.copy()
-            date_expr.setParseAction(pyparsing_common.convertToDate())
-            print(date_expr.parseString("1999-12-31"))
-
-        prints::
-
-            datetime.date(1999, 12, 31)
-        """
-
-        def cvt_fn(s, l, t):
-            try:
-                return datetime.strptime(t0, fmt).date()
-            except ValueError as ve:
-                raise ParseException(s, l, str(ve))
-
-        return cvt_fn
-
-    @staticmethod
-    def convertToDatetime(fmt="%Y-%m-%dT%H:%M:%S.%f"):
-        """Helper to create a parse action for converting parsed
-        datetime string to Python datetime.datetime
-
-        Params -
-         - fmt - format to be passed to datetime.strptime (default= ``"%Y-%m-%dT%H:%M:%S.%f"``)
-
-        Example::
-
-            dt_expr = pyparsing_common.iso8601_datetime.copy()
-            dt_expr.setParseAction(pyparsing_common.convertToDatetime())
-            print(dt_expr.parseString("1999-12-31T23:59:59.999"))
-
-        prints::
-
-            datetime.datetime(1999, 12, 31, 23, 59, 59, 999000)
-        """
-
-        def cvt_fn(s, l, t):
-            try:
-                return datetime.strptime(t0, fmt)
-            except ValueError as ve:
-                raise ParseException(s, l, str(ve))
-
-        return cvt_fn
-
-    iso8601_date = Regex(
-        r"(?P<year>\d{4})(?:-(?P<month>\d\d)(?:-(?P<day>\d\d))?)?"
-    ).setName("ISO8601 date")
-    "ISO8601 date (``yyyy-mm-dd``)"
-
-    iso8601_datetime = Regex(
-        r"(?P<year>\d{4})-(?P<month>\d\d)-(?P<day>\d\d)T (?P<hour>\d\d):(?P<minute>\d\d)(:(?P<second>\d\d(\.\d*)?)?)?(?P<tz>Z|+-\d\d:?\d\d)?"
-    ).setName("ISO8601 datetime")
-    "ISO8601 datetime (``yyyy-mm-ddThh:mm:ss.s(Z|+-00:00)``) - trailing seconds, milliseconds, and timezone optional; accepts separating ``'T'`` or ``' '``"
-
-    uuid = Regex(r"0-9a-fA-F{8}(-0-9a-fA-F{4}){3}-0-9a-fA-F{12}").setName("UUID")
-    "UUID (``xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx``)"
-
-    _html_stripper = anyOpenTag.suppress() | anyCloseTag.suppress()
-
-    @staticmethod
-    def stripHTMLTags(s, l, tokens):
-        """Parse action to remove HTML tags from web page HTML source
-
-        Example::
-
-            # strip HTML links from normal text
-            text = '<td>More info at the <a href="https://github.com/pyparsing/pyparsing/wiki">pyparsing</a> wiki page</td>'
-            td, td_end = makeHTMLTags("TD")
-            table_text = td + SkipTo(td_end).setParseAction(pyparsing_common.stripHTMLTags)("body") + td_end
-            print(table_text.parseString(text).body)
-
-        Prints::
-
-            More info at the pyparsing wiki page
-        """
-        return pyparsing_common._html_stripper.transformString(tokens0)
-
-    _commasepitem = (
-        Combine(
-            OneOrMore(
-                ~Literal(",")
-                + ~LineEnd()
-                + Word(printables, excludeChars=",")
-                + Optional(White(" \t") + ~FollowedBy(LineEnd() | ","))
-            )
-        )
-        .streamline()
-        .setName("commaItem")
-    )
-    comma_separated_list = delimitedList(
-        Optional(quotedString.copy() | _commasepitem, default="")
-    ).setName("comma separated list")
-    """Predefined expression of 1 or more printable words or quoted strin gs, separated by commas."""
-
-    upcaseTokens = staticmethod(tokenMap(lambda t: t.upper()))
-    """Parse action to convert tokens to upper case."""
-
-    downcaseTokens = staticmethod(tokenMap(lambda t: t.lower()))
-    """Parse action to convert tokens to lower case."""
-
-
-class _lazyclassproperty(object):
-    def __init__(self, fn):
-        self.fn = fn
-        self.__doc__ = fn.__doc__
-        self.__name__ = fn.__name__
-
-    def __get__(self, obj, cls):
-        if cls is None:
-            cls = type(obj)
-        if not hasattr(cls, "_intern") or any(
-            cls._intern is getattr(superclass, "_intern", )
-            for superclass in cls.__mro__1:
-        ):
-            cls._intern = {}
-        attrname = self.fn.__name__
-        if attrname not in cls._intern:
-            cls._internattrname = self.fn(cls)
-        return cls._internattrname
-
-
-class unicode_set(object):
-    """
-    A set of Unicode characters, for language-specific strings for
-    ``alphas``, ``nums``, ``alphanums``, and ``printables``.
-    A unicode_set is defined by a list of ranges in the Unicode character
-    set, in a class attribute ``_ranges``, such as::
-
-        _ranges = (0x0020, 0x007e), (0x00a0, 0x00ff),
-
-    A unicode set can also be defined using multiple inheritance of other unicode sets::
-
-        class CJK(Chinese, Japanese, Korean):
-            pass
-    """
-
-    _ranges = 
-
-    @classmethod
-    def _get_chars_for_ranges(cls):
-        ret = 
-        for cc in cls.__mro__:
-            if cc is unicode_set:
-                break
-            for rr in cc._ranges:
-                ret.extend(range(rr0, rr-1 + 1))
-        return chr(c) for c in sorted(set(ret))
-
-    @_lazyclassproperty
-    def printables(cls):
-        "all non-whitespace characters in this range"
-        return "".join(filterfalse(str.isspace, cls._get_chars_for_ranges()))
-
-    @_lazyclassproperty
-    def alphas(cls):
-        "all alphabetic characters in this range"
-        return "".join(filter(str.isalpha, cls._get_chars_for_ranges()))
-
-    @_lazyclassproperty
-    def nums(cls):
-        "all numeric digit characters in this range"
-        return "".join(filter(str.isdigit, cls._get_chars_for_ranges()))
-
-    @_lazyclassproperty
-    def alphanums(cls):
-        "all alphanumeric characters in this range"
-        return cls.alphas + cls.nums
-
-
-class pyparsing_unicode(unicode_set):
-    """
-    A namespace class for defining common language unicode_sets.
-    """
-
-    _ranges = (32, sys.maxunicode)
-
-    class Latin1(unicode_set):
-        "Unicode set for Latin-1 Unicode Character Range"
-        _ranges = 
-            (0x0020, 0x007E),
-            (0x00A0, 0x00FF),
-        
-
-    class LatinA(unicode_set):
-        "Unicode set for Latin-A Unicode Character Range"
-        _ranges = 
-            (0x0100, 0x017F),
-        
-
-    class LatinB(unicode_set):
-        "Unicode set for Latin-B Unicode Character Range"
-        _ranges = 
-            (0x0180, 0x024F),
-        
-
-    class Greek(unicode_set):
-        "Unicode set for Greek Unicode Character Ranges"
-        _ranges = 
-            (0x0370, 0x03FF),
-            (0x1F00, 0x1F15),
-            (0x1F18, 0x1F1D),
-            (0x1F20, 0x1F45),
-            (0x1F48, 0x1F4D),
-            (0x1F50, 0x1F57),
-            (0x1F59,),
-            (0x1F5B,),
-            (0x1F5D,),
-            (0x1F5F, 0x1F7D),
-            (0x1F80, 0x1FB4),
-            (0x1FB6, 0x1FC4),
-            (0x1FC6, 0x1FD3),
-            (0x1FD6, 0x1FDB),
-            (0x1FDD, 0x1FEF),
-            (0x1FF2, 0x1FF4),
-            (0x1FF6, 0x1FFE),
-        
-
-    class Cyrillic(unicode_set):
-        "Unicode set for Cyrillic Unicode Character Range"
-        _ranges = (0x0400, 0x04FF)
-
-    class Chinese(unicode_set):
-        "Unicode set for Chinese Unicode Character Range"
-        _ranges = 
-            (0x4E00, 0x9FFF),
-            (0x3000, 0x303F),
-        
-
-    class Japanese(unicode_set):
-        "Unicode set for Japanese Unicode Character Range, combining Kanji, Hiragana, and Katakana ranges"
-        _ranges = 
-
-        class Kanji(unicode_set):
-            "Unicode set for Kanji Unicode Character Range"
-            _ranges = 
-                (0x4E00, 0x9FBF),
-                (0x3000, 0x303F),
-            
-
-        class Hiragana(unicode_set):
-            "Unicode set for Hiragana Unicode Character Range"
-            _ranges = 
-                (0x3040, 0x309F),
-            
-
-        class Katakana(unicode_set):
-            "Unicode set for Katakana  Unicode Character Range"
-            _ranges = 
-                (0x30A0, 0x30FF),
-            
-
-    class Korean(unicode_set):
-        "Unicode set for Korean Unicode Character Range"
-        _ranges = 
-            (0xAC00, 0xD7AF),
-            (0x1100, 0x11FF),
-            (0x3130, 0x318F),
-            (0xA960, 0xA97F),
-            (0xD7B0, 0xD7FF),
-            (0x3000, 0x303F),
-        
-
-    class CJK(Chinese, Japanese, Korean):
-        "Unicode set for combined Chinese, Japanese, and Korean (CJK) Unicode Character Range"
-        pass
-
-    class Thai(unicode_set):
-        "Unicode set for Thai Unicode Character Range"
-        _ranges = 
-            (0x0E01, 0x0E3A),
-            (0x0E3F, 0x0E5B),
-        
-
-    class Arabic(unicode_set):
-        "Unicode set for Arabic Unicode Character Range"
-        _ranges = 
-            (0x0600, 0x061B),
-            (0x061E, 0x06FF),
-            (0x0700, 0x077F),
-        
-
-    class Hebrew(unicode_set):
-        "Unicode set for Hebrew Unicode Character Range"
-        _ranges = 
-            (0x0590, 0x05FF),
-        
-
-    class Devanagari(unicode_set):
-        "Unicode set for Devanagari Unicode Character Range"
-        _ranges = (0x0900, 0x097F), (0xA8E0, 0xA8FF)
-
-
-pyparsing_unicode.Japanese._ranges = (
-    pyparsing_unicode.Japanese.Kanji._ranges
-    + pyparsing_unicode.Japanese.Hiragana._ranges
-    + pyparsing_unicode.Japanese.Katakana._ranges
-)
-
-# define ranges in language character sets
-pyparsing_unicode.العربية = pyparsing_unicode.Arabic
-pyparsing_unicode.中文 = pyparsing_unicode.Chinese
-pyparsing_unicode.кириллица = pyparsing_unicode.Cyrillic
-pyparsing_unicode.Ελληνικά = pyparsing_unicode.Greek
-pyparsing_unicode.עִברִית = pyparsing_unicode.Hebrew
-pyparsing_unicode.日本語 = pyparsing_unicode.Japanese
-pyparsing_unicode.Japanese.漢字 = pyparsing_unicode.Japanese.Kanji
-pyparsing_unicode.Japanese.カタカナ = pyparsing_unicode.Japanese.Katakana
-pyparsing_unicode.Japanese.ひらがな = pyparsing_unicode.Japanese.Hiragana
-pyparsing_unicode.한국어 = pyparsing_unicode.Korean
-pyparsing_unicode.ไทย = pyparsing_unicode.Thai
-pyparsing_unicode.देवनागरी = pyparsing_unicode.Devanagari
-
-
-class pyparsing_test:
-    """
-    namespace class for classes useful in writing unit tests
-    """
-
-    class reset_pyparsing_context:
-        """
-        Context manager to be used when writing unit tests that modify pyparsing config values:
-         - packrat parsing
-         - default whitespace characters
-         - default keyword characters
-         - literal string auto-conversion class
-         - __diag__ settings
-
-        Example:
-            with reset_pyparsing_context():
-                # test that literals used to construct a grammar are automatically suppressed
-                ParserElement.inlineLiteralsUsing(Suppress)
-
-                term = Word(alphas) | Word(nums)
-                group = Group('(' + term... + ')')
-
-                # assert that the '()' characters are not included in the parsed tokens
-                self.assertParseAndCheckLisst(group, "(abc 123 def)", 'abc', '123', 'def')
-
-            # after exiting context manager, literals are converted to Literal expressions again
-        """
-
-        def __init__(self):
-            self._save_context = {}
-
-        def __enter__(self):
-            self.save()
-
-        def __exit__(self, *args):
-            self.restore()
-
-        def save(self):
-            self._save_context"default_whitespace" = ParserElement.DEFAULT_WHITE_CHARS
-            self._save_context"default_keyword_chars" = Keyword.DEFAULT_KEYWORD_CHARS
-            self._save_context
-                "literal_string_class"
-             = ParserElement._literalStringClass
-            self._save_context"packrat_enabled" = ParserElement._packratEnabled
-            self._save_context"packrat_parse" = ParserElement._parse
-            self._save_context"__diag__" = {
-                name: getattr(__diag__, name) for name in __diag__._all_names
-            }
-            self._save_context"__compat__" = {
-                "collect_all_And_tokens": __compat__.collect_all_And_tokens
-            }
-            return self
-
-        def restore(self):
-            # restore pyparsing global state to what was saved
-            ParserElement.setDefaultWhitespaceChars(
-                self._save_context"default_whitespace"
-            )
-            Keyword.DEFAULT_KEYWORD_CHARS = self._save_context"default_keyword_chars"
-            ParserElement.inlineLiteralsUsing(
-                self._save_context"literal_string_class"
-            )
-            ParserElement._packratEnabled = self._save_context"packrat_enabled"
-            ParserElement._parse = self._save_context"packrat_parse"
-            for name, value in self._save_context"__diag__".items():
-                (__diag__.enable if value else __diag__.disable)(name)
-            for name, value in self._save_context"__compat__".items():
-                setattr(__compat__, name, value)
-
-    class TestParseResultsAsserts(unittest.TestCase):
-        def assertParseResultsEquals(
-            self, result, expected_list=None, expected_dict=None, msg=None
-        ):
-            """
-            Unit test assertion to compare a ParseResults object with an optional expected_list,
-            and compare any defined results names with an optional expected_dict.
-            """
-            if expected_list is not None:
-                self.assertEqual(expected_list, result.asList(), msg=msg)
-            if expected_dict is not None:
-                self.assertEqual(expected_dict, result.asDict(), msg=msg)
-
-        def assertParseAndCheckList(
-            self, expr, test_string, expected_list, msg=None, verbose=True
-        ):
-            """
-            Convenience wrapper assert to test a parser element and input string, and assert that
-            the resulting ParseResults.asList() is equal to the expected_list.
-            """
-            result = expr.parseString(test_string, parseAll=True)
-            if verbose:
-                print(result.dump())
-            self.assertParseResultsEquals(result, expected_list=expected_list, msg=msg)
-
-        def assertParseAndCheckDict(
-            self, expr, test_string, expected_dict, msg=None, verbose=True
-        ):
-            """
-            Convenience wrapper assert to test a parser element and input string, and assert that
-            the resulting ParseResults.asDict() is equal to the expected_dict.
-            """
-            result = expr.parseString(test_string, parseAll=True)
-            if verbose:
-                print(result.dump())
-            self.assertParseResultsEquals(result, expected_dict=expected_dict, msg=msg)
-
-        def assertRunTestResults(
-            self, run_tests_report, expected_parse_results=None, msg=None
-        ):
-            """
-            Unit test assertion to evaluate output of ParserElement.runTests(). If a list of
-            list-dict tuples is given as the expected_parse_results argument, then these are zipped
-            with the report tuples returned by runTests and evaluated using assertParseResultsEquals.
-            Finally, asserts that the overall runTests() success value is True.
-
-            :param run_tests_report: tuple(bool, tuple(str, ParseResults or Exception)) returned from runTests
-            :param expected_parse_results (optional): tuple(str, list, dict, Exception)
-            """
-            run_test_success, run_test_results = run_tests_report
-
-            if expected_parse_results is not None:
-                merged = 
-                    (*rpt, expected)
-                    for rpt, expected in zip(run_test_results, expected_parse_results)
-                
-                for test_string, result, expected in merged:
-                    # expected should be a tuple containing a list and/or a dict or an exception,
-                    # and optional failure message string
-                    # an empty tuple will skip any result validation
-                    fail_msg = next(
-                        (exp for exp in expected if isinstance(exp, str)), None
-                    )
-                    expected_exception = next(
-                        (
-                            exp
-                            for exp in expected
-                            if isinstance(exp, type) and issubclass(exp, Exception)
-                        ),
-                        None,
-                    )
-                    if expected_exception is not None:
-                        with self.assertRaises(
-                            expected_exception=expected_exception, msg=fail_msg or msg
-                        ):
-                            if isinstance(result, Exception):
-                                raise result
-                    else:
-                        expected_list = next(
-                            (exp for exp in expected if isinstance(exp, list)), None
-                        )
-                        expected_dict = next(
-                            (exp for exp in expected if isinstance(exp, dict)), None
-                        )
-                        if (expected_list, expected_dict) != (None, None):
-                            self.assertParseResultsEquals(
-                                result,
-                                expected_list=expected_list,
-                                expected_dict=expected_dict,
-                                msg=fail_msg or msg,
-                            )
-                        else:
-                            # warning here maybe?
-                            print("no validation for {!r}".format(test_string))
-
-            # do this last, in case some specific test results can be reported instead
-            self.assertTrue(
-                run_test_success, msg=msg if msg is not None else "failed runTests"
-            )
-
-        @contextmanager
-        def assertRaisesParseException(self, exc_type=ParseException, msg=None):
-            with self.assertRaises(exc_type, msg=msg):
-                yield
-
-
-# build list of built-in expressions, for future reference if a global default value
-# gets updated
-_builtin_exprs = 
-    v
-    for v in itertools.chain(vars().values(), vars(pyparsing_common).values())
-    if isinstance(v, ParserElement)
-
-
-
-if __name__ == "__main__":
-
-    selectToken = CaselessLiteral("select")
-    fromToken = CaselessLiteral("from")
-
-    ident = Word(alphas, alphanums + "_$")
-
-    columnName = delimitedList(ident, ".", combine=True).setParseAction(
-        pyparsing_common.upcaseTokens
-    )
-    columnNameList = Group(delimitedList(columnName)).setName("columns")
-    columnSpec = "*" | columnNameList
-
-    tableName = delimitedList(ident, ".", combine=True).setParseAction(
-        pyparsing_common.upcaseTokens
-    )
-    tableNameList = Group(delimitedList(tableName)).setName("tables")
-
-    simpleSQL = (
-        selectToken("command")
-        + columnSpec("columns")
-        + fromToken
-        + tableNameList("tables")
-    )
-
-    # demo runTests method, including embedded comments in test string
-    simpleSQL.runTests(
-        """
-        # '*' as column list and dotted table name
-        select * from SYS.XYZZY
-
-        # caseless match on "SELECT", and casts back to "select"
-        SELECT * from XYZZY, ABC
-
-        # list of column names, and mixed case SELECT keyword
-        Select AA,BB,CC from Sys.dual
-
-        # multiple tables
-        Select A, B, C from Sys.dual, Table2
-
-        # invalid SELECT keyword - should fail
-        Xelect A, B, C from Sys.dual
-
-        # incomplete command - should fail
-        Select
-
-        # invalid column name - should fail
-        Select ^^^ frox Sys.dual
-
-        """
-    )
-
-    pyparsing_common.number.runTests(
-        """
-        100
-        -100
-        +100
-        3.14159
-        6.02e23
-        1e-12
-        """
-    )
-
-    # any int or real number, returned as float
-    pyparsing_common.fnumber.runTests(
-        """
-        100
-        -100
-        +100
-        3.14159
-        6.02e23
-        1e-12
-        """
-    )
-
-    pyparsing_common.hex_integer.runTests(
-        """
-        100
-        FF
-        """
-    )
-
-    import uuid
-
-    pyparsing_common.uuid.setParseAction(tokenMap(uuid.UUID))
-    pyparsing_common.uuid.runTests(
-        """
-        12345678-1234-5678-1234-567812345678
-        """
-    )

_service:tar_scm:pyparsing-3.0.9.tar.gz/update_pyparsing_timestamp.py Deleted

_service:tar_scm:pyparsing-3.0.9.tar.gz/CHANGES -> _service:tar_scm:pyparsing-3.1.1.tar.gz/CHANGES Changed

@@ -2,8 +2,246 @@
 Change Log
 ==========
 
-Version 3.0.9 -
----------------
+NOTE: In the future release 3.2.0, use of many of the pre-PEP8 methods (such as
+`ParserElement.parseString`) will start to raise `DeprecationWarnings`. 3.2.0 should
+get released some time later in 2023. I currently plan to completely
+drop the pre-PEP8 methods in pyparsing 4.0, though we won't see that release until
+at least late 2023 if not 2024. So there is plenty of time to convert existing parsers to
+the new function names before the old functions are completely removed. (Big
+help from Devin J. Pohly in structuring the code to enable this peaceful transition.)
+
+Version 3.2.0 will also discontinue support for Python versions 3.6 and 3.7.
+
+
+Version 3.1.1 - July, 2023
+--------------------------
+- Fixed regression in Word(min), reported by Ricardo Coccioli, good catch! (Issue #502)
+
+- Fixed bug in bad exception messages raised by Forward expressions. PR submitted
+  by Kyle Sunden, thanks for your patience and collaboration on this (#493).
+
+- Fixed regression in SkipTo, where ignored expressions were not checked when looking
+  for the target expression. Reported by catcombo, Issue #500.
+
+- Fixed type annotation for enable_packrat, PR submitted by Mike Urbach, thanks! (Issue #498)
+
+- Some general internal code cleanup. (Instigated by Michal Čihař, Issue #488)
+
+
+Version 3.1.0 - June, 2023
+--------------------------
+- Added `tag_emitter.py` to examples. This example demonstrates how to insert
+  tags into your parsed results that are not part of the original parsed text.
+
+
+Version 3.1.0b2 - May, 2023
+---------------------------
+- Updated `create_diagram()` code to be compatible with railroad-diagrams package
+  version 3.0. Fixes Issue #477 (railroad diagrams generated with black bars),
+  reported by Sam Morley-Short.
+
+- Fixed bug in `NotAny`, where parse actions on the negated expr were not being run.
+  This could cause `NotAny` to incorrectly fail if the expr would normally match,
+  but would fail to match if a condition used as a parse action returned False.
+  Fixes Issue #482, raised by byaka, thank you!
+
+- Fixed `create_diagram()` to accept keyword args, to be passed through to the
+  `template.render()` method to generate the output HTML (PR submitted by Aussie Schnore,
+  good catch!)
+
+- Fixed bug in `python_quoted_string` regex.
+
+- Added `examples/bf.py` Brainf*ck parser/executor example. Illustrates using
+  a pyparsing grammar to parse language syntax, and attach executable AST nodes to
+  the parsed results.
+
+
+Version 3.1.0b1 - April, 2023
+-----------------------------
+- Added support for Python 3.12.
+
+- API CHANGE: A slight change has been implemented when unquoting a quoted string
+  parsed using the `QuotedString` class. Formerly, when unquoting and processing
+  whitespace markers such as \t and \n, these substitutions would occur first, and
+  then any additional '\' escaping would be done on the resulting string. This would
+  parse "\\n" as "\<newline>". Now escapes and whitespace markers are all processed
+  in a single pass working left to right, so the quoted string "\\n" would get unquoted
+  to "\n" (a backslash followed by "n"). Fixes issue #474 raised by jakeanq,
+  thanks!
+
+- Added named field "url" to `pyparsing.common.url`, returning the entire
+  parsed URL string.
+
+- Fixed bug when parse actions returned an empty string for an expression that
+  had a results name, that the results name was not saved. That is:
+
+      expr = Literal("X").add_parse_action(lambda tokens: "")("value")
+      result = expr.parse_string("X")
+      print(result"value")
+
+  would raise a `KeyError`. Now empty strings will be saved with the associated
+  results name. Raised in Issue #470 by Nicco Kunzmann, thank you.
+
+- Fixed bug in `SkipTo` where ignore expressions were not properly handled while
+  scanning for the target expression. Issue #475, reported by elkniwt, thanks
+  (this bug has been there for a looooong time!).
+
+- Updated `ci.yml` permissions to limit default access to source - submitted by Joyce
+  Brum of Google. Thanks so much!
+
+- Updated the `lucene_grammar.py` example (better support for '*' and '?' wildcards)
+  and corrected the test cases - brought to my attention by Elijah Nicol, good catch!
+
+
+Version 3.1.0a1 - March, 2023
+-----------------------------
+- API ENHANCEMENT: `Optional(expr)` may now be written as `expr | ""`
+
+  This will make this code:
+
+      "{" + Optional(Literal("A") | Literal("a")) + "}"
+
+  writable as:
+
+      "{" + (Literal("A") | Literal("a") | "") + "}"
+
+  Some related changes implemented as part of this work:
+  - `Literal("")` now internally generates an `Empty()` (and no longer raises an exception)
+  - `Empty` is now a subclass of `Literal`
+
+  Suggested by Antony Lee (issue #412), PR (#413) by Devin J. Pohly.
+
+- Added new class property `identifier` to all Unicode set classes in `pyparsing.unicode`,
+  using the class's values for `cls.identchars` and `cls.identbodychars`. Now Unicode-aware
+  parsers that formerly wrote:
+
+      ppu = pyparsing.unicode
+      ident = Word(ppu.Greek.identchars, ppu.Greek.identbodychars)
+
+  can now write:
+
+      ident = ppu.Greek.identifier
+      # or
+      # ident = ppu.Ελληνικά.identifier
+
+- `ParseResults` now has a new method `deepcopy()`, in addition to the current
+  `copy()` method. `copy()` only makes a shallow copy - any contained `ParseResults`
+  are copied as references - changes in the copy will be seen as changes in the original.
+  In many cases, a shallow copy is sufficient, but some applications require a deep copy.
+  `deepcopy()` makes a deeper copy: any contained `ParseResults` or other mappings or
+  containers are built with copies from the original, and do not get changed if the
+  original is later changed. Addresses issue #463, reported by Bryn Pickering.
+
+- Reworked `delimited_list` function into the new `DelimitedList` class.
+  `DelimitedList` has the same constructor interface as `delimited_list`, and
+  in this release, `delimited_list` changes from a function to a synonym for
+  `DelimitedList`. `delimited_list` and the older `delimitedList` method will be
+  deprecated in a future release, in favor of `DelimitedList`.
+
+- Error messages from `MatchFirst` and `Or` expressions will try to give more details
+  if one of the alternatives matches better than the others, but still fails.
+  Question raised in Issue #464 by msdemlei, thanks!
+
+- Added new class method `ParserElement.using_each`, to simplify code
+  that creates a sequence of `Literals`, `Keywords`, or other `ParserElement`
+  subclasses.
+
+  For instance, to define suppressible punctuation, you would previously
+  write:
+
+      LPAR, RPAR, LBRACE, RBRACE, SEMI = map(Suppress, "(){};")
+
+  You can now write:
+
+      LPAR, RPAR, LBRACE, RBRACE, SEMI = Suppress.using_each("(){};")
+
+  `using_each` will also accept optional keyword args, which it will
+  pass through to the class initializer. Here is an expression for
+  single-letter variable names that might be used in an algebraic
+  expression:
+
+      algebra_var = MatchFirst(
+          Char.using_each(string.ascii_lowercase, as_keyword=True)
+      )
+
+- Added new builtin `python_quoted_string`, which will match any form
+  of single-line or multiline quoted strings defined in Python. (Inspired
+  by discussion with Andreas Schörgenhumer in Issue #421.)
+
+- Extended `expr` notation for repetition of `expr` to accept a
+  slice, where the slice's stop value indicates a `stop_on`
+  expression:
+
+      test = "BEGIN aaa bbb ccc END"
+      BEGIN, END = Keyword.using_each("BEGIN END".split())
+      body_word = Word(alphas)
+
+      expr = BEGIN + Group(body_word...:END) + END
+      # equivalent to
+      # expr = BEGIN + Group(ZeroOrMore(body_word, stop_on=END)) + END
+
+      print(expr.parse_string(test))
+
+  Prints:
+
+      'BEGIN', 'aaa', 'bbb', 'ccc', 'END'
+
+- `ParserElement.validate()` is deprecated. It predates the support for left-recursive
+  parsers, and was prone to false positives (warning that a grammar was invalid when
+  it was in fact valid).  It will be removed in a future pyparsing release. In its
+  place, developers should use debugging and analytical tools, such as `ParserElement.set_debug()`
+  and `ParserElement.create_diagram()`.
+  (Raised in Issue #444, thanks Andrea Micheli!)
+
+- Added bool `embed` argument to `ParserElement.create_diagram()`.
+  When passed as True, the resulting diagram will omit the `<DOCTYPE>`,
+  `<HEAD>`, and `<BODY>` tags so that it can be embedded in other
+  HTML source. (Useful when embedding a call to `create_diagram()` in
+  a PyScript HTML page.)
+
+- Added `recurse` argument to `ParserElement.set_debug` to set the
+  debug flag on an expression and all of its sub-expressions. Requested
+  by multimeric in Issue #399.
+
+- Added '·' (Unicode MIDDLE DOT) to the set of Latin1.identbodychars.
+
+- Fixed bug in `Word` when `max=2`. Also added performance enhancement
+  when specifying `exact` argument. Reported in issue #409 by
+  panda-34, nice catch!
+
+- `Word` arguments are now validated if `min` and `max` are both
+  given, that `min` <= `max`; raises `ValueError` if values are invalid.
+
+- Fixed bug in srange, when parsing escaped '/' and '\' inside a
+  range set.
+
+- Fixed exception messages for some `ParserElements` with custom names,
+  which instead showed their contained expression names.
+
+- Fixed bug in pyparsing.common.url, when input URL is not alone
+  on an input line. Fixes Issue #459, reported by David Kennedy.
+
+- Multiple added and corrected type annotations. With much help from
+  Stephen Rosen, thanks!
+
+- Some documentation and error message clarifications on pyparsing's
+  keyword logic, cited by Basil Peace.
+
+- General docstring cleanup for Sphinx doc generation, PRs submitted
+  by Devin J. Pohly. A dirty job, but someone has to do it - much
+  appreciated!
+
+- `invRegex.py` example renamed to `inv_regex.py` and updated to PEP-8
+  variable and method naming. PR submitted by Ross J. Duff, thanks!
+
+- Removed examples `sparser.py` and `pymicko.py`, since each included its
+  own GPL license in the header. Since this conflicts with pyparsing's
+  MIT license, they were removed from the distribution to avoid
+  confusion among those making use of them in their own projects.
+
+
+Version 3.0.9 - May, 2022
+-------------------------
 - Added Unicode set `BasicMultilingualPlane` (may also be referenced
   as `BMP`) representing the Basic Multilingual Plane (Unicode
   characters up to code point 65535). Can be used to parse
@@ -12,7 +250,7 @@
 
 - To address mypy confusion of `pyparsing.Optional` and `typing.Optional`
   resulting in `error: "_SpecialForm" not callable` message
-  reported in issue #365, fixed the import in exceptions.py. Nice
+  reported in issue #365, fixed the import in `exceptions.py`. Nice
   sleuthing by Iwan Aucamp and Dominic Davis-Foster, thank you!
   (Removed definitions of `OptionalType`, `DictType`, and `IterableType`
   and replaced them with `typing.Optional`, `typing.Dict`, and
@@ -24,13 +262,13 @@
 - Removed use of deprecated `pkg_resources` package in
   railroad diagramming code (issue #391).
 
-- Updated bigquery_view_parser.py example to parse examples at
+- Updated `bigquery_view_parser.py` example to parse examples at
   https://cloud.google.com/bigquery/docs/reference/legacy-sql
 
 
-Version 3.0.8 -
----------------
-- API CHANGE: modified pyproject.toml to require Python version
+Version 3.0.8 - April, 2022
+---------------------------
+- API CHANGE: modified `pyproject.toml` to require Python version
   3.6.8 or later for pyparsing 3.x. Earlier minor versions of 3.6
   fail in evaluating the `version_info` class (implemented using
   `typing.NamedTuple`). If you are using an earlier version of Python
@@ -39,7 +277,7 @@
 - Improved pyparsing import time by deferring regex pattern compiles.
   PR submitted by Anthony Sottile to fix issue #362, thanks!
 
-- Updated build to use flit, PR by Michał Górny, added BUILDING.md
+- Updated build to use flit, PR by Michał Górny, added `BUILDING.md`
   doc and removed old Windows build scripts - nice cleanup work!
 
 - More type-hinting added for all arithmetic and logical operator
@@ -65,8 +303,8 @@
   Serhiy Storchaka, thank you.
 
 
-Version 3.0.7 -
----------------
+Version 3.0.7 - January, 2022
+-----------------------------
 - Fixed bug #345, in which delimitedList changed expressions in place
   using `expr.streamline()`. Reported by Kim Gräsman, thanks!
 
@@ -130,8 +368,8 @@
 - Additional type annotations on public methods.
 
 
-Version 3.0.6 -
----------------
+Version 3.0.6 - November, 2021
+------------------------------
 - Added `suppress_warning()` method to individually suppress a warning on a
   specific ParserElement. Used to refactor `original_text_for` to preserve
   internal results names, which, while undocumented, had been adopted by
@@ -141,8 +379,8 @@
   parse expression.
 
 
-Version 3.0.5 -
----------------
+Version 3.0.5 - November, 2021
+------------------------------
 - Added return type annotations for `col`, `line`, and `lineno`.
 
 - Fixed bug when `warn_ungrouped_named_tokens_in_collection` warning was raised
@@ -157,8 +395,8 @@
   minor bug where separating line was not included after a test failure.
 
 
-Version 3.0.4 -
----------------
+Version 3.0.4 - October, 2021
+-----------------------------
 - Fixed bug in which `Dict` classes did not correctly return tokens as nested
   `ParseResults`, reported by and fix identified by Bu Sun Kim, many thanks!!!
 
@@ -186,8 +424,8 @@
   elements.
 
 
-Version 3.0.3 -
----------------
+Version 3.0.3 - October, 2021
+-----------------------------
 - Fixed regex typo in `one_of` fix for `as_keyword=True`.
 
 - Fixed a whitespace-skipping bug, Issue #319, introduced as part of the revert
@@ -198,8 +436,8 @@
   are longer than others.
 
 
-Version 3.0.2 -
----------------
+Version 3.0.2 - October, 2021
+-----------------------------
 - Reverted change in behavior with `LineStart` and `StringStart`, which changed the
   interpretation of when and how `LineStart` and `StringStart` should match when
   a line starts with spaces. In 3.0.0, the `xxxStart` expressions were not
@@ -233,8 +471,8 @@
   the `IndentedBlock` with `grouped=False`.
 
 
-Version 3.0.1 -
----------------
+Version 3.0.1 - October, 2021
+-----------------------------
 - Fixed bug where `Word(max=n)` did not match word groups less than length 'n'.
   Thanks to Joachim Metz for catching this!
 
@@ -245,15 +483,15 @@
   even when not enabled.
 
 
-Version 3.0.0 -
----------------
+Version 3.0.0 - October, 2021
+-----------------------------
 - A consolidated list of all the changes in the 3.0.0 release can be found in
   `docs/whats_new_in_3_0_0.rst`.
   (https://github.com/pyparsing/pyparsing/blob/master/docs/whats_new_in_3_0_0.rst)
 
 
-Version 3.0.0.final -
----------------------
+Version 3.0.0.final - October, 2021
+-----------------------------------
 - Added support for python `-W` warning option to call `enable_all_warnings`() at startup.
   Also detects setting of `PYPARSINGENABLEALLWARNINGS` environment variable to any non-blank
   value. (If using `-Wd` for testing, but wishing to disable pyparsing warnings, add
@@ -290,8 +528,8 @@
   `a` will get named "a", while `b` will keep its name "bbb".
 
 
-Version 3.0.0rc2 -
-------------------
+Version 3.0.0rc2 - October, 2021
+--------------------------------
 - Added `url` expression to `pyparsing_common`. (Sample code posted by Wolfgang Fahl,
   very nice!)
 
@@ -904,8 +1142,8 @@
   a few.
 
 
-Version 2.4.7 - March, 2020 (April, actually)
----------------------------------------------
+Version 2.4.7 - April, 2020
+---------------------------
 - Backport of selected fixes from 3.0.0 work:
   . Each bug with Regex expressions
   . And expressions not properly constructing with generator

_service:tar_scm:pyparsing-3.0.9.tar.gz/CONTRIBUTING.md -> _service:tar_scm:pyparsing-3.1.1.tar.gz/CONTRIBUTING.md Changed

@@ -34,6 +34,45 @@
   other open and closed issues. Or post your question on SO or reddit. But don't wait until you are desperate and
   frustrated - just ask! :)
 
+## Submitting examples
+
+If you have an example you wish to submit, please follow these guidelines.
+
+- **License - Submitted example code must be available for distribution with the rest of pyparsing under the MIT 
+  open source license.**
+
+- Please follow PEP8 name and coding guidelines, and use the black formatter
+  to auto-format code. 
+
+- Examples should import pyparsing and the common namespace classes as:
+
+      import pyparsing as pp
+      # if necessary
+      ppc = pp.pyparsing_common
+      ppu = pp.pyparsing_unicode
+
+- Submitted examples *must* be Python 3.6.8 or later compatible. (It is acceptable if examples use Python
+  features added after 3.6)
+
+- Where possible use operators to create composite parse expressions:
+
+      expr = expr_a + expr_b | expr_c
+
+  instead of:
+
+      expr = pp.MatchFirst(pp.And(expr_a, expr_b), expr_c)
+
+  Exception: if using a generator to create an expression:
+
+      import keyword
+      python_keywords = keyword.kwlist
+      any_keyword = pp.MatchFirst(pp.Keyword(kw)
+                                  for kw in python_keywords))
+
+- Learn Common Pitfalls When Writing Parsers(https://github.com/pyparsing/pyparsing/wiki/Common-Pitfalls-When-Writing-Parsers) and
+  how to avoid them when developing new examples.
+
+- See additional notes under Some Coding Points(#some-coding-points).
 
 ## Submitting changes
 
@@ -73,10 +112,6 @@
   applications - DO NOT MODIFY OR REMOVE THESE NAMES.
   See more information at the PEP8 wiki page(https://github.com/pyparsing/pyparsing/wiki/PEP-8-planning).
 
-  If you wish to submit a new example, please follow PEP8 name and coding guidelines, and use the black formatter
-  to auto-format code. Example code must be available for distribution with the rest of pyparsing under the MIT 
-  open source license.
-
 - No backslashes for line continuations.
   Continuation lines for expressions in ()'s should start with the continuing operator:
 
@@ -94,33 +129,6 @@
 - List, tuple, and dict literals should include a trailing comma after the last element, which reduces changeset
   clutter when another element gets added to the end.
 
-- Examples should import pyparsing and the common namespace classes as:
-
-      import pyparsing as pp
-      # if necessary
-      ppc = pp.pyparsing_common
-      ppu = pp.pyparsing_unicode
-
-  Submitted examples *must* be Python 3.6.8 or later compatible.
-
-- Where possible use operators to create composite parse expressions:
-
-      expr = expr_a + expr_b | expr_c
-
-  instead of:
-
-      expr = pp.MatchFirst(pp.And(expr_a, expr_b), expr_c)
-
-  Exception: if using a generator to create an expression:
-
-      import keyword
-      python_keywords = keyword.kwlist
-      any_keyword = pp.MatchFirst(pp.Keyword(kw)
-                                  for kw in python_keywords))
-
-- Learn Common Pitfalls When Writing Parsers(https://github.com/pyparsing/pyparsing/wiki/Common-Pitfalls-When-Writing-Parsers) and
-  how to avoid them when developing new examples.
-
 - New features should be accompanied by updates to unitTests.py and a bullet in the CHANGES file.
 
 - Do not modify pyparsing_archive.py. This file is kept as a reference artifact from when pyparsing was distributed

_service:tar_scm:pyparsing-3.0.9.tar.gz/PKG-INFO -> _service:tar_scm:pyparsing-3.1.1.tar.gz/PKG-INFO Changed

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: pyparsing
-Version: 3.0.9
+Version: 3.1.1
 Summary: pyparsing module - Classes and methods to define and execute parsing grammars
 Author-email: Paul McGuire <ptmcg.gm+pyparsing@gmail.com>
 Requires-Python: >=3.6.8
@@ -17,9 +17,13 @@
 Classifier: Programming Language :: Python :: 3.8
 Classifier: Programming Language :: Python :: 3.9
 Classifier: Programming Language :: Python :: 3.10
+Classifier: Programming Language :: Python :: 3.11
+Classifier: Programming Language :: Python :: 3.12
 Classifier: Programming Language :: Python :: 3 :: Only
 Classifier: Programming Language :: Python :: Implementation :: CPython
 Classifier: Programming Language :: Python :: Implementation :: PyPy
+Classifier: Topic :: Software Development :: Compilers
+Classifier: Topic :: Text Processing
 Classifier: Typing :: Typed
 Requires-Dist: railroad-diagrams ; extra == "diagrams"
 Requires-Dist: jinja2 ; extra == "diagrams"
@@ -29,7 +33,7 @@
 PyParsing -- A Python Parsing Module
 ====================================
 
-|Build Status| |Coverage|
+|Version| |Build Status| |Coverage| |License| |Python Versions| |Snyk Score|
 
 Introduction
 ============
@@ -91,7 +95,7 @@
 License
 =======
 
-MIT License. See header of the `pyparsing.py <https://github.com/pyparsing/pyparsing/blob/master/pyparsing/__init__.py#L1-L23>`__ file.
+MIT License. See header of the `pyparsing __init__.py <https://github.com/pyparsing/pyparsing/blob/master/pyparsing/__init__.py#L1-L23>`__ file.
 
 History
 =======
@@ -100,6 +104,23 @@
 
 .. |Build Status| image:: https://github.com/pyparsing/pyparsing/actions/workflows/ci.yml/badge.svg
    :target: https://github.com/pyparsing/pyparsing/actions/workflows/ci.yml
+
 .. |Coverage| image:: https://codecov.io/gh/pyparsing/pyparsing/branch/master/graph/badge.svg
   :target: https://codecov.io/gh/pyparsing/pyparsing
 
+.. |Version| image:: https://img.shields.io/pypi/v/pyparsing?style=flat-square
+    :target: https://pypi.org/project/pyparsing/
+    :alt: Version
+
+.. |License| image:: https://img.shields.io/pypi/l/pyparsing.svg?style=flat-square
+    :target: https://pypi.org/project/pyparsing/
+    :alt: License
+
+.. |Python Versions| image:: https://img.shields.io/pypi/pyversions/pyparsing.svg?style=flat-square
+    :target: https://pypi.org/project/python-liquid/
+    :alt: Python versions
+
+.. |Snyk Score| image:: https://snyk.io//advisor/python/pyparsing/badge.svg
+   :target: https://snyk.io//advisor/python/pyparsing
+   :alt: pyparsing
+

_service:tar_scm:pyparsing-3.0.9.tar.gz/README.rst -> _service:tar_scm:pyparsing-3.1.1.tar.gz/README.rst Changed

@@ -1,7 +1,7 @@
 PyParsing -- A Python Parsing Module
 ====================================
 
-|Build Status| |Coverage|
+|Version| |Build Status| |Coverage| |License| |Python Versions| |Snyk Score|
 
 Introduction
 ============
@@ -63,7 +63,7 @@
 License
 =======
 
-MIT License. See header of the `pyparsing.py <https://github.com/pyparsing/pyparsing/blob/master/pyparsing/__init__.py#L1-L23>`__ file.
+MIT License. See header of the `pyparsing __init__.py <https://github.com/pyparsing/pyparsing/blob/master/pyparsing/__init__.py#L1-L23>`__ file.
 
 History
 =======
@@ -72,5 +72,22 @@
 
 .. |Build Status| image:: https://github.com/pyparsing/pyparsing/actions/workflows/ci.yml/badge.svg
    :target: https://github.com/pyparsing/pyparsing/actions/workflows/ci.yml
+
 .. |Coverage| image:: https://codecov.io/gh/pyparsing/pyparsing/branch/master/graph/badge.svg
   :target: https://codecov.io/gh/pyparsing/pyparsing
+
+.. |Version| image:: https://img.shields.io/pypi/v/pyparsing?style=flat-square
+    :target: https://pypi.org/project/pyparsing/
+    :alt: Version
+
+.. |License| image:: https://img.shields.io/pypi/l/pyparsing.svg?style=flat-square
+    :target: https://pypi.org/project/pyparsing/
+    :alt: License
+
+.. |Python Versions| image:: https://img.shields.io/pypi/pyversions/pyparsing.svg?style=flat-square
+    :target: https://pypi.org/project/python-liquid/
+    :alt: Python versions
+
+.. |Snyk Score| image:: https://snyk.io//advisor/python/pyparsing/badge.svg
+   :target: https://snyk.io//advisor/python/pyparsing
+   :alt: pyparsing

_service:tar_scm:pyparsing-3.0.9.tar.gz/docs/HowToUsePyparsing.rst -> _service:tar_scm:pyparsing-3.1.1.tar.gz/docs/HowToUsePyparsing.rst Changed

@@ -5,10 +5,10 @@
 :author: Paul McGuire
 :address: ptmcg.pm+pyparsing@gmail.com
 
-:revision: 3.0.0
-:date: October, 2021
+:revision: 3.1.0
+:date: April, 2023
 
-:copyright: Copyright |copy| 2003-2022 Paul McGuire.
+:copyright: Copyright |copy| 2003-2023 Paul McGuire.
 
 .. |copy| unicode:: 0xA9
 
@@ -36,7 +36,7 @@
 **Note**: *In pyparsing 3.0, many method and function names which were
 originally written using camelCase have been converted to PEP8-compatible
 snake_case. So ``parseString()`` is being renamed to ``parse_string()``,
-``delimitedList`` to ``delimited_list``, and so on. You may see the old
+``delimitedList`` to DelimitedList_, and so on. You may see the old
 names in legacy parsers, and they will be supported for a time with
 synonyms, but the synonyms will be removed in a future release.*
 
@@ -182,7 +182,7 @@
   - ``expr... ,n`` is equivalent to ``expr*(0, n)``
     (read as "0 to n instances of expr")
 
-  - ``expr...`` and ``expr0, ...`` are equivalent to ``ZeroOrMore(expr)``
+  - ``expr...``, ``expr0, ...`` and ``expr * ...`` are equivalent to ``ZeroOrMore(expr)``
 
   - ``expr1, ...`` is equivalent to ``OneOrMore(expr)``
 
@@ -192,6 +192,11 @@
   occurrences.  If this behavior is desired, then write
   ``expr..., n + ~expr``.
 
+- ```` notation will also accept a stop expression using ':' slice
+  notation:
+
+  - ``expr...:end_expr`` is equivalent to ``ZeroOrMore(expr, stop_on=end_expr)``
+
 - MatchFirst_ expressions are matched left-to-right, and the first
   match found will skip all later expressions within, so be sure
   to define less-specific patterns after more-specific patterns.
@@ -229,7 +234,7 @@
 - Punctuation may be significant for matching, but is rarely of
   much interest in the parsed results.  Use the ``suppress()`` method
   to keep these tokens from cluttering up your returned lists of
-  tokens.  For example, ``delimited_list()`` matches a succession of
+  tokens.  For example, DelimitedList_ matches a succession of
   one or more expressions, separated by delimiters (commas by
   default), but only returns a list of the actual expressions -
   the delimiters are used for parsing, but are suppressed from the
@@ -263,6 +268,9 @@
 Classes
 =======
 
+All the pyparsing classes can be found in this
+`UML class diagram <_static/pyparsingClassDiagram_3.0.9.jpg>`_.
+
 Classes in the pyparsing module
 -------------------------------
 
@@ -348,10 +356,12 @@
         ^
     FAIL: Expected numeric digits, found end of text  (at char 4), (line:1, col:5)
 
+.. _set_results_name:
+
 - ``set_results_name(string, list_all_matches=False)`` - name to be given
   to tokens matching
   the element; if multiple tokens within
-  a repetition group (such as ``ZeroOrMore`` or ``delimited_list``) the
+  a repetition group (such as ZeroOrMore_ or DelimitedList_) the
   default is to return only the last matching token - if ``list_all_matches``
   is set to True, then a list of all the matching tokens is returned.
 
@@ -449,11 +459,13 @@
   repeatedly to specify multiple expressions; useful to specify
   patterns of comment syntax, for example
 
-- ``set_debug(debug_flag=True)`` - function to enable/disable tracing output
+- ``set_debug(flag=True)`` - function to enable/disable tracing output
   when trying to match this element
 
 - ``validate()`` - function to verify that the defined grammar does not
-  contain infinitely recursive constructs
+  contain infinitely recursive constructs (``validate()`` is deprecated, and
+  will be removed in a future pyparsing release. Pyparsing now supports
+  left-recursive parsers, which this function attempted to catch.)
 
 .. _parse_with_tabs:
 
@@ -495,7 +507,7 @@
   defined keyword
 
 - ``CaselessKeyword`` - similar to Keyword_, but with caseless matching
-  behavior
+  behavior as described in CaselessLiteral_.
 
 .. _Word:
 
@@ -535,16 +547,21 @@
 
   - ``max`` - indicating a maximum length of matching characters
 
-  - ``exact`` - indicating an exact length of matching characters
+  - ``exact`` - indicating an exact length of matching characters;
+    if ``exact`` is specified, it will override any values for ``min`` or ``max``
+
+  - ``as_keyword`` - indicating that preceding and following characters must
+    be whitespace or non-keyword characters
 
-  If ``exact`` is specified, it will override any values for ``min`` or ``max``.
+  - ``exclude_chars`` - a string of characters that should be excluded from
+    init_chars and body_chars
 
-  Sometimes you want to define a word using all
-  characters in a range except for one or two of them; you can do this
-  with the new ``exclude_chars`` argument. This is helpful if you want to define
-  a word with all ``printables`` except for a single delimiter character, such
-  as '.'. Previously, you would have to create a custom string to pass to Word.
-  With this change, you can just create ``Word(printables, exclude_chars='.')``.
+    Sometimes you want to define a word using all
+    characters in a range except for one or two of them; you can do this
+    with the ``exclude_chars`` argument. This is helpful if you want to define
+    a word with all ``printables`` except for a single delimiter character, such
+    as '.'. Previously, you would have to create a custom string to pass to Word.
+    With this change, you can just create ``Word(printables, exclude_chars='.')``.
 
 - ``Char`` - a convenience form of ``Word`` that will match just a single character from
   a string of matching characters::
@@ -680,12 +697,30 @@
   been renamed to ``Opt``. A compatibility synonym ``Optional`` is defined,
   but will be removed in a future release.)
 
+.. _ZeroOrMore:
+
 - ``ZeroOrMore`` - similar to ``Opt``, but can be repeated; ``ZeroOrMore(expr)``
   can also be written as ``expr...``.
 
-- ``OneOrMore`` - similar to ``ZeroOrMore``, but at least one match must
+.. _OneOrMore:
+
+- ``OneOrMore`` - similar to ZeroOrMore_, but at least one match must
   be present; ``OneOrMore(expr)`` can also be written as ``expr1, ...``.
 
+.. _DelimitedList:
+
+- ``DelimitedList`` - used for
+  matching one or more occurrences of ``expr``, separated by ``delim``.
+  By default, the delimiters are suppressed, so the returned results contain
+  only the separate list elements.  Can optionally specify ``combine=True``,
+  indicating that the expressions and delimiters should be returned as one
+  combined value (useful for scoped variables, such as ``"a.b.c"``, or
+  ``"a::b::c"``, or paths such as ``"a/b/c"``). Can also optionally specify ``min` and ``max``
+  restrictions on the length of the list, and
+  ``allow_trailing_delim`` to accept a trailing delimiter at the end of the list.
+
+.. _FollowedBy:
+
 - ``FollowedBy`` - a lookahead expression, requires matching of the given
   expressions, but does not advance the parsing position within the input string
 
@@ -769,7 +804,7 @@
 ------------------
 
 - ``Group`` - causes the matched tokens to be enclosed in a list;
-  useful in repeated elements like ``ZeroOrMore`` and ``OneOrMore`` to
+  useful in repeated elements like ZeroOrMore_ and OneOrMore_ to
   break up matched tokens into groups for each repeated pattern
 
 - ``Dict`` - like ``Group``, but also constructs a dictionary, using the
@@ -813,7 +848,8 @@
           'abc', '100', '200', '300', 'end'
 
       If the ``Group`` is constructed using ``aslist=True``, the resulting tokens
-      will be a Python list instead of a ParseResults_.
+      will be a Python list instead of a ParseResults_. In this case, the returned value will
+      no longer support the extended features or methods of a ParseResults_.
 
   - as a dictionary
 
@@ -825,8 +861,9 @@
       input text - in addition to ParseResults_ listed as ``  a1, b1, c1, ...,  a2, b2, c2, ...  ``
       it also acts as a dictionary with entries defined as ``{ a1 :  b1, c1, ...  }, { a2 :  b2, c2, ...  }``;
       this is especially useful when processing tabular data where the first column contains a key
-      value for that line of data; when constructed with ``aslist=True``, will
-      return an actual Python ``dict`` instead of a ParseResults_.
+      value for that line of data; when constructed with ``asdict=True``, will
+      return an actual Python ``dict`` instead of a ParseResults_. In this case, the returned value will
+      no longer support the extended features or methods of a ParseResults_.
 
     - list elements that are deleted using ``del`` will still be accessible by their
       dictionary keys
@@ -858,6 +895,10 @@
   (The ``pprint`` module is especially good at printing out the nested contents
   given by ``as_list()``.)
 
+  If a ParseResults_ is built with expressions that use results names (see _set_results_name) or
+  using the ``Dict`` class, then those names and values can be extracted as a Python
+  dict using ``as_dict()``.
+
   Finally, ParseResults_ can be viewed by calling ``dump()``. ``dump()`` will first show
   the ``as_list()`` output, followed by an indented structure listing parsed tokens that
   have been assigned results names.
@@ -1009,15 +1050,6 @@
 Helper methods
 --------------
 
-- ``delimited_list(expr, delim=',')`` - convenience function for
-  matching one or more occurrences of expr, separated by delim.
-  By default, the delimiters are suppressed, so the returned results contain
-  only the separate list elements.  Can optionally specify ``combine=True``,
-  indicating that the expressions and delimiters should be returned as one
-  combined value (useful for scoped variables, such as ``"a.b.c"``, or
-  ``"a::b::c"``, or paths such as ``"a/b/c"``). Can also optionally specify
-  ``allow_trailing_delim`` to accept a trailing delimiter at the end of the list.
-
 - ``counted_array(expr)`` - convenience function for a pattern where an list of
   instances of the given expression are preceded by an integer giving the count of
   elements in the list.  Returns an expression that parses the leading integer,
@@ -1247,9 +1279,9 @@
   ``ParseException`` if matching at a different column number; useful when parsing
   tabular data
 
-- ``common.convert_to_integer()`` - converts all matched tokens to uppercase
+- ``common.convert_to_integer()`` - converts all matched tokens to int
 
-- ``common.convert_to_float()`` - converts all matched tokens to uppercase
+- ``common.convert_to_float()`` - converts all matched tokens to float
 
 - ``common.convert_to_date()`` - converts matched token to a datetime.date
 
@@ -1275,6 +1307,19 @@
 
     ÀÁÂÃÄÅÆÇÈÉÊËÌÍÎÏÐÑÒÓÔÕÖØÙÚÛÜÝÞßàáâãäåæçèéêëìíîïðñòóôõöøùúûüýþ
 
+.. _identchars:
+
+- ``identchars`` - a string containing characters that are valid as initial identifier characters::
+
+    ABCDEFGHIJKLMNOPQRSTUVWXYZ_abcdefghijklmnopqrstuvwxyzª
+    µºÀÁÂÃÄÅÆÇÈÉÊËÌÍÎÏÐÑÒÓÔÕÖØÙÚÛÜÝÞßàáâãäåæçèéêëìíîïðñòóôõöøùúûüýþÿ
+
+- ``identbodychars`` - a string containing characters that are valid as identifier body characters (those following a
+  valid leading identifier character as given in identchars_)::
+
+    0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ_abcdefghijklmnopqrstuvwxyzª
+    µ·ºÀÁÂÃÄÅÆÇÈÉÊËÌÍÎÏÐÑÒÓÔÕÖØÙÚÛÜÝÞßàáâãäåæçèéêëìíîïðñòóôõöøùúûüýþÿ
+
 - ``printables`` - same as ``string.printable``, minus the space (``' '``) character
 
 - ``empty`` - a global ``Empty()``; will always match
@@ -1287,13 +1332,15 @@
 
 - ``quoted_string`` - ``sgl_quoted_string | dbl_quoted_string``
 
+- ``python_quoted_string`` - ``quoted_string | multiline quoted string``
+
 - ``c_style_comment`` - a comment block delimited by ``'/*'`` and ``'*/'`` sequences; can span
   multiple lines, but does not support nesting of comments
 
 - ``html_comment`` - a comment block delimited by ``''`` sequences; can span
   multiple lines, but does not support nesting of comments
 
-- ``comma_separated_list`` - similar to ``delimited_list``, except that the
+- ``comma_separated_list`` - similar to DelimitedList_, except that the
   list expressions can be any text value, or a quoted string; quoted strings can
   safely include commas without incorrectly breaking the string into two tokens
 
@@ -1355,21 +1402,21 @@
 --------------------------    -----------------     ------------------------------------------------
 Arabic                        العربية
 Chinese                       中文
+CJK                                                 Union of Chinese, Japanese, and Korean sets
 Cyrillic                      кириллица
+Devanagari                    देवनागरी
 Greek                         Ελληνικά
+Hangul                        Korean, 한국어
 Hebrew                        עִברִית
 Japanese                      日本語                 Union of Kanji, Katakana, and Hiragana sets
+Japanese.Hiragana             ひらがな
 Japanese.Kanji                漢字
 Japanese.Katakana             カタカナ
-Japanese.Hiragana             ひらがな
-Hangul                        Korean, 한국어
 Latin1                                              All Unicode characters up to code point 255
 LatinA
 LatinB
 Thai                          ไทย
-Devanagari                    देवनागरी
 BasicMultilingualPlane        BMP                   All Unicode characters up to code point 65535
-CJK                                                 Union of Chinese, Japanese, and Korean sets
 ==========================    =================     ================================================
 
 The base ``unicode`` class also includes definitions based on all Unicode code points up to ``sys.maxunicode``. This
@@ -1396,13 +1443,31 @@
 
 This will result in the railroad diagram being written to ``street_address_diagram.html``.
 
-Diagrams usually will vertically wrap expressions containing more than 3 terms. You can override this by
-passing the `vertical` argument to `create_diagram` with a larger value.
+`create_diagrams` takes the following arguments:
+
+- ``output_html`` (str or file-like object) - output target for generated diagram HTML
+
+- ``vertical`` (int) - threshold for formatting multiple alternatives vertically instead of horizontally (default=3)
+
+- ``show_results_names`` - bool flag whether diagram should show annotations for defined results names
+
+- ``show_groups`` - bool flag whether groups should be highlighted with an unlabeled surrounding box
+
+- ``embed`` - bool flag whether generated HTML should omit <HEAD>, <BODY>, and <DOCTYPE> tags to embed
+  the resulting HTML in an enclosing HTML source (such as PyScript HTML)
+
+- ``head`` - str containing additional HTML to insert into the <HEAD> section of the generated code;
+  can be used to insert custom CSS styling
+
+- ``body`` - str containing additional HTML to insert at the beginning of the <BODY> section of the
+  generated code
+
 
 Example
 -------
 You can view an example railroad diagram generated from `a pyparsing grammar for
-SQL SELECT statements <_static/sql_railroad.html>`_.
+SQL SELECT statements <_static/sql_railroad.html>`_ (generated from
+`examples/select_parser.py <../examples/select_parser.py>`_).
 
 Naming tip
 ----------

_service:tar_scm:pyparsing-3.1.1.tar.gz/docs/_static/pyparsingClassDiagram_3.0.9.jpg Added

_service:tar_scm:pyparsing-3.0.9.tar.gz/docs/conf.py -> _service:tar_scm:pyparsing-3.1.1.tar.gz/docs/conf.py Changed

_service:tar_scm:pyparsing-3.1.1.tar.gz/docs/make_sphinx_docs.bat Added

_service:tar_scm:pyparsing-3.0.9.tar.gz/docs/pyparsing_class_diagram.puml -> _service:tar_scm:pyparsing-3.1.1.tar.gz/docs/pyparsing_class_diagram.puml Changed

_service:tar_scm:pyparsing-3.0.9.tar.gz/docs/whats_new_in_3_0_0.rst -> _service:tar_scm:pyparsing-3.1.1.tar.gz/docs/whats_new_in_3_0_0.rst Changed

@@ -4,11 +4,11 @@
 
 :author: Paul McGuire
 
-:date: April, 2022
+:date: May, 2022
 
 :abstract: This document summarizes the changes made
     in the 3.0.0 release of pyparsing.
-    (Updated to reflect changes up to 3.0.8)
+    (Updated to reflect changes up to 3.0.10)
 
 .. sectnum::    :depth: 4
 
@@ -62,6 +62,20 @@
     # save as HTML
     parser.create_diagram('parser_rr_diag.html')
 
+``create_diagram`` accepts these named arguments:
+
+- ``vertical`` (int) - threshold for formatting multiple alternatives vertically
+  instead of horizontally (default=3)
+- ``show_results_names`` - bool flag whether diagram should show annotations for
+  defined results names
+- ``show_groups`` - bool flag whether groups should be highlighted with an unlabeled surrounding box
+- ``embed`` - bool flag whether generated HTML should omit ``<HEAD>``, ``<BODY>``, and ``<DOCTYPE>`` tags to embed
+  the resulting HTML in an enclosing HTML source (new in 3.0.10)
+- ``head`` - str containing additional HTML to insert into the ``<HEAD>`` section of the
+  generated code; can be used to insert custom CSS styling
+- ``body`` - str containing additional HTML to insert at the beginning of the ``<BODY>`` section of the
+  generated code
+
 To use this new feature, install the supporting diagramming packages using::
 
     pip install pyparsingdiagrams
@@ -200,7 +214,7 @@
   (**currently not working on PyPy**)
 
 Support for yielding native Python ``list`` and ``dict`` types in place of ``ParseResults``
--------------------------------------------------------------------------------
+-------------------------------------------------------------------------------------------
 To support parsers that are intended to generate native Python collection
 types such as lists and dicts, the ``Group`` and ``Dict`` classes now accept an
 additional boolean keyword argument ``aslist`` and ``asdict`` respectively. See
@@ -226,7 +240,7 @@
 using ``aslist=True``.
 
 New Located class to replace ``locatedExpr`` helper method
-------------------------------------------------------
+----------------------------------------------------------
 The new ``Located`` class will replace the current ``locatedExpr`` method for
 marking parsed results with the start and end locations of the parsed data in
 the input string.  ``locatedExpr`` had several bugs, and returned its results
@@ -279,7 +293,7 @@
 This is a fix to behavior that was added in 3.0.0, but was actually a regression from 2.4.x.
 
 New ``IndentedBlock`` class to replace ``indentedBlock`` helper method
---------------------------------------------------------------
+----------------------------------------------------------------------
 The new ``IndentedBlock`` class will replace the current ``indentedBlock`` method
 for defining indented blocks of text, similar to Python source code. Using
 ``IndentedBlock``, the expression instance itself keeps track of the indent stack,
@@ -392,7 +406,7 @@
   common fields in URLs. See the updated ``urlExtractorNew.py`` file in the
   ``examples`` directory. Submitted by Wolfgang Fahl.
 
-- ``delimited_list`` now supports an additional flag ``allow_trailing_delim``,
+- ``DelimitedList`` now supports an additional flag ``allow_trailing_delim``,
   to optionally parse an additional delimiter at the end of the list.
   Submitted by Kazantcev Andrey.
 
@@ -661,7 +675,8 @@
 cpp_style_comment               cppStyleComment
 dbl_quoted_string               dblQuotedString
 dbl_slash_comment               dblSlashComment
-delimited_list                  delimitedList
+DelimitedList                   delimitedList
+DelimitedList                   delimited_list
 dict_of                         dictOf
 html_comment                    htmlComment
 infix_notation                  infixNotation

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/0README.html -> _service:tar_scm:pyparsing-3.1.1.tar.gz/examples/0README.html Changed

@@ -21,12 +21,12 @@
 </li>
 <p>
 
-<li><a href="holaMundo.py">holaMundo.py</a> <i>~ submission by Marco Alfonso</i><br>
+<li><a href="hola_mundo.py">hola_mundo.py</a> <i>~ submission by Marco Alfonso</i><br>
 "Hello, World!" example translated to Spanish, from Marco Alfonso's blog.
 </li>
 <p>
 
-<li><a href="chemicalFormulas.py">chemicalFormulas.py</a><br>
+<li><a href="chemical_formulas.py">chemical_formulas.py</a><br>
 Simple example to demonstrate the use of ParseResults returned from parseString().
 Parses a chemical formula (such as "H2O" or "C6H5OH"), and walks the returned list of tokens to calculate the molecular weight.
 </li>
@@ -141,17 +141,6 @@
 </li>
 <p>
 
-<li><a href="sparser.py">sparser.py</a> <i>~ submission by Tim Cera</i><br>
-A configurable parser module that can be configured with a list of tuples, giving a high-level definition for parsing common sets
-of water table data files.  Tim had to contend with several different styles of data file formats, each with slight variations of its own.
-Tim created a configurable parser (or "SPECIFIED parser" - hence the name "sparser"), that simply works from a config variable listing
-the field names and data types, and implicitly, their order in the source data file.
-<p>
-See <a href="mayport_florida_8720220_data_def.txt">mayport_florida_8720220_data_def.txt</a> for an
-example configuration file.
-</li>
-<p>
-
 <li><a href="romanNumerals.py">romanNumerals.py</a><br>
 A Roman numeral generator and parser example, showing the power of parse actions
 to compile Roman numerals into their integer values.
@@ -256,26 +245,22 @@
 <p>
 
 <li><a href="builtin_parse_action_demo.py">builtin_parse_action_demo.py</a><br>
-<b>New in version 1.5.7</b><br>
 Demonstration of using builtins (min, max, sum, len, etc.) as parse actions.
 </li>
 <p>
 
 <li><a href="antlr_grammar.py">antlr_grammar.py</a><i>~ submission by Luca DellOlio</i><br>
-<b>New in version 1.5.7</b><br>
 Pyparsing example parsing ANTLR .a files and generating a working pyparsing parser.
 </li>
 <p>
 
 <li><a href="shapes.py">shapes.py</a><br>
-<b>New in version 1.5.7</b><br>
 Parse actions example simple shape definition syntax, and returning the matched tokens as
 domain objects instead of just strings.
 </li>
 <p>
 
 <li><a href="datetimeParseActions.py">datetimeParseActions.py</a><br>
-<b>New in version 1.5.7</b><br>
 Parse actions example showing a parse action returning a datetime object instead of
 string tokens, and doing validation of the tokens, raising a ParseException if the
 given YYYY/MM/DD string does not represent a valid date.
@@ -283,7 +268,6 @@
 <p>
 
 <li><a href="position.py">position.py</a><br>
-<b>New in version 1.5.7</b><br>
 Demonstration of a couple of different ways to capture the location a particular
 expression was found within the overall input string.
 </li>

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/adventureEngine.py -> _service:tar_scm:pyparsing-3.1.1.tar.gz/examples/adventureEngine.py Changed

@@ -2,39 +2,44 @@
 # Copyright 2005-2006, Paul McGuire
 #
 # Updated 2012 - latest pyparsing API
+# Updated 2023 - using PEP8 API names
 #
 
-from pyparsing import *
+import pyparsing as pp
 import random
 import string
 
 
-def aOrAn(item):
-    if item.desc0 in "aeiou":
+def a_or_an(item):
+    if item.desc.startswith(tuple("aeiou")):
         return "an " + item.desc
     else:
         return "a " + item.desc
 
-
-def enumerateItems(l):
-    if len(l) == 0:
+def enumerate_items(items_list):
+    if not items_list:
         return "nothing"
+    *all_but_last, last = items_list
     out = 
-    if len(l) > 1:
-        out.append(", ".join(aOrAn(item) for item in l:-1))
+    if all_but_last:
+        out.append(", ".join(a_or_an(item) for item in all_but_last))
+        if len(all_but_last) > 1:
+            out-1 += ','
         out.append("and")
-    out.append(aOrAn(l-1))
+    out.append(a_or_an(last))
     return " ".join(out)
 
-
-def enumerateDoors(l):
-    if len(l) == 0:
+def enumerate_doors(doors_list):
+    if not doors_list:
         return ""
+    *all_but_last, last = doors_list
     out = 
-    if len(l) > 1:
-        out.append(", ".join(l:-1))
+    if all_but_last:
+        out.append(", ".join(all_but_last))
+        if len(all_but_last) > 1:
+            out-1 += ','
         out.append("and")
-    out.append(l-1)
+    out.append(last)
     return " ".join(out)
 
 
@@ -57,10 +62,10 @@
         if self.gameOver:
             player.gameOver = True
 
-    def addItem(self, it):
+    def add_item(self, it):
         self.inv.append(it)
 
-    def removeItem(self, it):
+    def remove_item(self, it):
         self.inv.remove(it)
 
     def describe(self):
@@ -71,9 +76,9 @@
                 is_form = "are"
             else:
                 is_form = "is"
-            print("There {} {} here.".format(is_form, enumerateItems(visibleItems)))
+            print("There {} {} here.".format(is_form, enumerate_items(visibleItems)))
         else:
-            print("You see %s." % (enumerateItems(visibleItems)))
+            print("You see %s." % (enumerate_items(visibleItems)))
 
 
 class Exit(Room):
@@ -135,16 +140,16 @@
         else:
             self.contents = 
 
-    def openItem(self, player):
+    def open_item(self, player):
         if not self.isOpened:
             self.isOpened = not self.isOpened
             if self.contents is not None:
                 for item in self.contents:
-                    player.room.addItem(item)
+                    player.room.add_item(item)
                 self.contents = 
             self.desc = "open " + self.desc
 
-    def closeItem(self, player):
+    def close_item(self, player):
         if self.isOpened:
             self.isOpened = not self.isOpened
             if self.desc.startswith("open "):
@@ -159,15 +164,15 @@
         self.verbProg = verbProg
 
     @staticmethod
-    def helpDescription():
+    def help_description():
         return ""
 
-    def _doCommand(self, player):
+    def _do_command(self, player):
         pass
 
     def __call__(self, player):
         print(self.verbProg.capitalize() + "...")
-        self._doCommand(player)
+        self._do_command(player)
 
 
 class MoveCommand(Command):
@@ -176,11 +181,11 @@
         self.direction = quals.direction0
 
     @staticmethod
-    def helpDescription():
+    def help_description():
         return """MOVE or GO - go NORTH, SOUTH, EAST, or WEST
           (can abbreviate as 'GO N' and 'GO W', or even just 'E' and 'S')"""
 
-    def _doCommand(self, player):
+    def _do_command(self, player):
         rm = player.room
         nextRoom = rm.doors
             {
@@ -202,15 +207,15 @@
         self.subject = quals.item
 
     @staticmethod
-    def helpDescription():
+    def help_description():
         return "TAKE or PICKUP or PICK UP - pick up an object (but some are deadly)"
 
-    def _doCommand(self, player):
+    def _do_command(self, player):
         rm = player.room
         subj = Item.itemsself.subject
         if subj in rm.inv and subj.isVisible:
             if subj.isTakeable:
-                rm.removeItem(subj)
+                rm.remove_item(subj)
                 player.take(subj)
             else:
                 print(subj.cantTakeMessage)
@@ -224,17 +229,17 @@
         self.subject = quals.item
 
     @staticmethod
-    def helpDescription():
+    def help_description():
         return "DROP or LEAVE - drop an object (but fragile items may break)"
 
-    def _doCommand(self, player):
+    def _do_command(self, player):
         rm = player.room
         subj = Item.itemsself.subject
         if subj in player.inv:
-            rm.addItem(subj)
+            rm.add_item(subj)
             player.drop(subj)
         else:
-            print("You don't have %s." % (aOrAn(subj)))
+            print("You don't have %s." % (a_or_an(subj)))
 
 
 class InventoryCommand(Command):
@@ -242,11 +247,11 @@
         super().__init__("INV", "taking inventory")
 
     @staticmethod
-    def helpDescription():
+    def help_description():
         return "INVENTORY or INV or I - lists what items you have"
 
-    def _doCommand(self, player):
-        print("You have %s." % enumerateItems(player.inv))
+    def _do_command(self, player):
+        print("You have %s." % enumerate_items(player.inv))
 
 
 class LookCommand(Command):
@@ -254,24 +259,48 @@
         super().__init__("LOOK", "looking")
 
     @staticmethod
-    def helpDescription():
+    def help_description():
         return "LOOK or L - describes the current room and any objects in it"
 
-    def _doCommand(self, player):
+    def _do_command(self, player):
         player.room.describe()
 
 
+class ExamineCommand(Command):
+    def __init__(self, quals):
+        super().__init__("EXAMINE", "examining")
+        self.subject = Item.itemsquals.item
+
+    @staticmethod
+    def help_description():
+        return "EXAMINE or EX or X - look closely at an object"
+
+    def _do_command(self, player):
+        msg = random.choice(
+            
+                "It's {}.",
+                "It's just {}.",
+                "It's a beautiful {1}.",
+                "It's a rare and beautiful {1}.",
+                "It's a rare {1}.",
+                "Just {}, nothing special...",
+                "{0}, just {0}."
+            
+        )
+        print(msg.format(a_or_an(self.subject), self.subject).capitalize())
+
+
 class DoorsCommand(Command):
     def __init__(self, quals):
         super().__init__("DOORS", "looking for doors")
 
     @staticmethod
-    def helpDescription():
+    def help_description():
         return "DOORS - display what doors are visible from this room"
 
-    def _doCommand(self, player):
+    def _do_command(self, player):
         rm = player.room
-        numDoors = sum(1 for r in rm.doors if r is not None)
+        numDoors = sum(1 for r in rm.doors if r is not None)
         if numDoors == 0:
             reply = "There are no doors in any direction."
         else:
@@ -284,8 +313,7 @@
                 for i, d in enumerate(rm.doors)
                 if d is not None
             
-            # ~ print doorNames
-            reply += enumerateDoors(doorNames)
+            reply += enumerate_doors(doorNames)
             reply += "."
             print(reply)
 
@@ -300,10 +328,10 @@
             self.target = None
 
     @staticmethod
-    def helpDescription():
+    def help_description():
         return "USE or U - use an object, optionally IN or ON another object"
 
-    def _doCommand(self, player):
+    def _do_command(self, player):
         rm = player.room
         availItems = rm.inv + player.inv
         if self.subject in availItems:
@@ -321,16 +349,16 @@
         self.subject = Item.itemsquals.item
 
     @staticmethod
-    def helpDescription():
+    def help_description():
         return "OPEN or O - open an object"
 
-    def _doCommand(self, player):
+    def _do_command(self, player):
         rm = player.room
         availItems = rm.inv + player.inv
         if self.subject in availItems:
             if self.subject.isOpenable:
                 if not self.subject.isOpened:
-                    self.subject.openItem(player)
+                    self.subject.open_item(player)
                 else:
                     print("It's already open.")
             else:
@@ -345,16 +373,16 @@
         self.subject = Item.itemsquals.item
 
     @staticmethod
-    def helpDescription():
+    def help_description():
         return "CLOSE or CL - close an object"
 
-    def _doCommand(self, player):
+    def _do_command(self, player):
         rm = player.room
         availItems = rm.inv + player.inv
         if self.subject in availItems:
             if self.subject.isOpenable:
                 if self.subject.isOpened:
-                    self.subject.closeItem(player)
+                    self.subject.close_item(player)
                 else:
                     print("You can't close that, it's not open.")
             else:
@@ -368,10 +396,10 @@
         super().__init__("QUIT", "quitting")
 
     @staticmethod
-    def helpDescription():
+    def help_description():
         return "QUIT or Q - ends the game"
 
-    def _doCommand(self, player):
+    def _do_command(self, player):
         print("Ok....")
         player.gameOver = True
 
@@ -381,10 +409,10 @@
         super().__init__("HELP", "helping")
 
     @staticmethod
-    def helpDescription():
+    def help_description():
         return "HELP or H or ? - displays this help message"
 
-    def _doCommand(self, player):
+    def _do_command(self, player):
         print("Enter any of the following commands (not case sensitive):")
         for cmd in 
             InventoryCommand,
@@ -395,42 +423,43 @@
             CloseCommand,
             MoveCommand,
             LookCommand,
+            ExamineCommand,
             DoorsCommand,
             QuitCommand,
             HelpCommand,
         :
-            print("  - %s" % cmd.helpDescription())
+            print("  - %s" % cmd.help_description())
         print()
 
 
-class AppParseException(ParseException):
+class AppParseException(pp.ParseException):
     pass
 
 
 class Parser:
     def __init__(self):
-        self.bnf = self.makeBNF()
+        self.bnf = self.make_bnf()
 
-    def makeBNF(self):
-        invVerb = oneOf("INV INVENTORY I", caseless=True)
-        dropVerb = oneOf("DROP LEAVE", caseless=True)
-        takeVerb = oneOf("TAKE PICKUP", caseless=True) | (
-            CaselessLiteral("PICK") + CaselessLiteral("UP")
+    def make_bnf(self):
+        invVerb = pp.one_of("INV INVENTORY I", caseless=True)
+        dropVerb = pp.one_of("DROP LEAVE", caseless=True)
+        takeVerb = pp.one_of("TAKE PICKUP", caseless=True) | (
+            pp.CaselessLiteral("PICK") + pp.CaselessLiteral("UP")
         )
-        moveVerb = oneOf("MOVE GO", caseless=True) | empty
-        useVerb = oneOf("USE U", caseless=True)
-        openVerb = oneOf("OPEN O", caseless=True)
-        closeVerb = oneOf("CLOSE CL", caseless=True)
-        quitVerb = oneOf("QUIT Q", caseless=True)
-        lookVerb = oneOf("LOOK L", caseless=True)
-        doorsVerb = CaselessLiteral("DOORS")
-        helpVerb = oneOf("H HELP ?", caseless=True)
-
-        itemRef = OneOrMore(Word(alphas)).setParseAction(self.validateItemName)
-        nDir = oneOf("N NORTH", caseless=True).setParseAction(replaceWith("N"))
-        sDir = oneOf("S SOUTH", caseless=True).setParseAction(replaceWith("S"))
-        eDir = oneOf("E EAST", caseless=True).setParseAction(replaceWith("E"))
-        wDir = oneOf("W WEST", caseless=True).setParseAction(replaceWith("W"))
+        moveVerb = pp.one_of("MOVE GO", caseless=True) | pp.Empty()
+        useVerb = pp.one_of("USE U", caseless=True)
+        openVerb = pp.one_of("OPEN O", caseless=True)
+        closeVerb = pp.one_of("CLOSE CL", caseless=True)
+        quitVerb = pp.one_of("QUIT Q", caseless=True)
+        lookVerb = pp.one_of("LOOK L", caseless=True)
+        doorsVerb = pp.CaselessLiteral("DOORS")
+        helpVerb = pp.one_of("H HELP ?", caseless=True)
+
+        itemRef = pp.OneOrMore(pp.Word(pp.alphas)).set_parse_action(self.validate_item_name).setName("item_ref")
+        nDir = pp.one_of("N NORTH", caseless=True).set_parse_action(pp.replace_with("N"))
+        sDir = pp.one_of("S SOUTH", caseless=True).set_parse_action(pp.replace_with("S"))
+        eDir = pp.one_of("E EAST", caseless=True).set_parse_action(pp.replace_with("E"))
+        wDir = pp.one_of("W WEST", caseless=True).set_parse_action(pp.replace_with("W"))
         moveDirection = nDir | sDir | eDir | wDir
 
         invCommand = invVerb
@@ -439,32 +468,34 @@
         useCommand = (
             useVerb
             + itemRef("usedObj")
-            + Optional(oneOf("IN ON", caseless=True))
-            + Optional(itemRef, default=None)("targetObj")
+            + pp.Opt(pp.one_of("IN ON", caseless=True))
+            + pp.Opt(itemRef, default=None)("targetObj")
         )
         openCommand = openVerb + itemRef("item")
         closeCommand = closeVerb + itemRef("item")
-        moveCommand = moveVerb + moveDirection("direction")
+        moveCommand = (moveVerb | "") + moveDirection("direction")
         quitCommand = quitVerb
         lookCommand = lookVerb
-        doorsCommand = doorsVerb
+        examineCommand = pp.one_of("EXAMINE EX X", caseless=True) + itemRef("item")
+        doorsCommand = doorsVerb.setName("DOORS")
         helpCommand = helpVerb
 
         # attach command classes to expressions
-        invCommand.setParseAction(InventoryCommand)
-        dropCommand.setParseAction(DropCommand)
-        takeCommand.setParseAction(TakeCommand)
-        useCommand.setParseAction(UseCommand)
-        openCommand.setParseAction(OpenCommand)
-        closeCommand.setParseAction(CloseCommand)
-        moveCommand.setParseAction(MoveCommand)
-        quitCommand.setParseAction(QuitCommand)
-        lookCommand.setParseAction(LookCommand)
-        doorsCommand.setParseAction(DoorsCommand)
-        helpCommand.setParseAction(HelpCommand)
+        invCommand.set_parse_action(InventoryCommand)
+        dropCommand.set_parse_action(DropCommand)
+        takeCommand.set_parse_action(TakeCommand)
+        useCommand.set_parse_action(UseCommand)
+        openCommand.set_parse_action(OpenCommand)
+        closeCommand.set_parse_action(CloseCommand)
+        moveCommand.set_parse_action(MoveCommand)
+        quitCommand.set_parse_action(QuitCommand)
+        lookCommand.set_parse_action(LookCommand)
+        examineCommand.set_parse_action(ExamineCommand)
+        doorsCommand.set_parse_action(DoorsCommand)
+        helpCommand.set_parse_action(HelpCommand)
 
         # define parser using all command expressions
-        return (
+        parser = pp.ungroup(
             invCommand
             | useCommand
             | openCommand
@@ -473,24 +504,27 @@
             | takeCommand
             | moveCommand
             | lookCommand
+            | examineCommand
             | doorsCommand
             | helpCommand
             | quitCommand
-        )("command") + LineEnd()
+        )("command")
 
-    def validateItemName(self, s, l, t):
+        return parser
+
+    def validate_item_name(self, s, l, t):
         iname = " ".join(t)
         if iname not in Item.items:
             raise AppParseException(s, l, "No such item '%s'." % iname)
         return iname
 
-    def parseCmd(self, cmdstr):
+    def parse_cmd(self, cmdstr):
         try:
-            ret = self.bnf.parseString(cmdstr)
+            ret = self.bnf.parse_string(cmdstr)
             return ret
         except AppParseException as pe:
             print(pe.msg)
-        except ParseException as pe:
+        except pp.ParseException as pe:
             print(
                 random.choice(
                     
@@ -595,7 +629,7 @@
 def putItemInRoom(i, r):
     if isinstance(r, str):
         r = roomsr
-    r.addItem(Item.itemsi)
+    r.add_item(Item.itemsi)
 
 
 def playGame(p, startRoom):
@@ -604,98 +638,98 @@
     p.moveTo(startRoom)
     while not p.gameOver:
         cmdstr = input(">> ")
-        cmd = parser.parseCmd(cmdstr)
+        cmd = parser.parse_cmd(cmdstr)
         if cmd is not None:
             cmd.command(p)
     print()
     print("You ended the game with:")
     for i in p.inv:
-        print(" -", aOrAn(i))
-
-
-# ====================
-# start game definition
-roomMap = """
-     d-Z
-     |
-   f-c-e
-   . |
-   q<b
-     |
-     A
-"""
-rooms = createRooms(roomMap)
-rooms"A".desc = "You are standing on the front porch of a wooden shack."
-rooms"b".desc = "You are in a garden."
-rooms"c".desc = "You are in a kitchen."
-rooms"d".desc = "You are on the back porch."
-rooms"e".desc = "You are in a library."
-rooms"f".desc = "You are on the patio."
-rooms"q".desc = "You are sinking in quicksand.  You're dead..."
-rooms"q".gameOver = True
-
-# define global variables for referencing rooms
-frontPorch = rooms"A"
-garden = rooms"b"
-kitchen = rooms"c"
-backPorch = rooms"d"
-library = rooms"e"
-patio = rooms"f"
-
-# create items
-itemNames = (
-    """sword.diamond.apple.flower.coin.shovel.book.mirror.telescope.gold bar""".split(
-        "."
+        print(" -", a_or_an(i))
+
+
+if __name__ == '__main__':
+    # start game definition
+    roomMap = """
+         d-Z
+         |
+       f-c-e
+       . |
+       q<b
+         |
+         A
+    """
+    rooms = createRooms(roomMap)
+    rooms"A".desc = "You are standing on the front porch of a wooden shack."
+    rooms"b".desc = "You are in a garden."
+    rooms"c".desc = "You are in a kitchen."
+    rooms"d".desc = "You are on the back porch."
+    rooms"e".desc = "You are in a library."
+    rooms"f".desc = "You are on the patio."
+    rooms"q".desc = "You are sinking in quicksand.  You're dead..."
+    rooms"q".gameOver = True
+
+    # define global variables for referencing rooms
+    frontPorch = rooms"A"
+    garden = rooms"b"
+    kitchen = rooms"c"
+    backPorch = rooms"d"
+    library = rooms"e"
+    patio = rooms"f"
+
+    # create items
+    itemNames = (
+        """sword.diamond.apple.flower.coin.shovel.book.mirror.telescope.gold bar""".split(
+            "."
+        )
     )
-)
-for itemName in itemNames:
-    Item(itemName)
-Item.items"apple".isDeadly = True
-Item.items"mirror".isFragile = True
-Item.items"coin".isVisible = False
-Item.items"shovel".usableConditionTest = lambda p, t: p.room is garden
+    for itemName in itemNames:
+        Item(itemName)
+    Item.items"apple".isDeadly = True
+    Item.items"mirror".isFragile = True
+    Item.items"coin".isVisible = False
+    Item.items"shovel".usableConditionTest = lambda p, t: p.room is garden
 
 
-def useShovel(p, subj, target):
-    coin = Item.items"coin"
-    if not coin.isVisible and coin in p.room.inv:
-        coin.isVisible = True
+    def use_shovel(p, subj, target):
+        coin = Item.items"coin"
+        if not coin.isVisible and coin in p.room.inv:
+            coin.isVisible = True
 
 
-Item.items"shovel".useAction = useShovel
+    Item.items"shovel".useAction = use_shovel
 
-Item.items"telescope".isTakeable = False
+    Item.items"telescope".isTakeable = False
 
 
-def useTelescope(p, subj, target):
-    print("You don't see anything.")
+    def use_telescope(p, subj, target):
+        print("You don't see anything.")
 
 
-Item.items"telescope".useAction = useTelescope
+    Item.items"telescope".useAction = use_telescope
 
-OpenableItem("treasure chest", Item.items"gold bar")
-Item.items"chest" = Item.items"treasure chest"
-Item.items"chest".isTakeable = False
-Item.items"chest".cantTakeMessage = "It's too heavy!"
+    OpenableItem("treasure chest", Item.items"gold bar")
+    Item.items"chest" = Item.items"treasure chest"
+    Item.items"chest".isTakeable = False
+    Item.items"chest".cantTakeMessage = "It's too heavy!"
 
-OpenableItem("mailbox")
-Item.items"mailbox".isTakeable = False
-Item.items"mailbox".cantTakeMessage = "It's nailed to the wall!"
+    OpenableItem("mailbox")
+    Item.items"mailbox".isTakeable = False
+    Item.items"mailbox".cantTakeMessage = "It's nailed to the wall!"
 
-putItemInRoom("mailbox", frontPorch)
-putItemInRoom("shovel", frontPorch)
-putItemInRoom("coin", garden)
-putItemInRoom("flower", garden)
-putItemInRoom("apple", library)
-putItemInRoom("mirror", library)
-putItemInRoom("telescope", library)
-putItemInRoom("book", kitchen)
-putItemInRoom("diamond", backPorch)
-putItemInRoom("treasure chest", patio)
+    putItemInRoom("mailbox", frontPorch)
+    putItemInRoom("shovel", frontPorch)
+    putItemInRoom("coin", garden)
+    putItemInRoom("flower", garden)
+    putItemInRoom("apple", library)
+    putItemInRoom("mirror", library)
+    putItemInRoom("telescope", library)
+    putItemInRoom("book", kitchen)
+    putItemInRoom("diamond", backPorch)
+    putItemInRoom("treasure chest", patio)
 
-# create player
-plyr = Player("Bob")
-plyr.take(Item.items"sword")
+    # create player
+    plyr = Player("Bob")
+    plyr.take(Item.items"sword")
 
-# start game
-playGame(plyr, frontPorch)
+    # start game
+    playGame(plyr, frontPorch)

_service:tar_scm:pyparsing-3.1.1.tar.gz/examples/bf.py Added

@@ -0,0 +1,159 @@
+# bf.py
+#
+# Brainf*ck interpreter demo
+#
+# BF instructions (symbols):
+#   + - increment value at the current pointer
+#   - - decrement value at the current pointer
+#   > - increment pointer
+#   < - decrement pointer
+#   , - input new byte value, store at the current pointer
+#   . - output the byte at the current pointer
+#    - evaluate value at current pointer, if nonzero, execute all statements in 's and repeat
+#
+import pyparsing as pp
+
+# define the basic parser
+
+# define Literals for each symbol in the BF langauge
+PLUS, MINUS, GT, LT, INP, OUT, LBRACK, RBRACK = pp.Literal.using_each("+-<>,.")
+
+# use a pyparsing Forward for the recursive definition of an instruction that can
+# itself contain instructions
+instruction_expr = pp.Forward().set_name("instruction")
+
+# define a LOOP expression for the instructions enclosed in brackets; use a
+# pyparsing Group to wrap the instructions in a sub-list
+LOOP = pp.Group(LBRACK + instruction_expr... + RBRACK)
+
+# use '<<=' operator to insert expression definition into existing Forward
+instruction_expr <<= PLUS | MINUS | GT | LT | INP | OUT | LOOP
+
+program_expr = instruction_expr....set_name("program")
+
+# ignore everything that is not a BF symbol
+ignore_chars = pp.Word(pp.printables, exclude_chars="+-<>,.")
+program_expr.ignore(ignore_chars)
+
+
+class BFEngine:
+    """
+    Brainf*ck execution environment, with a memory array and pointer.
+    """
+    def __init__(self, memory_size: int = 1024):
+        self._ptr = 0
+        self._memory_size = memory_size
+        self._memory = 0 * self._memory_size
+
+    @property
+    def ptr(self):
+        return self._ptr
+
+    @ptr.setter
+    def ptr(self, value):
+        self._ptr = value % self._memory_size
+
+    @property
+    def at_ptr(self):
+        return self._memoryself._ptr
+
+    @at_ptr.setter
+    def at_ptr(self, value):
+        self._memoryself._ptr = value % 256
+
+    def output_value_at_ptr(self):
+        print(chr(self.at_ptr), end="")
+
+    def input_value(self):
+        input_char = input() or "\0"
+        self.at_ptr = ord(input_char0)
+
+    def reset(self):
+        self._ptr = 0
+        self._memory: = 0 * self._memory_size
+
+    def dump_state(self):
+        for i in range(30):
+            print(f"{self._memoryi:3d} ", end="")
+        print()
+
+        if self.ptr < 30:
+            print(f" {'    ' * self.ptr}^")
+
+
+# define executable classes for each instruction
+
+class Instruction:
+    """Abstract class for all instruction classes to implement."""
+    def __init__(self, tokens):
+        self.tokens = tokens
+
+    def execute(self, bf_engine: BFEngine):
+        raise NotImplementedError()
+
+
+class IncrPtr(Instruction):
+    def execute(self, bf_engine: BFEngine):
+        bf_engine.ptr += 1
+
+
+class DecrPtr(Instruction):
+    def execute(self, bf_engine: BFEngine):
+        bf_engine.ptr -= 1
+
+
+class IncrPtrValue(Instruction):
+    def execute(self, bf_engine: BFEngine):
+        bf_engine.at_ptr += 1
+
+
+class DecrPtrValue(Instruction):
+    def execute(self, bf_engine: BFEngine):
+        bf_engine.at_ptr -= 1
+
+
+class OutputPtrValue(Instruction):
+    def execute(self, bf_engine: BFEngine):
+        bf_engine.output_value_at_ptr()
+
+
+class InputPtrValue(Instruction):
+    def execute(self, bf_engine: BFEngine):
+        bf_engine.input_value()
+
+
+class RunInstructionLoop(Instruction):
+    def __init__(self, tokens):
+        super().__init__(tokens)
+        self.instructions = self.tokens01:-1
+
+    def execute(self, bf_engine: BFEngine):
+        while bf_engine.at_ptr:
+            for i in self.instructions:
+                i.execute(bf_engine)
+
+
+# add parse actions to all BF instruction expressions
+PLUS.add_parse_action(IncrPtrValue)
+MINUS.add_parse_action(DecrPtrValue)
+GT.add_parse_action(IncrPtr)
+LT.add_parse_action(DecrPtr)
+OUT.add_parse_action(OutputPtrValue)
+INP.add_parse_action(InputPtrValue)
+LOOP.add_parse_action(RunInstructionLoop)
+
+
+@program_expr.add_parse_action
+def run_program(tokens):
+    bf = BFEngine()
+    for t in tokens:
+        t.execute(bf)
+    print()
+
+
+# generate railroad diagram
+program_expr.create_diagram("bf.html")
+
+# execute an example BF program
+hw = "+-->->>+>-----<<<--<--->-.>>>+.>>..+++.><<<<.+++.------.<<-.>>>>+."
+program_expr.parse_string(hw)

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/booleansearchparser.py -> _service:tar_scm:pyparsing-3.1.1.tar.gz/examples/booleansearchparser.py Changed

@@ -90,11 +90,14 @@
     Suppress,
     OneOrMore,
     one_of,
+    ParserElement,
 )
 import re
 
+ParserElement.enablePackrat()
 
 # Updated on 02 Dec 2021 according to ftp://ftp.unicode.org/Public/UNIDATA/Blocks.txt
+# (includes characters not found in the BasicMultilingualPlane)
 alphabet_ranges = 
     # CYRILIC: https://en.wikipedia.org/wiki/Cyrillic_(Unicode_block)
     int("0400", 16), int("04FF", 16),
@@ -322,6 +325,7 @@
     """
 
     def Test(self):
+        # fmt: off
         exprs = {
             "0": "help",
             "1": "help or hulp",
@@ -363,93 +367,28 @@
 
         texts_matcheswith = {
             "halp thinks he needs help": 
-                "25",
-                "22",
-                "20",
-                "21",
-                "11",
-                "17",
-                "16",
-                "23",
-                "34",
-                "1",
-                "0",
-                "5",
-                "7",
-                "6",
-                "9",
-                "8",
+                "25", "22", "20", "21", "11", "17", "16", "23", "34", "1",
+                "0", "5", "7", "6", "9", "8",
             ,
             "he needs halp": "24", "25", "20", "11", "10", "12", "34", "6",
             "help": "25", "20", "12", "17", "16", "1", "0", "5", "6",
             "help hilp": 
-                "25",
-                "22",
-                "20",
-                "32",
-                "21",
-                "12",
-                "17",
-                "16",
-                "19",
-                "31",
-                "23",
-                "1",
-                "0",
-                "5",
-                "4",
-                "7",
-                "6",
-                "9",
-                "8",
-                "33",
+                "25", "22", "20", "32", "21", "12", "17", "16", "19", "31",
+                "23", "1", "0", "5", "4", "7", "6", "9", "8", "33",
             ,
             "help me please hulp": 
-                "30",
-                "25",
-                "27",
-                "20",
-                "13",
-                "12",
-                "15",
-                "14",
-                "17",
-                "16",
-                "19",
-                "18",
-                "23",
-                "29",
-                "1",
-                "0",
-                "3",
-                "2",
-                "5",
-                "4",
-                "6",
-                "9",
+                "30", "25", "27", "20", "13", "12", "15", "14", "17", "16",
+                "19", "18", "23", "29", "1", "0", "3", "2", "5", "4", "6", "9",
             ,
             "helper": "20", "10", "12", "16",
             "hulp hilp": 
-                "25",
-                "27",
-                "20",
-                "21",
-                "10",
-                "12",
-                "14",
-                "17",
-                "19",
-                "23",
-                "1",
-                "5",
-                "4",
-                "7",
-                "6",
-                "9",
+                "25", "27", "20", "21", "10", "12", "14", "17", "19", "23",
+                "1", "5", "4", "7", "6", "9",
             ,
             "nothing": "25", "10", "12",
             "안녕하세요, 당신은 어떠세요?": "10", "12", "25", "35",
         }
+        # fmt: on
 
         all_ok = True
         for text, matches in texts_matcheswith.items():
@@ -459,7 +398,9 @@
                     _matches.append(_id)
 
             test_passed = sorted(matches) == sorted(_matches)
-            if not test_passed:
+            if test_passed:
+                print("Passed", repr(text))
+            else:
                 print("Failed", repr(text), "expected", matches, "matched", _matches)
 
             all_ok = all_ok and test_passed
@@ -490,7 +431,9 @@
                     _matches.append(_id)
 
             test_passed = sorted(matches) == sorted(_matches)
-            if not test_passed:
+            if test_passed:
+                print("Passed", repr(text))
+            else:
                 print("Failed", repr(text), "expected", matches, "matched", _matches)
 
             all_ok = all_ok and test_passed
@@ -498,10 +441,13 @@
         return all_ok
 
 
-if __name__ == "__main__":
+def main():
     if ParserTest().Test():
         print("All tests OK")
-        exit(0)
     else:
         print("One or more tests FAILED")
-        exit(1)
+        raise Exception("One or more tests FAILED")
+
+
+if __name__ == "__main__":
+    main()

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/builtin_parse_action_demo.py -> _service:tar_scm:pyparsing-3.1.1.tar.gz/examples/builtin_parse_action_demo.py Changed

_service:tar_scm:pyparsing-3.1.1.tar.gz/examples/chemical_formulas.py Added

@@ -0,0 +1,119 @@
+#
+# chemicalFormulas.py
+#
+# Copyright (c) 2003,2019 Paul McGuire
+#
+
+import pyparsing as pp
+
+atomic_weight = {
+    "O": 15.9994,
+    "H": 1.00794,
+    "Na": 22.9897,
+    "Cl": 35.4527,
+    "C": 12.0107,
+}
+
+digits = "0123456789"
+
+# Version 1
+element = pp.Word(pp.alphas.upper(), pp.alphas.lower(), max=2).set_name("element")
+# for stricter matching, use this Regex instead
+# element = Regex("Acglmrstu|Baehikr?|Cadeflmorsu?|Dbsy|"
+#                 "Ersu|Femr?|Gade|Hefgos?|Inr?|Kr?|Lairu|"
+#                 "Mdgnot|Nabdeiop?|Os?|Pabdmortu?|Rabefghnu|"
+#                 "Sbcegimnr?|Tabcehilm|U(ubhopqst)?|V|W|Xe|Yb?|Znr")
+element_ref = pp.Group(element + pp.Opt(pp.Word(digits), default="1"))
+formula = element_ref...
+
+
+def sum_atomic_weights(element_list):
+    return sum(atomic_weightelem * int(qty) for elem, qty in element_list)
+
+
+formula.run_tests(
+    """\
+    H2O
+    C6H5OH
+    NaCl
+    """,
+    full_dump=False,
+    post_parse=lambda _, tokens: f"Molecular weight: {sum_atomic_weights(tokens)}",
+)
+print()
+
+
+# Version 2 - access parsed items by results name
+element_ref = pp.Group(
+    element("symbol") + pp.Opt(pp.Word(digits), default="1")("qty")
+)
+formula = element_ref...
+
+
+def sum_atomic_weights_by_results_name(element_list):
+    return sum(atomic_weightelem.symbol * int(elem.qty) for elem in element_list)
+
+
+formula.run_tests(
+    """\
+    H2O
+    C6H5OH
+    NaCl
+    """,
+    full_dump=False,
+    post_parse=lambda _, tokens:
+        f"Molecular weight: {sum_atomic_weights_by_results_name(tokens)}",
+)
+print()
+
+# Version 3 - convert integers during parsing process
+integer = pp.Word(digits).set_name("integer")
+integer.add_parse_action(lambda t: int(t0))
+element_ref = pp.Group(element("symbol") + pp.Opt(integer, default=1)("qty"))
+formula = element_ref....set_name("chemical_formula")
+
+
+def sum_atomic_weights_by_results_name_with_converted_ints(element_list):
+    return sum(atomic_weightelem.symbol * int(elem.qty) for elem in element_list)
+
+
+formula.run_tests(
+    """\
+    H2O
+    C6H5OH
+    NaCl
+    """,
+    full_dump=False,
+    post_parse=lambda _, tokens:
+        f"Molecular weight: {sum_atomic_weights_by_results_name_with_converted_ints(tokens)}",
+)
+print()
+
+# Version 4 - parse and convert integers as subscript digits
+subscript_digits = "₀₁₂₃₄₅₆₇₈₉"
+subscript_int_map = {e1: e0 for e in enumerate(subscript_digits)}
+
+
+def cvt_subscript_int(s):
+    ret = 0
+    for c in s0:
+        ret = ret * 10 + subscript_int_mapc
+    return ret
+
+
+subscript_int = pp.Word(subscript_digits).set_name("subscript")
+subscript_int.add_parse_action(cvt_subscript_int)
+
+element_ref = pp.Group(element("symbol") + pp.Opt(subscript_int, default=1)("qty"))
+formula = element_ref1, ....set_name("chemical_formula")
+formula.run_tests(
+    """\
+    H₂O
+    C₆H₅OH
+    NaCl
+    """,
+    full_dump=False,
+    post_parse=lambda _, tokens:
+        f"Molecular weight: {sum_atomic_weights_by_results_name_with_converted_ints(tokens)}",
+)
+print()

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/cpp_enum_parser.py -> _service:tar_scm:pyparsing-3.1.1.tar.gz/examples/cpp_enum_parser.py Changed

@@ -9,7 +9,7 @@
 #
 #
 
-from pyparsing import *
+import pyparsing as pp
 
 # sample string with enums and other stuff
 sample = """
@@ -35,19 +35,19 @@
     """
 
 # syntax we don't want to see in the final parse tree
-LBRACE, RBRACE, EQ, COMMA = map(Suppress, "{}=,")
-_enum = Suppress("enum")
-identifier = Word(alphas, alphanums + "_")
-integer = Word(nums)
-enumValue = Group(identifier("name") + Optional(EQ + integer("value")))
-enumList = Group(enumValue + ZeroOrMore(COMMA + enumValue))
+LBRACE, RBRACE, EQ, COMMA = pp.Suppress.using_each("{}=,")
+_enum = pp.Suppress("enum")
+identifier = pp.Word(pp.alphas + "_", pp.alphanums + "_")
+integer = pp.Word(pp.nums)
+enumValue = pp.Group(identifier("name") + pp.Optional(EQ + integer("value")))
+enumList = pp.Group(enumValue + (COMMA + enumValue)...)
 enum = _enum + identifier("enum") + LBRACE + enumList("names") + RBRACE
 
 # find instances of enums ignoring other syntax
-for item, start, stop in enum.scanString(sample):
-    id = 0
+for item, start, stop in enum.scan_string(sample):
+    idx = 0
     for entry in item.names:
         if entry.value != "":
-            id = int(entry.value)
-        print("%s_%s = %d" % (item.enum.upper(), entry.name.upper(), id))
-        id += 1
+            idx = int(entry.value)
+        print("%s_%s = %d" % (item.enum.upper(), entry.name.upper(), idx))
+        idx += 1

_service:tar_scm:pyparsing-3.1.1.tar.gz/examples/datetime_parse_actions.py Added

@@ -0,0 +1,84 @@
+# parseActions.py
+#
+#   A sample program a parser to match a date string of the form "YYYY/MM/DD",
+# and return it as a datetime, or raise an exception if not a valid date.
+#
+# Copyright 2012, Paul T. McGuire
+#
+from datetime import datetime
+import pyparsing as pp
+from pyparsing import pyparsing_common as ppc
+
+# define an integer string, and a parse action to convert it
+# to an integer at parse time
+integer = pp.Word(pp.nums).set_name("integer")
+
+
+def convert_to_int(tokens):
+    # no need to test for validity - we can't get here
+    # unless tokens0 contains all numeric digits
+    return int(tokens0)
+
+
+integer.set_parse_action(convert_to_int)
+# or can be written as one line as
+# integer = Word(nums).set_parse_action(lambda t: int(t0))
+
+# define a pattern for a year/month/day date
+date_expr = integer("year") + "/" + integer("month") + "/" + integer("day")
+date_expr.ignore(pp.python_style_comment)
+
+
+def convert_to_datetime(s, loc, tokens):
+    try:
+        # note that the year, month, and day fields were already
+        # converted to ints from strings by the parse action defined
+        # on the integer expression above
+        return datetime(tokens.year, tokens.month, tokens.day).date()
+    except Exception as ve:
+        errmsg = "'%s/%s/%s' is not a valid date, %s" % (
+            tokens.year,
+            tokens.month,
+            tokens.day,
+            ve,
+        )
+        raise pp.ParseException(s, loc, errmsg)
+
+
+date_expr.set_parse_action(convert_to_datetime)
+
+
+date_expr.run_tests(
+    """\
+    2000/1/1
+
+    # invalid month
+    2000/13/1
+
+    # 1900 was not a leap year
+    1900/2/29
+
+    # but 2000 was
+    2000/2/29
+    """
+)
+
+
+# if dates conform to ISO8601, use definitions in pyparsing_common
+date_expr = ppc.iso8601_date.set_parse_action(ppc.convert_to_date())
+date_expr.ignore(pp.python_style_comment)
+
+date_expr.run_tests(
+    """\
+    2000-01-01
+
+    # invalid month
+    2000-13-01
+
+    # 1900 was not a leap year
+    1900-02-29
+
+    # but 2000 was
+    2000-02-29
+    """
+)

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/delta_time.py -> _service:tar_scm:pyparsing-3.1.1.tar.gz/examples/delta_time.py Changed

@@ -39,7 +39,7 @@
 
 # basic grammar definitions
 def make_integer_word_expr(int_name, int_value):
-    return pp.CaselessKeyword(int_name).addParseAction(pp.replaceWith(int_value))
+    return pp.CaselessKeyword(int_name).add_parse_action(pp.replaceWith(int_value))
 
 
 integer_word = pp.MatchFirst(
@@ -50,52 +50,54 @@
         " seventeen eighteen nineteen twenty".split(),
         start=1,
     )
-).setName("integer_word")
+).set_name("integer_word")
 
 integer = pp.pyparsing_common.integer | integer_word
-integer.setName("numeric")
+integer.set_name("numeric")
 
 CK = pp.CaselessKeyword
 CL = pp.CaselessLiteral
-today, tomorrow, yesterday, noon, midnight, now = map(
-    CK, "today tomorrow yesterday noon midnight now".split()
+today, tomorrow, yesterday, noon, midnight, now = CK.using_each(
+    "today tomorrow yesterday noon midnight now".split()
 )
 
 
 def plural(s):
-    return CK(s) | CK(s + "s").addParseAction(pp.replaceWith(s))
+    return CK(s) | CK(s + "s").add_parse_action(pp.replaceWith(s))
 
 
 week, day, hour, minute, second = map(plural, "week day hour minute second".split())
 time_units = hour | minute | second
-any_time_units = (week | day | time_units).setName("time_units")
+any_time_units = (week | day | time_units).set_name("any_time_units")
 
 am = CL("am")
 pm = CL("pm")
 COLON = pp.Suppress(":")
 
-in_ = CK("in").setParseAction(pp.replaceWith(1))
-from_ = CK("from").setParseAction(pp.replaceWith(1))
-before = CK("before").setParseAction(pp.replaceWith(-1))
-after = CK("after").setParseAction(pp.replaceWith(1))
-ago = CK("ago").setParseAction(pp.replaceWith(-1))
-next_ = CK("next").setParseAction(pp.replaceWith(1))
-last_ = CK("last").setParseAction(pp.replaceWith(-1))
+in_ = CK("in").set_parse_action(pp.replaceWith(1))
+from_ = CK("from").set_parse_action(pp.replaceWith(1))
+before = CK("before").set_parse_action(pp.replaceWith(-1))
+after = CK("after").set_parse_action(pp.replaceWith(1))
+ago = CK("ago").set_parse_action(pp.replaceWith(-1))
+next_ = CK("next").set_parse_action(pp.replaceWith(1))
+last_ = CK("last").set_parse_action(pp.replaceWith(-1))
 at_ = CK("at")
 on_ = CK("on")
 
 couple = (
-    (pp.Optional(CK("a")) + CK("couple") + pp.Optional(CK("of")))
-    .setParseAction(pp.replaceWith(2))
-    .setName("couple")
+    (pp.Opt(CK("a")) + CK("couple") + pp.Opt(CK("of")))
+    .set_parse_action(pp.replaceWith(2))
+    .set_name("couple")
 )
 
-a_qty = (CK("a") | CK("an")).setParseAction(pp.replaceWith(1))
-the_qty = CK("the").setParseAction(pp.replaceWith(1))
+a_qty = (CK("a") | CK("an")).set_parse_action(pp.replaceWith(1))
+the_qty = CK("the").set_parse_action(pp.replaceWith(1))
 qty = pp.ungroup(
-    (integer | couple | a_qty | the_qty).setName("qty_expression")
-).setName("qty")
-time_ref_present = pp.Empty().addParseAction(pp.replaceWith(True))("time_ref_present")
+    (integer | couple | a_qty | the_qty).set_name("qty_expression")
+).set_name("qty")
+time_ref_present = pp.Empty().add_parse_action(pp.replace_with(True))(
+    "time_ref_present"
+)
 
 
 def fill_24hr_time_fields(t):
@@ -111,26 +113,28 @@
             tfld = 0
 
 
+# get weekday names from the calendar module
 weekday_name_list = list(calendar.day_name)
-weekday_name = pp.oneOf(weekday_name_list).setName("weekday_name")
+weekday_name = pp.one_of(weekday_name_list).set_name("weekday_name")
 
-_24hour_time = ~(integer + any_time_units).setName("numbered_time_units") + pp.Word(pp.nums, exact=4).setName("HHMM").addParseAction(
+# expressions for military 2400 time
+_24hour_time = ~(pp.Word(pp.nums) + any_time_units).set_name("numbered_time_units") + pp.Word(
+    pp.nums, exact=4, as_keyword=True
+).set_name("HHMM").add_parse_action(
     lambda t: int(t0:2), int(t02:), fill_24hr_time_fields
 )
-_24hour_time.setName("0000 time")
+_24hour_time.set_name("0000 time")
 ampm = am | pm
 timespec = (
     integer("HH")
-    + pp.Optional(
-        CK("o'clock") | COLON + integer("MM") + pp.Optional(COLON + integer("SS"))
-    )
+    + pp.Opt(CK("o'clock") | COLON + integer("MM") + pp.Opt(COLON + integer("SS")))
     + (am | pm)("ampm")
-).addParseAction(fill_default_time_fields)
+).add_parse_action(fill_default_time_fields)
 absolute_time = _24hour_time | timespec
-absolute_time.setName("absolute time")
+absolute_time.set_name("absolute time")
 
 absolute_time_of_day = noon | midnight | now | absolute_time
-absolute_time_of_day.setName("time of day")
+absolute_time_of_day.set_name("time of day")
 
 
 def add_computed_time(t):
@@ -145,12 +149,12 @@
         t"computed_time" = time(hour=t.HH, minute=t.MM, second=t.SS)
 
 
-absolute_time_of_day.addParseAction(add_computed_time)
+absolute_time_of_day.add_parse_action(add_computed_time)
 
 
 #     relative_time_reference ::= qty time_units ('ago' | ('from' | 'before' | 'after') absolute_time_of_day)
 #                                 | 'in' qty time_units
-time_units = (hour | minute | second).setName("time unit")
+time_units = (hour | minute | second).set_name("time unit")
 relative_time_reference = (
     (
         qty("qty")
@@ -162,7 +166,7 @@
         )
     )
     | in_("dir") + qty("qty") + time_units("units")
-).setName("relative time")
+).set_name("relative time")
 
 
 def compute_relative_time(t):
@@ -174,10 +178,10 @@
     t"time_delta" = timedelta(seconds=t.dir * delta_seconds)
 
 
-relative_time_reference.addParseAction(compute_relative_time)
+relative_time_reference.add_parse_action(compute_relative_time)
 
 time_reference = absolute_time_of_day | relative_time_reference
-time_reference.setName("time reference")
+time_reference.set_name("time reference")
 
 
 def add_default_time_ref_fields(t):
@@ -185,13 +189,13 @@
         t"time_delta" = timedelta()
 
 
-time_reference.addParseAction(add_default_time_ref_fields)
+time_reference.add_parse_action(add_default_time_ref_fields)
 
 #     absolute_day_reference ::= 'today' | 'tomorrow' | 'yesterday' | ('next' | 'last') weekday_name
 #     day_units ::= 'days' | 'weeks'
 
 day_units = day | week
-weekday_reference = pp.Optional(next_ | last_, 1)("dir") + weekday_name("day_name")
+weekday_reference = pp.Opt(next_ | last_, 1)("dir") + weekday_name("day_name")
 
 
 def convert_abs_day_reference_to_date(t):
@@ -222,8 +226,8 @@
 absolute_day_reference = (
     today | tomorrow | yesterday | now + time_ref_present | weekday_reference
 )
-absolute_day_reference.addParseAction(convert_abs_day_reference_to_date)
-absolute_day_reference.setName("absolute day")
+absolute_day_reference.add_parse_action(convert_abs_day_reference_to_date)
+absolute_day_reference.set_name("absolute day")
 
 #     relative_day_reference ::=  'in' qty day_units
 #                                   | qty day_units
@@ -234,7 +238,7 @@
 ) + day_units("units") + (
     ago("dir") | ((from_ | before | after)("dir") + absolute_day_reference("ref_day"))
 )
-relative_day_reference.setName("relative day")
+relative_day_reference.set_name("relative day")
 
 
 def compute_relative_date(t):
@@ -247,11 +251,11 @@
     t"date_delta" = timedelta(days=day_diff)
 
 
-relative_day_reference.addParseAction(compute_relative_date)
+relative_day_reference.add_parse_action(compute_relative_date)
 
 # combine expressions for absolute and relative day references
 day_reference = relative_day_reference | absolute_day_reference
-day_reference.setName("day reference")
+day_reference.set_name("day reference")
 
 
 def add_default_date_fields(t):
@@ -259,13 +263,13 @@
         t"date_delta" = timedelta()
 
 
-day_reference.addParseAction(add_default_date_fields)
+day_reference.add_parse_action(add_default_date_fields)
 
 # combine date and time expressions into single overall parser
-time_and_day = time_reference + time_ref_present + pp.Optional(
-    pp.Optional(on_) + day_reference
-) | day_reference + pp.Optional(at_ + absolute_time_of_day + time_ref_present)
-time_and_day.setName("time and day")
+time_and_day = time_reference + time_ref_present + pp.Opt(
+    pp.Opt(on_) + day_reference
+) | day_reference + pp.Opt(at_ + absolute_time_of_day + time_ref_present)
+time_and_day.set_name("time and day")
 
 # parse actions for total time_and_day expression
 def save_original_string(s, l, t):
@@ -318,12 +322,13 @@
             del tk
 
 
-time_and_day.addParseAction(save_original_string, compute_timestamp, remove_temp_keys)
+time_and_day.add_parse_action(save_original_string, compute_timestamp, remove_temp_keys)
 
 
 time_expression = time_and_day
 
 
+# fmt: off
 def main():
     current_time = datetime.now()
     # test grammar
@@ -415,9 +420,7 @@
         "the day after tomorrow": timedelta(days=2) - time_of_day,
         "tomorrow": timedelta(days=1) - time_of_day,
         "the day before yesterday": timedelta(days=-2) - time_of_day,
-        "8am the day after tomorrow": timedelta(days=+2)
-        - time_of_day
-        + timedelta(hours=8),
+        "8am the day after tomorrow": timedelta(days=+2) - time_of_day + timedelta(hours=8),
         "yesterday": timedelta(days=-1) - time_of_day,
         "today": -time_of_day,
         "midnight": -time_of_day,
@@ -430,14 +433,13 @@
         "12:15 AM today": -time_of_day + timedelta(minutes=15),
         "3pm 2 days from today": timedelta(days=2) - time_of_day + timedelta(hours=15),
         "ten seconds before noon tomorrow": timedelta(days=1)
-        - time_of_day
-        + timedelta(hours=12)
-        + timedelta(seconds=-10),
-        "20 seconds before noon": -time_of_day
-        + timedelta(hours=12)
-        + timedelta(seconds=-20),
+                                            - time_of_day
+                                            + timedelta(hours=12)
+                                            + timedelta(seconds=-10),
+        "20 seconds before noon": -time_of_day + timedelta(hours=12) + timedelta(seconds=-20),
         "in 3 days at 5pm": timedelta(days=3) - time_of_day + timedelta(hours=17),
     }
+    # fmt: on
 
     def verify_offset(instring, parsed):
         time_epsilon = timedelta(seconds=1)
@@ -449,7 +451,19 @@
                 parsed"verify_offset" = "FAIL"
 
     print("(relative to %s)" % datetime.now())
-    time_expression.runTests(tests, postParse=verify_offset)
+    success, report = time_expression.runTests(tests, postParse=verify_offset)
+    assert success
+
+    fails = 
+    for test, rpt in report:
+        if rpt.get("verify_offset", "PASS") != "PASS":
+            fails.append((test, rpt))
+
+    if fails:
+        print("\nFAILED")
+        print("\n".join("- " + test for test, rpt in fails))
+
+    assert not fails
 
 
 if __name__ == "__main__":

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/eval_arith.py -> _service:tar_scm:pyparsing-3.1.1.tar.gz/examples/eval_arith.py Changed

@@ -13,9 +13,9 @@
     nums,
     alphas,
     Combine,
-    oneOf,
-    opAssoc,
-    infixNotation,
+    one_of,
+    OpAssoc,
+    infix_notation,
     Literal,
     ParserElement,
 )
@@ -143,28 +143,28 @@
 variable = Word(alphas, exact=1)
 operand = real | integer | variable
 
-signop = oneOf("+ -")
-multop = oneOf("* /")
-plusop = oneOf("+ -")
+signop = one_of("+ -")
+multop = one_of("* /")
+plusop = one_of("+ -")
 expop = Literal("**")
 
 # use parse actions to attach EvalXXX constructors to sub-expressions
 operand.setParseAction(EvalConstant)
-arith_expr = infixNotation(
+arith_expr = infix_notation(
     operand,
     
-        (signop, 1, opAssoc.RIGHT, EvalSignOp),
-        (expop, 2, opAssoc.LEFT, EvalPowerOp),
-        (multop, 2, opAssoc.LEFT, EvalMultOp),
-        (plusop, 2, opAssoc.LEFT, EvalAddOp),
+        (signop, 1, OpAssoc.RIGHT, EvalSignOp),
+        (expop, 2, OpAssoc.LEFT, EvalPowerOp),
+        (multop, 2, OpAssoc.LEFT, EvalMultOp),
+        (plusop, 2, OpAssoc.LEFT, EvalAddOp),
     ,
 )
 
-comparisonop = oneOf("< <= > >= != = <> LT GT LE GE EQ NE")
-comp_expr = infixNotation(
+comparisonop = one_of("< <= > >= != = <> LT GT LE GE EQ NE")
+comp_expr = infix_notation(
     arith_expr,
     
-        (comparisonop, 2, opAssoc.LEFT, EvalComparisonOp),
+        (comparisonop, 2, OpAssoc.LEFT, EvalComparisonOp),
     ,
 )

_service:tar_scm:pyparsing-3.1.1.tar.gz/examples/excel_expr.py Added

@@ -0,0 +1,93 @@
+# excelExpr.py
+#
+# Copyright 2010, Paul McGuire
+#
+# A partial implementation of a parser of Excel formula expressions.
+#
+import pyparsing as pp
+ppc = pp.common
+
+pp.ParserElement.enable_packrat()
+
+EQ, LPAR, RPAR, COLON, COMMA = pp.Suppress.using_each("=():,")
+EXCL, DOLLAR = pp.Literal.using_each("!$")
+sheet_ref = pp.Word(pp.alphas, pp.alphanums) | pp.QuotedString("'", escQuote="''")
+col_ref = pp.Opt(DOLLAR) + pp.Word(pp.alphas, max=2)
+row_ref = pp.Opt(DOLLAR) + pp.Word(pp.nums)
+cell_ref = pp.Combine(
+    pp.Group(pp.Opt(sheet_ref + EXCL)("sheet") + col_ref("col") + row_ref("row"))
+)
+
+cell_range = (
+        pp.Group(cell_ref("start") + COLON + cell_ref("end"))("range")
+        | cell_ref
+        | pp.Word(pp.alphas, pp.alphanums)
+)
+
+expr = pp.Forward()
+
+COMPARISON_OP = pp.one_of("< = > >= <= != <>")
+cond_expr = expr + COMPARISON_OP + expr
+
+if_func = (
+    pp.CaselessKeyword("if")
+    - LPAR
+    + pp.Group(cond_expr)("condition")
+    + COMMA
+    + pp.Group(expr)("if_true")
+    + COMMA
+    + pp.Group(expr)("if_false")
+    + RPAR
+)
+
+
+def stat_function(name):
+    return pp.Group(pp.CaselessKeyword(name) + pp.Group(LPAR + pp.DelimitedList(expr) + RPAR))
+
+
+sum_func = stat_function("sum")
+min_func = stat_function("min")
+max_func = stat_function("max")
+ave_func = stat_function("ave")
+func_call = if_func | sum_func | min_func | max_func | ave_func
+
+mult_op = pp.one_of("* /")
+add_op = pp.one_of("+ -")
+numeric_literal = ppc.number
+operand = numeric_literal | func_call | cell_range | cell_ref
+arith_expr = pp.infix_notation(
+    operand,
+    
+        (mult_op, 2, pp.OpAssoc.LEFT),
+        (add_op, 2, pp.OpAssoc.LEFT),
+    ,
+)
+
+text_operand = pp.dbl_quoted_string | cell_ref
+text_expr = pp.infix_notation(
+    text_operand,
+    
+        ("&", 2, pp.OpAssoc.LEFT),
+    ,
+)
+
+expr <<= arith_expr | text_expr
+
+
+def main():
+    success, report = (EQ + expr).run_tests(
+        """\
+        =3*A7+5
+        =3*Sheet1!$A$7+5
+        =3*'Sheet 1'!$A$7+5
+        =3*'O''Reilly''s sheet'!$A$7+5
+        =if(Sum(A1:A25)>42,Min(B1:B25),if(Sum(C1:C25)>3.14, (Min(C1:C25)+3)*18,Max(B1:B25)))
+        =sum(a1:a25,10,min(b1,c2,d3))
+        =if("T"&a2="TTime", "Ready", "Not ready")
+    """
+    )
+    assert success
+
+
+if __name__ == '__main__':
+    main()

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/gen_ctypes.py -> _service:tar_scm:pyparsing-3.1.1.tar.gz/examples/gen_ctypes.py Changed

@@ -44,16 +44,16 @@
     "void": "None",
 }
 
-LPAR, RPAR, LBRACE, RBRACE, COMMA, SEMI = map(Suppress, "(){},;")
-ident = Word(alphas, alphanums + "_")
+LPAR, RPAR, LBRACE, RBRACE, COMMA, SEMI = Suppress.using_each("(){},;")
+ident = pyparsing_common.identifier
 integer = Regex(r"+-?\d+")
 hexinteger = Regex(r"0x0-9a-fA-F+")
 
 const = Suppress("const")
-primitiveType = oneOf(t for t in typemap if not t.endswith("*"))
+primitiveType = one_of(t for t in typemap if not t.endswith("*"))
 structType = Suppress("struct") + ident
 vartype = (
-    Optional(const) + (primitiveType | structType | ident) + Optional(Word("*")("ptr"))
+    Opt(const) + (primitiveType | structType | ident) + Opt(Word("*")("ptr"))
 )
 
 
@@ -64,14 +64,14 @@
         # ~ return ret
 
 
-vartype.setParseAction(normalizetype)
+vartype.set_parse_action(normalizetype)
 
-arg = Group(vartype("argtype") + Optional(ident("argname")))
+arg = Group(vartype("argtype") + Opt(ident("argname")))
 func_def = (
     vartype("fn_type")
     + ident("fn_name")
     + LPAR
-    + Optional(delimitedList(arg | "..."))("fn_args")
+    + Opt(DelimitedList(arg | "..."))("fn_args")
     + RPAR
     + SEMI
 )
@@ -82,7 +82,7 @@
         t"varargs" = True
 
 
-func_def.setParseAction(derivefields)
+func_def.set_parse_action(derivefields)
 
 fn_typedef = "typedef" + func_def
 var_typedef = "typedef" + primitiveType("primType") + ident("name") + SEMI
@@ -90,10 +90,10 @@
 enum_def = (
     Keyword("enum")
     + LBRACE
-    + delimitedList(Group(ident("name") + "=" + (hexinteger | integer)("value")))(
+    + DelimitedList(Group(ident("name") + "=" + (hexinteger | integer)("value")))(
         "evalues"
     )
-    + Optional(COMMA)
+    + Opt(COMMA)
     + RBRACE
 )
 
@@ -135,13 +135,13 @@
 
 
 # scan input header text for primitive typedefs
-for td, _, _ in var_typedef.scanString(c_header):
+for td, _, _ in var_typedef.scan_string(c_header):
     typedefs.append((td.name, td.primType))
     # add typedef type to typemap to map to itself
     typemaptd.name = td.name
 
 # scan input header text for function typedefs
-fn_typedefs = fn_typedef.searchString(c_header)
+fn_typedefs = fn_typedef.search_string(c_header)
 # add each function typedef to typemap to map to itself
 for fntd in fn_typedefs:
     typemapfntd.fn_name = fntd.fn_name
@@ -149,7 +149,7 @@
 # scan input header text, and keep running list of user-defined types
 for fn, _, _ in (
     cStyleComment.suppress() | fn_typedef.suppress() | func_def
-).scanString(c_header):
+).scan_string(c_header):
     if not fn:
         continue
     getUDType(fn.fn_type)
@@ -160,8 +160,8 @@
     functions.append(fn)
 
 # scan input header text for enums
-enum_def.ignore(cppStyleComment)
-for en_, _, _ in enum_def.scanString(c_header):
+enum_def.ignore(cpp_style_comment)
+for en_, _, _ in enum_def.scan_string(c_header):
     for ev in en_.evalues:
         enum_constants.append((ev.name, ev.value))

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/getNTPserversNew.py -> _service:tar_scm:pyparsing-3.1.1.tar.gz/examples/getNTPserversNew.py Changed

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/greeting.py -> _service:tar_scm:pyparsing-3.1.1.tar.gz/examples/greeting.py Changed

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/greetingInGreek.py -> _service:tar_scm:pyparsing-3.1.1.tar.gz/examples/greetingInGreek.py Changed

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/greetingInKorean.py -> _service:tar_scm:pyparsing-3.1.1.tar.gz/examples/greetingInKorean.py Changed

_service:tar_scm:pyparsing-3.1.1.tar.gz/examples/hola_mundo.py Added

@@ -0,0 +1,73 @@
+# escrito por Marco Alfonso, 2004 Noviembre
+
+# importamos los símbolos requeridos desde el módulo
+from pyparsing import (
+    Word,
+    one_of,
+    nums,
+    Group,
+    OneOrMore,
+    Opt,
+    pyparsing_unicode as ppu,
+)
+
+# usamos las letras en latin1, que incluye las como 'ñ', 'á', 'é', etc.
+alphas = ppu.Latin1.alphas
+
+# Aqui decimos que la gramatica "saludo" DEBE contener
+# una palabra compuesta de caracteres alfanumericos
+# (Word(alphas)) mas una ',' mas otra palabra alfanumerica,
+# mas '!' y esos seian nuestros tokens
+saludo = Word(alphas) + "," + Word(alphas) + one_of("! . ?")
+tokens = saludo.parse_string("Hola, Mundo !")
+
+# Ahora parseamos una cadena, "Hola, Mundo!",
+# el metodo parseString, nos devuelve una lista con los tokens
+# encontrados, en caso de no haber errores...
+for i, token in enumerate(tokens):
+    print(f"Token {i} -> {token}")
+
+# imprimimos cada uno de los tokens Y listooo!!, he aquí a salida
+# Token 0 -> Hola
+# Token 1 -> ,
+# Token 2-> Mundo
+# Token 3 -> !
+
+# ahora cambia el parseador, aceptando saludos con mas que una sola palabra antes que ','
+saludo = Group(OneOrMore(Word(alphas))) + "," + Word(alphas) + one_of("! . ?")
+tokens = saludo.parse_string("Hasta mañana, Mundo !")
+
+for i, token in enumerate(tokens):
+    print(f"Token {i} -> {token}")
+
+# Ahora parseamos algunas cadenas, usando el metodo runTests
+saludo.run_tests("""\
+        Hola, Mundo!
+        Hasta mañana, Mundo !
+    """,
+    fullDump=False,
+)
+
+# Por supuesto, se pueden "reutilizar" gramáticas, por ejemplo:
+numimag = Word(nums) + "i"
+numreal = Word(nums)
+numcomplex = numimag | numreal + Opt("+" + numimag)
+
+# Funcion para cambiar a complejo numero durante parsear:
+def hace_python_complejo(t):
+    valid_python = "".join(t).replace("i", "j")
+    for tipo in (int, complex):
+        try:
+            return tipo(valid_python)
+        except ValueError:
+            pass
+
+
+numcomplex.set_parse_action(hace_python_complejo)
+numcomplex.run_tests("""\
+    3
+    5i
+    3+5i   
+""")
+
+# Excelente!!, bueno, los dejo, me voy a seguir tirando código...

_service:tar_scm:pyparsing-3.1.1.tar.gz/examples/html_stripper.py Added

@@ -0,0 +1,58 @@
+#
+# html_stripper.py
+#
+#  Sample code for stripping HTML markup tags and scripts from
+#  HTML source files.
+#
+# Copyright (c) 2006, 2016, 2023, Paul McGuire
+#
+from urllib.request import urlopen
+from pyparsing import (
+    LineEnd,
+    quoted_string,
+    make_html_tags,
+    common_html_entity,
+    replace_html_entity,
+    html_comment,
+    any_open_tag,
+    any_close_tag,
+    replace_with,
+)
+
+# if <script> tags found, remove script content also
+script_open, script_close = make_html_tags("script")
+script_body = script_open + ... + script_close
+
+# translate HTML entities
+common_html_entity.set_parse_action(replace_html_entity)
+
+stripper = (
+        # parse quoted strings first, if they enclose HTML tags - keep these
+        quoted_string
+        # parse and translate HTML entities (&amp;, &lt;, &gt;, etc.)
+        | common_html_entity
+        # expressions to be stripped - suppress() will remove them when transforming
+        | (
+            html_comment | script_body | any_open_tag | any_close_tag
+          ).suppress()
+)
+
+repeated_newlines = LineEnd()2, ...
+repeated_newlines.set_parse_action(replace_with("\n\n"))
+
+
+if __name__ == '__main__':
+    # get some HTML
+    target_url = "https://wiki.python.org/moin/PythonDecoratorLibrary"
+    with urlopen(target_url) as targetPage:
+        target_html = targetPage.read().decode("UTF-8")
+
+    # first pass, strip out tags and translate entities
+    # (use transform_string() instead of parse_string - will do
+    # suppressions and parse actions)
+    first_pass = stripper.transform_string(target_html)
+
+    # first pass leaves many blank lines, collapse these down
+    second_pass = repeated_newlines.transform_string(first_pass)
+
+    print(second_pass)

_service:tar_scm:pyparsing-3.1.1.tar.gz/examples/html_table_parser.py Added

@@ -0,0 +1,81 @@
+#
+# htmlTableParser.py
+#
+# Example of parsing a simple HTML table into a list of rows, and optionally into a little database
+#
+# Copyright 2019, Paul McGuire
+#
+
+import pyparsing as pp
+import urllib.request
+
+
+# define basic HTML tags, and compose into a Table
+table, table_end = pp.make_html_tags("table")
+thead, thead_end = pp.make_html_tags("thead")
+tbody, tbody_end = pp.make_html_tags("tbody")
+tr, tr_end = pp.make_html_tags("tr")
+th, th_end = pp.make_html_tags("th")
+td, td_end = pp.make_html_tags("td")
+a, a_end = pp.make_html_tags("a")
+
+# method to strip HTML tags from a string - will be used to clean up content of table cells
+strip_html = (pp.any_open_tag | pp.any_close_tag).suppress().transform_string
+
+# expression for parsing <a href="url">text</a> links, returning a (text, url) tuple
+link = pp.Group(a + a.tag_body("text") + a_end.suppress())
+
+
+def extract_text_and_url(t):
+    return (t0.text, t0.href)
+
+
+link.addParseAction(extract_text_and_url)
+
+
+# method to create table rows of header and data tags
+def table_row(start_tag, end_tag):
+    body = start_tag.tag_body
+    body.add_parse_action(pp.token_map(str.strip), pp.token_map(strip_html))
+    row = pp.Group(
+        tr.suppress()
+        + (start_tag.suppress() + body + end_tag.suppress())...
+        + tr_end.suppress()
+    )
+    return row
+
+
+th_row = table_row(th, th_end)
+td_row = table_row(td, td_end)
+
+# define expression for overall table - may vary slightly for different pages
+html_table = (
+    table
+    + tbody
+    + th_row...("headers")
+    + td_row...("rows")
+    + tbody_end
+    + table_end
+)
+
+
+# read in a web page containing an interesting HTML table
+with urllib.request.urlopen(
+    "https://en.wikipedia.org/wiki/List_of_tz_database_time_zones"
+) as page:
+    page_html = page.read().decode()
+
+tz_table = html_table.searchString(page_html)0
+
+# convert rows to dicts
+rows = dict(zip(tz_table.headers0, row)) for row in tz_table.rows
+
+# make a dict keyed by TZ database identifier
+# (get identifier key from second column header)
+identifier_key = tz_table.headers01
+tz_db = {rowidentifier_key: row for row in rows}
+
+from pprint import pprint
+
+pprint(tz_db"America/Chicago")
+pprint(tz_db"Zulu")

_service:tar_scm:pyparsing-3.1.1.tar.gz/examples/inv_regex.py Added

@@ -0,0 +1,311 @@
+#
+# original file: https://raw.githubusercontent.com/pyparsing/pyparsing/pyparsing_3.0.9/examples/invRegex.py
+#
+# Copyright 2008, Paul McGuire
+#
+# pyparsing script to expand a regular expression into all possible matching strings
+# Supports:
+# - {n} and {m,n} repetition, but not unbounded + or * repetition
+# - ? optional elements
+# -  character ranges
+# - () grouping
+# - | alternation
+#
+__all__ = "count", "invert"
+
+from pyparsing import (
+    Literal,
+    one_of,
+    Empty,
+    printables,
+    ParserElement,
+    Combine,
+    SkipTo,
+    infix_notation,
+    ParseFatalException,
+    Word,
+    nums,
+    OpAssoc,
+    Suppress,
+    ParseResults,
+    srange,
+)
+
+ParserElement.enablePackrat()
+
+
+class CharacterRangeEmitter:
+    def __init__(self, chars):
+        # remove duplicate chars in character range, but preserve original order
+        seen = set()
+        self.charset = "".join(seen.add(c) or c for c in chars if c not in seen)
+
+    def __str__(self):
+        return "" + self.charset + ""
+
+    def __repr__(self):
+        return "" + self.charset + ""
+
+    def make_generator(self):
+        def gen_chars():
+            yield from self.charset
+
+        return gen_chars
+
+
+class OptionalEmitter:
+    def __init__(self, expr):
+        self.expr = expr
+
+    def make_generator(self):
+        def optional_gen():
+            yield ""
+            yield from self.expr.make_generator()()
+
+        return optional_gen
+
+
+class DotEmitter:
+    def make_generator(self):
+        def dot_gen():
+            yield from printables
+
+        return dot_gen
+
+
+class GroupEmitter:
+    def __init__(self, exprs):
+        self.exprs = ParseResults(exprs)
+
+    def make_generator(self):
+        def group_gen():
+            def recurse_list(elist):
+                if len(elist) == 1:
+                    yield from elist0.make_generator()()
+                else:
+                    for s in elist0.make_generator()():
+                        for s2 in recurse_list(elist1:):
+                            yield s + s2
+
+            if self.exprs:
+                yield from recurse_list(self.exprs)
+
+        return group_gen
+
+
+class AlternativeEmitter:
+    def __init__(self, exprs):
+        self.exprs = exprs
+
+    def make_generator(self):
+        def alt_gen():
+            for e in self.exprs:
+                yield from e.make_generator()()
+
+        return alt_gen
+
+
+class LiteralEmitter:
+    def __init__(self, lit):
+        self.lit = lit
+
+    def __str__(self):
+        return "Lit:" + self.lit
+
+    def __repr__(self):
+        return "Lit:" + self.lit
+
+    def make_generator(self):
+        def lit_gen():
+            yield self.lit
+
+        return lit_gen
+
+
+def handle_range(toks):
+    return CharacterRangeEmitter(srange(toks0))
+
+
+def handle_repetition(toks):
+    toks = toks0
+    if toks1 in "*+":
+        raise ParseFatalException("", 0, "unbounded repetition operators not supported")
+    if toks1 == "?":
+        return OptionalEmitter(toks0)
+    if "count" in toks:
+        return GroupEmitter(toks0 * int(toks.count))
+    if "minCount" in toks:
+        mincount = int(toks.minCount)
+        maxcount = int(toks.maxCount)
+        optcount = maxcount - mincount
+        if optcount:
+            opt = OptionalEmitter(toks0)
+            for i in range(1, optcount):
+                opt = OptionalEmitter(GroupEmitter(toks0, opt))
+            return GroupEmitter(toks0 * mincount + opt)
+        else:
+            return toks0 * mincount
+
+
+def handle_literal(toks):
+    lit = ""
+    for t in toks:
+        if t0 == "\\":
+            if t1 == "t":
+                lit += "\t"
+            else:
+                lit += t1
+        else:
+            lit += t
+    return LiteralEmitter(lit)
+
+
+def handle_macro(toks):
+    macro_char = toks01
+    if macro_char == "d":
+        return CharacterRangeEmitter("0123456789")
+    elif macro_char == "w":
+        return CharacterRangeEmitter(srange("A-Za-z0-9_"))
+    elif macro_char == "s":
+        return LiteralEmitter(" ")
+    else:
+        raise ParseFatalException(
+            "", 0, "unsupported macro character (" + macro_char + ")"
+        )
+
+
+def handle_sequence(toks):
+    return GroupEmitter(toks0)
+
+
+def handle_dot():
+    return CharacterRangeEmitter(printables)
+
+
+def handle_alternative(toks):
+    return AlternativeEmitter(toks0)
+
+
+_parser = None
+
+
+def parser():
+    global _parser
+    if _parser is None:
+        ParserElement.set_default_whitespace_chars("")
+        lbrack, rbrack, lbrace, rbrace, lparen, rparen, colon, qmark = Literal.using_each(
+            "{}():?"
+        )
+
+        re_macro = Combine("\\" + one_of("d w s"))
+        escaped_char = ~re_macro + Combine("\\" + one_of(list(printables)))
+        re_literal_char = (
+            "".join(c for c in printables if c not in r"\{}().*?+|") + " \t"
+        )
+
+        re_range = Combine(lbrack + SkipTo(rbrack, ignore=escaped_char) + rbrack) # type: ignore 
+        re_literal = escaped_char | one_of(list(re_literal_char))
+        re_non_capture_group = Suppress("?:")
+        re_dot = Literal(".")
+        repetition = (
+            (lbrace + Word(nums)("count") + rbrace)
+            | (lbrace + Word(nums)("minCount") + "," + Word(nums)("maxCount") + rbrace)
+            | one_of(list("*+?"))
+        )
+
+        re_range.add_parse_action(handle_range)
+        re_literal.add_parse_action(handle_literal)
+        re_macro.add_parse_action(handle_macro)
+        re_dot.add_parse_action(handle_dot)
+
+        re_term = re_literal | re_range | re_macro | re_dot | re_non_capture_group
+        re_expr = infix_notation(
+            re_term,
+            
+                (repetition, 1, OpAssoc.LEFT, handle_repetition),
+                (Empty(), 2, OpAssoc.LEFT, handle_sequence),
+                (Suppress("|"), 2, OpAssoc.LEFT, handle_alternative),
+            ,
+        )
+        _parser = re_expr
+
+    return _parser
+
+
+def count(gen):
+    """Simple function to count the number of elements returned by a generator."""
+    return sum(1 for _ in gen)
+
+
+def invert(regex):
+    r"""
+    Call this routine as a generator to return all the strings that
+    match the input regular expression.
+        for s in invert(r"A-Z{3}\d{3}"):
+            print s
+    """
+    invre = GroupEmitter(parser().parseString(regex)).make_generator()
+    return invre()
+
+
+def main():
+    tests = r"""
+    A-EA
+    A-D*
+    A-D{3}
+    XA-C{3}Y
+    XA-C{3}\(
+    X\d
+    foobar\d\d
+    foobar{2}
+    foobar{2,9}
+    foobarz{2}
+    (foobar){2}
+    (01\d)|(20-5)
+    (?:01\d)|(20-5)
+    (01\d\d)|(20-4\d)|(250-5)
+    A-C{1,2}
+    A-C{0,3}
+    A-C\sA-C\sA-C
+    A-C\s?A-CA-C
+    A-C\s(A-CA-C)
+    A-C\s(A-CA-C)?
+    A-C{2}\d{2}
+    @|TH12
+    @(@|TH12)?
+    @(@|TH12|AL12|SP123|TB(10-9?|20?|3-9))?
+    @(@|TH12|AL12|SP123|TB(10-9?|20?|3-9)|OH(10-9?|20-9?|30?|4-9))?
+    ((ECMP|HA|AK)SD|HS)T
+    A-CV{2}
+    Acglmrstu|Baehikr?|Cadeflmorsu?|Dbsy|Ersu|Femr?|Gade|Hefgos?|Inr?|Kr?|Lairu|Mdgnot|Nabdeiop?|Os?|Pabdmortu?|Rabefghnu|Sbcegimnr?|Tabcehilm|Uubhopqst|U|V|W|Xe|Yb?|Znr
+    (a|b)|(x|y)
+    (a|b) (x|y)
+    ABCDEFG(?:#|##|b|bb)?(?:maj|min|m|sus|aug|dim)?0-9?(?:/ABCDEFG(?:#|##|b|bb)?)?
+    (Fri|Mon|S(atur|un)|T(hur|ue)s|Wednes)day
+    A(pril|ugust)|((Dec|Nov|Sept)em|Octo)ber|(Febr|Jan)uary|Ju(ly|ne)|Ma(rch|y)
+    """.splitlines()
+
+    for t in tests:
+        t = t.strip()
+        if not t:
+            continue
+        print("-" * 50)
+        print(t)
+        try:
+            num = count(invert(t))
+            print(num)
+            maxprint = 30
+            for s in invert(t):
+                print(s)
+                maxprint -= 1
+                if not maxprint:
+                    break
+        except ParseFatalException as pfe:
+            print(pfe.msg)
+            print("")
+            continue
+        print("")
+
+
+if __name__ == "__main__":
+    main()

_service:tar_scm:pyparsing-3.1.1.tar.gz/examples/lineno_example.py Added

@@ -0,0 +1,56 @@
+#
+# lineno_example.py
+#
+# an example of using the location value returned by pyparsing to
+# extract the line and column number of the location of the matched text,
+# or to extract the entire line of text.
+#
+# Copyright (c) 2006, Paul McGuire
+#
+import pyparsing as pp
+
+data = """Now is the time
+for all good men
+to come to the aid
+of their country."""
+
+
+# demonstrate use of lineno, line, and col in a parse action
+def report_long_words(st, locn, toks):
+    word = toks0
+    if len(word) > 3:
+        print(
+            f"Found {word!r} on line {pp.lineno(locn, st)} at column {pp.col(locn, st)}"
+        )
+        print("The full line of text was:")
+        print(f"{pp.line(locn, st)!r}")
+        print(f" {'^':>{pp.col(locn, st)}}")
+        print()
+
+
+wd = pp.Word(pp.alphas).set_parse_action(report_long_words)
+wd1, ....parse_string(data)
+
+
+# demonstrate returning an object from a parse action, containing more information
+# than just the matching token text
+class Token:
+    def __init__(self, st, locn, tok_string):
+        self.token_string = tok_string
+        self.locn = locn
+        self.source_line = pp.line(locn, st)
+        self.line_no = pp.lineno(locn, st)
+        self.col = pp.col(locn, st)
+
+    def __str__(self):
+        return f"{self.token_string!r} (line: {self.line_no}, col: {self.col})"
+
+
+def create_token_object(st, locn, toks):
+    return Token(st, locn, toks0)
+
+
+wd = pp.Word(pp.alphas).set_parse_action(create_token_object)
+
+for token_obj in wd1, ....parse_string(data):
+    print(token_obj)

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/lucene_grammar.py -> _service:tar_scm:pyparsing-3.1.1.tar.gz/examples/lucene_grammar.py Changed

@@ -2,27 +2,29 @@
 # lucene_grammar.py
 #
 # Copyright 2011, Paul McGuire
+# Updated 2023
 #
 # implementation of Lucene grammar, as described
-# at http://svn.apache.org/viewvc/lucene/dev/trunk/lucene/docs/queryparsersyntax.html
+# at https://lucene.apache.org/core/2_9_4/queryparsersyntax.html
 #
 
 import pyparsing as pp
 from pyparsing import pyparsing_common as ppc
 
-pp.ParserElement.enablePackrat()
+pp.ParserElement.enable_packrat()
 
-COLON, LBRACK, RBRACK, LBRACE, RBRACE, TILDE, CARAT = map(pp.Literal, ":{}~^")
-LPAR, RPAR = map(pp.Suppress, "()")
-and_, or_, not_, to_ = map(pp.CaselessKeyword, "AND OR NOT TO".split())
+COLON, LBRACK, RBRACK, LBRACE, RBRACE, TILDE, CARAT = pp.Literal.using_each(":{}~^")
+LPAR, RPAR = pp.Suppress.using_each("()")
+and_, or_, not_, to_ = pp.CaselessKeyword.using_each("AND OR NOT TO".split())
 keyword = and_ | or_ | not_ | to_
 
 expression = pp.Forward()
 
 valid_word = pp.Regex(
-    r'(a-zA-Z0-9*_+.-|\\\\|\\(+\-!(){}\\^"~*?:|\|\||&&))+'
+    r'(a-zA-Z0-9_.-|\\\\|\\(+\-!(){}\\^"~*?:|\|\||&&))'
+    r'(a-zA-Z0-9*_+.-|\\\\|\\(+\-!(){}\\^"~*?:|\|\||&&)|\*|\?)*'
 ).setName("word")
-valid_word.setParseAction(
+valid_word.set_parse_action(
     lambda t: t0.replace("\\\\", chr(127)).replace("\\", "").replace(chr(127), "\\")
 )
 
@@ -33,10 +35,10 @@
 integer = ppc.integer()
 proximity_modifier = pp.Group(TILDE + integer("proximity"))
 number = ppc.fnumber()
-fuzzy_modifier = TILDE + pp.Optional(number, default=0.5)("fuzzy")
+fuzzy_modifier = TILDE + pp.Opt(number, default=0.5)("fuzzy")
 
-term = pp.Forward().setName("field")
-field_name = valid_word().setName("fieldname")
+term = pp.Forward().set_name("field")
+field_name = valid_word().set_name("fieldname")
 incl_range_search = pp.Group(LBRACK - term("lower") + to_ + term("upper") + RBRACK)
 excl_range_search = pp.Group(LBRACE - term("lower") + to_ + term("upper") + RBRACE)
 range_search = incl_range_search("incl_range") | excl_range_search("excl_range")
@@ -44,26 +46,28 @@
 
 string_expr = pp.Group(string + proximity_modifier) | string
 word_expr = pp.Group(valid_word + fuzzy_modifier) | valid_word
-term << (
-    pp.Optional(field_name("field") + COLON)
+term <<= (
+    ~keyword
+    + pp.Opt(field_name("field") + COLON)
     + (word_expr | string_expr | range_search | pp.Group(LPAR + expression + RPAR))
-    + pp.Optional(boost)
+    + pp.Opt(boost)
 )
-term.setParseAction(lambda t: t if "field" in t or "boost" in t else None)
+term.set_parse_action(lambda t: t if "field" in t or "boost" in t else None)
 
-expression << pp.infixNotation(
+expression <<= pp.infixNotation(
     term,
     
-        (required_modifier | prohibit_modifier, 1, pp.opAssoc.RIGHT),
-        ((not_ | "!").setParseAction(lambda: "NOT"), 1, pp.opAssoc.RIGHT),
-        ((and_ | "&&").setParseAction(lambda: "AND"), 2, pp.opAssoc.LEFT),
+        (required_modifier | prohibit_modifier, 1, pp.OpAssoc.RIGHT),
+        ((not_ | "!").set_parse_action(lambda: "NOT"), 1, pp.OpAssoc.RIGHT),
+        ((and_ | "&&").set_parse_action(lambda: "AND"), 2, pp.OpAssoc.LEFT),
         (
-            pp.Optional(or_ | "||").setName("or").setParseAction(lambda: "OR"),
+            pp.Opt(or_ | "||").setName("or").set_parse_action(lambda: "OR"),
             2,
-            pp.opAssoc.LEFT,
+            pp.OpAssoc.LEFT,
         ),
     ,
-)
+).set_name("query expression")
+
 
 if __name__ == "__main__":
 
@@ -83,6 +87,9 @@
         title:"The Right Way" AND text:go
         title:"Do it right" AND right
         title:Do it right
+        te?t
+        test*
+        te*t
         roam~
         roam~0.8
         "jakarta apache"~10
@@ -98,6 +105,7 @@
         "jakarta apache" NOT "Apache Lucene"
         "jakarta apache" -"Apache Lucene"
         (jakarta OR apache) AND website
+        title:(+return +"pink panther")
         $1+1$\:2
         c\:\\windows
         (fieldX:xxxxx OR fieldy:xxxxxxxx)^2 AND (fieldx:the OR fieldy:foo)
@@ -162,7 +170,6 @@
         term~1.1
         A TO C
         t*erm*
-        *term*
         term term^3.0 term
         term stop^3.0 term
         term +stop term
@@ -201,11 +208,6 @@
         bar blar {a TO z}
         gack ( bar blar { a TO z})
         gack (bar blar {a TO z})
-        * TO Z
-        * TO z
-        A TO *
-        a TO *
-        * TO *
         \* TO \*
         \!blah
         \:blah
@@ -236,7 +238,8 @@
         XYZ
         (item:\\ item:ABCD\\)
         \*
-        *
+        blah*blah
+        blah?blah
         \\
         \||
         \&&
@@ -269,15 +272,9 @@
         foo:zoo*
         foo:zoo*^2
         zoo
-        foo:*
-        foo:*^2
-        *:foo
         a:the OR a:foo
         a:woo OR a:the
-        *:*
-        (*:*)
-        +*:* -*:*
-        the wizard of ozzy
+        "the wizard of ozzy"
         """
 
     failtests = r"""
@@ -288,10 +285,34 @@
 
         # multiple '^'s in term
         (sub query)^5.0^2.0 plus more
+        
+        # cannot start with * or ?
+        *term1 AND term2 
+        ?term3 OR term4
+        *
+
+        # unbounded '*' range terms
+        * TO Z
+        * TO z
+        A TO *
+        a TO *
+        * TO *
+
+        # unbounded field values
+        foo:*
+        foo:*^2
+        *:foo
+        *:*
+        (*:*)
+        +*:* -*:*        
+
         a:b:c
         a:b:c~
         a:b:c*
         a:b:c~2.0
+        """
+    # strings with backslashes still to be tested
+    z = r"""
         \+blah
         \-blah
         foo \|| bar
@@ -336,7 +357,10 @@
     success1, _ = expression.runTests(tests)
     success2, _ = expression.runTests(failtests, failureTests=True)
 
-    print("All tests:", ("FAIL", "OK")success1 and success2)
+    print("\n")
+    print(f"Success tests: {'OK' if success1 else 'FAIL'}")
+    print(f"Fail tests:    {'OK' if success2 else 'FAIL'}")
+    print(f"All tests:     {'OK' if (success1 and success2) else 'FAIL'}")
 
     if not (success1 and success2):
         import sys

_service:tar_scm:pyparsing-3.1.1.tar.gz/examples/macro_expander.py Added

@@ -0,0 +1,64 @@
+# macro_expander.py
+#
+# Example pyparsing program for performing macro expansion, similar to
+# the C pre-processor.  This program is not as fully-featured, simply
+# processing macros of the form:
+#     #def xxx yyyyy
+# and replacing xxx with yyyyy in the rest of the input string.  Macros
+# can also be composed using other macros, such as
+#     #def zzz xxx+1
+# Since xxx was previously defined as yyyyy, then zzz will be replaced
+# with yyyyy+1.
+#
+# Copyright 2007, 2023 by Paul McGuire
+#
+import pyparsing as pp
+
+# define the structure of a macro definition (the empty term is used
+# to advance to the next non-whitespace character)
+identifier = pp.common.identifier
+macro_def = "#def" + identifier("macro") + pp.empty + pp.restOfLine("value")
+
+# define a placeholder for defined macros - initially nothing
+macro_expr = pp.Forward()
+macro_expr << pp.NoMatch()
+
+# global dictionary for macro definitions
+macros = {}
+
+
+# parse action for macro definitions
+def process_macro_defn(t):
+    macro_val = macro_expander.transform_string(t.value)
+    macrost.macro = macro_val
+    macro_expr << pp.MatchFirst(map(pp.Keyword, macros))
+    return f"#def {t.macro} {macro_val}"
+
+
+# parse action to replace macro references with their respective definition
+def process_macro_ref(t):
+    return macrost0
+
+
+# attach parse actions to expressions
+macro_expr.set_parse_action(process_macro_ref)
+macro_def.set_parse_action(process_macro_defn)
+
+# define pattern for scanning through the input string
+macro_expander = macro_expr | macro_def
+
+
+# test macro substitution using transformString
+test_string = """
+    #def A 100
+    #def ALEN A+1
+
+    char AstringALEN;
+    char AAA;
+    typedef charALEN Acharbuf;
+    """
+
+print(test_string)
+print("-" * 40)
+print(macro_expander.transform_string(test_string))
+print(macros)

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/make_diagram.py -> _service:tar_scm:pyparsing-3.1.1.tar.gz/examples/make_diagram.py Changed

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/number_words.py -> _service:tar_scm:pyparsing-3.1.1.tar.gz/examples/number_words.py Changed

@@ -52,9 +52,9 @@
     )
 
     if len(names) == 1:
-        ret.setName(names0)
+        ret.set_name(names0)
     else:
-        ret.setName("{}-{}".format(names0, names-1))
+        ret.set_name(f"{names0}-{names-1}")
 
     return ret
 
@@ -66,8 +66,8 @@
     return mul(*t)
 
 
-opt_dash = pp.Optional(pp.Suppress("-")).setName("'-'")
-opt_and = pp.Optional((pp.CaselessKeyword("and") | "-").suppress()).setName("'and/-'")
+opt_dash = pp.Opt(pp.Suppress("-")).set_name("'-'")
+opt_and = pp.Opt((pp.CaselessKeyword("and") | "-").suppress()).set_name("'and/-'")
 
 units = define_numeric_word_range("one two three four five six seven eight nine", 1, 9)
 teens_only = define_numeric_word_range(
@@ -81,38 +81,38 @@
 tens = define_numeric_word_range(
     "twenty thirty forty fifty sixty seventy eighty ninety", 20, 90, 10
 )
-one_to_99 = (units | teens | (tens + pp.Optional(opt_dash + units))).setName("1-99")
-one_to_99.addParseAction(sum)
+one_to_99 = (units | teens | (tens + pp.Opt(opt_dash + units))).set_name("1-99")
+one_to_99.add_parse_action(sum)
 
 hundred = define_numeric_word_range("hundred", 100)
 thousand = define_numeric_word_range("thousand", 1000)
 
 hundreds = (units | teens_only | (tens + opt_dash + units)) + hundred
-hundreds.setName("100s")
+hundreds.set_name("100s")
 
 one_to_999 = (
-    (pp.Optional(hundreds + opt_and) + one_to_99 | hundreds).addParseAction(sum)
-).setName("1-999")
+    (pp.Opt(hundreds + opt_and) + one_to_99 | hundreds).add_parse_action(sum)
+).set_name("1-999")
 
 thousands = one_to_999 + thousand
-thousands.setName("1000s")
+thousands.set_name("1000s")
 
 # for hundreds and thousands, must scale up (multiply) accordingly
-hundreds.addParseAction(multiply)
-thousands.addParseAction(multiply)
+hundreds.add_parse_action(multiply)
+thousands.add_parse_action(multiply)
 
 numeric_expression = (
-    pp.Optional(thousands + opt_and) + pp.Optional(hundreds + opt_and) + one_to_99
-    | pp.Optional(thousands + opt_and) + hundreds
+    pp.Opt(thousands + opt_and) + pp.Opt(hundreds + opt_and) + one_to_99
+    | pp.Opt(thousands + opt_and) + hundreds
     | thousands
-).setName("numeric_words")
+).set_name("numeric_words")
 
 # sum all sub-results into total
-numeric_expression.addParseAction(sum)
+numeric_expression.add_parse_action(sum)
 
 
 if __name__ == "__main__":
-    numeric_expression.runTests(
+    numeric_expression.run_tests(
         """
         one
         seven

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/numerics.py -> _service:tar_scm:pyparsing-3.1.1.tar.gz/examples/numerics.py Changed

_service:tar_scm:pyparsing-3.1.1.tar.gz/examples/parse_python_value.py Added

@@ -0,0 +1,80 @@
+# parsePythonValue.py
+#
+# Copyright, 2006, by Paul McGuire
+#
+import pyparsing as pp
+
+
+cvtBool = lambda t: t0 == "True"
+cvtInt = lambda toks: int(toks0)
+cvtReal = lambda toks: float(toks0)
+cvtTuple = lambda toks: tuple(toks.as_list())
+cvtSet = lambda toks: set(toks.as_list())
+cvtDict = lambda toks: dict(toks.as_list())
+cvtList = lambda toks: toks.as_list()
+
+# define punctuation as suppressed literals
+lparen, rparen, lbrack, rbrack, lbrace, rbrace, colon, comma = pp.Suppress.using_each("(){}:,")
+
+integer = pp.Regex(r"+-?\d+").set_name("integer").add_parse_action(cvtInt)
+real = pp.Regex(r"+-?\d+\.\d*(Ee+-?\d+)?").set_name("real").add_parse_action(cvtReal)
+tuple_str = pp.Forward().set_name("tuple_expr")
+list_str = pp.Forward().set_name("list_expr")
+set_str = pp.Forward().set_name("set_expr")
+dict_str = pp.Forward().set_name("dict_expr")
+
+unistr = pp.unicodeString().add_parse_action(lambda t: t02:-1)
+quoted_str = pp.quotedString().add_parse_action(lambda t: t01:-1)
+bool_literal = pp.oneOf("True False", as_keyword=True).add_parse_action(cvtBool)
+none_literal = pp.Keyword("None").add_parse_action(pp.replace_with(None))
+
+list_item = (
+    real
+    | integer
+    | quoted_str
+    | unistr
+    | bool_literal
+    | none_literal
+    | pp.Group(list_str)
+    | tuple_str
+    | set_str
+    | dict_str
+).set_name("list_item")
+
+tuple_str <<= (
+    lparen + pp.Opt(pp.DelimitedList(list_item, allow_trailing_delim=True)) + rparen
+)
+tuple_str.add_parse_action(cvtTuple)
+
+set_str <<= (
+    lbrace + pp.DelimitedList(list_item, allow_trailing_delim=True) + rbrace
+)
+set_str.add_parse_action(cvtSet)
+
+list_str <<= (
+    lbrack + pp.Opt(pp.DelimitedList(list_item, allow_trailing_delim=True)) + rbrack
+)
+list_str.add_parse_action(cvtList, lambda t: t0)
+
+dict_entry = pp.Group(list_item + colon + list_item).set_name("dict_entry")
+dict_str <<= (
+    lbrace + pp.Opt(pp.DelimitedList(dict_entry, allow_trailing_delim=True)) + rbrace
+)
+dict_str.add_parse_action(cvtDict)
+
+if __name__ == "__main__":
+
+    tests = """'a', 100, ('A', 101,102), 3.14,  +2.718, 'xyzzy', -1.414 
+               {0: 2, 1: }, {0: , 1: , 2: }, {0: 1, 2}
+               { 'A':1, 'B':2, 'C': {'a': 1.2, 'b': 3.4} }
+               { 1, 2, 11, "blah" }
+               { 'A':1, 'B':2, 'C': {'a', 1.2, 'b', 3.4} }
+               3.14159
+               42
+               6.02E23
+               6.02e+023
+               1.0e-7
+               'a quoted string'"""
+
+    list_item.run_tests(tests)
+    list_item.create_diagram("parse_python_value.html")

_service:tar_scm:pyparsing-3.1.1.tar.gz/examples/parse_results_sum_example.py Added

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/pgn.py -> _service:tar_scm:pyparsing-3.1.1.tar.gz/examples/pgn.py Changed

@@ -15,11 +15,9 @@
     Forward,
     Group,
     Literal,
-    oneOf,
-    OneOrMore,
-    Optional,
+    one_of,
+    Opt,
     Suppress,
-    ZeroOrMore,
     Word,
 )
 from pyparsing import ParseException
@@ -28,19 +26,19 @@
 # define pgn grammar
 #
 
-tag = Suppress("") + Word(alphanums) + Combine(quotedString) + Suppress("")
+tag = Suppress("") + Word(alphanums) + quotedString + Suppress("")
 comment = Suppress("{") + Word(alphanums + " ") + Suppress("}")
 
 dot = Literal(".")
-piece = oneOf("K Q B N R")
-file_coord = oneOf("a b c d e f g h")
-rank_coord = oneOf("1 2 3 4 5 6 7 8")
-capture = oneOf("x :")
+piece = one_of("K Q B N R")
+file_coord = one_of("a b c d e f g h")
+rank_coord = one_of("1 2 3 4 5 6 7 8")
+capture = one_of("x :")
 promote = Literal("=")
-castle_queenside = oneOf("O-O-O 0-0-0 o-o-o")
-castle_kingside = oneOf("O-O 0-0 o-o")
+castle_queenside = one_of("O-O-O 0-0-0 o-o-o")
+castle_kingside = one_of("O-O 0-0 o-o")
 
-move_number = Optional(comment) + Word(nums) + dot
+move_number = Opt(comment) + Word(nums) + dot
 m1 = file_coord + rank_coord  # pawn move e.g. d4
 m2 = file_coord + capture + file_coord + rank_coord  # pawn capture move e.g. dxe5
 m3 = file_coord + "8" + promote + piece  # pawn promotion e.g. e8=Q
@@ -50,7 +48,7 @@
 m7 = piece + capture + file_coord + rank_coord  # piece capture move e.g. Bxh7
 m8 = castle_queenside | castle_kingside  # castling e.g. o-o
 
-check = oneOf("+ ++")
+check = one_of("+ ++")
 mate = Literal("#")
 annotation = Word("!?", max=2)
 nag = " $" + Word(nums)
@@ -58,30 +56,28 @@
 
 variant = Forward()
 half_move = (
-    Combine((m3 | m1 | m2 | m4 | m5 | m6 | m7 | m8) + Optional(decoration))
-    + Optional(comment)
-    + Optional(variant)
+    Combine((m3 | m1 | m2 | m4 | m5 | m6 | m7 | m8) + Opt(decoration))
+    + Opt(comment)
+    + Opt(variant)
 )
-move = Suppress(move_number) + half_move + Optional(half_move)
-variant << "(" + OneOrMore(move) + ")"
+move = Suppress(move_number) + half_move + Opt(half_move)
+variant << "(" + move1, ... + ")"
 # grouping the plies (half-moves) for each move: useful to group annotations, variants...
 # suggested by Paul McGuire :)
-move = Group(Suppress(move_number) + half_move + Optional(half_move))
-variant << Group("(" + OneOrMore(move) + ")")
-game_terminator = oneOf("1-0 0-1 1/2-1/2 *")
+move = Group(Suppress(move_number) + half_move + Opt(half_move))
+variant << Group("(" + move1, ... + ")")
+game_terminator = one_of("1-0 0-1 1/2-1/2 *")
 
 pgnGrammar = (
-    Suppress(ZeroOrMore(tag)) + ZeroOrMore(move) + Optional(Suppress(game_terminator))
+    Suppress(tag...) + move... + Opt(Suppress(game_terminator))
 )
 
 
 def parsePGN(pgn, bnf=pgnGrammar, fn=None):
     try:
-        return bnf.parseString(pgn)
+        return bnf.parse_string(pgn, parse_all=True)
     except ParseException as err:
-        print(err.line)
-        print(" " * (err.column - 1) + "^")
-        print(err)
+        print(err.explain())
 
 
 if __name__ == "__main__":

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/protobuf_parser.py -> _service:tar_scm:pyparsing-3.1.1.tar.gz/examples/protobuf_parser.py Changed

@@ -13,20 +13,19 @@
     Suppress,
     Forward,
     Group,
-    oneOf,
-    ZeroOrMore,
-    Optional,
-    delimitedList,
-    restOfLine,
+    one_of,
+    Opt,
+    DelimitedList,
+    rest_of_line,
     quotedString,
     Dict,
     Keyword,
 )
 
-ident = Word(alphas + "_", alphanums + "_").setName("identifier")
+ident = Word(alphas + "_", alphanums + "_").set_name("identifier")
 integer = Regex(r"+-?\d+")
 
-LBRACE, RBRACE, LBRACK, RBRACK, LPAR, RPAR, EQ, SEMI = map(Suppress, "{}()=;")
+LBRACE, RBRACE, LBRACK, RBRACK, LPAR, RPAR, EQ, SEMI = Suppress.using_each("{}()=;")
 
 kwds = """message required optional repeated enum extensions extends extend
           to package service rpc returns true false option import syntax"""
@@ -38,9 +37,9 @@
 messageDefn = MESSAGE_ - ident("messageId") + LBRACE + messageBody("body") + RBRACE
 
 typespec = (
-    oneOf(
-        """double float int32 int64 uint32 uint64 sint32 sint64
-                    fixed32 fixed64 sfixed32 sfixed64 bool string bytes"""
+    one_of(
+        "double float int32 int64 uint32 uint64 sint32 sint64"
+        " fixed32 fixed64 sfixed32 sfixed64 bool string bytes"
     )
     | ident
 )
@@ -48,12 +47,12 @@
 fieldDirective = LBRACK + Group(ident + EQ + rvalue) + RBRACK
 fieldDefnPrefix = REQUIRED_ | OPTIONAL_ | REPEATED_
 fieldDefn = (
-    Optional(fieldDefnPrefix)
+    Opt(fieldDefnPrefix)
     + typespec("typespec")
     + ident("ident")
     + EQ
     + integer("fieldint")
-    + ZeroOrMore(fieldDirective)
+    + fieldDirective...
     + SEMI
 )
 
@@ -62,7 +61,7 @@
     ENUM_("typespec")
     - ident("name")
     + LBRACE
-    + Dict(ZeroOrMore(Group(ident + EQ + integer + SEMI)))("values")
+    + Dict((Group(ident + EQ + integer + SEMI))...)("values")
     + RBRACE
 )
 
@@ -73,10 +72,10 @@
 messageExtension = EXTEND_ - ident + LBRACE + messageBody + RBRACE
 
 # messageBody ::= { fieldDefn | enumDefn | messageDefn | extensionsDefn | messageExtension }*
-messageBody << Group(
-    ZeroOrMore(
-        Group(fieldDefn | enumDefn | messageDefn | extensionsDefn | messageExtension)
-    )
+messageBody <<= Group(
+    Group(
+        fieldDefn | enumDefn | messageDefn | extensionsDefn | messageExtension
+    )...
 )
 
 # methodDefn ::= 'rpc' ident '('  ident  ')' 'returns' '('  ident  ')' ';'
@@ -84,25 +83,25 @@
     RPC_
     - ident("methodName")
     + LPAR
-    + Optional(ident("methodParam"))
+    + Opt(ident("methodParam"))
     + RPAR
     + RETURNS_
     + LPAR
-    + Optional(ident("methodReturn"))
+    + Opt(ident("methodReturn"))
     + RPAR
 )
 
 # serviceDefn ::= 'service' ident '{' methodDefn* '}'
 serviceDefn = (
-    SERVICE_ - ident("serviceName") + LBRACE + ZeroOrMore(Group(methodDefn)) + RBRACE
+    SERVICE_ - ident("serviceName") + LBRACE + Group(methodDefn)... + RBRACE
 )
 
 syntaxDefn = SYNTAX_ + EQ - quotedString("syntaxString") + SEMI
 
 # packageDirective ::= 'package' ident  '.' ident* ';'
-packageDirective = Group(PACKAGE_ - delimitedList(ident, ".", combine=True) + SEMI)
+packageDirective = Group(PACKAGE_ - DelimitedList(ident, ".", combine=True) + SEMI)
 
-comment = "//" + restOfLine
+comment = "//" + rest_of_line
 
 importDirective = IMPORT_ - quotedString("importFileSpec") + SEMI
 
@@ -120,10 +119,11 @@
     | syntaxDefn
 )
 
-parser = Optional(packageDirective) + ZeroOrMore(topLevelStatement)
+parser = Opt(packageDirective) + topLevelStatement...
 
 parser.ignore(comment)
 
+
 if __name__ == "__main__":
 
     test1 = """message Person {
@@ -168,4 +168,4 @@
     }
     """
 
-    parser.runTests(test1, test2, test3)
+    parser.run_tests(test1, test2, test3)

_service:tar_scm:pyparsing-3.1.1.tar.gz/examples/range_check.py Added

@@ -0,0 +1,111 @@
+# rangeCheck.py
+#
+#   A sample program showing how parse actions can convert parsed
+# strings into a data type or object, and to validate the parsed value.
+#
+# Updated to use new addCondition method and expr() copy.
+#
+# Copyright 2011,2015 Paul T. McGuire
+#
+
+import pyparsing as pp
+from datetime import date
+from typing import Any
+
+
+def ranged_value(
+        expr: pp.ParserElement,
+        min_val: Any = None,
+        max_val: Any = None,
+        label: str = ""
+) -> pp.ParserElement:
+
+    # have to specify at least one range boundary
+    if (min_val, max_val) == (None, None):
+        raise ValueError("min_val or max_val must be specified")
+
+    expr_label = label or "value"
+
+    # set range testing function and error message depending on
+    # whether either or both min and max values are given
+    in_range_condition = {
+        (False, True): lambda s, l, t: t0 <= max_val,
+        (True, False): lambda s, l, t: min_val <= t0,
+        (True, True): lambda s, l, t: min_val <= t0 <= max_val,
+    }min_val is not None, max_val is not None
+
+    out_of_range_message = {
+        (False, True): f"{expr_label} is greater than {max_val}",
+        (True, False): f"{expr_label} is less than {min_val}",
+        (True, True): f"{expr_label} is not in the range ({min_val} to {max_val})",
+    }min_val is not None, max_val is not None
+
+    ret = expr().add_condition(in_range_condition, message=out_of_range_message)
+
+    if label:
+        ret.set_name(label)
+
+    return ret
+
+
+# define the expressions for a date of the form YYYY/MM/DD or YYYY/MM (assumes YYYY/MM/01)
+integer = pp.Word(pp.nums).set_name("integer")
+integer.set_parse_action(lambda t: int(t0))
+
+month = ranged_value(integer, 1, 12, "month")
+day = ranged_value(integer, 1, 31, "day")
+year = ranged_value(integer, 2000, None, "year")
+
+SLASH = pp.Suppress("/")
+dateExpr = year("year") + SLASH + month("month") + pp.Opt(SLASH + day("day"))
+dateExpr.set_name("date")
+
+# convert date fields to datetime (also validates dates as truly valid dates)
+dateExpr.set_parse_action(lambda t: date(t.year, t.month, t.day or 1))
+
+# add range checking on dates
+min_date = date(2002, 1, 1)
+max_date = date.today()
+date_expr = ranged_value(dateExpr, min_date, max_date, "date")
+
+date_expr.create_diagram("range_check.html")
+
+# tests of valid dates
+success_valid_tests, _ = date_expr.run_tests(
+    """
+    # valid date
+    2011/5/8
+    
+    # leap day
+    2004/2/29
+
+    # default day of month to 1
+    2004/2
+    """
+)
+
+# tests of invalid dates
+success_invalid_tests, _ = date_expr.run_tests(
+    """
+    # all values are in range, but date is too early
+    2001/1/1
+
+    # not a leap day
+    2005/2/29
+
+    # year number is < 2000
+    1999/12/31
+
+    # bad year field
+    XXXX/1/1
+
+    # bad month field
+    2010/XX/1
+
+    # bad day field
+    2010/11/XX
+    """,
+    failure_tests=True
+)
+
+assert (success_valid_tests and success_invalid_tests)

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/readJson.py -> _service:tar_scm:pyparsing-3.1.1.tar.gz/examples/readJson.py Changed

@@ -1895,22 +1895,24 @@
 {"last_update":"1191595695", "numofapproved":"1", "id":"11621"},
 {"last_update":"1193105000", "numofapproved":"1", "id":"13421"},
 {"last_update":"1195104657", "numofapproved":"1", "id":"16701"},
-"request_timestamp":1206363392.08521, "request_call":"requestDetails",
-"instance":"tbedi", "call_time":"0.10059", "request_date":"2008-03-2412:56:32 UTC", "request_url":"http://cmsdoc.cern.ch/cms/test/aprom/phedex/dev/gowri/datasvc/tbedi/requestDetails?format=json"}}
+"request_timestamp":1206363392.08521,
+"request_call":"requestDetails",
+"instance":"tbedi",
+"call_time":"0.10059",
+"request_date":"2008-03-2412:56:32 UTC",
+"request_url":"http://cmsdoc.cern.ch/cms/test/aprom/phedex/dev/gowri/datasvc/tbedi/requestDetails?format=json"}}
 """
 
 from jsonParser import jsonObject
 
-data = jsonObject.parseString(s)
+data = jsonObject.parseString(s)0
 
-# ~ from pprint import pprint
-# ~ pprint( data0.asList() )
-# ~ print
-# ~ print data.dump()
-print(data.phedex.call_time)
-print(data.phedex.instance)
-print(data.phedex.request_call)
-print(len(data.phedex.request))
-for req in data.phedex.request:10:
-    # ~ print req.dump()
-    print("-", req.id, req.last_update)
+# from pprint import pprint
+# pprint(data)
+# print()
+print(data"phedex""call_time")
+print(data"phedex""instance")
+print(data"phedex""request_call")
+print(len(data"phedex""request"))
+for req in data"phedex""request":10:
+    print("-", req"id", req"last_update")

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/rosettacode.py -> _service:tar_scm:pyparsing-3.1.1.tar.gz/examples/rosettacode.py Changed

@@ -50,46 +50,20 @@
 string = pp.QuotedString('"', convertWhitespaceEscapes=False).setName("quoted string")
 char = pp.Regex(r"'\\?.'")
 
+# fmt: off
 expr = pp.infixNotation(
     identifier | integer | char,
     
-        (
-            pp.oneOf("+ - !"),
-            1,
-            pp.opAssoc.RIGHT,
-        ),
-        (
-            pp.oneOf("* / %"),
-            2,
-            pp.opAssoc.LEFT,
-        ),
-        (
-            pp.oneOf("+ -"),
-            2,
-            pp.opAssoc.LEFT,
-        ),
-        (
-            pp.oneOf("< <= > >="),
-            2,
-            pp.opAssoc.LEFT,
-        ),
-        (
-            pp.oneOf("== !="),
-            2,
-            pp.opAssoc.LEFT,
-        ),
-        (
-            pp.oneOf("&&"),
-            2,
-            pp.opAssoc.LEFT,
-        ),
-        (
-            pp.oneOf("||"),
-            2,
-            pp.opAssoc.LEFT,
-        ),
+        (pp.oneOf("+ - !"), 1, pp.opAssoc.RIGHT,),
+        (pp.oneOf("* / %"), 2, pp.opAssoc.LEFT, ),
+        (pp.oneOf("+ -"), 2, pp.opAssoc.LEFT, ),
+        (pp.oneOf("< <= > >="), 2, pp.opAssoc.LEFT, ),
+        (pp.oneOf("== !="), 2, pp.opAssoc.LEFT, ),
+        (pp.oneOf("&&"), 2, pp.opAssoc.LEFT, ),
+        (pp.oneOf("||"), 2, pp.opAssoc.LEFT, ),
     ,
 )
+# fmt: on
 
 prt_list = pp.Group(pp.delimitedList(string | expr))
 paren_expr = pp.Group(LPAR + expr + RPAR)
@@ -300,15 +274,14 @@
     """,
 
 
-import sys
 
-sys.setrecursionlimit(2000)
+def main():
+    import sys
+    sys.setrecursionlimit(2000)
 
-for test in tests:
-    try:
-        results = code.parseString(test)
-    except pp.ParseException as pe:
-        pp.ParseException.explain(pe)
-    else:
-        results.pprint()
-    print()
+    success, report = code.run_tests(tests)
+    assert success
+
+
+if __name__ == '__main__':
+    main()
\ No newline at end of file

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/stackish.py -> _service:tar_scm:pyparsing-3.1.1.tar.gz/examples/stackish.py Changed

@@ -28,72 +28,60 @@
     separation character and perform reasonable diffs on two structures.
 """
 
-from pyparsing import (
-    Suppress,
-    Word,
-    nums,
-    alphas,
-    alphanums,
-    Combine,
-    oneOf,
-    Optional,
-    QuotedString,
-    Forward,
-    Group,
-    ZeroOrMore,
-    srange,
-    pyparsing_common as ppc,
-)
+import pyparsing as pp
+ppc = pp.common
 
-MARK, UNMARK, AT, COLON, QUOTE = map(Suppress, "@:'")
+MARK, UNMARK, AT, COLON, QUOTE = pp.Suppress.using_each("@:'")
 
 NUMBER = ppc.integer()
 FLOAT = ppc.real()
-STRING = QuotedString('"', multiline=True) | QuotedString("'", multiline=True)
-WORD = Word(alphas, alphanums + "_:")
-ATTRIBUTE = Combine(AT + WORD)
+STRING = pp.QuotedString('"', multiline=True) | pp.QuotedString("'", multiline=True)
+WORD = pp.DelimitedList(pp.Word(pp.alphas, pp.alphanums + "_"), delim=":", combine=True)
+ATTRIBUTE = pp.Combine(AT + WORD)
 
-strBody = Forward()
+str_body = pp.Forward()
 
 
-def setBodyLength(tokens):
-    strBody << Word(srange(r"\0x00-\0xffff"), exact=int(tokens0))
+def set_body_length(tokens):
+    str_body << pp.Word(pp.srange(r"\0x00-\0xffff"), exact=int(tokens0))
     return ""
 
 
-BLOB = Combine(
-    QUOTE + Word(nums).setParseAction(setBodyLength) + COLON + strBody + QUOTE
+BLOB = pp.Combine(
+    QUOTE + pp.Word(pp.nums).set_parse_action(set_body_length) + COLON + str_body + QUOTE
 )
 
-item = Forward()
-
 
-def assignUsing(s):
-    def assignPA(tokens):
+def assign_using(s):
+    def assign_pa(tokens):
         if s in tokens:
             tokenstokenss = tokens0
             del tokenss
 
-    return assignPA
+    return assign_pa
 
 
+item = pp.Forward()
+
 GROUP = (
     MARK
-    + Group(
-        ZeroOrMore(
-            (item + Optional(ATTRIBUTE)("attr")).setParseAction(assignUsing("attr"))
-        )
+    + pp.Group(
+        (item + ATTRIBUTE0, 1("attr")).set_parse_action(assign_using("attr"))...
     )
     + (WORD("name") | UNMARK)
-).setParseAction(assignUsing("name"))
+).set_parse_action(assign_using("name"))
 item <<= FLOAT | NUMBER | STRING | BLOB | GROUP
 
-item.runTests(
-    """\
-     '10:1234567890' @name 25 @age +0.45 @percentage person:zed
-      "hello" 1 child root
-     "child"  200 '4:like' "I" "hello" things root
-      "data"  2 1  @numbers child root
-      1 2 3  @test 4 5 6 root
-    """
-)
+if __name__ == '__main__':
+
+    success, _ = item.run_tests(
+        """\
+         '10:1234567890' @name 25 @age +0.45 @percentage person:zed
+          "hello" 1 child root
+         "child"  200 '4:like' "I" "hello" things root
+          "data"  2 1  @numbers child root
+          1 2 3  @test 4 5 6 root
+        """
+    )
+
+    assert success

_service:tar_scm:pyparsing-3.1.1.tar.gz/examples/tag_emitter.py Added

@@ -0,0 +1,34 @@
+#
+# tag_emitter.py
+#
+# Example showing how to inject tags into the parsed results by adding
+# an Empty() with a parse action to return the desired added data.
+#
+# Copyright 2023, Paul McGuire
+#
+import pyparsing as pp
+
+# define expressions to parse different forms of integer constants
+# add parse actions that will evaluate the integer correctly
+binary_int = ("0b" + pp.Word("01")).add_parse_action(lambda t: int(t1, base=2))
+hex_int = ("0x" + pp.Word(pp.hexnums)).add_parse_action(lambda t: int(t1, base=16))
+dec_int = pp.Word(pp.nums).add_parse_action(lambda t: int(t0))
+
+
+# define function to inject an expression that will add an extra tag in the
+# parsed output, to indicate what the original input format was
+def emit_tag(s):
+    return pp.Empty().add_parse_action(pp.replace_with(s))
+
+
+# define a parser that includes the tag emitter for each integer format type
+int_parser = (binary_int("value") + emit_tag("binary")("original_format")
+              | hex_int("value") + emit_tag("hex")("original_format")
+              | dec_int("value") + emit_tag("decimal")("original_format")
+              )
+
+# parse some integers
+int_parser.run_tests("""\
+    0b11011000001
+    0x6c1
+    1729""")

_service:tar_scm:pyparsing-3.0.9.tar.gz/examples/unicode_denormalizer.py -> _service:tar_scm:pyparsing-3.1.1.tar.gz/examples/unicode_denormalizer.py Changed

@@ -24,64 +24,102 @@
 import pyparsing as pp
 ppu = pp.pyparsing_unicode
 
-ident_chars = "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz_0123456789·"
-
-ident_char_map = {}.fromkeys(ident_chars, "")
-for ch in ppu.identbodychars:
+_· = "_·"
+ident_chars = (
+    "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz"
+    + "0123456789" + _·
+)
+
+# build map of each ASCII character to a string of
+# all the characters in the Basic Multilingual Plane
+# that NFKC normalizes back to that ASCII character
+ident_char_map = {c:  for c in ident_chars}
+for ch in ppu.BMP.identbodychars:
     normal = unicodedata.normalize("NFKC", ch)
     if normal in ident_char_map:
-        ident_char_mapnormal += ch
+        ident_char_mapnormal.append(ch)
 
+# ligatures will also normalize back to ASCII
+# (doubled elements have higher chance of being chosen by random.choice)
 ligature_map = {
-    'ffl': 'ﬄ ﬄ ﬀl fﬂ ffl',
-    'ffi': 'ﬃ ﬃ ﬀi fﬁ ffi',
-    'ff': 'ﬀ ff',
-    'fi': 'ﬁ fi',
-    'fl': 'ﬂ fl',
-
-    'ij': 'ij ĳ',
-    'lj': 'lj ǉ',
-    'nj': 'nj ǌ',
-    'dz': 'dz ǳ',
-    'ii': 'ii ⅱ',
-    'iv': 'iv ⅳ',
-    'vi': 'vi ⅵ',
-    'ix': 'ix ⅸ',
-    'xi': 'xi ⅺ',
+    'IJ': ('Ĳ', 'Ĳ', 'IJ'),
+    'LJ': ('Ǉ', 'Ǉ', 'LJ'),
+    'NJ': ('Ǌ', 'Ǌ', 'NJ'),
+    'DZ': ('Ǳ', 'Ǳ', 'DZ'),
+    'II': ('Ⅱ', 'Ⅱ', 'II'),
+    'IV': ('Ⅳ', 'Ⅳ', 'IV'),
+    'VI': ('Ⅵ', 'Ⅵ', 'VI'),
+    'IX': ('Ⅸ', 'Ⅸ', 'IX'),
+    'XI': ('Ⅺ', 'Ⅺ', 'XI'),
+    'ffl': ('ﬄ', 'ﬄ', 'ﬀl', 'fﬂ', 'ffl'),
+    'ffi': ('ﬃ', 'ﬃ', 'ﬀi', 'fﬁ', 'ffi'),
+    'ff': ('ﬀ', 'ﬀ', 'ff'),
+    'fi': ('ﬁ', 'ﬁ', 'fi'),
+    'fl': ('ﬂ', 'ﬂ', 'fl'),
+    'ij': ('ĳ', 'ĳ', 'ij'),
+    'lj': ('ǉ', 'ǉ', 'lj'),
+    'nj': ('ǌ', 'ǌ', 'nj'),
+    'dz': ('ǳ', 'ǳ', 'dz'),
+    'ii': ('ⅱ', 'ⅱ', 'ii'),
+    'iv': ('ⅳ', 'ⅳ', 'iv'),
+    'vi': ('ⅵ', 'ⅵ', 'vi'),
+    'ix': ('ⅸ', 'ⅸ', 'ix'),
+    'xi': ('ⅺ', 'ⅺ', 'xi'),
 }
-ligature_transformer = pp.oneOf(ligature_map).add_parse_action(lambda t: random.choice(ligature_mapt0.split()))
+
+ligature_transformer = pp.one_of(ligature_map).add_parse_action(
+    lambda t: random.choice(ligature_mapt0)
+)
 
 
 def make_mixed_font(t):
-    t_0 = t00
-    ret = '_' if t_0 == '_' else random.choice(ident_char_map.get(t_0, t_0))
-    t_rest = ligature_transformer.transform_string(t01:)
+    # extract leading character and remainder to process separately
+    t_first, t_rest = t00, t01:
+
+    # a leading '_' must be written using the ASCII character '_'
+    ret = '_' if t_first == '_'
+           else random.choice(ident_char_map.get(t_first, t_first))
+    t_rest = ligature_transformer.transform_string(t_rest)
     ret.extend(random.choice(ident_char_map.get(c, c)) for c in t_rest)
     return ''.join(ret)
 
 
+# define a pyparsing expression to match any identifier; add a parse
+# action to convert to mixed Unicode characters
 identifier = pp.pyparsing_common.identifier
 identifier.add_parse_action(make_mixed_font)
 
+# match quoted strings (which may be f-strings)
 python_quoted_string = pp.Opt(pp.Char("fF")("f_string_prefix")) + (
-        pp.quotedString
-        | pp.QuotedString('"""', multiline=True, unquoteResults=False)
-        | pp.QuotedString("'''", multiline=True, unquoteResults=False)
+        pp.python_quoted_string
 )("quoted_string_body")
 
 
 def mix_fstring_expressions(t):
     if not t.f_string_prefix:
         return
+
+    # define an expression and transformer to handle embedded
+    # f-string field expressions
     fstring_arg = pp.QuotedString("{", end_quote_char="}")
-    fstring_arg.add_parse_action(lambda tt: "{" + transformer.transform_string(tt0) + "}")
-    ret = t.f_string_prefix + fstring_arg.transform_string(t.quoted_string_body)
-    return ret
+    fstring_arg.add_parse_action(
+        lambda tt: "{" + transformer.transform_string(tt0) + "}"
+    )
 
+    return (
+        t.f_string_prefix
+        + fstring_arg.transform_string(t.quoted_string_body)
+    )
 
+# add parse action to transform identifiers in f-strings
 python_quoted_string.add_parse_action(mix_fstring_expressions)
 
-any_keyword = pp.MatchFirst(map(pp.Keyword, list(keyword.kwlist) + getattr(keyword, "softkwlist", )))
+# match keywords separately from identifiers - keywords must be kept in their
+# original ASCII
+any_keyword = pp.one_of(
+    list(keyword.kwlist) + getattr(keyword, "softkwlist", ),
+    as_keyword=True
+)
 
 # quoted strings and keywords will be parsed, but left untransformed
 transformer = python_quoted_string | any_keyword | identifier
@@ -101,16 +139,16 @@
     if __name__ == "__main__":
         hello()
     """)
-    source = hello_source
 
-    transformed = transformer.transform_string(source)
+    # use transformer to generate code with denormalized identifiers
+    transformed = transformer.transform_string(hello_source)
     print(transformed)
 
-    # does it really work?
-    code = compile(transformed, source, mode="exec")
+    # does it really work? compile the transformed code and run it!
+    code = compile(transformed, "inline source", mode="exec")
     exec(code)
 
-    if 0:
+    if 1:
         # pick some code from the stdlib
         import unittest.util as lib_module
         import inspect

_service:tar_scm:pyparsing-3.1.1.tar.gz/examples/verilog_parse.py Added

@@ -0,0 +1,946 @@
+#
+# verilogParse.py
+#
+# an example of using the pyparsing module to be able to process Verilog files
+# uses BNF defined at http://www.verilog.com/VerilogBNF.html
+#
+#    Copyright (c) 2004-2011 Paul T. McGuire.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining
+# a copy of this software and associated documentation files (the
+# "Software"), to deal in the Software without restriction, including
+# without limitation the rights to use, copy, modify, merge, publish,
+# distribute, sublicense, and/or sell copies of the Software, and to
+# permit persons to whom the Software is furnished to do so, subject to
+# the following conditions:
+#
+# The above copyright notice and this permission notice shall be
+# included in all copies or substantial portions of the Software.
+#
+# If you find this software to be useful, please make a donation to one
+# of the following charities:
+# - the Red Cross (https://www.redcross.org/)
+# - Hospice Austin (https://www.hospiceaustin.org/)
+#
+#    DISCLAIMER:
+#    THIS SOFTWARE IS PROVIDED BY PAUL T. McGUIRE ``AS IS'' AND ANY EXPRESS OR
+#    IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+#    MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO
+#    EVENT SHALL PAUL T. McGUIRE OR CO-CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+#    INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+#    BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OFUSE,
+#    DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+#    OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+#    NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+#    EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#    For questions or inquiries regarding this license, or commercial use of
+#    this software, contact the author via e-mail: ptmcg@users.sourceforge.net
+#
+# Todo:
+#  - add pre-process pass to implement compilerDirectives (ifdef, include, etc.)
+#
+# Revision History:
+#
+#   1.0   - Initial release
+#   1.0.1 - Fixed grammar errors:
+#           . real declaration was incorrect
+#           . tolerant of '=>' for '*>' operator
+#           . tolerant of '?' as hex character
+#           . proper handling of mintypmax_expr within path delays
+#   1.0.2 - Performance tuning (requires pyparsing 1.3)
+#   1.0.3 - Performance updates, using Regex (requires pyparsing 1.4)
+#   1.0.4 - Performance updates, enable packrat parsing (requires pyparsing 1.4.2)
+#   1.0.5 - Converted keyword Literals to Keywords, added more use of Group to
+#           group parsed results tokens
+#   1.0.6 - Added support for module header with no ports list (thanks, Thomas Dejanovic!)
+#   1.0.7 - Fixed erroneous '<<' Forward definition in timCheckCond, omitting ()'s
+#   1.0.8 - Re-released under MIT license
+#   1.0.9 - Enhanced udpInstance to handle identifiers with leading '\' and subscripting
+#   1.0.10 - Fixed change added in 1.0.9 to work for all identifiers, not just those used
+#           for udpInstance.
+#   1.0.11 - Fixed bug in inst_args, content alternatives were reversed
+#   1.1.0 - Some performance fixes, convert most literal strs to Keywords
+#
+from pathlib import Path
+import pprint
+import time
+
+__version__ = "1.1.0"
+
+__all__ = "__version__", "verilogbnf"
+
+from pyparsing import (
+    Literal,
+    Keyword,
+    Word,
+    Forward,
+    DelimitedList,
+    Group,
+    Optional,
+    Combine,
+    alphas,
+    nums,
+    restOfLine,
+    alphanums,
+    dbl_quoted_string,
+    empty,
+    ParseException,
+    one_of,
+    StringEnd,
+    FollowedBy,
+    ParserElement,
+    Regex,
+    cppStyleComment,
+)
+import pyparsing
+
+usePackrat = True
+
+packratOn = False
+if usePackrat:
+    try:
+        ParserElement.enable_packrat()
+    except Exception:
+        pass
+    else:
+        packratOn = True
+
+
+verilogbnf = None
+
+
+def make_verilog_bnf():
+    global verilogbnf
+
+    if verilogbnf is None:
+
+        # compiler directives
+        compilerDirective = Combine(
+            "`"
+            + one_of(
+                "define undef ifdef else endif default_nettype"
+                " include resetall timescale unconnected_drive"
+                " nounconnected_drive celldefine endcelldefine",
+                as_keyword=True,
+            )
+            + restOfLine
+        ).set_name("compilerDirective")
+
+        # primitives
+        (
+            SEMI,
+            COLON,
+            LPAR,
+            RPAR,
+            LBRACE,
+            RBRACE,
+            LBRACK,
+            RBRACK,
+            DOT,
+            COMMA,
+            EQ,
+        ) = Literal.using_each(";:(){}.,=")
+
+        identLead = alphas + "$_"
+        identBody = alphanums + "$_"
+        identifier1 = Regex(
+            rf"\.?{identLead}{identBody}*(\.{identLead}{identBody}*)*"
+        ).set_name("baseIdent")
+        identifier2 = (
+            Regex(r"\\\S+").setParseAction(lambda t: t01:).set_name("escapedIdent")
+        )  # .setDebug()
+        identifier = identifier1 | identifier2
+        assert identifier2 == r"\abc"
+
+        hexnums = nums + "abcdefABCDEF" + "_?"
+        base = Regex("'bBoOdDhH").set_name("base")
+        basedNumber = Combine(
+            (Word(nums + "_") | "") + base + Word(hexnums + "xXzZ"),
+            joinString=" ",
+            adjacent=False,
+        ).set_name("basedNumber")
+        # number = ( basedNumber | Combine( Word( "+-"+spacedNums, spacedNums ) +
+        # Optional( DOT + Optional( Word( spacedNums ) ) ) +
+        # Optional( e + Word( "+-"+spacedNums, spacedNums ) ) ).set_name("numeric") )
+        number = (
+            basedNumber | Regex(r"+-?0-9_+(\.0-9_*)?(Ee+-?0-9_+)?")
+        ).set_name("numeric")
+
+        expr = Forward().set_name("expr")
+        concat = Group(LBRACE + DelimitedList(expr) + RBRACE)
+        multiConcat = Group("{" + expr + concat + "}").set_name("multiConcat")
+        funcCall = Group(
+            identifier + LPAR + (DelimitedList(expr) | "") + RPAR
+        ).set_name("funcCall")
+
+        subscrRef = Group(LBRACK + DelimitedList(expr, COLON) + RBRACK)
+        subscrIdentifier = Group(identifier + (subscrRef | ""))
+        # scalarConst = "0" | (( FollowedBy('1') + one_of("1'b0 1'b1 1'bx 1'bX 1'B0 1'B1 1'Bx 1'BX 1") ))
+        scalarConst = Regex("0|1('Bb01xX)?")
+        mintypmaxExpr = Group(expr + COLON + expr + COLON + expr).set_name("mintypmax")
+        primary = (
+            number
+            | (LPAR + mintypmaxExpr + RPAR)
+            | (LPAR + Group(expr) + RPAR).set_name("nestedExpr")
+            | multiConcat
+            | concat
+            | dbl_quoted_string
+            | funcCall
+            | subscrIdentifier
+        )
+
+        unop = one_of("+  -  !  ~  &  ~&  |  ^|  ^  ~^").set_name("unop")
+        binop = one_of(
+            "+  -  *  /  %  ==  !=  ===  !==  &&  "
+            "||  <  <=  >  >=  &  |  ^  ^~  >>  << ** <<< >>>"
+        ).set_name("binop")
+
+        expr <<= (
+            (unop + expr)
+            | (primary + "?" + expr + COLON + expr)  # must be first!
+            | (primary + ((binop + expr) | ""))
+        )
+
+        lvalue = subscrIdentifier | concat
+
+        # keywords
+        reg = Keyword("reg")
+        trireg = Keyword("trireg")
+        signed = Keyword("signed")
+        parameter = Keyword("parameter")
+        input_, output, inout = Keyword.using_each("input output inout".split())
+        time = Keyword("time")
+        integer = Keyword("integer")
+        real = Keyword("real")
+        event = Keyword("event")
+        scalared = Keyword("scalared")
+        vectored = Keyword("vectored")
+        if_ = Keyword("if")
+        else_ = Keyword("else")
+        always = Keyword("always")
+        initial = Keyword("initial")
+        small, medium, large = Keyword.using_each("small medium large".split())
+        edge = Keyword("edge")
+        posedge = Keyword("posedge")
+        negedge = Keyword("negedge")
+        specify, endspecify = Keyword.using_each("specify endspecify".split())
+        primitive, endprimitive = Keyword.using_each("primitive endprimitive".split())
+        fork = Keyword("fork")
+        join = Keyword("join")
+        begin = Keyword("begin")
+        end = Keyword("end")
+        default = Keyword("default")
+        forever = Keyword("forever")
+        repeat = Keyword("repeat")
+        while_ = Keyword("while")
+        for_ = Keyword("for")
+        case = one_of("case casez casex", as_keyword=True)
+        endcase = Keyword("endcase")
+        wait = Keyword("wait")
+        disable = Keyword("disable")
+        deassign = Keyword("deassign")
+        force = Keyword("force")
+        release = Keyword("release")
+        assign = Keyword("assign")
+        table, endtable = Keyword.using_each("table endtable".split())
+        function, endfunction = Keyword.using_each("function endfunction".split())
+        task, endtask = Keyword.using_each("task endtask".split())
+        module, macromodule, endmodule = Keyword.using_each(
+            "module macromodule endmodule".split()
+        )
+
+        eventExpr = Forward()
+        eventTerm = (
+            (posedge + expr) | (negedge + expr) | expr | (LPAR + eventExpr + RPAR)
+        )
+        eventExpr <<= Group(DelimitedList(eventTerm, Keyword("or")))
+        eventControl = Group(
+            "@" + ((LPAR + eventExpr + RPAR) | identifier | "*")
+        ).set_name("eventCtrl")
+
+        delayArg = (
+            number
+            | Word(alphanums + "$_")
+            | (LPAR + Group(DelimitedList(mintypmaxExpr | expr)) + RPAR)  # identifier |
+        ).set_name(
+            "delayArg"
+        )  # .setDebug()
+        delay = Group("#" + delayArg).set_name("delay")  # .setDebug()
+        delayOrEventControl = delay | eventControl
+
+        assgnmt = Group(lvalue + EQ + (delayOrEventControl | "") + expr).set_name(
+            "assgnmt"
+        )
+        nbAssgnmt = Group(
+            (lvalue + "<=" + (delay | "") + expr)
+            | (lvalue + "<=" + (eventControl | "") + expr)
+        ).set_name("nbassgnmt")
+
+        range_ = LBRACK + expr + COLON + expr + RBRACK
+
+        paramAssgnmt = Group(identifier + EQ + expr).set_name("paramAssgnmt")
+        parameterDecl = Group(
+            parameter + (range_ | "") + DelimitedList(paramAssgnmt) + SEMI
+        ).set_name("paramDecl")
+
+        inputDecl = Group(input_ + (range_ | "") + DelimitedList(identifier) + SEMI)
+        outputDecl = Group(output + (range_ | "") + DelimitedList(identifier) + SEMI)
+        inoutDecl = Group(inout + (range_ | "") + DelimitedList(identifier) + SEMI)
+
+        regIdentifier = Group(identifier + (LBRACK + expr + COLON + expr + RBRACK | ""))
+        regDecl = Group(
+            reg + (signed | "") + (range_ | "") + DelimitedList(regIdentifier) + SEMI
+        ).set_name("regDecl")
+        timeDecl = Group(time + DelimitedList(regIdentifier) + SEMI)
+        integerDecl = Group(integer + DelimitedList(regIdentifier) + SEMI)
+
+        strength0 = one_of("supply0  strong0  pull0  weak0  highz0", as_keyword=True)
+        strength1 = one_of("supply1  strong1  pull1  weak1  highz1", as_keyword=True)
+        driveStrength = Group(
+            LPAR
+            + ((strength0 + COMMA + strength1) | (strength1 + COMMA + strength0))
+            + RPAR
+        ).set_name("driveStrength")
+        nettype = one_of(
+            "wire  tri  tri1  supply0  wand  triand  tri0  supply1  wor  trior  trireg",
+            as_keyword=True,
+        )
+        expandRange = (scalared | vectored | "") + range_
+        realDecl = Group(real + DelimitedList(identifier) + SEMI)
+
+        eventDecl = Group(event + DelimitedList(identifier) + SEMI)
+
+        blockDecl = (
+            parameterDecl | regDecl | integerDecl | realDecl | timeDecl | eventDecl
+        )
+
+        stmt = Forward().set_name("stmt")  # .setDebug()
+        stmtOrNull = stmt | SEMI
+        caseItem = (DelimitedList(expr) + COLON + stmtOrNull) | (
+            default + Optional(":") + stmtOrNull
+        )
+        stmt <<= Group(
+            (begin + Group(stmt...:end) + end).set_name("begin-end")
+            | (
+                if_ + Group(LPAR + expr + RPAR) + stmtOrNull + (else_ + stmtOrNull | "")
+            ).set_name("if")
+            | (delayOrEventControl + stmtOrNull)
+            | (case + LPAR + expr + RPAR + caseItem1, ... + endcase)
+            | (forever + stmt)
+            | (repeat + LPAR + expr + RPAR + stmt)
+            | (while_ + LPAR + expr + RPAR + stmt)
+            | (
+                for_
+                + LPAR
+                + assgnmt
+                + SEMI
+                + Group(expr)
+                + SEMI
+                + assgnmt
+                + RPAR
+                + stmt
+            )
+            | (fork + stmt... + join)
+            | (fork + COLON + identifier + blockDecl... + stmt... + end)
+            | (wait + LPAR + expr + RPAR + stmtOrNull)
+            | ("->" + identifier + SEMI)
+            | (disable + identifier + SEMI)
+            | (assign + assgnmt + SEMI)
+            | (deassign + lvalue + SEMI)
+            | (force + assgnmt + SEMI)
+            | (release + lvalue + SEMI)
+            | (begin + COLON + identifier + blockDecl... + stmt... + end).set_name(
+                "begin:label-end"
+            )
+            |
+            # these  *have* to go at the end of the list!!!
+            (assgnmt + SEMI)
+            | (nbAssgnmt + SEMI)
+            | (
+                Combine(Optional("$") + identifier)
+                + (LPAR + DelimitedList(expr | empty) + RPAR | "")
+                + SEMI
+            )
+        ).set_name("stmtBody")
+        """
+        x::=<blocking_assignment> ;
+        x||= <non_blocking_assignment> ;
+        x||= if ( <expression> ) <statement_or_null>
+        x||= if ( <expression> ) <statement_or_null> else <statement_or_null>
+        x||= case ( <expression> ) <case_item>+ endcase
+        x||= casez ( <expression> ) <case_item>+ endcase
+        x||= casex ( <expression> ) <case_item>+ endcase
+        x||= forever <statement>
+        x||= repeat ( <expression> ) <statement>
+        x||= while ( <expression> ) <statement>
+        x||= for ( <assignment> ; <expression> ; <assignment> ) <statement>
+        x||= <delay_or_event_control> <statement_or_null>
+        x||= wait ( <expression> ) <statement_or_null>
+        x||= -> <name_of_event> ;
+        x||= <seq_block>
+        x||= <par_block>
+        x||= <task_enable>
+        x||= <system_task_enable>
+        x||= disable <name_of_task> ;
+        x||= disable <name_of_block> ;
+        x||= assign <assignment> ;
+        x||= deassign <lvalue> ;
+        x||= force <assignment> ;
+        x||= release <lvalue> ;
+        """
+        alwaysStmt = Group(always + (eventControl | "") + stmt).set_name("alwaysStmt")
+        initialStmt = Group(initial + stmt).set_name("initialStmt")
+
+        chargeStrength = Group(LPAR + (small | medium | large) + RPAR).set_name(
+            "chargeStrength"
+        )
+
+        continuousAssign = Group(
+            assign + (driveStrength | "") + (delay | "") + DelimitedList(assgnmt) + SEMI
+        ).set_name("continuousAssign")
+
+        tfDecl = (
+            parameterDecl
+            | inputDecl
+            | outputDecl
+            | inoutDecl
+            | regDecl
+            | timeDecl
+            | integerDecl
+            | realDecl
+        )
+
+        functionDecl = Group(
+            function
+            + (range_ | "integer" | "real" | "")
+            + identifier
+            + SEMI
+            + Group(tfDecl1, ...)
+            + Group(stmt...)
+            + endfunction
+        )
+
+        inputOutput = input_ | output
+        netDecl1Arg = (
+            nettype
+            + (expandRange | "")
+            + (delay | "")
+            + Group(DelimitedList(~inputOutput + identifier))
+        )
+        netDecl2Arg = (
+            trireg
+            + (chargeStrength | "")
+            + (expandRange | "")
+            + (delay | "")
+            + Group(DelimitedList(~inputOutput + identifier))
+        )
+        netDecl3Arg = (
+            nettype
+            + (driveStrength | "")
+            + (expandRange | "")
+            + (delay | "")
+            + Group(DelimitedList(assgnmt))
+        )
+        netDecl1 = Group(netDecl1Arg + SEMI).set_name("netDecl1")
+        netDecl2 = Group(netDecl2Arg + SEMI).set_name("netDecl2")
+        netDecl3 = Group(netDecl3Arg + SEMI).set_name("netDecl3")
+
+        gateType = one_of(
+            "and  nand  or  nor xor  xnor buf  bufif0 bufif1 "
+            "not  notif0 notif1  pulldown pullup nmos  rnmos "
+            "pmos rpmos cmos rcmos   tran rtran  tranif0  "
+            "rtranif0  tranif1 rtranif1",
+            as_keyword=True,
+        )
+        gateInstance = (
+            (Group(identifier + (range_ | "")) | "")
+            + LPAR
+            + Group(DelimitedList(expr))
+            + RPAR
+        )
+        gateDecl = Group(
+            gateType
+            + (driveStrength | "")
+            + (delay | "")
+            + DelimitedList(gateInstance)
+            + SEMI
+        )
+
+        udpInstance = Group(
+            Group(identifier + (range_ | subscrRef | ""))
+            + LPAR
+            + Group(DelimitedList(expr))
+            + RPAR
+        )
+        udpInstantiation = Group(
+            identifier
+            - (driveStrength | "")
+            + (delay | "")
+            + DelimitedList(udpInstance)
+            + SEMI
+        ).set_name("udpInstantiation")
+
+        parameterValueAssignment = Group(
+            Literal("#") + LPAR + Group(DelimitedList(expr)) + RPAR
+        )
+        namedPortConnection = Group(DOT + identifier + LPAR + expr + RPAR).set_name(
+            "namedPortConnection"
+        )  # .setDebug()
+        # assert r".\abc (abc )" == namedPortConnection
+        modulePortConnection = expr | empty
+        inst_args = Group(
+            LPAR
+            + (DelimitedList(namedPortConnection) | DelimitedList(modulePortConnection))
+            + RPAR
+        ).set_name("inst_args")
+        moduleInstance = Group(Group(identifier + (range_ | "")) + inst_args).set_name(
+            "moduleInstance"
+        )  # .setDebug()
+
+        moduleInstantiation = Group(
+            identifier
+            + (parameterValueAssignment | "")
+            + DelimitedList(moduleInstance).set_name("moduleInstanceList")
+            + SEMI
+        ).set_name("moduleInstantiation")
+
+        parameterOverride = Group("defparam" + DelimitedList(paramAssgnmt) + SEMI)
+        task = Group(task + identifier + SEMI + tfDecl... + stmtOrNull + endtask)
+
+        specparamDecl = Group("specparam" + DelimitedList(paramAssgnmt) + SEMI)
+
+        pathDescr1 = Group(LPAR + subscrIdentifier + "=>" + subscrIdentifier + RPAR)
+        pathDescr2 = Group(
+            LPAR
+            + Group(DelimitedList(subscrIdentifier))
+            + "*>"
+            + Group(DelimitedList(subscrIdentifier))
+            + RPAR
+        )
+        pathDescr3 = Group(
+            LPAR
+            + Group(DelimitedList(subscrIdentifier))
+            + "=>"
+            + Group(DelimitedList(subscrIdentifier))
+            + RPAR
+        )
+        pathDelayValue = Group(
+            (LPAR + Group(DelimitedList(mintypmaxExpr | expr)) + RPAR)
+            | mintypmaxExpr
+            | expr
+        )
+        pathDecl = Group(
+            (pathDescr1 | pathDescr2 | pathDescr3) + EQ + pathDelayValue + SEMI
+        ).set_name("pathDecl")
+
+        portConditionExpr = Forward()
+        portConditionTerm = (unop | "") + subscrIdentifier
+        portConditionExpr <<= portConditionTerm + (binop + portConditionExpr | "")
+        polarityOp = one_of("+ -")
+        levelSensitivePathDecl1 = Group(
+            if_
+            + Group(LPAR + portConditionExpr + RPAR)
+            + subscrIdentifier
+            + (polarityOp | "")
+            + "=>"
+            + subscrIdentifier
+            + EQ
+            + pathDelayValue
+            + SEMI
+        )
+        levelSensitivePathDecl2 = Group(
+            if_
+            + Group(LPAR + portConditionExpr + RPAR)
+            + LPAR
+            + Group(DelimitedList(subscrIdentifier))
+            + (polarityOp | "")
+            + "*>"
+            + Group(DelimitedList(subscrIdentifier))
+            + RPAR
+            + EQ
+            + pathDelayValue
+            + SEMI
+        )
+        levelSensitivePathDecl = levelSensitivePathDecl1 | levelSensitivePathDecl2
+
+        edgeIdentifier = posedge | negedge
+        edgeSensitivePathDecl1 = Group(
+            (if_ + Group(LPAR + expr + RPAR) | "")
+            + LPAR
+            + (edgeIdentifier | "")
+            + subscrIdentifier
+            + "=>"
+            + LPAR
+            + subscrIdentifier
+            + (polarityOp | "")
+            + COLON
+            + expr
+            + RPAR
+            + RPAR
+            + EQ
+            + pathDelayValue
+            + SEMI
+        )
+        edgeSensitivePathDecl2 = Group(
+            (if_ + Group(LPAR + expr + RPAR) | "")
+            + LPAR
+            + (edgeIdentifier | "")
+            + subscrIdentifier
+            + "*>"
+            + LPAR
+            + DelimitedList(subscrIdentifier)
+            + (polarityOp | "")
+            + COLON
+            + expr
+            + RPAR
+            + RPAR
+            + EQ
+            + pathDelayValue
+            + SEMI
+        )
+        edgeSensitivePathDecl = edgeSensitivePathDecl1 | edgeSensitivePathDecl2
+
+        edgeDescr = one_of("01 10 0x x1 1x x0").set_name("edgeDescr")
+
+        timCheckEventControl = Group(
+            posedge | negedge | (edge + LBRACK + DelimitedList(edgeDescr) + RBRACK)
+        )
+        timCheckCond = Forward()
+        timCondBinop = one_of("== === != !==")
+        timCheckCondTerm = (expr + timCondBinop + scalarConst) | (Optional("~") + expr)
+        timCheckCond <<= (LPAR + timCheckCond + RPAR) | timCheckCondTerm
+        timCheckEvent = Group(
+            (timCheckEventControl | "") + subscrIdentifier + ("&&&" + timCheckCond | "")
+        )
+        timCheckLimit = expr
+        controlledTimingCheckEvent = Group(
+            timCheckEventControl + subscrIdentifier + ("&&&" + timCheckCond | "")
+        )
+        notifyRegister = identifier
+
+        systemTimingCheck1 = Group(
+            "$setup"
+            + LPAR
+            + timCheckEvent
+            + COMMA
+            + timCheckEvent
+            + COMMA
+            + timCheckLimit
+            + (COMMA + notifyRegister | "")
+            + RPAR
+            + SEMI
+        )
+        systemTimingCheck2 = Group(
+            "$hold"
+            + LPAR
+            + timCheckEvent
+            + COMMA
+            + timCheckEvent
+            + COMMA
+            + timCheckLimit
+            + (COMMA + notifyRegister | "")
+            + RPAR
+            + SEMI
+        )
+        systemTimingCheck3 = Group(
+            "$period"
+            + LPAR
+            + controlledTimingCheckEvent
+            + COMMA
+            + timCheckLimit
+            + (COMMA + notifyRegister | "")
+            + RPAR
+            + SEMI
+        )
+        systemTimingCheck4 = Group(
+            "$width"
+            + LPAR
+            + controlledTimingCheckEvent
+            + COMMA
+            + timCheckLimit
+            + (COMMA + expr + COMMA + notifyRegister | "")
+            + RPAR
+            + SEMI
+        )
+        systemTimingCheck5 = Group(
+            "$skew"
+            + LPAR
+            + timCheckEvent
+            + COMMA
+            + timCheckEvent
+            + COMMA
+            + timCheckLimit
+            + (COMMA + notifyRegister | "")
+            + RPAR
+            + SEMI
+        )
+        systemTimingCheck6 = Group(
+            "$recovery"
+            + LPAR
+            + controlledTimingCheckEvent
+            + COMMA
+            + timCheckEvent
+            + COMMA
+            + timCheckLimit
+            + (COMMA + notifyRegister | "")
+            + RPAR
+            + SEMI
+        )
+        systemTimingCheck7 = Group(
+            "$setuphold"
+            + LPAR
+            + timCheckEvent
+            + COMMA
+            + timCheckEvent
+            + COMMA
+            + timCheckLimit
+            + COMMA
+            + timCheckLimit
+            + (COMMA + notifyRegister | "")
+            + RPAR
+            + SEMI
+        )
+        systemTimingCheck = (
+            FollowedBy("$")
+            + (
+                systemTimingCheck1
+                | systemTimingCheck2
+                | systemTimingCheck3
+                | systemTimingCheck4
+                | systemTimingCheck5
+                | systemTimingCheck6
+                | systemTimingCheck7
+            )
+        ).set_name("systemTimingCheck")
+        sdpd = (
+            if_
+            + Group(LPAR + expr + RPAR)
+            + (pathDescr1 | pathDescr2)
+            + EQ
+            + pathDelayValue
+            + SEMI
+        )
+
+        specifyItem = (
+            specparamDecl
+            | pathDecl
+            | levelSensitivePathDecl
+            | edgeSensitivePathDecl
+            | systemTimingCheck
+            | sdpd
+        )
+        """
+        x::= <specparam_declaration>
+        x||= <path_declaration>
+        x||= <level_sensitive_path_declaration>
+        x||= <edge_sensitive_path_declaration>
+        x||= <system_timing_check>
+        x||= <sdpd>
+        """
+        specifyBlock = Group(
+            specify + specifyItem...:endspecify + endspecify
+        ).set_name("specifyBlock")
+
+        moduleItem = (
+            parameterDecl
+            | inputDecl
+            | outputDecl
+            | inoutDecl
+            | regDecl
+            | netDecl3
+            | netDecl1
+            | netDecl2
+            | timeDecl
+            | integerDecl
+            | realDecl
+            | eventDecl
+            | gateDecl
+            | parameterOverride
+            | continuousAssign
+            | specifyBlock
+            | initialStmt
+            | alwaysStmt
+            | task
+            | functionDecl
+            # these have to be at the end - they start with identifiers
+            | moduleInstantiation
+            | udpInstantiation
+        )
+        """  All possible moduleItems, from Verilog grammar spec
+        x::= <parameter_declaration>
+        x||= <input_declaration>
+        x||= <output_declaration>
+        x||= <inout_declaration>
+        ?||= <net_declaration>  (spec does not seem consistent for this item)
+        x||= <reg_declaration>
+        x||= <time_declaration>
+        x||= <integer_declaration>
+        x||= <real_declaration>
+        x||= <event_declaration>
+        x||= <gate_declaration>
+        x||= <UDP_instantiation>
+        x||= <module_instantiation>
+        x||= <parameter_override>
+        x||= <continuous_assign>
+        x||= <specify_block>
+        x||= <initial_statement>
+        x||= <always_statement>
+        x||= <task>
+        x||= <function>
+        """
+        portRef = subscrIdentifier
+        portExpr = portRef | Group(LBRACE + DelimitedList(portRef) + RBRACE)
+        port = portExpr | Group(DOT + identifier + LPAR + portExpr + RPAR)
+
+        moduleHdr = Group(
+            (module | macromodule)
+            + identifier
+            + (
+                LPAR
+                + Group(
+                    (
+                        DelimitedList(
+                            Group(
+                                (input_ | output)
+                                + (netDecl1Arg | netDecl2Arg | netDecl3Arg)
+                            )
+                            | port
+                        )
+                        | ""
+                    )
+                )
+                + RPAR
+                | ""
+            )
+            + SEMI
+        ).set_name("moduleHdr")
+
+        module_expr = Group(
+            moduleHdr + Group(moduleItem...:endmodule) + endmodule
+        ).set_name(
+            "module"
+        )  # .setDebug()
+
+        udpDecl = outputDecl | inputDecl | regDecl
+        # udpInitVal = one_of("1'b0 1'b1 1'bx 1'bX 1'B0 1'B1 1'Bx 1'BX 1 0 x X")
+        udpInitVal = (Regex("1'bB01xX|01xX")).set_name("udpInitVal")
+        udpInitialStmt = Group(
+            "initial" + identifier + EQ + udpInitVal + SEMI
+        ).set_name("udpInitialStmt")
+
+        levelSymbol = one_of("0   1   x   X   ?   b   B")
+        levelInputList = Group(levelSymbol1, ....set_name("levelInpList"))
+
+        outputSymbol = one_of("0   1   x   X")
+        combEntry = Group(levelInputList + COLON + outputSymbol + SEMI)
+        edgeSymbol = one_of("r   R   f   F   p   P   n   N   *")
+        edge = Group(LPAR + levelSymbol + levelSymbol + RPAR) | Group(edgeSymbol)
+        edgeInputList = Group(levelSymbol... + edge + levelSymbol...)
+        inputList = levelInputList | edgeInputList
+        seqEntry = Group(
+            inputList + COLON + levelSymbol + COLON + (outputSymbol | "-") + SEMI
+        ).set_name("seqEntry")
+        udpTableDefn = Group(
+            table + (combEntry | seqEntry)1, ... + endtable
+        ).set_name("table")
+
+        """
+        <UDP>
+        ::= primitive <name_of_UDP> ( <name_of_variable> <,<name_of_variable>>* ) ;
+                <UDP_declaration>+
+                <UDP_initial_statement>?
+                <table_definition>
+                endprimitive
+        """
+        udp = Group(
+            primitive
+            + identifier
+            + LPAR
+            + Group(DelimitedList(identifier))
+            + RPAR
+            + SEMI
+            + udpDecl1, ...
+            + (udpInitialStmt | "")
+            + udpTableDefn
+            + endprimitive
+        )
+
+        verilogbnf = (module_expr | udp)1, ... + StringEnd()
+
+        verilogbnf.ignore(cppStyleComment)
+        verilogbnf.ignore(compilerDirective)
+
+    return verilogbnf
+
+
+def test(strng):
+    tokens = 
+    try:
+        tokens = make_verilog_bnf().parse_string(strng)
+    except ParseException as err:
+        print(err.explain())
+    return tokens
+
+
+if __name__ == "__main__":
+
+    def main():
+        import sys
+
+        sys.setrecursionlimit(5000)
+        print(f"Verilog parser test (V {__version__})")
+        print(f" - using pyparsing version {pyparsing.__version__}")
+        print(f" - using Python version {sys.version}")
+        if packratOn:
+            print(" - using packrat parsing")
+        print()
+
+        import gc
+
+        failCount = 0
+        make_verilog_bnf()
+        numlines = 0
+        fileDir = "verilog"
+        fileDir = "scratch/verilog"
+        # fileDir = "scratch/verilog/new3"
+        fileDir = Path(fileDir)
+        allFiles = f for f in fileDir.glob("*.v")
+
+        pretty = pprint.PrettyPrinter(indent=2)
+        totalTime = 0
+        for vfile in allFiles:
+            gc.collect()
+            gc.collect()
+            filelines = vfile.read_text().splitlines()
+            print(vfile.name, len(filelines), end=" ")
+            numlines += len(filelines)
+            teststr = "\n".join(filelines)
+            time1 = time.perf_counter()
+            tokens = test(teststr)
+            time2 = time.perf_counter()
+            elapsed = time2 - time1
+            totalTime += elapsed
+            if len(tokens):
+                print(f"OK {elapsed}")
+
+                (fileDir / "parseOutput").mkdir(exist_ok=True)
+                outfile = fileDir / "parseOutput" / (vfile.name + ".parsed.txt")
+                outfile.write_text(f"{teststr}\n\n{pretty.pformat(tokens.as_list())}\n")
+            else:
+                print(f"failed {elapsed}")
+                failCount += 1
+                for i, line in enumerate(filelines, 1):
+                    print(f"{i:4d}: {line.rstrip()}")
+
+        print(f"Total parse time: {totalTime}")
+        print(f"Total source lines: {numlines}")
+        print(f"Average lines/sec: {numlines / (totalTime + 0.05):.1f}")
+        if failCount:
+            print(f"FAIL - {failCount} files failed to parse")
+        else:
+            print("SUCCESS - all files parsed")
+
+        return 0
+
+    main()

_service:tar_scm:pyparsing-3.0.9.tar.gz/pyparsing/__init__.py -> _service:tar_scm:pyparsing-3.1.1.tar.gz/pyparsing/__init__.py Changed

@@ -56,7 +56,7 @@
 :class:`'|'<MatchFirst>`, :class:`'^'<Or>` and :class:`'&'<Each>` operators.
 
 The :class:`ParseResults` object returned from
-:class:`ParserElement.parseString` can be
+:class:`ParserElement.parse_string` can be
 accessed as a nested list, a dictionary, or an object with named
 attributes.
 
@@ -85,11 +85,11 @@
    and :class:`'&'<Each>` operators to combine simple expressions into
    more complex ones
  - associate names with your parsed results using
-   :class:`ParserElement.setResultsName`
+   :class:`ParserElement.set_results_name`
  - access the parsed data, which is returned as a :class:`ParseResults`
    object
- - find some helpful expression short-cuts like :class:`delimitedList`
-   and :class:`oneOf`
+ - find some helpful expression short-cuts like :class:`DelimitedList`
+   and :class:`one_of`
  - find more useful common expressions in the :class:`pyparsing_common`
    namespace class
 """
@@ -106,30 +106,22 @@
     @property
     def __version__(self):
         return (
-            "{}.{}.{}".format(self.major, self.minor, self.micro)
+            f"{self.major}.{self.minor}.{self.micro}"
             + (
-                "{}{}{}".format(
-                    "r" if self.releaselevel0 == "c" else "",
-                    self.releaselevel0,
-                    self.serial,
-                ),
+                f"{'r' if self.releaselevel0 == 'c' else ''}{self.releaselevel0}{self.serial}",
                 "",
             )self.releaselevel == "final"
         )
 
     def __str__(self):
-        return "{} {} / {}".format(__name__, self.__version__, __version_time__)
+        return f"{__name__} {self.__version__} / {__version_time__}"
 
     def __repr__(self):
-        return "{}.{}({})".format(
-            __name__,
-            type(self).__name__,
-            ", ".join("{}={!r}".format(*nv) for nv in zip(self._fields, self)),
-        )
+        return f"{__name__}.{type(self).__name__}({', '.join('{}={!r}'.format(*nv) for nv in zip(self._fields, self))})"
 
 
-__version_info__ = version_info(3, 0, 9, "final", 0)
-__version_time__ = "05 May 2022 07:02 UTC"
+__version_info__ = version_info(3, 1, 1, "final", 1)
+__version_time__ = "29 Jul 2023 22:27 UTC"
 __version__ = __version_info__.__version__
 __versionTime__ = __version_time__
 __author__ = "Paul McGuire <ptmcg.gm+pyparsing@gmail.com>"
@@ -139,9 +131,9 @@
 from .actions import *
 from .core import __diag__, __compat__
 from .results import *
-from .core import *
+from .core import *  # type: ignoremisc, assignment
 from .core import _builtin_exprs as core_builtin_exprs
-from .helpers import *
+from .helpers import *  # type: ignoremisc, assignment
 from .helpers import _builtin_exprs as helper_builtin_exprs
 
 from .unicode import unicode_set, UnicodeRangeList, pyparsing_unicode as unicode
@@ -153,11 +145,11 @@
 
 # define backward compat synonyms
 if "pyparsing_unicode" not in globals():
-    pyparsing_unicode = unicode
+    pyparsing_unicode = unicode  # type: ignoremisc
 if "pyparsing_common" not in globals():
-    pyparsing_common = common
+    pyparsing_common = common  # type: ignoremisc
 if "pyparsing_test" not in globals():
-    pyparsing_test = testing
+    pyparsing_test = testing  # type: ignoremisc
 
 core_builtin_exprs += common_builtin_exprs + helper_builtin_exprs
 
@@ -174,7 +166,9 @@
     "CaselessKeyword",
     "CaselessLiteral",
     "CharsNotIn",
+    "CloseMatch",
     "Combine",
+    "DelimitedList",
     "Dict",
     "Each",
     "Empty",
@@ -227,9 +221,11 @@
     "alphas8bit",
     "any_close_tag",
     "any_open_tag",
+    "autoname_elements",
     "c_style_comment",
     "col",
     "common_html_entity",
+    "condition_as_parse_action",
     "counted_array",
     "cpp_style_comment",
     "dbl_quoted_string",
@@ -241,6 +237,7 @@
     "html_comment",
     "identchars",
     "identbodychars",
+    "infix_notation",
     "java_style_comment",
     "line",
     "line_end",
@@ -255,8 +252,12 @@
     "null_debug_action",
     "nums",
     "one_of",
+    "original_text_for",
     "printables",
     "punc8bit",
+    "pyparsing_common",
+    "pyparsing_test",
+    "pyparsing_unicode",
     "python_style_comment",
     "quoted_string",
     "remove_quotes",
@@ -267,28 +268,20 @@
     "srange",
     "string_end",
     "string_start",
+    "token_map",
     "trace_parse_action",
+    "ungroup",
+    "unicode_set",
     "unicode_string",
     "with_attribute",
-    "indentedBlock",
-    "original_text_for",
-    "ungroup",
-    "infix_notation",
-    "locatedExpr",
     "with_class",
-    "CloseMatch",
-    "token_map",
-    "pyparsing_common",
-    "pyparsing_unicode",
-    "unicode_set",
-    "condition_as_parse_action",
-    "pyparsing_test",
     # pre-PEP8 compatibility names
     "__versionTime__",
     "anyCloseTag",
     "anyOpenTag",
     "cStyleComment",
     "commonHTMLEntity",
+    "conditionAsParseAction",
     "countedArray",
     "cppStyleComment",
     "dblQuotedString",
@@ -296,9 +289,12 @@
     "delimitedList",
     "dictOf",
     "htmlComment",
+    "indentedBlock",
+    "infixNotation",
     "javaStyleComment",
     "lineEnd",
     "lineStart",
+    "locatedExpr",
     "makeHTMLTags",
     "makeXMLTags",
     "matchOnlyAtCol",
@@ -308,6 +304,7 @@
     "nullDebugAction",
     "oneOf",
     "opAssoc",
+    "originalTextFor",
     "pythonStyleComment",
     "quotedString",
     "removeQuotes",
@@ -317,15 +314,12 @@
     "sglQuotedString",
     "stringEnd",
     "stringStart",
+    "tokenMap",
     "traceParseAction",
     "unicodeString",
     "withAttribute",
-    "indentedBlock",
-    "originalTextFor",
-    "infixNotation",
-    "locatedExpr",
     "withClass",
-    "tokenMap",
-    "conditionAsParseAction",
-    "autoname_elements",
+    "common",
+    "unicode",
+    "testing",

_service:tar_scm:pyparsing-3.0.9.tar.gz/pyparsing/actions.py -> _service:tar_scm:pyparsing-3.1.1.tar.gz/pyparsing/actions.py Changed

@@ -1,7 +1,7 @@
 # actions.py
 
 from .exceptions import ParseException
-from .util import col
+from .util import col, replaced_by_pep8
 
 
 class OnlyOnce:
@@ -38,7 +38,7 @@
 
     def verify_col(strg, locn, toks):
         if col(locn, strg) != n:
-            raise ParseException(strg, locn, "matched token not at column {}".format(n))
+            raise ParseException(strg, locn, f"matched token not at column {n}")
 
     return verify_col
 
@@ -148,15 +148,13 @@
                 raise ParseException(
                     s,
                     l,
-                    "attribute {!r} has value {!r}, must be {!r}".format(
-                        attrName, tokensattrName, attrValue
-                    ),
+                    f"attribute {attrName!r} has value {tokensattrName!r}, must be {attrValue!r}",
                 )
 
     return pa
 
 
-with_attribute.ANY_VALUE = object()
+with_attribute.ANY_VALUE = object()  # type: ignore attr-defined
 
 
 def with_class(classname, namespace=""):
@@ -195,13 +193,25 @@
         1 4 0 1 0
         1,3 2,3 1,1
     """
-    classattr = "{}:class".format(namespace) if namespace else "class"
+    classattr = f"{namespace}:class" if namespace else "class"
     return with_attribute(**{classattr: classname})
 
 
 # pre-PEP8 compatibility symbols
-replaceWith = replace_with
-removeQuotes = remove_quotes
-withAttribute = with_attribute
-withClass = with_class
-matchOnlyAtCol = match_only_at_col
+# fmt: off
+@replaced_by_pep8(replace_with)
+def replaceWith(): ...
+
+@replaced_by_pep8(remove_quotes)
+def removeQuotes(): ...
+
+@replaced_by_pep8(with_attribute)
+def withAttribute(): ...
+
+@replaced_by_pep8(with_class)
+def withClass(): ...
+
+@replaced_by_pep8(match_only_at_col)
+def matchOnlyAtCol(): ...
+
+# fmt: on

_service:tar_scm:pyparsing-3.0.9.tar.gz/pyparsing/common.py -> _service:tar_scm:pyparsing-3.1.1.tar.gz/pyparsing/common.py Changed

@@ -1,6 +1,6 @@
 # common.py
 from .core import *
-from .helpers import delimited_list, any_open_tag, any_close_tag
+from .helpers import DelimitedList, any_open_tag, any_close_tag
 from datetime import datetime
 
 
@@ -22,17 +22,17 @@
 
     Parse actions:
 
-    - :class:`convertToInteger`
-    - :class:`convertToFloat`
-    - :class:`convertToDate`
-    - :class:`convertToDatetime`
-    - :class:`stripHTMLTags`
-    - :class:`upcaseTokens`
-    - :class:`downcaseTokens`
+    - :class:`convert_to_integer`
+    - :class:`convert_to_float`
+    - :class:`convert_to_date`
+    - :class:`convert_to_datetime`
+    - :class:`strip_html_tags`
+    - :class:`upcase_tokens`
+    - :class:`downcase_tokens`
 
     Example::
 
-        pyparsing_common.number.runTests('''
+        pyparsing_common.number.run_tests('''
             # any int or real number, returned as the appropriate type
             100
             -100
@@ -42,7 +42,7 @@
             1e-12
             ''')
 
-        pyparsing_common.fnumber.runTests('''
+        pyparsing_common.fnumber.run_tests('''
             # any int or real number, returned as float
             100
             -100
@@ -52,19 +52,19 @@
             1e-12
             ''')
 
-        pyparsing_common.hex_integer.runTests('''
+        pyparsing_common.hex_integer.run_tests('''
             # hex numbers
             100
             FF
             ''')
 
-        pyparsing_common.fraction.runTests('''
+        pyparsing_common.fraction.run_tests('''
             # fractions
             1/2
             -3/4
             ''')
 
-        pyparsing_common.mixed_integer.runTests('''
+        pyparsing_common.mixed_integer.run_tests('''
             # mixed fractions
             1
             1/2
@@ -73,8 +73,8 @@
             ''')
 
         import uuid
-        pyparsing_common.uuid.setParseAction(tokenMap(uuid.UUID))
-        pyparsing_common.uuid.runTests('''
+        pyparsing_common.uuid.set_parse_action(token_map(uuid.UUID))
+        pyparsing_common.uuid.run_tests('''
             # uuid
             12345678-1234-5678-1234-567812345678
             ''')
@@ -260,8 +260,8 @@
         Example::
 
             date_expr = pyparsing_common.iso8601_date.copy()
-            date_expr.setParseAction(pyparsing_common.convertToDate())
-            print(date_expr.parseString("1999-12-31"))
+            date_expr.set_parse_action(pyparsing_common.convert_to_date())
+            print(date_expr.parse_string("1999-12-31"))
 
         prints::
 
@@ -287,8 +287,8 @@
         Example::
 
             dt_expr = pyparsing_common.iso8601_datetime.copy()
-            dt_expr.setParseAction(pyparsing_common.convertToDatetime())
-            print(dt_expr.parseString("1999-12-31T23:59:59.999"))
+            dt_expr.set_parse_action(pyparsing_common.convert_to_datetime())
+            print(dt_expr.parse_string("1999-12-31T23:59:59.999"))
 
         prints::
 
@@ -326,9 +326,9 @@
 
             # strip HTML links from normal text
             text = '<td>More info at the <a href="https://github.com/pyparsing/pyparsing/wiki">pyparsing</a> wiki page</td>'
-            td, td_end = makeHTMLTags("TD")
-            table_text = td + SkipTo(td_end).setParseAction(pyparsing_common.stripHTMLTags)("body") + td_end
-            print(table_text.parseString(text).body)
+            td, td_end = make_html_tags("TD")
+            table_text = td + SkipTo(td_end).set_parse_action(pyparsing_common.strip_html_tags)("body") + td_end
+            print(table_text.parse_string(text).body)
 
         Prints::
 
@@ -348,7 +348,7 @@
         .streamline()
         .set_name("commaItem")
     )
-    comma_separated_list = delimited_list(
+    comma_separated_list = DelimitedList(
         Opt(quoted_string.copy() | _commasepitem, default="")
     ).set_name("comma separated list")
     """Predefined expression of 1 or more printable words or quoted strings, separated by commas."""
@@ -363,7 +363,7 @@
     url = Regex(
         # https://mathiasbynens.be/demo/url-regex
         # https://gist.github.com/dperini/729294
-        r"^" +
+        r"(?P<url>" +
         # protocol identifier (optional)
         # short syntax // still required
         r"(?:(?:(?P<scheme>https?|ftp):)?\/\/)" +
@@ -405,18 +405,26 @@
         r"(\?(?P<query>^#*))?" +
         # fragment (optional)
         r"(#(?P<fragment>\S*))?" +
-        r"$"
+        r")"
     ).set_name("url")
+    """URL (http/https/ftp scheme)"""
     # fmt: on
 
     # pre-PEP8 compatibility names
     convertToInteger = convert_to_integer
+    """Deprecated - use :class:`convert_to_integer`"""
     convertToFloat = convert_to_float
+    """Deprecated - use :class:`convert_to_float`"""
     convertToDate = convert_to_date
+    """Deprecated - use :class:`convert_to_date`"""
     convertToDatetime = convert_to_datetime
+    """Deprecated - use :class:`convert_to_datetime`"""
     stripHTMLTags = strip_html_tags
+    """Deprecated - use :class:`strip_html_tags`"""
     upcaseTokens = upcase_tokens
+    """Deprecated - use :class:`upcase_tokens`"""
     downcaseTokens = downcase_tokens
+    """Deprecated - use :class:`downcase_tokens`"""
 
 
 _builtin_exprs =

_service:tar_scm:pyparsing-3.0.9.tar.gz/pyparsing/core.py -> _service:tar_scm:pyparsing-3.1.1.tar.gz/pyparsing/core.py Changed

@@ -1,19 +1,22 @@
 #
 # core.py
 #
+
+from collections import deque
 import os
 import typing
 from typing import (
-    NamedTuple,
-    Union,
-    Callable,
     Any,
+    Callable,
     Generator,
-    Tuple,
     List,
-    TextIO,
-    Set,
+    NamedTuple,
     Sequence,
+    Set,
+    TextIO,
+    Tuple,
+    Union,
+    cast,
 )
 from abc import ABC, abstractmethod
 from enum import Enum
@@ -40,6 +43,7 @@
     _flatten,
     LRUMemo as _LRUMemo,
     UnboundedMemo as _UnboundedMemo,
+    replaced_by_pep8,
 )
 from .exceptions import *
 from .actions import *
@@ -134,6 +138,7 @@
 class Diagnostics(Enum):
     """
     Diagnostic configuration (all default to disabled)
+
     - ``warn_multiple_tokens_in_named_alternation`` - flag to enable warnings when a results
       name is defined on a :class:`MatchFirst` or :class:`Or` expression with one or more :class:`And` subexpressions
     - ``warn_ungrouped_named_tokens_in_collection`` - flag to enable warnings when a results
@@ -228,6 +233,8 @@
 }
 
 _generatorType = types.GeneratorType
+ParseImplReturnType = Tupleint, Any
+PostParseReturnType = UnionParseResults, SequenceParseResults
 ParseAction = Union
     Callable, Any,
     CallableParseResults, Any,
@@ -256,7 +263,7 @@
 alphanums = alphas + nums
 printables = "".join(c for c in string.printable if c not in string.whitespace)
 
-_trim_arity_call_line: traceback.StackSummary = None
+_trim_arity_call_line: traceback.StackSummary = None  # type: ignoreassignment
 
 
 def _trim_arity(func, max_limit=3):
@@ -269,11 +276,6 @@
     limit = 0
     found_arity = False
 
-    def extract_tb(tb, limit=0):
-        frames = traceback.extract_tb(tb, limit=limit)
-        frame_summary = frames-1
-        return frame_summary:2
-
     # synthesize what would be returned by traceback.extract_stack at the call to
     # user's parse action 'func', so that we don't incur call penalty at parse time
 
@@ -297,8 +299,10 @@
                     raise
                 else:
                     tb = te.__traceback__
+                    frames = traceback.extract_tb(tb, limit=2)
+                    frame_summary = frames-1
                     trim_arity_type_error = (
-                        extract_tb(tb, limit=2)-1:2 == pa_call_line_synth
+                        frame_summary:2-1:2 == pa_call_line_synth
                     )
                     del tb
 
@@ -320,7 +324,7 @@
 
 
 def condition_as_parse_action(
-    fn: ParseCondition, message: str = None, fatal: bool = False
+    fn: ParseCondition, message: typing.Optionalstr = None, fatal: bool = False
 ) -> ParseAction:
     """
     Function to convert a simple predicate function that returns ``True`` or ``False``
@@ -353,15 +357,9 @@
     cache_hit_str = "*" if cache_hit else ""
     print(
         (
-            "{}Match {} at loc {}({},{})\n  {}\n  {}^".format(
-                cache_hit_str,
-                expr,
-                loc,
-                lineno(loc, instring),
-                col(loc, instring),
-                line(loc, instring),
-                " " * (col(loc, instring) - 1),
-            )
+            f"{cache_hit_str}Match {expr} at loc {loc}({lineno(loc, instring)},{col(loc, instring)})\n"
+            f"  {line(loc, instring)}\n"
+            f"  {' ' * (col(loc, instring) - 1)}^"
         )
     )
 
@@ -375,7 +373,7 @@
     cache_hit: bool = False,
 ):
     cache_hit_str = "*" if cache_hit else ""
-    print("{}Matched {} -> {}".format(cache_hit_str, expr, toks.as_list()))
+    print(f"{cache_hit_str}Matched {expr} -> {toks.as_list()}")
 
 
 def _default_exception_debug_action(
@@ -386,11 +384,7 @@
     cache_hit: bool = False,
 ):
     cache_hit_str = "*" if cache_hit else ""
-    print(
-        "{}Match {} failed, {} raised: {}".format(
-            cache_hit_str, expr, type(exc).__name__, exc
-        )
-    )
+    print(f"{cache_hit_str}Match {expr} failed, {type(exc).__name__} raised: {exc}")
 
 
 def null_debug_action(*args):
@@ -402,7 +396,7 @@
 
     DEFAULT_WHITE_CHARS: str = " \n\t\r"
     verbose_stacktrace: bool = False
-    _literalStringClass: typing.Optionaltype = None
+    _literalStringClass: type = None  # type: ignoreassignment
 
     @staticmethod
     def set_default_whitespace_chars(chars: str) -> None:
@@ -447,6 +441,18 @@
         """
         ParserElement._literalStringClass = cls
 
+    @classmethod
+    def using_each(cls, seq, **class_kwargs):
+        """
+        Yields a sequence of class(obj, **class_kwargs) for obj in seq.
+
+        Example::
+
+            LPAR, RPAR, LBRACE, RBRACE, SEMI = Suppress.using_each("(){};")
+
+        """
+        yield from (cls(obj, **class_kwargs) for obj in seq)
+
     class DebugActions(NamedTuple):
         debug_try: typing.OptionalDebugStartAction
         debug_match: typing.OptionalDebugSuccessAction
@@ -455,9 +461,9 @@
     def __init__(self, savelist: bool = False):
         self.parseAction: ListParseAction = list()
         self.failAction: typing.OptionalParseFailAction = None
-        self.customName = None
-        self._defaultName = None
-        self.resultsName = None
+        self.customName: str = None  # type: ignoreassignment
+        self._defaultName: typing.Optionalstr = None
+        self.resultsName: str = None  # type: ignoreassignment
         self.saveAsList = savelist
         self.skipWhitespace = True
         self.whiteChars = set(ParserElement.DEFAULT_WHITE_CHARS)
@@ -490,12 +496,29 @@
             base.suppress_warning(Diagnostics.warn_on_parse_using_empty_Forward)
 
             # statement would normally raise a warning, but is now suppressed
-            print(base.parseString("x"))
+            print(base.parse_string("x"))
 
         """
         self.suppress_warnings_.append(warning_type)
         return self
 
+    def visit_all(self):
+        """General-purpose method to yield all expressions and sub-expressions
+        in a grammar. Typically just for internal use.
+        """
+        to_visit = deque(self)
+        seen = set()
+        while to_visit:
+            cur = to_visit.popleft()
+
+            # guard against looping forever through recursive grammars
+            if cur in seen:
+                continue
+            seen.add(cur)
+
+            to_visit.extend(cur.recurse())
+            yield cur
+
     def copy(self) -> "ParserElement":
         """
         Make a copy of this :class:`ParserElement`.  Useful for defining
@@ -585,11 +608,11 @@
                 pdb.set_trace()
                 return _parseMethod(instring, loc, doActions, callPreParse)
 
-            breaker._originalParseMethod = _parseMethod
-            self._parse = breaker
+            breaker._originalParseMethod = _parseMethod  # type: ignore attr-defined
+            self._parse = breaker  # type: ignore assignment
         else:
             if hasattr(self._parse, "_originalParseMethod"):
-                self._parse = self._parse._originalParseMethod
+                self._parse = self._parse._originalParseMethod  # type: ignore attr-defined, assignment
         return self
 
     def set_parse_action(self, *fns: ParseAction, **kwargs) -> "ParserElement":
@@ -601,9 +624,9 @@
         Each parse action ``fn`` is a callable method with 0-3 arguments, called as
         ``fn(s, loc, toks)`` , ``fn(loc, toks)`` , ``fn(toks)`` , or just ``fn()`` , where:
 
-        - s   = the original string being parsed (see note below)
-        - loc = the location of the matching substring
-        - toks = a list of the matched tokens, packaged as a :class:`ParseResults` object
+        - ``s``    = the original string being parsed (see note below)
+        - ``loc``  = the location of the matching substring
+        - ``toks`` = a list of the matched tokens, packaged as a :class:`ParseResults` object
 
         The parsed tokens are passed to the parse action as ParseResults. They can be
         modified in place using list-style append, extend, and pop operations to update
@@ -621,7 +644,7 @@
 
         Optional keyword arguments:
 
-        - call_during_try = (default= ``False``) indicate if parse action should be run during
+        - ``call_during_try`` = (default= ``False``) indicate if parse action should be run during
           lookaheads and alternate testing. For parse actions that have side effects, it is
           important to only call the parse action once it is determined that it is being
           called as part of a successful parse. For parse actions that perform additional
@@ -697,10 +720,10 @@
 
         Optional keyword arguments:
 
-        - message = define a custom message to be used in the raised exception
-        - fatal = if True, will raise ParseFatalException to stop parsing immediately; otherwise will raise
+        - ``message`` = define a custom message to be used in the raised exception
+        - ``fatal`` = if True, will raise ParseFatalException to stop parsing immediately; otherwise will raise
           ParseException
-        - call_during_try = boolean to indicate if this method should be called during internal tryParse calls,
+        - ``call_during_try`` = boolean to indicate if this method should be called during internal tryParse calls,
           default=False
 
         Example::
@@ -716,7 +739,9 @@
         for fn in fns:
             self.parseAction.append(
                 condition_as_parse_action(
-                    fn, message=kwargs.get("message"), fatal=kwargs.get("fatal", False)
+                    fn,
+                    message=str(kwargs.get("message")),
+                    fatal=bool(kwargs.get("fatal", False)),
                 )
             )
 
@@ -731,30 +756,38 @@
         Fail acton fn is a callable function that takes the arguments
         ``fn(s, loc, expr, err)`` where:
 
-        - s = string being parsed
-        - loc = location where expression match was attempted and failed
-        - expr = the parse expression that failed
-        - err = the exception thrown
+        - ``s`` = string being parsed
+        - ``loc`` = location where expression match was attempted and failed
+        - ``expr`` = the parse expression that failed
+        - ``err`` = the exception thrown
 
         The function returns no value.  It may throw :class:`ParseFatalException`
         if it is desired to stop parsing immediately."""
         self.failAction = fn
         return self
 
-    def _skipIgnorables(self, instring, loc):
+    def _skipIgnorables(self, instring: str, loc: int) -> int:
+        if not self.ignoreExprs:
+            return loc
         exprsFound = True
+        ignore_expr_fns = e._parse for e in self.ignoreExprs
+        last_loc = loc
         while exprsFound:
             exprsFound = False
-            for e in self.ignoreExprs:
+            for ignore_fn in ignore_expr_fns:
                 try:
                     while 1:
-                        loc, dummy = e._parse(instring, loc)
+                        loc, dummy = ignore_fn(instring, loc)
                         exprsFound = True
                 except ParseException:
                     pass
+            # check if all ignore exprs matched but didn't actually advance the parse location
+            if loc == last_loc:
+                break
+            last_loc = loc
         return loc
 
-    def preParse(self, instring, loc):
+    def preParse(self, instring: str, loc: int) -> int:
         if self.ignoreExprs:
             loc = self._skipIgnorables(instring, loc)
 
@@ -830,7 +863,7 @@
                 try:
                     for fn in self.parseAction:
                         try:
-                            tokens = fn(instring, tokens_start, ret_tokens)
+                            tokens = fn(instring, tokens_start, ret_tokens)  # type: ignore call-arg, arg-type
                         except IndexError as parse_action_exc:
                             exc = ParseException("exception raised in parse action")
                             raise exc from parse_action_exc
@@ -853,7 +886,7 @@
             else:
                 for fn in self.parseAction:
                     try:
-                        tokens = fn(instring, tokens_start, ret_tokens)
+                        tokens = fn(instring, tokens_start, ret_tokens)  # type: ignore call-arg, arg-type
                     except IndexError as parse_action_exc:
                         exc = ParseException("exception raised in parse action")
                         raise exc from parse_action_exc
@@ -875,17 +908,24 @@
 
         return loc, ret_tokens
 
-    def try_parse(self, instring: str, loc: int, raise_fatal: bool = False) -> int:
+    def try_parse(
+        self,
+        instring: str,
+        loc: int,
+        *,
+        raise_fatal: bool = False,
+        do_actions: bool = False,
+    ) -> int:
         try:
-            return self._parse(instring, loc, doActions=False)0
+            return self._parse(instring, loc, doActions=do_actions)0
         except ParseFatalException:
             if raise_fatal:
                 raise
             raise ParseException(instring, loc, self.errmsg, self)
 
-    def can_parse_next(self, instring: str, loc: int) -> bool:
+    def can_parse_next(self, instring: str, loc: int, do_actions: bool = False) -> bool:
         try:
-            self.try_parse(instring, loc)
+            self.try_parse(instring, loc, do_actions=do_actions)
         except (ParseException, IndexError):
             return False
         else:
@@ -897,10 +937,23 @@
         Tupleint, "Forward", bool, Tupleint, UnionParseResults, Exception
      = {}
 
+    class _CacheType(dict):
+        """
+        class to help type checking
+        """
+
+        not_in_cache: bool
+
+        def get(self, *args):
+            ...
+
+        def set(self, *args):
+            ...
+
     # argument cache for optimizing repeated calls when backtracking through recursive expressions
     packrat_cache = (
-        {}
-    )  # this is set later by enabled_packrat(); this is here so that reset_cache() doesn't fail
+        _CacheType()
+    )  # set later by enable_packrat(); this is here so that reset_cache() doesn't fail
     packrat_cache_lock = RLock()
     packrat_cache_stats = 0, 0
 
@@ -930,24 +983,25 @@
                 ParserElement.packrat_cache_statsHIT += 1
                 if self.debug and self.debugActions.debug_try:
                     try:
-                        self.debugActions.debug_try(instring, loc, self, cache_hit=True)
+                        self.debugActions.debug_try(instring, loc, self, cache_hit=True)  # type: ignore call-arg
                     except TypeError:
                         pass
                 if isinstance(value, Exception):
                     if self.debug and self.debugActions.debug_fail:
                         try:
                             self.debugActions.debug_fail(
-                                instring, loc, self, value, cache_hit=True
+                                instring, loc, self, value, cache_hit=True  # type: ignore call-arg
                             )
                         except TypeError:
                             pass
                     raise value
 
+                value = cast(Tupleint, ParseResults, int, value)
                 loc_, result, endloc = value0, value1.copy(), value2
                 if self.debug and self.debugActions.debug_match:
                     try:
                         self.debugActions.debug_match(
-                            instring, loc_, endloc, self, result, cache_hit=True
+                            instring, loc_, endloc, self, result, cache_hit=True  # type: ignore call-arg
                         )
                     except TypeError:
                         pass
@@ -1009,7 +1063,7 @@
 
         Parameters:
 
-        - cache_size_limit - (default=``None``) - memoize at most this many
+        - ``cache_size_limit`` - (default=``None``) - memoize at most this many
           ``Forward`` elements during matching; if ``None`` (the default),
           memoize all ``Forward`` elements.
 
@@ -1022,15 +1076,17 @@
         elif ParserElement._packratEnabled:
             raise RuntimeError("Packrat and Bounded Recursion are not compatible")
         if cache_size_limit is None:
-            ParserElement.recursion_memos = _UnboundedMemo()
+            ParserElement.recursion_memos = _UnboundedMemo()  # type: ignoreassignment
         elif cache_size_limit > 0:
-            ParserElement.recursion_memos = _LRUMemo(capacity=cache_size_limit)
+            ParserElement.recursion_memos = _LRUMemo(capacity=cache_size_limit)  # type: ignoreassignment
         else:
             raise NotImplementedError("Memo size of %s" % cache_size_limit)
         ParserElement._left_recursion_enabled = True
 
     @staticmethod
-    def enable_packrat(cache_size_limit: int = 128, *, force: bool = False) -> None:
+    def enable_packrat(
+        cache_size_limit: Unionint, None = 128, *, force: bool = False
+    ) -> None:
         """
         Enables "packrat" parsing, which adds memoizing to the parsing logic.
         Repeated parse attempts at the same string location (which happens
@@ -1040,7 +1096,7 @@
 
         Parameters:
 
-        - cache_size_limit - (default= ``128``) - if an integer value is provided
+        - ``cache_size_limit`` - (default= ``128``) - if an integer value is provided
           will limit the size of the packrat cache; if None is passed, then
           the cache size will be unbounded; if 0 is passed, the cache will
           be effectively disabled.
@@ -1070,7 +1126,7 @@
             if cache_size_limit is None:
                 ParserElement.packrat_cache = _UnboundedCache()
             else:
-                ParserElement.packrat_cache = _FifoCache(cache_size_limit)
+                ParserElement.packrat_cache = _FifoCache(cache_size_limit)  # type: ignoreassignment
             ParserElement._parse = ParserElement._parseCache
 
     def parse_string(
@@ -1088,7 +1144,7 @@
           an object with attributes if the given parser includes results names.
 
         If the input string is required to match the entire grammar, ``parse_all`` flag must be set to ``True``. This
-        is also equivalent to ending the grammar with :class:`StringEnd`().
+        is also equivalent to ending the grammar with :class:`StringEnd`\\ ().
 
         To report proper column numbers, ``parse_string`` operates on a copy of the input string where all tabs are
         converted to spaces (8 spaces per tab, as per the default in ``string.expandtabs``). If the input string
@@ -1198,7 +1254,9 @@
         try:
             while loc <= instrlen and matches < maxMatches:
                 try:
-                    preloc = preparseFn(instring, loc)
+                    preloc: int = preparseFn(instring, loc)
+                    nextLoc: int
+                    tokens: ParseResults
                     nextLoc, tokens = parseFn(instring, preloc, callPreParse=False)
                 except ParseException:
                     loc = preloc + 1
@@ -1352,7 +1410,7 @@
     def __add__(self, other) -> "ParserElement":
         """
         Implementation of ``+`` operator - returns :class:`And`. Adding strings to a :class:`ParserElement`
-        converts them to :class:`Literal`s by default.
+        converts them to :class:`Literal`\\ s by default.
 
         Example::
 
@@ -1364,11 +1422,11 @@
 
             Hello, World! -> 'Hello', ',', 'World', '!'
 
-        ``...`` may be used as a parse expression as a short form of :class:`SkipTo`.
+        ``...`` may be used as a parse expression as a short form of :class:`SkipTo`::
 
             Literal('start') + ... + Literal('end')
 
-        is equivalent to:
+        is equivalent to::
 
             Literal('start') + SkipTo('end')("_skipped*") + Literal('end')
 
@@ -1382,11 +1440,7 @@
         if isinstance(other, str_type):
             other = self._literalStringClass(other)
         if not isinstance(other, ParserElement):
-            raise TypeError(
-                "Cannot combine element of type {} with ParserElement".format(
-                    type(other).__name__
-                )
-            )
+            return NotImplemented
         return And(self, other)
 
     def __radd__(self, other) -> "ParserElement":
@@ -1399,11 +1453,7 @@
         if isinstance(other, str_type):
             other = self._literalStringClass(other)
         if not isinstance(other, ParserElement):
-            raise TypeError(
-                "Cannot combine element of type {} with ParserElement".format(
-                    type(other).__name__
-                )
-            )
+            return NotImplemented
         return other + self
 
     def __sub__(self, other) -> "ParserElement":
@@ -1413,11 +1463,7 @@
         if isinstance(other, str_type):
             other = self._literalStringClass(other)
         if not isinstance(other, ParserElement):
-            raise TypeError(
-                "Cannot combine element of type {} with ParserElement".format(
-                    type(other).__name__
-                )
-            )
+            return NotImplemented
         return self + And._ErrorStop() + other
 
     def __rsub__(self, other) -> "ParserElement":
@@ -1427,11 +1473,7 @@
         if isinstance(other, str_type):
             other = self._literalStringClass(other)
         if not isinstance(other, ParserElement):
-            raise TypeError(
-                "Cannot combine element of type {} with ParserElement".format(
-                    type(other).__name__
-                )
-            )
+            return NotImplemented
         return other - self
 
     def __mul__(self, other) -> "ParserElement":
@@ -1440,11 +1482,12 @@
         ``expr + expr + expr``.  Expressions may also be multiplied by a 2-integer
         tuple, similar to ``{min, max}`` multipliers in regular expressions.  Tuples
         may also include ``None`` as in:
+
         - ``expr*(n, None)`` or ``expr*(n, )`` is equivalent
-             to ``expr*n + ZeroOrMore(expr)``
-             (read as "at least n instances of ``expr``")
+          to ``expr*n + ZeroOrMore(expr)``
+          (read as "at least n instances of ``expr``")
         - ``expr*(None, n)`` is equivalent to ``expr*(0, n)``
-             (read as "0 to n instances of ``expr``")
+          (read as "0 to n instances of ``expr``")
         - ``expr*(None, None)`` is equivalent to ``ZeroOrMore(expr)``
         - ``expr*(1, None)`` is equivalent to ``OneOrMore(expr)``
 
@@ -1477,17 +1520,9 @@
                 minElements, optElements = other
                 optElements -= minElements
             else:
-                raise TypeError(
-                    "cannot multiply ParserElement and ({}) objects".format(
-                        ",".join(type(item).__name__ for item in other)
-                    )
-                )
+                return NotImplemented
         else:
-            raise TypeError(
-                "cannot multiply ParserElement and {} objects".format(
-                    type(other).__name__
-                )
-            )
+            return NotImplemented
 
         if minElements < 0:
             raise ValueError("cannot multiply ParserElement by negative value")
@@ -1531,13 +1566,12 @@
             return _PendingSkip(self, must_skip=True)
 
         if isinstance(other, str_type):
+            # `expr | ""` is equivalent to `Opt(expr)`
+            if other == "":
+                return Opt(self)
             other = self._literalStringClass(other)
         if not isinstance(other, ParserElement):
-            raise TypeError(
-                "Cannot combine element of type {} with ParserElement".format(
-                    type(other).__name__
-                )
-            )
+            return NotImplemented
         return MatchFirst(self, other)
 
     def __ror__(self, other) -> "ParserElement":
@@ -1547,11 +1581,7 @@
         if isinstance(other, str_type):
             other = self._literalStringClass(other)
         if not isinstance(other, ParserElement):
-            raise TypeError(
-                "Cannot combine element of type {} with ParserElement".format(
-                    type(other).__name__
-                )
-            )
+            return NotImplemented
         return other | self
 
     def __xor__(self, other) -> "ParserElement":
@@ -1561,11 +1591,7 @@
         if isinstance(other, str_type):
             other = self._literalStringClass(other)
         if not isinstance(other, ParserElement):
-            raise TypeError(
-                "Cannot combine element of type {} with ParserElement".format(
-                    type(other).__name__
-                )
-            )
+            return NotImplemented
         return Or(self, other)
 
     def __rxor__(self, other) -> "ParserElement":
@@ -1575,11 +1601,7 @@
         if isinstance(other, str_type):
             other = self._literalStringClass(other)
         if not isinstance(other, ParserElement):
-            raise TypeError(
-                "Cannot combine element of type {} with ParserElement".format(
-                    type(other).__name__
-                )
-            )
+            return NotImplemented
         return other ^ self
 
     def __and__(self, other) -> "ParserElement":
@@ -1589,11 +1611,7 @@
         if isinstance(other, str_type):
             other = self._literalStringClass(other)
         if not isinstance(other, ParserElement):
-            raise TypeError(
-                "Cannot combine element of type {} with ParserElement".format(
-                    type(other).__name__
-                )
-            )
+            return NotImplemented
         return Each(self, other)
 
     def __rand__(self, other) -> "ParserElement":
@@ -1603,11 +1621,7 @@
         if isinstance(other, str_type):
             other = self._literalStringClass(other)
         if not isinstance(other, ParserElement):
-            raise TypeError(
-                "Cannot combine element of type {} with ParserElement".format(
-                    type(other).__name__
-                )
-            )
+            return NotImplemented
         return other & self
 
     def __invert__(self) -> "ParserElement":
@@ -1636,38 +1650,58 @@
 
         ``None`` may be used in place of ``...``.
 
-        Note that ``expr..., n`` and ``exprm, n``do not raise an exception
-        if more than ``n`` ``expr``s exist in the input stream.  If this behavior is
+        Note that ``expr..., n`` and ``exprm, n`` do not raise an exception
+        if more than ``n`` ``expr``\\ s exist in the input stream.  If this behavior is
         desired, then write ``expr..., n + ~expr``.
+
+        For repetition with a stop_on expression, use slice notation:
+
+        - ``expr...: end_expr`` and ``expr0, ...: end_expr`` are equivalent to ``ZeroOrMore(expr, stop_on=end_expr)``
+        - ``expr1, ...: end_expr`` is equivalent to ``OneOrMore(expr, stop_on=end_expr)``
+
         """
 
+        stop_on_defined = False
+        stop_on = NoMatch()
+        if isinstance(key, slice):
+            key, stop_on = key.start, key.stop
+            if key is None:
+                key = ...
+            stop_on_defined = True
+        elif isinstance(key, tuple) and isinstance(key-1, slice):
+            key, stop_on = (key0, key1.start), key1.stop
+            stop_on_defined = True
+
         # convert single arg keys to tuples
+        if isinstance(key, str_type):
+            key = (key,)
         try:
-            if isinstance(key, str_type):
-                key = (key,)
             iter(key)
         except TypeError:
             key = (key, key)
 
         if len(key) > 2:
             raise TypeError(
-                "only 1 or 2 index arguments supported ({}{})".format(
-                    key:5, "... {}".format(len(key)) if len(key) > 5 else ""
-                )
+                f"only 1 or 2 index arguments supported ({key:5}{f'... {len(key)}' if len(key) > 5 else ''})"
             )
 
         # clip to 2 elements
         ret = self * tuple(key:2)
+        ret = typing.cast(_MultipleMatch, ret)
+
+        if stop_on_defined:
+            ret.stopOn(stop_on)
+
         return ret
 
-    def __call__(self, name: str = None) -> "ParserElement":
+    def __call__(self, name: typing.Optionalstr = None) -> "ParserElement":
         """
         Shortcut for :class:`set_results_name`, with ``list_all_matches=False``.
 
         If ``name`` is given with a trailing ``'*'`` character, then ``list_all_matches`` will be
         passed as ``True``.
 
-        If ``name` is omitted, same as calling :class:`copy`.
+        If ``name`` is omitted, same as calling :class:`copy`.
 
         Example::
 
@@ -1775,17 +1809,18 @@
           should have the signature ``fn(input_string: str, location: int, expression: ParserElement, exception: Exception, cache_hit: bool)``
         """
         self.debugActions = self.DebugActions(
-            start_action or _default_start_debug_action,
-            success_action or _default_success_debug_action,
-            exception_action or _default_exception_debug_action,
+            start_action or _default_start_debug_action,  # type: ignoretruthy-function
+            success_action or _default_success_debug_action,  # type: ignoretruthy-function
+            exception_action or _default_exception_debug_action,  # type: ignoretruthy-function
         )
         self.debug = True
         return self
 
-    def set_debug(self, flag: bool = True) -> "ParserElement":
+    def set_debug(self, flag: bool = True, recurse: bool = False) -> "ParserElement":
         """
         Enable display of debugging messages while doing pattern matching.
         Set ``flag`` to ``True`` to enable, ``False`` to disable.
+        Set ``recurse`` to ``True`` to set the debug flag on this expression and all sub-expressions.
 
         Example::
 
@@ -1819,6 +1854,11 @@
         which makes debugging and exception messages easier to understand - for instance, the default
         name created for the :class:`Word` expression without calling ``set_name`` is ``"W:(A-Za-z)"``.
         """
+        if recurse:
+            for expr in self.visit_all():
+                expr.set_debug(flag, recurse=False)
+            return self
+
         if flag:
             self.set_debug_actions(
                 _default_start_debug_action,
@@ -1836,7 +1876,7 @@
         return self._defaultName
 
     @abstractmethod
-    def _generateDefaultName(self):
+    def _generateDefaultName(self) -> str:
         """
         Child classes must define this method, which defines how the ``default_name`` is set.
         """
@@ -1844,7 +1884,9 @@
     def set_name(self, name: str) -> "ParserElement":
         """
         Define name for this expression, makes debugging and exception messages clearer.
+
         Example::
+
             Word(nums).parse_string("ABC")  # -> Exception: Expected W:(0-9) (at char 0), (line:1, col:1)
             Word(nums).set_name("integer").parse_string("ABC")  # -> Exception: Expected integer (at char 0), (line:1, col:1)
         """
@@ -1870,7 +1912,7 @@
         self._defaultName = None
         return self
 
-    def recurse(self) -> Sequence"ParserElement":
+    def recurse(self) -> List"ParserElement":
         return 
 
     def _checkRecursion(self, parseElementList):
@@ -1882,6 +1924,11 @@
         """
         Check defined expressions for valid structure, check for infinite recursive definitions.
         """
+        warnings.warn(
+            "ParserElement.validate() is deprecated, and should not be used to check for left recursion",
+            DeprecationWarning,
+            stacklevel=2,
+        )
         self._checkRecursion()
 
     def parse_file(
@@ -1899,8 +1946,10 @@
         """
         parseAll = parseAll or parse_all
         try:
+            file_or_filename = typing.cast(TextIO, file_or_filename)
             file_contents = file_or_filename.read()
         except AttributeError:
+            file_or_filename = typing.cast(str, file_or_filename)
             with open(file_or_filename, "r", encoding=encoding) as f:
                 file_contents = f.read()
         try:
@@ -1932,6 +1981,7 @@
         inline microtests of sub expressions while building up larger parser.
 
         Parameters:
+
         - ``test_string`` - to test against this expression for a match
         - ``parse_all`` - (default= ``True``) - flag to pass to :class:`parse_string` when running tests
 
@@ -1955,7 +2005,7 @@
         full_dump: bool = True,
         print_results: bool = True,
         failure_tests: bool = False,
-        post_parse: Callablestr, ParseResults, str = None,
+        post_parse: typing.OptionalCallablestr, ParseResults, str = None,
         file: typing.OptionalTextIO = None,
         with_line_numbers: bool = False,
         *,
@@ -1963,7 +2013,7 @@
         fullDump: bool = True,
         printResults: bool = True,
         failureTests: bool = False,
-        postParse: Callablestr, ParseResults, str = None,
+        postParse: typing.OptionalCallablestr, ParseResults, str = None,
     ) -> Tuplebool, ListTuplestr, UnionParseResults, Exception:
         """
         Execute the parse expression on a series of test strings, showing each
@@ -1971,6 +2021,7 @@
         run a parse expression against a list of sample strings.
 
         Parameters:
+
         - ``tests`` - a list of separate test strings, or a multiline string of test strings
         - ``parse_all`` - (default= ``True``) - flag to pass to :class:`parse_string` when running tests
         - ``comment`` - (default= ``'#'``) - expression for indicating embedded comments in the test
@@ -2067,22 +2118,27 @@
         failureTests = failureTests or failure_tests
         postParse = postParse or post_parse
         if isinstance(tests, str_type):
+            tests = typing.cast(str, tests)
             line_strip = type(tests).strip
             tests = line_strip(test_line) for test_line in tests.rstrip().splitlines()
-        if isinstance(comment, str_type):
-            comment = Literal(comment)
+        comment_specified = comment is not None
+        if comment_specified:
+            if isinstance(comment, str_type):
+                comment = typing.cast(str, comment)
+                comment = Literal(comment)
+        comment = typing.cast(ParserElement, comment)
         if file is None:
             file = sys.stdout
         print_ = file.write
 
         result: UnionParseResults, Exception
-        allResults = 
-        comments = 
+        allResults: ListTuplestr, UnionParseResults, Exception = 
+        comments: Liststr = 
         success = True
         NL = Literal(r"\n").add_parse_action(replace_with("\n")).ignore(quoted_string)
         BOM = "\ufeff"
         for t in tests:
-            if comment is not None and comment.matches(t, False) or comments and not t:
+            if comment_specified and comment.matches(t, False) or comments and not t:
                 comments.append(
                     pyparsing_test.with_line_numbers(t) if with_line_numbers else t
                 )
@@ -2107,7 +2163,7 @@
                 success = success and failureTests
                 result = pe
             except Exception as exc:
-                out.append("FAIL-EXCEPTION: {}: {}".format(type(exc).__name__, exc))
+                out.append(f"FAIL-EXCEPTION: {type(exc).__name__}: {exc}")
                 if ParserElement.verbose_stacktrace:
                     out.extend(traceback.format_tb(exc.__traceback__))
                 success = success and failureTests
@@ -2127,9 +2183,7 @@
                     except Exception as e:
                         out.append(result.dump(full=fullDump))
                         out.append(
-                            "{} failed: {}: {}".format(
-                                postParse.__name__, type(e).__name__, e
-                            )
+                            f"{postParse.__name__} failed: {type(e).__name__}: {e}"
                         )
                 else:
                     out.append(result.dump(full=fullDump))
@@ -2148,19 +2202,28 @@
         vertical: int = 3,
         show_results_names: bool = False,
         show_groups: bool = False,
+        embed: bool = False,
         **kwargs,
     ) -> None:
         """
         Create a railroad diagram for the parser.
 
         Parameters:
-        - output_html (str or file-like object) - output target for generated
+
+        - ``output_html`` (str or file-like object) - output target for generated
           diagram HTML
-        - vertical (int) - threshold for formatting multiple alternatives vertically
+        - ``vertical`` (int) - threshold for formatting multiple alternatives vertically
           instead of horizontally (default=3)
-        - show_results_names - bool flag whether diagram should show annotations for
+        - ``show_results_names`` - bool flag whether diagram should show annotations for
           defined results names
-        - show_groups - bool flag whether groups should be highlighted with an unlabeled surrounding box
+        - ``show_groups`` - bool flag whether groups should be highlighted with an unlabeled surrounding box
+        - ``embed`` - bool flag whether generated HTML should omit <HEAD>, <BODY>, and <DOCTYPE> tags to embed
+          the resulting HTML in an enclosing HTML source
+        - ``head`` - str containing additional HTML to insert into the <HEAD> section of the generated code;
+          can be used to insert custom CSS styling
+        - ``body`` - str containing additional HTML to insert at the beginning of the <BODY> section of the
+          generated code
+
         Additional diagram-formatting keyword arguments can also be included;
         see railroad.Diagram class.
         """
@@ -2183,38 +2246,93 @@
         )
         if isinstance(output_html, (str, Path)):
             with open(output_html, "w", encoding="utf-8") as diag_file:
-                diag_file.write(railroad_to_html(railroad))
+                diag_file.write(railroad_to_html(railroad, embed=embed, **kwargs))
         else:
             # we were passed a file-like object, just write to it
-            output_html.write(railroad_to_html(railroad))
+            output_html.write(railroad_to_html(railroad, embed=embed, **kwargs))
+
+    # Compatibility synonyms
+    # fmt: off
+    @staticmethod
+    @replaced_by_pep8(inline_literals_using)
+    def inlineLiteralsUsing(): ...
+
+    @staticmethod
+    @replaced_by_pep8(set_default_whitespace_chars)
+    def setDefaultWhitespaceChars(): ...
+
+    @replaced_by_pep8(set_results_name)
+    def setResultsName(self): ...
+
+    @replaced_by_pep8(set_break)
+    def setBreak(self): ...
+
+    @replaced_by_pep8(set_parse_action)
+    def setParseAction(self): ...
+
+    @replaced_by_pep8(add_parse_action)
+    def addParseAction(self): ...
+
+    @replaced_by_pep8(add_condition)
+    def addCondition(self): ...
+
+    @replaced_by_pep8(set_fail_action)
+    def setFailAction(self): ...
+
+    @replaced_by_pep8(try_parse)
+    def tryParse(self): ...
+
+    @staticmethod
+    @replaced_by_pep8(enable_left_recursion)
+    def enableLeftRecursion(): ...
+
+    @staticmethod
+    @replaced_by_pep8(enable_packrat)
+    def enablePackrat(): ...
+
+    @replaced_by_pep8(parse_string)
+    def parseString(self): ...
+
+    @replaced_by_pep8(scan_string)
+    def scanString(self): ...
+
+    @replaced_by_pep8(transform_string)
+    def transformString(self): ...
+
+    @replaced_by_pep8(search_string)
+    def searchString(self): ...
+
+    @replaced_by_pep8(ignore_whitespace)
+    def ignoreWhitespace(self): ...
+
+    @replaced_by_pep8(leave_whitespace)
+    def leaveWhitespace(self): ...
+
+    @replaced_by_pep8(set_whitespace_chars)
+    def setWhitespaceChars(self): ...
+
+    @replaced_by_pep8(parse_with_tabs)
+    def parseWithTabs(self): ...
+
+    @replaced_by_pep8(set_debug_actions)
+    def setDebugActions(self): ...
+
+    @replaced_by_pep8(set_debug)
+    def setDebug(self): ...
+
+    @replaced_by_pep8(set_name)
+    def setName(self): ...
+
+    @replaced_by_pep8(parse_file)
+    def parseFile(self): ...
+
+    @replaced_by_pep8(run_tests)
+    def runTests(self): ...
 
-    setDefaultWhitespaceChars = set_default_whitespace_chars
-    inlineLiteralsUsing = inline_literals_using
-    setResultsName = set_results_name
-    setBreak = set_break
-    setParseAction = set_parse_action
-    addParseAction = add_parse_action
-    addCondition = add_condition
-    setFailAction = set_fail_action
-    tryParse = try_parse
     canParseNext = can_parse_next
     resetCache = reset_cache
-    enableLeftRecursion = enable_left_recursion
-    enablePackrat = enable_packrat
-    parseString = parse_string
-    scanString = scan_string
-    searchString = search_string
-    transformString = transform_string
-    setWhitespaceChars = set_whitespace_chars
-    parseWithTabs = parse_with_tabs
-    setDebugActions = set_debug_actions
-    setDebug = set_debug
     defaultName = default_name
-    setName = set_name
-    parseFile = parse_file
-    runTests = run_tests
-    ignoreWhitespace = ignore_whitespace
-    leaveWhitespace = leave_whitespace
+    # fmt: on
 
 
 class _PendingSkip(ParserElement):
@@ -2225,7 +2343,7 @@
         self.anchor = expr
         self.must_skip = must_skip
 
-    def _generateDefaultName(self):
+    def _generateDefaultName(self) -> str:
         return str(self.anchor + Empty()).replace("Empty", "...")
 
     def __add__(self, other) -> "ParserElement":
@@ -2266,21 +2384,10 @@
     def __init__(self):
         super().__init__(savelist=False)
 
-    def _generateDefaultName(self):
+    def _generateDefaultName(self) -> str:
         return type(self).__name__
 
 
-class Empty(Token):
-    """
-    An empty token, will always match.
-    """
-
-    def __init__(self):
-        super().__init__()
-        self.mayReturnEmpty = True
-        self.mayIndexError = False
-
-
 class NoMatch(Token):
     """
     A token that will never match.
@@ -2312,25 +2419,33 @@
     use :class:`Keyword` or :class:`CaselessKeyword`.
     """
 
+    def __new__(cls, match_string: str = "", *, matchString: str = ""):
+        # Performance tuning: select a subclass with optimized parseImpl
+        if cls is Literal:
+            match_string = matchString or match_string
+            if not match_string:
+                return super().__new__(Empty)
+            if len(match_string) == 1:
+                return super().__new__(_SingleCharLiteral)
+
+        # Default behavior
+        return super().__new__(cls)
+
+    # Needed to make copy.copy() work correctly if we customize __new__
+    def __getnewargs__(self):
+        return (self.match,)
+
     def __init__(self, match_string: str = "", *, matchString: str = ""):
         super().__init__()
         match_string = matchString or match_string
         self.match = match_string
         self.matchLen = len(match_string)
-        try:
-            self.firstMatchChar = match_string0
-        except IndexError:
-            raise ValueError("null string passed to Literal; use Empty() instead")
+        self.firstMatchChar = match_string:1
         self.errmsg = "Expected " + self.name
         self.mayReturnEmpty = False
         self.mayIndexError = False
 
-        # Performance tuning: modify __class__ to select
-        # a parseImpl optimized for single-character check
-        if self.matchLen == 1 and type(self) is Literal:
-            self.__class__ = _SingleCharLiteral
-
-    def _generateDefaultName(self):
+    def _generateDefaultName(self) -> str:
         return repr(self.match)
 
     def parseImpl(self, instring, loc, doActions=True):
@@ -2341,6 +2456,23 @@
         raise ParseException(instring, loc, self.errmsg, self)
 
 
+class Empty(Literal):
+    """
+    An empty token, will always match.
+    """
+
+    def __init__(self, match_string="", *, matchString=""):
+        super().__init__("")
+        self.mayReturnEmpty = True
+        self.mayIndexError = False
+
+    def _generateDefaultName(self) -> str:
+        return "Empty"
+
+    def parseImpl(self, instring, loc, doActions=True):
+        return loc, 
+
+
 class _SingleCharLiteral(Literal):
     def parseImpl(self, instring, loc, doActions=True):
         if instringloc == self.firstMatchChar:
@@ -2354,8 +2486,8 @@
 class Keyword(Token):
     """
     Token to exactly match a specified string as a keyword, that is,
-    it must be immediately followed by a non-keyword character.  Compare
-    with :class:`Literal`:
+    it must be immediately preceded and followed by whitespace or
+    non-keyword characters. Compare with :class:`Literal`:
 
     - ``Literal("if")`` will match the leading ``'if'`` in
       ``'ifAndOnlyIf'``.
@@ -2365,7 +2497,7 @@
     Accepts two optional constructor arguments in addition to the
     keyword string:
 
-    - ``identChars`` is a string of characters that would be valid
+    - ``ident_chars`` is a string of characters that would be valid
       identifier characters, defaulting to all alphanumerics + "_" and
       "$"
     - ``caseless`` allows case-insensitive matching, default is ``False``.
@@ -2400,7 +2532,7 @@
             self.firstMatchChar = match_string0
         except IndexError:
             raise ValueError("null string passed to Keyword; use Empty() instead")
-        self.errmsg = "Expected {} {}".format(type(self).__name__, self.name)
+        self.errmsg = f"Expected {type(self).__name__} {self.name}"
         self.mayReturnEmpty = False
         self.mayIndexError = False
         self.caseless = caseless
@@ -2409,7 +2541,7 @@
             identChars = identChars.upper()
         self.identChars = set(identChars)
 
-    def _generateDefaultName(self):
+    def _generateDefaultName(self) -> str:
         return repr(self.match)
 
     def parseImpl(self, instring, loc, doActions=True):
@@ -2559,7 +2691,7 @@
     def __init__(
         self,
         match_string: str,
-        max_mismatches: int = None,
+        max_mismatches: typing.Optionalint = None,
         *,
         maxMismatches: int = 1,
         caseless=False,
@@ -2568,15 +2700,13 @@
         super().__init__()
         self.match_string = match_string
         self.maxMismatches = maxMismatches
-        self.errmsg = "Expected {!r} (with up to {} mismatches)".format(
-            self.match_string, self.maxMismatches
-        )
+        self.errmsg = f"Expected {self.match_string!r} (with up to {self.maxMismatches} mismatches)"
         self.caseless = caseless
         self.mayIndexError = False
         self.mayReturnEmpty = False
 
-    def _generateDefaultName(self):
-        return "{}:{!r}".format(type(self).__name__, self.match_string)
+    def _generateDefaultName(self) -> str:
+        return f"{type(self).__name__}:{self.match_string!r}"
 
     def parseImpl(self, instring, loc, doActions=True):
         start = loc
@@ -2612,7 +2742,9 @@
 
 class Word(Token):
     """Token for matching words composed of allowed character sets.
+
     Parameters:
+
     - ``init_chars`` - string of all characters that should be used to
       match as a word; "ABC" will match "AAA", "ABAB", "CBAC", etc.;
       if ``body_chars`` is also specified, then this is the string of
@@ -2697,26 +2829,24 @@
         super().__init__()
         if not initChars:
             raise ValueError(
-                "invalid {}, initChars cannot be empty string".format(
-                    type(self).__name__
-                )
+                f"invalid {type(self).__name__}, initChars cannot be empty string"
             )
 
-        initChars = set(initChars)
-        self.initChars = initChars
+        initChars_set = set(initChars)
         if excludeChars:
-            excludeChars = set(excludeChars)
-            initChars -= excludeChars
+            excludeChars_set = set(excludeChars)
+            initChars_set -= excludeChars_set
             if bodyChars:
-                bodyChars = set(bodyChars) - excludeChars
-        self.initCharsOrig = "".join(sorted(initChars))
+                bodyChars = "".join(set(bodyChars) - excludeChars_set)
+        self.initChars = initChars_set
+        self.initCharsOrig = "".join(sorted(initChars_set))
 
         if bodyChars:
-            self.bodyCharsOrig = "".join(sorted(bodyChars))
             self.bodyChars = set(bodyChars)
+            self.bodyCharsOrig = "".join(sorted(bodyChars))
         else:
-            self.bodyCharsOrig = "".join(sorted(initChars))
-            self.bodyChars = set(initChars)
+            self.bodyChars = initChars_set
+            self.bodyCharsOrig = self.initCharsOrig
 
         self.maxSpecified = max > 0
 
@@ -2725,6 +2855,11 @@
                 "cannot specify a minimum length < 1; use Opt(Word()) if zero-length word is permitted"
             )
 
+        if self.maxSpecified and min > max:
+            raise ValueError(
+                f"invalid args, if min and max both specified min must be <= max (min={min}, max={max})"
+            )
+
         self.minLen = min
 
         if max > 0:
@@ -2733,62 +2868,64 @@
             self.maxLen = _MAX_INT
 
         if exact > 0:
+            min = max = exact
             self.maxLen = exact
             self.minLen = exact
 
         self.errmsg = "Expected " + self.name
         self.mayIndexError = False
         self.asKeyword = asKeyword
+        if self.asKeyword:
+            self.errmsg += " as a keyword"
 
         # see if we can make a regex for this Word
-        if " " not in self.initChars | self.bodyChars and (min == 1 and exact == 0):
+        if " " not in (self.initChars | self.bodyChars):
+            if len(self.initChars) == 1:
+                re_leading_fragment = re.escape(self.initCharsOrig)
+            else:
+                re_leading_fragment = f"{_collapse_string_to_ranges(self.initChars)}"
+
             if self.bodyChars == self.initChars:
-                if max == 0:
+                if max == 0 and self.minLen == 1:
                     repeat = "+"
                 elif max == 1:
                     repeat = ""
                 else:
-                    repeat = "{{{},{}}}".format(
-                        self.minLen, "" if self.maxLen == _MAX_INT else self.maxLen
-                    )
-                self.reString = "{}{}".format(
-                    _collapse_string_to_ranges(self.initChars),
-                    repeat,
-                )
-            elif len(self.initChars) == 1:
-                if max == 0:
-                    repeat = "*"
-                else:
-                    repeat = "{{0,{}}}".format(max - 1)
-                self.reString = "{}{}{}".format(
-                    re.escape(self.initCharsOrig),
-                    _collapse_string_to_ranges(self.bodyChars),
-                    repeat,
-                )
+                    if self.minLen != self.maxLen:
+                        repeat = f"{{{self.minLen},{'' if self.maxLen == _MAX_INT else self.maxLen}}}"
+                    else:
+                        repeat = f"{{{self.minLen}}}"
+                self.reString = f"{re_leading_fragment}{repeat}"
             else:
-                if max == 0:
-                    repeat = "*"
-                elif max == 2:
+                if max == 1:
+                    re_body_fragment = ""
                     repeat = ""
                 else:
-                    repeat = "{{0,{}}}".format(max - 1)
-                self.reString = "{}{}{}".format(
-                    _collapse_string_to_ranges(self.initChars),
-                    _collapse_string_to_ranges(self.bodyChars),
-                    repeat,
-                )
+                    re_body_fragment = f"{_collapse_string_to_ranges(self.bodyChars)}"
+                    if max == 0 and self.minLen == 1:
+                        repeat = "*"
+                    elif max == 2:
+                        repeat = "?" if min <= 1 else ""
+                    else:
+                        if min != max:
+                            repeat = f"{{{min - 1 if min > 0 else ''},{max - 1 if max > 0 else ''}}}"
+                        else:
+                            repeat = f"{{{min - 1 if min > 0 else ''}}}"
+
+                self.reString = f"{re_leading_fragment}{re_body_fragment}{repeat}"
+
             if self.asKeyword:
-                self.reString = r"\b" + self.reString + r"\b"
+                self.reString = rf"\b{self.reString}\b"
 
             try:
                 self.re = re.compile(self.reString)
             except re.error:
-                self.re = None
+                self.re = None  # type: ignoreassignment
             else:
                 self.re_match = self.re.match
-                self.__class__ = _WordRegex
+                self.parseImpl = self.parseImpl_regex  # type: ignoreassignment
 
-    def _generateDefaultName(self):
+    def _generateDefaultName(self) -> str:
         def charsAsStr(s):
             max_repr_len = 16
             s = _collapse_string_to_ranges(s, re_escape=False)
@@ -2798,11 +2935,9 @@
                 return s
 
         if self.initChars != self.bodyChars:
-            base = "W:({}, {})".format(
-                charsAsStr(self.initChars), charsAsStr(self.bodyChars)
-            )
+            base = f"W:({charsAsStr(self.initChars)}, {charsAsStr(self.bodyChars)})"
         else:
-            base = "W:({})".format(charsAsStr(self.initChars))
+            base = f"W:({charsAsStr(self.initChars)})"
 
         # add length specification
         if self.minLen > 1 or self.maxLen != _MAX_INT:
@@ -2810,11 +2945,11 @@
                 if self.minLen == 1:
                     return base2:
                 else:
-                    return base + "{{{}}}".format(self.minLen)
+                    return base + f"{{{self.minLen}}}"
             elif self.maxLen == _MAX_INT:
-                return base + "{{{},...}}".format(self.minLen)
+                return base + f"{{{self.minLen},...}}"
             else:
-                return base + "{{{},{}}}".format(self.minLen, self.maxLen)
+                return base + f"{{{self.minLen},{self.maxLen}}}"
         return base
 
     def parseImpl(self, instring, loc, doActions=True):
@@ -2849,9 +2984,7 @@
 
         return loc, instringstart:loc
 
-
-class _WordRegex(Word):
-    def parseImpl(self, instring, loc, doActions=True):
+    def parseImpl_regex(self, instring, loc, doActions=True):
         result = self.re_match(instring, loc)
         if not result:
             raise ParseException(instring, loc, self.errmsg, self)
@@ -2860,7 +2993,7 @@
         return loc, result.group()
 
 
-class Char(_WordRegex):
+class Char(Word):
     """A short-cut class for defining :class:`Word` ``(characters, exact=1)``,
     when defining a match of any single character in a string of
     characters.
@@ -2878,13 +3011,8 @@
         asKeyword = asKeyword or as_keyword
         excludeChars = excludeChars or exclude_chars
         super().__init__(
-            charset, exact=1, asKeyword=asKeyword, excludeChars=excludeChars
+            charset, exact=1, as_keyword=asKeyword, exclude_chars=excludeChars
         )
-        self.reString = "{}".format(_collapse_string_to_ranges(self.initChars))
-        if asKeyword:
-            self.reString = r"\b{}\b".format(self.reString)
-        self.re = re.compile(self.reString)
-        self.re_match = self.re.match
 
 
 class Regex(Token):
@@ -2954,9 +3082,9 @@
         self.asGroupList = asGroupList
         self.asMatch = asMatch
         if self.asGroupList:
-            self.parseImpl = self.parseImplAsGroupList
+            self.parseImpl = self.parseImplAsGroupList  # type: ignore assignment
         if self.asMatch:
-            self.parseImpl = self.parseImplAsMatch
+            self.parseImpl = self.parseImplAsMatch  # type: ignore assignment
 
     @cached_property
     def re(self):
@@ -2966,9 +3094,7 @@
             try:
                 return re.compile(self.pattern, self.flags)
             except re.error:
-                raise ValueError(
-                    "invalid pattern ({!r}) passed to Regex".format(self.pattern)
-                )
+                raise ValueError(f"invalid pattern ({self.pattern!r}) passed to Regex")
 
     @cached_property
     def re_match(self):
@@ -2978,7 +3104,7 @@
     def mayReturnEmpty(self):
         return self.re_match("") is not None
 
-    def _generateDefaultName(self):
+    def _generateDefaultName(self) -> str:
         return "Re:({})".format(repr(self.pattern).replace("\\\\", "\\"))
 
     def parseImpl(self, instring, loc, doActions=True):
@@ -3024,10 +3150,12 @@
             # prints "<h1>main title</h1>"
         """
         if self.asGroupList:
-            raise TypeError("cannot use sub() with Regex(asGroupList=True)")
+            raise TypeError("cannot use sub() with Regex(as_group_list=True)")
 
         if self.asMatch and callable(repl):
-            raise TypeError("cannot use sub() with a callable with Regex(asMatch=True)")
+            raise TypeError(
+                "cannot use sub() with a callable with Regex(as_match=True)"
+            )
 
         if self.asMatch:
 
@@ -3081,7 +3209,7 @@
         'This is the "quote"'
         'This is the quote with "embedded" quotes'
     """
-    ws_map = ((r"\t", "\t"), (r"\n", "\n"), (r"\f", "\f"), (r"\r", "\r"))
+    ws_map = dict(((r"\t", "\t"), (r"\n", "\n"), (r"\f", "\f"), (r"\r", "\r")))
 
     def __init__(
         self,
@@ -3101,139 +3229,164 @@
         convertWhitespaceEscapes: bool = True,
     ):
         super().__init__()
-        escChar = escChar or esc_char
-        escQuote = escQuote or esc_quote
-        unquoteResults = unquoteResults and unquote_results
-        endQuoteChar = endQuoteChar or end_quote_char
-        convertWhitespaceEscapes = (
+        esc_char = escChar or esc_char
+        esc_quote = escQuote or esc_quote
+        unquote_results = unquoteResults and unquote_results
+        end_quote_char = endQuoteChar or end_quote_char
+        convert_whitespace_escapes = (
             convertWhitespaceEscapes and convert_whitespace_escapes
         )
         quote_char = quoteChar or quote_char
 
-        # remove white space from quote chars - wont work anyway
+        # remove white space from quote chars
         quote_char = quote_char.strip()
         if not quote_char:
             raise ValueError("quote_char cannot be the empty string")
 
-        if endQuoteChar is None:
-            endQuoteChar = quote_char
+        if end_quote_char is None:
+            end_quote_char = quote_char
         else:
-            endQuoteChar = endQuoteChar.strip()
-            if not endQuoteChar:
-                raise ValueError("endQuoteChar cannot be the empty string")
-
-        self.quoteChar = quote_char
-        self.quoteCharLen = len(quote_char)
-        self.firstQuoteChar = quote_char0
-        self.endQuoteChar = endQuoteChar
-        self.endQuoteCharLen = len(endQuoteChar)
-        self.escChar = escChar
-        self.escQuote = escQuote
-        self.unquoteResults = unquoteResults
-        self.convertWhitespaceEscapes = convertWhitespaceEscapes
-
-        sep = ""
-        inner_pattern = ""
-
-        if escQuote:
-            inner_pattern += r"{}(?:{})".format(sep, re.escape(escQuote))
-            sep = "|"
-
-        if escChar:
-            inner_pattern += r"{}(?:{}.)".format(sep, re.escape(escChar))
-            sep = "|"
-            self.escCharReplacePattern = re.escape(self.escChar) + "(.)"
-
-        if len(self.endQuoteChar) > 1:
-            inner_pattern += (
-                "{}(?:".format(sep)
+            end_quote_char = end_quote_char.strip()
+            if not end_quote_char:
+                raise ValueError("end_quote_char cannot be the empty string")
+
+        self.quote_char: str = quote_char
+        self.quote_char_len: int = len(quote_char)
+        self.first_quote_char: str = quote_char0
+        self.end_quote_char: str = end_quote_char
+        self.end_quote_char_len: int = len(end_quote_char)
+        self.esc_char: str = esc_char or ""
+        self.has_esc_char: bool = esc_char is not None
+        self.esc_quote: str = esc_quote or ""
+        self.unquote_results: bool = unquote_results
+        self.convert_whitespace_escapes: bool = convert_whitespace_escapes
+        self.multiline = multiline
+        self.re_flags = re.RegexFlag(0)
+
+        # fmt: off
+        # build up re pattern for the content between the quote delimiters
+        inner_pattern = 
+
+        if esc_quote:
+            inner_pattern.append(rf"(?:{re.escape(esc_quote)})")
+
+        if esc_char:
+            inner_pattern.append(rf"(?:{re.escape(esc_char)}.)")
+
+        if len(self.end_quote_char) > 1:
+            inner_pattern.append(
+                "(?:"
                 + "|".join(
-                    "(?:{}(?!{}))".format(
-                        re.escape(self.endQuoteChar:i),
-                        re.escape(self.endQuoteChari:),
-                    )
-                    for i in range(len(self.endQuoteChar) - 1, 0, -1)
+                    f"(?:{re.escape(self.end_quote_char:i)}(?!{re.escape(self.end_quote_chari:)}))"
+                    for i in range(len(self.end_quote_char) - 1, 0, -1)
                 )
                 + ")"
             )
-            sep = "|"
 
-        if multiline:
-            self.flags = re.MULTILINE | re.DOTALL
-            inner_pattern += r"{}(?:^{}{})".format(
-                sep,
-                _escape_regex_range_chars(self.endQuoteChar0),
-                (_escape_regex_range_chars(escChar) if escChar is not None else ""),
+        if self.multiline:
+            self.re_flags |= re.MULTILINE | re.DOTALL
+            inner_pattern.append(
+                rf"(?:^{_escape_regex_range_chars(self.end_quote_char0)}"
+                rf"{(_escape_regex_range_chars(esc_char) if self.has_esc_char else '')})"
             )
         else:
-            self.flags = 0
-            inner_pattern += r"{}(?:^{}\n\r{})".format(
-                sep,
-                _escape_regex_range_chars(self.endQuoteChar0),
-                (_escape_regex_range_chars(escChar) if escChar is not None else ""),
+            inner_pattern.append(
+                rf"(?:^{_escape_regex_range_chars(self.end_quote_char0)}\n\r"
+                rf"{(_escape_regex_range_chars(esc_char) if self.has_esc_char else '')})"
             )
 
         self.pattern = "".join(
             
-                re.escape(self.quoteChar),
+                re.escape(self.quote_char),
                 "(?:",
-                inner_pattern,
+                '|'.join(inner_pattern),
                 ")*",
-                re.escape(self.endQuoteChar),
+                re.escape(self.end_quote_char),
             
         )
 
+        if self.unquote_results:
+            if self.convert_whitespace_escapes:
+                self.unquote_scan_re = re.compile(
+                    rf"({'|'.join(re.escape(k) for k in self.ws_map)})"
+                    rf"|({re.escape(self.esc_char)}.)"
+                    rf"|(\n|.)",
+                    flags=self.re_flags,
+                )
+            else:
+                self.unquote_scan_re = re.compile(
+                    rf"({re.escape(self.esc_char)}.)"
+                    rf"|(\n|.)",
+                    flags=self.re_flags
+                )
+        # fmt: on
+
         try:
-            self.re = re.compile(self.pattern, self.flags)
+            self.re = re.compile(self.pattern, self.re_flags)
             self.reString = self.pattern
             self.re_match = self.re.match
         except re.error:
-            raise ValueError(
-                "invalid pattern {!r} passed to Regex".format(self.pattern)
-            )
+            raise ValueError(f"invalid pattern {self.pattern!r} passed to Regex")
 
         self.errmsg = "Expected " + self.name
         self.mayIndexError = False
         self.mayReturnEmpty = True
 
-    def _generateDefaultName(self):
-        if self.quoteChar == self.endQuoteChar and isinstance(self.quoteChar, str_type):
-            return "string enclosed in {!r}".format(self.quoteChar)
+    def _generateDefaultName(self) -> str:
+        if self.quote_char == self.end_quote_char and isinstance(
+            self.quote_char, str_type
+        ):
+            return f"string enclosed in {self.quote_char!r}"
 
-        return "quoted string, starting with {} ending with {}".format(
-            self.quoteChar, self.endQuoteChar
-        )
+        return f"quoted string, starting with {self.quote_char} ending with {self.end_quote_char}"
 
     def parseImpl(self, instring, loc, doActions=True):
+        # check first character of opening quote to see if that is a match
+        # before doing the more complicated regex match
         result = (
-            instringloc == self.firstQuoteChar
+            instringloc == self.first_quote_char
             and self.re_match(instring, loc)
             or None
         )
         if not result:
             raise ParseException(instring, loc, self.errmsg, self)
 
+        # get ending loc and matched string from regex matching result
         loc = result.end()
         ret = result.group()
 
-        if self.unquoteResults:
-
+        if self.unquote_results:
             # strip off quotes
-            ret = retself.quoteCharLen : -self.endQuoteCharLen
+            ret = retself.quote_char_len : -self.end_quote_char_len
 
             if isinstance(ret, str_type):
-                # replace escaped whitespace
-                if "\\" in ret and self.convertWhitespaceEscapes:
-                    for wslit, wschar in self.ws_map:
-                        ret = ret.replace(wslit, wschar)
-
-                # replace escaped characters
-                if self.escChar:
-                    ret = re.sub(self.escCharReplacePattern, r"\g<1>", ret)
+                # fmt: off
+                if self.convert_whitespace_escapes:
+                    # as we iterate over matches in the input string,
+                    # collect from whichever match group of the unquote_scan_re
+                    # regex matches (only 1 group will match at any given time)
+                    ret = "".join(
+                        # match group 1 matches \t, \n, etc.
+                        self.ws_mapmatch.group(1) if match.group(1)
+                        # match group 2 matches escaped characters
+                        else match.group(2)-1 if match.group(2)
+                        # match group 3 matches any character
+                        else match.group(3)
+                        for match in self.unquote_scan_re.finditer(ret)
+                    )
+                else:
+                    ret = "".join(
+                        # match group 1 matches escaped characters
+                        match.group(1)-1 if match.group(1)
+                        # match group 2 matches any character
+                        else match.group(2)
+                        for match in self.unquote_scan_re.finditer(ret)
+                    )
+                # fmt: on
 
                 # replace escaped quotes
-                if self.escQuote:
-                    ret = ret.replace(self.escQuote, self.endQuoteChar)
+                if self.esc_quote:
+                    ret = ret.replace(self.esc_quote, self.end_quote_char)
 
         return loc, ret
 
@@ -3252,7 +3405,7 @@
 
         # define a comma-separated-value as anything that is not a ','
         csv_value = CharsNotIn(',')
-        print(delimited_list(csv_value).parse_string("dkls,lsdkjf,s12 34,@!#,213"))
+        print(DelimitedList(csv_value).parse_string("dkls,lsdkjf,s12 34,@!#,213"))
 
     prints::
 
@@ -3294,12 +3447,12 @@
         self.mayReturnEmpty = self.minLen == 0
         self.mayIndexError = False
 
-    def _generateDefaultName(self):
+    def _generateDefaultName(self) -> str:
         not_chars_str = _collapse_string_to_ranges(self.notChars)
         if len(not_chars_str) > 16:
-            return "!W:({}...)".format(self.notChars: 16 - 3)
+            return f"!W:({self.notChars: 16 - 3}...)"
         else:
-            return "!W:({})".format(self.notChars)
+            return f"!W:({self.notChars})"
 
     def parseImpl(self, instring, loc, doActions=True):
         notchars = self.notCharsSet
@@ -3376,7 +3529,7 @@
             self.maxLen = exact
             self.minLen = exact
 
-    def _generateDefaultName(self):
+    def _generateDefaultName(self) -> str:
         return "".join(White.whiteStrsc for c in self.matchWhite)
 
     def parseImpl(self, instring, loc, doActions=True):
@@ -3411,7 +3564,7 @@
         super().__init__()
         self.col = colno
 
-    def preParse(self, instring, loc):
+    def preParse(self, instring: str, loc: int) -> int:
         if col(loc, instring) != self.col:
             instrlen = len(instring)
             if self.ignoreExprs:
@@ -3446,7 +3599,7 @@
         B AAA and definitely not this one
         '''
 
-        for t in (LineStart() + 'AAA' + restOfLine).search_string(test):
+        for t in (LineStart() + 'AAA' + rest_of_line).search_string(test):
             print(t)
 
     prints::
@@ -3464,7 +3617,7 @@
         self.skipper = Empty().set_whitespace_chars(self.whiteChars)
         self.errmsg = "Expected start of line"
 
-    def preParse(self, instring, loc):
+    def preParse(self, instring: str, loc: int) -> int:
         if loc == 0:
             return loc
         else:
@@ -3624,7 +3777,7 @@
                 self.exprs = exprs
         self.callPreparse = False
 
-    def recurse(self) -> SequenceParserElement:
+    def recurse(self) -> ListParserElement:
         return self.exprs:
 
     def append(self, other) -> ParserElement:
@@ -3669,8 +3822,8 @@
                 e.ignore(self.ignoreExprs-1)
         return self
 
-    def _generateDefaultName(self):
-        return "{}:({})".format(self.__class__.__name__, str(self.exprs))
+    def _generateDefaultName(self) -> str:
+        return f"{self.__class__.__name__}:({str(self.exprs)})"
 
     def streamline(self) -> ParserElement:
         if self.streamlined:
@@ -3714,6 +3867,11 @@
         return self
 
     def validate(self, validateTrace=None) -> None:
+        warnings.warn(
+            "ParserElement.validate() is deprecated, and should not be used to check for left recursion",
+            DeprecationWarning,
+            stacklevel=2,
+        )
         tmp = (validateTrace if validateTrace is not None else ): + self
         for e in self.exprs:
             e.validate(tmp)
@@ -3721,6 +3879,7 @@
 
     def copy(self) -> ParserElement:
         ret = super().copy()
+        ret = typing.cast(ParseExpression, ret)
         ret.exprs = e.copy() for e in self.exprs
         return ret
 
@@ -3750,8 +3909,14 @@
 
         return super()._setResultsName(name, listAllMatches)
 
-    ignoreWhitespace = ignore_whitespace
-    leaveWhitespace = leave_whitespace
+    # Compatibility synonyms
+    # fmt: off
+    @replaced_by_pep8(leave_whitespace)
+    def leaveWhitespace(self): ...
+
+    @replaced_by_pep8(ignore_whitespace)
+    def ignoreWhitespace(self): ...
+    # fmt: on
 
 
 class And(ParseExpression):
@@ -3777,7 +3942,7 @@
             super().__init__(*args, **kwargs)
             self.leave_whitespace()
 
-        def _generateDefaultName(self):
+        def _generateDefaultName(self) -> str:
             return "-"
 
     def __init__(
@@ -3789,7 +3954,9 @@
             for i, expr in enumerate(exprs):
                 if expr is Ellipsis:
                     if i < len(exprs) - 1:
-                        skipto_arg: ParserElement = (Empty() + exprsi + 1).exprs-1
+                        skipto_arg: ParserElement = typing.cast(
+                            ParseExpression, (Empty() + exprsi + 1)
+                        ).exprs-1
                         tmp.append(SkipTo(skipto_arg)("_skipped*"))
                     else:
                         raise Exception(
@@ -3822,8 +3989,9 @@
                 and isinstance(e.exprs-1, _PendingSkip)
                 for e in self.exprs:-1
             ):
+                deleted_expr_marker = NoMatch()
                 for i, e in enumerate(self.exprs:-1):
-                    if e is None:
+                    if e is deleted_expr_marker:
                         continue
                     if (
                         isinstance(e, ParseExpression)
@@ -3831,17 +3999,19 @@
                         and isinstance(e.exprs-1, _PendingSkip)
                     ):
                         e.exprs-1 = e.exprs-1 + self.exprsi + 1
-                        self.exprsi + 1 = None
-                self.exprs = e for e in self.exprs if e is not None
+                        self.exprsi + 1 = deleted_expr_marker
+                self.exprs = e for e in self.exprs if e is not deleted_expr_marker
 
         super().streamline()
 
         # link any IndentedBlocks to the prior expression
+        prev: ParserElement
+        cur: ParserElement
         for prev, cur in zip(self.exprs, self.exprs1:):
             # traverse cur or any first embedded expr of cur looking for an IndentedBlock
             # (but watch out for recursive grammar)
             seen = set()
-            while cur:
+            while True:
                 if id(cur) in seen:
                     break
                 seen.add(id(cur))
@@ -3853,7 +4023,10 @@
                     )
                     break
                 subs = cur.recurse()
-                cur = next(iter(subs), None)
+                next_first = next(iter(subs), None)
+                if next_first is None:
+                    break
+                cur = typing.cast(ParserElement, next_first)
 
         self.mayReturnEmpty = all(e.mayReturnEmpty for e in self.exprs)
         return self
@@ -3884,13 +4057,14 @@
                     )
             else:
                 loc, exprtokens = e._parse(instring, loc, doActions)
-            if exprtokens or exprtokens.haskeys():
-                resultlist += exprtokens
+            resultlist += exprtokens
         return loc, resultlist
 
     def __iadd__(self, other):
         if isinstance(other, str_type):
             other = self._literalStringClass(other)
+        if not isinstance(other, ParserElement):
+            return NotImplemented
         return self.append(other)  # And(self, other)
 
     def _checkRecursion(self, parseElementList):
@@ -3900,7 +4074,7 @@
             if not e.mayReturnEmpty:
                 break
 
-    def _generateDefaultName(self):
+    def _generateDefaultName(self) -> str:
         inner = " ".join(str(e) for e in self.exprs)
         # strip off redundant inner {}'s
         while len(inner) > 1 and inner0 :: len(inner) - 1 == "{}":
@@ -3958,7 +4132,7 @@
                 loc2 = e.try_parse(instring, loc, raise_fatal=True)
             except ParseFatalException as pfe:
                 pfe.__traceback__ = None
-                pfe.parserElement = e
+                pfe.parser_element = e
                 fatals.append(pfe)
                 maxException = None
                 maxExcLoc = -1
@@ -4016,12 +4190,15 @@
             if len(fatals) > 1:
                 fatals.sort(key=lambda e: -e.loc)
                 if fatals0.loc == fatals1.loc:
-                    fatals.sort(key=lambda e: (-e.loc, -len(str(e.parserElement))))
+                    fatals.sort(key=lambda e: (-e.loc, -len(str(e.parser_element))))
             max_fatal = fatals0
             raise max_fatal
 
         if maxException is not None:
-            maxException.msg = self.errmsg
+            # infer from this check that all alternatives failed at the current position
+            # so emit this collective error message instead of any single error message
+            if maxExcLoc == loc:
+                maxException.msg = self.errmsg
             raise maxException
         else:
             raise ParseException(
@@ -4031,9 +4208,11 @@
     def __ixor__(self, other):
         if isinstance(other, str_type):
             other = self._literalStringClass(other)
+        if not isinstance(other, ParserElement):
+            return NotImplemented
         return self.append(other)  # Or(self, other)
 
-    def _generateDefaultName(self):
+    def _generateDefaultName(self) -> str:
         return "{" + " ^ ".join(str(e) for e in self.exprs) + "}"
 
     def _setResultsName(self, name, listAllMatches=False):
@@ -4118,7 +4297,7 @@
                 )
             except ParseFatalException as pfe:
                 pfe.__traceback__ = None
-                pfe.parserElement = e
+                pfe.parser_element = e
                 raise
             except ParseException as err:
                 if err.loc > maxExcLoc:
@@ -4132,7 +4311,10 @@
                     maxExcLoc = len(instring)
 
         if maxException is not None:
-            maxException.msg = self.errmsg
+            # infer from this check that all alternatives failed at the current position
+            # so emit this collective error message instead of any individual error message
+            if maxExcLoc == loc:
+                maxException.msg = self.errmsg
             raise maxException
         else:
             raise ParseException(
@@ -4142,9 +4324,11 @@
     def __ior__(self, other):
         if isinstance(other, str_type):
             other = self._literalStringClass(other)
+        if not isinstance(other, ParserElement):
+            return NotImplemented
         return self.append(other)  # MatchFirst(self, other)
 
-    def _generateDefaultName(self):
+    def _generateDefaultName(self) -> str:
         return "{" + " | ".join(str(e) for e in self.exprs) + "}"
 
     def _setResultsName(self, name, listAllMatches=False):
@@ -4242,6 +4426,13 @@
         self.initExprGroups = True
         self.saveAsList = True
 
+    def __iand__(self, other):
+        if isinstance(other, str_type):
+            other = self._literalStringClass(other)
+        if not isinstance(other, ParserElement):
+            return NotImplemented
+        return self.append(other)  # Each(self, other)
+
     def streamline(self) -> ParserElement:
         super().streamline()
         if self.exprs:
@@ -4296,7 +4487,7 @@
                     tmpLoc = e.try_parse(instring, tmpLoc, raise_fatal=True)
                 except ParseFatalException as pfe:
                     pfe.__traceback__ = None
-                    pfe.parserElement = e
+                    pfe.parser_element = e
                     fatals.append(pfe)
                     failed.append(e)
                 except ParseException:
@@ -4315,7 +4506,7 @@
             if len(fatals) > 1:
                 fatals.sort(key=lambda e: -e.loc)
                 if fatals0.loc == fatals1.loc:
-                    fatals.sort(key=lambda e: (-e.loc, -len(str(e.parserElement))))
+                    fatals.sort(key=lambda e: (-e.loc, -len(str(e.parser_element))))
             max_fatal = fatals0
             raise max_fatal
 
@@ -4324,7 +4515,7 @@
             raise ParseException(
                 instring,
                 loc,
-                "Missing one or more required elements ({})".format(missing),
+                f"Missing one or more required elements ({missing})",
             )
 
         # add any unmatched Opts, in case they have default values defined
@@ -4337,7 +4528,7 @@
 
         return loc, total_results
 
-    def _generateDefaultName(self):
+    def _generateDefaultName(self) -> str:
         return "{" + " & ".join(str(e) for e in self.exprs) + "}"
 
 
@@ -4349,12 +4540,14 @@
     def __init__(self, expr: UnionParserElement, str, savelist: bool = False):
         super().__init__(savelist)
         if isinstance(expr, str_type):
+            expr_str = typing.cast(str, expr)
             if issubclass(self._literalStringClass, Token):
-                expr = self._literalStringClass(expr)
+                expr = self._literalStringClass(expr_str)  # type: ignorecall-arg
             elif issubclass(type(self), self._literalStringClass):
-                expr = Literal(expr)
+                expr = Literal(expr_str)
             else:
-                expr = self._literalStringClass(Literal(expr))
+                expr = self._literalStringClass(Literal(expr_str))  # type: ignoreassignment, call-arg
+        expr = typing.cast(ParserElement, expr)
         self.expr = expr
         if expr is not None:
             self.mayIndexError = expr.mayIndexError
@@ -4367,12 +4560,17 @@
             self.callPreparse = expr.callPreparse
             self.ignoreExprs.extend(expr.ignoreExprs)
 
-    def recurse(self) -> SequenceParserElement:
+    def recurse(self) -> ListParserElement:
         return self.expr if self.expr is not None else 
 
     def parseImpl(self, instring, loc, doActions=True):
         if self.expr is not None:
-            return self.expr._parse(instring, loc, doActions, callPreParse=False)
+            try:
+                return self.expr._parse(instring, loc, doActions, callPreParse=False)
+            except ParseBaseException as pbe:
+                if not isinstance(self, Forward) or self.customName is not None:
+                    pbe.msg = self.errmsg
+                raise
         else:
             raise ParseException(instring, loc, "No expression defined", self)
 
@@ -4380,8 +4578,8 @@
         super().leave_whitespace(recursive)
 
         if recursive:
-            self.expr = self.expr.copy()
             if self.expr is not None:
+                self.expr = self.expr.copy()
                 self.expr.leave_whitespace(recursive)
         return self
 
@@ -4389,8 +4587,8 @@
         super().ignore_whitespace(recursive)
 
         if recursive:
-            self.expr = self.expr.copy()
             if self.expr is not None:
+                self.expr = self.expr.copy()
                 self.expr.ignore_whitespace(recursive)
         return self
 
@@ -4420,6 +4618,11 @@
             self.expr._checkRecursion(subRecCheckList)
 
     def validate(self, validateTrace=None) -> None:
+        warnings.warn(
+            "ParserElement.validate() is deprecated, and should not be used to check for left recursion",
+            DeprecationWarning,
+            stacklevel=2,
+        )
         if validateTrace is None:
             validateTrace = 
         tmp = validateTrace: + self
@@ -4427,11 +4630,17 @@
             self.expr.validate(tmp)
         self._checkRecursion()
 
-    def _generateDefaultName(self):
-        return "{}:({})".format(self.__class__.__name__, str(self.expr))
+    def _generateDefaultName(self) -> str:
+        return f"{self.__class__.__name__}:({str(self.expr)})"
+
+    # Compatibility synonyms
+    # fmt: off
+    @replaced_by_pep8(leave_whitespace)
+    def leaveWhitespace(self): ...
 
-    ignoreWhitespace = ignore_whitespace
-    leaveWhitespace = leave_whitespace
+    @replaced_by_pep8(ignore_whitespace)
+    def ignoreWhitespace(self): ...
+    # fmt: on
 
 
 class IndentedBlock(ParseElementEnhance):
@@ -4443,13 +4652,13 @@
     class _Indent(Empty):
         def __init__(self, ref_col: int):
             super().__init__()
-            self.errmsg = "expected indent at column {}".format(ref_col)
+            self.errmsg = f"expected indent at column {ref_col}"
             self.add_condition(lambda s, l, t: col(l, s) == ref_col)
 
     class _IndentGreater(Empty):
         def __init__(self, ref_col: int):
             super().__init__()
-            self.errmsg = "expected indent at column greater than {}".format(ref_col)
+            self.errmsg = f"expected indent at column greater than {ref_col}"
             self.add_condition(lambda s, l, t: col(l, s) > ref_col)
 
     def __init__(
@@ -4469,7 +4678,7 @@
 
         # see if self.expr matches at the current location - if not it will raise an exception
         # and no further work is necessary
-        self.expr.try_parse(instring, anchor_loc, doActions)
+        self.expr.try_parse(instring, anchor_loc, do_actions=doActions)
 
         indent_col = col(anchor_loc, instring)
         peer_detect_expr = self._Indent(indent_col)
@@ -4532,7 +4741,7 @@
         B AAA and definitely not this one
         '''
 
-        for t in (AtLineStart('AAA') + restOfLine).search_string(test):
+        for t in (AtLineStart('AAA') + rest_of_line).search_string(test):
             print(t)
 
     prints::
@@ -4598,9 +4807,9 @@
 
     Parameters:
 
-    - expr - expression that must match prior to the current parse
+    - ``expr`` - expression that must match prior to the current parse
       location
-    - retreat - (default= ``None``) - (int) maximum number of characters
+    - ``retreat`` - (default= ``None``) - (int) maximum number of characters
       to lookbehind prior to the current parse location
 
     If the lookbehind expression is a string, :class:`Literal`,
@@ -4627,6 +4836,7 @@
         self.mayIndexError = False
         self.exact = False
         if isinstance(expr, str_type):
+            expr = typing.cast(str, expr)
             retreat = len(expr)
             self.exact = True
         elif isinstance(expr, (Literal, Keyword)):
@@ -4746,18 +4956,18 @@
         self.errmsg = "Found unwanted token, " + str(self.expr)
 
     def parseImpl(self, instring, loc, doActions=True):
-        if self.expr.can_parse_next(instring, loc):
+        if self.expr.can_parse_next(instring, loc, do_actions=doActions):
             raise ParseException(instring, loc, self.errmsg, self)
         return loc, 
 
-    def _generateDefaultName(self):
+    def _generateDefaultName(self) -> str:
         return "~{" + str(self.expr) + "}"
 
 
 class _MultipleMatch(ParseElementEnhance):
     def __init__(
         self,
-        expr: ParserElement,
+        expr: Unionstr, ParserElement,
         stop_on: typing.OptionalUnionParserElement, str = None,
         *,
         stopOn: typing.OptionalUnionParserElement, str = None,
@@ -4781,7 +4991,7 @@
         self_skip_ignorables = self._skipIgnorables
         check_ender = self.not_ender is not None
         if check_ender:
-            try_not_ender = self.not_ender.tryParse
+            try_not_ender = self.not_ender.try_parse
 
         # must be at least one (but first see if we are the stopOn sentinel;
         # if so, fail)
@@ -4798,8 +5008,7 @@
                 else:
                     preloc = loc
                 loc, tmptokens = self_expr_parse(instring, preloc, doActions)
-                if tmptokens or tmptokens.haskeys():
-                    tokens += tmptokens
+                tokens += tmptokens
         except (ParseException, IndexError):
             pass
 
@@ -4837,10 +5046,11 @@
     Repetition of one or more of the given expression.
 
     Parameters:
-    - expr - expression that must match one or more times
-    - stop_on - (default= ``None``) - expression for a terminating sentinel
-         (only required if the sentinel would ordinarily match the repetition
-         expression)
+
+    - ``expr`` - expression that must match one or more times
+    - ``stop_on`` - (default= ``None``) - expression for a terminating sentinel
+      (only required if the sentinel would ordinarily match the repetition
+      expression)
 
     Example::
 
@@ -4859,7 +5069,7 @@
         (attr_expr * (1,)).parse_string(text).pprint()
     """
 
-    def _generateDefaultName(self):
+    def _generateDefaultName(self) -> str:
         return "{" + str(self.expr) + "}..."
 
 
@@ -4868,6 +5078,7 @@
     Optional repetition of zero or more of the given expression.
 
     Parameters:
+
     - ``expr`` - expression that must match zero or more times
     - ``stop_on`` - expression for a terminating sentinel
       (only required if the sentinel would ordinarily match the repetition
@@ -4878,7 +5089,7 @@
 
     def __init__(
         self,
-        expr: ParserElement,
+        expr: Unionstr, ParserElement,
         stop_on: typing.OptionalUnionParserElement, str = None,
         *,
         stopOn: typing.OptionalUnionParserElement, str = None,
@@ -4892,10 +5103,75 @@
         except (ParseException, IndexError):
             return loc, ParseResults(, name=self.resultsName)
 
-    def _generateDefaultName(self):
+    def _generateDefaultName(self) -> str:
         return "" + str(self.expr) + "..."
 
 
+class DelimitedList(ParseElementEnhance):
+    def __init__(
+        self,
+        expr: Unionstr, ParserElement,
+        delim: Unionstr, ParserElement = ",",
+        combine: bool = False,
+        min: typing.Optionalint = None,
+        max: typing.Optionalint = None,
+        *,
+        allow_trailing_delim: bool = False,
+    ):
+        """Helper to define a delimited list of expressions - the delimiter
+        defaults to ','. By default, the list elements and delimiters can
+        have intervening whitespace, and comments, but this can be
+        overridden by passing ``combine=True`` in the constructor. If
+        ``combine`` is set to ``True``, the matching tokens are
+        returned as a single token string, with the delimiters included;
+        otherwise, the matching tokens are returned as a list of tokens,
+        with the delimiters suppressed.
+
+        If ``allow_trailing_delim`` is set to True, then the list may end with
+        a delimiter.
+
+        Example::
+
+            DelimitedList(Word(alphas)).parse_string("aa,bb,cc") # -> 'aa', 'bb', 'cc'
+            DelimitedList(Word(hexnums), delim=':', combine=True).parse_string("AA:BB:CC:DD:EE") # -> 'AA:BB:CC:DD:EE'
+        """
+        if isinstance(expr, str_type):
+            expr = ParserElement._literalStringClass(expr)
+        expr = typing.cast(ParserElement, expr)
+
+        if min is not None:
+            if min < 1:
+                raise ValueError("min must be greater than 0")
+        if max is not None:
+            if min is not None and max < min:
+                raise ValueError("max must be greater than, or equal to min")
+
+        self.content = expr
+        self.raw_delim = str(delim)
+        self.delim = delim
+        self.combine = combine
+        if not combine:
+            self.delim = Suppress(delim)
+        self.min = min or 1
+        self.max = max
+        self.allow_trailing_delim = allow_trailing_delim
+
+        delim_list_expr = self.content + (self.delim + self.content) * (
+            self.min - 1,
+            None if self.max is None else self.max - 1,
+        )
+        if self.allow_trailing_delim:
+            delim_list_expr += Opt(self.delim)
+
+        if self.combine:
+            delim_list_expr = Combine(delim_list_expr)
+
+        super().__init__(delim_list_expr, savelist=True)
+
+    def _generateDefaultName(self) -> str:
+        return "{0} {1} {0}...".format(self.content.streamline(), self.raw_delim)
+
+
 class _NullToken:
     def __bool__(self):
         return False
@@ -4909,6 +5185,7 @@
     Optional matching of the given expression.
 
     Parameters:
+
     - ``expr`` - expression that must match zero or more times
     - ``default`` (optional) - value to be returned if the optional expression is not found.
 
@@ -4969,7 +5246,7 @@
                 tokens = 
         return loc, tokens
 
-    def _generateDefaultName(self):
+    def _generateDefaultName(self) -> str:
         inner = str(self.expr)
         # strip off redundant inner {}'s
         while len(inner) > 1 and inner0 :: len(inner) - 1 == "{}":
@@ -4986,6 +5263,7 @@
     expression is found.
 
     Parameters:
+
     - ``expr`` - target expression marking the end of the data to be skipped
     - ``include`` - if ``True``, the target expression is also parsed
       (the skipped text and target expression are returned as a 2-element
@@ -5045,10 +5323,10 @@
         self,
         other: UnionParserElement, str,
         include: bool = False,
-        ignore: bool = None,
+        ignore: typing.OptionalUnionParserElement, str = None,
         fail_on: typing.OptionalUnionParserElement, str = None,
         *,
-        failOn: UnionParserElement, str = None,
+        failOn: typing.OptionalUnionParserElement, str = None,
     ):
         super().__init__(other)
         failOn = failOn or fail_on
@@ -5062,6 +5340,20 @@
         else:
             self.failOn = failOn
         self.errmsg = "No match found for " + str(self.expr)
+        self.ignorer = Empty().leave_whitespace()
+        self._update_ignorer()
+
+    def _update_ignorer(self):
+        # rebuild internal ignore expr from current ignore exprs and assigned ignoreExpr
+        self.ignorer.ignoreExprs.clear()
+        for e in self.expr.ignoreExprs:
+            self.ignorer.ignore(e)
+        if self.ignoreExpr:
+            self.ignorer.ignore(self.ignoreExpr)
+
+    def ignore(self, expr):
+        super().ignore(expr)
+        self._update_ignorer()
 
     def parseImpl(self, instring, loc, doActions=True):
         startloc = loc
@@ -5070,9 +5362,7 @@
         self_failOn_canParseNext = (
             self.failOn.canParseNext if self.failOn is not None else None
         )
-        self_ignoreExpr_tryParse = (
-            self.ignoreExpr.tryParse if self.ignoreExpr is not None else None
-        )
+        ignorer_try_parse = self.ignorer.try_parse if self.ignorer.ignoreExprs else None
 
         tmploc = loc
         while tmploc <= instrlen:
@@ -5081,13 +5371,18 @@
                 if self_failOn_canParseNext(instring, tmploc):
                     break
 
-            if self_ignoreExpr_tryParse is not None:
+            if ignorer_try_parse is not None:
                 # advance past ignore expressions
+                prev_tmploc = tmploc
                 while 1:
                     try:
-                        tmploc = self_ignoreExpr_tryParse(instring, tmploc)
+                        tmploc = ignorer_try_parse(instring, tmploc)
                     except ParseBaseException:
                         break
+                    # see if all ignorers matched, but didn't actually ignore anything
+                    if tmploc == prev_tmploc:
+                        break
+                    prev_tmploc = tmploc
 
             try:
                 self_expr_parse(instring, tmploc, doActions=False, callPreParse=False)
@@ -5145,15 +5440,20 @@
 
     def __init__(self, other: typing.OptionalUnionParserElement, str = None):
         self.caller_frame = traceback.extract_stack(limit=2)0
-        super().__init__(other, savelist=False)
+        super().__init__(other, savelist=False)  # type: ignorearg-type
         self.lshift_line = None
 
-    def __lshift__(self, other):
+    def __lshift__(self, other) -> "Forward":
         if hasattr(self, "caller_frame"):
             del self.caller_frame
         if isinstance(other, str_type):
             other = self._literalStringClass(other)
+
+        if not isinstance(other, ParserElement):
+            return NotImplemented
+
         self.expr = other
+        self.streamlined = other.streamlined
         self.mayIndexError = self.expr.mayIndexError
         self.mayReturnEmpty = self.expr.mayReturnEmpty
         self.set_whitespace_chars(
@@ -5162,13 +5462,16 @@
         self.skipWhitespace = self.expr.skipWhitespace
         self.saveAsList = self.expr.saveAsList
         self.ignoreExprs.extend(self.expr.ignoreExprs)
-        self.lshift_line = traceback.extract_stack(limit=2)-2
+        self.lshift_line = traceback.extract_stack(limit=2)-2  # type: ignoreassignment
         return self
 
-    def __ilshift__(self, other):
+    def __ilshift__(self, other) -> "Forward":
+        if not isinstance(other, ParserElement):
+            return NotImplemented
+
         return self << other
 
-    def __or__(self, other):
+    def __or__(self, other) -> "ParserElement":
         caller_line = traceback.extract_stack(limit=2)-2
         if (
             __diag__.warn_on_match_first_with_lshift_operator
@@ -5205,12 +5508,12 @@
             not in self.suppress_warnings_
         ):
             # walk stack until parse_string, scan_string, search_string, or transform_string is found
-            parse_fns = 
+            parse_fns = (
                 "parse_string",
                 "scan_string",
                 "search_string",
                 "transform_string",
-            
+            )
             tb = traceback.extract_stack(limit=200)
             for i, frm in enumerate(reversed(tb), start=1):
                 if frm.name in parse_fns:
@@ -5308,6 +5611,11 @@
         return self
 
     def validate(self, validateTrace=None) -> None:
+        warnings.warn(
+            "ParserElement.validate() is deprecated, and should not be used to check for left recursion",
+            DeprecationWarning,
+            stacklevel=2,
+        )
         if validateTrace is None:
             validateTrace = 
 
@@ -5317,7 +5625,7 @@
                 self.expr.validate(tmp)
         self._checkRecursion()
 
-    def _generateDefaultName(self):
+    def _generateDefaultName(self) -> str:
         # Avoid infinite recursion by setting a temporary _defaultName
         self._defaultName = ": ..."
 
@@ -5356,8 +5664,14 @@
 
         return super()._setResultsName(name, list_all_matches)
 
-    ignoreWhitespace = ignore_whitespace
-    leaveWhitespace = leave_whitespace
+    # Compatibility synonyms
+    # fmt: off
+    @replaced_by_pep8(leave_whitespace)
+    def leaveWhitespace(self): ...
+
+    @replaced_by_pep8(ignore_whitespace)
+    def ignoreWhitespace(self): ...
+    # fmt: on
 
 
 class TokenConverter(ParseElementEnhance):
@@ -5439,11 +5753,11 @@
         ident = Word(alphas)
         num = Word(nums)
         term = ident | num
-        func = ident + Opt(delimited_list(term))
+        func = ident + Opt(DelimitedList(term))
         print(func.parse_string("fn a, b, 100"))
         # -> 'fn', 'a', 'b', '100'
 
-        func = ident + Group(Opt(delimited_list(term)))
+        func = ident + Group(Opt(DelimitedList(term)))
         print(func.parse_string("fn a, b, 100"))
         # -> 'fn', 'a', 'b', '100'
     """
@@ -5579,7 +5893,7 @@
         'a', 'b', 'c', 'd'
         'START', 'relevant text ', 'END'
 
-    (See also :class:`delimited_list`.)
+    (See also :class:`DelimitedList`.)
     """
 
     def __init__(self, expr: UnionParserElement, str, savelist: bool = False):
@@ -5638,15 +5952,13 @@
         s, l, t = paArgs-3:
         if len(paArgs) > 3:
             thisFunc = paArgs0.__class__.__name__ + "." + thisFunc
-        sys.stderr.write(
-            ">>entering {}(line: {!r}, {}, {!r})\n".format(thisFunc, line(l, s), l, t)
-        )
+        sys.stderr.write(f">>entering {thisFunc}(line: {line(l, s)!r}, {l}, {t!r})\n")
         try:
             ret = f(*paArgs)
         except Exception as exc:
-            sys.stderr.write("<<leaving {} (exception: {})\n".format(thisFunc, exc))
+            sys.stderr.write(f"<<leaving {thisFunc} (exception: {exc})\n")
             raise
-        sys.stderr.write("<<leaving {} (ret: {!r})\n".format(thisFunc, ret))
+        sys.stderr.write(f"<<leaving {thisFunc} (ret: {ret!r})\n")
         return ret
 
     z.__name__ = f.__name__
@@ -5660,7 +5972,7 @@
 string_start = StringStart().set_name("string_start")
 string_end = StringEnd().set_name("string_end")
 
-_escapedPunc = Word(_bslash, r"\-*.$+^?()~ ", exact=2).set_parse_action(
+_escapedPunc = Regex(r"\\\\\\/\-\*\.\$\+\^\?()~ ").set_parse_action(
     lambda s, l, t: t01
 )
 _escapedHexChar = Regex(r"\\0?xX0-9a-fA-F+").set_parse_action(
@@ -5677,7 +5989,7 @@
     Literal("")
     + Opt("^").set_results_name("negate")
     + Group(OneOrMore(_charRange | _singleChar)).set_results_name("body")
-    + ""
+    + Literal("")
 )
 
 
@@ -5714,7 +6026,7 @@
     )
     try:
         return "".join(_expanded(part) for part in _reBracketExpr.parse_string(s).body)
-    except Exception:
+    except Exception as e:
         return ""
 
 
@@ -5769,7 +6081,11 @@
     Utility to simplify mass-naming of parser elements, for
     generating railroad diagram with named subdiagrams.
     """
-    for name, var in sys._getframe().f_back.f_locals.items():
+    calling_frame = sys._getframe().f_back
+    if calling_frame is None:
+        return
+    calling_frame = typing.cast(types.FrameType, calling_frame)
+    for name, var in calling_frame.f_locals.items():
         if isinstance(var, ParserElement) and not var.customName:
             var.set_name(name)
 
@@ -5783,9 +6099,28 @@
 ).set_name("string enclosed in single quotes")
 
 quoted_string = Combine(
-    Regex(r'"(?:^"\n\r\\|(?:"")|(?:\\(?:^x|x0-9a-fA-F+)))*') + '"'
-    | Regex(r"'(?:^'\n\r\\|(?:'')|(?:\\(?:^x|x0-9a-fA-F+)))*") + "'"
-).set_name("quotedString using single or double quotes")
+    (Regex(r'"(?:^"\n\r\\|(?:"")|(?:\\(?:^x|x0-9a-fA-F+)))*') + '"').set_name(
+        "double quoted string"
+    )
+    | (Regex(r"'(?:^'\n\r\\|(?:'')|(?:\\(?:^x|x0-9a-fA-F+)))*") + "'").set_name(
+        "single quoted string"
+    )
+).set_name("quoted string using single or double quotes")
+
+python_quoted_string = Combine(
+    (Regex(r'"""(?:^"\\|""(?!")|"(?!"")|\\.)*', flags=re.MULTILINE) + '"""').set_name(
+        "multiline double quoted string"
+    )
+    ^ (
+        Regex(r"'''(?:^'\\|''(?!')|'(?!'')|\\.)*", flags=re.MULTILINE) + "'''"
+    ).set_name("multiline single quoted string")
+    ^ (Regex(r'"(?:^"\n\r\\|(?:\\")|(?:\\(?:^x|x0-9a-fA-F+)))*') + '"').set_name(
+        "double quoted string"
+    )
+    ^ (Regex(r"'(?:^'\n\r\\|(?:\\')|(?:\\(?:^x|x0-9a-fA-F+)))*") + "'").set_name(
+        "single quoted string"
+    )
+).set_name("Python quoted string")
 
 unicode_string = Combine("u" + quoted_string.copy()).set_name("unicode string literal")
 
@@ -5800,9 +6135,7 @@
 
 
 # backward compatibility names
-tokenMap = token_map
-conditionAsParseAction = condition_as_parse_action
-nullDebugAction = null_debug_action
+# fmt: off
 sglQuotedString = sgl_quoted_string
 dblQuotedString = dbl_quoted_string
 quotedString = quoted_string
@@ -5811,4 +6144,16 @@
 lineEnd = line_end
 stringStart = string_start
 stringEnd = string_end
-traceParseAction = trace_parse_action
+
+@replaced_by_pep8(null_debug_action)
+def nullDebugAction(): ...
+
+@replaced_by_pep8(trace_parse_action)
+def traceParseAction(): ...
+
+@replaced_by_pep8(condition_as_parse_action)
+def conditionAsParseAction(): ...
+
+@replaced_by_pep8(token_map)
+def tokenMap(): ...
+# fmt: on

_service:tar_scm:pyparsing-3.0.9.tar.gz/pyparsing/diagram/__init__.py -> _service:tar_scm:pyparsing-3.1.1.tar.gz/pyparsing/diagram/__init__.py Changed

@@ -1,3 +1,4 @@
+# mypy: ignore-errors
 import railroad
 import pyparsing
 import typing
@@ -17,11 +18,13 @@
 
 
 jinja2_template_source = """\
+{% if not embed %}
 <!DOCTYPE html>
 <html>
 <head>
+{% endif %}
     {% if not head %}
-        <style type="text/css">
+        <style>
             .railroad-heading {
                 font-family: monospace;
             }
@@ -29,8 +32,10 @@
     {% else %}
         {{ head | safe }}
     {% endif %}
+{% if not embed %}
 </head>
 <body>
+{% endif %}
 {{ body | safe }}
 {% for diagram in diagrams %}
     <div class="railroad-group">
@@ -41,8 +46,10 @@
         </div>
     </div>
 {% endfor %}
+{% if not embed %}
 </body>
 </html>
+{% endif %}
 """
 
 template = Template(jinja2_template_source)
@@ -127,7 +134,7 @@
         return self.func(*args, **kwargs)
 
 
-def railroad_to_html(diagrams: ListNamedDiagram, **kwargs) -> str:
+def railroad_to_html(diagrams: ListNamedDiagram, embed=False, **kwargs) -> str:
     """
     Given a list of NamedDiagram, produce a single HTML string that visualises those diagrams
     :params kwargs: kwargs to be passed in to the template
@@ -137,13 +144,17 @@
         if diagram.diagram is None:
             continue
         io = StringIO()
-        diagram.diagram.writeSvg(io.write)
+        try:
+            css = kwargs.get('css')
+            diagram.diagram.writeStandalone(io.write, css=css)
+        except AttributeError:
+            diagram.diagram.writeSvg(io.write)
         title = diagram.name
         if diagram.index == 0:
             title += " (root)"
         data.append({"title": title, "text": "", "svg": io.getvalue()})
 
-    return template.render(diagrams=data, **kwargs)
+    return template.render(diagrams=data, embed=embed, **kwargs)
 
 
 def resolve_partial(partial: "EditablePartialT") -> T:
@@ -398,7 +409,6 @@
         show_results_names: bool = False,
         show_groups: bool = False,
     ) -> typing.OptionalEditablePartial:
-
         ret = fn(
             element,
             parent,
@@ -555,9 +565,11 @@
         else:
             ret = EditablePartial.from_call(railroad.Group, label="", item="")
     elif isinstance(element, pyparsing.TokenConverter):
-        ret = EditablePartial.from_call(
-            AnnotatedItem, label=type(element).__name__.lower(), item=""
-        )
+        label = type(element).__name__.lower()
+        if label == "tokenconverter":
+            ret = EditablePartial.from_call(railroad.Sequence, items=)
+        else:
+            ret = EditablePartial.from_call(AnnotatedItem, label=label, item="")
     elif isinstance(element, pyparsing.Opt):
         ret = EditablePartial.from_call(railroad.Optional, item="")
     elif isinstance(element, pyparsing.OneOrMore):
@@ -571,10 +583,12 @@
     elif isinstance(element, pyparsing.Empty) and not element.customName:
         # Skip unnamed "Empty" elements
         ret = None
-    elif len(exprs) > 1:
+    elif isinstance(element, pyparsing.ParseElementEnhance):
         ret = EditablePartial.from_call(railroad.Sequence, items=)
     elif len(exprs) > 0 and not element_results_name:
         ret = EditablePartial.from_call(railroad.Group, item="", label=name)
+    elif len(exprs) > 0:
+        ret = EditablePartial.from_call(railroad.Sequence, items=)
     else:
         terminal = EditablePartial.from_call(railroad.Terminal, element.defaultName)
         ret = terminal

_service:tar_scm:pyparsing-3.0.9.tar.gz/pyparsing/exceptions.py -> _service:tar_scm:pyparsing-3.1.1.tar.gz/pyparsing/exceptions.py Changed

@@ -4,7 +4,13 @@
 import sys
 import typing
 
-from .util import col, line, lineno, _collapse_string_to_ranges
+from .util import (
+    col,
+    line,
+    lineno,
+    _collapse_string_to_ranges,
+    replaced_by_pep8,
+)
 from .unicode import pyparsing_unicode as ppu
 
 
@@ -19,6 +25,20 @@
 class ParseBaseException(Exception):
     """base exception class for all parsing runtime exceptions"""
 
+    loc: int
+    msg: str
+    pstr: str
+    parser_element: typing.Any  # "ParserElement"
+    args: typing.Tuplestr, int, typing.Optionalstr
+
+    __slots__ = (
+        "loc",
+        "msg",
+        "pstr",
+        "parser_element",
+        "args",
+    )
+
     # Performance tuning: we construct a *lot* of these, so keep this
     # constructor as small and fast as possible
     def __init__(
@@ -35,7 +55,7 @@
         else:
             self.msg = msg
             self.pstr = pstr
-        self.parser_element = self.parserElement = elem
+        self.parser_element = elem
         self.args = (pstr, loc, msg)
 
     @staticmethod
@@ -64,7 +84,7 @@
         if isinstance(exc, ParseBaseException):
             ret.append(exc.line)
             ret.append(" " * (exc.column - 1) + "^")
-        ret.append("{}: {}".format(type(exc).__name__, exc))
+        ret.append(f"{type(exc).__name__}: {exc}")
 
         if depth > 0:
             callers = inspect.getinnerframes(exc.__traceback__, context=depth)
@@ -74,7 +94,9 @@
 
                 f_self = frm.f_locals.get("self", None)
                 if isinstance(f_self, ParserElement):
-                    if frm.f_code.co_name not in ("parseImpl", "_parseNoCache"):
+                    if not frm.f_code.co_name.startswith(
+                        ("parseImpl", "_parseNoCache")
+                    ):
                         continue
                     if id(f_self) in seen:
                         continue
@@ -82,21 +104,19 @@
 
                     self_type = type(f_self)
                     ret.append(
-                        "{}.{} - {}".format(
-                            self_type.__module__, self_type.__name__, f_self
-                        )
+                        f"{self_type.__module__}.{self_type.__name__} - {f_self}"
                     )
 
                 elif f_self is not None:
                     self_type = type(f_self)
-                    ret.append("{}.{}".format(self_type.__module__, self_type.__name__))
+                    ret.append(f"{self_type.__module__}.{self_type.__name__}")
 
                 else:
                     code = frm.f_code
                     if code.co_name in ("wrapper", "<module>"):
                         continue
 
-                    ret.append("{}".format(code.co_name))
+                    ret.append(code.co_name)
 
                 depth -= 1
                 if not depth:
@@ -110,7 +130,7 @@
         internal factory method to simplify creating one type of ParseException
         from another - avoids having __init__ signature conflicts among subclasses
         """
-        return cls(pe.pstr, pe.loc, pe.msg, pe.parserElement)
+        return cls(pe.pstr, pe.loc, pe.msg, pe.parser_element)
 
     @property
     def line(self) -> str:
@@ -140,6 +160,15 @@
         """
         return col(self.loc, self.pstr)
 
+    # pre-PEP8 compatibility
+    @property
+    def parserElement(self):
+        return self.parser_element
+
+    @parserElement.setter
+    def parserElement(self, elem):
+        self.parser_element = elem
+
     def __str__(self) -> str:
         if self.pstr:
             if self.loc >= len(self.pstr):
@@ -154,14 +183,14 @@
                 foundstr = (", found %r" % found).replace(r"\\", "\\")
         else:
             foundstr = ""
-        return "{}{}  (at char {}), (line:{}, col:{})".format(
-            self.msg, foundstr, self.loc, self.lineno, self.column
-        )
+        return f"{self.msg}{foundstr}  (at char {self.loc}), (line:{self.lineno}, col:{self.column})"
 
     def __repr__(self):
         return str(self)
 
-    def mark_input_line(self, marker_string: str = None, *, markerString=">!<") -> str:
+    def mark_input_line(
+        self, marker_string: typing.Optionalstr = None, *, markerString: str = ">!<"
+    ) -> str:
         """
         Extracts the exception line from the input string, and marks
         the location of the exception with a special symbol.
@@ -214,7 +243,10 @@
         """
         return self.explain_exception(self, depth)
 
-    markInputline = mark_input_line
+    # fmt: off
+    @replaced_by_pep8(mark_input_line)
+    def markInputline(self): ...
+    # fmt: on
 
 
 class ParseException(ParseBaseException):
@@ -264,4 +296,4 @@
         self.parseElementTrace = parseElementList
 
     def __str__(self) -> str:
-        return "RecursiveGrammarException: {}".format(self.parseElementTrace)
+        return f"RecursiveGrammarException: {self.parseElementTrace}"

_service:tar_scm:pyparsing-3.0.9.tar.gz/pyparsing/helpers.py -> _service:tar_scm:pyparsing-3.1.1.tar.gz/pyparsing/helpers.py Changed

@@ -1,73 +1,22 @@
 # helpers.py
 import html.entities
 import re
+import sys
 import typing
 
 from . import __diag__
 from .core import *
-from .util import _bslash, _flatten, _escape_regex_range_chars
+from .util import (
+    _bslash,
+    _flatten,
+    _escape_regex_range_chars,
+    replaced_by_pep8,
+)
 
 
 #
 # global helpers
 #
-def delimited_list(
-    expr: Unionstr, ParserElement,
-    delim: Unionstr, ParserElement = ",",
-    combine: bool = False,
-    min: typing.Optionalint = None,
-    max: typing.Optionalint = None,
-    *,
-    allow_trailing_delim: bool = False,
-) -> ParserElement:
-    """Helper to define a delimited list of expressions - the delimiter
-    defaults to ','. By default, the list elements and delimiters can
-    have intervening whitespace, and comments, but this can be
-    overridden by passing ``combine=True`` in the constructor. If
-    ``combine`` is set to ``True``, the matching tokens are
-    returned as a single token string, with the delimiters included;
-    otherwise, the matching tokens are returned as a list of tokens,
-    with the delimiters suppressed.
-
-    If ``allow_trailing_delim`` is set to True, then the list may end with
-    a delimiter.
-
-    Example::
-
-        delimited_list(Word(alphas)).parse_string("aa,bb,cc") # -> 'aa', 'bb', 'cc'
-        delimited_list(Word(hexnums), delim=':', combine=True).parse_string("AA:BB:CC:DD:EE") # -> 'AA:BB:CC:DD:EE'
-    """
-    if isinstance(expr, str_type):
-        expr = ParserElement._literalStringClass(expr)
-
-    dlName = "{expr} {delim} {expr}...{end}".format(
-        expr=str(expr.copy().streamline()),
-        delim=str(delim),
-        end=" {}".format(str(delim)) if allow_trailing_delim else "",
-    )
-
-    if not combine:
-        delim = Suppress(delim)
-
-    if min is not None:
-        if min < 1:
-            raise ValueError("min must be greater than 0")
-        min -= 1
-    if max is not None:
-        if min is not None and max <= min:
-            raise ValueError("max must be greater than, or equal to min")
-        max -= 1
-    delimited_list_expr = expr + (delim + expr)min, max
-
-    if allow_trailing_delim:
-        delimited_list_expr += Opt(delim)
-
-    if combine:
-        return Combine(delimited_list_expr).set_name(dlName)
-    else:
-        return delimited_list_expr.set_name(dlName)
-
-
 def counted_array(
     expr: ParserElement,
     int_expr: typing.OptionalParserElement = None,
@@ -187,7 +136,7 @@
             theseTokens = _flatten(t.as_list())
             if theseTokens != matchTokens:
                 raise ParseException(
-                    s, l, "Expected {}, found{}".format(matchTokens, theseTokens)
+                    s, l, f"Expected {matchTokens}, found{theseTokens}"
                 )
 
         rep.set_parse_action(must_match_these_tokens, callDuringTry=True)
@@ -218,7 +167,7 @@
     - ``caseless`` - treat all literals as caseless - (default= ``False``)
     - ``use_regex`` - as an optimization, will
       generate a :class:`Regex` object; otherwise, will generate
-      a :class:`MatchFirst` object (if ``caseless=True`` or ``asKeyword=True``, or if
+      a :class:`MatchFirst` object (if ``caseless=True`` or ``as_keyword=True``, or if
       creating a :class:`Regex` raises an exception) - (default= ``True``)
     - ``as_keyword`` - enforce :class:`Keyword`-style matching on the
       generated expressions - (default= ``False``)
@@ -262,6 +211,7 @@
 
     symbols: Liststr = 
     if isinstance(strs, str_type):
+        strs = typing.cast(str, strs)
         symbols = strs.split()
     elif isinstance(strs, Iterable):
         symbols = list(strs)
@@ -293,15 +243,13 @@
         try:
             if all(len(sym) == 1 for sym in symbols):
                 # symbols are just single characters, create range regex pattern
-                patt = "{}".format(
-                    "".join(_escape_regex_range_chars(sym) for sym in symbols)
-                )
+                patt = f"{''.join(_escape_regex_range_chars(sym) for sym in symbols)}"
             else:
                 patt = "|".join(re.escape(sym) for sym in symbols)
 
             # wrap with \b word break markers if defining as keywords
             if asKeyword:
-                patt = r"\b(?:{})\b".format(patt)
+                patt = rf"\b(?:{patt})\b"
 
             ret = Regex(patt, flags=re_flags).set_name(" | ".join(symbols))
 
@@ -371,7 +319,7 @@
     expression.  Useful to restore the parsed fields of an HTML start
     tag into the raw tag text itself, or to revert separate tokens with
     intervening whitespace back to the original matching input text. By
-    default, returns astring containing the original parsed text.
+    default, returns a string containing the original parsed text.
 
     If the optional ``as_string`` argument is passed as
     ``False``, then the return value is
@@ -390,7 +338,7 @@
         src = "this is test <b> bold <i>text</i> </b> normal text "
         for tag in ("b", "i"):
             opener, closer = make_html_tags(tag)
-            patt = original_text_for(opener + SkipTo(closer) + closer)
+            patt = original_text_for(opener + ... + closer)
             print(patt.search_string(src)0)
 
     prints::
@@ -426,7 +374,7 @@
 
 def locatedExpr(expr: ParserElement) -> ParserElement:
     """
-    (DEPRECATED - future code should use the Located class)
+    (DEPRECATED - future code should use the :class:`Located` class)
     Helper to decorate a returned token with its starting and ending
     locations in the input string.
 
@@ -437,12 +385,12 @@
     - ``value`` - the actual parsed results
 
     Be careful if the input text contains ``<TAB>`` characters, you
-    may want to call :class:`ParserElement.parseWithTabs`
+    may want to call :class:`ParserElement.parse_with_tabs`
 
     Example::
 
         wd = Word(alphas)
-        for match in locatedExpr(wd).searchString("ljsdf123lksdjjf123lkkjj1222"):
+        for match in locatedExpr(wd).search_string("ljsdf123lksdjjf123lkkjj1222"):
             print(match)
 
     prints::
@@ -471,6 +419,7 @@
     closing delimiters (``"("`` and ``")"`` are the default).
 
     Parameters:
+
     - ``opener`` - opening character for a nested list
       (default= ``"("``); can also be a pyparsing expression
     - ``closer`` - closing character for a nested list
@@ -507,7 +456,7 @@
 
         c_function = (decl_data_type("type")
                       + ident("name")
-                      + LPAR + Opt(delimited_list(arg), )("args") + RPAR
+                      + LPAR + Opt(DelimitedList(arg), )("args") + RPAR
                       + code_body("body"))
         c_function.ignore(c_style_comment)
 
@@ -539,6 +488,8 @@
         raise ValueError("opening and closing strings cannot be the same")
     if content is None:
         if isinstance(opener, str_type) and isinstance(closer, str_type):
+            opener = typing.cast(str, opener)
+            closer = typing.cast(str, closer)
             if len(opener) == 1 and len(closer) == 1:
                 if ignoreExpr is not None:
                     content = Combine(
@@ -695,12 +646,15 @@
 )
 
 
-def replace_html_entity(t):
+def replace_html_entity(s, l, t):
     """Helper parser action to replace common HTML entities with their special characters"""
     return _htmlEntityMap.get(t.entity)
 
 
 class OpAssoc(Enum):
+    """Enumeration of operator associativity
+    - used in constructing InfixNotationOperatorSpec for :class:`infix_notation`"""
+
     LEFT = 1
     RIGHT = 2
 
@@ -742,6 +696,7 @@
     improve your parser performance.
 
     Parameters:
+
     - ``base_expr`` - expression representing the most basic operand to
       be used in the expression
     - ``op_list`` - list of tuples, one for each operator precedence level
@@ -764,11 +719,11 @@
         ``set_parse_action(*fn)``
         (:class:`ParserElement.set_parse_action`)
     - ``lpar`` - expression for matching left-parentheses; if passed as a
-      str, then will be parsed as Suppress(lpar). If lpar is passed as
+      str, then will be parsed as ``Suppress(lpar)``. If lpar is passed as
       an expression (such as ``Literal('(')``), then it will be kept in
       the parsed results, and grouped with them. (default= ``Suppress('(')``)
     - ``rpar`` - expression for matching right-parentheses; if passed as a
-      str, then will be parsed as Suppress(rpar). If rpar is passed as
+      str, then will be parsed as ``Suppress(rpar)``. If rpar is passed as
       an expression (such as ``Literal(')')``), then it will be kept in
       the parsed results, and grouped with them. (default= ``Suppress(')')``)
 
@@ -800,9 +755,13 @@
         (5+3)*6
         5, '+', 3, '*', 6
 
+        (5+x)*y
+        5, '+', 'x', '*', 'y'
+
         -2--11
         '-', 2, '-', '-', 11
     """
+
     # captive version of FollowedBy that does not do parse actions or capture results names
     class _FB(FollowedBy):
         def parseImpl(self, instring, loc, doActions=True):
@@ -823,19 +782,25 @@
     else:
         lastExpr = base_expr | (lpar + ret + rpar)
 
+    arity: int
+    rightLeftAssoc: opAssoc
+    pa: typing.OptionalParseAction
+    opExpr1: ParserElement
+    opExpr2: ParserElement
     for i, operDef in enumerate(op_list):
-        opExpr, arity, rightLeftAssoc, pa = (operDef + (None,)):4
+        opExpr, arity, rightLeftAssoc, pa = (operDef + (None,)):4  # type: ignoreassignment
         if isinstance(opExpr, str_type):
             opExpr = ParserElement._literalStringClass(opExpr)
+        opExpr = typing.cast(ParserElement, opExpr)
         if arity == 3:
             if not isinstance(opExpr, (tuple, list)) or len(opExpr) != 2:
                 raise ValueError(
                     "if numterms=3, opExpr must be a tuple or list of two expressions"
                 )
             opExpr1, opExpr2 = opExpr
-            term_name = "{}{} term".format(opExpr1, opExpr2)
+            term_name = f"{opExpr1}{opExpr2} term"
         else:
-            term_name = "{} term".format(opExpr)
+            term_name = f"{opExpr} term"
 
         if not 1 <= arity <= 3:
             raise ValueError("operator must be unary (1), binary (2), or ternary (3)")
@@ -843,7 +808,8 @@
         if rightLeftAssoc not in (OpAssoc.LEFT, OpAssoc.RIGHT):
             raise ValueError("operator must indicate right or left associativity")
 
-        thisExpr: Forward = Forward().set_name(term_name)
+        thisExpr: ParserElement = Forward().set_name(term_name)
+        thisExpr = typing.cast(Forward, thisExpr)
         if rightLeftAssoc is OpAssoc.LEFT:
             if arity == 1:
                 matchExpr = _FB(lastExpr + opExpr) + Group(lastExpr + opExpr1, ...)
@@ -890,7 +856,7 @@
 
 def indentedBlock(blockStatementExpr, indentStack, indent=True, backup_stacks=):
     """
-    (DEPRECATED - use IndentedBlock class instead)
+    (DEPRECATED - use :class:`IndentedBlock` class instead)
     Helper method for defining space-delimited indentation blocks,
     such as those used to define block statements in Python source code.
 
@@ -1063,22 +1029,28 @@
 
 
 
+# compatibility function, superseded by DelimitedList class
+def delimited_list(
+    expr: Unionstr, ParserElement,
+    delim: Unionstr, ParserElement = ",",
+    combine: bool = False,
+    min: typing.Optionalint = None,
+    max: typing.Optionalint = None,
+    *,
+    allow_trailing_delim: bool = False,
+) -> ParserElement:
+    """(DEPRECATED - use :class:`DelimitedList` class)"""
+    return DelimitedList(
+        expr, delim, combine, min, max, allow_trailing_delim=allow_trailing_delim
+    )
+
+
 # pre-PEP8 compatible names
-delimitedList = delimited_list
-countedArray = counted_array
-matchPreviousLiteral = match_previous_literal
-matchPreviousExpr = match_previous_expr
-oneOf = one_of
-dictOf = dict_of
-originalTextFor = original_text_for
-nestedExpr = nested_expr
-makeHTMLTags = make_html_tags
-makeXMLTags = make_xml_tags
-anyOpenTag, anyCloseTag = any_open_tag, any_close_tag
-commonHTMLEntity = common_html_entity
-replaceHTMLEntity = replace_html_entity
+# fmt: off
 opAssoc = OpAssoc
-infixNotation = infix_notation
+anyOpenTag = any_open_tag
+anyCloseTag = any_close_tag
+commonHTMLEntity = common_html_entity
 cStyleComment = c_style_comment
 htmlComment = html_comment
 restOfLine = rest_of_line
@@ -1086,3 +1058,43 @@
 cppStyleComment = cpp_style_comment
 javaStyleComment = java_style_comment
 pythonStyleComment = python_style_comment
+
+@replaced_by_pep8(DelimitedList)
+def delimitedList(): ...
+
+@replaced_by_pep8(DelimitedList)
+def delimited_list(): ...
+
+@replaced_by_pep8(counted_array)
+def countedArray(): ...
+
+@replaced_by_pep8(match_previous_literal)
+def matchPreviousLiteral(): ...
+
+@replaced_by_pep8(match_previous_expr)
+def matchPreviousExpr(): ...
+
+@replaced_by_pep8(one_of)
+def oneOf(): ...
+
+@replaced_by_pep8(dict_of)
+def dictOf(): ...
+
+@replaced_by_pep8(original_text_for)
+def originalTextFor(): ...
+
+@replaced_by_pep8(nested_expr)
+def nestedExpr(): ...
+
+@replaced_by_pep8(make_html_tags)
+def makeHTMLTags(): ...
+
+@replaced_by_pep8(make_xml_tags)
+def makeXMLTags(): ...
+
+@replaced_by_pep8(replace_html_entity)
+def replaceHTMLEntity(): ...
+
+@replaced_by_pep8(infix_notation)
+def infixNotation(): ...
+# fmt: on

_service:tar_scm:pyparsing-3.0.9.tar.gz/pyparsing/results.py -> _service:tar_scm:pyparsing-3.1.1.tar.gz/pyparsing/results.py Changed

@@ -1,18 +1,25 @@
 # results.py
-from collections.abc import MutableMapping, Mapping, MutableSequence, Iterator
+from collections.abc import (
+    MutableMapping,
+    Mapping,
+    MutableSequence,
+    Iterator,
+    Sequence,
+    Container,
+)
 import pprint
-from weakref import ref as wkref
-from typing import Tuple, Any
+from typing import Tuple, Any, Dict, Set, List
 
 str_type: Tupletype, ... = (str, bytes)
 _generator_type = type((_ for _ in ()))
 
 
 class _ParseResultsWithOffset:
+    tup: Tuple"ParseResults", int
     __slots__ = "tup"
 
-    def __init__(self, p1, p2):
-        self.tup = (p1, p2)
+    def __init__(self, p1: "ParseResults", p2: int):
+        self.tup: TupleParseResults, int = (p1, p2)
 
     def __getitem__(self, i):
         return self.tupi
@@ -47,7 +54,7 @@
         result = date_str.parse_string("1999/12/31")
 
         def test(s, fn=repr):
-            print("{} -> {}".format(s, fn(eval(s))))
+            print(f"{s} -> {fn(eval(s))}")
         test("list(result)")
         test("result0")
         test("result'month'")
@@ -70,27 +77,33 @@
         - year: '1999'
     """
 
-    _null_values: TupleAny, ... = (None, , "", ())
+    _null_values: TupleAny, ... = (None, , ())
 
-    __slots__ = 
+    _name: str
+    _parent: "ParseResults"
+    _all_names: Setstr
+    _modal: bool
+    _toklist: ListAny
+    _tokdict: Dictstr, Any
+
+    __slots__ = (
         "_name",
         "_parent",
         "_all_names",
         "_modal",
         "_toklist",
         "_tokdict",
-        "__weakref__",
-    
+    )
 
     class List(list):
         """
         Simple wrapper class to distinguish parsed list results that should be preserved
-        as actual Python lists, instead of being converted to :class:`ParseResults`:
+        as actual Python lists, instead of being converted to :class:`ParseResults`::
 
             LBRACK, RBRACK = map(pp.Suppress, "")
             element = pp.Forward()
             item = ppc.integer
-            element_list = LBRACK + pp.delimited_list(element) + RBRACK
+            element_list = LBRACK + pp.DelimitedList(element) + RBRACK
 
             # add parse actions to convert from ParseResults to actual Python collection types
             def as_python_list(t):
@@ -107,7 +120,7 @@
                 (2,3,4)
                 ''', post_parse=lambda s, r: (r0, type(r0)))
 
-        prints:
+        prints::
 
             100
             (100, <class 'int'>)
@@ -127,8 +140,7 @@
 
             if not isinstance(contained, list):
                 raise TypeError(
-                    "{} may only be constructed with a list,"
-                    " not {}".format(cls.__name__, type(contained).__name__)
+                    f"{cls.__name__} may only be constructed with a list, not {type(contained).__name__}"
                 )
 
             return list.__new__(cls)
@@ -159,6 +171,7 @@
     def __init__(
         self, toklist=None, name=None, asList=True, modal=True, isinstance=isinstance
     ):
+        self._tokdict: Dictstr, _ParseResultsWithOffset
         self._modal = modal
         if name is not None and name != "":
             if isinstance(name, int):
@@ -210,7 +223,7 @@
             
             sub = v
         if isinstance(sub, ParseResults):
-            sub._parent = wkref(self)
+            sub._parent = self
 
     def __delitem__(self, i):
         if isinstance(i, (int, slice)):
@@ -263,7 +276,7 @@
         """
         Since ``keys()`` returns an iterator, this method is helpful in bypassing
         code that looks for the existence of any defined results names."""
-        return bool(self._tokdict)
+        return not not self._tokdict
 
     def pop(self, *args, **kwargs):
         """
@@ -311,9 +324,7 @@
             if k == "default":
                 args = (args0, v)
             else:
-                raise TypeError(
-                    "pop() got an unexpected keyword argument {!r}".format(k)
-                )
+                raise TypeError(f"pop() got an unexpected keyword argument {k!r}")
         if isinstance(args0, int) or len(args) == 1 or args0 in self:
             index = args0
             ret = selfindex
@@ -423,12 +434,15 @@
                 raise AttributeError(name)
             return ""
 
-    def __add__(self, other) -> "ParseResults":
+    def __add__(self, other: "ParseResults") -> "ParseResults":
         ret = self.copy()
         ret += other
         return ret
 
-    def __iadd__(self, other) -> "ParseResults":
+    def __iadd__(self, other: "ParseResults") -> "ParseResults":
+        if not other:
+            return self
+
         if other._tokdict:
             offset = len(self._toklist)
             addoffset = lambda a: offset if a < 0 else a + offset
@@ -441,7 +455,7 @@
             for k, v in otherdictitems:
                 selfk = v
                 if isinstance(v0, ParseResults):
-                    v0._parent = wkref(self)
+                    v0._parent = self
 
         self._toklist += other._toklist
         self._all_names |= other._all_names
@@ -456,7 +470,7 @@
             return other + self
 
     def __repr__(self) -> str:
-        return "{}({!r}, {})".format(type(self).__name__, self._toklist, self.as_dict())
+        return f"{type(self).__name__}({self._toklist!r}, {self.as_dict()})"
 
     def __str__(self) -> str:
         return (
@@ -532,7 +546,10 @@
 
     def copy(self) -> "ParseResults":
         """
-        Returns a new copy of a :class:`ParseResults` object.
+        Returns a new shallow copy of a :class:`ParseResults` object. `ParseResults`
+        items contained within the source are shared with the copy. Use
+        :class:`ParseResults.deepcopy()` to create a copy with its own separate
+        content values.
         """
         ret = ParseResults(self._toklist)
         ret._tokdict = self._tokdict.copy()
@@ -541,6 +558,27 @@
         ret._name = self._name
         return ret
 
+    def deepcopy(self) -> "ParseResults":
+        """
+        Returns a new deep copy of a :class:`ParseResults` object.
+        """
+        ret = self.copy()
+        # replace values with copies if they are of known mutable types
+        for i, obj in enumerate(self._toklist):
+            if isinstance(obj, ParseResults):
+                self._toklisti = obj.deepcopy()
+            elif isinstance(obj, (str, bytes)):
+                pass
+            elif isinstance(obj, MutableMapping):
+                self._toklisti = dest = type(obj)()
+                for k, v in obj.items():
+                    destk = v.deepcopy() if isinstance(v, ParseResults) else v
+            elif isinstance(obj, Container):
+                self._toklisti = type(obj)(
+                    v.deepcopy() if isinstance(v, ParseResults) else v for v in obj
+                )
+        return ret
+
     def get_name(self):
         r"""
         Returns the results name for this token expression. Useful when several
@@ -569,20 +607,17 @@
         if self._name:
             return self._name
         elif self._parent:
-            par = self._parent()
-
-            def find_in_parent(sub):
-                return next(
-                    (
-                        k
-                        for k, vlist in par._tokdict.items()
-                        for v, loc in vlist
-                        if sub is v
-                    ),
-                    None,
-                )
-
-            return find_in_parent(self) if par else None
+            par: "ParseResults" = self._parent
+            parent_tokdict_items = par._tokdict.items()
+            return next(
+                (
+                    k
+                    for k, vlist in parent_tokdict_items
+                    for v, loc in vlist
+                    if v is self
+                ),
+                None,
+            )
         elif (
             len(self) == 1
             and len(self._tokdict) == 1
@@ -623,7 +658,7 @@
                 for k, v in items:
                     if out:
                         out.append(NL)
-                    out.append("{}{}- {}: ".format(indent, ("  " * _depth), k))
+                    out.append(f"{indent}{('  ' * _depth)}- {k}: ")
                     if isinstance(v, ParseResults):
                         if v:
                             out.append(
@@ -685,7 +720,7 @@
             num = Word(nums)
             func = Forward()
             term = ident | num | Group('(' + func + ')')
-            func <<= ident + Group(Optional(delimited_list(term)))
+            func <<= ident + Group(Optional(DelimitedList(term)))
             result = func.parse_string("fna a,b,(fnb c,d,200),100")
             result.pprint(width=40)
 
@@ -705,7 +740,7 @@
             self._toklist,
             (
                 self._tokdict.copy(),
-                self._parent is not None and self._parent() or None,
+                None,
                 self._all_names,
                 self._name,
             ),
@@ -714,10 +749,7 @@
     def __setstate__(self, state):
         self._toklist, (self._tokdict, par, inAccumNames, self._name) = state
         self._all_names = set(inAccumNames)
-        if par is not None:
-            self._parent = wkref(par)
-        else:
-            self._parent = None
+        self._parent = None
 
     def __getnewargs__(self):
         return self._toklist, self._name
@@ -738,6 +770,7 @@
                 iter(obj)
             except Exception:
                 return False
+            # str's are iterable, but in pyparsing, we don't want to iterate over them
             else:
                 return not isinstance(obj, str_type)
 
@@ -752,8 +785,11 @@
         return ret
 
     asList = as_list
+    """Deprecated - use :class:`as_list`"""
     asDict = as_dict
+    """Deprecated - use :class:`as_dict`"""
     getName = get_name
+    """Deprecated - use :class:`get_name`"""
 
 
 MutableMapping.register(ParseResults)

_service:tar_scm:pyparsing-3.0.9.tar.gz/pyparsing/testing.py -> _service:tar_scm:pyparsing-3.1.1.tar.gz/pyparsing/testing.py Changed

@@ -222,7 +222,7 @@
                             )
                         else:
                             # warning here maybe?
-                            print("no validation for {!r}".format(test_string))
+                            print(f"no validation for {test_string!r}")
 
             # do this last, in case some specific test results can be reported instead
             self.assertTrue(
@@ -265,15 +265,18 @@
         if expand_tabs:
             s = s.expandtabs()
         if mark_control is not None:
+            mark_control = typing.cast(str, mark_control)
             if mark_control == "unicode":
-                tbl = str.maketrans(
-                    {c: u for c, u in zip(range(0, 33), range(0x2400, 0x2433))}
-                    | {127: 0x2421}
-                )
+                transtable_map = {
+                    c: u for c, u in zip(range(0, 33), range(0x2400, 0x2433))
+                }
+                transtable_map127 = 0x2421
+                tbl = str.maketrans(transtable_map)
                 eol_mark = ""
             else:
+                ord_mark_control = ord(mark_control)
                 tbl = str.maketrans(
-                    {c: mark_control for c in list(range(0, 32)) + 127}
+                    {c: ord_mark_control for c in list(range(0, 32)) + 127}
                 )
             s = s.translate(tbl)
         if mark_spaces is not None and mark_spaces != " ":
@@ -303,7 +306,7 @@
             header0 = (
                 lead
                 + "".join(
-                    "{}{}".format(" " * 99, (i + 1) % 100)
+                    f"{' ' * 99}{(i + 1) % 100}"
                     for i in range(max(max_line_len // 100, 1))
                 )
                 + "\n"
@@ -313,10 +316,7 @@
         header1 = (
             header0
             + lead
-            + "".join(
-                "         {}".format((i + 1) % 10)
-                for i in range(-(-max_line_len // 10))
-            )
+            + "".join(f"         {(i + 1) % 10}" for i in range(-(-max_line_len // 10)))
             + "\n"
         )
         header2 = lead + "1234567890" * (-(-max_line_len // 10)) + "\n"
@@ -324,7 +324,7 @@
             header1
             + header2
             + "\n".join(
-                "{:{}d}:{}{}".format(i, lineno_width, line, eol_mark)
+                f"{i:{lineno_width}d}:{line}{eol_mark}"
                 for i, line in enumerate(s_lines, start=start_line)
             )
             + "\n"

_service:tar_scm:pyparsing-3.0.9.tar.gz/pyparsing/unicode.py -> _service:tar_scm:pyparsing-3.1.1.tar.gz/pyparsing/unicode.py Changed

@@ -64,27 +64,27 @@
 
     @_lazyclassproperty
     def printables(cls):
-        "all non-whitespace characters in this range"
+        """all non-whitespace characters in this range"""
         return "".join(filterfalse(str.isspace, cls._chars_for_ranges))
 
     @_lazyclassproperty
     def alphas(cls):
-        "all alphabetic characters in this range"
+        """all alphabetic characters in this range"""
         return "".join(filter(str.isalpha, cls._chars_for_ranges))
 
     @_lazyclassproperty
     def nums(cls):
-        "all numeric digit characters in this range"
+        """all numeric digit characters in this range"""
         return "".join(filter(str.isdigit, cls._chars_for_ranges))
 
     @_lazyclassproperty
     def alphanums(cls):
-        "all alphanumeric characters in this range"
+        """all alphanumeric characters in this range"""
         return cls.alphas + cls.nums
 
     @_lazyclassproperty
     def identchars(cls):
-        "all characters in this range that are valid identifier characters, plus underscore '_'"
+        """all characters in this range that are valid identifier characters, plus underscore '_'"""
         return "".join(
             sorted(
                 set(
@@ -100,13 +100,13 @@
     def identbodychars(cls):
         """
         all characters in this range that are valid identifier body characters,
-        plus the digits 0-9
+        plus the digits 0-9, and · (Unicode MIDDLE DOT)
         """
         return "".join(
             sorted(
                 set(
                     cls.identchars
-                    + "0123456789"
+                    + "0123456789·"
                     + "".join(
                         c for c in cls._chars_for_ranges if ("_" + c).isidentifier()
                     )
@@ -114,6 +114,16 @@
             )
         )
 
+    @_lazyclassproperty
+    def identifier(cls):
+        """
+        a pyparsing Word expression for an identifier using this range's definitions for
+        identchars and identbodychars
+        """
+        from pyparsing import Word
+
+        return Word(cls.identchars, cls.identbodychars)
+
 
 class pyparsing_unicode(unicode_set):
     """
@@ -128,32 +138,32 @@
     
 
     class BasicMultilingualPlane(unicode_set):
-        "Unicode set for the Basic Multilingual Plane"
+        """Unicode set for the Basic Multilingual Plane"""
         _ranges: UnicodeRangeList = 
             (0x0020, 0xFFFF),
         
 
     class Latin1(unicode_set):
-        "Unicode set for Latin-1 Unicode Character Range"
+        """Unicode set for Latin-1 Unicode Character Range"""
         _ranges: UnicodeRangeList = 
             (0x0020, 0x007E),
             (0x00A0, 0x00FF),
         
 
     class LatinA(unicode_set):
-        "Unicode set for Latin-A Unicode Character Range"
+        """Unicode set for Latin-A Unicode Character Range"""
         _ranges: UnicodeRangeList = 
             (0x0100, 0x017F),
         
 
     class LatinB(unicode_set):
-        "Unicode set for Latin-B Unicode Character Range"
+        """Unicode set for Latin-B Unicode Character Range"""
         _ranges: UnicodeRangeList = 
             (0x0180, 0x024F),
         
 
     class Greek(unicode_set):
-        "Unicode set for Greek Unicode Character Ranges"
+        """Unicode set for Greek Unicode Character Ranges"""
         _ranges: UnicodeRangeList = 
             (0x0342, 0x0345),
             (0x0370, 0x0377),
@@ -193,7 +203,7 @@
         
 
     class Cyrillic(unicode_set):
-        "Unicode set for Cyrillic Unicode Character Range"
+        """Unicode set for Cyrillic Unicode Character Range"""
         _ranges: UnicodeRangeList = 
             (0x0400, 0x052F),
             (0x1C80, 0x1C88),
@@ -206,7 +216,7 @@
         
 
     class Chinese(unicode_set):
-        "Unicode set for Chinese Unicode Character Range"
+        """Unicode set for Chinese Unicode Character Range"""
         _ranges: UnicodeRangeList = 
             (0x2E80, 0x2E99),
             (0x2E9B, 0x2EF3),
@@ -229,8 +239,7 @@
         
 
     class Japanese(unicode_set):
-        "Unicode set for Japanese Unicode Character Range, combining Kanji, Hiragana, and Katakana ranges"
-        _ranges: UnicodeRangeList = 
+        """Unicode set for Japanese Unicode Character Range, combining Kanji, Hiragana, and Katakana ranges"""
 
         class Kanji(unicode_set):
             "Unicode set for Kanji Unicode Character Range"
@@ -240,7 +249,7 @@
             
 
         class Hiragana(unicode_set):
-            "Unicode set for Hiragana Unicode Character Range"
+            """Unicode set for Hiragana Unicode Character Range"""
             _ranges: UnicodeRangeList = 
                 (0x3041, 0x3096),
                 (0x3099, 0x30A0),
@@ -252,7 +261,7 @@
             
 
         class Katakana(unicode_set):
-            "Unicode set for Katakana  Unicode Character Range"
+            """Unicode set for Katakana  Unicode Character Range"""
             _ranges: UnicodeRangeList = 
                 (0x3099, 0x309C),
                 (0x30A0, 0x30FF),
@@ -265,8 +274,18 @@
                 (0x1F213,),
             
 
+        漢字 = Kanji
+        カタカナ = Katakana
+        ひらがな = Hiragana
+
+        _ranges = (
+            Kanji._ranges
+            + Hiragana._ranges
+            + Katakana._ranges
+        )
+
     class Hangul(unicode_set):
-        "Unicode set for Hangul (Korean) Unicode Character Range"
+        """Unicode set for Hangul (Korean) Unicode Character Range"""
         _ranges: UnicodeRangeList = 
             (0x1100, 0x11FF),
             (0x302E, 0x302F),
@@ -288,17 +307,17 @@
     Korean = Hangul
 
     class CJK(Chinese, Japanese, Hangul):
-        "Unicode set for combined Chinese, Japanese, and Korean (CJK) Unicode Character Range"
+        """Unicode set for combined Chinese, Japanese, and Korean (CJK) Unicode Character Range"""
 
     class Thai(unicode_set):
-        "Unicode set for Thai Unicode Character Range"
+        """Unicode set for Thai Unicode Character Range"""
         _ranges: UnicodeRangeList = 
             (0x0E01, 0x0E3A),
             (0x0E3F, 0x0E5B)
         
 
     class Arabic(unicode_set):
-        "Unicode set for Arabic Unicode Character Range"
+        """Unicode set for Arabic Unicode Character Range"""
         _ranges: UnicodeRangeList = 
             (0x0600, 0x061B),
             (0x061E, 0x06FF),
@@ -306,7 +325,7 @@
         
 
     class Hebrew(unicode_set):
-        "Unicode set for Hebrew Unicode Character Range"
+        """Unicode set for Hebrew Unicode Character Range"""
         _ranges: UnicodeRangeList = 
             (0x0591, 0x05C7),
             (0x05D0, 0x05EA),
@@ -320,33 +339,23 @@
         
 
     class Devanagari(unicode_set):
-        "Unicode set for Devanagari Unicode Character Range"
+        """Unicode set for Devanagari Unicode Character Range"""
         _ranges: UnicodeRangeList = 
             (0x0900, 0x097F),
             (0xA8E0, 0xA8FF)
         
 
-    # fmt: on
+    BMP = BasicMultilingualPlane
 
+    # add language identifiers using language Unicode
+    العربية = Arabic
+    中文 = Chinese
+    кириллица = Cyrillic
+    Ελληνικά = Greek
+    עִברִית = Hebrew
+    日本語 = Japanese
+    한국어 = Korean
+    ไทย = Thai
+    देवनागरी = Devanagari
 
-pyparsing_unicode.Japanese._ranges = (
-    pyparsing_unicode.Japanese.Kanji._ranges
-    + pyparsing_unicode.Japanese.Hiragana._ranges
-    + pyparsing_unicode.Japanese.Katakana._ranges
-)
-
-pyparsing_unicode.BMP = pyparsing_unicode.BasicMultilingualPlane
-
-# add language identifiers using language Unicode
-pyparsing_unicode.العربية = pyparsing_unicode.Arabic
-pyparsing_unicode.中文 = pyparsing_unicode.Chinese
-pyparsing_unicode.кириллица = pyparsing_unicode.Cyrillic
-pyparsing_unicode.Ελληνικά = pyparsing_unicode.Greek
-pyparsing_unicode.עִברִית = pyparsing_unicode.Hebrew
-pyparsing_unicode.日本語 = pyparsing_unicode.Japanese
-pyparsing_unicode.Japanese.漢字 = pyparsing_unicode.Japanese.Kanji
-pyparsing_unicode.Japanese.カタカナ = pyparsing_unicode.Japanese.Katakana
-pyparsing_unicode.Japanese.ひらがな = pyparsing_unicode.Japanese.Hiragana
-pyparsing_unicode.한국어 = pyparsing_unicode.Korean
-pyparsing_unicode.ไทย = pyparsing_unicode.Thai
-pyparsing_unicode.देवनागरी = pyparsing_unicode.Devanagari
+    # fmt: on

_service:tar_scm:pyparsing-3.0.9.tar.gz/pyparsing/util.py -> _service:tar_scm:pyparsing-3.1.1.tar.gz/pyparsing/util.py Changed

@@ -1,12 +1,14 @@
 # util.py
+import inspect
 import warnings
 import types
 import collections
 import itertools
-from functools import lru_cache
-from typing import List, Union, Iterable
+from functools import lru_cache, wraps
+from typing import Callable, List, Union, Iterable, TypeVar, cast
 
 _bslash = chr(92)
+C = TypeVar("C", bound=Callable)
 
 
 class __config_flags:
@@ -20,18 +22,15 @@
     def _set(cls, dname, value):
         if dname in cls._fixed_names:
             warnings.warn(
-                "{}.{} {} is {} and cannot be overridden".format(
-                    cls.__name__,
-                    dname,
-                    cls._type_desc,
-                    str(getattr(cls, dname)).upper(),
-                )
+                f"{cls.__name__}.{dname} {cls._type_desc} is {str(getattr(cls, dname)).upper()}"
+                f" and cannot be overridden",
+                stacklevel=3,
             )
             return
         if dname in cls._all_names:
             setattr(cls, dname, value)
         else:
-            raise ValueError("no such {} {!r}".format(cls._type_desc, dname))
+            raise ValueError(f"no such {cls._type_desc} {dname!r}")
 
     enable = classmethod(lambda cls, name: cls._set(name, True))
     disable = classmethod(lambda cls, name: cls._set(name, False))
@@ -45,7 +44,7 @@
 
     Note: the default parsing behavior is to expand tabs in the input string
     before starting the parsing process.  See
-    :class:`ParserElement.parseString` for more
+    :class:`ParserElement.parse_string` for more
     information on parsing strings containing ``<TAB>`` s, and suggested
     methods to maintain a consistent view of the parsed string, the parse
     location, and line and column positions within the parsed string.
@@ -60,7 +59,7 @@
     The first line is number 1.
 
     Note - the default parsing behavior is to expand tabs in the input string
-    before starting the parsing process.  See :class:`ParserElement.parseString`
+    before starting the parsing process.  See :class:`ParserElement.parse_string`
     for more information on parsing strings containing ``<TAB>`` s, and
     suggested methods to maintain a consistent view of the parsed string, the
     parse location, and line and column positions within the parsed string.
@@ -102,19 +101,24 @@
 class _FifoCache:
     def __init__(self, size):
         self.not_in_cache = not_in_cache = object()
-        cache = collections.OrderedDict()
+        cache = {}
+        keyring = object() * size
         cache_get = cache.get
+        cache_pop = cache.pop
+        keyiter = itertools.cycle(range(size))
 
         def get(_, key):
             return cache_get(key, not_in_cache)
 
         def set_(_, key, value):
             cachekey = value
-            while len(cache) > size:
-                cache.popitem(last=False)
+            i = next(keyiter)
+            cache_pop(keyringi, None)
+            keyringi = key
 
         def clear(_):
             cache.clear()
+            keyring: = object() * size
 
         self.size = size
         self.get = types.MethodType(get, self)
@@ -189,9 +193,9 @@
             is_consecutive.value = next(is_consecutive.counter)
         return is_consecutive.value
 
-    is_consecutive.prev = 0
-    is_consecutive.counter = itertools.count()
-    is_consecutive.value = -1
+    is_consecutive.prev = 0  # type: ignore attr-defined
+    is_consecutive.counter = itertools.count()  # type: ignore attr-defined
+    is_consecutive.value = -1  # type: ignore attr-defined
 
     def escape_re_range_char(c):
         return "\\" + c if c in r"\^-" else c
@@ -215,9 +219,7 @@
             else:
                 sep = "" if ord(last) == ord(first) + 1 else "-"
                 ret.append(
-                    "{}{}{}".format(
-                        escape_re_range_char(first), sep, escape_re_range_char(last)
-                    )
+                    f"{escape_re_range_char(first)}{sep}{escape_re_range_char(last)}"
                 )
     else:
         ret = escape_re_range_char(c) for c in s
@@ -233,3 +235,50 @@
         else:
             ret.append(i)
     return ret
+
+
+def _make_synonym_function(compat_name: str, fn: C) -> C:
+    # In a future version, uncomment the code in the internal _inner() functions
+    # to begin emitting DeprecationWarnings.
+
+    # Unwrap staticmethod/classmethod
+    fn = getattr(fn, "__func__", fn)
+
+    # (Presence of 'self' arg in signature is used by explain_exception() methods, so we take
+    # some extra steps to add it if present in decorated function.)
+    if "self" == list(inspect.signature(fn).parameters)0:
+
+        @wraps(fn)
+        def _inner(self, *args, **kwargs):
+            # warnings.warn(
+            #     f"Deprecated - use {fn.__name__}", DeprecationWarning, stacklevel=3
+            # )
+            return fn(self, *args, **kwargs)
+
+    else:
+
+        @wraps(fn)
+        def _inner(*args, **kwargs):
+            # warnings.warn(
+            #     f"Deprecated - use {fn.__name__}", DeprecationWarning, stacklevel=3
+            # )
+            return fn(*args, **kwargs)
+
+    _inner.__doc__ = f"""Deprecated - use :class:`{fn.__name__}`"""
+    _inner.__name__ = compat_name
+    _inner.__annotations__ = fn.__annotations__
+    if isinstance(fn, types.FunctionType):
+        _inner.__kwdefaults__ = fn.__kwdefaults__
+    elif isinstance(fn, type) and hasattr(fn, "__init__"):
+        _inner.__kwdefaults__ = fn.__init__.__kwdefaults__
+    else:
+        _inner.__kwdefaults__ = None
+    _inner.__qualname__ = fn.__qualname__
+    return cast(C, _inner)
+
+
+def replaced_by_pep8(fn: C) -> CallableCallable, C:
+    """
+    Decorator for pre-PEP8 compatibility synonyms, to link them to the new function.
+    """
+    return lambda other: _make_synonym_function(other.__name__, fn)

_service:tar_scm:pyparsing-3.0.9.tar.gz/pyproject.toml -> _service:tar_scm:pyparsing-3.1.1.tar.gz/pyproject.toml Changed

_service:tar_scm:pyparsing-3.0.9.tar.gz/tests/README.md -> _service:tar_scm:pyparsing-3.1.1.tar.gz/tests/README.md Changed

_service:tar_scm:pyparsing-3.1.1.tar.gz/tests/diag_embed.html Added

@@ -0,0 +1,61 @@
+
+    
+        <style>
+            .railroad-heading {
+                font-family: monospace;
+            }
+        </style>
+    
+
+
+
+    <div class="railroad-group">
+        <h1 class="railroad-heading"></h1>
+        <div class="railroad-description"></div>
+        <div class="railroad-svg">
+            <svg class="railroad-diagram" height="94" viewBox="0 0 529.5 94" width="529.5" xmlns="http://www.w3.org/2000/svg">
+<g transform="translate(.5 .5)">
+<style>/* <!CDATA */
+	svg.railroad-diagram {
+		background-color:hsl(30,20%,95%);
+	}
+	svg.railroad-diagram path {
+		stroke-width:3;
+		stroke:black;
+		fill:rgba(0,0,0,0);
+	}
+	svg.railroad-diagram text {
+		font:bold 14px monospace;
+		text-anchor:middle;
+	}
+	svg.railroad-diagram text.label{
+		text-anchor:start;
+	}
+	svg.railroad-diagram text.comment{
+		font:italic 12px monospace;
+	}
+	svg.railroad-diagram rect{
+		stroke-width:3;
+		stroke:black;
+		fill:hsl(120,100%,90%);
+	}
+	svg.railroad-diagram rect.group-box {
+		stroke: gray;
+		stroke-dasharray: 10 5;
+		fill: none;
+	}
+
+/* > */
+</style><g>
+<path d="M20 45v20m10 -20v20m-10 -10h20"></path></g><path d="M40 55h10"></path><g>
+<path d="M50 55h0.0"></path><path d="M479.5 55h0.0"></path><rect class="group-box" height="38" rx="10" ry="10" width="429.5" x="50.0" y="36"></rect><g>
+<path d="M50.0 55h10.0"></path><path d="M469.5 55h10.0"></path><g class="terminal ">
+<path d="M60.0 55h0.0"></path><path d="M139.5 55h0.0"></path><rect height="22" rx="10" ry="10" width="79.5" x="60.0" y="44"></rect><text x="99.75" y="59">W:(0-9)</text></g><path d="M139.5 55h10"></path><path d="M149.5 55h10"></path><g class="terminal ">
+<path d="M159.5 55h0.0"></path><path d="M205.0 55h0.0"></path><rect height="22" rx="10" ry="10" width="45.5" x="159.5" y="44"></rect><text x="182.25" y="59">':'</text></g><path d="M205.0 55h10"></path><path d="M215.0 55h10"></path><g class="terminal ">
+<path d="M225.0 55h0.0"></path><path d="M304.5 55h0.0"></path><rect height="22" rx="10" ry="10" width="79.5" x="225.0" y="44"></rect><text x="264.75" y="59">W:(0-9)</text></g><path d="M304.5 55h10"></path><path d="M314.5 55h10"></path><g class="terminal ">
+<path d="M324.5 55h0.0"></path><path d="M370.0 55h0.0"></path><rect height="22" rx="10" ry="10" width="45.5" x="324.5" y="44"></rect><text x="347.25" y="59">':'</text></g><path d="M370.0 55h10"></path><path d="M380.0 55h10"></path><g class="terminal ">
+<path d="M390.0 55h0.0"></path><path d="M469.5 55h0.0"></path><rect height="22" rx="10" ry="10" width="79.5" x="390.0" y="44"></rect><text x="429.75" y="59">W:(0-9)</text></g></g><g class="non-terminal ">
+<path d="M50.0 28h0.0"></path><path d="M123.0 28h0.0"></path><text class="comment" x="86.5" y="33">&#91;combine&#93;</text></g></g><path d="M479.5 55h10"></path><path d="M 489.5 55 h 20 m -10 -10 v 20 m 10 -20 v 20"></path></g></svg>
+        </div>
+    </div>
+

_service:tar_scm:pyparsing-3.1.1.tar.gz/tests/diag_no_embed.html Added

@@ -0,0 +1,71 @@
+
+<!DOCTYPE html>
+<html>
+<head>
+
+    
+        <style>
+            .railroad-heading {
+                font-family: monospace;
+            }
+        </style>
+    
+
+</head>
+<body>
+
+
+
+    <div class="railroad-group">
+        <h1 class="railroad-heading"></h1>
+        <div class="railroad-description"></div>
+        <div class="railroad-svg">
+            <svg class="railroad-diagram" height="94" viewBox="0 0 529.5 94" width="529.5" xmlns="http://www.w3.org/2000/svg">
+<g transform="translate(.5 .5)">
+<style>/* <!CDATA */
+	svg.railroad-diagram {
+		background-color:hsl(30,20%,95%);
+	}
+	svg.railroad-diagram path {
+		stroke-width:3;
+		stroke:black;
+		fill:rgba(0,0,0,0);
+	}
+	svg.railroad-diagram text {
+		font:bold 14px monospace;
+		text-anchor:middle;
+	}
+	svg.railroad-diagram text.label{
+		text-anchor:start;
+	}
+	svg.railroad-diagram text.comment{
+		font:italic 12px monospace;
+	}
+	svg.railroad-diagram rect{
+		stroke-width:3;
+		stroke:black;
+		fill:hsl(120,100%,90%);
+	}
+	svg.railroad-diagram rect.group-box {
+		stroke: gray;
+		stroke-dasharray: 10 5;
+		fill: none;
+	}
+
+/* > */
+</style><g>
+<path d="M20 45v20m10 -20v20m-10 -10h20"></path></g><path d="M40 55h10"></path><g>
+<path d="M50 55h0.0"></path><path d="M479.5 55h0.0"></path><rect class="group-box" height="38" rx="10" ry="10" width="429.5" x="50.0" y="36"></rect><g>
+<path d="M50.0 55h10.0"></path><path d="M469.5 55h10.0"></path><g class="terminal ">
+<path d="M60.0 55h0.0"></path><path d="M139.5 55h0.0"></path><rect height="22" rx="10" ry="10" width="79.5" x="60.0" y="44"></rect><text x="99.75" y="59">W:(0-9)</text></g><path d="M139.5 55h10"></path><path d="M149.5 55h10"></path><g class="terminal ">
+<path d="M159.5 55h0.0"></path><path d="M205.0 55h0.0"></path><rect height="22" rx="10" ry="10" width="45.5" x="159.5" y="44"></rect><text x="182.25" y="59">':'</text></g><path d="M205.0 55h10"></path><path d="M215.0 55h10"></path><g class="terminal ">
+<path d="M225.0 55h0.0"></path><path d="M304.5 55h0.0"></path><rect height="22" rx="10" ry="10" width="79.5" x="225.0" y="44"></rect><text x="264.75" y="59">W:(0-9)</text></g><path d="M304.5 55h10"></path><path d="M314.5 55h10"></path><g class="terminal ">
+<path d="M324.5 55h0.0"></path><path d="M370.0 55h0.0"></path><rect height="22" rx="10" ry="10" width="45.5" x="324.5" y="44"></rect><text x="347.25" y="59">':'</text></g><path d="M370.0 55h10"></path><path d="M380.0 55h10"></path><g class="terminal ">
+<path d="M390.0 55h0.0"></path><path d="M469.5 55h0.0"></path><rect height="22" rx="10" ry="10" width="79.5" x="390.0" y="44"></rect><text x="429.75" y="59">W:(0-9)</text></g></g><g class="non-terminal ">
+<path d="M50.0 28h0.0"></path><path d="M123.0 28h0.0"></path><text class="comment" x="86.5" y="33">&#91;combine&#93;</text></g></g><path d="M479.5 55h10"></path><path d="M 489.5 55 h 20 m -10 -10 v 20 m 10 -20 v 20"></path></g></svg>
+        </div>
+    </div>
+
+
+</body>
+</html>

_service:tar_scm:pyparsing-3.1.1.tar.gz/tests/mypy-ignore-cases/forward_methods.py Added

_service:tar_scm:pyparsing-3.0.9.tar.gz/tests/test_diagram.py -> _service:tar_scm:pyparsing-3.1.1.tar.gz/tests/test_diagram.py Changed

@@ -1,4 +1,6 @@
 import unittest
+from io import StringIO
+from pathlib import Path
 from typing import List
 
 from examples.jsonParser import jsonObject
@@ -11,22 +13,56 @@
 import os
 import sys
 
+print(f"Running {__file__}")
+print(sys.version_info)
+
+curdir = Path(__file__).parent
+
+
+def is_run_with_coverage():
+    """Check whether test is run with coverage.
+    From https://stackoverflow.com/a/69812849/165216
+    """
+    gettrace = getattr(sys, "gettrace", None)
+
+    if gettrace is None:
+        return False
+    else:
+        gettrace_result = gettrace()
+
+    try:
+        from coverage.pytracer import PyTracer
+        from coverage.tracer import CTracer
+
+        if isinstance(gettrace_result, (CTracer, PyTracer)):
+            return True
+    except ImportError:
+        pass
+
+    return False
 
-class TestRailroadDiagrams(unittest.TestCase):
-    def railroad_debug(self) -> bool:
-        """
-        Returns True if we're in debug mode (determined by either setting
-        environment var, or running in a debugger which sets sys.settrace)
-        """
-        return os.environ.get("RAILROAD_DEBUG", False) or sys.gettrace()
 
+def running_in_debug() -> bool:
+    """
+    Returns True if we're in debug mode (determined by either setting
+    environment var, or running in a debugger which sets sys.settrace)
+    """
+    return (
+        os.environ.get("RAILROAD_DEBUG", False)
+        or sys.gettrace()
+        and not is_run_with_coverage()
+    )
+
+
+class TestRailroadDiagrams(unittest.TestCase):
     def get_temp(self):
         """
         Returns an appropriate temporary file for writing a railroad diagram
         """
+        delete_on_close = not running_in_debug()
         return tempfile.NamedTemporaryFile(
             dir=".",
-            delete=not self.railroad_debug(),
+            delete=delete_on_close,
             mode="w",
             encoding="utf-8",
             suffix=".html",
@@ -42,34 +78,39 @@
             railroad = to_railroad(expr, show_results_names=show_results_names)
             temp.write(railroad_to_html(railroad))
 
-        if self.railroad_debug():
+        if running_in_debug():
             print(f"{label}: {temp.name}")
 
         return railroad
 
-    def test_bool_expr(self):
-        railroad = self.generate_railroad(boolExpr, "boolExpr")
-        assert len(railroad) == 5
-        railroad = self.generate_railroad(boolExpr, "boolExpr", show_results_names=True)
-        assert len(railroad) == 5
-
-    def test_json(self):
-        railroad = self.generate_railroad(jsonObject, "jsonObject")
-        assert len(railroad) == 9
-        railroad = self.generate_railroad(jsonObject, "jsonObject", show_results_names=True)
-        assert len(railroad) == 9
-
-    def test_sql(self):
-        railroad = self.generate_railroad(simpleSQL, "simpleSQL")
-        assert len(railroad) == 18
-        railroad = self.generate_railroad(simpleSQL, "simpleSQL", show_results_names=True)
-        assert len(railroad) == 18
-
-    def test_calendars(self):
-        railroad = self.generate_railroad(calendars, "calendars")
-        assert len(railroad) == 13
-        railroad = self.generate_railroad(calendars, "calendars", show_results_names=True)
-        assert len(railroad) == 13
+    def test_example_rr_diags(self):
+        subtests = 
+            (jsonObject, "jsonObject", 8),
+            (boolExpr, "boolExpr", 5),
+            (simpleSQL, "simpleSQL", 20),
+            (calendars, "calendars", 13),
+        
+        for example_expr, label, expected_rr_len in subtests:
+            with self.subTest(f"{label}: test rr diag without results names"):
+                railroad = self.generate_railroad(example_expr, example_expr)
+                if len(railroad) != expected_rr_len:
+                    diag_html = railroad_to_html(railroad)
+                    for line in diag_html.splitlines():
+                        if 'h1 class="railroad-heading"' in line:
+                            print(line)
+                assert (
+                    len(railroad) == expected_rr_len
+                ), f"expected {expected_rr_len}, got {len(railroad)}"
+
+            with self.subTest(f"{label}: test rr diag with results names"):
+                railroad = self.generate_railroad(
+                    example_expr, example_expr, show_results_names=True
+                )
+                if len(railroad) != expected_rr_len:
+                    print(railroad_to_html(railroad))
+                assert (
+                    len(railroad) == expected_rr_len
+                ), f"expected {expected_rr_len}, got {len(railroad)}"
 
     def test_nested_forward_with_inner_and_outer_names(self):
         outer = pp.Forward().setName("outer")
@@ -78,7 +119,9 @@
 
         railroad = self.generate_railroad(outer, "inner_outer_names")
         assert len(railroad) == 2
-        railroad = self.generate_railroad(outer, "inner_outer_names", show_results_names=True)
+        railroad = self.generate_railroad(
+            outer, "inner_outer_names", show_results_names=True
+        )
         assert len(railroad) == 2
 
     def test_nested_forward_with_inner_name_only(self):
@@ -102,7 +145,9 @@
         ).setName("int-word-uuid in any order")
         railroad = self.generate_railroad(grammar, "each_expression")
         assert len(railroad) == 2
-        railroad = self.generate_railroad(grammar, "each_expression", show_results_names=True)
+        railroad = self.generate_railroad(
+            grammar, "each_expression", show_results_names=True
+        )
         assert len(railroad) == 2
 
     def test_none_name(self):
@@ -122,9 +167,145 @@
     def test_complete_combine_element(self):
         ints = pp.Word(pp.nums)
         grammar = pp.Combine(
-            ints('hours') + pp.Literal(":") + ints('minutes') + pp.Literal(":") + ints('seconds')
+            ints("hours")
+            + pp.Literal(":")
+            + ints("minutes")
+            + pp.Literal(":")
+            + ints("seconds")
         )
         railroad = to_railroad(grammar)
         assert len(railroad) == 1
         railroad = to_railroad(grammar, show_results_names=True)
         assert len(railroad) == 1
+
+    def test_create_diagram(self):
+        ints = pp.Word(pp.nums)
+        grammar = pp.Combine(
+            ints("hours")
+            + pp.Literal(":")
+            + ints("minutes")
+            + pp.Literal(":")
+            + ints("seconds")
+        )
+
+        diag_strio = StringIO()
+        grammar.create_diagram(output_html=diag_strio)
+        diag_str = diag_strio.getvalue().lower()
+        tags = "<html> </html> <head> </head> <body> </body>".split()
+        assert all(tag in diag_str for tag in tags)
+
+    def test_create_diagram_embed(self):
+        ints = pp.Word(pp.nums)
+        grammar = pp.Combine(
+            ints("hours")
+            + pp.Literal(":")
+            + ints("minutes")
+            + pp.Literal(":")
+            + ints("seconds")
+        )
+
+        diag_strio = StringIO()
+        grammar.create_diagram(output_html=diag_strio, embed=True)
+        diag_str = diag_strio.getvalue().lower()
+        tags = "<html> </html> <head> </head> <body> </body>".split()
+        assert not any(tag in diag_str for tag in tags)
+
+    def test_kwargs_pass_thru_create_diagram(self):
+        from io import StringIO
+        # Creates a simple diagram with a blue body and
+        # various other railroad features colored with
+        # a complete disregard for taste
+
+        # Very simple grammar for demo purposes
+        salutation = pp.Word(pp.alphas).set_name("salutation")
+        subject = pp.rest_of_line.set_name("subject")
+        parse_grammar = salutation + subject
+
+        # This is used to turn off the railroads
+        # definition of DEFAULT_STYLE.
+        # If this is set to 'None' the default style
+        # will be written as part of each diagram
+        # and will you will not be able to set the
+        # css style globally and the string 'expStyle'
+        # will have no effect.
+        # There is probably a PR to railroad_diagram to
+        # remove some cruft left in the SVG.
+        DEFAULT_STYLE = ""
+
+        # CSS Code to be placed into head of the html file
+        expStyle = """
+        <style type="text/css">
+
+        body {
+            background-color: blue;
+        }
+
+        .railroad-heading {
+            font-family: monospace;
+            color: bisque;
+        }
+
+        svg.railroad-diagram {
+            background-color: hsl(264,45%,85%);
+        }
+        svg.railroad-diagram path {
+            stroke-width: 3;
+            stroke: green;
+            fill: rgba(0,0,0,0);
+        }
+        svg.railroad-diagram text {
+            font: bold 14px monospace;
+            text-anchor: middle;
+            white-space: pre;
+        }
+        svg.railroad-diagram text.diagram-text {
+            font-size: 12px;
+        }
+        svg.railroad-diagram text.diagram-arrow {
+            font-size: 16px;
+        }
+        svg.railroad-diagram text.label {
+            text-anchor: start;
+        }
+        svg.railroad-diagram text.comment {
+            font: italic 12px monospace;
+        }
+        svg.railroad-diagram g.non-terminal text {
+            /*font-style: italic;*/
+        }
+        svg.railroad-diagram rect {
+            stroke-width: 3;
+            stroke: black;
+            fill: hsl(55, 72%, 69%);
+        }
+        svg.railroad-diagram rect.group-box {
+            stroke: rgb(33, 8, 225);
+            stroke-dasharray: 10 5;
+            fill: none;
+        }
+        svg.railroad-diagram path.diagram-text {
+            stroke-width: 3;
+            stroke: black;
+            fill: white;
+            cursor: help;
+        }
+        svg.railroad-diagram g.diagram-text:hover path.diagram-text {
+            fill: #eee;
+        }
+        </style>
+        """
+
+        # the 'css=DEFAULT_STYLE' or 'css=""' is needed to turn off railroad_diagrams styling
+        diag_html_capture = StringIO()
+        parse_grammar.create_diagram(
+            diag_html_capture,
+            vertical=6,
+            show_results_names=True,
+            css=DEFAULT_STYLE,
+            head=expStyle
+        )
+
+        self.assertIn(expStyle, diag_html_capture.getvalue())
+
+if __name__ == "__main__":
+    unittest.main()

_service:tar_scm:pyparsing-3.0.9.tar.gz/tests/test_examples.py -> _service:tar_scm:pyparsing-3.1.1.tar.gz/tests/test_examples.py Changed

@@ -4,11 +4,17 @@
 from importlib import import_module
 import unittest
 
+from pyparsing import testing as ppt
+
 
 class TestExamples(unittest.TestCase):
     def _run(self, name):
         mod = import_module("examples." + name)
-        getattr(mod, "main", lambda *args, **kwargs: None)()
+
+        # use pyparsing context to reset each test to clean
+        # pyparsing settings
+        with ppt.reset_pyparsing_context():
+            getattr(mod, "main", lambda *args, **kwargs: None)()
 
     def test_numerics(self):
         self._run("numerics")
@@ -33,3 +39,21 @@
 
     def test_select_parser(self):
         self._run("select_parser")
+
+    def test_booleansearchparser(self):
+        self._run("booleansearchparser")
+
+    def test_rosettacode(self):
+        self._run("rosettacode")
+
+    def test_excelExpr(self):
+        self._run("excel_expr")
+
+    def test_lucene_grammar(self):
+        self._run("lucene_grammar")
+
+    def test_range_check(self):
+        self._run("range_check")
+
+    def test_stackish(self):
+        self._run("stackish")

_service:tar_scm:pyparsing-3.0.9.tar.gz/tests/test_simple_unit.py -> _service:tar_scm:pyparsing-3.1.1.tar.gz/tests/test_simple_unit.py Changed

@@ -10,7 +10,7 @@
 import unittest
 import pyparsing as pp
 from collections import namedtuple
-from datetime import datetime
+from datetime import datetime, timezone
 
 ppt = pp.pyparsing_test
 TestParseResultsAsserts = ppt.TestParseResultsAsserts
@@ -47,9 +47,7 @@
             with self.subTest(test_spec=test_spec):
                 test_spec.expr.streamline()
                 print(
-                    "\n{} - {}({})".format(
-                        test_spec.desc, type(test_spec.expr).__name__, test_spec.expr
-                    )
+                    f"\n{test_spec.desc} - {type(test_spec.expr).__name__}({test_spec.expr})"
                 )
 
                 parsefn = getattr(test_spec.expr, test_spec.parse_fn)
@@ -405,18 +403,18 @@
         PpTestSpec(
             desc="Use two parse actions to convert numeric string, then convert to datetime",
             expr=pp.Word(pp.nums).add_parse_action(
-                lambda t: int(t0), lambda t: datetime.utcfromtimestamp(t0)
+                lambda t: int(t0), lambda t: datetime.fromtimestamp(t0, timezone.utc)
             ),
             text="1537415628",
-            expected_list=datetime(2018, 9, 20, 3, 53, 48),
+            expected_list=datetime(2018, 9, 20, 3, 53, 48, tzinfo=timezone.utc),
         ),
         PpTestSpec(
             desc="Use tokenMap for parse actions that operate on a single-length token",
             expr=pp.Word(pp.nums).add_parse_action(
-                pp.token_map(int), pp.token_map(datetime.utcfromtimestamp)
+                pp.token_map(int), pp.token_map(lambda t: datetime.fromtimestamp(t, timezone.utc))
             ),
             text="1537415628",
-            expected_list=datetime(2018, 9, 20, 3, 53, 48),
+            expected_list=datetime(2018, 9, 20, 3, 53, 48, tzinfo=timezone.utc),
         ),
         PpTestSpec(
             desc="Using a built-in function that takes a sequence of strs as a parse action",
@@ -506,7 +504,7 @@
         htmltag = TestTransformStringUsingParseActions.markup_convert_map
             t.markup_symbol
         
-        return "<{}>{}</{}>".format(htmltag, t.body, htmltag)
+        return f"<{htmltag}>{t.body}</{htmltag}>"
 
     tests = 
         PpTestSpec(

_service:tar_scm:pyparsing-3.0.9.tar.gz/tests/test_unit.py -> _service:tar_scm:pyparsing-3.1.1.tar.gz/tests/test_unit.py Changed

@@ -101,16 +101,24 @@
 
         if getattr(ar, "exception", None) is not None:
             print(
-                "Raised expected exception: {}: {}".format(
-                    type(ar.exception).__name__, str(ar.exception)
-                )
+                f"Raised expected exception: {type(ar.exception).__name__}: {ar.exception}"
             )
         else:
-            print(
-                "Expected {} exception not raised".format(
-                    expected_exception_type.__name__
-                )
-            )
+            print(f"Expected {expected_exception_type.__name__} exception not raised")
+        return ar
+
+    @contextlib.contextmanager
+    def assertWarns(self, expected_warning_type: Any, msg: Any = None):
+        """
+        Simple wrapper to print out the warnings raised after assertWarns
+        """
+        with super().assertWarns(expected_warning_type, msg=msg) as ar:
+            yield
+
+        if getattr(ar, "warning", None) is not None:
+            print(f"Raised expected warning: {type(ar.warning).__name__}: {ar.warning}")
+        else:
+            print(f"Expected {expected_warning_type.__name__} warning not raised")
         return ar
 
     @contextlib.contextmanager
@@ -121,9 +129,9 @@
                 yield
             except Exception as e:
                 if msg is None:
-                    msg = "unexpected warning {} raised".format(e)
+                    msg = f"unexpected warning {e} raised"
                 if isinstance(e, warning_type):
-                    self.fail("{}: {}".format(msg, e))
+                    self.fail(f"{msg}: {e}")
                 else:
                     raise
 
@@ -164,7 +172,7 @@
 
         all_success = True
         for args, expected in tests:
-            message = "{} should be {}".format(args, expected)
+            message = f"{args} should be {expected}"
             print(message, end=" -> ")
             actual = pp.core._should_enable_warnings(*args)
             print("PASS" if actual == expected else "FAIL")
@@ -237,9 +245,7 @@
         self.assertParseResultsEquals(result, "    ", "test", {"word": "test"})
 
     def testTransformString(self):
-        make_int_with_commas = ppc.integer().addParseAction(
-            lambda t: "{:,}".format(t0)
-        )
+        make_int_with_commas = ppc.integer().addParseAction(lambda t: f"{t0:,}")
         lower_case_words = pp.Word(pp.alphas.lower(), asKeyword=True) + pp.Optional(
             pp.White()
         )
@@ -389,7 +395,7 @@
             30 print 890
             """
 
-            parsed_program = program.parseString(test)
+            parsed_program = program.parseString(test, parseAll=True)
             print(parsed_program.dump())
             self.assertEqual(
                 3,
@@ -413,7 +419,7 @@
                 test_string = "\n".join(test_str * 3)
                 result = parser.parseString(test_string, parseAll=True)
                 print(result.dump())
-                self.assertEqual(1, len(result), "failed {!r}".format(test_string))
+                self.assertEqual(1, len(result), f"failed {test_string!r}")
 
             pp.ParserElement.setDefaultWhitespaceChars(" \t")
 
@@ -422,7 +428,7 @@
                 test_string = "\n".join(test_str * 3)
                 result = parser.parseString(test_string, parseAll=True)
                 print(result.dump())
-                self.assertEqual(3, len(result), "failed {!r}".format(test_string))
+                self.assertEqual(3, len(result), f"failed {test_string!r}")
 
             pp.ParserElement.setDefaultWhitespaceChars(" \n\t")
 
@@ -431,7 +437,7 @@
                 test_string = "\n".join(test_str * 3)
                 result = parser.parseString(test_string, parseAll=True)
                 print(result.dump())
-                self.assertEqual(1, len(result), "failed {!r}".format(test_string))
+                self.assertEqual(1, len(result), f"failed {test_string!r}")
 
     def testParseFourFn(self):
         import examples.fourFn as fourFn
@@ -439,16 +445,16 @@
 
         def test(s, ans):
             fourFn.exprStack: = 
-            results = fourFn.BNF().parseString(s)
+            results = fourFn.BNF().parseString(s, parseAll=True)
             try:
                 resultValue = fourFn.evaluate_stack(fourFn.exprStack)
             except Exception:
-                self.assertIsNone(ans, "exception raised for expression {!r}".format(s))
+                self.assertIsNone(ans, f"exception raised for expression {s!r}")
             else:
                 self.assertEqual(
                     ans,
                     resultValue,
-                    "failed to evaluate {}, got {:f}".format(s, resultValue),
+                    f"failed to evaluate {s}, got {resultValue:f}",
                 )
                 print(s, "->", resultValue)
 
@@ -505,23 +511,21 @@
 
         def test(s, num_expected_toks, expected_errloc=-1):
             try:
-                sqlToks = flatten(simpleSQL.simpleSQL.parseString(s).asList())
+                sqlToks = flatten(
+                    simpleSQL.simpleSQL.parseString(s, parseAll=True).asList()
+                )
                 print(s, sqlToks, len(sqlToks))
                 self.assertEqual(
                     num_expected_toks,
                     len(sqlToks),
-                    "invalid parsed tokens, expected {}, found {} ({})".format(
-                        num_expected_toks, len(sqlToks), sqlToks
-                    ),
+                    f"invalid parsed tokens, expected {num_expected_toks}, found {len(sqlToks)} ({sqlToks})",
                 )
             except ParseException as e:
                 if expected_errloc >= 0:
                     self.assertEqual(
                         expected_errloc,
                         e.loc,
-                        "expected error at {}, found at {}".format(
-                            expected_errloc, e.loc
-                        ),
+                        f"expected error at {expected_errloc}, found at {e.loc}",
                     )
 
         test("SELECT * from XYZZY, ABC", 6)
@@ -551,7 +555,7 @@
             print("Parsing", fnam, "...", end=" ")
             with open(fnam) as infile:
                 iniFileLines = "\n".join(infile.read().splitlines())
-            iniData = configParse.inifile_BNF().parseString(iniFileLines)
+            iniData = configParse.inifile_BNF().parseString(iniFileLines, parseAll=True)
             print(len(flatten(iniData.asList())))
             print(list(iniData.keys()))
             self.assertEqual(
@@ -567,9 +571,7 @@
                 self.assertEqual(
                     chkexpect,
                     var,
-                    "ParseConfigFileTest: failed to parse ini {!r} as expected {!r}, found {}".format(
-                        chkkey, chkexpect, var
-                    ),
+                    f"ParseConfigFileTest: failed to parse ini {chkkey!r} as expected {chkexpect!r}, found {var}",
                 )
             print("OK")
 
@@ -795,7 +797,7 @@
         
 
         for t, exp_result in zip((test1, test2, test3, test4, test5), expected):
-            result = jsonObject.parseString(t)
+            result = jsonObject.parseString(t, parseAll=True)
             self.assertEqual(exp_result, result0)
 
     def testParseCommaSeparatedValues(self):
@@ -821,7 +823,7 @@
         
         for line, tests in zip(testData, testVals):
             print("Parsing: %r ->" % line, end=" ")
-            results = ppc.comma_separated_list.parseString(line)
+            results = ppc.comma_separated_list.parseString(line, parseAll=True)
             print(results)
             for t in tests:
                 if not (len(results) > t0 and resultst0 == t1):
@@ -866,13 +868,15 @@
         print("Parsing EBNF grammar with EBNF parser...")
         parsers = ebnf.parse(grammar, table)
         ebnf_parser = parsers"syntax"
+        ebnf_comment = pp.Literal("(*") + ... + "*)"
+        ebnf_parser.ignore(ebnf_comment)
         print("-", "\n- ".join(parsers.keys()))
         self.assertEqual(
             13, len(list(parsers.keys())), "failed to construct syntax grammar"
         )
 
         print("Parsing EBNF grammar with generated EBNF parser...")
-        parsed_chars = ebnf_parser.parseString(grammar)
+        parsed_chars = ebnf_parser.parseString(grammar, parseAll=True)
         parsed_char_len = len(parsed_chars)
 
         print(",\n".join(str(parsed_chars.asList()).split(",")))
@@ -889,7 +893,7 @@
             print(strng)
             try:
                 bnf = idlParse.CORBA_IDL_BNF()
-                tokens = bnf.parseString(strng)
+                tokens = bnf.parseString(strng, parseAll=True)
                 print("tokens = ")
                 tokens.pprint()
                 tokens = flatten(tokens.asList())
@@ -897,7 +901,7 @@
                 self.assertEqual(
                     numToks,
                     len(tokens),
-                    "error matching IDL string, {} -> {}".format(strng, str(tokens)),
+                    f"error matching IDL string, {strng} -> {str(tokens)}",
                 )
             except ParseException as err:
                 print(err.line)
@@ -906,9 +910,7 @@
                 self.assertEqual(
                     0,
                     numToks,
-                    "unexpected ParseException while parsing {}, {}".format(
-                        strng, str(err)
-                    ),
+                    f"unexpected ParseException while parsing {strng}, {str(err)}",
                 )
                 self.assertEqual(
                     expectedErrloc,
@@ -1013,7 +1015,6 @@
         pass
 
     def testScanString(self):
-
         testdata = """
             <table border="0" cellpadding="3" cellspacing="3" frame="" width="90%">
                 <tr align="left" valign="top">
@@ -1094,117 +1095,131 @@
             """
         print(testData)
 
-        sglStrings = 
-            (t0, b, e) for (t, b, e) in pp.sglQuotedString.scanString(testData)
-        
-        print(sglStrings)
-        self.assertTrue(
-            len(sglStrings) == 1
-            and (sglStrings01 == 17 and sglStrings02 == 47),
-            "single quoted string failure",
-        )
+        with self.subTest():
+            sglStrings = 
+                (t0, b, e) for (t, b, e) in pp.sglQuotedString.scanString(testData)
+            
+            print(sglStrings)
+            self.assertTrue(
+                len(sglStrings) == 1
+                and (sglStrings01 == 17 and sglStrings02 == 47),
+                "single quoted string failure",
+            )
 
-        dblStrings = 
-            (t0, b, e) for (t, b, e) in pp.dblQuotedString.scanString(testData)
-        
-        print(dblStrings)
-        self.assertTrue(
-            len(dblStrings) == 1
-            and (dblStrings01 == 154 and dblStrings02 == 184),
-            "double quoted string failure",
-        )
+        with self.subTest():
+            dblStrings = 
+                (t0, b, e) for (t, b, e) in pp.dblQuotedString.scanString(testData)
+            
+            print(dblStrings)
+            self.assertTrue(
+                len(dblStrings) == 1
+                and (dblStrings01 == 154 and dblStrings02 == 184),
+                "double quoted string failure",
+            )
 
-        allStrings = 
-            (t0, b, e) for (t, b, e) in pp.quotedString.scanString(testData)
-        
-        print(allStrings)
-        self.assertTrue(
-            len(allStrings) == 2
-            and (allStrings01 == 17 and allStrings02 == 47)
-            and (allStrings11 == 154 and allStrings12 == 184),
-            "quoted string failure",
-        )
+        with self.subTest():
+            allStrings = 
+                (t0, b, e) for (t, b, e) in pp.quotedString.scanString(testData)
+            
+            print(allStrings)
+            self.assertTrue(
+                len(allStrings) == 2
+                and (allStrings01 == 17 and allStrings02 == 47)
+                and (allStrings11 == 154 and allStrings12 == 184),
+                "quoted string failure",
+            )
 
         escapedQuoteTest = r"""
                 'This string has an escaped (\') quote character'
                 "This string has an escaped (\") quote character"
             """
 
-        sglStrings = 
-            (t0, b, e)
-            for (t, b, e) in pp.sglQuotedString.scanString(escapedQuoteTest)
-        
-        print(sglStrings)
-        self.assertTrue(
-            len(sglStrings) == 1
-            and (sglStrings01 == 17 and sglStrings02 == 66),
-            "single quoted string escaped quote failure (%s)" % str(sglStrings0),
-        )
+        with self.subTest():
+            sglStrings = 
+                (t0, b, e)
+                for (t, b, e) in pp.sglQuotedString.scanString(escapedQuoteTest)
+            
+            print(sglStrings)
+            self.assertTrue(
+                len(sglStrings) == 1
+                and (sglStrings01 == 17 and sglStrings02 == 66),
+                "single quoted string escaped quote failure (%s)" % str(sglStrings0),
+            )
 
-        dblStrings = 
-            (t0, b, e)
-            for (t, b, e) in pp.dblQuotedString.scanString(escapedQuoteTest)
-        
-        print(dblStrings)
-        self.assertTrue(
-            len(dblStrings) == 1
-            and (dblStrings01 == 83 and dblStrings02 == 132),
-            "double quoted string escaped quote failure (%s)" % str(dblStrings0),
-        )
+        with self.subTest():
+            dblStrings = 
+                (t0, b, e)
+                for (t, b, e) in pp.dblQuotedString.scanString(escapedQuoteTest)
+            
+            print(dblStrings)
+            self.assertTrue(
+                len(dblStrings) == 1
+                and (dblStrings01 == 83 and dblStrings02 == 132),
+                "double quoted string escaped quote failure (%s)" % str(dblStrings0),
+            )
 
-        allStrings = 
-            (t0, b, e) for (t, b, e) in pp.quotedString.scanString(escapedQuoteTest)
-        
-        print(allStrings)
-        self.assertTrue(
-            len(allStrings) == 2
-            and (
-                allStrings01 == 17
-                and allStrings02 == 66
-                and allStrings11 == 83
-                and allStrings12 == 132
-            ),
-            "quoted string escaped quote failure (%s)"
-            % (str(s0) for s in allStrings),
-        )
+        with self.subTest():
+            allStrings = 
+                (t0, b, e)
+                for (t, b, e) in pp.quotedString.scanString(escapedQuoteTest)
+            
+            print(allStrings)
+            self.assertTrue(
+                len(allStrings) == 2
+                and (
+                    allStrings01 == 17
+                    and allStrings02 == 66
+                    and allStrings11 == 83
+                    and allStrings12 == 132
+                ),
+                "quoted string escaped quote failure (%s)"
+                % (str(s0) for s in allStrings),
+            )
 
         dblQuoteTest = r"""
                 'This string has an doubled ('') quote character'
                 "This string has an doubled ("") quote character"
             """
-        sglStrings = 
-            (t0, b, e) for (t, b, e) in pp.sglQuotedString.scanString(dblQuoteTest)
-        
-        print(sglStrings)
-        self.assertTrue(
-            len(sglStrings) == 1
-            and (sglStrings01 == 17 and sglStrings02 == 66),
-            "single quoted string escaped quote failure (%s)" % str(sglStrings0),
-        )
-        dblStrings = 
-            (t0, b, e) for (t, b, e) in pp.dblQuotedString.scanString(dblQuoteTest)
-        
-        print(dblStrings)
-        self.assertTrue(
-            len(dblStrings) == 1
-            and (dblStrings01 == 83 and dblStrings02 == 132),
-            "double quoted string escaped quote failure (%s)" % str(dblStrings0),
-        )
-        allStrings = 
-            (t0, b, e) for (t, b, e) in pp.quotedString.scanString(dblQuoteTest)
-        
-        print(allStrings)
-        self.assertTrue(
-            len(allStrings) == 2
-            and (
-                allStrings01 == 17
-                and allStrings02 == 66
-                and allStrings11 == 83
-                and allStrings12 == 132
-            ),
-            "quoted string escaped quote failure (%s)"
-            % (str(s0) for s in allStrings),
-        )
+        with self.subTest():
+            sglStrings = 
+                (t0, b, e)
+                for (t, b, e) in pp.sglQuotedString.scanString(dblQuoteTest)
+            
+            print(sglStrings)
+            self.assertTrue(
+                len(sglStrings) == 1
+                and (sglStrings01 == 17 and sglStrings02 == 66),
+                "single quoted string escaped quote failure (%s)" % str(sglStrings0),
+            )
+
+        with self.subTest():
+            dblStrings = 
+                (t0, b, e)
+                for (t, b, e) in pp.dblQuotedString.scanString(dblQuoteTest)
+            
+            print(dblStrings)
+            self.assertTrue(
+                len(dblStrings) == 1
+                and (dblStrings01 == 83 and dblStrings02 == 132),
+                "double quoted string escaped quote failure (%s)" % str(dblStrings0),
+            )
+
+        with self.subTest():
+            allStrings = 
+                (t0, b, e) for (t, b, e) in pp.quotedString.scanString(dblQuoteTest)
+            
+            print(allStrings)
+            self.assertTrue(
+                len(allStrings) == 2
+                and (
+                    allStrings01 == 17
+                    and allStrings02 == 66
+                    and allStrings11 == 83
+                    and allStrings12 == 132
+                ),
+                "quoted string escaped quote failure (%s)"
+                % (str(s0) for s in allStrings),
+            )
 
         print(
             "testing catastrophic RE backtracking in implementation of dblQuotedString"
@@ -1217,17 +1232,130 @@
             (pp.QuotedString('"'), '"' + "\\xff" * 500),
             (pp.QuotedString("'"), "'" + "\\xff" * 500),
         :
-            expr.parseString(test_string + test_string0)
-            try:
-                expr.parseString(test_string)
-            except Exception:
-                continue
+            with self.subTest(expr=expr, test_string=test_string):
+                expr.parseString(test_string + test_string0, parseAll=True)
+                try:
+                    expr.parseString(test_string, parseAll=True)
+                except Exception:
+                    continue
 
         # test invalid endQuoteChar
-        with self.assertRaises(
-            ValueError, msg="issue raising error for invalid endQuoteChar"
-        ):
-            expr = pp.QuotedString('"', endQuoteChar=" ")
+        with self.subTest():
+            with self.assertRaises(
+                ValueError, msg="issue raising error for invalid endQuoteChar"
+            ):
+                expr = pp.QuotedString('"', endQuoteChar=" ")
+
+        with self.subTest():
+            source = """
+                '''
+                multiline quote with comment # this is a comment
+                '''
+                \"\"\"
+                multiline quote with comment # this is a comment
+                \"\"\"
+                "single line quote with comment # this is a comment"
+                'single line quote with comment # this is a comment'
+            """
+            stripped = (
+                pp.python_style_comment.ignore(pp.python_quoted_string)
+                .suppress()
+                .transform_string(source)
+            )
+            self.assertEqual(source, stripped)
+
+    def testQuotedStringUnquotesAndConvertWhitespaceEscapes(self):
+        # test for Issue #474
+        # fmt: off
+        backslash = chr(92)  # a single backslash
+        tab = "\t"
+        newline = "\n"
+        test_string_0 = f'"{backslash}{backslash}n"'              # r"\\n"
+        test_string_1 = f'"{backslash}t{backslash}{backslash}n"'  # r"\t\\n"
+        test_string_2 = f'"a{backslash}tb"'                       # r"a\tb"
+        test_string_3 = f'"{backslash}{backslash}{backslash}n"'   # r"\\\n"
+        T, F = True, False  # these make the test cases format nicely
+        for test_parameters in (
+                # Parameters are the arguments to creating a QuotedString
+                # and the expected parsed list of characters):
+                # - unquote_results
+                # - convert_whitespace_escapes
+                # - test string
+                # - expected parsed characters (broken out as separate
+                #   list items (all those doubled backslashes make it
+                #   difficult to interpret the output)
+                (T, T, test_string_0, backslash, "n"),
+                (T, F, test_string_0, backslash, "n"),
+                (F, F, test_string_0, '"', backslash, backslash, "n", '"'),
+                (T, T, test_string_1, tab, backslash, "n"),
+                (T, F, test_string_1, "t", backslash, "n"),
+                (F, F, test_string_1, '"', backslash, "t", backslash, backslash, "n", '"'),
+                (T, T, test_string_2, "a", tab, "b"),
+                (T, F, test_string_2, "a", "t", "b"),
+                (F, F, test_string_2, '"', "a", backslash, "t", "b", '"'),
+                (T, T, test_string_3, backslash, newline),
+                (T, F, test_string_3, backslash, "n"),
+                (F, F, test_string_3, '"', backslash, backslash, backslash, "n", '"'),
+        ):
+            unquote_results, convert_ws_escapes, test_string, expected_list = test_parameters
+            test_description = f"Testing with parameters {test_parameters}"
+            with self.subTest(msg=test_description):
+                print(test_description)
+                print(f"unquote_results: {unquote_results}"
+                      f"\nconvert_whitespace_escapes: {convert_ws_escapes}")
+                qs_expr = pp.QuotedString(
+                        quoteChar='"',
+                        escChar='\\',
+                        unquote_results=unquote_results,
+                        convert_whitespace_escapes=convert_ws_escapes
+                    )
+                result = qs_expr.parse_string(test_string)
+
+                # do this instead of assertParserAndCheckList to explicitly
+                # check and display the separate items in the list
+                print("Results:")
+                control_chars = {newline: "<NEWLINE>", backslash: "<BACKSLASH>", tab: "<TAB>"}
+                print(f"{', '.join(control_chars.get(c, repr(c)) for c in result0)}")
+                self.assertEqual(expected_list, list(result0))
+
+                print()
+        # fmt: on
+
+    def testPythonQuotedStrings(self):
+        # fmt: off
+        success1, _ = pp.python_quoted_string.run_tests(
+            '"""xyz"""',
+            '''"""xyz
+            """''',
+            '"""xyz "" """',
+            '''"""xyz ""
+            """''',
+            '"""xyz " """',
+            '''"""xyz "
+            """''',
+            r'''"""xyz \"""
+
+            """''',
+            "'''xyz'''",
+            """'''xyz
+            '''""",
+            "'''xyz '' '''",
+            """'''xyz ''
+            '''""",
+            "'''xyz ' '''",
+            """'''xyz '
+            '''""",
+            r"""'''xyz \'''
+            '''""",
+        )
+
+        print("\n\nFailure tests")
+        success2, _ = pp.python_quoted_string.run_tests(
+            '"xyz"""',
+        , failure_tests=True)
+
+        self.assertTrue(success1 and success2, "Python quoted string matching failure")
+        # fmt: on
 
     def testCaselessOneOf(self):
         caseless1 = pp.oneOf("d a b c aA B A C", caseless=True)
@@ -1245,14 +1373,14 @@
             caseless1str, caseless2str, "Caseless option properly sorted"
         )
 
-        res = caseless1....parseString("AAaaAaaA")
+        res = caseless1....parseString("AAaaAaaA", parseAll=True)
         print(res)
         self.assertEqual(4, len(res), "caseless1 oneOf failed")
         self.assertEqual(
             "aA" * 4, "".join(res), "caseless1 CaselessLiteral return failed"
         )
 
-        res = caseless2....parseString("AAaaAaaA")
+        res = caseless2....parseString("AAaaAaaA", parseAll=True)
         print(res)
         self.assertEqual(4, len(res), "caseless2 oneOf failed")
         self.assertEqual(
@@ -1335,7 +1463,9 @@
             + words("Tail")
         )
 
-        results = phrase.parseString("xavier yeti alpha beta charlie will beaver")
+        results = phrase.parseString(
+            "xavier yeti alpha beta charlie will beaver", parseAll=True
+        )
         print(results, results.Head, results.ABC, results.Tail)
         for key, ln in ("Head", 2), ("ABC", 3), ("Tail", 2):
             self.assertEqual(
@@ -1352,7 +1482,7 @@
             print("Test", s)
             print("Match Literal", end=" ")
             try:
-                print(lit.parseString(s))
+                print(lit.parseString(s, parseAll=False))
             except Exception:
                 print("failed")
                 if litShouldPass:
@@ -1363,7 +1493,7 @@
 
             print("Match Keyword", end=" ")
             try:
-                print(kw.parseString(s))
+                print(kw.parseString(s, parseAll=False))
             except Exception:
                 print("failed")
                 if kwShouldPass:
@@ -1393,7 +1523,7 @@
         name = pp.Word(pp.alphas).setName("word")("word*")
         list_of_num = pp.delimitedList(hexnum | num | name, ",")
 
-        tokens = list_of_num.parseString("1, 0x2, 3, 0x4, aaa")
+        tokens = list_of_num.parseString("1, 0x2, 3, 0x4, aaa", parseAll=True)
         print(tokens.dump())
         self.assertParseResultsEquals(
             tokens,
@@ -1420,7 +1550,7 @@
 
         test = """Q(x,y,z):-Bloo(x,"Mitsis",y),Foo(y,z,1243),y>28,x<12,x>3"""
 
-        queryRes = Query.parseString(test)
+        queryRes = Query.parseString(test, parseAll=True)
         print(queryRes.dump())
         self.assertParseResultsEquals(
             queryRes.pred,
@@ -1455,6 +1585,7 @@
             r"\0xa1-\0xbf\0xd7\0xf7",
             r"\0xc0-\0xd6\0xd8-\0xf6\0xf8-\0xff",
             r"\0xa1-\0xbf\0xd7\0xf7",
+            r"\\\\/\-\*\.\$\+\^\?()~ ",
         )
         expectedResults = (
             "ABCDEFGHIJKLMNOPQRSTUVWXYZ",
@@ -1482,6 +1613,7 @@
             "¡¢£¤¥¦§¨©ª«¬\xad®¯°±²³´µ¶·¸¹º»¼½¾¿×÷",
             pp.alphas8bit,
             pp.punc8bit,
+            r"\/-*.$+^?()~ ",
         )
         for test in zip(testCases, expectedResults):
             t, exp = test
@@ -1490,9 +1622,7 @@
             self.assertEqual(
                 exp,
                 res,
-                "srange error, srange({!r})->'{!r}', expected '{!r}'".format(
-                    t, res, exp
-                ),
+                f"srange error, srange({t!r})->'{res!r}', expected '{exp!r}'",
             )
 
     def testSkipToParserTests(self):
@@ -1503,7 +1633,7 @@
         )
 
         def test_parse(someText):
-            print(testExpr.parseString(someText))
+            print(testExpr.parseString(someText, parseAll=True))
 
         # This first test works, as the SkipTo expression is immediately following the ignore expression (cStyleComment)
         test_parse("some text /* comment with ; in */; working")
@@ -1527,7 +1657,7 @@
         data = pp.Literal("DATA")
         suffix = pp.Literal("suffix")
         expr = pp.SkipTo(data + suffix)("prefix") + data + suffix
-        result = expr.parseString(text)
+        result = expr.parseString(text, parseAll=True)
         self.assertTrue(
             isinstance(result.prefix, str),
             "SkipTo created with wrong saveAsList attribute",
@@ -1541,11 +1671,11 @@
         def test(expr, test_string, expected_list, expected_dict):
             if (expected_list, expected_dict) == (None, None):
                 with self.assertRaises(
-                    Exception, msg="{} failed to parse {!r}".format(expr, test_string)
+                    Exception, msg=f"{expr} failed to parse {test_string!r}"
                 ):
-                    expr.parseString(test_string)
+                    expr.parseString(test_string, parseAll=True)
             else:
-                result = expr.parseString(test_string)
+                result = expr.parseString(test_string, parseAll=True)
                 self.assertParseResultsEquals(
                     result, expected_list=expected_list, expected_dict=expected_dict
                 )
@@ -1654,13 +1784,42 @@
             {"_skipped": "red ", "456 "},
         )
 
-    def testEllipsisRepetition(self):
+    def testSkipToPreParseIgnoreExprs(self):
+        # added to verify fix to Issue #475
+        from pyparsing import Word, alphanums, python_style_comment
+
+        some_grammar = Word(alphanums) + ":=" + ... + ";"
+        some_grammar.ignore(python_style_comment)
+        try:
+            result = some_grammar.parse_string(
+                """\
+                var1 := 2 # 3; <== this semi-colon will match!
+                      + 1;
+                """,
+                parse_all=True,
+            )
+        except ParseException as pe:
+            print(pe.explain())
+            raise
+        else:
+            print(result.dump())
 
+    def testSkipToIgnoreExpr2(self):
+        a, star = pp.Literal.using_each("a*")
+        wrapper = a + ... + a
+        expr = star + pp.SkipTo(star, ignore=wrapper) + star
+
+        # pyparsing 3.0.9 -> '*', 'a_*_a', '*'
+        # pyparsing 3.1.0 -> '*', '', '*'
+        self.assertParseAndCheckList(expr, "*a_*_a*", "*", "a_*_a", "*")
+
+    def testEllipsisRepetition(self):
         word = pp.Word(pp.alphas).setName("word")
         num = pp.Word(pp.nums).setName("num")
 
         exprs = 
             word... + num,
+            word * ... + num,
             word0, ... + num,
             word1, ... + num,
             word2, ... + num,
@@ -1671,6 +1830,7 @@
         expected_res = 
             r"(abcd+ )*\d+",
             r"(abcd+ )*\d+",
+            r"(abcd+ )*\d+",
             r"(abcd+ )+\d+",
             r"(abcd+ ){2,}\d+",
             r"(abcd+ ){0,3}\d+",
@@ -1790,9 +1950,7 @@
             self.assertEqual(
                 expected,
                 quoteExpr.searchString(testString)00,
-                "failed to match {}, expected '{}', got '{}'".format(
-                    quoteExpr, expected, quoteExpr.searchString(testString)0
-                ),
+                f"failed to match {quoteExpr}, expected '{expected}', got '{quoteExpr.searchString(testString)0}'",
             )
             print()
 
@@ -1813,7 +1971,6 @@
             pp.QuotedString("", "\\")
 
     def testCustomQuotes2(self):
-
         qs = pp.QuotedString(quote_char=".", end_quote_char=".")
         print(qs.reString)
         self.assertParseAndCheckList(qs, ".....", "...")
@@ -1864,7 +2021,7 @@
             self.assertEqual(
                 expected,
                 found,
-                "Failed repeater for test: {}, matching {}".format(tst, str(seq)),
+                f"Failed repeater for test: {tst}, matching {str(seq)}",
             )
         print()
 
@@ -1884,7 +2041,7 @@
             self.assertEqual(
                 expected,
                 found,
-                "Failed repeater for test: {}, matching {}".format(tst, str(seq)),
+                f"Failed repeater for test: {tst}, matching {str(seq)}",
             )
 
         print()
@@ -1916,7 +2073,7 @@
             self.assertEqual(
                 expected,
                 found,
-                "Failed repeater for test: {}, matching {}".format(tst, str(seq)),
+                f"Failed repeater for test: {tst}, matching {str(seq)}",
             )
 
         print()
@@ -1936,7 +2093,7 @@
             self.assertEqual(
                 expected,
                 found,
-                "Failed repeater for test: {}, matching {}".format(tst, str(seq)),
+                f"Failed repeater for test: {tst}, matching {str(seq)}",
             )
 
     def testRepeater2(self):
@@ -1954,7 +2111,7 @@
 
         tst = "12"
         expected = "12"
-        result = seq.parseString(tst)
+        result = seq.parseString(tst, parseAll=True)
         print(result.dump())
 
         self.assertParseResultsEquals(result, expected_list=expected)
@@ -1974,7 +2131,7 @@
 
         tst = "aaaddd12aaaddd"
         expected = "aaa", "ddd", "12", "aaa", "ddd"
-        result = seq.parseString(tst)
+        result = seq.parseString(tst, parseAll=True)
         print(result.dump())
 
         self.assertParseResultsEquals(result, expected_list=expected)
@@ -2001,7 +2158,7 @@
 
         tst = "aaa ddd 12 aaa ddd"
         expected = "aaa", "ddd", "aaa", "ddd"
-        result = expr.parseString(tst)
+        result = expr.parseString(tst, parseAll=True)
         print(result.dump())
 
         self.assertParseResultsEquals(result, expected_list=expected)
@@ -2021,7 +2178,7 @@
 
         tst = "aaa 12 aaa"
         expected = tst.replace("12", "").split()
-        result = expr.parseString(tst)
+        result = expr.parseString(tst, parseAll=True)
         print(result.dump())
 
         self.assertParseResultsEquals(result, expected_list=expected)
@@ -2032,7 +2189,7 @@
         stream <<= pp.Optional(pp.Word(pp.alphas)) + pp.Optional(
             "(" + pp.Word(pp.nums) + ")" + stream
         )
-        expected = "".join(stream.parseString(testInput))
+        expected = "".join(stream.parseString(testInput, parseAll=True))
         print(expected)
 
         stream = pp.Forward()
@@ -2040,11 +2197,22 @@
             pp.Optional(pp.Word(pp.alphas))
             + pp.Optional("(" + pp.Word(pp.nums) + ")" + stream)
         )
-        testVal = stream.parseString(testInput)
+        testVal = stream.parseString(testInput, parseAll=True)
         print(testVal)
 
         self.assertParseResultsEquals(testVal, expected_list=expected)
 
+    def testCombineSetName(self):
+        ab = pp.Combine(
+            pp.Literal("a").set_name("AAA") | pp.Literal("b").set_name("BBB")
+        ).set_name("AB")
+        self.assertEqual("AB", ab.name)
+        self.assertEqual("AB", str(ab))
+        try:
+            ab.parse_string("C")
+        except ParseException as pe:
+            self.assertTrue(str(pe).startswith("Expected AB"))
+
     def testHTMLEntities(self):
         html_source = dedent(
             """\
@@ -2214,12 +2382,10 @@
         print("r =", boolVars"r")
         print()
         for t in test:
-            res = boolExpr.parseString(t)
+            res = boolExpr.parseString(t, parseAll=True)
             print(t, "\n", res0, "=", bool(res0), "\n")
             expected = eval(t, {}, boolVars)
-            self.assertEqual(
-                expected, bool(res0), "failed boolean eval test {}".format(t)
-            )
+            self.assertEqual(expected, bool(res0), f"failed boolean eval test {t}")
 
     def testInfixNotationMinimalParseActionCalls(self):
         count = 0
@@ -2257,7 +2423,9 @@
         test = "9"
         for t in test:
             count = 0
-            print("%r => %s (count=%d)" % (t, expr.parseString(t), count))
+            print(
+                "%r => %s (count=%d)" % (t, expr.parseString(t, parseAll=True), count)
+            )
             self.assertEqual(1, count, "count evaluated too many times!")
 
     def testInfixNotationWithParseActions(self):
@@ -2287,7 +2455,7 @@
         
         for test, expected in tests:
             print(test)
-            results = f.parseString(test)
+            results = f.parseString(test, parseAll=True)
             print(results)
             self.assertParseResultsEquals(results, expected_list=expected)
             print()
@@ -2362,14 +2530,12 @@
             if not t:
                 continue
 
-            parsed = expr.parseString(t)
+            parsed = expr.parseString(t, parseAll=True)
             eval_value = parsed0.eval()
             self.assertEqual(
                 eval(t),
                 eval_value,
-                "Error evaluating {!r}, expected {!r}, got {!r}".format(
-                    t, eval(t), eval_value
-                ),
+                f"Error evaluating {t!r}, expected {eval(t)!r}, got {eval_value!r}",
             )
 
     def testInfixNotationExceptions(self):
@@ -2519,7 +2685,9 @@
 
         # test 1
         body = pp.makeHTMLTags("BODY")0
-        result = body.parseString("<BODY BGCOLOR='#00FFBB' FGCOLOR=black>")
+        result = body.parseString(
+            "<BODY BGCOLOR='#00FFBB' FGCOLOR=black>", parseAll=True
+        )
         print(result.dump())
 
         for protocol in range(pickle.HIGHEST_PROTOCOL + 1):
@@ -2556,7 +2724,7 @@
 
         string = "Good morning, Miss Crabtree!"
 
-        result = greeting.parseString(string)
+        result = greeting.parseString(string, parseAll=True)
         self.assertParseResultsEquals(
             result,
             "Good", "morning", "Miss", "Crabtree", "!",
@@ -2581,26 +2749,24 @@
             self.assertEqual(
                 newresult.dump(),
                 result.dump(),
-                "failed to pickle/unpickle ParseResults: expected {!r}, got {!r}".format(
-                    result, newresult
-                ),
+                f"failed to pickle/unpickle ParseResults: expected {result!r}, got {newresult!r}",
             )
 
     def testParseResultsPickle3(self):
         import pickle
 
         # result with aslist=False
-        res_not_as_list = pp.Word("ABC").parseString("BABBAB")
+        res_not_as_list = pp.Word("ABC").parseString("BABBAB", parseAll=True)
 
         # result with aslist=True
-        res_as_list = pp.Group(pp.Word("ABC")).parseString("BABBAB")
+        res_as_list = pp.Group(pp.Word("ABC")).parseString("BABBAB", parseAll=True)
 
         # result with modal=True
-        res_modal = pp.Word("ABC")("name").parseString("BABBAB")
+        res_modal = pp.Word("ABC")("name").parseString("BABBAB", parseAll=True)
         # self.assertTrue(res_modal._modal)
 
         # result with modal=False
-        res_not_modal = pp.Word("ABC")("name*").parseString("BABBAB")
+        res_not_modal = pp.Word("ABC")("name*").parseString("BABBAB", parseAll=True)
         # self.assertFalse(res_not_modal._modal)
 
         for result in (res_as_list, res_not_as_list, res_modal, res_not_modal):
@@ -2617,9 +2783,7 @@
                 self.assertEqual(
                     newresult.dump(),
                     result.dump(),
-                    "failed to pickle/unpickle ParseResults: expected {!r}, got {!r}".format(
-                        result, newresult
-                    ),
+                    f"failed to pickle/unpickle ParseResults: expected {result!r}, got {newresult!r}",
                 )
 
     def testParseResultsInsertWithResultsNames(self):
@@ -2634,7 +2798,7 @@
             + pp.Group(wd...)("additional")
         )
 
-        result = expr.parseString(test_string)
+        result = expr.parseString(test_string, parseAll=True)
         print("Pre-insert")
         print(result.dump())
 
@@ -2666,7 +2830,9 @@
             joinString="/",
             adjacent=False,
         )
-        self.assertEqual("123/dice/rolledfirsttry", expr.parseString(test_string)0)
+        self.assertEqual(
+            "123/dice/rolledfirsttry", expr.parseString(test_string, parseAll=True)0
+        )
 
     def testParseResultsAcceptingACollectionTypeValue(self):
         # from Issue #276 - ParseResults parameterizes generic types if passed as the value of toklist parameter
@@ -2683,13 +2849,92 @@
     def testParseResultsReturningDunderAttribute(self):
         # from Issue #208
         parser = pp.Word(pp.alphas)("A")
-        result = parser.parseString("abc")
+        result = parser.parseString("abc", parseAll=True)
         print(result.dump())
         self.assertEqual("abc", result.A)
         self.assertEqual("", result.B)
         with self.assertRaises(AttributeError):
             result.__xyz__
 
+    def testParseResultsNamedResultWithEmptyString(self):
+        # from Issue #470
+
+        # Check which values can be returned from a parse action
+        for test_value, expected_in_result_by_name in 
+            ("x", True),
+            ("", True),
+            (True, True),
+            (False, True),
+            (1, True),
+            (0, True),
+            (None, True),
+            (b"", True),
+            (b"a", True),
+            (, False),
+            ((), False),
+        :
+            msg = (
+                f"value = {test_value!r},"
+                f" expected X {'not ' if not expected_in_result_by_name else ''}in result"
+            )
+            with self.subTest(msg):
+                print(msg)
+                grammar = (
+                    (pp.Suppress("a") + pp.ZeroOrMore("x"))
+                    .add_parse_action(lambda p: test_value)
+                    .set_results_name("X")
+                )
+                result = grammar.parse_string("a")
+                print(result.dump())
+                if expected_in_result_by_name:
+                    self.assertIn(
+                        "X",
+                        result,
+                        f"Expected X not found for parse action value {test_value!r}",
+                    )
+                    print(repr(result"X"))
+                else:
+                    self.assertNotIn(
+                        "X",
+                        result,
+                        f"Unexpected X found for parse action value {test_value!r}",
+                    )
+                    with self.assertRaises(KeyError):
+                        print(repr(result"X"))
+                print()
+
+        # Do not add a parse result.
+        msg = "value = <no parse action defined>, expected X in result"
+        with self.subTest(msg):
+            print(msg)
+            grammar = (pp.Suppress("a") + pp.ZeroOrMore("x")).set_results_name("X")
+            result = grammar.parse_string("a")
+            print(result.dump())
+            self.assertIn("X", result, f"Expected X not found with no parse action")
+            print()
+
+        # Test by directly creating a ParseResults
+        print("Create empty string value directly")
+        result = pp.ParseResults("", name="X")
+        print(result.dump())
+        self.assertIn(
+            "X",
+            result,
+            "failed to construct ParseResults with named value using empty string",
+        )
+        print(repr(result"X"))
+        print()
+
+        print("Create empty string value from a dict")
+        result = pp.ParseResults.from_dict({"X": ""})
+        print(result.dump())
+        self.assertIn(
+            "X",
+            result,
+            "failed to construct ParseResults with named value using from_dict",
+        )
+        print(repr(result"X"))
+
     def testMatchOnlyAtCol(self):
         """successfully use matchOnlyAtCol helper function"""
 
@@ -2697,7 +2942,7 @@
         expr.setParseAction(pp.matchOnlyAtCol(5))
         largerExpr = pp.ZeroOrMore(pp.Word("A")) + expr + pp.ZeroOrMore(pp.Word("A"))
 
-        res = largerExpr.parseString("A A 3 A")
+        res = largerExpr.parseString("A A 3 A", parseAll=True)
         print(res.dump())
 
     def testMatchOnlyAtColErr(self):
@@ -2708,89 +2953,96 @@
         largerExpr = pp.ZeroOrMore(pp.Word("A")) + expr + pp.ZeroOrMore(pp.Word("A"))
 
         with self.assertRaisesParseException():
-            largerExpr.parseString("A A 3 A")
+            largerExpr.parseString("A A 3 A", parseAll=True)
 
     def testParseResultsWithNamedTuple(self):
         expr = pp.Literal("A")("Achar")
         expr.setParseAction(pp.replaceWith(tuple("A", "Z")))
 
-        res = expr.parseString("A")
+        res = expr.parseString("A", parseAll=True)
         print(repr(res))
         print(res.Achar)
         self.assertParseResultsEquals(
             res,
             expected_dict={"Achar": ("A", "Z")},
-            msg="Failed accessing named results containing a tuple, "
-            "got {!r}".format(res.Achar),
+            msg=f"Failed accessing named results containing a tuple, got {res.Achar!r}",
         )
 
     def testParserElementAddOperatorWithOtherTypes(self):
         """test the overridden "+" operator with other data types"""
 
         # ParserElement + str
-        expr = pp.Word(pp.alphas)("first") + pp.Word(pp.alphas)("second") + "suf"
-        result = expr.parseString("spam eggs suf")
-        print(result)
+        with self.subTest():
+            expr = pp.Word(pp.alphas)("first") + pp.Word(pp.alphas)("second") + "suf"
+            result = expr.parseString("spam eggs suf", parseAll=True)
+            print(result)
 
-        expected_l = "spam", "eggs", "suf"
-        self.assertParseResultsEquals(
-            result, expected_l, msg="issue with ParserElement + str"
-        )
+            expected_l = "spam", "eggs", "suf"
+            self.assertParseResultsEquals(
+                result, expected_l, msg="issue with ParserElement + str"
+            )
 
         # str + ParserElement
-        expr = "pre" + pp.Word(pp.alphas)("first") + pp.Word(pp.alphas)("second")
-        result = expr.parseString("pre spam eggs")
-        print(result)
+        with self.subTest():
+            expr = "pre" + pp.Word(pp.alphas)("first") + pp.Word(pp.alphas)("second")
+            result = expr.parseString("pre spam eggs", parseAll=True)
+            print(result)
 
-        expected_l = "pre", "spam", "eggs"
-        self.assertParseResultsEquals(
-            result, expected_l, msg="issue with str + ParserElement"
-        )
+            expected_l = "pre", "spam", "eggs"
+            self.assertParseResultsEquals(
+                result, expected_l, msg="issue with str + ParserElement"
+            )
 
         # ParserElement + int
-        expr = None
-        with self.assertRaises(TypeError, msg="failed to warn ParserElement + int"):
-            expr = pp.Word(pp.alphas)("first") + pp.Word(pp.alphas)("second") + 12
-        self.assertEqual(expr, None)
+        with self.subTest():
+            expr = None
+            with self.assertRaises(TypeError, msg="failed to warn ParserElement + int"):
+                expr = pp.Word(pp.alphas)("first") + pp.Word(pp.alphas)("second") + 12
+            self.assertEqual(expr, None)
 
         # int + ParserElement
-        expr = None
-        with self.assertRaises(TypeError, msg="failed to warn int + ParserElement"):
-            expr = 12 + pp.Word(pp.alphas)("first") + pp.Word(pp.alphas)("second")
-        self.assertEqual(expr, None)
+        with self.subTest():
+            expr = None
+            with self.assertRaises(TypeError, msg="failed to warn int + ParserElement"):
+                expr = 12 + pp.Word(pp.alphas)("first") + pp.Word(pp.alphas)("second")
+            self.assertEqual(expr, None)
 
     def testParserElementSubOperatorWithOtherTypes(self):
         """test the overridden "-" operator with other data types"""
 
         # ParserElement - str
-        expr = pp.Word(pp.alphas)("first") + pp.Word(pp.alphas)("second") - "suf"
-        result = expr.parseString("spam eggs suf")
-        print(result)
-        expected = "spam", "eggs", "suf"
-        self.assertParseResultsEquals(
-            result, expected, msg="issue with ParserElement - str"
-        )
+        with self.subTest():
+            expr = pp.Word(pp.alphas)("first") + pp.Word(pp.alphas)("second") - "suf"
+            result = expr.parseString("spam eggs suf", parseAll=True)
+            print(result)
+            expected = "spam", "eggs", "suf"
+            self.assertParseResultsEquals(
+                result, expected, msg="issue with ParserElement - str"
+            )
 
         # str - ParserElement
-        expr = "pre" - pp.Word(pp.alphas)("first") + pp.Word(pp.alphas)("second")
-        result = expr.parseString("pre spam eggs")
-        print(result)
-        expected = "pre", "spam", "eggs"
-        self.assertParseResultsEquals(
-            result, expected, msg="issue with str - ParserElement"
-        )
+        with self.subTest():
+            expr = "pre" - pp.Word(pp.alphas)("first") + pp.Word(pp.alphas)("second")
+            result = expr.parseString("pre spam eggs", parseAll=True)
+            print(result)
+            expected = "pre", "spam", "eggs"
+            self.assertParseResultsEquals(
+                result, expected, msg="issue with str - ParserElement"
+            )
 
         # ParserElement - int
-        expr = None
-        with self.assertRaises(TypeError, msg="failed to warn ParserElement - int"):
-            expr = pp.Word(pp.alphas)("first") + pp.Word(pp.alphas)("second") - 12
-        self.assertEqual(expr, None)
+        with self.subTest():
+            expr = None
+            with self.assertRaises(TypeError, msg="failed to warn ParserElement - int"):
+                expr = pp.Word(pp.alphas)("first") + pp.Word(pp.alphas)("second") - 12
+            self.assertEqual(expr, None)
 
         # int - ParserElement
-        expr = None
-        with self.assertRaises(TypeError, msg="failed to warn int - ParserElement"):
-            expr = 12 - pp.Word(pp.alphas)("first") + pp.Word(pp.alphas)("second")
-        self.assertEqual(expr, None)
+        with self.subTest():
+            expr = None
+            with self.assertRaises(TypeError, msg="failed to warn int - ParserElement"):
+                expr = 12 - pp.Word(pp.alphas)("first") + pp.Word(pp.alphas)("second")
+            self.assertEqual(expr, None)
 
     def testParserElementMulOperatorWithTuples(self):
         """test ParserElement "*" with various tuples"""
@@ -2798,75 +3050,87 @@
         # ParserElement * (None, n)
         expr = pp.Word(pp.alphas)("first") + pp.Word(pp.nums)("second*") * (None, 3)
 
-        results1 = expr.parseString("spam")
-        print(results1.dump())
-        expected = "spam"
-        self.assertParseResultsEquals(
-            results1, expected, msg="issue with ParserElement * w/ optional matches"
-        )
+        with self.subTest():
+            results1 = expr.parseString("spam", parseAll=True)
+            print(results1.dump())
+            expected = "spam"
+            self.assertParseResultsEquals(
+                results1, expected, msg="issue with ParserElement * w/ optional matches"
+            )
 
-        results2 = expr.parseString("spam 12 23 34")
-        print(results2.dump())
-        expected = "spam", "12", "23", "34"
-        self.assertParseResultsEquals(
-            results2, expected, msg="issue with ParserElement * w/ optional matches"
-        )
+        with self.subTest():
+            results2 = expr.parseString("spam 12 23 34", parseAll=True)
+            print(results2.dump())
+            expected = "spam", "12", "23", "34"
+            self.assertParseResultsEquals(
+                results2, expected, msg="issue with ParserElement * w/ optional matches"
+            )
 
         # ParserElement * (1, 1)
-        expr = pp.Word(pp.alphas)("first") + pp.Word(pp.nums)("second*") * (1, 1)
-        results = expr.parseString("spam 45")
-        print(results.dump())
+        with self.subTest():
+            expr = pp.Word(pp.alphas)("first") + pp.Word(pp.nums)("second*") * (1, 1)
+            results = expr.parseString("spam 45", parseAll=True)
+            print(results.dump())
 
-        expected = "spam", "45"
-        self.assertParseResultsEquals(
-            results, expected, msg="issue with ParserElement * (1, 1)"
-        )
+            expected = "spam", "45"
+            self.assertParseResultsEquals(
+                results, expected, msg="issue with ParserElement * (1, 1)"
+            )
 
         # ParserElement * (1, 1+n)
-        expr = pp.Word(pp.alphas)("first") + pp.Word(pp.nums)("second*") * (1, 3)
+        with self.subTest():
+            expr = pp.Word(pp.alphas)("first") + pp.Word(pp.nums)("second*") * (1, 3)
 
-        results1 = expr.parseString("spam 100")
-        print(results1.dump())
-        expected = "spam", "100"
-        self.assertParseResultsEquals(
-            results1, expected, msg="issue with ParserElement * (1, 1+n)"
-        )
+            results1 = expr.parseString("spam 100", parseAll=True)
+            print(results1.dump())
+            expected = "spam", "100"
+            self.assertParseResultsEquals(
+                results1, expected, msg="issue with ParserElement * (1, 1+n)"
+            )
 
-        results2 = expr.parseString("spam 100 200 300")
-        print(results2.dump())
-        expected = "spam", "100", "200", "300"
-        self.assertParseResultsEquals(
-            results2, expected, msg="issue with ParserElement * (1, 1+n)"
-        )
+        with self.subTest():
+            results2 = expr.parseString("spam 100 200 300", parseAll=True)
+            print(results2.dump())
+            expected = "spam", "100", "200", "300"
+            self.assertParseResultsEquals(
+                results2, expected, msg="issue with ParserElement * (1, 1+n)"
+            )
 
         # ParserElement * (lesser, greater)
-        expr = pp.Word(pp.alphas)("first") + pp.Word(pp.nums)("second*") * (2, 3)
+        with self.subTest():
+            expr = pp.Word(pp.alphas)("first") + pp.Word(pp.nums)("second*") * (2, 3)
 
-        results1 = expr.parseString("spam 1 2")
-        print(results1.dump())
-        expected = "spam", "1", "2"
-        self.assertParseResultsEquals(
-            results1, expected, msg="issue with ParserElement * (lesser, greater)"
-        )
+            results1 = expr.parseString("spam 1 2", parseAll=True)
+            print(results1.dump())
+            expected = "spam", "1", "2"
+            self.assertParseResultsEquals(
+                results1, expected, msg="issue with ParserElement * (lesser, greater)"
+            )
 
-        results2 = expr.parseString("spam 1 2 3")
-        print(results2.dump())
-        expected = "spam", "1", "2", "3"
-        self.assertParseResultsEquals(
-            results2, expected, msg="issue with ParserElement * (lesser, greater)"
-        )
+        with self.subTest():
+            results2 = expr.parseString("spam 1 2 3", parseAll=True)
+            print(results2.dump())
+            expected = "spam", "1", "2", "3"
+            self.assertParseResultsEquals(
+                results2, expected, msg="issue with ParserElement * (lesser, greater)"
+            )
 
         # ParserElement * (greater, lesser)
-        with self.assertRaises(
-            ValueError, msg="ParserElement * (greater, lesser) should raise error"
-        ):
-            expr = pp.Word(pp.alphas)("first") + pp.Word(pp.nums)("second") * (3, 2)
+        with self.subTest():
+            with self.assertRaises(
+                ValueError, msg="ParserElement * (greater, lesser) should raise error"
+            ):
+                expr = pp.Word(pp.alphas)("first") + pp.Word(pp.nums)("second") * (3, 2)
 
         # ParserElement * (str, str)
-        with self.assertRaises(
-            TypeError, msg="ParserElement * (str, str) should raise error"
-        ):
-            expr = pp.Word(pp.alphas)("first") + pp.Word(pp.nums)("second") * ("2", "3")
+        with self.subTest():
+            with self.assertRaises(
+                TypeError, msg="ParserElement * (str, str) should raise error"
+            ):
+                expr = pp.Word(pp.alphas)("first") + pp.Word(pp.nums)("second") * (
+                    "2",
+                    "3",
+                )
 
     def testParserElementMulByZero(self):
         alpwd = pp.Word(pp.alphas)
@@ -2874,130 +3138,175 @@
 
         test_string = "abd def ghi jkl"
 
-        parser = alpwd * 2 + numwd * 0 + alpwd * 2
-        self.assertParseAndCheckList(
-            parser, test_string, expected_list=test_string.split()
-        )
+        with self.subTest():
+            parser = alpwd * 2 + numwd * 0 + alpwd * 2
+            self.assertParseAndCheckList(
+                parser, test_string, expected_list=test_string.split()
+            )
 
-        parser = alpwd * 2 + numwd * (0, 0) + alpwd * 2
-        self.assertParseAndCheckList(
-            parser, test_string, expected_list=test_string.split()
-        )
+        with self.subTest():
+            parser = alpwd * 2 + numwd * (0, 0) + alpwd * 2
+            self.assertParseAndCheckList(
+                parser, test_string, expected_list=test_string.split()
+            )
 
     def testParserElementMulOperatorWithOtherTypes(self):
         """test the overridden "*" operator with other data types"""
 
         # ParserElement * str
-        with self.assertRaises(TypeError, msg="ParserElement * str should raise error"):
-            expr = pp.Word(pp.alphas)("first") + pp.Word(pp.nums)("second") * "3"
+        with self.subTest():
+            with self.assertRaises(
+                TypeError, msg="ParserElement * str should raise error"
+            ):
+                expr = pp.Word(pp.alphas)("first") + pp.Word(pp.nums)("second") * "3"
 
         # str * ParserElement
-        with self.assertRaises(TypeError, msg="str * ParserElement should raise error"):
-            expr = pp.Word(pp.alphas)("first") + "3" * pp.Word(pp.nums)("second")
+        with self.subTest():
+            with self.assertRaises(
+                TypeError, msg="str * ParserElement should raise error"
+            ):
+                expr = pp.Word(pp.alphas)("first") + "3" * pp.Word(pp.nums)("second")
 
         # ParserElement * int
-        expr = pp.Word(pp.alphas)("first") + pp.Word(pp.nums)("second*") * 2
-        results = expr.parseString("spam 11 22")
+        with self.subTest():
+            expr = pp.Word(pp.alphas)("first") + pp.Word(pp.nums)("second*") * 2
+            results = expr.parseString("spam 11 22", parseAll=True)
 
-        print(results.dump())
-        expected = "spam", "11", "22"
-        self.assertParseResultsEquals(
-            results, expected, msg="issue with ParserElement * int"
-        )
+            print(results.dump())
+            expected = "spam", "11", "22"
+            self.assertParseResultsEquals(
+                results, expected, msg="issue with ParserElement * int"
+            )
 
         # int * ParserElement
-        expr = pp.Word(pp.alphas)("first") + 2 * pp.Word(pp.nums)("second*")
-        results = expr.parseString("spam 111 222")
+        with self.subTest():
+            expr = pp.Word(pp.alphas)("first") + 2 * pp.Word(pp.nums)("second*")
+            results = expr.parseString("spam 111 222", parseAll=True)
 
-        print(results.dump())
-        expected = "spam", "111", "222"
-        self.assertParseResultsEquals(
-            results, expected, msg="issue with int * ParserElement"
-        )
+            print(results.dump())
+            expected = "spam", "111", "222"
+            self.assertParseResultsEquals(
+                results, expected, msg="issue with int * ParserElement"
+            )
 
     def testParserElementMatchFirstOperatorWithOtherTypes(self):
         """test the overridden "|" operator with other data types"""
 
         # ParserElement | int
-        expr = None
-        with self.assertRaises(TypeError, msg="failed to warn ParserElement | int"):
-            expr = pp.Word(pp.alphas)("first") + (pp.Word(pp.alphas)("second") | 12)
-        self.assertEqual(expr, None)
+        with self.subTest():
+            expr = None
+            with self.assertRaises(TypeError, msg="failed to warn ParserElement | int"):
+                expr = pp.Word(pp.alphas)("first") + (pp.Word(pp.alphas)("second") | 12)
+            self.assertEqual(expr, None)
 
         # int | ParserElement
-        expr = None
-        with self.assertRaises(TypeError, msg="failed to warn int | ParserElement"):
-            expr = pp.Word(pp.alphas)("first") + (12 | pp.Word(pp.alphas)("second"))
-        self.assertEqual(expr, None)
+        with self.subTest():
+            expr = None
+            with self.assertRaises(TypeError, msg="failed to warn int | ParserElement"):
+                expr = pp.Word(pp.alphas)("first") + (12 | pp.Word(pp.alphas)("second"))
+            self.assertEqual(expr, None)
 
     def testParserElementMatchLongestWithOtherTypes(self):
         """test the overridden "^" operator with other data types"""
 
         # ParserElement ^ str
-        expr = pp.Word(pp.alphas)("first") + (pp.Word(pp.nums)("second") ^ "eggs")
-        result = expr.parseString("spam eggs")
-        print(result)
+        with self.subTest():
+            expr = pp.Word(pp.alphas)("first") + (pp.Word(pp.nums)("second") ^ "eggs")
+            result = expr.parseString("spam eggs", parseAll=True)
+            print(result)
 
-        expected = "spam", "eggs"
-        self.assertParseResultsEquals(
-            result, expected, msg="issue with ParserElement ^ str"
-        )
+            expected = "spam", "eggs"
+            self.assertParseResultsEquals(
+                result, expected, msg="issue with ParserElement ^ str"
+            )
 
         # str ^ ParserElement
-        expr = ("pre" ^ pp.Word("pr")("first")) + pp.Word(pp.alphas)("second")
-        result = expr.parseString("pre eggs")
-        print(result)
+        with self.subTest():
+            expr = ("pre" ^ pp.Word("pr")("first")) + pp.Word(pp.alphas)("second")
+            result = expr.parseString("pre eggs", parseAll=True)
+            print(result)
 
-        expected = "pre", "eggs"
-        self.assertParseResultsEquals(
-            result, expected, msg="issue with str ^ ParserElement"
-        )
+            expected = "pre", "eggs"
+            self.assertParseResultsEquals(
+                result, expected, msg="issue with str ^ ParserElement"
+            )
 
         # ParserElement ^ int
-        expr = None
-        with self.assertRaises(TypeError, msg="failed to warn ParserElement ^ int"):
-            expr = pp.Word(pp.alphas)("first") + (pp.Word(pp.alphas)("second") ^ 54)
-        self.assertEqual(expr, None)
+        with self.subTest():
+            expr = None
+            with self.assertRaises(TypeError, msg="failed to warn ParserElement ^ int"):
+                expr = pp.Word(pp.alphas)("first") + (pp.Word(pp.alphas)("second") ^ 54)
+            self.assertEqual(expr, None)
 
         # int ^ ParserElement
-        expr = None
-        with self.assertRaises(TypeError, msg="failed to warn int ^ ParserElement"):
-            expr = pp.Word(pp.alphas)("first") + (65 ^ pp.Word(pp.alphas)("second"))
-        self.assertEqual(expr, None)
+        with self.subTest():
+            expr = None
+            with self.assertRaises(TypeError, msg="failed to warn int ^ ParserElement"):
+                expr = pp.Word(pp.alphas)("first") + (65 ^ pp.Word(pp.alphas)("second"))
+            self.assertEqual(expr, None)
 
     def testParserElementEachOperatorWithOtherTypes(self):
         """test the overridden "&" operator with other data types"""
 
         # ParserElement & str
-        expr = pp.Word(pp.alphas)("first") + (pp.Word(pp.alphas)("second") & "and")
-        with self.assertRaisesParseException(msg="issue with ParserElement & str"):
-            result = expr.parseString("spam and eggs")
+        with self.subTest():
+            expr = pp.Word(pp.alphas)("first") + (pp.Word(pp.alphas)("second") & "and")
+            with self.assertRaisesParseException(msg="issue with ParserElement & str"):
+                result = expr.parseString("spam and eggs", parseAll=True)
 
         # str & ParserElement
-        expr = pp.Word(pp.alphas)("first") + ("and" & pp.Word(pp.alphas)("second"))
-        result = expr.parseString("spam and eggs")
+        with self.subTest():
+            expr = pp.Word(pp.alphas)("first") + ("and" & pp.Word(pp.alphas)("second"))
+            result = expr.parseString("spam and eggs", parseAll=True)
 
-        print(result.dump())
-        expected_l = "spam", "and", "eggs"
-        expected_d = {"first": "spam", "second": "eggs"}
-        self.assertParseResultsEquals(
-            result,
-            expected_list=expected_l,
-            expected_dict=expected_d,
-            msg="issue with str & ParserElement",
-        )
+            print(result.dump())
+            expected_l = "spam", "and", "eggs"
+            expected_d = {"first": "spam", "second": "eggs"}
+            self.assertParseResultsEquals(
+                result,
+                expected_list=expected_l,
+                expected_dict=expected_d,
+                msg="issue with str & ParserElement",
+            )
 
         # ParserElement & int
-        expr = None
-        with self.assertRaises(TypeError, msg="failed to warn ParserElement & int"):
-            expr = pp.Word(pp.alphas)("first") + (pp.Word(pp.alphas) & 78)
-        self.assertEqual(expr, None)
+        with self.subTest():
+            expr = None
+            with self.assertRaises(TypeError, msg="failed to warn ParserElement & int"):
+                expr = pp.Word(pp.alphas)("first") + (pp.Word(pp.alphas) & 78)
+            self.assertEqual(expr, None)
 
         # int & ParserElement
-        expr = None
-        with self.assertRaises(TypeError, msg="failed to warn int & ParserElement"):
-            expr = pp.Word(pp.alphas)("first") + (89 & pp.Word(pp.alphas))
-        self.assertEqual(expr, None)
+        with self.subTest():
+            expr = None
+            with self.assertRaises(TypeError, msg="failed to warn int & ParserElement"):
+                expr = pp.Word(pp.alphas)("first") + (89 & pp.Word(pp.alphas))
+            self.assertEqual(expr, None)
+
+    def testLshiftOperatorWithOtherTypes(self):
+        # Forward << ParserElement
+        with self.subTest():
+            f = pp.Forward()
+            f << pp.Word(pp.alphas)...
+            test_string = "sljdf sldkjf Ljs"
+            result = f.parse_string(test_string)
+            print(result)
+            self.assertEqual(test_string.split(), result.as_list())
+
+        # Forward << str
+        with self.subTest():
+            f = pp.Forward()
+            f << "AAA"
+            test_string = "AAA"
+            result = f.parse_string(test_string)
+            print(result)
+            self.assertEqual(test_string.split(), result.as_list())
+
+        # Forward << int
+        with self.subTest():
+            f = pp.Forward()
+            with self.assertRaises(TypeError, msg="failed to warn int & ParserElement"):
+                f << 12
 
     def testParserElementPassedThreeArgsToMultiplierShorthand(self):
         """test the ParserElement form exprm,n,o"""
@@ -3019,7 +3328,7 @@
         """test less common paths of ParseResults.__new__()"""
 
         parser = pp.Word(pp.alphas)...
-        result = parser.parseString("sldkjf sldkjf")
+        result = parser.parseString("sldkjf sldkjf", parseAll=True)
 
         # hasattr uses __getattr__, which for ParseResults will return "" if the
         # results name is not defined. So hasattr() won't work with ParseResults.
@@ -3057,7 +3366,7 @@
 
         tst = "1 2 3 4 5"
         expr = pp.OneOrMore(pp.Word(pp.nums))
-        result = expr.parseString(tst)
+        result = expr.parseString(tst, parseAll=True)
 
         reversed_list = ii for ii in reversed(result)
         print(reversed_list)
@@ -3070,7 +3379,7 @@
         """test simple case of ParseResults.values()"""
 
         expr = pp.Word(pp.alphas)("first") + pp.Word(pp.alphas)("second")
-        result = expr.parseString("spam eggs")
+        result = expr.parseString("spam eggs", parseAll=True)
 
         values_set = set(result.values())
         print(values_set)
@@ -3087,7 +3396,7 @@
             tokens.append(sum(map(int, tokens)))
 
         expr = pp.OneOrMore(pp.Word(pp.nums)).addParseAction(append_sum)
-        result = expr.parseString("0 123 321")
+        result = expr.parseString("0 123 321", parseAll=True)
 
         expected = "0", "123", "321", 444
         print(result.dump())
@@ -3100,7 +3409,7 @@
 
         tst = "spam eggs"
         expr = pp.Word(pp.alphas)("first") + pp.Word(pp.alphas)("second")
-        result = expr.parseString(tst)
+        result = expr.parseString(tst, parseAll=True)
 
         print(result.dump())
         self.assertParseResultsEquals(
@@ -3126,7 +3435,7 @@
 
         tst = "abc def ghi"
         expr = pp.OneOrMore(pp.Word(pp.alphas))
-        result = expr.addParseAction(make_palindrome).parseString(tst)
+        result = expr.addParseAction(make_palindrome).parseString(tst, parseAll=True)
         print(result.dump())
 
         expected = "abc", "def", "ghi", "ihg", "fed", "cba"
@@ -3138,8 +3447,8 @@
         """test ParseResults.extend() with input of type ParseResults"""
 
         expr = pp.OneOrMore(pp.Word(pp.alphas))
-        result1 = expr.parseString("spam eggs")
-        result2 = expr.parseString("foo bar")
+        result1 = expr.parseString("spam eggs", parseAll=True)
+        result2 = expr.parseString("foo bar", parseAll=True)
 
         result1.extend(result2)
         print(result1.dump())
@@ -3148,6 +3457,17 @@
             result1, expected, msg="issue with ParseResults.extend(ParseResults)"
         )
 
+    def testQuotedStringLoc(self):
+        expr = pp.QuotedString("'")
+        expr.add_parse_action(lambda t: t0.upper())
+
+        test_string = "Using 'quotes' for 'sarcasm' or 'emphasis' is not good 'style'."
+        transformed = expr.transform_string(test_string)
+        print(test_string)
+        print(transformed)
+        expected = re.sub(r"'(^'+)'", lambda match: match1.upper(), test_string)
+        self.assertEqual(expected, transformed)
+
     def testParseResultsWithNestedNames(self):
         from pyparsing import (
             Dict,
@@ -3238,7 +3558,9 @@
         ):
             modifier_parser = modifier_list_fn("default")
 
-            result = modifier_parser.parseString("/respectaccents/ignoreaccents")
+            result = modifier_parser.parseString(
+                "/respectaccents/ignoreaccents", parseAll=True
+            )
             for r in result:
                 print(r)
                 print(r.get("_info_"))
@@ -3284,7 +3606,9 @@
 
         from random import randint
 
-        result = pp.Word(pp.alphas)....parseString("A B C D E F G H I J")
+        result = pp.Word(pp.alphas)....parseString(
+            "A B C D E F G H I J", parseAll=True
+        )
         compare_list = result.asList()
 
         print(result)
@@ -3310,10 +3634,10 @@
             self.fail("fail getting named result when empty")
 
     def testParseResultsBool(self):
-        result = pp.Word(pp.alphas)....parseString("AAA")
+        result = pp.Word(pp.alphas)....parseString("AAA", parseAll=True)
         self.assertTrue(result, "non-empty ParseResults evaluated as False")
 
-        result = pp.Word(pp.alphas)....parseString("")
+        result = pp.Word(pp.alphas)....parseString("", parseAll=True)
         self.assertFalse(result, "empty ParseResults evaluated as True")
 
         result"A" = 0
@@ -3322,12 +3646,165 @@
             "ParseResults with empty list but containing a results name evaluated as False",
         )
 
+    def testParseResultsCopy(self):
+        expr = (
+            pp.Word(pp.nums)
+            + pp.Group(pp.Word(pp.alphas)("key") + "=" + pp.Word(pp.nums)("value"))...
+        )
+        result = expr.parse_string("1 a=100 b=200 c=300")
+        print(result.dump())
+
+        r2 = result.copy()
+        print(r2.dump())
+
+        # check copy is different, but contained results is the same as in original
+        self.assertFalse(r2 is result, "copy failed")
+        self.assertTrue(r21 is result1, "shallow copy failed")
+
+        # update result sub-element in place
+        result10 = "z"
+        self.assertParseResultsEquals(
+            result,
+            expected_list=
+                "1",
+                "z", "=", "100",
+                "b", "=", "200",
+                "c", "=", "300",
+            ,
+        )
+
+        # update contained results, verify list and dict contents are updated as expected
+        result10 = result1"key" = "q"
+        result1"xyz" = 1000
+        print(result.dump())
+        self.assertParseResultsEquals(
+            result,
+            expected_list=
+                "1",
+                "q", "=", "100",
+                "b", "=", "200",
+                "c", "=", "300",
+            ,
+        )
+        self.assertParseResultsEquals(
+            result1, expected_dict={"key": "q", "value": "100", "xyz": 1000}
+        )
+
+        # verify that list and dict contents are the same in copy
+        self.assertParseResultsEquals(
+            r2,
+            expected_list=
+                "1",
+                "q", "=", "100",
+                "b", "=", "200",
+                "c", "=", "300",
+            ,
+        )
+        self.assertParseResultsEquals(
+            r21, expected_dict={"key": "q", "value": "100", "xyz": 1000}
+        )
+
+    def testParseResultsDeepcopy(self):
+        expr = (
+            pp.Word(pp.nums)
+            + pp.Group(pp.Word(pp.alphas)("key") + "=" + pp.Word(pp.nums)("value"))...
+        )
+        result = expr.parse_string("1 a=100 b=200 c=300")
+
+        r2 = result.deepcopy()
+        print(r2.dump())
+
+        # check copy and contained results are different from original
+        self.assertFalse(r2 is result, "copy failed")
+        self.assertFalse(r21 is result1, "deep copy failed")
+
+        # update contained results
+        result10 = result1"key" = "q"
+        result1"xyz" = 1000
+        print(result.dump())
+
+        # verify that list and dict contents are unchanged in the copy
+        self.assertParseResultsEquals(
+            r2,
+            expected_list=
+                "1",
+                "a", "=", "100",
+                "b", "=", "200",
+                "c", "=", "300",
+            ,
+        )
+        self.assertParseResultsEquals(r21, expected_dict={"key": "a", "value": "100"})
+
+    def testParseResultsDeepcopy2(self):
+        expr = (
+            pp.Word(pp.nums)
+            + pp.Group(
+                pp.Word(pp.alphas)("key") + "=" + pp.Word(pp.nums)("value"), aslist=True
+            )...
+        )
+        result = expr.parse_string("1 a=100 b=200 c=300")
+
+        r2 = result.deepcopy()
+        print(r2.dump())
+
+        # check copy and contained results are different from original
+        self.assertFalse(r2 is result, "copy failed")
+        self.assertFalse(r21 is result1, "deep copy failed")
+
+        # update contained results
+        result10 = "q"
+        print(result.dump())
+
+        # verify that list and dict contents are unchanged in the copy
+        self.assertParseResultsEquals(
+            r2,
+            expected_list=
+                "1",
+                "a", "=", "100",
+                "b", "=", "200",
+                "c", "=", "300",
+            ,
+        )
+
+    def testParseResultsDeepcopy3(self):
+        expr = (
+            pp.Word(pp.nums)
+            + pp.Group(
+                (
+                    pp.Word(pp.alphas)("key") + "=" + pp.Word(pp.nums)("value")
+                ).add_parse_action(lambda t: tuple(t))
+            )...
+        )
+        result = expr.parse_string("1 a=100 b=200 c=300")
+
+        r2 = result.deepcopy()
+        print(r2.dump())
+
+        # check copy and contained results are different from original
+        self.assertFalse(r2 is result, "copy failed")
+        self.assertFalse(r21 is result1, "deep copy failed")
+
+        # update contained results
+        result10 = "q"
+        print(result.dump())
+
+        # verify that list and dict contents are unchanged in the copy
+        self.assertParseResultsEquals(
+            r2,
+            expected_list=
+                "1",
+                ("a", "=", "100"),
+                ("b", "=", "200"),
+                ("c", "=", "300"),
+            ,
+        )
+
     def testIgnoreString(self):
         """test ParserElement.ignore() passed a string arg"""
 
         tst = "I like totally like love pickles"
         expr = pp.Word(pp.alphas)....ignore("like")
-        result = expr.parseString(tst)
+        result = expr.parseString(tst, parseAll=True)
 
         print(result)
         expected = "I", "totally", "love", "pickles"
@@ -3362,24 +3839,18 @@
                 self.assertEqual(
                     expectedEmpty,
                     bool(t.empty),
-                    "expected {} token, got {}".format(
-                        expectedEmpty and "empty" or "not empty",
-                        t.empty and "empty" or "not empty",
-                    ),
+                    f"expected {expectedEmpty and 'empty' or 'not empty'} token,"
+                    f" got {t.empty and 'empty' or 'not empty'}",
                 )
                 self.assertEqual(
                     expectedBG,
                     t.bgcolor,
-                    "failed to match BGCOLOR, expected {}, got {}".format(
-                        expectedBG, t.bgcolor
-                    ),
+                    f"failed to match BGCOLOR, expected {expectedBG}, got {t.bgcolor}",
                 )
                 self.assertEqual(
                     expectedFG,
                     t.fgcolor,
-                    "failed to match FGCOLOR, expected {}, got {}".format(
-                        expectedFG, t.bgcolor
-                    ),
+                    f"failed to match FGCOLOR, expected {expectedFG}, got {t.bgcolor}",
                 )
             elif "endBody" in t:
                 print("end tag")
@@ -3396,7 +3867,7 @@
         with self.assertRaises(TypeError):
             expr.setParseAction(uncallable)
 
-        res = expr.parseString("A")
+        res = expr.parseString("A", parseAll=True)
         print(res.dump())
 
     def testMulWithNegativeNumber(self):
@@ -3409,7 +3880,7 @@
         """multiply an expression with Ellipsis as ``expr * ...`` to match ZeroOrMore"""
 
         expr = pp.Literal("A")("Achar") * ...
-        res = expr.parseString("A")
+        res = expr.parseString("A", parseAll=True)
         self.assertEqual("A", res.asList(), "expected expr * ... to match ZeroOrMore")
         print(res.dump())
 
@@ -3439,7 +3910,7 @@
         kw = pp.Keyword("mykey", caseless=True).setParseAction(ppc.upcaseTokens)(
             "rname"
         )
-        ret = kw.parseString("mykey")
+        ret = kw.parseString("mykey", parseAll=True)
         print(ret.rname)
         self.assertEqual(
             "MYKEY", ret.rname, "failed to upcase with named result (pyparsing_common)"
@@ -3448,7 +3919,7 @@
         kw = pp.Keyword("MYKEY", caseless=True).setParseAction(ppc.downcaseTokens)(
             "rname"
         )
-        ret = kw.parseString("mykey")
+        ret = kw.parseString("mykey", parseAll=True)
         print(ret.rname)
         self.assertEqual("mykey", ret.rname, "failed to upcase with named result")
 
@@ -3472,7 +3943,6 @@
             )
 
     def testParseUsingRegex(self):
-
         signedInt = pp.Regex(r"-+0-9+")
         unsignedInt = pp.Regex(r"0-9+")
         simpleString = pp.Regex(r'("^\"*")|(\'^\'*\')')
@@ -3482,17 +3952,12 @@
         def testMatch(expression, instring, shouldPass, expectedString=None):
             if shouldPass:
                 try:
-                    result = expression.parseString(instring)
-                    print(
-                        "{} correctly matched {}".format(
-                            repr(expression), repr(instring)
-                        )
-                    )
+                    result = expression.parseString(instring, parseAll=False)
+                    print(f"{repr(expression)} correctly matched {repr(instring)}")
                     if expectedString != result0:
                         print("\tbut failed to match the pattern as expected:")
                         print(
-                            "\tproduced %s instead of %s"
-                            % (repr(result0), repr(expectedString))
+                            f"\tproduced {repr(result0)} instead of {repr(expectedString)}"
                         )
                     return True
                 except pp.ParseException:
@@ -3502,18 +3967,11 @@
                     )
             else:
                 try:
-                    result = expression.parseString(instring)
-                    print(
-                        "{} incorrectly matched {}".format(
-                            repr(expression), repr(instring)
-                        )
-                    )
-                    print("\tproduced %s as a result" % repr(result0))
+                    result = expression.parseString(instring, parseAll=False)
+                    print(f"{expression!r} incorrectly matched {instring!r}")
+                    print(f"\tproduced {result0!r} as a result")
                 except pp.ParseException:
-                    print(
-                        "%s correctly failed to match %s"
-                        % (repr(expression), repr(instring))
-                    )
+                    print(f"{expression!r} correctly failed to match {instring!r}")
                     return True
             return False
 
@@ -3585,13 +4043,14 @@
             testMatch(namedGrouping, '"foo bar" baz', True, '"foo bar"'),
             "Re: (16) failed, expected pass",
         )
-        ret = namedGrouping.parseString('"zork" blah')
+        ret = namedGrouping.parseString('"zork" blah', parseAll=False)
         print(ret)
         print(list(ret.items()))
         print(ret.content)
         self.assertEqual("zork", ret.content, "named group lookup failed")
+
         self.assertEqual(
-            simpleString.parseString('"zork" blah')0,
+            simpleString.parseString('"zork" blah', parseAll=False)0,
             ret0,
             "Regex not properly returning ParseResults for named vs. unnamed groups",
         )
@@ -3611,13 +4070,12 @@
             pp.Regex("").re
 
     def testRegexAsType(self):
-
         test_str = "sldkjfj 123 456 lsdfkj"
 
         print("return as list of match groups")
         expr = pp.Regex(r"\w+ (\d+) (\d+) (\w+)", asGroupList=True)
         expected_group_list = tuple(test_str.split()1:)
-        result = expr.parseString(test_str)
+        result = expr.parseString(test_str, parseAll=True)
         print(result.dump())
         print(expected_group_list)
         self.assertParseResultsEquals(
@@ -3630,7 +4088,7 @@
         expr = pp.Regex(
             r"\w+ (?P<num1>\d+) (?P<num2>\d+) (?P<last_word>\w+)", asMatch=True
         )
-        result = expr.parseString(test_str)
+        result = expr.parseString(test_str, parseAll=True)
         print(result.dump())
         print(result0.groups())
         print(expected_group_list)
@@ -3646,7 +4104,6 @@
         )
 
     def testRegexSub(self):
-
         print("test sub with string")
         expr = pp.Regex(r"<title>").sub("'Richard III'")
         result = expr.transformString("This is the title: <title>")
@@ -3707,7 +4164,6 @@
             expr = pp.Regex(12)
 
     def testPrecededBy(self):
-
         num = pp.Word(pp.nums).setParseAction(lambda t: int(t0))
         interesting_num = pp.PrecededBy(pp.Char("abc")("prefix*")) + num
         semi_interesting_num = pp.PrecededBy("_") + num
@@ -3747,13 +4203,12 @@
             print("got maximum excursion limit exception")
 
     def testCountedArray(self):
-
         testString = "2 5 7 6 0 1 2 3 4 5 0 3 5 4 3"
 
         integer = pp.Word(pp.nums).setParseAction(lambda t: int(t0))
         countedField = pp.countedArray(integer)
 
-        r = pp.OneOrMore(pp.Group(countedField)).parseString(testString)
+        r = pp.OneOrMore(pp.Group(countedField)).parseString(testString, parseAll=True)
         print(testString)
         print(r)
 
@@ -3763,14 +4218,15 @@
 
     # addresses bug raised by Ralf Vosseler
     def testCountedArrayTest2(self):
-
         testString = "2 5 7 6 0 1 2 3 4 5 0 3 5 4 3"
 
         integer = pp.Word(pp.nums).setParseAction(lambda t: int(t0))
         countedField = pp.countedArray(integer)
 
         dummy = pp.Word("A")
-        r = pp.OneOrMore(pp.Group(dummy ^ countedField)).parseString(testString)
+        r = pp.OneOrMore(pp.Group(dummy ^ countedField)).parseString(
+            testString, parseAll=True
+        )
         print(testString)
         print(r)
 
@@ -3779,7 +4235,6 @@
         )
 
     def testCountedArrayTest3(self):
-
         int_chars = "_" + pp.alphas
         array_counter = pp.Word(int_chars).setParseAction(
             lambda t: int_chars.index(t0)
@@ -3791,7 +4246,7 @@
         integer = pp.Word(pp.nums).setParseAction(lambda t: int(t0))
         countedField = pp.countedArray(integer, intExpr=array_counter)
 
-        r = pp.OneOrMore(pp.Group(countedField)).parseString(testString)
+        r = pp.OneOrMore(pp.Group(countedField)).parseString(testString, parseAll=True)
         print(testString)
         print(r)
 
@@ -3822,8 +4277,8 @@
 
         print(testString)
         print(r.dump())
-        print("type = {!r}".format(r.type))
-        print("source = {!r}".format(r.source))
+        print(f"type = {r.type!r}")
+        print(f"source = {r.source!r}")
 
         self.assertParseResultsEquals(
             r,
@@ -3849,7 +4304,7 @@
         typed_array = pp.countedArray(
             pp.Word(pp.alphanums), intExpr=count_with_metadata
         )("items")
-        result = typed_array.parseString("3 bool True True False")
+        result = typed_array.parseString("3 bool True True False", parseAll=True)
         print(result.dump())
 
         self.assertParseResultsEquals(
@@ -3859,7 +4314,6 @@
         )
 
     def testLineStart(self):
-
         pass_tests = 
             """\
             AAA
@@ -3926,7 +4380,6 @@
             self.assertTrue(success, "failed LineStart failure mode tests (3)")
 
     def testLineStart2(self):
-
         test = """\
         AAA 1
         AAA 2
@@ -4083,7 +4536,6 @@
             test(P_MTARG3, "\n   aaa")
 
     def testLineAndStringEnd(self):
-
         NLs = pp.OneOrMore(pp.lineEnd)
         bnf1 = pp.delimitedList(pp.Word(pp.alphanums).leaveWhitespace(), NLs)
         bnf2 = pp.Word(pp.alphanums) + pp.stringEnd
@@ -4095,7 +4547,7 @@
         
 
         for test, expected in tests:
-            res1 = bnf1.parseString(test)
+            res1 = bnf1.parseString(test, parseAll=True)
             print(res1, "=?", expected)
             self.assertParseResultsEquals(
                 res1,
@@ -4117,7 +4569,7 @@
                 + str(res2),
             )
 
-            res3 = bnf3.parseString(test)
+            res3 = bnf3.parseString(test, parseAll=True)
             first = res30
             rest = res31
             # ~ print res3.dump()
@@ -4302,7 +4754,7 @@
         )
         # fmt: on
         testString = "VUTSRQPONMLKJIHGFEDCBA"
-        res = gg.parseString(testString)
+        res = gg.parseString(testString, parseAll=True)
         print(res)
         self.assertParseResultsEquals(
             res,
@@ -4322,7 +4774,7 @@
         )
         # fmt: on
         testString = "VUTSRQPONMLKJIHGFEDCBA"
-        res = gg.parseString(testString)
+        res = gg.parseString(testString, parseAll=True)
         print(list(map(str, res)))
         self.assertEqual(
             list(testString),
@@ -4332,7 +4784,6 @@
         )
 
     def testSingleArgException(self):
-
         testMessage = "just one arg"
         try:
             raise pp.ParseFatalException(testMessage)
@@ -4378,7 +4829,6 @@
         )
 
     def testPackratParsingCacheCopy(self):
-
         integer = pp.Word(pp.nums).setName("integer")
         id = pp.Word(pp.alphas + "_", pp.alphanums + "_")
         simpleType = pp.Literal("int")
@@ -4408,7 +4858,6 @@
         )
 
     def testPackratParsingCacheCopyTest2(self):
-
         DO, AA = list(map(pp.Keyword, "DO AA".split()))
         LPAR, RPAR = list(map(pp.Suppress, "()"))
         identifier = ~AA + pp.Word("Z")
@@ -4423,7 +4872,7 @@
         )  # .setDebug()#.setBreak()
 
         stmt = DO + pp.Group(pp.delimitedList(identifier + ".*" | expr))
-        result = stmt.parseString("DO Z")
+        result = stmt.parseString("DO Z", parseAll=True)
         print(result.asList())
         self.assertEqual(
             1, len(result1), "packrat parsing is duplicating And term exprs"
@@ -4433,7 +4882,7 @@
         grammar = pp.OneOrMore(pp.Word(pp.nums))("ints") + pp.OneOrMore(
             pp.Word(pp.alphas)
         )("words")
-        res = grammar.parseString("123 456 ABC DEF")
+        res = grammar.parseString("123 456 ABC DEF", parseAll=True)
         print(res.dump())
         origInts = res.ints.asList()
         origWords = res.words.asList()
@@ -4497,7 +4946,6 @@
             ,
             expected,
         ):
-
             tagStart.setParseAction(attrib)
             result = expr.searchString(data)
 
@@ -4505,9 +4953,7 @@
             self.assertParseResultsEquals(
                 result,
                 expected_list=exp,
-                msg="Failed test, expected {}, got {}".format(
-                    expected, result.asList()
-                ),
+                msg=f"Failed test, expected {expected}, got {result.asList()}",
             )
 
     def testNestedExpressions(self):
@@ -4534,14 +4980,12 @@
         expr = pp.nestedExpr()
 
         expected = "ax", "+", "by", "*C"
-        result = expr.parseString(teststring)
+        result = expr.parseString(teststring, parseAll=False)
         print(result.dump())
         self.assertParseResultsEquals(
             result,
             expected_list=expected,
-            msg="Defaults didn't work. That's a bad sign. Expected: {}, got: {}".format(
-                expected, result
-            ),
+            msg=f"Defaults didn't work. That's a bad sign. Expected: {expected}, got: {result}",
         )
 
         # Going through non-defaults, one by one; trying to think of anything
@@ -4556,9 +5000,7 @@
             expr,
             teststring,
             expected,
-            "Non-default opener didn't work. Expected: {}, got: {}".format(
-                expected, result
-            ),
+            f"Non-default opener didn't work. Expected: {expected}, got: {result}",
             verbose=True,
         )
 
@@ -4572,9 +5014,7 @@
             expr,
             teststring,
             expected,
-            "Non-default closer didn't work. Expected: {}, got: {}".format(
-                expected, result
-            ),
+            f"Non-default closer didn't work. Expected: {expected}, got: {result}",
             verbose=True,
         )
 
@@ -4594,9 +5034,7 @@
             expr,
             teststring,
             expected,
-            "Multicharacter opener and closer didn't work. Expected: {}, got: {}".format(
-                expected, result
-            ),
+            f"Multicharacter opener and closer didn't work. Expected: {expected}, got: {result}",
             verbose=True,
         )
 
@@ -4621,9 +5059,7 @@
             expr,
             teststring,
             expected,
-            'Lisp-ish comments (";; <...> $") didn\'t work. Expected: {}, got: {}'.format(
-                expected, result
-            ),
+            f'Lisp-ish comments (";; <...> $") didn\'t work. Expected: {expected}, got: {result}',
             verbose=True,
         )
 
@@ -4650,9 +5086,7 @@
             expr,
             teststring,
             expected,
-            'Lisp-ish comments (";; <...> $") and quoted strings didn\'t work. Expected: {}, got: {}'.format(
-                expected, result
-            ),
+            f'Lisp-ish comments (";; <...> $") and quoted strings didn\'t work. Expected: {expected}, got: {result}',
             verbose=True,
         )
 
@@ -4683,7 +5117,7 @@
         # multi-character opener and/or closer
         tstMulti = "aName {{ outer {{ 'inner with opener {{ and closer }} in quoted string' }} }}"
         expr = name + pp.nestedExpr(opener="{{", closer="}}")
-        result = expr.parseString(tstMulti)
+        result = expr.parseString(tstMulti, parseAll=True)
         expected = 
             "aName",
             "outer", "'inner with opener {{ and closer }} in quoted string'",
@@ -4694,16 +5128,14 @@
         )
 
         # single character opener and closer with ignoreExpr=None
-        tst = (
-            "aName { outer { 'inner with opener { and closer } in quoted string' }} }}"
-        )
+        tst = "aName { outer { 'inner with opener { and closer } in quoted string' }}"
         expr = name + pp.nestedExpr(opener="{", closer="}", ignoreExpr=None)
-        singleCharResult = expr.parseString(tst)
+        singleCharResult = expr.parseString(tst, parseAll=True)
         print(singleCharResult.dump())
 
         # multi-character opener and/or closer with ignoreExpr=None
         expr = name + pp.nestedExpr(opener="{{", closer="}}", ignoreExpr=None)
-        multiCharResult = expr.parseString(tstMulti)
+        multiCharResult = expr.parseString(tstMulti, parseAll=True)
         print(multiCharResult.dump())
 
         self.assertParseResultsEquals(
@@ -4741,17 +5173,138 @@
         for p in parsers:
             print(p, getattr(p, "reString", "..."), end=" ", flush=True)
             try:
-                p.parseString("A123")
+                p.parseString("A123", parseAll=True)
             except Exception as e:
                 print("      <<< FAIL")
                 fails.append(p)
             else:
                 print()
         if fails:
-            self.fail("{} failed to match".format(",".join(str(f) for f in fails)))
+            self.fail(f"{','.join(str(f) for f in fails)} failed to match")
 
-    def testWordExclude(self):
+    def testWordMinMaxExactArgs(self):
+        for minarg in range(1, 9):
+            for maxarg in range(minarg, 10):
+                with self.subTest(minarg=minarg, maxarg=maxarg):
+                    expr = pp.Word("AB", pp.nums, min=minarg, max=maxarg)
+                    print(minarg, maxarg, expr.reString, end=" ")
+                    trailing = expr.reString.rpartition("")-1
+                    expected_special = {
+                        (1, 1): "",
+                        (1, 2): "?",
+                        (2, 2): "",
+                    }
+                    expected_default = (
+                        f"{{{minarg - 1}}}"
+                        if minarg == maxarg
+                        else f"{{{minarg - 1},{maxarg - 1}}}"
+                    )
+                    expected = expected_special.get((minarg, maxarg), expected_default)
+
+                    print(trailing == expected)
+
+                    self.assertEqual(trailing, expected)
+
+                    self.assertParseAndCheckList(
+                        expr + pp.restOfLine.suppress(),
+                        "A1234567890",
+                        "A1234567890":maxarg,
+                    )
+
+        for exarg in range(1, 9):
+            with self.subTest(exarg=exarg):
+                expr = pp.Word("AB", pp.nums, exact=exarg)
+                print(exarg, expr.reString, end=" ")
+                trailing = expr.reString.rpartition("")-1
+                if exarg < 3:
+                    expected = ""
+                else:
+                    expected = f"{{{exarg - 1}}}"
+                print(trailing == expected)
+
+                self.assertEqual(trailing, expected)
+
+                self.assertParseAndCheckList(
+                    expr + pp.restOfLine.suppress(),
+                    "A1234567890",
+                    "A1234567890":exarg,
+                )
+
+    def testWordMin(self):
+        # failing tests
+        for min_val in range(3, 5):
+            with self.subTest(min_val=min_val):
+                wd = pp.Word("a", "1", min=min_val)
+                print(min_val, wd.reString)
+                with self.assertRaisesParseException():
+                    wd.parse_string("a1")
+
+        for min_val in range(2, 5):
+            with self.subTest(min_val=min_val):
+                wd = pp.Word("a", min=min_val)
+                print(min_val, wd.reString)
+                with self.assertRaisesParseException():
+                    wd.parse_string("a")
+
+        for min_val in range(3, 5):
+            with self.subTest(min_val=min_val):
+                wd = pp.Word("a", "1", min=min_val)
+                print(min_val, wd.reString)
+                with self.assertRaisesParseException():
+                    wd.parse_string("a1")
+
+        # passing tests
+        for min_val in range(2, 5):
+            with self.subTest(min_val=min_val):
+                wd = pp.Word("a", min=min_val)
+                test_string = "a" * min_val
+                self.assertParseAndCheckList(
+                    wd,
+                    test_string,
+                    test_string,
+                    msg=f"Word(min={min_val}) failed",
+                    verbose=True,
+                )
+
+        for min_val in range(2, 5):
+            with self.subTest(min_val=min_val):
+                wd = pp.Word("a", "1", min=min_val)
+                test_string = "a" + "1" * (min_val - 1)
+                self.assertParseAndCheckList(
+                    wd,
+                    test_string,
+                    test_string,
+                    msg=f"Word(min={min_val}) failed",
+                    verbose=True,
+                )
+
+    def testWordExact(self):
+        # failing tests
+        for exact_val in range(2, 5):
+            with self.subTest(exact_val=exact_val):
+                wd = pp.Word("a", exact=exact_val)
+                print(exact_val, wd.reString)
+                with self.assertRaisesParseException():
+                    wd.parse_string("a")
+
+        # passing tests
+        for exact_val in range(2, 5):
+            with self.subTest(exact_val=exact_val):
+                wd = pp.Word("a", exact=exact_val)
+                test_string = "a" * exact_val
+                self.assertParseAndCheckList(
+                    wd,
+                    test_string,
+                    test_string,
+                    msg=f"Word(exact={exact_val}) failed",
+                    verbose=True,
+                )
+
+    def testInvalidMinMaxArgs(self):
+        with self.assertRaises(ValueError):
+            wd = pp.Word(min=2, max=1)
 
+    def testWordExclude(self):
         allButPunc = pp.Word(pp.printables, excludeChars=".,:;-_!?")
 
         test = "Hello, Mr. Ed, it's Wilbur!"
@@ -4763,6 +5316,30 @@
             "failed WordExcludeTest",
         )
 
+    def testWordExclude2(self):
+        punc_chars = ".,:;-_!?"
+
+        all_but_punc = pp.Word(pp.printables, excludeChars=punc_chars)
+        all_and_punc = pp.Word(pp.printables)
+
+        assert set(punc_chars) & set(all_but_punc.initChars) == set()
+
+        expr = all_but_punc("no_punc*") | all_and_punc("with_punc*")
+
+        self.assertParseAndCheckDict(
+            expr...,
+            "Mr. Ed,",
+            {"no_punc": "Mr", "Ed", "with_punc": ".", ","},
+            "failed matching with excludeChars (1)",
+        )
+
+        self.assertParseAndCheckDict(
+            expr...,
+            ":Mr. Ed,",
+            {"no_punc": "Ed", "with_punc": ":Mr.", ","},
+            "failed matching with excludeChars (2)",
+        )
+
     def testWordMinOfZero(self):
         """test a Word with min=0"""
 
@@ -4784,7 +5361,7 @@
         """test a Word with max>0 and asKeyword=True"""
         setup = self.setup_testWordMaxGreaterThanZeroAndAsKeyword()
 
-        result = setup.bool_operand....parseString(setup.test_string)
+        result = setup.bool_operand....parseString(setup.test_string, parseAll=True)
         self.assertParseAndCheckList(
             setup.bool_operand...,
             setup.test_string,
@@ -4800,7 +5377,7 @@
         with self.assertRaisesParseException(
             msg=__() + "failed to detect Word with max > 0 and asKeyword=True"
         ):
-            setup.bool_operand.parseString("abc")
+            setup.bool_operand.parseString("abc", parseAll=True)
 
     def testCharAsKeyword(self):
         """test a Char with asKeyword=True"""
@@ -4808,7 +5385,7 @@
         grade = pp.OneOrMore(pp.Char("ABCDF", asKeyword=True))
 
         # all single char words
-        result = grade.parseString("B B C A D")
+        result = grade.parseString("B B C A D", parseAll=True)
 
         print(result)
         expected = "B", "B", "C", "A", "D"
@@ -4818,7 +5395,7 @@
 
         # NOT all single char words
         test2 = "B BB C A D"
-        result2 = grade.parseString(test2)
+        result2 = grade.parseString(test2, parseAll=False)
 
         print(result2)
         expected2 = "B"
@@ -4826,6 +5403,10 @@
             result2, expected2, msg="issue with Char asKeyword=True parsing 2 chars"
         )
 
+    def testCharRe(self):
+        expr = pp.Char("ABCDEFG")
+        self.assertEqual("A-G", expr.reString)
+
     def testCharsNotIn(self):
         """test CharsNotIn initialized with various arguments"""
 
@@ -4834,7 +5415,7 @@
 
         # default args
         consonants = pp.CharsNotIn(vowels)
-        result = consonants.parseString(tst)
+        result = consonants.parseString(tst, parseAll=True)
         print(result)
         self.assertParseResultsEquals(
             result, tst, msg="issue with CharsNotIn w/ default args"
@@ -4846,7 +5427,7 @@
 
         # max > 0
         consonants = pp.CharsNotIn(vowels, max=5)
-        result = consonants.parseString(tst)
+        result = consonants.parseString(tst, parseAll=False)
         print(result)
         self.assertParseResultsEquals(
             result, tst:5, msg="issue with CharsNotIn w max > 0"
@@ -4854,7 +5435,7 @@
 
         # exact > 0
         consonants = pp.CharsNotIn(vowels, exact=10)
-        result = consonants.parseString(tst:10)
+        result = consonants.parseString(tst:10, parseAll=True)
         print(result)
         self.assertParseResultsEquals(
             result, tst:10, msg="issue with CharsNotIn w/ exact > 0"
@@ -4863,10 +5444,9 @@
         # min > length
         consonants = pp.CharsNotIn(vowels, min=25)
         with self.assertRaisesParseException(msg="issue with CharsNotIn min > tokens"):
-            result = consonants.parseString(tst)
+            result = consonants.parseString(tst, parseAll=True)
 
     def testParseAll(self):
-
         testExpr = pp.Word("A")
 
         tests = 
@@ -4877,11 +5457,7 @@
         
         for s, parseAllFlag, shouldSucceed in tests:
             try:
-                print(
-                    "'{}' parseAll={} (shouldSucceed={})".format(
-                        s, parseAllFlag, shouldSucceed
-                    )
-                )
+                print(f"'{s}' parseAll={parseAllFlag} (shouldSucceed={shouldSucceed})")
                 testExpr.parseString(s, parseAll=parseAllFlag)
                 self.assertTrue(
                     shouldSucceed, "successfully parsed when should have failed"
@@ -4903,11 +5479,7 @@
         
         for s, parseAllFlag, shouldSucceed in tests:
             try:
-                print(
-                    "'{}' parseAll={} (shouldSucceed={})".format(
-                        s, parseAllFlag, shouldSucceed
-                    )
-                )
+                print(f"'{s}' parseAll={parseAllFlag} (shouldSucceed={shouldSucceed})")
                 testExpr.parseString(s, parseAll=parseAllFlag)
                 self.assertTrue(
                     shouldSucceed, "successfully parsed when should have failed"
@@ -4933,11 +5505,7 @@
         
         for s, parseAllFlag, shouldSucceed in tests:
             try:
-                print(
-                    "'{}' parseAll={} (shouldSucceed={})".format(
-                        s, parseAllFlag, shouldSucceed
-                    )
-                )
+                print(f"'{s}' parseAll={parseAllFlag} (shouldSucceed={shouldSucceed})")
                 testExpr.parseString(s, parseAll=parseAllFlag)
                 self.assertTrue(
                     shouldSucceed, "successfully parsed when should have failed"
@@ -4949,7 +5517,6 @@
                 )
 
     def testGreedyQuotedStrings(self):
-
         src = """\
            "string1", "strin""g2"
            'string1', 'string2'
@@ -4985,27 +5552,28 @@
 
         val = tok_sql_quoted_value | tok_sql_computed_value | tok_sql_identifier
         vals = pp.delimitedList(val)
-        print(vals.parseString(src))
+        print(vals.parseString(src, parseAll=False))
         self.assertEqual(
-            5, len(vals.parseString(src)), "error in greedy quote escaping"
+            5,
+            len(vals.parseString(src, parseAll=False)),
+            "error in greedy quote escaping",
         )
 
     def testQuotedStringEscapedQuotes(self):
         quoted = pp.QuotedString('"', escQuote='""')
-        res = quoted.parseString('"like ""SQL"""')
+        res = quoted.parseString('"like ""SQL"""', parseAll=True)
         print(res.asList())
         self.assertEqual('like "SQL"', res.asList())
 
         # Issue #263 - handle case when the escQuote is not a repeated character
         quoted = pp.QuotedString("y", escChar=None, escQuote="xy")
-        res = quoted.parseString("yaaay")
+        res = quoted.parseString("yaaay", parseAll=True)
         self.assertEqual("aaa", res.asList())
-        res = quoted.parseString("yaaaxyaaay")
+        res = quoted.parseString("yaaaxyaaay", parseAll=True)
         print(res.asList())
         self.assertEqual("aaayaaa", res.asList())
 
     def testWordBoundaryExpressions(self):
-
         ws = pp.WordStart()
         we = pp.WordEnd()
         vowel = pp.oneOf(list("AEIOUY"))
@@ -5057,9 +5625,7 @@
             self.assertEqual(
                 expected,
                 results,
-                "Failed WordBoundaryTest, expected {}, got {}".format(
-                    expected, results
-                ),
+                f"Failed WordBoundaryTest, expected {expected}, got {results}",
             )
 
     def testWordBoundaryExpressions2(self):
@@ -5075,19 +5641,18 @@
         for i, (ws, we) in enumerate(product((ws1, ws2, ws3), (we1, we2, we3))):
             try:
                 expr = "(" + ws + pp.Word(pp.alphas) + we + ")"
-                expr.parseString("(abc)")
+                expr.parseString("(abc)", parseAll=True)
             except pp.ParseException as pe:
                 self.fail(f"Test {i} failed: {pe}")
             else:
                 pass
 
     def testRequiredEach(self):
-
         parser = pp.Keyword("bam") & pp.Keyword("boo")
         try:
-            res1 = parser.parseString("bam boo")
+            res1 = parser.parseString("bam boo", parseAll=True)
             print(res1.asList())
-            res2 = parser.parseString("boo bam")
+            res2 = parser.parseString("boo bam", parseAll=True)
             print(res2.asList())
         except ParseException:
             failed = True
@@ -5106,7 +5671,6 @@
             )
 
     def testOptionalEachTest1(self):
-
         for the_input in 
             "Tal Weiss Major",
             "Tal Major",
@@ -5121,8 +5685,8 @@
             parser2 = pp.Optional(
                 pp.Optional("Tal") + pp.Optional("Weiss")
             ) & pp.Keyword("Major")
-            p1res = parser1.parseString(the_input)
-            p2res = parser2.parseString(the_input)
+            p1res = parser1.parseString(the_input, parseAll=True)
+            p2res = parser2.parseString(the_input, parseAll=True)
             self.assertEqual(
                 p1res.asList(),
                 p2res.asList(),
@@ -5133,7 +5697,6 @@
             )
 
     def testOptionalEachTest2(self):
-
         word = pp.Word(pp.alphanums + "_").setName("word")
         with_stmt = "with" + pp.OneOrMore(pp.Group(word("key") + "=" + word("value")))(
             "overrides"
@@ -5149,7 +5712,6 @@
         )
 
     def testOptionalEachTest3(self):
-
         foo = pp.Literal("foo")
         bar = pp.Literal("bar")
 
@@ -5170,15 +5732,14 @@
                 exp,
                 test,
                 test.strip("{}").split(),
-                "failed to parse Each expression {!r}".format(test),
+                f"failed to parse Each expression {test!r}",
                 verbose=True,
             )
 
         with self.assertRaisesParseException():
-            exp.parseString("{bar}")
+            exp.parseString("{bar}", parseAll=True)
 
     def testOptionalEachTest4(self):
-
         expr = (~ppc.iso8601_date + ppc.integer("id")) & (
             pp.Group(ppc.iso8601_date)("date*")...
         )
@@ -5191,7 +5752,6 @@
         )
 
     def testEachWithParseFatalException(self):
-
         option_expr = pp.Keyword("options") - "(" + ppc.integer + ")"
         step_expr1 = pp.Keyword("step") - "(" + ppc.integer + ")"
         step_expr2 = pp.Keyword("step") - "(" + ppc.integer + "Z" + ")"
@@ -5223,7 +5783,7 @@
             self.assertEqual(
                 test_lookuptest_str,
                 str(result),
-                "incorrect exception raised for test string {!r}".format(test_str),
+                f"incorrect exception raised for test string {test_str!r}",
             )
 
     def testEachWithMultipleMatch(self):
@@ -5262,7 +5822,6 @@
                 self.assertParseResultsEquals(result, expected_dict=expected_dict)
 
     def testSumParseResults(self):
-
         samplestr1 = "garbage;DOB 10-10-2010;more garbage\nID PARI12345678;more garbage"
         samplestr2 = "garbage;ID PARI12345678;more garbage\nDOB 10-10-2010;more garbage"
         samplestr3 = "garbage;DOB 10-10-2010"
@@ -5283,7 +5842,7 @@
         results = (res1, res2, res3, res4)
         for test, expected in zip(tests, results):
             person = sum(person_data.searchString(test))
-            result = "ID:{} DOB:{} INFO:{}".format(person.id, person.dob, person.info)
+            result = f"ID:{person.id} DOB:{person.dob} INFO:{person.info}"
             print(test)
             print(expected)
             print(result)
@@ -5293,19 +5852,16 @@
             self.assertEqual(
                 expected,
                 result,
-                "Failed to parse '{}' correctly, \nexpected '{}', got '{}'".format(
-                    test, expected, result
-                ),
+                f"Failed to parse '{test}' correctly, \nexpected '{expected}', got '{result}'",
             )
 
     def testMarkInputLine(self):
-
         samplestr1 = "DOB 100-10-2010;more garbage\nID PARI12345678;more garbage"
 
         dob_ref = "DOB" + pp.Regex(r"\d{2}-\d{2}-\d{4}")("dob")
 
         try:
-            res = dob_ref.parseString(samplestr1)
+            res = dob_ref.parseString(samplestr1, parseAll=True)
         except ParseException as pe:
             outstr = pe.markInputline()
             print(outstr)
@@ -5384,7 +5940,7 @@
         source = "AAA 123 456 789 234"
         patt = pp.Word(pp.alphas)("name") + pp.Word(pp.nums) * (1,)
 
-        result = patt.parseString(source)
+        result = patt.parseString(source, parseAll=True)
         tests = 
             (0, "AAA", "123", "456", "789", "234"),
             (None, "234", "123", "456", "789"),
@@ -5403,14 +5959,12 @@
             self.assertEqual(
                 val,
                 ret,
-                "wrong value returned, got {!r}, expected {!r}".format(ret, val),
+                f"wrong value returned, got {ret!r}, expected {val!r}",
             )
             self.assertEqual(
                 remaining,
                 result.asList(),
-                "list is in wrong state after pop, got {!r}, expected {!r}".format(
-                    result.asList(), remaining
-                ),
+                f"list is in wrong state after pop, got {result.asList()!r}, expected {remaining!r}",
             )
             print()
 
@@ -5421,16 +5975,12 @@
         self.assertEqual(
             "noname",
             ret,
-            "default value not successfully returned, got {!r}, expected {!r}".format(
-                ret, "noname"
-            ),
+            f"default value not successfully returned, got {ret!r}, expected {'noname'!r}",
         )
         self.assertEqual(
             prevlist,
             result.asList(),
-            "list is in wrong state after pop, got {!r}, expected {!r}".format(
-                result.asList(), remaining
-            ),
+            f"list is in wrong state after pop, got {result.asList()!r}, expected {remaining!r}",
         )
 
     def testPopKwargsErr(self):
@@ -5438,14 +5988,13 @@
 
         source = "AAA 123 456 789 234"
         patt = pp.Word(pp.alphas)("name") + pp.Word(pp.nums) * (1,)
-        result = patt.parseString(source)
+        result = patt.parseString(source, parseAll=True)
         print(result.dump())
 
         with self.assertRaises(TypeError):
             result.pop(notDefault="foo")
 
     def testAddCondition(self):
-
         numParser = pp.Word(pp.nums)
         numParser.addParseAction(lambda s, l, t: int(t0))
         numParser.addCondition(lambda s, l, t: t0 % 2)
@@ -5505,7 +6054,8 @@
         # detecting the "Literal" Expression but only after the Or-decision has been made
         # (which is too late)...
         try:
-            result = (a ^ b ^ c).parseString("def")
+            result = (a ^ b ^ c).parseString("def", parseAll=False)
+            print(result)
             self.assertEqual(
                 "de",
                 result.asList(),
@@ -5533,7 +6083,7 @@
         c.streamline()
         print(c)
         test_string = "foo bar temp"
-        result = c.parseString(test_string)
+        result = c.parseString(test_string, parseAll=True)
         print(test_string, "->", result.asList())
 
         self.assertEqual(
@@ -5541,19 +6091,17 @@
         )
 
     def testEachWithOptionalWithResultsName(self):
-
         result = (pp.Optional("foo")("one") & pp.Optional("bar")("two")).parseString(
-            "bar foo"
+            "bar foo", parseAll=True
         )
         print(result.dump())
         self.assertEqual(sorted("one", "two"), sorted(result.keys()))
 
     def testUnicodeExpression(self):
-
         z = "a" | pp.Literal("\u1111")
         z.streamline()
         try:
-            z.parseString("b")
+            z.parseString("b", parseAll=True)
         except ParseException as pe:
             self.assertEqual(
                 r"""Expected {'a' | 'ᄑ'}""",
@@ -5562,7 +6110,6 @@
             )
 
     def testSetName(self):
-
         a = pp.oneOf("a b c")
         b = pp.oneOf("d e f")
         # fmt: off
@@ -5629,14 +6176,15 @@
             self.assertEqual(
                 e,
                 tname,
-                "expression name mismatch, expected {} got {}".format(e, tname),
+                f"expression name mismatch, expected {e} got {tname}",
             )
 
     def testTrimArityExceptionMasking(self):
-
         invalid_message = "<lambda>() missing 1 required positional argument: 't'"
         try:
-            pp.Word("a").setParseAction(lambda t: t0 + 1).parseString("aaa")
+            pp.Word("a").setParseAction(lambda t: t0 + 1).parseString(
+                "aaa", parseAll=True
+            )
         except Exception as e:
             exc_msg = str(e)
             self.assertNotEqual(
@@ -5654,7 +6202,9 @@
 
             invalid_message = "<lambda>() missing 1 required positional argument: 't'"
             try:
-                pp.Word("a").setParseAction(lambda t: t0 + 1).parseString("aaa")
+                pp.Word("a").setParseAction(lambda t: t0 + 1).parseString(
+                    "aaa", parseAll=True
+                )
             except Exception as e:
                 exc_msg = str(e)
                 self.assertNotEqual(
@@ -5693,30 +6243,30 @@
         K()
 
     def testClearParseActions(self):
-
         realnum = ppc.real()
         self.assertEqual(
             3.14159,
-            realnum.parseString("3.14159")0,
+            realnum.parseString("3.14159", parseAll=True)0,
             "failed basic real number parsing",
         )
 
         # clear parse action that converts to float
         realnum.setParseAction(None)
         self.assertEqual(
-            "3.14159", realnum.parseString("3.14159")0, "failed clearing parse action"
+            "3.14159",
+            realnum.parseString("3.14159", parseAll=True)0,
+            "failed clearing parse action",
         )
 
         # add a new parse action that tests if a '.' is prsent
         realnum.addParseAction(lambda t: "." in t0)
         self.assertEqual(
             True,
-            realnum.parseString("3.14159")0,
+            realnum.parseString("3.14159", parseAll=True)0,
             "failed setting new parse action after clearing parse action",
         )
 
     def testOneOrMoreStop(self):
-
         test = "BEGIN aaa bbb ccc END"
         BEGIN, END = map(pp.Keyword, "BEGIN,END".split(","))
         body_word = pp.Word(pp.alphas).setName("word")
@@ -5726,9 +6276,28 @@
                 expr, test, "Did not successfully stop on ending expression %r" % ender
             )
 
-            expr = BEGIN + body_word....stopOn(ender) + END
-            self.assertEqual(
-                expr, test, "Did not successfully stop on ending expression %r" % ender
+            expr = BEGIN + body_word1, ....stopOn(ender) + END
+            self.assertParseAndCheckList(
+                expr,
+                test,
+                test.split(),
+                "Did not successfully stop on ending expression %r" % ender,
+            )
+
+            expr = BEGIN + body_word1, ...:ender + END
+            self.assertParseAndCheckList(
+                expr,
+                test,
+                test.split(),
+                "Did not successfully stop on ending expression %r" % ender,
+            )
+
+            expr = BEGIN + body_word(1, ...):ender + END
+            self.assertParseAndCheckList(
+                expr,
+                test,
+                test.split(),
+                "Did not successfully stop on ending expression %r" % ender,
             )
 
         number = pp.Word(pp.nums + ",.()").setName("number with optional commas")
@@ -5749,17 +6318,38 @@
         body_word = pp.Word(pp.alphas).setName("word")
         for ender in (END, "END", pp.CaselessKeyword("END")):
             expr = BEGIN + pp.ZeroOrMore(body_word, stopOn=ender) + END
-            self.assertEqual(
-                expr, test, "Did not successfully stop on ending expression %r" % ender
+            self.assertParseAndCheckList(
+                expr,
+                test,
+                test.split(),
+                "Did not successfully stop on ending expression %r" % ender,
             )
 
-            expr = BEGIN + body_word0, ....stopOn(ender) + END
-            self.assertEqual(
-                expr, test, "Did not successfully stop on ending expression %r" % ender
+            expr = BEGIN + body_word....stopOn(ender) + END
+            self.assertParseAndCheckList(
+                expr,
+                test,
+                test.split(),
+                "Did not successfully stop on ending expression %r" % ender,
             )
 
-    def testNestedAsDict(self):
+            expr = BEGIN + body_word...:ender + END
+            self.assertParseAndCheckList(
+                expr,
+                test,
+                test.split(),
+                "Did not successfully stop on ending expression %r" % ender,
+            )
+
+            expr = BEGIN + body_word:ender + END
+            self.assertParseAndCheckList(
+                expr,
+                test,
+                test.split(),
+                "Did not successfully stop on ending expression %r" % ender,
+            )
 
+    def testNestedAsDict(self):
         equals = pp.Literal("=").suppress()
         lbracket = pp.Literal("").suppress()
         rbracket = pp.Literal("").suppress()
@@ -5787,7 +6377,7 @@
         rsp = (
             "username=goat; errors={username=already taken, too short}; empty_field="
         )
-        result_dict = response.parseString(rsp).asDict()
+        result_dict = response.parseString(rsp, parseAll=True).asDict()
         print(result_dict)
         self.assertEqual(
             "goat",
@@ -5812,7 +6402,7 @@
         integer = pp.Word(pp.nums).addParseAction(convert_to_int)
         integer.addParseAction(pp.traceParseAction(lambda t: t0 * 10))
         integer.addParseAction(pp.traceParseAction(Z()))
-        integer.parseString("132")
+        integer.parseString("132", parseAll=True)
 
     def testRunTests(self):
         integer = pp.Word(pp.nums).setParseAction(lambda t: int(t0))
@@ -5856,7 +6446,7 @@
 
         def eval_fraction(test, result):
             accum.append((test, result.asList()))
-            return "eval: {}".format(result.numerator / result.denominator)
+            return f"eval: {result.numerator / result.denominator}"
 
         success = fraction.runTests(
             """\
@@ -5881,7 +6471,7 @@
         expr.addParseAction(ppc.convertToDate())
 
         with self.assertRaisesParseException():
-            expr.parseString("1997-07-error")
+            expr.parseString("1997-07-error", parseAll=True)
 
     def testConvertToDatetimeErr(self):
         """raise a ParseException in convertToDatetime with incompatible datetime str"""
@@ -5890,232 +6480,249 @@
         expr.addParseAction(ppc.convertToDatetime())
 
         with self.assertRaisesParseException():
-            expr.parseString("1997-07-error")
+            expr.parseString("1997-07-error", parseAll=True)
 
     def testCommonExpressions(self):
         import ast
 
-        success = ppc.mac_address.runTests(
-            """
-            AA:BB:CC:DD:EE:FF
-            AA.BB.CC.DD.EE.FF
-            AA-BB-CC-DD-EE-FF
-            """
-        )0
-        self.assertTrue(success, "error in parsing valid MAC address")
-
-        success = ppc.mac_address.runTests(
-            """
-            # mixed delimiters
-            AA.BB:CC:DD:EE:FF
-            """,
-            failureTests=True,
-        )0
-        self.assertTrue(success, "error in detecting invalid mac address")
-
-        success = ppc.ipv4_address.runTests(
-            """
-            0.0.0.0
-            1.1.1.1
-            127.0.0.1
-            1.10.100.199
-            255.255.255.255
-            """
-        )0
-        self.assertTrue(success, "error in parsing valid IPv4 address")
-
-        success = ppc.ipv4_address.runTests(
-            """
-            # out of range value
-            256.255.255.255
-            """,
-            failureTests=True,
-        )0
-        self.assertTrue(success, "error in detecting invalid IPv4 address")
-
-        success = ppc.ipv6_address.runTests(
-            """
-            2001:0db8:85a3:0000:0000:8a2e:0370:7334
-            2134::1234:4567:2468:1236:2444:2106
-            0:0:0:0:0:0:A00:1
-            1080::8:800:200C:417A
-            ::A00:1
+        with self.subTest("MAC address success run_tests"):
+            success = ppc.mac_address.runTests(
+                """
+                AA:BB:CC:DD:EE:FF
+                AA.BB.CC.DD.EE.FF
+                AA-BB-CC-DD-EE-FF
+                """
+            )0
+            self.assertTrue(success, "error in parsing valid MAC address")
 
-            # loopback address
-            ::1
+        with self.subTest("MAC address expected failure run_tests"):
+            success = ppc.mac_address.runTests(
+                """
+                # mixed delimiters
+                AA.BB:CC:DD:EE:FF
+                """,
+                failureTests=True,
+            )0
+            self.assertTrue(success, "error in detecting invalid mac address")
 
-            # the null address
-            ::
+        with self.subTest("IPv4 address success run_tests"):
+            success = ppc.ipv4_address.runTests(
+                """
+                0.0.0.0
+                1.1.1.1
+                127.0.0.1
+                1.10.100.199
+                255.255.255.255
+                """
+            )0
+            self.assertTrue(success, "error in parsing valid IPv4 address")
 
-            # ipv4 compatibility form
-            ::ffff:192.168.0.1
-            """
-        )0
-        self.assertTrue(success, "error in parsing valid IPv6 address")
+        with self.subTest("IPv4 address expected failure run_tests"):
+            success = ppc.ipv4_address.runTests(
+                """
+                # out of range value
+                256.255.255.255
+                """,
+                failureTests=True,
+            )0
+            self.assertTrue(success, "error in detecting invalid IPv4 address")
 
-        success = ppc.ipv6_address.runTests(
-            """
-            # too few values
-            1080:0:0:0:8:800:200C
+        with self.subTest("IPv6 address success run_tests"):
+            success = ppc.ipv6_address.runTests(
+                """
+                2001:0db8:85a3:0000:0000:8a2e:0370:7334
+                2134::1234:4567:2468:1236:2444:2106
+                0:0:0:0:0:0:A00:1
+                1080::8:800:200C:417A
+                ::A00:1
+    
+                # loopback address
+                ::1
+    
+                # the null address
+                ::
+    
+                # ipv4 compatibility form
+                ::ffff:192.168.0.1
+                """
+            )0
+            self.assertTrue(success, "error in parsing valid IPv6 address")
 
-            # too many ::'s, only 1 allowed
-            2134::1234:4567::2444:2106
-            """,
-            failureTests=True,
-        )0
-        self.assertTrue(success, "error in detecting invalid IPv6 address")
+        with self.subTest("IPv6 address expected failure run_tests"):
+            success = ppc.ipv6_address.runTests(
+                """
+                # too few values
+                1080:0:0:0:8:800:200C
+    
+                # too many ::'s, only 1 allowed
+                2134::1234:4567::2444:2106
+                """,
+                failureTests=True,
+            )0
+            self.assertTrue(success, "error in detecting invalid IPv6 address")
 
-        success = ppc.number.runTests(
-            """
-            100
-            -100
-            +100
-            3.14159
-            6.02e23
-            1e-12
-            """
-        )0
-        self.assertTrue(success, "error in parsing valid numerics")
+        with self.subTest("ppc.number success run_tests"):
+            success = ppc.number.runTests(
+                """
+                100
+                -100
+                +100
+                3.14159
+                6.02e23
+                1e-12
+                """
+            )0
+            self.assertTrue(success, "error in parsing valid numerics")
 
-        success = ppc.sci_real.runTests(
-            """
-            1e12
-            -1e12
-            3.14159
-            6.02e23
-            """
-        )0
-        self.assertTrue(success, "error in parsing valid scientific notation reals")
+        with self.subTest("ppc.sci_real success run_tests"):
+            success = ppc.sci_real.runTests(
+                """
+                1e12
+                -1e12
+                3.14159
+                6.02e23
+                """
+            )0
+            self.assertTrue(success, "error in parsing valid scientific notation reals")
 
         # any int or real number, returned as float
-        success = ppc.fnumber.runTests(
-            """
-            100
-            -100
-            +100
-            3.14159
-            6.02e23
-            1e-12
-            """
-        )0
-        self.assertTrue(success, "error in parsing valid numerics")
+        with self.subTest("ppc.fnumber success run_tests"):
+            success = ppc.fnumber.runTests(
+                """
+                100
+                -100
+                +100
+                3.14159
+                6.02e23
+                1e-12
+                """
+            )0
+            self.assertTrue(success, "error in parsing valid numerics")
 
-        success, results = ppc.iso8601_date.runTests(
-            """
-            1997
-            1997-07
-            1997-07-16
-            """
-        )
-        self.assertTrue(success, "error in parsing valid iso8601_date")
-        expected = ("1997", None, None), ("1997", "07", None), ("1997", "07", "16")
-        for r, exp in zip(results, expected):
-            self.assertEqual(
-                exp,
-                (r1.year, r1.month, r1.day),
-                "failed to parse date into fields",
+        with self.subTest("ppc.iso8601_date success run_tests"):
+            success, results = ppc.iso8601_date.runTests(
+                """
+                1997
+                1997-07
+                1997-07-16
+                """
             )
+            self.assertTrue(success, "error in parsing valid iso8601_date")
+            expected = 
+                ("1997", None, None),
+                ("1997", "07", None),
+                ("1997", "07", "16"),
+            
+            for r, exp in zip(results, expected):
+                self.assertEqual(
+                    exp,
+                    (r1.year, r1.month, r1.day),
+                    "failed to parse date into fields",
+                )
 
-        success, results = (
-            ppc.iso8601_date()
-            .addParseAction(ppc.convertToDate())
-            .runTests(
+        with self.subTest("ppc.iso8601_date conversion success run_tests"):
+            success, results = (
+                ppc.iso8601_date()
+                .addParseAction(ppc.convertToDate())
+                .runTests(
+                    """
+                1997-07-16
                 """
-            1997-07-16
-            """
+                )
+            )
+            self.assertTrue(
+                success, "error in parsing valid iso8601_date with parse action"
+            )
+            self.assertEqual(
+                datetime.date(1997, 7, 16),
+                results010,
+                "error in parsing valid iso8601_date with parse action - incorrect value",
             )
-        )
-        self.assertTrue(
-            success, "error in parsing valid iso8601_date with parse action"
-        )
-        self.assertEqual(
-            datetime.date(1997, 7, 16),
-            results010,
-            "error in parsing valid iso8601_date with parse action - incorrect value",
-        )
-
-        success, results = ppc.iso8601_datetime.runTests(
-            """
-            1997-07-16T19:20+01:00
-            1997-07-16T19:20:30+01:00
-            1997-07-16T19:20:30.45Z
-            1997-07-16 19:20:30.45
-            """
-        )
-        self.assertTrue(success, "error in parsing valid iso8601_datetime")
 
-        success, results = (
-            ppc.iso8601_datetime()
-            .addParseAction(ppc.convertToDatetime())
-            .runTests(
+        with self.subTest("ppc.iso8601_datetime success run_tests"):
+            success, results = ppc.iso8601_datetime.runTests(
+                """
+                1997-07-16T19:20+01:00
+                1997-07-16T19:20:30+01:00
+                1997-07-16T19:20:30.45Z
+                1997-07-16 19:20:30.45
                 """
-            1997-07-16T19:20:30.45
-            """
             )
-        )
+            self.assertTrue(success, "error in parsing valid iso8601_datetime")
 
-        self.assertTrue(success, "error in parsing valid iso8601_datetime")
-        self.assertEqual(
-            datetime.datetime(1997, 7, 16, 19, 20, 30, 450000),
-            results010,
-            "error in parsing valid iso8601_datetime - incorrect value",
-        )
+        with self.subTest("ppc.iso8601_datetime conversion success run_tests"):
+            success, results = (
+                ppc.iso8601_datetime()
+                .addParseAction(ppc.convertToDatetime())
+                .runTests(
+                    """
+                1997-07-16T19:20:30.45
+                """
+                )
+            )
 
-        success = ppc.uuid.runTests(
-            """
-            123e4567-e89b-12d3-a456-426655440000
-            """
-        )0
-        self.assertTrue(success, "failed to parse valid uuid")
+            self.assertTrue(success, "error in parsing valid iso8601_datetime")
+            self.assertEqual(
+                datetime.datetime(1997, 7, 16, 19, 20, 30, 450000),
+                results010,
+                "error in parsing valid iso8601_datetime - incorrect value",
+            )
 
-        success = ppc.fraction.runTests(
-            """
-            1/2
-            -15/16
-            -3/-4
-            """
-        )0
-        self.assertTrue(success, "failed to parse valid fraction")
+        with self.subTest("ppc.uuid success run_tests"):
+            success = ppc.uuid.runTests(
+                """
+                123e4567-e89b-12d3-a456-426655440000
+                """
+            )0
+            self.assertTrue(success, "failed to parse valid uuid")
 
-        success = ppc.mixed_integer.runTests(
-            """
-            1/2
-            -15/16
-            -3/-4
-            1 1/2
-            2 -15/16
-            0 -3/-4
-            12
-            """
-        )0
-        self.assertTrue(success, "failed to parse valid mixed integer")
+        with self.subTest("ppc.fraction success run_tests"):
+            success = ppc.fraction.runTests(
+                """
+                1/2
+                -15/16
+                -3/-4
+                """
+            )0
+            self.assertTrue(success, "failed to parse valid fraction")
 
-        success, results = ppc.number.runTests(
-            """
-            100
-            -3
-            1.732
-            -3.14159
-            6.02e23"""
-        )
-        self.assertTrue(success, "failed to parse numerics")
+        with self.subTest("ppc.mixed_integer success run_tests"):
+            success = ppc.mixed_integer.runTests(
+                """
+                1/2
+                -15/16
+                -3/-4
+                1 1/2
+                2 -15/16
+                0 -3/-4
+                12
+                """
+            )0
+            self.assertTrue(success, "failed to parse valid mixed integer")
 
-        for test, result in results:
-            expected = ast.literal_eval(test)
-            self.assertEqual(
-                expected,
-                result0,
-                "numeric parse failed (wrong value) ({} should be {})".format(
-                    result0, expected
-                ),
-            )
-            self.assertEqual(
-                type(expected),
-                type(result0),
-                "numeric parse failed (wrong type) ({} should be {})".format(
-                    type(result0), type(expected)
-                ),
+        with self.subTest("ppc.number success run_tests"):
+            success, results = ppc.number.runTests(
+                """
+                100
+                -3
+                1.732
+                -3.14159
+                6.02e23"""
             )
+            self.assertTrue(success, "failed to parse numerics")
+
+            for test, result in results:
+                expected = ast.literal_eval(test)
+                self.assertEqual(
+                    expected,
+                    result0,
+                    f"numeric parse failed (wrong value) ({result0} should be {expected})",
+                )
+                self.assertEqual(
+                    type(expected),
+                    type(result0),
+                    f"numeric parse failed (wrong type) ({type(result0)} should be {type(expected)})",
+                )
 
     def testCommonUrl(self):
         url_good_tests = """\
@@ -6205,18 +6812,34 @@
         parts = urlparse(sample_url)
         expected = {
             "scheme": parts.scheme,
-            "auth": "{}:{}".format(parts.username, parts.password),
+            "auth": f"{parts.username}:{parts.password}",
             "host": parts.hostname,
             "port": str(parts.port),
             "path": parts.path,
             "query": parts.query,
             "fragment": parts.fragment,
+            "url": sample_url,
         }
 
         self.assertParseAndCheckDict(ppc.url, sample_url, expected, verbose=True)
 
-    def testNumericExpressions(self):
+    def testCommonUrlExprs(self):
+        def extract_parts(s, split=" "):
+            return _.strip(split) for _ in s.strip(split).split(split)
+
+        test_string = "http://example.com https://blah.org "
+        self.assertParseAndCheckList(
+            pp.Group(ppc.url)..., test_string, extract_parts(test_string)
+        )
+
+        test_string = test_string.replace(" ", " , ")
+        self.assertParseAndCheckList(
+            pp.delimited_list(pp.Group(ppc.url), allow_trailing_delim=True),
+            test_string,
+            extract_parts(test_string, " , "),
+        )
 
+    def testNumericExpressions(self):
         # disable parse actions that do type conversion so we don't accidentally trigger
         # conversion exceptions when what we want to check is the parsing expression
         real = ppc.real().setParseAction(None)
@@ -6332,14 +6955,13 @@
             print(
                 expr,
                 ("FAIL", "PASS")success,
-                "{}valid tests ({})".format("in" if is_fail else "", len(tests)),
+                f"{'in' if is_fail else ''}valid tests ({len(tests)})",
             )
             all_pass = all_pass and success
 
         self.assertTrue(all_pass, "failed one or more numeric tests")
 
     def testTokenMap(self):
-
         parser = pp.OneOrMore(pp.Word(pp.hexnums)).setParseAction(pp.tokenMap(int, 16))
         success, report = parser.runTests(
             """
@@ -6354,21 +6976,32 @@
         )
 
     def testParseFile(self):
-
         s = """
         123 456 789
         """
-        input_file = StringIO(s)
-        integer = ppc.integer
+        from pathlib import Path
 
-        results = pp.OneOrMore(integer).parseFile(input_file)
-        print(results)
+        integer = ppc.integer
+        test_parser = integer1, ...
 
-        results = pp.OneOrMore(integer).parseFile("tests/parsefiletest_input_file.txt")
-        print(results)
+        input_file_as_stringio = StringIO(s)
+        input_file_as_str = "tests/parsefiletest_input_file.txt"
+        input_file_as_path = Path(input_file_as_str)
+
+        expected_list = int(i) for i in s.split()
+
+        for input_file in (
+            input_file_as_stringio,
+            input_file_as_str,
+            input_file_as_path,
+        ):
+            with self.subTest(input_file=input_file):
+                print(f"parse_file() called with {type(input_file).__name__}")
+                results = test_parser.parseFile(input_file)
+                print(results)
+                self.assertEqual(expected_list, results.as_list())
 
     def testHTMLStripper(self):
-
         sample = """
         <html>
         Here is some sample <i>HTML</i> text.
@@ -6377,11 +7010,10 @@
         read_everything = pp.originalTextFor(pp.OneOrMore(pp.Word(pp.printables)))
         read_everything.addParseAction(ppc.stripHTMLTags)
 
-        result = read_everything.parseString(sample)
+        result = read_everything.parseString(sample, parseAll=True)
         self.assertEqual("Here is some sample HTML text.", result0.strip())
 
     def testExprSplitter(self):
-
         expr = pp.Literal(";") + pp.Empty()
         expr.ignore(pp.quotedString)
         expr.ignore(pp.pythonStyleComment)
@@ -6512,26 +7144,11 @@
                 self.fail("invalid split on expression with maxSplits=1, corner case")
 
     def testParseFatalException(self):
-
         with self.assertRaisesParseException(
             exc_type=ParseFatalException, msg="failed to raise ErrorStop exception"
         ):
             expr = "ZZZ" - pp.Word(pp.nums)
-            expr.parseString("ZZZ bad")
-
-        # WAS:
-        # success = False
-        # try:
-        #     expr = "ZZZ" - Word(nums)
-        #     expr.parseString("ZZZ bad")
-        # except ParseFatalException as pfe:
-        #     print('ParseFatalException raised correctly')
-        #     success = True
-        # except Exception as e:
-        #     print(type(e))
-        #     print(e)
-        #
-        # self.assertTrue(success, "bad handling of syntax error")
+            expr.parseString("ZZZ bad", parseAll=True)
 
     def testParseFatalException2(self):
         # Fatal exception raised in MatchFirst should not be superseded later non-fatal exceptions
@@ -6548,7 +7165,7 @@
         )
 
         with self.assertRaisesParseException(pp.ParseFatalException):
-            test.parseString("1s")
+            test.parseString("1s", parseAll=True)
 
     def testParseFatalException3(self):
         # Fatal exception raised in MatchFirst should not be superseded later non-fatal exceptions
@@ -6560,18 +7177,21 @@
         )
 
         with self.assertRaisesParseException(pp.ParseFatalException):
-            test.parseString("1")
+            test.parseString("1", parseAll=True)
 
     def testInlineLiteralsUsing(self):
-
         wd = pp.Word(pp.alphas)
 
         pp.ParserElement.inlineLiteralsUsing(pp.Suppress)
-        result = (wd + "," + wd + pp.oneOf("! . ?")).parseString("Hello, World!")
+        result = (wd + "," + wd + pp.oneOf("! . ?")).parseString(
+            "Hello, World!", parseAll=True
+        )
         self.assertEqual(3, len(result), "inlineLiteralsUsing(Suppress) failed!")
 
         pp.ParserElement.inlineLiteralsUsing(pp.Literal)
-        result = (wd + "," + wd + pp.oneOf("! . ?")).parseString("Hello, World!")
+        result = (wd + "," + wd + pp.oneOf("! . ?")).parseString(
+            "Hello, World!", parseAll=True
+        )
         self.assertEqual(4, len(result), "inlineLiteralsUsing(Literal) failed!")
 
         pp.ParserElement.inlineLiteralsUsing(pp.CaselessKeyword)
@@ -6616,7 +7236,6 @@
         )
 
     def testCloseMatch(self):
-
         searchseq = pp.CloseMatch("ATCATCGAATGGA", 2)
 
         _, results = searchseq.runTests(
@@ -6636,9 +7255,7 @@
                 self.assertEqual(
                     exp,
                     r1.mismatches,
-                    "fail CloseMatch between {!r} and {!r}".format(
-                        searchseq.match_string, r0
-                    ),
+                    f"fail CloseMatch between {searchseq.match_string!r} and {r0!r}",
                 )
             print(
                 r0,
@@ -6648,7 +7265,6 @@
             )
 
     def testCloseMatchCaseless(self):
-
         searchseq = pp.CloseMatch("ATCATCGAATGGA", 2, caseless=True)
 
         _, results = searchseq.runTests(
@@ -6668,9 +7284,7 @@
                 self.assertEqual(
                     exp,
                     r1.mismatches,
-                    "fail CaselessCloseMatch between {!r} and {!r}".format(
-                        searchseq.match_string, r0
-                    ),
+                    f"fail CaselessCloseMatch between {searchseq.match_string!r} and {r0!r}",
                 )
             print(
                 r0,
@@ -6680,38 +7294,41 @@
             )
 
     def testDefaultKeywordChars(self):
-
         with self.assertRaisesParseException(
             msg="failed to fail matching keyword using updated keyword chars"
         ):
-            pp.Keyword("start").parseString("start1000")
+            pp.Keyword("start").parseString("start1000", parseAll=True)
 
         try:
-            pp.Keyword("start", identChars=pp.alphas).parseString("start1000")
+            pp.Keyword("start", identChars=pp.alphas).parseString(
+                "start1000", parseAll=False
+            )
         except pp.ParseException:
             self.fail("failed to match keyword using updated keyword chars")
 
         with ppt.reset_pyparsing_context():
             pp.Keyword.setDefaultKeywordChars(pp.alphas)
             try:
-                pp.Keyword("start").parseString("start1000")
+                pp.Keyword("start").parseString("start1000", parseAll=False)
             except pp.ParseException:
                 self.fail("failed to match keyword using updated keyword chars")
 
         with self.assertRaisesParseException(
             msg="failed to fail matching keyword using updated keyword chars"
         ):
-            pp.CaselessKeyword("START").parseString("start1000")
+            pp.CaselessKeyword("START").parseString("start1000", parseAll=False)
 
         try:
-            pp.CaselessKeyword("START", identChars=pp.alphas).parseString("start1000")
+            pp.CaselessKeyword("START", identChars=pp.alphas).parseString(
+                "start1000", parseAll=False
+            )
         except pp.ParseException:
             self.fail("failed to match keyword using updated keyword chars")
 
         with ppt.reset_pyparsing_context():
             pp.Keyword.setDefaultKeywordChars(pp.alphas)
             try:
-                pp.CaselessKeyword("START").parseString("start1000")
+                pp.CaselessKeyword("START").parseString("start1000", parseAll=False)
             except pp.ParseException:
                 self.assertTrue(
                     False, "failed to match keyword using updated keyword chars"
@@ -6722,8 +7339,14 @@
         b_keyword = a_keyword.copy()
         self.assertEqual(a_keyword.identChars, b_keyword.identChars)
 
-    def testLiteralVsKeyword(self):
+    def testCopyLiteralAttrs(self):
+        lit = pp.Literal("foo").leave_whitespace()
+        lit2 = lit.copy()
+        self.assertFalse(lit2.skipWhitespace)
+        lit3 = lit2.ignore_whitespace().copy()
+        self.assertTrue(lit3.skipWhitespace)
 
+    def testLiteralVsKeyword(self):
         integer = ppc.integer
         literal_expr = integer + pp.Literal("start") + integer
         keyword_expr = integer + pp.Keyword("start") + integer
@@ -6784,7 +7407,6 @@
             print(word_keyword_expr.parseString(test_string, parseAll=True))
 
     def testCol(self):
-
         test = "*\n* \n*   ALF\n*\n"
         initials = c for i, c in enumerate(test) if pp.col(i, test) == 1
         print(initials)
@@ -6793,7 +7415,6 @@
         )
 
     def testLiteralException(self):
-
         for cls in (
             pp.Literal,
             pp.CaselessLiteral,
@@ -6805,14 +7426,12 @@
             expr = cls("xyz")  # .setName('{}_expr'.format(cls.__name__.lower()))
 
             try:
-                expr.parseString(" ")
+                expr.parseString(" ", parseAll=True)
             except Exception as e:
                 print(cls.__name__, str(e))
                 self.assertTrue(
                     isinstance(e, pp.ParseBaseException),
-                    "class {} raised wrong exception type {}".format(
-                        cls.__name__, type(e).__name__
-                    ),
+                    f"class {cls.__name__} raised wrong exception type {type(e).__name__}",
                 )
 
     def testParseActionException(self):
@@ -6828,7 +7447,7 @@
         expr = number | symbol
 
         try:
-            expr.parseString("1 + 2")
+            expr.parseString("1 + 2", parseAll=True)
         except Exception as e:
             print_traceback = True
             try:
@@ -6854,7 +7473,6 @@
 
     # tests Issue #22
     def testParseActionNesting(self):
-
         vals = pp.OneOrMore(ppc.integer)("int_values")
 
         def add_total(tokens):
@@ -6862,7 +7480,7 @@
             return tokens
 
         vals.addParseAction(add_total)
-        results = vals.parseString("244 23 13 2343")
+        results = vals.parseString("244 23 13 2343", parseAll=True)
         print(results.dump())
         self.assertParseResultsEquals(
             results,
@@ -6875,7 +7493,7 @@
         nameScore = pp.Group(name + score)
         line1 = nameScore("Rider")
 
-        result1 = line1.parseString("Mauney 46.5")
+        result1 = line1.parseString("Mauney 46.5", parseAll=True)
 
         print("### before parse action is added ###")
         print("result1.dump():\n" + result1.dump() + "\n")
@@ -6883,7 +7501,7 @@
 
         line1.setParseAction(lambda t: t)
 
-        result1 = line1.parseString("Mauney 46.5")
+        result1 = line1.parseString("Mauney 46.5", parseAll=True)
         after_pa_dict = result1.asDict()
 
         print("### after parse action was added ###")
@@ -6940,8 +7558,29 @@
 
         self.assertParseAndCheckList(named_number_list, test_string, expected)
 
-    def testParseResultsNameBelowUngroupedName(self):
+    def testParseActionRunsInNotAny(self):
+        # see Issue #482
+        data = """ gog1 G1 gog2 gog3 gog4 G2 gog5 G3 gog6 """
+
+        poi_type = pp.Word(pp.alphas).set_results_name("type")
+        poi = pp.Suppress("") + poi_type + pp.Char(pp.nums) + pp.Suppress("")
+
+        def cnd_is_type(val):
+            return lambda toks: toks.type == val
+
+        poi_gog = poi("gog").add_condition(cnd_is_type("gog"))
+        poi_g = poi("g").add_condition(cnd_is_type("G"))
+
+        pattern = poi_gog + ~poi_g
 
+        matches = pattern.search_string(data).as_list()
+        self.assertEqual(
+            "gog", "2", "gog", "3", "gog", "6",
+            matches,
+            "failed testing parse actions being run inside a NotAny",
+        )
+
+    def testParseResultsNameBelowUngroupedName(self):
         rule_num = pp.Regex("0-9+")("LIT_NUM*")
         list_num = pp.Group(
             pp.Literal("")("START_LIST")
@@ -6952,14 +7591,13 @@
         test_string = " 1,2,3,4,5,6 "
         list_num.runTests(test_string)
 
-        U = list_num.parseString(test_string)
+        U = list_num.parseString(test_string, parseAll=True)
         self.assertTrue(
             "LIT_NUM" not in U.LIST.LIST_VALUES,
             "results name retained as sub in ungrouped named result",
         )
 
     def testParseResultsNamesInGroupWithDict(self):
-
         key = ppc.identifier()
         value = ppc.integer()
         lat = ppc.real()
@@ -6977,7 +7615,7 @@
         site.runTests(test_string)
 
         a, aEnd = pp.makeHTMLTags("a")
-        attrs = a.parseString("<a href='blah'>")
+        attrs = a.parseString("<a href='blah'>", parseAll=True)
         print(attrs.dump())
         self.assertParseResultsEquals(
             attrs,
@@ -6995,14 +7633,13 @@
         body, bodyEnd = pp.makeXMLTags("body")
         tst = "<body>Hello</body>"
         expr = body + pp.Word(pp.alphas)("contents") + bodyEnd
-        result = expr.parseString(tst)
+        result = expr.parseString(tst, parseAll=True)
         print(result.dump())
         self.assertParseResultsEquals(
             result, "body", False, "Hello", "</body>", msg="issue using makeXMLTags"
         )
 
     def testFollowedBy(self):
-
         expr = pp.Word(pp.alphas)("item") + pp.FollowedBy(ppc.integer("qty"))
         result = expr.parseString("balloon 99", parseAll=False)
         print(result.dump())
@@ -7033,13 +7670,12 @@
 
         with ppt.reset_pyparsing_context():
             pdb.set_trace = mock_set_trace
-            wd.parseString("ABC")
+            wd.parseString("ABC", parseAll=True)
 
         print("After parsing with setBreak:", was_called)
         self.assertTrue(was_called, "set_trace wasn't called by setBreak")
 
     def testUnicodeTests(self):
-
         ppu = pp.pyparsing_unicode
 
         # verify proper merging of ranges by addition
@@ -7079,7 +7715,7 @@
 
         # input string
         hello = "Καλημέρα, κόσμε!"
-        result = greet.parseString(hello)
+        result = greet.parseString(hello, parseAll=True)
         print(result)
         self.assertParseResultsEquals(
             result,
@@ -7119,7 +7755,9 @@
             şehir=İzmir
             ülke=Türkiye
             nüfus=4279677"""
-        result = pp.Dict(pp.OneOrMore(pp.Group(key_value))).parseString(sample)
+        result = pp.Dict(pp.OneOrMore(pp.Group(key_value))).parseString(
+            sample, parseAll=True
+        )
 
         print(result.dump())
         self.assertParseResultsEquals(
@@ -7158,7 +7796,6 @@
 
     # Make sure example in indentedBlock docstring actually works!
     def testIndentedBlockExample(self):
-
         data = dedent(
             """
         def A(z):
@@ -7274,7 +7911,7 @@
         text = dedent(text)
         print(text)
 
-        result = parser.parseString(text)
+        result = parser.parseString(text, parseAll=True)
         print(result.dump())
         self.assertEqual(100, result.a, "invalid indented block result")
         self.assertEqual(200, result.c.c1, "invalid indented block result")
@@ -7282,7 +7919,6 @@
 
     # exercise indentedBlock with example posted in issue #87
     def testIndentedBlockTest2(self):
-
         indent_stack = 1
 
         key = pp.Word(pp.alphas, pp.alphanums) + pp.Suppress(":")
@@ -7500,7 +8136,7 @@
         integer = ppc.integer
         group = pp.Group(pp.Char(pp.alphas) + pp.IndentedBlock(integer))
 
-        group....parseString(data).pprint()
+        group....parseString(data, parseAll=True).pprint()
 
         self.assertParseAndCheckList(
             group..., data, "A", 100, 101, 102, "B", 200, 201, "C", 300
@@ -7580,7 +8216,7 @@
         )
 
         print("using parseString")
-        print(group....parseString(data).dump())
+        print(group....parseString(data, parseAll=True).dump())
 
         dotted_int = pp.delimited_list(
             pp.Word(pp.nums), ".", allow_trailing_delim=True, combine=True
@@ -7698,11 +8334,11 @@
             the bird
         """
         )
-        result = expr.parseString("not the bird")
+        result = expr.parseString("not the bird", parseAll=True)
         self.assertParseResultsEquals(
             result, "not", "the", "bird", {"rexp": "not", "the", "bird"}
         )
-        result = expr.parseString("the bird")
+        result = expr.parseString("the bird", parseAll=True)
         self.assertParseResultsEquals(
             result, "the", "bird", {"rexp": "the", "bird"}
         )
@@ -7714,11 +8350,11 @@
             the bird
         """
         )
-        result = expr.parseString("not the bird")
+        result = expr.parseString("not the bird", parseAll=True)
         self.assertParseResultsEquals(
             result, "not", "the", "bird", {"rexp": "not", "the", "bird"}
         )
-        result = expr.parseString("the bird")
+        result = expr.parseString("the bird", parseAll=True)
         self.assertParseResultsEquals(
             result, "the", "bird", {"rexp": "the", "bird"}
         )
@@ -7750,10 +8386,12 @@
             """
             )
             self.assertEqual(
-                "not the bird".split(), list(expr.parseString("not the bird")"rexp")
+                "not the bird".split(),
+                list(expr.parseString("not the bird", parseAll=True)"rexp"),
             )
             self.assertEqual(
-                "the bird".split(), list(expr.parseString("the bird")"rexp")
+                "the bird".split(),
+                list(expr.parseString("the bird", parseAll=True)"rexp"),
             )
 
     def testEmptyDictDoesNotRaiseException(self):
@@ -7767,12 +8405,13 @@
                 """\
             a = 10
             b = 20
-            """
+            """,
+                parseAll=True,
             ).dump()
         )
 
         try:
-            print(key_value_dict.parseString("").dump())
+            print(key_value_dict.parseString("", parseAll=True).dump())
         except pp.ParseException as pe:
             print(pp.ParseException.explain(pe))
         else:
@@ -7781,13 +8420,13 @@
     def testExplainException(self):
         expr = pp.Word(pp.nums).setName("int") + pp.Word(pp.alphas).setName("word")
         try:
-            expr.parseString("123 355")
+            expr.parseString("123 355", parseAll=True)
         except pp.ParseException as pe:
             print(pe.explain(depth=0))
 
         expr = pp.Word(pp.nums).setName("int") - pp.Word(pp.alphas).setName("word")
         try:
-            expr.parseString("123 355 (test using ErrorStop)")
+            expr.parseString("123 355 (test using ErrorStop)", parseAll=True)
         except pp.ParseSyntaxException as pe:
             print(pe.explain())
 
@@ -7795,12 +8434,12 @@
         expr = integer + integer
 
         def divide_args(t):
-            integer.parseString("A")
+            integer.parseString("A", parseAll=True)
             return t0 / t1
 
         expr.addParseAction(divide_args)
         try:
-            expr.parseString("123 0")
+            expr.parseString("123 0", parseAll=True)
         except pp.ParseException as pe:
             print(pe.explain())
         except Exception as exc:
@@ -7818,7 +8457,7 @@
         expr = integer + integer
 
         def divide_args(t):
-            integer.parseString("A")
+            integer.parseString("A", parseAll=True)
             return t0 / t1
 
         expr.addParseAction(divide_args)
@@ -7830,7 +8469,7 @@
             print("Explain for", memo_kind)
 
             try:
-                expr.parseString("123 0")
+                expr.parseString("123 0", parseAll=True)
             except pp.ParseException as pe:
                 print(pe.explain())
             except Exception as exc:
@@ -7892,9 +8531,7 @@
           have results names (default=True)
         """
         with self.assertDoesNotWarn(
-            msg="raised {} warning when not enabled".format(
-                pp.Diagnostics.warn_ungrouped_named_tokens_in_collection
-            )
+            msg=f"raised {pp.Diagnostics.warn_ungrouped_named_tokens_in_collection} warning when not enabled"
         ):
             COMMA = pp.Suppress(",").setName("comma")
             coord = ppc.integer("x") + COMMA + ppc.integer("y")
@@ -7932,11 +8569,10 @@
             pp.enable_diag(pp.Diagnostics.warn_ungrouped_named_tokens_in_collection)
 
             with self.assertDoesNotWarn(
-                msg="raised {} warning when warn on ungrouped named tokens was suppressed (original_text_for)".format(
-                    pp.Diagnostics.warn_ungrouped_named_tokens_in_collection
-                )
+                msg=f"raised {pp.Diagnostics.warn_ungrouped_named_tokens_in_collection}"
+                f" warning when warn on ungrouped named tokens was suppressed (original_text_for)"
             ):
-                pp.originalTextFor(pp.Word("ABC")...)("words")
+                pp.original_text_for(pp.Word("ABC")...)("words")
 
     def testWarnNameSetOnEmptyForward(self):
         """
@@ -7945,9 +8581,7 @@
         """
 
         with self.assertDoesNotWarn(
-            msg="raised {} warning when not enabled".format(
-                pp.Diagnostics.warn_name_set_on_empty_Forward
-            )
+            msg=f"raised {pp.Diagnostics.warn_name_set_on_empty_Forward} warning when not enabled"
         ):
             base = pp.Forward()("z")
 
@@ -7977,13 +8611,11 @@
         """
 
         with self.assertDoesNotWarn(
-            msg="raised {} warning when not enabled".format(
-                pp.Diagnostics.warn_on_parse_using_empty_Forward
-            )
+            msg=f"raised {pp.Diagnostics.warn_on_parse_using_empty_Forward} warning when not enabled"
         ):
             base = pp.Forward()
             try:
-                print(base.parseString("x"))
+                print(base.parseString("x", parseAll=True))
             except ParseException as pe:
                 pass
 
@@ -7997,7 +8629,7 @@
                 msg="failed to warn when parsing using an empty Forward expression",
             ):
                 try:
-                    print(base.parseString("x"))
+                    print(base.parseString("x", parseAll=True))
                 except ParseException as pe:
                     pass
 
@@ -8007,7 +8639,7 @@
             ):
                 base.suppress_warning(pp.Diagnostics.warn_on_parse_using_empty_Forward)
                 try:
-                    print(base.parseString("x"))
+                    print(base.parseString("x", parseAll=True))
                 except ParseException as pe:
                     pass
 
@@ -8025,9 +8657,7 @@
             base = pp.Word(pp.alphas)... | "(" + base + ")"
 
         with self.assertDoesNotWarn(
-            msg="raised {} warning when not enabled".format(
-                pp.Diagnostics.warn_on_assignment_to_Forward
-            )
+            msg=f"raised {pp.Diagnostics.warn_on_assignment_to_Forward} warning when not enabled"
         ):
             a_method()
 
@@ -8058,11 +8688,9 @@
           incorrectly called with multiple str arguments (default=True)
         """
         with self.assertDoesNotWarn(
-            msg="raised {} warning when not enabled".format(
-                pp.Diagnostics.warn_on_multiple_string_args_to_oneof
-            )
+            msg=f"raised {pp.Diagnostics.warn_on_multiple_string_args_to_oneof} warning when not enabled"
         ):
-            a = pp.oneOf("A", "B")
+            a = pp.one_of("A", "B")
 
         with ppt.reset_pyparsing_context():
             pp.enable_diag(pp.Diagnostics.warn_on_multiple_string_args_to_oneof)
@@ -8107,7 +8735,30 @@
         print(bool_constant)
         print(bool_constant.streamline())
         print(bool_list2)
-        self.assertEqual("bool , bool...", str(bool_list2))
+        with self.subTest():
+            self.assertEqual("bool , bool...", str(bool_list2))
+
+        with self.subTest():
+            street_address = pp.common.integer.set_name("integer") + pp.Word(pp.alphas)
+                1, ...
+            .set_name("street_name")
+            self.assertEqual(
+                "{integer street_name} , {integer street_name}...",
+                str(pp.delimitedList(street_address)),
+            )
+
+        with self.subTest():
+            operand = pp.Char(pp.alphas).set_name("var")
+            math = pp.infixNotation(
+                operand,
+                
+                    (pp.one_of("+ -"), 2, pp.opAssoc.LEFT),
+                ,
+            )
+            self.assertEqual(
+                "Forward: + | - term , Forward: + | - term...",
+                str(pp.delimitedList(math)),
+            )
 
     def testDelimitedListOfStrLiterals(self):
         expr = pp.delimitedList("ABC")
@@ -8138,6 +8789,99 @@
                 expr, source, s.strip() for s in source.split(",")
             )
 
+    def testDelimitedListParseActions1(self):
+        # from issue #408
+        keyword = pp.Keyword("foobar")
+        untyped_identifier = ~keyword + pp.Word(pp.alphas)
+        dotted_vars = pp.delimited_list(untyped_identifier, delim=".")
+        lvalue = pp.Opt(dotted_vars)
+
+        # uncomment this line to see the problem
+        stmt = pp.delimited_list(pp.Opt(dotted_vars))
+        # stmt = delimited_list(dotted_vars)
+        # stmt = pp.Opt(dotted_vars)
+
+        def parse_identifier(toks):
+            print("YAY!", toks)
+
+        untyped_identifier.set_parse_action(parse_identifier)
+
+        save_stdout = StringIO()
+        with contextlib.redirect_stdout(save_stdout):
+            dotted_vars.parse_string("B.C")
+
+        self.assertEqual(
+            dedent(
+                """\
+                YAY! 'B'
+                YAY! 'C'
+                """
+            ),
+            save_stdout.getvalue(),
+        )
+
+    def testDelimitedListParseActions2(self):
+        # from issue #408
+        keyword = pp.Keyword("foobar")
+        untyped_identifier = ~keyword + pp.Word(pp.alphas)
+        dotted_vars = pp.delimited_list(untyped_identifier, delim=".")
+        lvalue = pp.Opt(dotted_vars)
+
+        # uncomment this line to see the problem
+        # stmt = delimited_list(Opt(dotted_vars))
+        stmt = pp.delimited_list(dotted_vars)
+        # stmt = pp.Opt(dotted_vars)
+
+        def parse_identifier(toks):
+            print("YAY!", toks)
+
+        untyped_identifier.set_parse_action(parse_identifier)
+
+        save_stdout = StringIO()
+        with contextlib.redirect_stdout(save_stdout):
+            dotted_vars.parse_string("B.C")
+
+        self.assertEqual(
+            dedent(
+                """\
+                YAY! 'B'
+                YAY! 'C'
+                """
+            ),
+            save_stdout.getvalue(),
+        )
+
+    def testDelimitedListParseActions3(self):
+        # from issue #408
+        keyword = pp.Keyword("foobar")
+        untyped_identifier = ~keyword + pp.Word(pp.alphas)
+        dotted_vars = pp.delimited_list(untyped_identifier, delim=".")
+        lvalue = pp.Opt(dotted_vars)
+
+        # uncomment this line to see the problem
+        # stmt = delimited_list(Opt(dotted_vars))
+        # stmt = delimited_list(dotted_vars)
+        stmt = pp.Opt(dotted_vars)
+
+        def parse_identifier(toks):
+            print("YAY!", toks)
+
+        untyped_identifier.set_parse_action(parse_identifier)
+
+        save_stdout = StringIO()
+        with contextlib.redirect_stdout(save_stdout):
+            dotted_vars.parse_string("B.C")
+
+        self.assertEqual(
+            dedent(
+                """\
+                YAY! 'B'
+                YAY! 'C'
+                """
+            ),
+            save_stdout.getvalue(),
+        )
+
     def testEnableDebugOnNamedExpressions(self):
         """
         - enable_debug_on_named_expressions - flag to auto-enable debug on all subsequent
@@ -8153,7 +8897,7 @@
                 pp.enable_diag(pp.Diagnostics.enable_debug_on_named_expressions)
                 integer = pp.Word(pp.nums).setName("integer")
 
-                integer....parseString("1 2 3")
+                integer....parseString("1 2 3", parseAll=True)
 
             expected_debug_output = dedent(
                 """\
@@ -8185,7 +8929,6 @@
             )
 
     def testEnableDebugOnExpressionWithParseAction(self):
-
         test_stdout = StringIO()
         with resetting(sys, "stdout", "stderr"):
             sys.stdout = test_stdout
@@ -8193,12 +8936,12 @@
 
             parser = (ppc.integer().setDebug() | pp.Word(pp.alphanums).setDebug())...
             parser.setDebug()
-            parser.parseString("123 A100")
+            parser.parseString("123 A100", parseAll=True)
 
             # now turn off debug - should only get output for components, not overall parser
             print()
             parser.setDebug(False)
-            parser.parseString("123 A100")
+            parser.parseString("123 A100", parseAll=True)
 
         expected_debug_output = dedent(
             """\
@@ -8258,7 +9001,6 @@
         )
 
     def testEnableDebugWithCachedExpressionsMarkedWithAsterisk(self):
-
         a = pp.Literal("a").setName("A").setDebug()
         b = pp.Literal("b").setName("B").setDebug()
         z = pp.Literal("z").setName("Z").setDebug()
@@ -8272,7 +9014,7 @@
         with resetting(sys, "stdout", "stderr"):
             sys.stdout = test_stdout
             sys.stderr = test_stdout
-            grammar.parseString("aba")
+            grammar.parseString("aba", parseAll=True)
 
         expected_debug_output = dedent(
             """\
@@ -8360,11 +9102,58 @@
             expected_debug_output,
             output,
             (
-                "invalid debug output showing cached results marked with '*',"
-                " and packrat parsing {}".format(packrat_status)
+                f"invalid debug output showing cached results marked with '*',"
+                f" and packrat parsing {packrat_status}"
             ),
         )
 
+    def testSetDebugRecursively(self):
+        expr = pp.Word(pp.alphas)
+        contained = expr + pp.Empty().set_name("innermost")
+        depth = 4
+        for _ in range(depth):
+            contained = pp.Group(contained + pp.Empty())
+        contained.set_debug(recurse=True)
+        self.assertTrue(expr.debug)
+        # contained.parse_string("ABC")
+        test_stdout = StringIO()
+        with resetting(sys, "stdout", "stderr"):
+            sys.stdout = test_stdout
+            sys.stderr = test_stdout
+            contained.parseString("aba", parseAll=True)
+
+        output = test_stdout.getvalue()
+        print(output)
+        self.assertEqual(depth, output.count("Matched Empty -> "))
+        self.assertEqual(1, output.count("Matched innermost -> "))
+
+    def testSetDebugRecursivelyWithForward(self):
+        expr = pp.Word(pp.alphas).set_name("innermost")
+        contained = pp.infix_notation(
+            expr,
+            
+                ("NOT", 1, pp.opAssoc.RIGHT),
+                ("AND", 2, pp.opAssoc.LEFT),
+                ("OR", 2, pp.opAssoc.LEFT),
+            ,
+        )
+
+        contained.set_debug(recurse=True)
+        self.assertTrue(expr.debug)
+
+        # contained.parse_string("ABC")
+        test_stdout = StringIO()
+        with resetting(sys, "stdout", "stderr"):
+            sys.stdout = test_stdout
+            sys.stderr = test_stdout
+            contained.parseString("aba", parseAll=True)
+
+        output = test_stdout.getvalue()
+        print(output)
+        # count of matches varies with packrat state, can't match exact count, but at least test if contains
+        # self.assertEqual(4, output.count("Matched innermost -> 'aba'"))
+        self.assertTrue("Matched innermost -> 'aba'" in output)
+
     def testUndesirableButCommonPractices(self):
         # While these are valid constructs, and they are not encouraged
         # there is apparently a lot of code out there using these
@@ -8412,7 +9201,7 @@
         for diag_name in warn_names:
             self.assertFalse(
                 getattr(pp.__diag__, diag_name),
-                "__diag__.{} not set to True".format(diag_name),
+                f"__diag__.{diag_name} not set to True",
             )
 
         with ppt.reset_pyparsing_context():
@@ -8424,21 +9213,21 @@
             for diag_name in warn_names:
                 self.assertTrue(
                     getattr(pp.__diag__, diag_name),
-                    "__diag__.{} not set to True".format(diag_name),
+                    f"__diag__.{diag_name} not set to True",
                 )
 
             # non-warn diag_names must be enabled individually
             for diag_name in other_names:
                 self.assertFalse(
                     getattr(pp.__diag__, diag_name),
-                    "__diag__.{} not set to True".format(diag_name),
+                    f"__diag__.{diag_name} not set to True",
                 )
 
         # make sure they are off after AutoReset
         for diag_name in warn_names:
             self.assertFalse(
                 getattr(pp.__diag__, diag_name),
-                "__diag__.{} not set to True".format(diag_name),
+                f"__diag__.{diag_name} not set to True",
             )
 
     def testWordInternalReRangeWithConsecutiveChars(self):
@@ -8460,14 +9249,12 @@
         failed = 
         for word_string, expected_re in tests:
             try:
-                msg = "failed to generate correct internal re for {!r}".format(
-                    word_string
-                )
+                msg = f"failed to generate correct internal re for {word_string!r}"
                 resultant_re = pp.Word(word_string).reString
                 self.assertEqual(
                     expected_re,
                     resultant_re,
-                    msg + "; expected {!r} got {!r}".format(expected_re, resultant_re),
+                    msg + f"; expected {expected_re!r} got {resultant_re!r}",
                 )
             except AssertionError:
                 failed.append(msg)
@@ -8493,14 +9280,9 @@
             next_char = chr(ord(esc_char) + 1)
             prev_char = chr(ord(esc_char) - 1)
             esc_word = pp.Word(esc_char + next_char)
-            expected = r"{}{}+".format(
-                esc_re_set_char(esc_char),
-                esc_re_set_char(next_char),
-            )
+            expected = rf"{esc_re_set_char(esc_char)}{esc_re_set_char(next_char)}+"
             print(
-                "Testing escape char: {} -> {} re: '{}')".format(
-                    esc_char, esc_word, esc_word.reString
-                )
+                f"Testing escape char: {esc_char} -> {esc_word} re: '{esc_word.reString}')"
             )
             self.assertEqual(
                 expected, esc_word.reString, "failed to generate correct internal re"
@@ -8509,26 +9291,19 @@
                 random.choice(esc_char, next_char) for __ in range(16)
             )
             print(
-                "Match '{}' -> {}".format(
-                    test_string, test_string == esc_word.parseString(test_string)0
-                )
+                f"Match '{test_string}' -> {test_string == esc_word.parseString(test_string, parseAll=True)0}"
             )
             self.assertEqual(
                 test_string,
-                esc_word.parseString(test_string)0,
+                esc_word.parseString(test_string, parseAll=True)0,
                 "Word using escaped range char failed to parse",
             )
 
             # test escape char as last character in range
             esc_word = pp.Word(prev_char + esc_char)
-            expected = r"{}{}+".format(
-                esc_re_set_char(prev_char),
-                esc_re_set_char(esc_char),
-            )
+            expected = rf"{esc_re_set_char(prev_char)}{esc_re_set_char(esc_char)}+"
             print(
-                "Testing escape char: {} -> {} re: '{}')".format(
-                    esc_char, esc_word, esc_word.reString
-                )
+                f"Testing escape char: {esc_char} -> {esc_word} re: '{esc_word.reString}')"
             )
             self.assertEqual(
                 expected, esc_word.reString, "failed to generate correct internal re"
@@ -8537,13 +9312,11 @@
                 random.choice(esc_char, prev_char) for __ in range(16)
             )
             print(
-                "Match '{}' -> {}".format(
-                    test_string, test_string == esc_word.parseString(test_string)0
-                )
+                f"Match '{test_string}' -> {test_string == esc_word.parseString(test_string, parseAll=True)0}"
             )
             self.assertEqual(
                 test_string,
-                esc_word.parseString(test_string)0,
+                esc_word.parseString(test_string, parseAll=True)0,
                 "Word using escaped range char failed to parse",
             )
 
@@ -8551,14 +9324,9 @@
             next_char = chr(ord(esc_char) + 1)
             prev_char = chr(ord(esc_char) - 1)
             esc_word = pp.Word(esc_char + next_char)
-            expected = r"{}{}+".format(
-                esc_re_set_char(esc_char),
-                esc_re_set_char(next_char),
-            )
+            expected = rf"{esc_re_set_char(esc_char)}{esc_re_set_char(next_char)}+"
             print(
-                "Testing escape char: {} -> {} re: '{}')".format(
-                    esc_char, esc_word, esc_word.reString
-                )
+                f"Testing escape char: {esc_char} -> {esc_word} re: '{esc_word.reString}')"
             )
             self.assertEqual(
                 expected, esc_word.reString, "failed to generate correct internal re"
@@ -8567,23 +9335,19 @@
                 random.choice(esc_char, next_char) for __ in range(16)
             )
             print(
-                "Match '{}' -> {}".format(
-                    test_string, test_string == esc_word.parseString(test_string)0
-                )
+                f"Match '{test_string}' -> {test_string == esc_word.parseString(test_string, parseAll=True)0}"
             )
             self.assertEqual(
                 test_string,
-                esc_word.parseString(test_string)0,
+                esc_word.parseString(test_string, parseAll=True)0,
                 "Word using escaped range char failed to parse",
             )
 
             # test escape char as only character in range
             esc_word = pp.Word(esc_char, pp.alphas.upper())
-            expected = r"{}A-Z*".format(esc_re_set2_char(esc_char))
+            expected = rf"{esc_re_set2_char(esc_char)}A-Z*"
             print(
-                "Testing escape char: {} -> {} re: '{}')".format(
-                    esc_char, esc_word, esc_word.reString
-                )
+                f"Testing escape char: {esc_char} -> {esc_word} re: '{esc_word.reString}')"
             )
             self.assertEqual(
                 expected, esc_word.reString, "failed to generate correct internal re"
@@ -8592,23 +9356,19 @@
                 random.choice(pp.alphas.upper()) for __ in range(16)
             )
             print(
-                "Match '{}' -> {}".format(
-                    test_string, test_string == esc_word.parseString(test_string)0
-                )
+                f"Match '{test_string}' -> {test_string == esc_word.parseString(test_string, parseAll=True)0}"
             )
             self.assertEqual(
                 test_string,
-                esc_word.parseString(test_string)0,
+                esc_word.parseString(test_string, parseAll=True)0,
                 "Word using escaped range char failed to parse",
             )
 
             # test escape char as only character
             esc_word = pp.Word(esc_char, pp.alphas.upper())
-            expected = r"{}A-Z*".format(re.escape(esc_char))
+            expected = rf"{re.escape(esc_char)}A-Z*"
             print(
-                "Testing escape char: {} -> {} re: '{}')".format(
-                    esc_char, esc_word, esc_word.reString
-                )
+                f"Testing escape char: {esc_char} -> {esc_word} re: '{esc_word.reString}')"
             )
             self.assertEqual(
                 expected, esc_word.reString, "failed to generate correct internal re"
@@ -8617,13 +9377,11 @@
                 random.choice(pp.alphas.upper()) for __ in range(16)
             )
             print(
-                "Match '{}' -> {}".format(
-                    test_string, test_string == esc_word.parseString(test_string)0
-                )
+                f"Match '{test_string}' -> {test_string == esc_word.parseString(test_string, parseAll=True)0}"
             )
             self.assertEqual(
                 test_string,
-                esc_word.parseString(test_string)0,
+                esc_word.parseString(test_string, parseAll=True)0,
                 "Word using escaped range char failed to parse",
             )
             print()
@@ -8632,17 +9390,11 @@
         ppu = pp.pyparsing_unicode
 
         latin_identifier = pp.Word(pp.identchars, pp.identbodychars)("latin*")
-        japanese_identifier = pp.Word(
-            ppu.Japanese.identchars, ppu.Japanese.identbodychars
-        )("japanese*")
-        cjk_identifier = pp.Word(ppu.CJK.identchars, ppu.CJK.identbodychars)("cjk*")
-        greek_identifier = pp.Word(ppu.Greek.identchars, ppu.Greek.identbodychars)(
-            "greek*"
-        )
-        cyrillic_identifier = pp.Word(
-            ppu.Cyrillic.identchars, ppu.Cyrillic.identbodychars
-        )("cyrillic*")
-        thai_identifier = pp.Word(ppu.Thai.identchars, ppu.Thai.identbodychars)("thai*")
+        japanese_identifier = ppu.Japanese.identifier("japanese*")
+        cjk_identifier = ppu.CJK.identifier("cjk*")
+        greek_identifier = ppu.Greek.identifier("greek*")
+        cyrillic_identifier = ppu.Cyrillic.identifier("cyrillic*")
+        thai_identifier = ppu.Thai.identifier("thai*")
         idents = (
             latin_identifier
             | japanese_identifier
@@ -8653,7 +9405,8 @@
         )
 
         result = idents....parseString(
-            "abc_100 кириллицаx_10 日本語f_300 ไทยg_600 def_200 漢字y_300 한국어_中文c_400 Ελληνικάb_500"
+            "abc_100 кириллицаx_10 日本語f_300 ไทยg_600 def_200 漢字y_300 한국어_中文c_400 Ελληνικάb_500",
+            parseAll=True,
         )
         self.assertParseResultsEquals(
             result,
@@ -8755,7 +9508,9 @@
     def testMatchFirstIteratesOverAllChoices(self):
         # test MatchFirst bugfix
         print("verify MatchFirst iterates properly")
-        results = pp.quotedString.parseString("'this is a single quoted string'")
+        results = pp.quotedString.parseString(
+            "'this is a single quoted string'", parseAll=True
+        )
         self.assertTrue(
             len(results) > 0, "MatchFirst error - not iterating over all choices"
         )
@@ -8783,8 +9538,8 @@
         print("verify Optional's do not cause match failure if have results name")
         testGrammar = pp.Literal("A") + pp.Optional("B")("gotB") + pp.Literal("C")
         try:
-            testGrammar.parseString("ABC")
-            testGrammar.parseString("AC")
+            testGrammar.parseString("ABC", parseAll=True)
+            testGrammar.parseString("AC", parseAll=True)
         except pp.ParseException as pe:
             print(pe.pstr, "->", pe)
             self.fail("error in Optional matching of string %s" % pe.pstr)
@@ -8795,8 +9550,8 @@
             pp.Literal("A") | (pp.Literal("B") + pp.Literal("C")) | pp.Literal("E")
         )
         try:
-            testGrammar.parseString("BC")
-            testGrammar.parseString("BD")
+            testGrammar.parseString("BC", parseAll=True)
+            testGrammar.parseString("BD", parseAll=True)
         except pp.ParseException as pe:
             print(pe.pstr, "->", pe)
             self.assertEqual("BD", pe.pstr, "wrong test string failed to parse")
@@ -8817,7 +9572,10 @@
         def testValidation(grmr, gnam, isValid):
             try:
                 grmr.streamline()
-                grmr.validate()
+                with self.assertWarns(
+                    DeprecationWarning, msg="failed to warn validate() is deprecated"
+                ):
+                    grmr.validate()
                 self.assertTrue(isValid, "validate() accepted invalid grammar " + gnam)
             except pp.RecursiveGrammarException as rge:
                 print(grmr)
@@ -8847,8 +9605,8 @@
         g1 = "XXX" + (aaa | bbb | ccc)...
         teststring = "XXX b bb a bbb bbbb aa bbbbb :c bbbbbb aaa"
         names = 
-        print(g1.parseString(teststring).dump())
-        for t in g1.parseString(teststring):
+        print(g1.parseString(teststring, parseAll=True).dump())
+        for t in g1.parseString(teststring, parseAll=True):
             print(t, repr(t))
             try:
                 names.append(t0.getName())
@@ -8873,12 +9631,12 @@
             print(t, t.getName())
 
         ident.addParseAction(getNameTester)
-        scanner.parseString("lsjd sldkjf IF Saslkj AND lsdjf")
+        scanner.parseString("lsjd sldkjf IF Saslkj AND lsdjf", parseAll=True)
 
         # test ParseResults.get() method
         print("verify behavior of ParseResults.get()")
         # use sum() to merge separate groups into single ParseResults
-        res = sum(g1.parseString(teststring)1:)
+        res = sum(g1.parseString(teststring, parseAll=True)1:)
         print(res.dump())
         print(res.get("A", "A not found"))
         print(res.get("D", "!D"))
@@ -8890,16 +9648,14 @@
     def testOptionalBeyondEndOfString(self):
         print("verify handling of Optional's beyond the end of string")
         testGrammar = "A" + pp.Optional("B") + pp.Optional("C") + pp.Optional("D")
-        testGrammar.parseString("A")
-        testGrammar.parseString("AB")
+        testGrammar.parseString("A", parseAll=True)
+        testGrammar.parseString("AB", parseAll=True)
 
     def testCreateLiteralWithEmptyString(self):
         # test creating Literal with empty string
-        print('verify non-fatal usage of Literal("")')
-        with self.assertRaises(
-            ValueError, msg="failed to warn use of empty string for Literal"
-        ):
-            e = pp.Literal("")
+        print('verify that Literal("") is optimized to Empty()')
+        e = pp.Literal("")
+        self.assertIsInstance(e, pp.Empty)
 
     def testLineMethodSpecialCaseAtStart(self):
         # test line() behavior when starting at 0 and the opening line is an \n
@@ -8937,67 +9693,83 @@
         grammar = abb | abc | aba
 
         self.assertEqual(
-            "aba", "".join(grammar.parseString("aba")), "Packrat ABA failure!"
+            "aba",
+            "".join(grammar.parseString("aba", parseAll=True)),
+            "Packrat ABA failure!",
         )
 
     def testSetResultsNameWithOneOrMoreAndZeroOrMore(self):
         print("verify behavior of setResultsName with OneOrMore and ZeroOrMore")
         stmt = pp.Keyword("test")
-        print(stmt...("tests").parseString("test test").tests)
-        print(stmt1, ...("tests").parseString("test test").tests)
-        print(pp.Optional(stmt1, ...("tests")).parseString("test test").tests)
-        print(pp.Optional(stmt1, ...)("tests").parseString("test test").tests)
+        print(stmt...("tests").parseString("test test", parseAll=True).tests)
+        print(stmt1, ...("tests").parseString("test test", parseAll=True).tests)
+        print(
+            pp.Optional(stmt1, ...("tests"))
+            .parseString("test test", parseAll=True)
+            .tests
+        )
+        print(
+            pp.Optional(stmt1, ...)("tests")
+            .parseString("test test", parseAll=True)
+            .tests
+        )
         print(
-            pp.Optional(pp.delimitedList(stmt))("tests").parseString("test,test").tests
+            pp.Optional(pp.delimitedList(stmt))("tests")
+            .parseString("test,test", parseAll=True)
+            .tests
         )
         self.assertEqual(
             2,
-            len(stmt...("tests").parseString("test test").tests),
+            len(stmt...("tests").parseString("test test", parseAll=True).tests),
             "ZeroOrMore failure with setResultsName",
         )
         self.assertEqual(
             2,
-            len(stmt1, ...("tests").parseString("test test").tests),
+            len(stmt1, ...("tests").parseString("test test", parseAll=True).tests),
             "OneOrMore failure with setResultsName",
         )
         self.assertEqual(
             2,
-            len(pp.Optional(stmt1, ...("tests")).parseString("test test").tests),
+            len(
+                pp.Optional(stmt1, ...("tests"))
+                .parseString("test test", parseAll=True)
+                .tests
+            ),
             "OneOrMore failure with setResultsName",
         )
         self.assertEqual(
             2,
             len(
                 pp.Optional(pp.delimitedList(stmt))("tests")
-                .parseString("test,test")
+                .parseString("test,test", parseAll=True)
                 .tests
             ),
             "delimitedList failure with setResultsName",
         )
         self.assertEqual(
             2,
-            len((stmt * 2)("tests").parseString("test test").tests),
+            len((stmt * 2)("tests").parseString("test test", parseAll=True).tests),
             "multiplied(1) failure with setResultsName",
         )
         self.assertEqual(
             2,
-            len(stmt..., 2("tests").parseString("test test").tests),
+            len(stmt..., 2("tests").parseString("test test", parseAll=True).tests),
             "multiplied(2) failure with setResultsName",
         )
         self.assertEqual(
             2,
-            len(stmt1, ...("tests").parseString("test test").tests),
+            len(stmt1, ...("tests").parseString("test test", parseAll=True).tests),
             "multiplied(3) failure with setResultsName",
         )
         self.assertEqual(
             2,
-            len(stmt2, ...("tests").parseString("test test").tests),
+            len(stmt2, ...("tests").parseString("test test", parseAll=True).tests),
             "multiplied(3) failure with setResultsName",
         )
 
     def testParseResultsReprWithResultsNames(self):
         word = pp.Word(pp.printables)("word")
-        res = word....parseString("test blub")
+        res = word....parseString("test blub", parseAll=True)
 
         print(repr(res))
         print(res"word")
@@ -9010,7 +9782,7 @@
         )
 
         word = pp.Word(pp.printables)("word*")
-        res = word....parseString("test blub")
+        res = word....parseString("test blub", parseAll=True)
 
         print(repr(res))
         print(res"word")
@@ -9023,7 +9795,6 @@
         )
 
     def testWarnUsingLshiftForward(self):
-
         print(
             "verify that using '<<' operator with a Forward raises a warning if there is a dangling '|' operator"
         )
@@ -9076,7 +9847,7 @@
         ):
             print(expr, cls)
             parser = cls(expr)
-            parsed_result = parser.parseString(test_string)
+            parsed_result = parser.parseString(test_string, parseAll=False)
             print(parsed_result.dump())
             self.assertParseResultsEquals(parsed_result, expected)
 
@@ -9085,7 +9856,7 @@
         ):
             parser = cls(expr, expr)
             print(parser)
-            parsed_result = parser.parseString(test_string)
+            parsed_result = parser.parseString(test_string, parseAll=False)
             print(parsed_result.dump())
             self.assertParseResultsEquals(parsed_result, expected)
 
@@ -9113,7 +9884,7 @@
         pa = pp.OnlyOnce(append_sum)
         expr = pp.OneOrMore(pp.Word(pp.nums)).addParseAction(pa)
 
-        result = expr.parseString("0 123 321")
+        result = expr.parseString("0 123 321", parseAll=True)
         print(result.dump())
         expected = "0", "123", "321", 444
         self.assertParseResultsEquals(
@@ -9123,7 +9894,7 @@
         with self.assertRaisesParseException(
             msg="failed to raise exception calling OnlyOnce more than once"
         ):
-            result2 = expr.parseString("1 2 3 4 5")
+            result2 = expr.parseString("1 2 3 4 5", parseAll=True)
 
         pa.reset()
         result = expr.parseString("100 200 300")
@@ -9152,7 +9923,7 @@
 
         expecteds = "11.11.13", 14.21, "21.12.12", 41
         for line, expected in zip(infile, expecteds):
-            result = patt.parseString(line)
+            result = patt.parseString(line, parseAll=True)
             print(result)
 
             self.assertEqual(
@@ -9169,7 +9940,7 @@
             with self.assertRaisesParseException(
                 msg="issue with GoToColumn not finding match"
             ):
-                result = patt.parseString(line)
+                result = patt.parseString(line, parseAll=True)
 
     def testExceptionExplainVariations(self):
         class Modifier:
@@ -9187,7 +9958,7 @@
         self_testcase_name = "tests.test_unit." + type(self).__name__
 
         try:
-            grammar.parseString("1000")
+            grammar.parseString("1000", parseAll=True)
         except Exception as e:
             # extract the exception explanation
             explain_str = ParseException.explain_exception(e)
@@ -9196,7 +9967,7 @@
 
             expected = 
                 self_testcase_name,
-                "pyparsing.core._WordRegex - integer",
+                "pyparsing.core.Word - integer",
                 "tests.test_unit.Modifier",
                 "pyparsing.results.ParseResults",
             
@@ -9213,9 +9984,49 @@
             exception_line = explain_str_lines-(len(expected) + 1)
             self.assertTrue(
                 exception_line.startswith("TypeError:"),
-                msg="unexpected exception line ({!r})".format(exception_line),
+                msg=f"unexpected exception line ({exception_line!r})",
             )
 
+    def testForwardReferenceException(self):
+        token = pp.Forward()
+        num = pp.Word(pp.nums)
+        num.setName("num")
+        text = pp.Word(pp.alphas)
+        text.setName("text")
+        fail = pp.Regex(r"\\A-Za-z*")("name")
+
+        def parse_fail(s, loc, toks):
+            raise pp.ParseFatalException(s, loc, f"Unknown symbol: {toks'name'}")
+
+        fail.set_parse_action(parse_fail)
+        token <<= num | text | fail
+
+        # If no name is given, do not intercept error messages
+        with self.assertRaises(pp.ParseFatalException, msg="Unknown symbol: \\fail"):
+            token.parse_string("\\fail")
+
+        # If name is given, do intercept error messages
+        token.set_name("token")
+        with self.assertRaises(pp.ParseFatalException, msg="Expected token, found.*"):
+            token.parse_string("\\fail")
+
+    def testForwardExceptionText(self):
+        wd = pp.Word(pp.alphas)
+
+        ff = pp.Forward().set_name("fffff!")
+        ff <<= wd + pp.Opt(ff)
+
+        with self.assertRaises(pp.ParseFatalException, msg="no numbers!"):
+            try:
+                ff.parse_string("123")
+            except pp.ParseException as pe:
+                raise pp.ParseSyntaxException("no numbers! just alphas!") from pe
+
+        with self.assertRaises(pp.ParseException, msg="Expected W:(A-Za-z)"):
+            ff2 = pp.Forward()
+            ff2 <<= wd
+            ff2.parse_string("123")
+
     def testMiscellaneousExceptionBits(self):
         pp.ParserElement.verbose_stacktrace = True
 
@@ -9223,7 +10034,7 @@
 
         # force a parsing exception - match an integer against "ABC"
         try:
-            pp.Word(pp.nums).parseString("ABC")
+            pp.Word(pp.nums).parseString("ABC", parseAll=True)
         except pp.ParseException as pe:
             expected_str = "Expected W:(0-9), found 'ABC'  (at char 0), (line:1, col:1)"
             self.assertEqual(expected_str, str(pe), "invalid ParseException str")
@@ -9241,29 +10052,29 @@
             depth_0_explain_str = pe.explain(depth=0)
             depth_1_explain_str = pe.explain(depth=1)
             print(depth_none_explain_str)
+            print()
+            print(depth_0_explain_str)
+            print()
+            print(depth_1_explain_str)
 
-            expr_name = "pyparsing.core._WordRegex - W:(0-9)"
+            expr_name = "pyparsing.core.Word - W:(0-9)"
             for expected_function in self_testcase_name, expr_name:
                 self.assertTrue(
                     expected_function in depth_none_explain_str,
-                    "{!r} not found in ParseException.explain()".format(
-                        expected_function
-                    ),
+                    f"{expected_function!r} not found in ParseException.explain()",
                 )
                 self.assertFalse(
                     expected_function in depth_0_explain_str,
-                    "{!r} found in ParseException.explain(depth=0)".format(
-                        expected_function
-                    ),
+                    f"{expected_function!r} found in ParseException.explain(depth=0)",
                 )
 
             self.assertTrue(
                 expr_name in depth_1_explain_str,
-                "{!r} not found in ParseException.explain()".format(expected_function),
+                f"{expected_function!r} not found in ParseException.explain()",
             )
             self.assertFalse(
                 self_testcase_name in depth_1_explain_str,
-                "{!r} not found in ParseException.explain()".format(expected_function),
+                f"{expected_function!r} not found in ParseException.explain()",
             )
 
     def testExpressionDefaultStrings(self):
@@ -9300,6 +10111,26 @@
             expr.streamline()
             to_railroad(expr)
 
+    def testForwardsDoProperStreamlining(self):
+        wd = pp.Word(pp.alphas)
+        w3 = wd + wd + wd
+        # before streamlining, w3 is {{W:(A-Za-z) W:(A-Za-z)} W:(A-Za-z)}
+        self.assertIsInstance(w3.exprs0, pp.And)
+        self.assertEqual(len(w3.exprs), 2)
+
+        ff = pp.Forward()
+        ff <<= w3 + pp.Opt(ff)
+        # before streamlining, ff is {{{W:(A-Za-z) W:(A-Za-z)} W:(A-Za-z)} Forward: None}
+        self.assertEqual(len(ff.expr.exprs), 2)
+
+        ff.streamline()
+
+        # after streamlining:
+        #   w3 is {W:(A-Za-z) W:(A-Za-z) W:(A-Za-z)}
+        #   ff is {W:(A-Za-z) W:(A-Za-z) W:(A-Za-z) Forward: None}
+        self.assertEqual(len(ff.expr.exprs), 4)
+        self.assertEqual(len(w3.exprs), 3)
+
 
 class Test03_EnablePackratParsing(TestCase):
     def runTest(self):
@@ -9453,20 +10284,23 @@
         """repetition rules formulated with recursion"""
         one_or_more = pp.Forward().setName("one_or_more")
         one_or_more <<= one_or_more + "a" | "a"
-        self.assertParseResultsEquals(one_or_more.parseString("a"), expected_list="a")
         self.assertParseResultsEquals(
-            one_or_more.parseString("aaa aa"), expected_list="a", "a", "a", "a", "a"
+            one_or_more.parseString("a", parseAll=True), expected_list="a"
+        )
+        self.assertParseResultsEquals(
+            one_or_more.parseString("aaa aa", parseAll=True),
+            expected_list="a", "a", "a", "a", "a",
         )
         delimited_list = pp.Forward().setName("delimited_list")
         delimited_list <<= delimited_list + pp.Suppress(",") + "b" | "b"
         self.assertParseResultsEquals(
-            delimited_list.parseString("b"), expected_list="b"
+            delimited_list.parseString("b", parseAll=True), expected_list="b"
         )
         self.assertParseResultsEquals(
-            delimited_list.parseString("b,b"), expected_list="b", "b"
+            delimited_list.parseString("b,b", parseAll=True), expected_list="b", "b"
         )
         self.assertParseResultsEquals(
-            delimited_list.parseString("b,b , b, b,b"),
+            delimited_list.parseString("b,b , b, b,b", parseAll=True),
             expected_list="b", "b", "b", "b", "b",
         )
 
@@ -9476,10 +10310,10 @@
         num = pp.Word(pp.nums)
         expr <<= expr + "+" - num | num
         self.assertParseResultsEquals(
-            expr.parseString("1+2"), expected_list="1", "+", "2"
+            expr.parseString("1+2", parseAll=True), expected_list="1", "+", "2"
         )
         self.assertParseResultsEquals(
-            expr.parseString("1+2+3+4"),
+            expr.parseString("1+2+3+4", parseAll=True),
             expected_list="1", "+", "2", "+", "3", "+", "4",
         )
 
@@ -9489,10 +10323,10 @@
         num = pp.Word(pp.nums)
         expr <<= pp.Group(expr) + "+" - num | num
         self.assertParseResultsEquals(
-            expr.parseString("1+2"), expected_list="1", "+", "2"
+            expr.parseString("1+2", parseAll=True), expected_list="1", "+", "2"
         )
         self.assertParseResultsEquals(
-            expr.parseString("1+2+3+4"),
+            expr.parseString("1+2+3+4", parseAll=True),
             expected_list="1", "+", "2", "+", "3", "+", "4",
         )
 
@@ -9505,11 +10339,11 @@
             | (expr + "-" - num).setParseAction(lambda t: t0 - t2)
             | num
         )
-        self.assertEqual(expr.parseString("1+2")0, 3)
-        self.assertEqual(expr.parseString("1+2+3")0, 6)
-        self.assertEqual(expr.parseString("1+2-3")0, 0)
-        self.assertEqual(expr.parseString("1-2+3")0, 2)
-        self.assertEqual(expr.parseString("1-2-3")0, -4)
+        self.assertEqual(expr.parseString("1+2", parseAll=True)0, 3)
+        self.assertEqual(expr.parseString("1+2+3", parseAll=True)0, 6)
+        self.assertEqual(expr.parseString("1+2-3", parseAll=True)0, 0)
+        self.assertEqual(expr.parseString("1-2+3", parseAll=True)0, 2)
+        self.assertEqual(expr.parseString("1-2-3", parseAll=True)0, -4)
 
     def test_math(self):
         """precedence climbing parser for math"""
@@ -9539,35 +10373,40 @@
         terminal <<= number | signed | group
         expr <<= add_sub
         # simple add_sub expressions
-        self.assertEqual(expr.parseString("1+2")0, 3)
-        self.assertEqual(expr.parseString("1+2+3")0, 6)
-        self.assertEqual(expr.parseString("1+2-3")0, 0)
-        self.assertEqual(expr.parseString("1-2+3")0, 2)
-        self.assertEqual(expr.parseString("1-2-3")0, -4)
+        self.assertEqual(expr.parseString("1+2", parseAll=True)0, 3)
+        self.assertEqual(expr.parseString("1+2+3", parseAll=True)0, 6)
+        self.assertEqual(expr.parseString("1+2-3", parseAll=True)0, 0)
+        self.assertEqual(expr.parseString("1-2+3", parseAll=True)0, 2)
+        self.assertEqual(expr.parseString("1-2-3", parseAll=True)0, -4)
         # precedence overwriting via parentheses
-        self.assertEqual(expr.parseString("1+(2+3)")0, 6)
-        self.assertEqual(expr.parseString("1+(2-3)")0, 0)
-        self.assertEqual(expr.parseString("1-(2+3)")0, -4)
-        self.assertEqual(expr.parseString("1-(2-3)")0, 2)
+        self.assertEqual(expr.parseString("1+(2+3)", parseAll=True)0, 6)
+        self.assertEqual(expr.parseString("1+(2-3)", parseAll=True)0, 0)
+        self.assertEqual(expr.parseString("1-(2+3)", parseAll=True)0, -4)
+        self.assertEqual(expr.parseString("1-(2-3)", parseAll=True)0, 2)
         # complicated math expressions – same as Python expressions
-        self.assertEqual(expr.parseString("1----3")0, 1 - ---3)
-        self.assertEqual(expr.parseString("1+2*3")0, 1 + 2 * 3)
-        self.assertEqual(expr.parseString("1*2+3")0, 1 * 2 + 3)
-        self.assertEqual(expr.parseString("1*2^3")0, 1 * 2**3)
-        self.assertEqual(expr.parseString("4^3^2^1")0, 4**3**2**1)
+        self.assertEqual(expr.parseString("1----3", parseAll=True)0, 1 - ---3)
+        self.assertEqual(expr.parseString("1+2*3", parseAll=True)0, 1 + 2 * 3)
+        self.assertEqual(expr.parseString("1*2+3", parseAll=True)0, 1 * 2 + 3)
+        self.assertEqual(expr.parseString("1*2^3", parseAll=True)0, 1 * 2**3)
+        self.assertEqual(
+            expr.parseString("4^3^2^1", parseAll=True)0, 4**3**2**1
+        )
 
     def test_terminate_empty(self):
         """Recursion with ``Empty`` terminates"""
         empty = pp.Forward().setName("e")
         empty <<= empty + pp.Empty() | pp.Empty()
-        self.assertParseResultsEquals(empty.parseString(""), expected_list=)
+        self.assertParseResultsEquals(
+            empty.parseString("", parseAll=True), expected_list=
+        )
 
     def test_non_peg(self):
         """Recursion works for non-PEG operators"""
         expr = pp.Forward().setName("expr")
         expr <<= expr + "a" ^ expr + "ab" ^ expr + "abc" ^ "."
         self.assertParseResultsEquals(
-            expr.parseString(".abcabaabc"), expected_list=".", "abc", "ab", "a", "abc"
+            expr.parseString(".abcabaabc", parseAll=True),
+            expected_list=".", "abc", "ab", "a", "abc",
         )

_service:tar_scm:pyparsing-3.0.9.tar.gz/tox.ini -> _service:tar_scm:pyparsing-3.1.1.tar.gz/tox.ini Changed

@@ -1,21 +1,17 @@
 tox
 skip_missing_interpreters=true
 envlist =
-    py{36,37,38,39,310,py3},pyparsing_packaging
+    py{36,37,38,39,310,311,312,py3},mypy-test
 isolated_build = True
 
 testenv
-deps=coverage
+deps=pytest
 extras=diagrams
 commands=
-    coverage run --parallel --branch -m unittest
+    pytest tests
 
-testenv:pyparsing_packaging
-deps=
-    pretend
-    pytest
-commands=
-    python -c "import shutil,os,stat;os.path.exists('packaging') and shutil.rmtree('packaging', onerror=lambda fn, path, _:os.chmod(path,stat.S_IWRITE) or fn(path))"
-    git clone --depth 10 https://github.com/pypa/packaging.git
-    python -m pytest packaging/tests
-    python -c "import shutil,os,stat;shutil.rmtree('packaging', onerror=lambda fn, path, _:os.chmod(path,stat.S_IWRITE) or fn(path))"
+testenv:mypy-test
+deps = mypy==0.960
+# note: cd to tests/ to avoid mypy trying to check pyparsing (which fails)
+changedir = tests
+commands = mypy --show-error-codes --warn-unused-ignores mypy-ignore-cases/