开源软件构建与测试

_service:tar_scm:mesa.spec Changed

@@ -1,7 +1,5 @@
 %global llvm_toolset %{nil}
 %global llvm_pkg_prefix %{nil}
-%global vendor_name rust-bindgen-0.64.0
-%global vendor_bidngen 0
 
 %ifarch s390x
 %define with_hardware 0
@@ -36,6 +34,7 @@
 %ifarch %{arm} riscv64
 %define with_xa        1
 %define with_vmware    1
+%define with_vaapi 0
 %endif
 
 %global dri_drivers %{?platform_drivers}
@@ -50,18 +49,16 @@
 
 Name:           mesa
 Summary:        Mesa graphics libraries
-Version:        23.0.0
+Version:        23.0.3
 Release:        1
 
 License:        MIT
 URL:            http://www.mesa3d.org
 Source0:        https://mesa.freedesktop.org/archive/%{name}-%{version}.tar.xz
-Source1:        vendor.tar.xz
 
 Patch0:         0001-llvmpipe-add-an-implementation-with-llvm-orcjit.patch
 Patch1:         0002-llvmpipe-add-riscv-support-in-orcjit.patch
 Patch2:         0003-llvmpipe-make-unnamed-global-have-internal-linkage.patch
-Patch3:         U_glx-fix-indirect-initialization-crash.patch
 
 BuildRequires:  gcc
 BuildRequires:  gcc-c++
@@ -110,11 +107,9 @@
 BuildRequires:  rust cargo
 BuildRequires:  pkgconfig(SPIRV-Tools)
 BuildRequires:  pkgconfig(LLVMSPIRVLib)
-%if 0%{?vendor_bidngen} == 0
 BuildRequires:  rust-bindgen
 %endif
 %endif
-%endif
 BuildRequires: python3-mako
 %ifarch %{valgrind_arches}
 BuildRequires: pkgconfig(valgrind)
@@ -154,6 +149,8 @@
 %package libEGL
 Summary:        Mesa libEGL runtime libraries
 Requires:       libglvnd-egl%{?_isa} >= 1:1.2.0-1
+Requires:       %{name}-libgbm%{?_isa} = %{?epoch:%{epoch}:}%{version}-%{release}            
+Requires:       %{name}-libglapi%{?_isa} = %{?epoch:%{epoch}:}%{version}-%{release}
 
 %description libEGL
 %{summary}.
@@ -172,6 +169,7 @@
 Summary:        Mesa-based DRI drivers
 Requires:       %{name}-filesystem%{?_isa} = %{?epoch:%{epoch}:}%{version}-%{release}
 Requires:	libdrm >= 2.4.103
+Requires:       %{name}-libglapi%{?_isa} = %{?epoch:%{epoch}:}%{version}-%{release}
 
 %description dri-drivers
 %{summary}.
@@ -326,24 +324,6 @@
 %endif
 
 %prep
-%if 0%{?vendor_bidngen}
-mkdir -p rust_vendor
-cd rust_vendor
-%{__tar} xf %{SOURCE1}
-mkdir .cargo
-cat > .cargo/config <<EOL
-source.crates-io
-replace-with = "vendored-sources"
-source.vendored-sources
-directory = "`pwd`/%{vendor_name}/vendor"
-EOL
-env CARGO_HOME=.cargo \
-cargo build --release \
---manifest-path %{vendor_name}/Cargo.toml 
-export PATH=`pwd`/%{vendor_name}/target/release/:$PATH
-cd -
-%endif
-
 %autosetup -n %{name}-%{version} -p1
 
 # Make sure the build uses gnu++17 as llvm 10 headers require that
@@ -367,10 +347,12 @@
   -Dgallium-va=%{?with_vaapi:enabled}%{!?with_vaapi:disabled} \
   -Dgallium-xa=%{?with_xa:enabled}%{!?with_xa:disabled} \
   -Dgallium-nine=%{?with_nine:true}%{!?with_nine:false} \
+%if 0%{?with_opencl}
   -Dgallium-opencl=%{?with_opencl:icd}%{!?with_opencl:disabled} \
-%if 0%{?with_opencl} && 0%{?with_rusticl}
+%if 0%{?with_rusticl}
   -Dgallium-rusticl=true -Drust_std=2021 \
 %endif
+%endif
   -Dvulkan-drivers=%{?vulkan_drivers} \
   -Dvulkan-layers=device-select \
   -Dshared-glapi=enabled \

_service:tar_scm:U_glx-fix-indirect-initialization-crash.patch Deleted

@@ -1,55 +0,0 @@
-From 1eab7e69e2ba84244f551f6901f4307a687a9504 Mon Sep 17 00:00:00 2001
-From: Illia Polishchuk <illia.a.polishchuk@globallogic.com>
-Date: Tue, 28 Feb 2023 16:07:59 +0200
-Subject: PATCH glx: fix indirect initialization crash
-
-Fixes: b090246a ("glx: Only compute client GL extensions for indirect contexts")
-Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8393
-
-Reviewed-by: Adam Jackson <ajax@redhat.com>
-
-Signed-off-by: Illia Polishchuk <illia.a.polishchuk@globallogic.com>
-Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21591>
----
- src/glx/glxext.c       | 9 ++++++++-
- src/glx/indirect_glx.c | 1 -
- 2 files changed, 8 insertions(+), 2 deletions(-)
-
-diff --git a/src/glx/glxext.c b/src/glx/glxext.c
-index 755a75ab568..4b3496b5a14 100644
---- a/src/glx/glxext.c
-+++ b/src/glx/glxext.c
-@@ -813,10 +813,17 @@ AllocAndFetchScreenConfigs(Display * dpy, struct glx_display * priv)
-       if (psc == NULL)
-          psc = applegl_create_screen(i, priv);
- #else
-+      bool indirect = false;
-       if (psc == NULL)
--	 psc = indirect_create_screen(i, priv);
-+      {
-+         psc = indirect_create_screen(i, priv);
-+         indirect = true;
-+      }
- #endif
-       priv->screensi = psc;
-+
-+      if(indirect) /* Load extensions required only for indirect glx */
-+         glxSendClientInfo(priv, i);
-    }
-    SyncHandle();
-    return GL_TRUE;
-diff --git a/src/glx/indirect_glx.c b/src/glx/indirect_glx.c
-index dc3464fc99e..abe561f700b 100644
---- a/src/glx/indirect_glx.c
-+++ b/src/glx/indirect_glx.c
-@@ -365,7 +365,6 @@ indirect_create_screen(int screen, struct glx_display * priv)
-       return NULL;
- 
-    glx_screen_init(psc, screen, priv);
--   glxSendClientInfo(priv, screen);
-    psc->vtable = &indirect_screen_vtable;
- 
-    return psc;
--- 
-2.35.3
-

_service Changed

_service:tar_scm:mesa-23.0.0.tar.xz/.pick_status.json -> _service:tar_scm:mesa-23.0.3.tar.xz/.pick_status.json Changed

@@ -1,12 +1,30693 @@
 
     {
+        "sha": "d99211b22c0b419e2ad414f2e09bfe43f656db4b",
+        "description": "radv: debug: Update decode ring umr command",
+        "nominated": false,
+        "nomination_type": null,
+        "resolution": 4,
+        "main_sha": null,
+        "because_sha": null,
+        "notes": null
+    },
+    {
+        "sha": "cb282b6a8135c8c4222d7683f5122ae35602158d",
+        "description": "vk/entry_points:: fix mingw build",
+        "nominated": true,
+        "nomination_type": 0,
+        "resolution": 0,
+        "main_sha": null,
+        "because_sha": "7e833713d83087934221cd47ece49e87199a00d1",
+        "notes": null
+    },
+    {
+        "sha": "6bc2dce228d60994b72de9a32c14747816557fec",
+        "description": "radv: use gfx_level in radv_flush_occlusion_query_state()",
+        "nominated": false,
+        "nomination_type": null,
+        "resolution": 4,
+        "main_sha": null,
+        "because_sha": null,
+        "notes": null
+    },
+    {
+        "sha": "fbab8df43fe20fffcdfbdffea60dc40254ec9766",
+        "description": "radv: emit PIXEL_PIPE_STAT_CONTROL in the gfx preamble for GFX11",
+        "nominated": false,
+        "nomination_type": null,
+        "resolution": 4,
+        "main_sha": null,
+        "because_sha": null,
+        "notes": null
+    },
+    {
+        "sha": "c1d32880f7ba767f4d36c8e1bd239311855043a8",
+        "description": "radv: track DB_COUNT_CONTROL changes to avoid context rolls",
+        "nominated": false,
+        "nomination_type": null,
+        "resolution": 4,
+        "main_sha": null,
+        "because_sha": null,
+        "notes": null
+    },
+    {
+        "sha": "02443d752e83d470f400af004e3702fb8f7d8ce3",
+        "description": "radv: delay enabling/disabling occlusion queries at draw time",
+        "nominated": false,
+        "nomination_type": null,
+        "resolution": 4,
+        "main_sha": null,
+        "because_sha": null,
+        "notes": null
+    },
+    {
+        "sha": "3017d01c9ded9c9fd097b600081b1bbe86e90fb8",
+        "description": "zink: check for extendedDynamicState3DepthClipNegativeOneToOne for ds3 support",
+        "nominated": true,
+        "nomination_type": 1,
+        "resolution": 0,
+        "main_sha": null,
+        "because_sha": "c7f46d2ad6de5368cdef09e77bba9f4ff59cad76",
+        "notes": null
+    },
+    {
+        "sha": "e6701f723147c45798584ba77da7095f2317684c",
+        "description": "radeonsi/vcn: AV1 skip the redundant bs resize",
+        "nominated": false,
+        "nomination_type": null,
+        "resolution": 4,
+        "main_sha": null,
+        "because_sha": null,
+        "notes": null
+    },
+    {
+        "sha": "d44651bfc3c8f6cb6aba8914f5bd21e440d69a4c",
+        "description": "radv: wait for occlusion queries in the resolve query shader",
+        "nominated": false,
+        "nomination_type": null,
+        "resolution": 4,
+        "main_sha": null,
+        "because_sha": null,
+        "notes": null
+    },
+    {
+        "sha": "1e6e3427f032a3ca0193d57facbd9a63b75e6a7c",
+        "description": "drisw: don't leak the winsys",
+        "nominated": true,
+        "nomination_type": 0,
+        "resolution": 0,
+        "main_sha": null,
+        "because_sha": null,
+        "notes": null
+    },
+    {
+        "sha": "2d6527c9f15b06b556de884fa81c525cb4568a59",
+        "description": "pvr: fix typo in pvr_rt_get_region_headers_stride_size()",
+        "nominated": false,
+        "nomination_type": null,
+        "resolution": 4,
+        "main_sha": null,
+        "because_sha": null,
+        "notes": null
+    },
+    {
+        "sha": "83a1b74240df3afcdb0e723c5bf6514b3321b411",
+        "description": "zink: don't create separate shader dsls if there are no bindings",
+        "nominated": false,
+        "nomination_type": null,
+        "resolution": 4,
+        "main_sha": null,
+        "because_sha": null,
+        "notes": null
+    },
+    {
+        "sha": "329473c24212d4a6854afdec5c772458644b6dd1",
+        "description": "zink: add a util function for printing shaders",
+        "nominated": false,
+        "nomination_type": null,
+        "resolution": 4,
+        "main_sha": null,
+        "because_sha": null,
+        "notes": null
+    },
+    {
+        "sha": "f2f6012f4a094bac274f7cf35a142f379f3c18c9",
+        "description": "zink: call zink_shader_free for compute shaders",
+        "nominated": false,
+        "nomination_type": null,
+        "resolution": 4,
+        "main_sha": null,
+        "because_sha": null,
+        "notes": null
+    },
+    {
+        "sha": "ee8c1a44c1a01a1bd63aab5c58ff38136cea85b6",
+        "description": "zink: always wait on precompile fence at start of zink_gfx_shader_free()",
+        "nominated": false,
+        "nomination_type": null,
+        "resolution": 4,
+        "main_sha": null,
+        "because_sha": null,
+        "notes": null
+    },
+    {
+        "sha": "b2ecafd1ac9534cd4ba11df31d4b5288e90600e4",
+        "description": "zink: split out generic shader destruction for reuse",
+        "nominated": false,
+        "nomination_type": null,
+        "resolution": 4,
+        "main_sha": null,
+        "because_sha": null,
+        "notes": null
+    },
+    {
+        "sha": "9f6eec03e0023fa0f849bdb35eea58594293edac",
+        "description": "zink: zink_shader_free -> zink_gfx_shader_free",
+        "nominated": false,
+        "nomination_type": null,
+        "resolution": 4,
+        "main_sha": null,
+        "because_sha": null,
+        "notes": null
+    },
+    {
+        "sha": "9bf4db8ebb4d12a867edbf0740b55cc920fef712",
+        "description": "zink: don't bitcast bool deref loads/stores",
+        "nominated": true,
+        "nomination_type": 0,
+        "resolution": 0,
+        "main_sha": null,
+        "because_sha": null,
+        "notes": null
+    },
+    {
+        "sha": "82add9f2e992be166c60551cfc5baaea0fd0d3a3",
+        "description": "zink: avoid recursion during msrtss blits from flushing clears",
+        "nominated": false,
+        "nomination_type": null,
+        "resolution": 4,
+        "main_sha": null,
+        "because_sha": null,
+        "notes": null
+    },
+    {
+        "sha": "8ea506e94bf22b757b3123c242430ab2392638c2",
+        "description": "zink: skip msrtss replicate if the attachment will be full-cleared",
+        "nominated": false,
+        "nomination_type": null,
+        "resolution": 4,
+        "main_sha": null,
+        "because_sha": null,

_service:tar_scm:mesa-23.0.0.tar.xz/VERSION -> _service:tar_scm:mesa-23.0.3.tar.xz/VERSION Changed

_service:tar_scm:mesa-23.0.0.tar.xz/docs/drivers/zink.rst -> _service:tar_scm:mesa-23.0.3.tar.xz/docs/drivers/zink.rst Changed

_service:tar_scm:mesa-23.0.0.tar.xz/docs/envvars.rst -> _service:tar_scm:mesa-23.0.3.tar.xz/docs/envvars.rst Changed

_service:tar_scm:mesa-23.0.0.tar.xz/docs/relnotes.rst -> _service:tar_scm:mesa-23.0.3.tar.xz/docs/relnotes.rst Changed

_service:tar_scm:mesa-23.0.0.tar.xz/docs/relnotes/23.0.0.rst -> _service:tar_scm:mesa-23.0.3.tar.xz/docs/relnotes/23.0.0.rst Changed

_service:tar_scm:mesa-23.0.3.tar.xz/docs/relnotes/23.0.1.rst Added

@@ -0,0 +1,262 @@
+Mesa 23.0.1 Release Notes / 2023-03-24
+======================================
+
+Mesa 23.0.1 is a bug fix release which fixes bugs found since the 23.0.0 release.
+
+Mesa 23.0.1 implements the OpenGL 4.6 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.6. OpenGL
+4.6 is **only** available if requested at context creation.
+Compatibility contexts may report a lower version depending on each driver.
+
+Mesa 23.0.1 implements the Vulkan 1.3 API, but the version reported by
+the apiVersion property of the VkPhysicalDeviceProperties struct
+depends on the particular driver being used.
+
+SHA256 checksum
+---------------
+
+::
+
+    e8e586856b55893abae9bdcdb98b41c081d909bb1faf372e6e7262307bf34adf  mesa-23.0.1.tar.xz
+
+
+
+New features
+------------
+
+- None
+
+
+Bug fixes
+---------
+
+- radv: A Plague Tale: Requiem black "flash" on 7900XTX
+- 7900 XTX: Graphical corruption / artifacts in Cyberpunk
+- radv: CmdCopyQueryPoolResults broken for VK_QUERY_TYPE_PRIMITIVES_GENERATED_EXT with queryCount > 1
+- radeonsi draws spurious values to depth buffer
+- rusticl over llvmpipe + ffmpeg's Opencl filter = error -51
+- rusticl over llvmpipe + ffmpeg's Opencl filter = error -51
+- OpenGL crashes in X-Plane 11
+- Bisected Regression: Project Zomboid renders black
+- hasvk: Black pixels with 8xMSAA and fast clears on Intel(R) HD Graphics 4400 (HSW GT2)
+- radv: GTA IV graphical artifacts on 7900XTX
+- radv: Resident Evil Revelations 2 artifacts on 7900XTX with DCC
+- radv: Prototype 2 black textures on RDNA 3 when DCC is enabled
+- Mesa 23.0.0 crashes immediately with indirect rendering
+- RADV Returnal - pistol muzzle flash fills whole screen (graphical artifact)
+- ACO: dEQP-VK.binding_model.descriptor_buffer.multiple.graphics_geom_buffers1_sets3_imm_samplers hangs on NAVI10
+- Build failures with recent lld
+- r600,regression:  Glitches on terrain with the NIR backend on Transport Fever 2
+- r600/TURKS: Crash of the game "A Hat in Time" with Gallium Nine and NIR path (third report)
+- gen9atom Vulkan tests cause gpu hang: dEQP-VK.memory_model.*
+- GL_SHADER_BINARY_FORMAT_SPIR_V is not added to the list of GL_SHADER_BINARY_FORMATS even if GL_ARB_gl_spirv is supported.
+- ANV/DG2 Vertex explosion in nvpro-samples/vk_raytracing_tutorial_KHR/ray_tracing_gltf
+- CUEtools FLACCL hit assert in rusticl
+- Assertion Failed on Intel HD 5500 with Linux / Mesa 22.3.1 / OpenGL
+
+
+Changes
+-------
+
+Błażej Szczygieł (1):
+
+- glx: Fix glXGetFBConfigFromVisualSGIX
+
+Caio Oliveira (2):
+
+- iris, crocus: Align workaround address to 32B
+- gallivm: Fix handling of nir_intrinsic_scoped_barrier
+
+Daniel Schürmann (1):
+
+- aco: fix NIR infinite loops
+
+Daniel Stone (1):
+
+- intel/isl: Don't scream FINISHME into logs for 3D vs. CCS
+
+Dave Airlie (1):
+
+- llvmpipe: fix compute address bits to return native pointer size.
+
+Dylan Baker (11):
+
+- docs: Add sha256 sum for 23.0.0
+- .pick_status.json: Update to 56a9aad4010ff9f2c0afcadec0ac61a6274de0a3
+- .pick_status.json: Update to aa791961a82e1f5a9dd841c3e0398c3e80d09652
+- .pick_status.json: Update to e45bbcf6492a178e52e4b87bad31bb01bc22e507
+- .pick_status.json: Update to baea3b328b7a39abcee48c733236f242e1f4cf0e
+- util: rzalloc and free hash_table_u64
+- .pick_status.json: Update to 6cb0c8b6d746fe055bbe905025550140c0980720
+- .pick_status.json: Update to 8c51c8697ab122472b9136f9a17813a7a6513c59
+- .pick_status.json: Update to 8c51c8697ab122472b9136f9a17813a7a6513c59
+- .pick_status.json: Update to 69cbc2e7eea599fb63f93373408a589f4345c6de
+- .pick_status.json: Update to 0cd89a27ed0da0bf79c3eae9aac314ee33c3a852
+
+Emma Anholt (1):
+
+- ci: Re-enable some swrast testing using fd.o's shared runners for now.
+
+Eric Engestrom (2):
+
+- radv: split linker script for android since it requires different symbols
+- glapi/meson: drop duplicate line in deps
+
+Erik Faye-Lund (1):
+
+- docs/zink: fixup wording of the GL 4.6 requirements
+
+Friedrich Vock (2):
+
+- mesa: Report GL_SHADER_BINARY_FORMAT_SPIR_V as supported
+- docs: Fix formatting for RMV tracing docs
+
+Georg Lehmann (1):
+
+- aco/optimizer_postRA: assume all registers are untrackable in loop headers
+
+Gert Wollny (3):
+
+- r600/sfn: be more conservative with channel use in multi-slot ops
+- r600/sfn: Fix minimum required registers
+- r600/sfn: Fix atomic lowering
+
+Illia Polishchuk (1):
+
+- glx: fix indirect initialization crash
+
+Iván Briano (3):
+
+- vulkan: track the right value on CmdSetColorWriteMasks
+- anv: fix testing for dynamic color blend bits
+- anv: stop tracking color blend state in the pipeline
+
+José Roberto de Souza (1):
+
+- iris: Don't mark protected bo as reusable
+
+Karol Herbst (3):
+
+- nir/deref: don't replace casts with deref_struct if we'd lose the stride
+- rusticl/kernel: Images arg sizes also have to match the host pointer size
+- gallivm: fix lp_vec_add_offset_ptr for 32 bit builds
+
+Kenneth Graunke (1):
+
+- intel/fs: Fix inferred_sync_pipe for F16TO32 opcodes
+
+Lionel Landwerlin (19):
+
+- anv: fix invalid masking of 48bit address
+- anv: fix vma heap memory leak
+- genxml: Fix STATE_BASE_ADDRESS::BindlessSurfaceStateSize field size
+- genxml: fix border color offset field on Gfx12+
+- anv: fixup condition for Wa_14016118574
+- anv: pull Wa_14016118574 out of some loop not changing state
+- anv: fix incorrect parameter
+- anv: fix generated forward jump with more than 67M draws
+- anv: remove copied code from generation shader
+- anv: remove BTI related flush in generation shaders
+- anv: correctly program 3DSTATE_SF in generation shaders
+- anv: limit push constant dirtyness with generation shaders
+- anv: remove pre hasvk split assert
+- anv: remove commented code
+- anv: fix indirect draws VF cache tracking of index buffer
+- anv: make sure mi_memcpy lands before push constant loads
+- anv: remove MI_NOOPs at the end of the generation batch
+- nir: fix nir_ishl_imm
+- anv: force MEDIA_INTERFACE_DESCRIPTOR_LOAD reemit after 3D->GPGPU switch
+
+Marek Olšák (8):
+
+- amd: add missing gfx11 register definitions
+- radeonsi/gfx11: fix the CU_EN clear mask for RSRC4_GS
+- radeonsi/gfx11: don't set non-existent VGT_STRMOUT_BUFFER_CONFIG
+- radeonsi/gfx11: set CB_COLORi_INFO.MAX_COMP_FRAG on GFX1103_R2
+- radeonsi: disable Smart Access Memory because CPU access has large overhead
+- nir: lower to fragment_mask_fetch/load_amd with EQAA correctly
+- mesa: fix glPopClientAttrib with fixed-func VP and zero-stride varyings
+- radeonsi: don't merge SET_* packets that have a different index in si_pm4_state
+
+Mike Blumenkrantz (10):
+
+- zink: fix shader read access removal for barrier generation
+- zink: avoid adding ubo/ssbo bindings multiple times for different bitsizes
+- zink: remove suspended queries from list before resuming
+- zink: disable queries for clear_texture()
+- zink: fix zink_resource_access_is_write()
+- zink: only add deferred barrier on fb unbind when layout needs to change
+- zink: fix descriptor update flagging on null ssbo set
+- zink: propagate valid_buffer_range when replacing buffer storage
+- aux/tc: fix rp info resizing clobbering current info
+- vulkan/wsi: fix crash in failed swapchain creation for wayland
+
+Patrick Lerda (1):
+
+- r600: fix shader blob memory leak
+

_service:tar_scm:mesa-23.0.3.tar.xz/docs/relnotes/23.0.2.rst Added

@@ -0,0 +1,233 @@
+Mesa 23.0.2 Release Notes / 2023-04-07
+======================================
+
+Mesa 23.0.2 is a bug fix release which fixes bugs found since the 23.0.1 release.
+
+Mesa 23.0.2 implements the OpenGL 4.6 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.6. OpenGL
+4.6 is **only** available if requested at context creation.
+Compatibility contexts may report a lower version depending on each driver.
+
+Mesa 23.0.2 implements the Vulkan 1.3 API, but the version reported by
+the apiVersion property of the VkPhysicalDeviceProperties struct
+depends on the particular driver being used.
+
+SHA256 checksum
+---------------
+
+::
+
+    1b7d3399fc6f16f030361f925d33ebc7600cbf98094582f54775b6a1180529e7  mesa-23.0.2.tar.xz
+
+
+
+New features
+------------
+
+- None
+
+
+Bug fixes
+---------
+
+- allwinner a64: DRM_IOCTL_MODE_CREATE_DUMB failed: Cannot allocate memory after some time of apps usage
+- mesa: index buffer leaking
+- RadeonSI: null dereference in amdgpu_cs_add_buffer, potential refcount mismatch, running BeyondAllReason
+- eglCreateImageKHR, error: EGL_BAD_ALLOC (0x3003), message: "createImageFromDmaBufs failed" on AMD multi-gpu with explicit format modifiers
+- libgrl.a installed but not used?
+- radv: crash compiling UE5 lumen hardware RT shader
+- aco: unused vtmp_in_loop
+- radv,nir: dEQP-VK.ray_query.builtin.rayqueryterminate.* failures
+- glsl compiled error when the RHS of operator \`>>` is int64_t by enabling GL_ARB_gpu_shader_int64 extension
+- QPainter fails to render multiple shapes with a brush set since Mesa 23.0
+- eglSwapBuffers blocks in wayland when it's wl_surface_frame event is stolen.
+- plasmashell sometimes hangs with mesa_glthread
+- pps_device.h:23:11: error: ‘uint32_t’ does not name a type
+
+
+Changes
+-------
+
+Alyssa Rosenzweig (1):
+
+- panfrost: Don't round up Midgard polygon list BOs
+
+Daniel Schürmann (2):
+
+- radv/rt: place any-hit scratch vars after intersection scratch vars
+- radv/rt: Fix any_hit scratch variables.
+
+David Heidelberg (1):
+
+- aco: drop leftover variable
+
+Dylan Baker (5):
+
+- docs: Add sha256 sum for 23.0.1
+- .pick_status.json: Update to 5e9ea154849ebe19b96a243b9716bd264545bf8b
+- .pick_status.json: Update to 2cc9364c2061fe4a66398678cabf61e3464e4d77
+- .pick_status.json: Update to 7abd8c499b4388f1e2947d78c59aafa0b52c254a
+- .pick_status.json: Update to debc543904235ed7dfc14217bf43f33f9f768e5a
+
+Emma Anholt (1):
+
+- turnip: Don't push inline uniform buffer contents outside constlen.
+
+Eric Engestrom (1):
+
+- v3d: fix \`dirty` bitset being too small to accept V3D_DIRTY_SSBO
+
+Erico Nunes (1):
+
+- lima: don't use resource_from_handle while creating scanout
+
+Filip Gawin (1):
+
+- crocus: don't quantize the clear value
+
+Francisco Jerez (1):
+
+- intel/fs: Fix register coalesce in presence of force_writemask_all copy source writes.
+
+Gert Wollny (1):
+
+- r600/sfn: fix container allocators
+
+Iago Toral Quiroga (1):
+
+- vulkan/wsi/display: set pDisplay to NULL on error
+
+Ilya K (1):
+
+- intel/vk/grl: don't install libgrl.a
+
+Isabella Basso (2):
+
+- nir/algebraic: insert patterns inside optimizations list
+- nir/algebraic: remove duplicate bool conversion lowerings
+
+Iván Briano (1):
+
+- vulkan/wsi/display: do not dereference a NULL pointer
+
+Jesse Natalie (2):
+
+- nir: Propagate alignment when rematerializing cast derefs
+- microsoft/compiler: Fix setting bit 31 in feature flags
+
+Kai-Heng Feng (2):
+
+- iris: Retry DRM_IOCTL_I915_GEM_EXECBUFFER2 on ENOMEM
+- Revert "iris: Avoid abort() if kernel can't allocate memory"
+
+Karol Herbst (3):
+
+- nvc0: enable fp helper invocation memory loads on Turing+
+- rusticl/util: extract offset_of macro
+- rusticl/icd: Make it work in case Rustc shuffles struct around
+
+Konstantin Seurer (3):
+
+- radv/sqtt: Skip dumping pipeline libraries
+- radv/rt: Handle load_constant instructions when inlining shaders
+- nir/lower_shader_calls: Remat derefs before lowering resumes
+
+Lang Yu (1):
+
+- amd/common: fix a typo
+
+Lionel Landwerlin (12):
+
+- intel/fs: don't SEND messages as partial writes
+- intel/fs: fix nir_opt_peephole_ffma max vec assumption
+- intel/fs: fixup sources number from opt_algebraic
+- intel/fs: fix subgroup invocation read bounds checking
+- anv: fix incorrect utrace bo release
+- anv: implement recommended flush/wait of AUX-TT invalidation
+- iris: implement recommended flush/wait of AUX-TT invalidation
+- anv: take care of maxStorageBufferRange being uint32_t
+- isl: update max buffer size for SKL+
+- intel/perf: fix OA format selection on MTL
+- intel/fs: don't consider fixup_nomask_control_flow SENDs predicate
+- intel/fs: UNDEF fixup_nomask_control_flow temp register
+
+Lynne (1):
+
+- aco_validate: allow for wave32 in p_dual_src_export_gfx11
+
+Marcin Ślusarz (1):
+
+- anv,hasvk: remove stale comments
+
+Marek Olšák (1):
+
+- vbo: fix current attribs not updating gallium vertex elements
+
+Mike Blumenkrantz (9):
+
+- aux/trace: delete GALLIUM_TRACE_NIR log message
+- zink: track tc fences better
+- zink: double check layouts for possible feedback loop images
+- zink: handle swapchain creation failure less lazily
+- aux/trace: fix GALLIUM_TRACE_NIR handling
+- llvmpipe: fix linear fs analysis with nonzero fs outputs
+- llvmpipe: fix handling of unused color attachments
+- zink: block resolves where src extents > dst extents
+- zink: flag vertex buffers for rebind after vstate draws
+
+Patrick Lerda (1):
+
+- r600: fix typo that could lead to a possible crash
+
+Pierre-Eric Pelloux-Prayer (5):
+
+- yegl/wayland: fix glthread deadlocks
+- Revert "driconf: add a workaround for plasmashell freezing"
+- radeonsi: don't use alignment_log2 of imported buffers
+- mesa: fix invalid index_bo refcounting
+- util/vbuf: fix index_bo leak
+
+Qiang Yu (2):
+
+- ac/llvm: respect channel_type when ac_build_buffer_load
+- ac/llvm: add missing type convert for nir_load_buffer_amd
+
+Rhys Perry (1):
+
+- aco: fix nir_var_shader_out barriers for task shaders

_service:tar_scm:mesa-23.0.3.tar.xz/docs/relnotes/23.0.3.rst Added

@@ -0,0 +1,150 @@
+Mesa 23.0.3 Release Notes / 2023-04-20
+======================================
+
+Mesa 23.0.3 is a bug fix release which fixes bugs found since the 23.0.2 release.
+
+Mesa 23.0.3 implements the OpenGL 4.6 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.6. OpenGL
+4.6 is **only** available if requested at context creation.
+Compatibility contexts may report a lower version depending on each driver.
+
+Mesa 23.0.3 implements the Vulkan 1.3 API, but the version reported by
+the apiVersion property of the VkPhysicalDeviceProperties struct
+depends on the particular driver being used.
+
+SHA256 checksum
+---------------
+
+::
+
+    TBD.
+
+
+New features
+------------
+
+- None
+
+
+Bug fixes
+---------
+
+- overlay layer: unable to launch titles on steam
+- radv: possibly not setting state dirty bits correctly
+- RADV: VRS attachment not working in specific scenario
+- anv: zink ADL failures
+- Vulkan loader \`vk_common_GetPhysicalDeviceFormatProperties` fails to sanitize properties bits.
+- Loading a model in PrusaSlicer 2.6.0-alpha5 crashes GNOME on radeonsi
+
+
+Changes
+-------
+
+Alyssa Rosenzweig (4):
+
+- vulkan: Add common features2_to_features
+- tu: Use vk_features2_to_features
+- util/prim_convert: Don't set index_bounds_valid
+- mesa/st: Only set seamless for GLES3
+
+Andres Calderon Jaramillo (1):
+
+- r600: Report multi-plane formats as unsupported
+
+Bas Nieuwenhuizen (1):
+
+- radv: Reserve space in framebuffer emission.
+
+David (Ming Qiang) Wu (1):
+
+- radeonsi/vcn: add an exception of field case for h264 decoding
+
+Dylan Baker (3):
+
+- docs: Add sha256 sum for 23.0.2
+- .pick_status.json: Update to d6b30d42b05a93aa80c93c7fcc1782f9c59a6f1a
+- .pick_status.json: Update to d99211b22c0b419e2ad414f2e09bfe43f656db4b
+
+Jesse Natalie (3):
+
+- dzn: Fix SRV barrier state on compute command lists
+- dzn: Ensure pipeline variants are used for dynamic stencil masks
+- dzn: Don't use write-combine memory for cache-coherent UMA
+
+Juan A. Suarez Romero (1):
+
+- v3d: set depth compare function correctly
+
+Karol Herbst (1):
+
+- rusticl/event: drop work item before updating status
+
+Kenneth Graunke (1):
+
+- intel/compiler: Use nir_dest_bit_size() for ballot bit size check
+
+Lionel Landwerlin (3):
+
+- anv: fixup streamout write barriers
+- intel/fs: use nomask for setting cr0 for float controls
+- vulkan/overlay: deal with unknown pNext structures
+
+Luc Ma (1):
+
+- meson: keep Mako version checking in accord with build msg
+
+Mike Blumenkrantz (9):
+
+- llvmpipe: fix LP_PERF=no_depth to ignore depth format
+- aux/tc: flag late zs clears as partial clears
+- zink: try to prune resources from barrier jit on fb unbind
+- zink: free GPL input/output libs on context destroy to avoid leaking
+- lavapipe: fix dynamic depth clamping
+- lavapipe: set render_condition_enabled=false for vkCmdClearDepthStencilImage
+- mesa/st/program: don't init xfb info if there are no outputs
+- glthread: use id 0 for internal buffer objects
+- lavapipe: don't double-inline ubo0
+
+Patrick Lerda (3):
+
+- egl: fix memory leak related to _eglRefreshDeviceList()
+- r600: fix refcnt imbalance related to r600_set_vertex_buffers()
+- r600: fix refcnt imbalance related to evergreen_set_shader_images()
+
+Qiang Yu (3):
+
+- ac/nir/ngg: fix gs culling vertex liveness check for odd vertices
+- ac/nir/ngg: fix store shared alignment
+- radeonsi: fix max scrach lds size calculation when ngg
+
+Ruijing Dong (1):
+
+- frontends/va: disable skip_frame_enable in vaapi interface.
+
+Samuel Pitoiset (4):
+
+- vulkan: ignore rasterizationSamples when the state is dynamic
+- radv: try to keep HTILE compressed for READ_ONLY_OPTIMAL layout
+- radv: fix VS prologs with GPL and static binding stride
+- radv: re-emit the guardband state when related PSO are bound
+
+SoroushIMG (1):
+
+- zink: fix stale point sprite mode state
+
+Timur Kristóf (4):
+
+- ac/llvm: Cover runtime 0 in GFX10 gs_alloc_req workaround.
+- radv/amdgpu: Fix mismatching return type of radv_amdgpu_cs_submit.
+- radv/amdgpu: Only allow IB BOs on graphics and compute queues.
+- radv/amdgpu: Use correct alignment when creating CS BOs.
+
+Tomeu Vizoso (1):
+
+- etnaviv: don't read too much from uniform arrays
+
+xurui (1):
+
+- zink: bs->dd.push_pool1.pool should be freed

_service:tar_scm:mesa-23.0.0.tar.xz/meson.build -> _service:tar_scm:mesa-23.0.3.tar.xz/meson.build Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/amd/common/ac_nir_lower_ngg.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/amd/common/ac_nir_lower_ngg.c Changed

@@ -2733,6 +2733,7 @@
    /* Calculate and store per-vertex primitive flags based on vertex counts:
     * - bit 0: whether this vertex finishes a primitive (a real primitive, not the strip)
     * - bit 1: whether the primitive index is odd (if we are emitting triangle strips, otherwise always 0)
+    *          only set when the vertex also finishes the primitive
     * - bit 2: whether vertex is live (if culling is enabled: set after culling, otherwise always 1)
     */
 
@@ -2746,11 +2747,15 @@
 
    nir_ssa_def *prim_flag = nir_ior(b, vertex_live_flag, complete_flag);
    if (s->num_vertices_per_primitive == 3) {
-      nir_ssa_def *odd = nir_iand_imm(b, current_vtx_per_prim, 1);
-      prim_flag = nir_iadd_nuw(b, prim_flag, nir_ishl(b, odd, nir_imm_int(b, 1)));
+      nir_ssa_def *odd = nir_iand(b, current_vtx_per_prim, complete_flag);
+      nir_ssa_def *odd_flag = nir_ishl(b, odd, nir_imm_int(b, 1));
+      prim_flag = nir_ior(b, prim_flag, odd_flag);
    }
 
-   nir_store_shared(b, nir_u2u8(b, prim_flag), gs_emit_vtx_addr, .base = s->lds_offs_primflags + stream, .align_mul = 4u);
+   nir_store_shared(b, nir_u2u8(b, prim_flag), gs_emit_vtx_addr,
+                    .base = s->lds_offs_primflags + stream,
+                    .align_mul = 4, .align_offset = stream);
+
    nir_instr_remove(&intrin->instr);
    return true;
 }

_service:tar_scm:mesa-23.0.0.tar.xz/src/amd/common/ac_nir_lower_taskmesh_io_to_mem.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/amd/common/ac_nir_lower_taskmesh_io_to_mem.c Changed

@@ -211,7 +211,7 @@
    nir_ssa_def *workgroup_index = task_workgroup_index(b, s);
 
    nir_ssa_def *idx = nir_iadd_nuw(b, ring_entry, workgroup_index);
-   return nir_ubfe(b, idx, nir_imm_int(b, util_bitcount(s->num_entries - 1)), nir_imm_int(b, 1));
+   return nir_u2u8(b, nir_ubfe(b, idx, nir_imm_int(b, util_bitcount(s->num_entries - 1)), nir_imm_int(b, 1)));
 }
 
 static nir_ssa_def *
@@ -288,9 +288,13 @@
       nir_ssa_def *x = nir_channel(b, dimensions, 0);
       nir_ssa_def *y = nir_channel(b, dimensions, 1);
       nir_ssa_def *z = nir_channel(b, dimensions, 2);
-      nir_ssa_def *rdy = task_draw_ready_bit(b, s);
-      nir_ssa_def *store_val = nir_vec4(b, x, y, z, rdy);
-      task_write_draw_ring(b, store_val, 0, s);
+
+      /* Dispatch dimensions of mesh shader workgroups. */
+      task_write_draw_ring(b, nir_vec3(b, x, y, z), 0, s);
+      /* Prevent the two stores from being reordered. */
+      nir_scoped_memory_barrier(b, NIR_SCOPE_INVOCATION, NIR_MEMORY_RELEASE, nir_var_shader_out);
+      /* Ready bit, only write the low 8 bits. */
+      task_write_draw_ring(b, task_draw_ready_bit(b, s), 12, s);
    }
    nir_pop_if(b, if_invocation_index_zero);

_service:tar_scm:mesa-23.0.0.tar.xz/src/amd/common/ac_rgp.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/amd/common/ac_rgp.c Changed

@@ -288,6 +288,7 @@
    SQTT_MEMORY_TYPE_DDR2 = 0x2,
    SQTT_MEMORY_TYPE_DDR3 = 0x3,
    SQTT_MEMORY_TYPE_DDR4 = 0x4,
+   SQTT_MEMORY_TYPE_DDR5 = 0x5,
    SQTT_MEMORY_TYPE_GDDR3 = 0x10,
    SQTT_MEMORY_TYPE_GDDR4 = 0x11,
    SQTT_MEMORY_TYPE_GDDR5 = 0x12,
@@ -379,17 +380,22 @@
       return SQTT_MEMORY_TYPE_DDR3;
    case AMD_VRAM_TYPE_DDR4:
       return SQTT_MEMORY_TYPE_DDR4;
+   case AMD_VRAM_TYPE_DDR5:
+      return SQTT_MEMORY_TYPE_DDR5;
+   case AMD_VRAM_TYPE_GDDR3:
+      return SQTT_MEMORY_TYPE_GDDR3;
+   case AMD_VRAM_TYPE_GDDR4:
+      return SQTT_MEMORY_TYPE_GDDR4;
    case AMD_VRAM_TYPE_GDDR5:
       return SQTT_MEMORY_TYPE_GDDR5;
-   case AMD_VRAM_TYPE_HBM:
-      return SQTT_MEMORY_TYPE_HBM;
    case AMD_VRAM_TYPE_GDDR6:
       return SQTT_MEMORY_TYPE_GDDR6;
-   case AMD_VRAM_TYPE_DDR5:
+   case AMD_VRAM_TYPE_HBM:
+      return SQTT_MEMORY_TYPE_HBM;
+   case AMD_VRAM_TYPE_LPDDR4:
+      return SQTT_MEMORY_TYPE_LPDDR4;
+   case AMD_VRAM_TYPE_LPDDR5:
       return SQTT_MEMORY_TYPE_LPDDR5;
-   case AMD_VRAM_TYPE_GDDR1:
-   case AMD_VRAM_TYPE_GDDR3:
-   case AMD_VRAM_TYPE_GDDR4:
    default:
       unreachable("Invalid vram type");
    }

_service:tar_scm:mesa-23.0.0.tar.xz/src/amd/common/ac_surface.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/amd/common/ac_surface.c Changed

@@ -1779,9 +1779,7 @@
          MAX2(surf->u.gfx9.surf_slice_size,
               surf->u.gfx9.surf_pitch * out.height * surf->bpe * surf->blk_w);
       surf->surf_size = surf->u.gfx9.surf_slice_size * in->numSlices;
-   }
 
-   if (in->swizzleMode == ADDR_SW_LINEAR) {
       int alignment = 256 / surf->bpe;
       for (unsigned i = 0; i < in->numMipLevels; i++) {
          surf->u.gfx9.offseti = mip_infoi.offset;
@@ -1789,6 +1787,12 @@
          surf->u.gfx9.pitchi = align(mip_infoi.pitch / surf->blk_w, alignment);
       }
       surf->u.gfx9.base_mip_width = surf->u.gfx9.surf_pitch;
+   } else if (in->swizzleMode == ADDR_SW_LINEAR) {
+      for (unsigned i = 0; i < in->numMipLevels; i++) {
+         surf->u.gfx9.offseti = mip_infoi.offset;
+         surf->u.gfx9.pitchi = mip_infoi.pitch;
+      }
+      surf->u.gfx9.base_mip_width = surf->u.gfx9.surf_pitch;
    } else {
       surf->u.gfx9.base_mip_width = mip_info0.pitch;
    }
@@ -3041,7 +3045,7 @@
    assert(info->gfx_level >= GFX9);
 
    ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT input = {0};
-   input.size = sizeof(ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT);
+   input.size = sizeof(ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT);
    input.slice = layer;
    input.mipId = level;
    input.unalignedWidth = DIV_ROUND_UP(surf_info->width, surf->blk_w);

_service:tar_scm:mesa-23.0.0.tar.xz/src/amd/common/amd_family.h -> _service:tar_scm:mesa-23.0.3.tar.xz/src/amd/common/amd_family.h Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/amd/compiler/aco_insert_NOPs.cpp -> _service:tar_scm:mesa-23.0.3.tar.xz/src/amd/compiler/aco_insert_NOPs.cpp Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/amd/compiler/aco_instruction_selection.cpp -> _service:tar_scm:mesa-23.0.3.tar.xz/src/amd/compiler/aco_instruction_selection.cpp Changed

@@ -7394,7 +7394,8 @@
       storage_allowed |= storage_task_payload;
 
    /* Allow VMEM output for all stages that can have outputs. */
-   if (ctx->stage.hw != HWStage::CS && ctx->stage.hw != HWStage::FS)
+   if ((ctx->stage.hw != HWStage::CS && ctx->stage.hw != HWStage::FS) ||
+       ctx->stage.has(SWStage::TS))
       storage_allowed |= storage_vmem_output;
 
    /* Workgroup barriers can hang merged shaders that can potentially have 0 threads in either half.
@@ -10501,19 +10502,6 @@
    loop_context lc;
    begin_loop(ctx, &lc);
 
-   /* NIR seems to allow this, and even though the loop exit has no predecessors, SSA defs from the
-    * loop header are live. Handle this without complicating the ACO IR by creating a dummy break.
-    */
-   if (nir_cf_node_cf_tree_next(&loop->cf_node)->predecessors->entries == 0) {
-      Builder bld(ctx->program, ctx->block);
-      Temp cond = bld.copy(bld.def(s1, scc), Operand::zero());
-      if_context ic;
-      begin_uniform_if_then(ctx, &ic, cond);
-      emit_loop_break(ctx);
-      begin_uniform_if_else(ctx, &ic);
-      end_uniform_if(ctx, &ic);
-   }
-
    bool unreachable = visit_cf_list(ctx, &loop->body);
 
    unsigned loop_header_idx = ctx->cf_info.parent_loop.header_idx;
@@ -10555,6 +10543,19 @@
       }
    }
 
+   /* NIR seems to allow this, and even though the loop exit has no predecessors, SSA defs from the
+    * loop header are live. Handle this without complicating the ACO IR by creating a dummy break.
+    */
+   if (nir_cf_node_cf_tree_next(&loop->cf_node)->predecessors->entries == 0) {
+      Builder bld(ctx->program, ctx->block);
+      Temp cond = bld.copy(bld.def(s1, scc), Operand::zero());
+      if_context ic;
+      begin_uniform_if_then(ctx, &ic, cond);
+      emit_loop_break(ctx);
+      begin_uniform_if_else(ctx, &ic);
+      end_uniform_if(ctx, &ic);
+   }
+
    end_loop(ctx, &lc);
 }

_service:tar_scm:mesa-23.0.0.tar.xz/src/amd/compiler/aco_lower_to_hw_instr.cpp -> _service:tar_scm:mesa-23.0.3.tar.xz/src/amd/compiler/aco_lower_to_hw_instr.cpp Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/amd/compiler/aco_optimizer_postRA.cpp -> _service:tar_scm:mesa-23.0.3.tar.xz/src/amd/compiler/aco_optimizer_postRA.cpp Changed

@@ -109,13 +109,13 @@
          std::fill(instr_idx_by_regsblock->index.begin(), instr_idx_by_regsblock->index.end(),
                    not_written_yet);
       } else if (block->kind & block_kind_loop_header) {
-         /* Initialize with content from loop preheader */
-         memcpy(&instr_idx_by_regsblock->index0, &instr_idx_by_regsblock->index - 10,
-                max_reg_cnt * sizeof(Idx));
-
-         /* Assume exec writes on back-edges */
-         instr_idx_by_regsblock->index126 = overwritten_untrackable;
-         instr_idx_by_regsblock->index127 = overwritten_untrackable;
+         /* Instructions inside the loop may overwrite registers of temporaries that are
+          * not live inside the loop, but we can't detect that because we haven't processed
+          * the blocks in the loop yet. As a workaround, mark all registers as untrackable.
+          * TODO: Consider improving this in the future.
+          */
+         std::fill(instr_idx_by_regsblock->index.begin(), instr_idx_by_regsblock->index.end(),
+                   overwritten_untrackable);
       } else {
          reset_block_regs(block->linear_preds, block->index, 0, max_sgpr_cnt);
          reset_block_regs(block->linear_preds, block->index, 251, 3);

_service:tar_scm:mesa-23.0.0.tar.xz/src/amd/compiler/aco_reduce_assign.cpp -> _service:tar_scm:mesa-23.0.3.tar.xz/src/amd/compiler/aco_reduce_assign.cpp Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/amd/compiler/aco_register_allocation.cpp -> _service:tar_scm:mesa-23.0.3.tar.xz/src/amd/compiler/aco_register_allocation.cpp Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/amd/compiler/aco_ssa_elimination.cpp -> _service:tar_scm:mesa-23.0.3.tar.xz/src/amd/compiler/aco_ssa_elimination.cpp Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/amd/compiler/aco_validate.cpp -> _service:tar_scm:mesa-23.0.3.tar.xz/src/amd/compiler/aco_validate.cpp Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/amd/llvm/ac_llvm_build.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/amd/llvm/ac_llvm_build.c Changed

@@ -1343,23 +1343,28 @@
       if (soffset)
          offset = LLVMBuildAdd(ctx->builder, offset, soffset, "");
 
+      char name256, type_name8;
+      ac_build_type_name_for_intr(channel_type, type_name, sizeof(type_name));
+      snprintf(name, sizeof(name), "llvm.amdgcn.s.buffer.load.%s", type_name);
+
+      LLVMValueRef channel_size = LLVMConstInt(ctx->i32, ac_get_type_size(channel_type), 0);
+
       for (int i = 0; i < num_channels; i++) {
          if (i) {
-            offset = LLVMBuildAdd(ctx->builder, offset, LLVMConstInt(ctx->i32, 4, 0), "");
+            offset = LLVMBuildAdd(ctx->builder, offset, channel_size, "");
          }
          LLVMValueRef args3 = {
             rsrc,
             offset,
             LLVMConstInt(ctx->i32, get_load_cache_policy(ctx, cache_policy), 0),
          };
-         resulti = ac_build_intrinsic(ctx, "llvm.amdgcn.s.buffer.load.f32", ctx->f32, args, 3,
-                                        AC_ATTR_INVARIANT_LOAD);
+         resulti = ac_build_intrinsic(ctx, name, channel_type, args, 3, AC_ATTR_INVARIANT_LOAD);
       }
       if (num_channels == 1)
          return result0;
 
       if (num_channels == 3 && !ac_has_vec3_support(ctx->gfx_level, false))
-         resultnum_channels++ = LLVMGetUndef(ctx->f32);
+         resultnum_channels++ = LLVMGetUndef(channel_type);
       return ac_build_gather_values(ctx, result, num_channels);
    }
 
@@ -4434,43 +4439,48 @@
                                    LLVMValueRef vtx_cnt, LLVMValueRef prim_cnt)
 {
    LLVMBuilderRef builder = ctx->builder;
-   LLVMValueRef tmp;
-   bool export_dummy_prim = false;
 
-   /* HW workaround for a GPU hang with 100% culling.
+   if (wave_id)
+      ac_build_ifcc(ctx, LLVMBuildICmp(builder, LLVMIntEQ, wave_id, ctx->i32_0, ""), 5020);
+
+   /* HW workaround for a GPU hang with 100% culling on GFX10.
     * We always have to export at least 1 primitive.
     * Export a degenerate triangle using vertex 0 for all 3 vertices.
+    * 
+    * NOTE: We rely on the caller to set the vertex count also to 0 when the primitive count is 0.
     */
-   if (prim_cnt == ctx->i32_0 && ctx->gfx_level == GFX10) {
-      assert(vtx_cnt == ctx->i32_0);
-      prim_cnt = ctx->i32_1;
-      vtx_cnt = ctx->i32_1;
-      export_dummy_prim = true;
-   }
-
-   if (wave_id)
-      ac_build_ifcc(ctx, LLVMBuildICmp(builder, LLVMIntEQ, wave_id, ctx->i32_0, ""), 5020);
+   if (ctx->gfx_level == GFX10) {
+      ac_build_ifcc(ctx, LLVMBuildICmp(builder, LLVMIntEQ, ac_get_thread_id(ctx), ctx->i32_0, ""), 5021);
+      LLVMValueRef prim_cnt_is_0 = LLVMBuildICmp(builder, LLVMIntEQ, prim_cnt, ctx->i32_0, "");
+      ac_build_ifcc(ctx, prim_cnt_is_0, 5022);
+      {
+         LLVMValueRef x = LLVMBuildShl(builder, ctx->i32_1, LLVMConstInt(ctx->i32, 12, false), "");
+         x = LLVMBuildOr(builder, x, ctx->i32_1, "");
+         ac_build_sendmsg(ctx, AC_SENDMSG_GS_ALLOC_REQ, x);
+
+         /* The vertex indices are 0, 0, 0. */
+         struct ac_ngg_prim prim = {0};
+         prim.passthrough = ctx->i32_0;
+
+         /* The HW culls primitives with NaN. */
+         struct ac_export_args pos = {0};
+         pos.out0 = pos.out1 = pos.out2 = pos.out3 = LLVMConstReal(ctx->f32, NAN);
+         pos.target = V_008DFC_SQ_EXP_POS;
+         pos.enabled_channels = 0xf;
+         pos.done = true;
+
+         ac_build_export_prim(ctx, &prim);
+         ac_build_export(ctx, &pos);
+      }
+      ac_build_else(ctx, 5022);
+   }
+
+   LLVMValueRef x = LLVMBuildShl(builder, prim_cnt, LLVMConstInt(ctx->i32, 12, false), "");
+   x = LLVMBuildOr(builder, x, vtx_cnt, "");
+   ac_build_sendmsg(ctx, AC_SENDMSG_GS_ALLOC_REQ, x);
 
-   tmp = LLVMBuildShl(builder, prim_cnt, LLVMConstInt(ctx->i32, 12, false), "");
-   tmp = LLVMBuildOr(builder, tmp, vtx_cnt, "");
-   ac_build_sendmsg(ctx, AC_SENDMSG_GS_ALLOC_REQ, tmp);
-
-   if (export_dummy_prim) {
-      struct ac_ngg_prim prim = {0};
-      /* The vertex indices are 0,0,0. */
-      prim.passthrough = ctx->i32_0;
-
-      struct ac_export_args pos = {0};
-      /* The hw culls primitives with NaN. */
-      pos.out0 = pos.out1 = pos.out2 = pos.out3 = LLVMConstReal(ctx->f32, NAN);
-      pos.target = V_008DFC_SQ_EXP_POS;
-      pos.enabled_channels = 0xf;
-      pos.done = true;
-
-      ac_build_ifcc(ctx, LLVMBuildICmp(builder, LLVMIntEQ, ac_get_thread_id(ctx), ctx->i32_0, ""),
-                    5021);
-      ac_build_export_prim(ctx, &prim);
-      ac_build_export(ctx, &pos);
+   if (ctx->gfx_level == GFX10) {
+      ac_build_endif(ctx, 5022);
       ac_build_endif(ctx, 5021);
    }

_service:tar_scm:mesa-23.0.0.tar.xz/src/amd/llvm/ac_nir_to_llvm.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/amd/llvm/ac_nir_to_llvm.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/amd/registers/gfx11.json -> _service:tar_scm:mesa-23.0.3.tar.xz/src/amd/registers/gfx11.json Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/amd/registers/parse_kernel_headers.py -> _service:tar_scm:mesa-23.0.3.tar.xz/src/amd/registers/parse_kernel_headers.py Changed

@@ -711,6 +711,34 @@
     "VGT_DRAW_PAYLOAD_CNTL": "EN_VRS_RATE", 6, 6,
     "VGT_SHADER_STAGES_EN": "PRIMGEN_PASSTHRU_NO_MSG", 26, 26,
   },
+  'gfx11': {
+    "VGT_DRAW_PAYLOAD_CNTL": "EN_VRS_RATE", 6, 6,
+    # Only GFX1103_R2:
+    "CB_COLOR0_FDCC_CONTROL": "DISABLE_OVERRIDE_INCONSISTENT_KEYS", 25, 25,
+                               "ENABLE_MAX_COMP_FRAG_OVERRIDE", 26, 26,
+                               "MAX_COMP_FRAGS", 27, 29,
+    "CB_COLOR1_FDCC_CONTROL": "DISABLE_OVERRIDE_INCONSISTENT_KEYS", 25, 25,
+                               "ENABLE_MAX_COMP_FRAG_OVERRIDE", 26, 26,
+                               "MAX_COMP_FRAGS", 27, 29,
+    "CB_COLOR2_FDCC_CONTROL": "DISABLE_OVERRIDE_INCONSISTENT_KEYS", 25, 25,
+                               "ENABLE_MAX_COMP_FRAG_OVERRIDE", 26, 26,
+                               "MAX_COMP_FRAGS", 27, 29,
+    "CB_COLOR3_FDCC_CONTROL": "DISABLE_OVERRIDE_INCONSISTENT_KEYS", 25, 25,
+                               "ENABLE_MAX_COMP_FRAG_OVERRIDE", 26, 26,
+                               "MAX_COMP_FRAGS", 27, 29,
+    "CB_COLOR4_FDCC_CONTROL": "DISABLE_OVERRIDE_INCONSISTENT_KEYS", 25, 25,
+                               "ENABLE_MAX_COMP_FRAG_OVERRIDE", 26, 26,
+                               "MAX_COMP_FRAGS", 27, 29,
+    "CB_COLOR5_FDCC_CONTROL": "DISABLE_OVERRIDE_INCONSISTENT_KEYS", 25, 25,
+                               "ENABLE_MAX_COMP_FRAG_OVERRIDE", 26, 26,
+                               "MAX_COMP_FRAGS", 27, 29,
+    "CB_COLOR6_FDCC_CONTROL": "DISABLE_OVERRIDE_INCONSISTENT_KEYS", 25, 25,
+                               "ENABLE_MAX_COMP_FRAG_OVERRIDE", 26, 26,
+                               "MAX_COMP_FRAGS", 27, 29,
+    "CB_COLOR7_FDCC_CONTROL": "DISABLE_OVERRIDE_INCONSISTENT_KEYS", 25, 25,
+                               "ENABLE_MAX_COMP_FRAG_OVERRIDE", 26, 26,
+                               "MAX_COMP_FRAGS", 27, 29,
+  },
 }
 
 ######### END HARDCODED CONFIGURATION

_service:tar_scm:mesa-23.0.0.tar.xz/src/amd/vulkan/layers/radv_sqtt_layer.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/amd/vulkan/layers/radv_sqtt_layer.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/amd/vulkan/meson.build -> _service:tar_scm:mesa-23.0.3.tar.xz/src/amd/vulkan/meson.build Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/amd/vulkan/radv_cmd_buffer.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/amd/vulkan/radv_cmd_buffer.c Changed

@@ -338,6 +338,12 @@
 #undef RADV_CMP_COPY
 
    cmd_buffer->state.dirty |= dest_mask;
+
+   /* Handle driver specific states that need to be re-emitted when PSO are bound. */
+   if (dest_mask & (RADV_DYNAMIC_VIEWPORT | RADV_DYNAMIC_POLYGON_MODE | RADV_DYNAMIC_LINE_WIDTH |
+                    RADV_DYNAMIC_PRIMITIVE_TOPOLOGY)) {
+      cmd_buffer->state.dirty |= RADV_CMD_DIRTY_GUARDBAND;
+   }
 }
 
 bool
@@ -3389,6 +3395,9 @@
                             ? S_028C70_FORMAT_GFX11(V_028C70_COLOR_INVALID)
                             : S_028C70_FORMAT_GFX6(V_028C70_COLOR_INVALID);
 
+   ASSERTED unsigned cdw_max =
+      radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 48 + MAX_RTS * 70);
+
    for (i = 0; i < render->color_att_count; ++i) {
       struct radv_image_view *iview = render->color_atti.iview;
       if (!iview) {
@@ -3520,6 +3529,8 @@
       }
    }
 
+   assert(cmd_buffer->cs->cdw <= cdw_max);
+
    cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
 }
 
@@ -3687,8 +3698,8 @@
    STATIC_ASSERT(sizeof(union vs_prolog_key_header) == 4);
    assert(vs_shader->info.vs.dynamic_inputs);
 
+   const struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
    const struct radv_vs_input_state *state = &cmd_buffer->state.dynamic_vs_input;
-   struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
    struct radv_device *device = cmd_buffer->device;
 
    unsigned num_attributes = pipeline->last_vertex_attrib_bit;
@@ -3706,10 +3717,20 @@
          uint8_t binding = state->bindingsindex;
          if (!(cmd_buffer->state.vbo_bound_mask & BITFIELD_BIT(binding)))
             continue;
+
          uint8_t req = state->format_align_req_minus_1index;
-         struct radv_vertex_binding *vb = &cmd_buffer->vertex_bindingsbinding;
-         VkDeviceSize offset = vb->offset + state->offsetsindex;
-         if ((offset & req) || (vb->stride & req))
+         uint64_t vb_offset = cmd_buffer->vertex_bindingsbinding.offset;
+         uint64_t vb_stride;
+
+         if (pipeline->dynamic_states & (RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE |
+                                         RADV_DYNAMIC_VERTEX_INPUT)) {
+            vb_stride = cmd_buffer->vertex_bindingsbinding.stride;
+         } else {
+            vb_stride = pipeline->binding_stridebinding;
+         }
+
+         VkDeviceSize offset = vb_offset + state->offsetsindex;
+         if ((offset & req) || (vb_stride & req))
             misaligned_mask |= BITFIELD_BIT(index);
       }
       cmd_buffer->state.vbo_misaligned_mask = misaligned_mask;
@@ -6039,7 +6060,7 @@
       /* Flush noncoherent images on GFX9+ so we can assume they're clean on the start of a
        * command buffer.
        */
-      if (cmd_buffer->state.rb_noncoherent_dirty && can_skip_buffer_l2_flushes(cmd_buffer->device))
+      if (cmd_buffer->state.rb_noncoherent_dirty && !can_skip_buffer_l2_flushes(cmd_buffer->device))
          cmd_buffer->state.flush_bits |= radv_src_access_flush(
             cmd_buffer,
             VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT |
@@ -7149,6 +7170,8 @@
       primary->state.last_vrs_rates_sgpr_idx = secondary->state.last_vrs_rates_sgpr_idx;
 
       primary->state.last_pa_sc_binner_cntl_0 = secondary->state.last_pa_sc_binner_cntl_0;
+
+      primary->state.rb_noncoherent_dirty |= secondary->state.rb_noncoherent_dirty;
    }
 
    /* After executing commands from secondary buffers we have to dirty
@@ -7871,6 +7894,25 @@
    radv_emit_userdata_task_ib_only(cmd_buffer, ib_va, first_task ? 8 : 0);
 }
 
+/* Bind an internal index buffer for GPUs that hang with 0-sized index buffers to handle robustness2
+ * which requires 0 for out-of-bounds access.
+ */
+static void
+radv_handle_zero_index_buffer_bug(struct radv_cmd_buffer *cmd_buffer, uint64_t *index_va,
+                                  uint32_t *remaining_indexes)
+{
+   const uint32_t zero = 0;
+   uint32_t offset;
+
+   if (!radv_cmd_buffer_upload_data(cmd_buffer, sizeof(uint32_t), &zero, &offset)) {
+      vk_command_buffer_set_error(&cmd_buffer->vk, VK_ERROR_OUT_OF_HOST_MEMORY);
+      return;
+   }
+
+   *index_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + offset;
+   *remaining_indexes = 1;
+}
+
 ALWAYS_INLINE static void
 radv_emit_draw_packets_indexed(struct radv_cmd_buffer *cmd_buffer,
                                const struct radv_draw_info *info,
@@ -7891,18 +7933,17 @@
       if (vertexOffset) {
          radv_emit_userdata_vertex(cmd_buffer, info, *vertexOffset);
          vk_foreach_multi_draw_indexed(draw, i, minfo, drawCount, stride) {
-            const uint32_t remaining_indexes = MAX2(state->max_index_count, draw->firstIndex) - draw->firstIndex;
+            uint32_t remaining_indexes = MAX2(state->max_index_count, draw->firstIndex) - draw->firstIndex;
+            uint64_t index_va = state->index_va + draw->firstIndex * index_size;
 
-            /* Skip draw calls with 0-sized index buffers if the GPU can't handle them */
+            /* Handle draw calls with 0-sized index buffers if the GPU can't support them. */
             if (!remaining_indexes &&
                 cmd_buffer->device->physical_device->rad_info.has_zero_index_buffer_bug)
-               continue;
+               radv_handle_zero_index_buffer_bug(cmd_buffer, &index_va, &remaining_indexes);
 
             if (i > 0)
                radeon_set_sh_reg(cs, state->graphics_pipeline->vtx_base_sgpr + sizeof(uint32_t), i);
 
-            const uint64_t index_va = state->index_va + draw->firstIndex * index_size;
-
             if (!state->render.view_mask) {
                radv_cs_emit_draw_indexed_packet(cmd_buffer, index_va, remaining_indexes, draw->indexCount, false);
             } else {
@@ -7915,12 +7956,13 @@
          }
       } else {
          vk_foreach_multi_draw_indexed(draw, i, minfo, drawCount, stride) {
-            const uint32_t remaining_indexes = MAX2(state->max_index_count, draw->firstIndex) - draw->firstIndex;
+            uint32_t remaining_indexes = MAX2(state->max_index_count, draw->firstIndex) - draw->firstIndex;
+            uint64_t index_va = state->index_va + draw->firstIndex * index_size;
 
-            /* Skip draw calls with 0-sized index buffers if the GPU can't handle them */
+            /* Handle draw calls with 0-sized index buffers if the GPU can't support them. */
             if (!remaining_indexes &&
                 cmd_buffer->device->physical_device->rad_info.has_zero_index_buffer_bug)
-               continue;
+               radv_handle_zero_index_buffer_bug(cmd_buffer, &index_va, &remaining_indexes);
 
             if (i > 0) {
                if (state->last_vertex_offset != draw->vertexOffset)
@@ -7930,8 +7972,6 @@
             } else
                radv_emit_userdata_vertex(cmd_buffer, info, draw->vertexOffset);
 
-            const uint64_t index_va = state->index_va + draw->firstIndex * index_size;
-
             if (!state->render.view_mask) {
                radv_cs_emit_draw_indexed_packet(cmd_buffer, index_va, remaining_indexes, draw->indexCount, false);
             } else {
@@ -7962,14 +8002,13 @@
 
          radv_emit_userdata_vertex(cmd_buffer, info, *vertexOffset);
          vk_foreach_multi_draw_indexed(draw, i, minfo, drawCount, stride) {
-            const uint32_t remaining_indexes = MAX2(state->max_index_count, draw->firstIndex) - draw->firstIndex;
+            uint32_t remaining_indexes = MAX2(state->max_index_count, draw->firstIndex) - draw->firstIndex;
+            uint64_t index_va = state->index_va + draw->firstIndex * index_size;
 
-            /* Skip draw calls with 0-sized index buffers if the GPU can't handle them */
+            /* Handle draw calls with 0-sized index buffers if the GPU can't support them. */
             if (!remaining_indexes &&
                 cmd_buffer->device->physical_device->rad_info.has_zero_index_buffer_bug)
-               continue;
-
-            const uint64_t index_va = state->index_va + draw->firstIndex * index_size;
+               radv_handle_zero_index_buffer_bug(cmd_buffer, &index_va, &remaining_indexes);
 
             if (!state->render.view_mask) {
                radv_cs_emit_draw_indexed_packet(cmd_buffer, index_va, remaining_indexes, draw->indexCount, can_eop && i < drawCount - 1);
@@ -7983,19 +8022,18 @@
          }
       } else {
          vk_foreach_multi_draw_indexed(draw, i, minfo, drawCount, stride) {
-            const uint32_t remaining_indexes = MAX2(state->max_index_count, draw->firstIndex) - draw->firstIndex;
+            uint32_t remaining_indexes = MAX2(state->max_index_count, draw->firstIndex) - draw->firstIndex;
+            uint64_t index_va = state->index_va + draw->firstIndex * index_size;
 
-            /* Skip draw calls with 0-sized index buffers if the GPU can't handle them */
+            /* Handle draw calls with 0-sized index buffers if the GPU can't support them. */
             if (!remaining_indexes &&
                 cmd_buffer->device->physical_device->rad_info.has_zero_index_buffer_bug)
-               continue;
+               radv_handle_zero_index_buffer_bug(cmd_buffer, &index_va, &remaining_indexes);
 
             const VkMultiDrawIndexedInfoEXT *next = (const VkMultiDrawIndexedInfoEXT*)(i < drawCount - 1 ? ((uint8_t*)draw + stride) : NULL);
             const bool offset_changes = next && next->vertexOffset != draw->vertexOffset;
             radv_emit_userdata_vertex(cmd_buffer, info, draw->vertexOffset);
 
-            const uint64_t index_va = state->index_va + draw->firstIndex * index_size;
-
             if (!state->render.view_mask) {

_service:tar_scm:mesa-23.0.0.tar.xz/src/amd/vulkan/radv_formats.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/amd/vulkan/radv_formats.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/amd/vulkan/radv_image.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/amd/vulkan/radv_image.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/amd/vulkan/radv_pipeline.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/amd/vulkan/radv_pipeline.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/amd/vulkan/radv_query.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/amd/vulkan/radv_query.c Changed

@@ -605,6 +605,9 @@
    return b.shader;
 }
 
+#define RADV_PGQ_STRIDE 32
+#define RADV_PGQ_STRIDE_GDS (RADV_PGQ_STRIDE + 4 * 2)
+
 static nir_shader *
 build_pg_query_shader(struct radv_device *device)
 {
@@ -665,8 +668,12 @@
    /* Compute global ID. */
    nir_ssa_def *global_id = get_global_ids(&b, 1);
 
+   /* Determine if the query pool uses GDS for NGG. */
+   nir_ssa_def *uses_gds =
+      nir_i2b(&b, nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 16), .range = 20));
+
    /* Compute src/dst strides. */
-   nir_ssa_def *input_stride = nir_imm_int(&b, 32);
+   nir_ssa_def *input_stride = nir_bcsel(&b, uses_gds, nir_imm_int(&b, RADV_PGQ_STRIDE_GDS), nir_imm_int(&b, RADV_PGQ_STRIDE));
    nir_ssa_def *input_base = nir_imul(&b, input_stride, global_id);
    nir_ssa_def *output_stride = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 4), .range = 16);
    nir_ssa_def *output_base = nir_imul(&b, output_stride, global_id);
@@ -698,8 +705,7 @@
 
    nir_store_var(&b, result, primitive_storage_needed, 0x1);
 
-   nir_ssa_def *uses_gds = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 16), .range = 20);
-   nir_push_if(&b, nir_i2b(&b, uses_gds));
+   nir_push_if(&b, uses_gds);
    {
       nir_ssa_def *gds_start =
          nir_load_ssbo(&b, 1, 32, src_buf, nir_iadd(&b, input_base, nir_imm_int(&b, 32)), .align_mul = 4);
@@ -1124,12 +1130,13 @@
       pool->stride = 32;
       break;
    case VK_QUERY_TYPE_PRIMITIVES_GENERATED_EXT:
-      pool->stride = 32;
       if (pool->uses_gds && device->physical_device->rad_info.gfx_level < GFX11) {
          /* When the hardware can use both the legacy and the NGG paths in the same begin/end pair,
           * allocate 2x32-bit values for the GDS counters.
           */
-         pool->stride += 4 * 2;
+         pool->stride = RADV_PGQ_STRIDE_GDS;
+      } else {
+         pool->stride = RADV_PGQ_STRIDE;
       }
       break;
    case VK_QUERY_TYPE_PERFORMANCE_QUERY_KHR: {

_service:tar_scm:mesa-23.0.0.tar.xz/src/amd/vulkan/radv_rt_shader.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/amd/vulkan/radv_rt_shader.c Changed

@@ -765,6 +765,48 @@
 }
 
 static void
+inline_constants(nir_shader *dst, nir_shader *src)
+{
+   if (!src->constant_data_size)
+      return;
+
+   uint32_t align_mul = 1;
+   if (dst->constant_data_size) {
+      nir_foreach_block (block, nir_shader_get_entrypoint(src)) {
+         nir_foreach_instr (instr, block) {
+            if (instr->type != nir_instr_type_intrinsic)
+               continue;
+
+            nir_intrinsic_instr *intrinsic = nir_instr_as_intrinsic(instr);
+            if (intrinsic->intrinsic == nir_intrinsic_load_constant)
+               align_mul = MAX2(align_mul, nir_intrinsic_align_mul(intrinsic));
+         }
+      }
+   }
+
+   uint32_t old_constant_data_size = dst->constant_data_size;
+   uint32_t base_offset = align(dst->constant_data_size, align_mul);
+   dst->constant_data_size = base_offset + src->constant_data_size;
+   dst->constant_data =
+      rerzalloc_size(dst, dst->constant_data, old_constant_data_size, dst->constant_data_size);
+   memcpy((char *)dst->constant_data + base_offset, src->constant_data, src->constant_data_size);
+
+   if (!base_offset)
+      return;
+
+   nir_foreach_block (block, nir_shader_get_entrypoint(src)) {
+      nir_foreach_instr (instr, block) {
+         if (instr->type != nir_instr_type_intrinsic)
+            continue;
+
+         nir_intrinsic_instr *intrinsic = nir_instr_as_intrinsic(instr);
+         if (intrinsic->intrinsic == nir_intrinsic_load_constant)
+            nir_intrinsic_set_base(intrinsic, base_offset + nir_intrinsic_base(intrinsic));
+      }
+   }
+}
+
+static void
 insert_rt_case(nir_builder *b, nir_shader *shader, struct rt_variables *vars, nir_ssa_def *idx,
                uint32_t call_idx_base, uint32_t call_idx)
 {
@@ -784,6 +826,8 @@
 
    reserve_stack_size(vars, shader->scratch_size);
 
+   inline_constants(b->shader, shader);
+
    nir_push_if(b, nir_ieq_imm(b, idx, call_idx));
    nir_inline_function_impl(b, nir_shader_get_entrypoint(shader), NULL, var_remap);
    nir_pop_if(b, NULL);
@@ -855,6 +899,11 @@
          .num_components = 1,
          .bit_size = 32,
       },
+      {
+         /* Scratch offset */
+         .num_components = 1,
+         .bit_size = 32,
+      },
    };
    impl->function->num_params = ARRAY_SIZE(params);
    impl->function->params = ralloc_array(any_hit, nir_parameter, ARRAY_SIZE(params));
@@ -869,6 +918,7 @@
    nir_ssa_def *commit_ptr = nir_load_param(b, 0);
    nir_ssa_def *hit_t = nir_load_param(b, 1);
    nir_ssa_def *hit_kind = nir_load_param(b, 2);
+   nir_ssa_def *scratch_offset = nir_load_param(b, 3);
 
    nir_deref_instr *commit =
       nir_build_deref_cast(b, commit_ptr, nir_var_function_temp, glsl_bool_type(), 0);
@@ -908,6 +958,26 @@
                nir_instr_remove(&intrin->instr);
                break;
 
+            /* We place all any_hit scratch variables after intersection scratch variables.
+             * For that reason, we increment the scratch offset by the intersection scratch
+             * size. For call_data, we have to subtract the offset again.
+             */
+            case nir_intrinsic_load_scratch:
+               b->cursor = nir_before_instr(instr);
+               nir_instr_rewrite_src_ssa(instr, &intrin->src0,
+                                         nir_iadd_nuw(b, scratch_offset, intrin->src0.ssa));
+               break;
+            case nir_intrinsic_store_scratch:
+               b->cursor = nir_before_instr(instr);
+               nir_instr_rewrite_src_ssa(instr, &intrin->src1,
+                                         nir_iadd_nuw(b, scratch_offset, intrin->src1.ssa));
+               break;
+            case nir_intrinsic_load_rt_arg_scratch_offset_amd:
+               b->cursor = nir_after_instr(instr);
+               nir_ssa_def *arg_offset = nir_isub(b, &intrin->dest.ssa, scratch_offset);
+               nir_ssa_def_rewrite_uses_after(&intrin->dest.ssa, arg_offset, arg_offset->parent_instr);
+               break;
+
             default:
                break;
             }
@@ -950,6 +1020,9 @@
    if (any_hit) {
       any_hit = nir_shader_clone(dead_ctx, any_hit);
       NIR_PASS(_, any_hit, nir_opt_dce);
+
+      inline_constants(intersection, any_hit);
+
       any_hit_impl = lower_any_hit_for_intersection(any_hit);
       any_hit_var_remap = _mesa_pointer_hash_table_create(dead_ctx);
    }
@@ -996,6 +1069,7 @@
                      &nir_build_deref_var(b, commit_tmp)->dest.ssa,
                      hit_t,
                      hit_kind,
+                     nir_imm_int(b, intersection->scratch_size),
                   };
                   nir_inline_function_impl(b, any_hit_impl, params, any_hit_var_remap);
                }
@@ -1014,7 +1088,8 @@
          nir_ssa_def_rewrite_uses(&intrin->dest.ssa, accepted);
       }
    }
-
+   /* Any-hit scratch variables are placed after intersection scratch variables. */
+   intersection->scratch_size += any_hit->scratch_size;
    nir_metadata_preserve(impl, nir_metadata_none);
 
    /* We did some inlining; have to re-index SSA defs */

_service:tar_scm:mesa-23.0.0.tar.xz/src/amd/vulkan/radv_sdma_copy_image.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/amd/vulkan/radv_sdma_copy_image.c Changed

_service:tar_scm:mesa-23.0.3.tar.xz/src/amd/vulkan/vulkan-android.sym Added

_service:tar_scm:mesa-23.0.0.tar.xz/src/amd/vulkan/vulkan.sym -> _service:tar_scm:mesa-23.0.3.tar.xz/src/amd/vulkan/vulkan.sym Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c Changed

@@ -119,13 +119,7 @@
 ring_can_use_ib_bos(const struct radv_amdgpu_winsys *ws,
                     enum amd_ip_type ip_type)
 {
-   if (ip_type == AMD_IP_UVD ||
-       ip_type == AMD_IP_VCE ||
-       ip_type == AMD_IP_UVD_ENC ||
-       ip_type == AMD_IP_VCN_DEC ||
-       ip_type == AMD_IP_VCN_ENC)
-      return false;
-   return ws->use_ib_bos;
+   return ws->use_ib_bos && (ip_type == AMD_IP_GFX || ip_type == AMD_IP_COMPUTE);
 }
 
 struct radv_amdgpu_cs_request {
@@ -161,9 +155,9 @@
    uint64_t seq_no;
 };
 
-static int radv_amdgpu_cs_submit(struct radv_amdgpu_ctx *ctx,
-                                 struct radv_amdgpu_cs_request *request,
-                                 struct radv_winsys_sem_info *sem_info);
+static VkResult radv_amdgpu_cs_submit(struct radv_amdgpu_ctx *ctx,
+                                      struct radv_amdgpu_cs_request *request,
+                                      struct radv_winsys_sem_info *sem_info);
 
 static void
 radv_amdgpu_request_to_fence(struct radv_amdgpu_ctx *ctx, struct radv_amdgpu_fence *fence,
@@ -240,7 +234,7 @@
 
    if (cs->use_ib) {
       VkResult result =
-         ws->buffer_create(ws, ib_size, 0, radv_amdgpu_cs_domain(ws),
+         ws->buffer_create(ws, ib_size, cs->ws->info.ib_alignment, radv_amdgpu_cs_domain(ws),
                            RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING |
                               RADEON_FLAG_READ_ONLY | RADEON_FLAG_GTT_WC,
                            RADV_BO_PRIORITY_CS, 0, &cs->ib_buffer);
@@ -387,11 +381,11 @@
    /* max that fits in the chain size field. */
    ib_size = align(MIN2(ib_size, 0xfffff), ib_pad_dw_mask + 1);
 
-   VkResult result =
-      cs->ws->base.buffer_create(&cs->ws->base, ib_size, 0, radv_amdgpu_cs_domain(&cs->ws->base),
-                                 RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING |
-                                    RADEON_FLAG_READ_ONLY | RADEON_FLAG_GTT_WC,
-                                 RADV_BO_PRIORITY_CS, 0, &cs->ib_buffer);
+   VkResult result = cs->ws->base.buffer_create(
+      &cs->ws->base, ib_size, cs->ws->info.ib_alignment, radv_amdgpu_cs_domain(&cs->ws->base),
+      RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING | RADEON_FLAG_READ_ONLY |
+         RADEON_FLAG_GTT_WC,
+      RADV_BO_PRIORITY_CS, 0, &cs->ib_buffer);
 
    if (result != VK_SUCCESS) {
       cs->base.cdw = 0;
@@ -1121,10 +1115,10 @@
                pad_words++;
             }
 
-            ws->buffer_create(
-               ws, 4 * size, 4096, radv_amdgpu_cs_domain(ws),
-               RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING | RADEON_FLAG_READ_ONLY |
-               RADEON_FLAG_GTT_WC, RADV_BO_PRIORITY_CS, 0, &bosj);
+            ws->buffer_create(ws, 4 * size, cs->ws->info.ib_alignment, radv_amdgpu_cs_domain(ws),
+                              RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING |
+                                 RADEON_FLAG_READ_ONLY | RADEON_FLAG_GTT_WC,
+                              RADV_BO_PRIORITY_CS, 0, &bosj);
             ptr = ws->buffer_map(bosj);
 
             if (needs_preamble) {
@@ -1165,10 +1159,10 @@
          }
          assert(cnt);
 
-         ws->buffer_create(
-            ws, 4 * size, 4096, radv_amdgpu_cs_domain(ws),
-            RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING | RADEON_FLAG_READ_ONLY |
-            RADEON_FLAG_GTT_WC, RADV_BO_PRIORITY_CS, 0, &bos0);
+         ws->buffer_create(ws, 4 * size, cs->ws->info.ib_alignment, radv_amdgpu_cs_domain(ws),
+                           RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING |
+                              RADEON_FLAG_READ_ONLY | RADEON_FLAG_GTT_WC,
+                           RADV_BO_PRIORITY_CS, 0, &bos0);
          ptr = ws->buffer_map(bos0);
 
          if (preamble_cs) {

_service:tar_scm:mesa-23.0.0.tar.xz/src/compiler/glsl/ast_to_hir.cpp -> _service:tar_scm:mesa-23.0.3.tar.xz/src/compiler/glsl/ast_to_hir.cpp Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/compiler/glsl/ir_expression_operation.py -> _service:tar_scm:mesa-23.0.3.tar.xz/src/compiler/glsl/ir_expression_operation.py Changed

@@ -22,6 +22,7 @@
 
 import mako.template
 import sys
+import itertools
 
 class type(object):
    def __init__(self, c_type, union_field, glsl_type):
@@ -112,20 +113,10 @@
       break;""")
 
 # This template is for binary operations that can operate on some combination
-# of scalar and vector operands.
+# of scalar and vector operands where both source types are the same.
 constant_template_vector_scalar = mako.template.Template("""\
    case ${op.get_enum_name()}:
-    % if "mixed" in op.flags:
-        % for i in range(op.num_operands):
-      assert(op${i}->type->base_type == ${op.source_types0.glsl_type} ||
-            % for src_type in op.source_types1:-1:
-             op${i}->type->base_type == ${src_type.glsl_type} ||
-            % endfor
-             op${i}->type->base_type == ${op.source_types-1.glsl_type});
-        % endfor
-    % else:
       assert(op0->type == op1->type || op0_scalar || op1_scalar);
-    % endif
       for (unsigned c = 0, c0 = 0, c1 = 0;
            c < components;
            c0 += c0_inc, c1 += c1_inc, c++) {
@@ -142,6 +133,41 @@
       }
       break;""")
 
+# This template is for binary operations that can operate on some combination
+# of scalar and vector operands where the source types can be mixed.
+constant_template_vector_scalar_mixed = mako.template.Template("""\
+   case ${op.get_enum_name()}:
+        % for i in range(op.num_operands):
+      assert(op${i}->type->base_type == ${op.source_types0.glsl_type} ||
+            % for src_type in op.source_types1:-1:
+             op${i}->type->base_type == ${src_type.glsl_type} ||
+            % endfor
+             op${i}->type->base_type == ${op.source_types-1.glsl_type});
+        % endfor
+      for (unsigned c = 0, c0 = 0, c1 = 0;
+           c < components;
+           c0 += c0_inc, c1 += c1_inc, c++) {
+         <%
+           first_sig_dst_type, first_sig_src_types = op.signatures()0
+           last_sig_dst_type, last_sig_src_types = op.signatures()-1
+         %>
+         if (op0->type->base_type == ${first_sig_src_types0.glsl_type} &&
+             op1->type->base_type == ${first_sig_src_types1.glsl_type}) {
+            data.${first_sig_dst_type.union_field}c = ${op.get_c_expression(first_sig_src_types, ("c0", "c1", "c2"))};
+    % for dst_type, src_types in op.signatures()1:-1:
+         } else if (op0->type->base_type == ${src_types0.glsl_type} &&
+                    op1->type->base_type == ${src_types1.glsl_type}) {
+            data.${dst_type.union_field}c = ${op.get_c_expression(src_types, ("c0", "c1", "c2"))};
+    % endfor
+         } else if (op0->type->base_type == ${last_sig_src_types0.glsl_type} &&
+                    op1->type->base_type == ${last_sig_src_types1.glsl_type}) {
+            data.${last_sig_dst_type.union_field}c = ${op.get_c_expression(last_sig_src_types, ("c0", "c1", "c2"))};
+         } else {
+            unreachable("invalid types");
+         }
+      }
+      break;""")
+
 # This template is for multiplication.  It is unique because it has to support
 # matrix * vector and matrix * matrix operations, and those are just different.
 constant_template_mul = mako.template.Template("""\
@@ -378,7 +404,10 @@
          elif self.name == "vector_extract":
             return constant_template_vector_extract.render(op=self)
          elif vector_scalar_operation in self.flags:
-            return constant_template_vector_scalar.render(op=self)
+            if mixed_type_operation in self.flags:
+               return constant_template_vector_scalar_mixed.render(op=self)
+            else:
+               return constant_template_vector_scalar.render(op=self)
       elif self.num_operands == 3:
          if self.name == "vector_insert":
             return constant_template_vector_insert.render(op=self)
@@ -663,8 +692,12 @@
    operation("any_nequal", 2, source_types=all_types, dest_type=bool_type, c_expression="!op0->has_value(op1)", flags=frozenset((horizontal_operation, types_identical_operation))),
 
    # Bit-wise binary operations.
-   operation("lshift", 2, printable_name="<<", source_types=integer_types, c_expression="{src0} << {src1}", flags=frozenset((vector_scalar_operation, mixed_type_operation))),
-   operation("rshift", 2, printable_name=">>", source_types=integer_types, c_expression="{src0} >> {src1}", flags=frozenset((vector_scalar_operation, mixed_type_operation))),
+   operation("lshift", 2,
+             printable_name="<<", all_signatures=list((src_sig0, src_sig) for src_sig in itertools.product(integer_types, repeat=2)),
+             source_types=integer_types, c_expression="{src0} << {src1}", flags=frozenset((vector_scalar_operation, mixed_type_operation))),
+   operation("rshift", 2,
+             printable_name=">>", all_signatures=list((src_sig0, src_sig) for src_sig in itertools.product(integer_types, repeat=2)),
+             source_types=integer_types, c_expression="{src0} >> {src1}", flags=frozenset((vector_scalar_operation, mixed_type_operation))),
    operation("bit_and", 2, printable_name="&", source_types=integer_types, c_expression="{src0} & {src1}", flags=vector_scalar_operation),
    operation("bit_xor", 2, printable_name="^", source_types=integer_types, c_expression="{src0} ^ {src1}", flags=vector_scalar_operation),
    operation("bit_or", 2, printable_name="|", source_types=integer_types, c_expression="{src0} | {src1}", flags=vector_scalar_operation),

_service:tar_scm:mesa-23.0.0.tar.xz/src/compiler/glsl/ir_validate.cpp -> _service:tar_scm:mesa-23.0.3.tar.xz/src/compiler/glsl/ir_validate.cpp Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/compiler/nir/nir_builder.h -> _service:tar_scm:mesa-23.0.3.tar.xz/src/compiler/nir/nir_builder.h Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/compiler/nir/nir_deref.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/compiler/nir/nir_deref.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/compiler/nir/nir_lower_image.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/compiler/nir/nir_lower_image.c Changed

@@ -61,6 +61,25 @@
    nir_instr_free(&intrin->instr);
 }
 
+/* Adjust the sample index according to AMD FMASK (fragment mask).
+ *
+ * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
+ * which is the identity mapping. Each nibble says which physical sample
+ * should be fetched to get that sample.
+ *
+ * For example, 0x11111100 means there are only 2 samples stored and
+ * the second sample covers 3/4 of the pixel. When reading samples 0
+ * and 1, return physical sample 0 (determined by the first two 0s
+ * in FMASK), otherwise return physical sample 1.
+ *
+ * The sample index should be adjusted as follows:
+ *   sample_index = ubfe(fmask, sample_index * 4, 3);
+ *
+ * Only extract 3 bits because EQAA can generate number 8 in FMASK, which
+ * means the physical sample index is unknown. We can map 8 to any valid
+ * sample index, and extracting only 3 bits will map it to 0, which works
+ * with all MSAA modes.
+ */
 static void
 lower_image_to_fragment_mask_load(nir_builder *b, nir_intrinsic_instr *intrin)
 {
@@ -96,7 +115,7 @@
    /* extract real color buffer index from fmask buffer */
    nir_ssa_def *sample_index_old = intrin->src2.ssa;
    nir_ssa_def *fmask_offset = nir_ishl_imm(b, sample_index_old, 2);
-   nir_ssa_def *fmask_width = nir_imm_int(b, 4);
+   nir_ssa_def *fmask_width = nir_imm_int(b, 3);
    nir_ssa_def *sample_index_new = nir_ubfe(b, fmask, fmask_offset, fmask_width);
 
    /* fix color buffer load */

_service:tar_scm:mesa-23.0.0.tar.xz/src/compiler/nir/nir_lower_shader_calls.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/compiler/nir/nir_lower_shader_calls.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/compiler/nir/nir_lower_tex.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/compiler/nir/nir_lower_tex.c Changed

@@ -1262,6 +1262,25 @@
    nir_ssa_def_rewrite_uses_after(&tex->dest.ssa, size, size->parent_instr);
 }
 
+/* Adjust the sample index according to AMD FMASK (fragment mask).
+ *
+ * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
+ * which is the identity mapping. Each nibble says which physical sample
+ * should be fetched to get that sample.
+ *
+ * For example, 0x11111100 means there are only 2 samples stored and
+ * the second sample covers 3/4 of the pixel. When reading samples 0
+ * and 1, return physical sample 0 (determined by the first two 0s
+ * in FMASK), otherwise return physical sample 1.
+ *
+ * The sample index should be adjusted as follows:
+ *   sample_index = ubfe(fmask, sample_index * 4, 3);
+ *
+ * Only extract 3 bits because EQAA can generate number 8 in FMASK, which
+ * means the physical sample index is unknown. We can map 8 to any valid
+ * sample index, and extracting only 3 bits will map it to 0, which works
+ * with all MSAA modes.
+ */
 static void
 nir_lower_ms_txf_to_fragment_fetch(nir_builder *b, nir_tex_instr *tex)
 {
@@ -1295,16 +1314,8 @@
    int ms_index = nir_tex_instr_src_index(tex, nir_tex_src_ms_index);
    assert(ms_index >= 0);
    nir_src sample = tex->srcms_index.src;
-   nir_ssa_def *new_sample = NULL;
-   if (nir_src_is_const(sample) && (nir_src_as_uint(sample) == 0 || nir_src_as_uint(sample) == 7)) {
-      if (nir_src_as_uint(sample) == 7)
-         new_sample = nir_ushr(b, &fmask_fetch->dest.ssa, nir_imm_int(b, 28));
-      else
-         new_sample = nir_iand_imm(b, &fmask_fetch->dest.ssa, 0xf);
-   } else {
-      new_sample = nir_ubitfield_extract(b, &fmask_fetch->dest.ssa,
-                                         nir_imul_imm(b, sample.ssa, 4), nir_imm_int(b, 4));
-   }
+   nir_ssa_def *new_sample = nir_ubfe(b, &fmask_fetch->dest.ssa,
+                                      nir_ishl_imm(b, sample.ssa, 2), nir_imm_int(b, 3));
 
    /* Update instruction. */
    tex->op = nir_texop_fragment_fetch_amd;

_service:tar_scm:mesa-23.0.0.tar.xz/src/compiler/nir/nir_opt_algebraic.py -> _service:tar_scm:mesa-23.0.3.tar.xz/src/compiler/nir/nir_opt_algebraic.py Changed

@@ -964,18 +964,18 @@
 
        (('fadd', ('b2f{}'.format(s), ('flt', 0.0, 'a@{}'.format(s))), ('fneg', ('b2f{}'.format(s), ('flt', 'a@{}'.format(s), 0.0)))), ('fsign', a), '!options->lower_fsign'),
        (('iadd', ('b2i{}'.format(s), ('flt', 0, 'a@{}'.format(s))), ('ineg', ('b2i{}'.format(s), ('flt', 'a@{}'.format(s), 0)))), ('f2i{}'.format(s), ('fsign', a)), '!options->lower_fsign'),
-    )
 
-    # float? -> float? -> floatS ==> float? -> floatS
-    (('~f2f{}'.format(s), ('f2f', a)), ('f2f{}'.format(s), a)),
+       # float? -> float? -> floatS ==> float? -> floatS
+       (('~f2f{}'.format(s), ('f2f', a)), ('f2f{}'.format(s), a)),
 
-    # int? -> float? -> floatS ==> int? -> floatS
-    (('~f2f{}'.format(s), ('u2f', a)), ('u2f{}'.format(s), a)),
-    (('~f2f{}'.format(s), ('i2f', a)), ('i2f{}'.format(s), a)),
-
-    # float? -> float? -> intS ==> float? -> intS
-    (('~f2u{}'.format(s), ('f2f', a)), ('f2u{}'.format(s), a)),
-    (('~f2i{}'.format(s), ('f2f', a)), ('f2i{}'.format(s), a)),
+       # int? -> float? -> floatS ==> int? -> floatS
+       (('~f2f{}'.format(s), ('u2f', a)), ('u2f{}'.format(s), a)),
+       (('~f2f{}'.format(s), ('i2f', a)), ('i2f{}'.format(s), a)),
+
+       # float? -> float? -> intS ==> float? -> intS
+       (('~f2u{}'.format(s), ('f2f', a)), ('f2u{}'.format(s), a)),
+       (('~f2i{}'.format(s), ('f2f', a)), ('f2i{}'.format(s), a)),
+    )
 
     for B in 32, 64:
         if s < B:
@@ -986,11 +986,6 @@
                (('i2i{}'.format(s), ('i2i{}'.format(B), 'a@{}'.format(s))), a),
                (('u2u{}'.format(s), ('u2u{}'.format(B), 'a@{}'.format(s))), a),
 
-               # bool1 -> typeB -> typeS ==> bool1 -> typeS
-               (('f2f{}'.format(s), ('b2f{}'.format(B), 'a@1')), ('b2f{}'.format(s), a)),
-               (('i2i{}'.format(s), ('b2i{}'.format(B), 'a@1')), ('b2i{}'.format(s), a)),
-               (('u2u{}'.format(s), ('b2i{}'.format(B), 'a@1')), ('b2i{}'.format(s), a)),
-
                # floatS -> floatB -> intB ==> floatS -> intB
                (('f2u{}'.format(B), ('f2f{}'.format(B), 'a@{}'.format(s))), ('f2u{}'.format(B), a)),
                (('f2i{}'.format(B), ('f2f{}'.format(B), 'a@{}'.format(s))), ('f2i{}'.format(B), a)),

_service:tar_scm:mesa-23.0.0.tar.xz/src/compiler/nir/nir_passthrough_gs.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/compiler/nir/nir_passthrough_gs.c Changed

@@ -49,7 +49,7 @@
 
    nir_variable *in_varsVARYING_SLOT_MAX;
    nir_variable *out_varsVARYING_SLOT_MAX;
-   unsigned num_vars = 0;
+   unsigned num_inputs = 0, num_outputs = 0;
 
    /* Create input/output variables. */
    nir_foreach_shader_out_variable(var, prev_stage) {
@@ -72,6 +72,15 @@
       in->data.interpolation = var->data.interpolation;
       in->data.compact = var->data.compact;
 
+      in_varsnum_inputs++ = in;
+
+      nir->num_inputs++;
+      if (in->data.location == VARYING_SLOT_EDGE)
+         continue;
+
+      if (var->data.location != VARYING_SLOT_POS)
+         nir->num_outputs++;
+
       if (var->name)
          snprintf(name, sizeof(name), "out_%s", var->name);
       else
@@ -85,17 +94,38 @@
       out->data.interpolation = var->data.interpolation;
       out->data.compact = var->data.compact;
 
-      in_varsnum_vars = in;
-      out_varsnum_vars++ = out;
+      out_varsnum_outputs++ = out;
+   }
+
+   unsigned int start_vert = 0;
+   unsigned int end_vert = vertices;
+   unsigned int vert_step = 1;
+   switch (primitive_type) {
+   case PIPE_PRIM_LINES_ADJACENCY:
+   case PIPE_PRIM_LINE_STRIP_ADJACENCY:
+      start_vert = 1;
+      end_vert += 1;
+      break;
+   case PIPE_PRIM_TRIANGLES_ADJACENCY:
+   case PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY:
+      end_vert = 5;
+      vert_step = 2;
+      break;
+   default:
+      break;
    }
 
-   for (unsigned i = 0; i < vertices; ++i) {
+   for (unsigned i = start_vert; i < end_vert; i += vert_step) {
       /* Copy inputs to outputs. */
-      for (unsigned j = 0; j < num_vars; ++j) {
+      for (unsigned j = 0, oj = 0; j < num_inputs; ++j) {
+         if (in_varsj->data.location == VARYING_SLOT_EDGE) {
+            continue;
+         }
          /* no need to use copy_var to save a lower pass */
          nir_ssa_def *value = nir_load_array_var_imm(&b, in_varsj, i);
-         nir_store_var(&b, out_varsj, value,
+         nir_store_var(&b, out_varsoj, value,
                        (1u << value->num_components) - 1);
+         ++oj;
       }
       nir_emit_vertex(&b, 0);
    }

_service:tar_scm:mesa-23.0.0.tar.xz/src/egl/drivers/dri2/platform_wayland.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/egl/drivers/dri2/platform_wayland.c Changed

@@ -1522,15 +1522,6 @@
    if (!dri2_surf->wl_win)
       return _eglError(EGL_BAD_NATIVE_WINDOW, "dri2_swap_buffers");
 
-   while (dri2_surf->throttle_callback != NULL)
-      if (wl_display_dispatch_queue(dri2_dpy->wl_dpy,
-                                    dri2_surf->wl_queue) == -1)
-         return -1;
-
-   for (int i = 0; i < ARRAY_SIZE(dri2_surf->color_buffers); i++)
-      if (dri2_surf->color_buffersi.age > 0)
-         dri2_surf->color_buffersi.age++;
-
    /* Flush (and finish glthread) before:
     *   - update_buffers_if_needed because the unmarshalling thread
     *     may be running currently, and we would concurrently alloc/free
@@ -1538,10 +1529,21 @@
     *   - swapping current/back because flushing may free the buffer and
     *     dri_image and reallocate them using get_back_bo (which causes a
     *     a crash because 'current' becomes NULL).
+    *   - using any wl_* function because accessing them from this thread
+    *     and glthread causes troubles (see #7624 and #8136)
     */
    dri2_flush_drawable_for_swapbuffers(disp, draw);
    dri2_dpy->flush->invalidate(dri2_surf->dri_drawable);
 
+   while (dri2_surf->throttle_callback != NULL)
+      if (wl_display_dispatch_queue(dri2_dpy->wl_dpy,
+                                    dri2_surf->wl_queue) == -1)
+         return -1;
+
+   for (int i = 0; i < ARRAY_SIZE(dri2_surf->color_buffers); i++)
+      if (dri2_surf->color_buffersi.age > 0)
+         dri2_surf->color_buffersi.age++;
+
    /* Make sure we have a back buffer in case we're swapping without ever
     * rendering. */
    if (update_buffers_if_needed(dri2_surf) < 0)

_service:tar_scm:mesa-23.0.0.tar.xz/src/egl/main/egldevice.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/egl/main/egldevice.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/freedreno/ci/traces-freedreno.yml -> _service:tar_scm:mesa-23.0.3.tar.xz/src/freedreno/ci/traces-freedreno.yml Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/freedreno/vulkan/tu_cmd_buffer.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/freedreno/vulkan/tu_cmd_buffer.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/freedreno/vulkan/tu_formats.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/freedreno/vulkan/tu_formats.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/auxiliary/driver_trace/tr_dump.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/auxiliary/driver_trace/tr_dump.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/auxiliary/gallivm/lp_bld_nir.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/auxiliary/gallivm/lp_bld_nir.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/auxiliary/gallivm/lp_bld_nir_soa.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/auxiliary/gallivm/lp_bld_nir_soa.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/auxiliary/indices/u_primconvert.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/auxiliary/indices/u_primconvert.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/auxiliary/util/u_threaded_context.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/auxiliary/util/u_threaded_context.c Changed

@@ -118,7 +118,7 @@
 
 /* ensure the batch's array of renderpass data is large enough for the current index */
 static void
-tc_batch_renderpass_infos_resize(struct tc_batch *batch)
+tc_batch_renderpass_infos_resize(struct threaded_context *tc, struct tc_batch *batch)
 {
    unsigned size = batch->renderpass_infos.capacity;
    unsigned cur_num = batch->renderpass_info_idx;
@@ -126,6 +126,10 @@
    if (size / sizeof(struct tc_renderpass_info) > cur_num)
       return;
 
+   struct tc_renderpass_info *infos = batch->renderpass_infos.data;
+   unsigned old_idx = batch->renderpass_info_idx - 1;
+   bool redo = tc->renderpass_info_recording &&
+               tc->renderpass_info_recording == &infosold_idx;
    if (!util_dynarray_resize(&batch->renderpass_infos, struct tc_renderpass_info, cur_num + 10))
       mesa_loge("tc: memory alloc fail!");
 
@@ -136,9 +140,12 @@
       unsigned start = size / sizeof(struct tc_renderpass_info);
       unsigned count = (batch->renderpass_infos.capacity - size) /
                        sizeof(struct tc_renderpass_info);
-      struct tc_renderpass_info *infos = batch->renderpass_infos.data;
+      infos = batch->renderpass_infos.data;
       for (unsigned i = 0; i < count; i++)
          util_queue_fence_init(&infosstart + i.ready);
+      /* re-set current recording info on resize */
+      if (redo)
+         tc->renderpass_info_recording = &infosold_idx;
    }
 }
 
@@ -164,7 +171,7 @@
    tc_signal_renderpass_info_ready(tc);
    /* increment rp info and initialize it */
    batch->renderpass_info_idx++;
-   tc_batch_renderpass_infos_resize(batch);
+   tc_batch_renderpass_infos_resize(tc, batch);
    tc_info = batch->renderpass_infos.data;
 
    if (full_copy) {
@@ -4340,8 +4347,13 @@
       if (info) {
          /* full clears use a different load operation, but are only valid if draws haven't occurred yet */
          info->cbuf_clear |= (buffers >> 2) & ~info->cbuf_load;
-         if (buffers & PIPE_CLEAR_DEPTHSTENCIL && !info->zsbuf_load && !info->zsbuf_clear_partial)
-            info->zsbuf_clear = true;
+         if (buffers & PIPE_CLEAR_DEPTHSTENCIL) {
+            if (!info->zsbuf_load && !info->zsbuf_clear_partial)
+               info->zsbuf_clear = true;
+            else if (!info->zsbuf_clear)
+               /* this is a clear that occurred after a draw: flag as partial to ensure it isn't ignored */
+               info->zsbuf_clear_partial = true;
+         }
       }
    }
    p->scissor_state_set = !!scissor_state;
@@ -4858,7 +4870,7 @@
       tc->batch_slotsi.renderpass_info_idx = -1;
       if (tc->options.parse_renderpass_info) {
          util_dynarray_init(&tc->batch_slotsi.renderpass_infos, NULL);
-         tc_batch_renderpass_infos_resize(&tc->batch_slotsi);
+         tc_batch_renderpass_infos_resize(tc, &tc->batch_slotsi);
       }
    }
    for (unsigned i = 0; i < TC_MAX_BUFFER_LISTS; i++)

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/auxiliary/util/u_vbuf.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/auxiliary/util/u_vbuf.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/crocus/ci/crocus-hsw-fails.txt -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/crocus/ci/crocus-hsw-fails.txt Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/crocus/crocus_clear.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/crocus/crocus_clear.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/crocus/crocus_context.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/crocus/crocus_context.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/d3d12/d3d12_video_dec_references_mgr.cpp -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/d3d12/d3d12_video_dec_references_mgr.cpp Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/d3d12/d3d12_video_dec_vp9.cpp -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/d3d12/d3d12_video_dec_vp9.cpp Changed

@@ -310,7 +310,7 @@
          dxvaStructure.ref_frame_coded_widthi  = pipe_vp9->refi->width;
          dxvaStructure.ref_frame_coded_heighti = pipe_vp9->refi->height;
       } else
-         dxvaStructure.ref_frame_mapi.bPicEntry = DXVA_VP9_INVALID_PICTURE_INDEX;
+         dxvaStructure.ref_frame_mapi.bPicEntry = DXVA_VP9_INVALID_PICTURE_ENTRY;
    }
 
    /* DXVA spec The enums and indices for ref_frame_sign_bias are defined */
@@ -319,7 +319,7 @@
    const uint8_t signbias_alt_index = 3;
 
    /* AssociatedFlag When Index7Bits does not contain an index to a valid uncompressed surface, the value shall be set to 127, to indicate that the index is invalid. */
-   memset(&dxvaStructure.frame_refs0, DXVA_VP9_INVALID_PICTURE_INDEX, sizeof(dxvaStructure.frame_refs));
+   memset(&dxvaStructure.frame_refs0, DXVA_VP9_INVALID_PICTURE_ENTRY, sizeof(dxvaStructure.frame_refs));
 
    if (pipe_vp9->refpipe_vp9->picture_parameter.pic_fields.last_ref_frame) {
       /* AssociatedFlag When Index7Bits does not contain an index to a valid uncompressed surface, the value shall be set to 127, to indicate that the index is invalid. */
@@ -348,10 +348,16 @@
    dxvaStructure.filter_level    = pipe_vp9->picture_parameter.filter_level;
    dxvaStructure.sharpness_level = pipe_vp9->picture_parameter.sharpness_level;
 
-   bool use_last_frame_mvs = !pipe_vp9->picture_parameter.pic_fields.error_resilient_mode && pipe_vp9->picture_parameter.pic_fields.show_frame;
+   bool use_prev_in_find_mv_refs =
+      !pipe_vp9->picture_parameter.pic_fields.error_resilient_mode &&
+      !(pipe_vp9->picture_parameter.pic_fields.frame_type == 0 /*KEY_FRAME*/ || pipe_vp9->picture_parameter.pic_fields.intra_only) &&
+      pipe_vp9->picture_parameter.pic_fields.prev_show_frame &&
+      pipe_vp9->picture_parameter.frame_width == pipe_vp9->picture_parameter.prev_frame_width &&
+      pipe_vp9->picture_parameter.frame_height == pipe_vp9->picture_parameter.prev_frame_height;
+
    dxvaStructure.wControlInfoFlags = (pipe_vp9->picture_parameter.mode_ref_delta_enabled  << 0) |
                            (pipe_vp9->picture_parameter.mode_ref_delta_update             << 1) |
-                           (use_last_frame_mvs                                            << 2) |
+                           (use_prev_in_find_mv_refs                                      << 2) |
                            (0                                                             << 3);
 
    for (uint32_t i = 0; i < 4; i++)

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/d3d12/d3d12_video_dec_vp9.h -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/d3d12/d3d12_video_dec_vp9.h Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/etnaviv/etnaviv_disk_cache.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/etnaviv/etnaviv_disk_cache.c Changed

@@ -100,11 +100,11 @@
    blob_copy_bytes(blob, v->code, 4 * v->code_size);
 
    blob_copy_bytes(blob, &v->uniforms.count, sizeof(v->uniforms.count));
-   v->uniforms.contents = malloc(v->uniforms.count * sizeof(v->uniforms.contents));
-   v->uniforms.data = malloc(v->uniforms.count * sizeof(v->uniforms.data));
+   v->uniforms.contents = malloc(v->uniforms.count * sizeof(*v->uniforms.contents));
+   v->uniforms.data = malloc(v->uniforms.count * sizeof(*v->uniforms.data));
 
-   blob_copy_bytes(blob, v->uniforms.contents, v->uniforms.count * sizeof(v->uniforms.contents));
-   blob_copy_bytes(blob, v->uniforms.data, v->uniforms.count * sizeof(v->uniforms.data));
+   blob_copy_bytes(blob, v->uniforms.contents, v->uniforms.count * sizeof(*v->uniforms.contents));
+   blob_copy_bytes(blob, v->uniforms.data, v->uniforms.count * sizeof(*v->uniforms.data));
 }
 
 static void
@@ -116,8 +116,8 @@
    blob_write_bytes(blob, v->code, 4 * v->code_size);
 
    blob_write_bytes(blob, &v->uniforms.count, sizeof(v->uniforms.count));
-   blob_write_bytes(blob, v->uniforms.contents, imm_count * sizeof(v->uniforms.contents));
-   blob_write_bytes(blob, v->uniforms.data, imm_count * sizeof(v->uniforms.data));
+   blob_write_bytes(blob, v->uniforms.contents, imm_count * sizeof(*v->uniforms.contents));
+   blob_write_bytes(blob, v->uniforms.data, imm_count * sizeof(*v->uniforms.data));
 }
 
 bool

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/iris/iris_batch.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/iris/iris_batch.c Changed

@@ -981,9 +981,14 @@
    }
 
    int ret = 0;
-   if (!batch->screen->devinfo->no_hw &&
-       intel_ioctl(batch->screen->fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf))
-      ret = -errno;
+   if (!batch->screen->devinfo->no_hw) {
+      do {
+         ret = intel_ioctl(batch->screen->fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf);
+      } while (ret && errno == ENOMEM);
+
+      if (ret)
+	 ret = -errno;
+   }
 
    simple_mtx_unlock(bo_deps_lock);
 
@@ -1092,9 +1097,8 @@
     * with a new logical context, and inform iris_context that all state
     * has been lost and needs to be re-initialized.  If this succeeds,
     * dubiously claim success...
-    * Also handle ENOMEM here.
     */
-   if ((ret == -EIO || ret == -ENOMEM) && replace_kernel_ctx(batch)) {
+   if (ret == -EIO && replace_kernel_ctx(batch)) {
       if (batch->reset->reset) {
          /* Tell gallium frontends the device is lost and it was our fault. */
          batch->reset->reset(batch->reset->data, PIPE_GUILTY_CONTEXT_RESET);

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/iris/iris_bufmgr.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/iris/iris_bufmgr.c Changed

@@ -308,8 +308,12 @@
  */
 static struct bo_cache_bucket *
 bucket_for_size(struct iris_bufmgr *bufmgr, uint64_t size,
-                enum iris_heap heap)
+                enum iris_heap heap, unsigned flags)
 {
+   /* Protected bo needs special handling during allocation */
+   if (flags & BO_ALLOC_PROTECTED)
+      return NULL;
+
    /* Calculating the pages and rounding up to the page size. */
    const unsigned pages = (size + PAGE_SIZE - 1) / PAGE_SIZE;
 
@@ -872,8 +876,7 @@
                     unsigned flags,
                     bool match_zone)
 {
-   /* Don't put anything protected in the BO cache. */
-   if (!bucket || (flags & BO_ALLOC_PROTECTED))
+   if (!bucket)
       return NULL;
 
    struct iris_bo *bo = NULL;
@@ -1080,7 +1083,7 @@
    unsigned int page_size = getpagesize();
    enum iris_heap heap = flags_to_heap(bufmgr, flags);
    bool local = heap != IRIS_HEAP_SYSTEM_MEMORY;
-   struct bo_cache_bucket *bucket = bucket_for_size(bufmgr, size, heap);
+   struct bo_cache_bucket *bucket = bucket_for_size(bufmgr, size, heap, flags);
 
    if (memzone != IRIS_MEMZONE_OTHER || (flags & BO_ALLOC_COHERENT))
       flags |= BO_ALLOC_NO_SUBALLOC;
@@ -1480,7 +1483,7 @@
 
    bucket = NULL;
    if (bo->real.reusable)
-      bucket = bucket_for_size(bufmgr, bo->size, bo->real.heap);
+      bucket = bucket_for_size(bufmgr, bo->size, bo->real.heap, 0);
    /* Put the buffer into our internal cache for reuse if we can. */
    if (bucket && iris_bo_madvise(bo, I915_MADV_DONTNEED)) {
       bo->real.free_time = time;
@@ -2135,9 +2138,9 @@
    list_inithead(&bucketsi.head);
    bucketsi.size = size;
 
-   assert(bucket_for_size(bufmgr, size, heap) == &bucketsi);
-   assert(bucket_for_size(bufmgr, size - 2048, heap) == &bucketsi);
-   assert(bucket_for_size(bufmgr, size + 1, heap) != &bucketsi);
+   assert(bucket_for_size(bufmgr, size, heap, 0) == &bucketsi);
+   assert(bucket_for_size(bufmgr, size - 2048, heap, 0) == &bucketsi);
+   assert(bucket_for_size(bufmgr, size + 1, heap, 0) != &bucketsi);
 }
 
 static void

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/iris/iris_screen.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/iris/iris_screen.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/iris/iris_state.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/iris/iris_state.c Changed

@@ -2823,6 +2823,21 @@
                                                &res->surf, view,
                                                &isl_surf, view, &offset_B,
                                                &tile_x_el, &tile_y_el);
+
+      /* On Broadwell, HALIGN and VALIGN are specified in pixels and are
+       * hard-coded to align to exactly the block size of the compressed
+       * texture. This means that, when reinterpreted as a non-compressed
+       * texture, the tile offsets may be anything.
+       *
+       * We need them to be multiples of 4 to be usable in RENDER_SURFACE_STATE,
+       * so force the state tracker to take fallback paths if they're not.
+       */
+#if GFX_VER == 8
+      if (tile_x_el % 4 != 0 || tile_y_el % 4 != 0) {
+         ok = false;
+      }
+#endif
+
       if (!ok) {
          free(surf);
          return NULL;
@@ -5694,9 +5709,27 @@
        *
        * An end of pipe sync is needed here, otherwise we see GPU hangs in
        * dEQP-GLES31.functional.copy_image.* tests.
+       *
+       * HSD 22012751911: SW Programming sequence when issuing aux invalidation:
+       *
+       *    "Render target Cache Flush + L3 Fabric Flush + State Invalidation + CS Stall"
+       *
+       * Notice we don't set the L3 Fabric Flush here, because we have
+       * PIPE_CONTROL_CS_STALL. The PIPE_CONTROL::L3 Fabric Flush
+       * documentation says :
+       *
+       *    "L3 Fabric Flush will ensure all the pending transactions in the
+       *     L3 Fabric are flushed to global observation point. HW does
+       *     implicit L3 Fabric Flush on all stalling flushes (both explicit
+       *     and implicit) and on PIPECONTROL having Post Sync Operation
+       *     enabled."
+       *
+       * Therefore setting L3 Fabric Flush here would be redundant.
        */
       iris_emit_end_of_pipe_sync(batch, "Invalidate aux map table",
-                                 PIPE_CONTROL_CS_STALL);
+                                 PIPE_CONTROL_CS_STALL |
+                                 PIPE_CONTROL_RENDER_TARGET_FLUSH |
+                                 PIPE_CONTROL_STATE_CACHE_INVALIDATE);
 
       /* If the aux-map state number increased, then we need to rewrite the
        * register. Rewriting the register is used to both set the aux-map
@@ -5704,6 +5737,20 @@
        * cached translations.
        */
       iris_load_register_imm32(batch, GENX(GFX_CCS_AUX_INV_num), 1);
+
+      /* HSD 22012751911: SW Programming sequence when issuing aux invalidation:
+       *
+       *    "Poll Aux Invalidation bit once the invalidation is set (Register
+       *     4208 bit 0)"
+       */
+      iris_emit_cmd(batch, GENX(MI_SEMAPHORE_WAIT), sem) {
+         sem.CompareOperation = COMPARE_SAD_EQUAL_SDD;
+         sem.WaitMode = PollingMode;
+         sem.RegisterPollMode = true;
+         sem.SemaphoreDataDword = 0x0;
+         sem.SemaphoreAddress = ro_bo(NULL, GENX(GFX_CCS_AUX_INV_num));
+      }
+
       batch->last_aux_map_state = aux_map_state_num;
    }
 }

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/lima/lima_resource.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/lima/lima_resource.c Changed

@@ -59,7 +59,10 @@
    struct lima_screen *screen = lima_screen(pscreen);
    struct renderonly_scanout *scanout;
    struct winsys_handle handle;
-   struct pipe_resource *pres;
+
+   struct lima_resource *res = CALLOC_STRUCT(lima_resource);
+   if (!res)
+      return NULL;
 
    struct pipe_resource scanout_templat = *templat;
    scanout_templat.width0 = width;
@@ -71,20 +74,31 @@
    if (!scanout)
       return NULL;
 
+   res->base = *templat;
+   res->base.screen = pscreen;
+   pipe_reference_init(&res->base.reference, 1);
+   res->levels0.offset = handle.offset;
+   res->levels0.stride = handle.stride;
+
    assert(handle.type == WINSYS_HANDLE_TYPE_FD);
-   pres = pscreen->resource_from_handle(pscreen, templat, &handle,
-                                        PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE);
+   res->bo = lima_bo_import(screen, &handle);
+   if (!res->bo) {
+      FREE(res);
+      return NULL;
+   }
+
+   res->modifier_constant = true;
 
    close(handle.handle);
-   if (!pres) {
+   if (!res->bo) {
       renderonly_scanout_destroy(scanout, screen->ro);
+      FREE(res);
       return NULL;
    }
 
-   struct lima_resource *res = lima_resource(pres);
    res->scanout = scanout;
 
-   return pres;
+   return &res->base;
 }
 
 static uint32_t

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/llvmpipe/ci/gitlab-ci.yml -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/llvmpipe/ci/gitlab-ci.yml Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/llvmpipe/lp_screen.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/llvmpipe/lp_screen.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/llvmpipe/lp_state_fs.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/llvmpipe/lp_state_fs.c Changed

@@ -3466,7 +3466,9 @@
 
    /* Loop over color outputs / color buffers to do blending */
    for (unsigned cbuf = 0; cbuf < key->nr_cbufs; cbuf++) {
-      if (key->cbuf_formatcbuf != PIPE_FORMAT_NONE) {
+      if (key->cbuf_formatcbuf != PIPE_FORMAT_NONE &&
+          (key->blend.rtcbuf.blend_enable || key->blend.logicop_enable ||
+           find_output_by_semantic(&shader->info.base, TGSI_SEMANTIC_COLOR, cbuf) != -1)) {
          LLVMValueRef color_ptr;
          LLVMValueRef stride;
          LLVMValueRef sample_stride = NULL;
@@ -3971,7 +3973,12 @@
       shader->base.tokens = tgsi_dup_tokens(templ->tokens);
    } else {
       shader->base.ir.nir = templ->ir.nir;
-      nir_tgsi_scan_shader(templ->ir.nir, &shader->info.base, true);
+
+      /* lower FRAG_RESULT_COLOR -> DATA0-7 to correctly handle unused attachments */
+      nir_shader *nir = shader->base.ir.nir;
+      NIR_PASS_V(nir, nir_lower_fragcolor, nir->info.fs.color_is_dual_source ? 1 : 8);
+
+      nir_tgsi_scan_shader(nir, &shader->info.base, true);
    }
 
    shader->draw_data = draw_create_fragment_shader(llvmpipe->draw, templ);

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/llvmpipe/lp_state_fs_analysis.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/llvmpipe/lp_state_fs_analysis.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/llvmpipe/lp_state_surface.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/llvmpipe/lp_state_surface.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/nouveau/nouveau_screen.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/nouveau/nouveau_screen.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/nouveau/nvc0/mme/comc597.mme.h -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/nouveau/nvc0/mme/comc597.mme.h Changed

@@ -834,6 +834,59 @@
                  ADD, ZERO,  ZERO,  ZERO,                 0,   NONE,      NONE),
 };
 
+const uint32_t mmec597_set_priv_reg = {
+// r0 = load();
+// mthd(WAIT_FOR_IDLE, 0);
+// send(0);
+// mthd(SET_MME_SHADOW_SCRATCH(0), 1);
+// send(0);
+   MME_INSN(0,   ADD,   R0,     LOAD0,      ZERO, (0<<12)|0x0110/4,     IMMED0, IMMEDHIGH0,
+                 ADD, ZERO,      ZERO,      ZERO, (1<<12)|0x3400/4,     IMMED1, IMMEDHIGH0),
+// send(load());
+   MME_INSN(0,   ADD, ZERO,      ZERO,      ZERO,                0,       NONE,      LOAD0,
+                 ADD, ZERO,      ZERO,      ZERO,                0,       NONE,       NONE),
+// alu0 = r0;
+// r0 = read(NVC597_SET_MME_SHADOW_SCRATCH(26));
+// send(load());
+// mthd(SET_FALCON04, 0);
+// send(alu0);
+   MME_INSN(0,   ADD, ZERO,        R0,      ZERO, (0<<12)|0x2310/4,       NONE,      LOAD0,
+               STATE,   R0,     IMMED,      ZERO,         0x3468/4,     IMMED0,       ALU0),
+// r0 &= 0xffff;
+   MME_INSN(0, MERGE,   R0,      ZERO,        R0, (0<<10)|(8<<5)|0,       NONE,       NONE,
+                 ADD, ZERO,      ZERO,      ZERO,                0,       NONE,       NONE),
+// if (r0 == 2) {
+   MME_INSN(0,   BEQ, ZERO,        R0, IMMEDPAIR,   (2<<14)|0x0004,       NONE,       NONE,
+                 ADD, ZERO,      ZERO,      ZERO,                2,       NONE,       NONE),
+//    do {
+//       r0 = read(NVC597_SET_MME_SHADOW_SCRATCH(0));
+//       mthd(NO_OPERATION);
+//       send(0);
+   MME_INSN(0, STATE,   R0,     IMMED,      ZERO,         0x3400/4,     IMMED1, IMMEDHIGH1,
+                 ADD, ZERO,      ZERO,      ZERO,         0x0100/4,       NONE,       NONE),
+//    } while(r0 != 1);
+   MME_INSN(1,   BEQ, ZERO,        R0, IMMEDPAIR,   (1<<14)|0x1fff,       NONE,       NONE,
+                 ADD, ZERO,      ZERO,      ZERO,                1,       NONE,       NONE),
+// } else {
+   MME_INSN(0,   JAL, ZERO,      ZERO,      ZERO,   (1<<15)|0x0003,       NONE,       NONE,
+                 ADD, ZERO,      ZERO,      ZERO,                0,       NONE,       NONE),
+//    while (HW_LOOP_COUNT < 10) {
+   MME_INSN(0,  LOOP, ZERO, IMMEDPAIR,      ZERO,                2,       NONE,       NONE,
+                 ADD, ZERO,      ZERO,      ZERO,               10,       NONE,       NONE),
+//       mthd(NO_OPERATION, 0);
+//       send(0);
+//    }
+// }
+   MME_INSN(0,   ADD, ZERO,      ZERO,      ZERO, (0<<12)|0x0100/4,     IMMED0,     IMMED1,
+                 ADD, ZERO,      ZERO,      ZERO,                0,       NONE,       NONE),
+// nop
+   MME_INSN(1,   ADD, ZERO,      ZERO,      ZERO,                0,       NONE,       NONE,
+                 ADD, ZERO,      ZERO,      ZERO,                0,       NONE,       NONE),
+// nop
+   MME_INSN(0,   ADD, ZERO,      ZERO,      ZERO,                0,       NONE,       NONE,
+                 ADD, ZERO,      ZERO,      ZERO,                0,       NONE,       NONE),
+};
+
 const uint32_t mmec597_compute_counter = {
 // r0 = load();
 // r1 = 1;

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/nouveau/nvc0/nvc0_macros.h -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/nouveau/nvc0/nvc0_macros.h Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/panfrost/pan_cmdstream.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/panfrost/pan_cmdstream.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/r600/evergreen_state.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/r600/evergreen_state.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/r600/r600_shader.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/r600/r600_shader.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/r600/r600_state.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/r600/r600_state.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/r600/r600_state_common.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/r600/r600_state_common.c Changed

@@ -586,10 +586,10 @@
 	/* Set vertex buffers. */
 	if (input) {
 		for (i = 0; i < count; i++) {
-			if ((inputi.buffer.resource != vbi.buffer.resource) ||
-			    (vbi.stride != inputi.stride) ||
-			    (vbi.buffer_offset != inputi.buffer_offset) ||
-			    (vbi.is_user_buffer != inputi.is_user_buffer)) {
+			if (likely((inputi.buffer.resource != vbi.buffer.resource) ||
+				   (vbi.stride != inputi.stride) ||
+				   (vbi.buffer_offset != inputi.buffer_offset) ||
+				   (vbi.is_user_buffer != inputi.is_user_buffer))) {
 				if (inputi.buffer.resource) {
 					vbi.stride = inputi.stride;
 					vbi.buffer_offset = inputi.buffer_offset;
@@ -606,6 +606,14 @@
 					pipe_resource_reference(&vbi.buffer.resource, NULL);
 					disable_mask |= 1 << i;
 				}
+			} else if (inputi.buffer.resource) {
+				if (take_ownership) {
+					pipe_resource_reference(&vbi.buffer.resource, NULL);
+					vbi.buffer.resource = inputi.buffer.resource;
+				} else {
+					pipe_resource_reference(&vbi.buffer.resource,
+								inputi.buffer.resource);
+				}
 			}
 		}
 	} else {

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/r600/sfn/sfn_instr_alu.cpp -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/r600/sfn/sfn_instr_alu.cpp Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/r600/sfn/sfn_instr_tex.h -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/r600/sfn/sfn_instr_tex.h Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/r600/sfn/sfn_nir.cpp -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/r600/sfn/sfn_nir.cpp Changed

@@ -443,23 +443,30 @@
 static bool
 r600_nir_lower_atomics(nir_shader *shader)
 {
-   /* First re-do the offsets, in Hardware we start at zero for each new
-    * binding, and we use an offset of one per counter */
-   int current_binding = -1;
-   int current_offset = 0;
-   nir_foreach_variable_with_modes(var, shader, nir_var_uniform)
-   {
-      if (!var->type->contains_atomic())
-         continue;
+   /* In Hardware we start at a zero index for each new
+    * binding, and we use an offset of one per counter. We also
+    * need to sort the atomics according to binding and offset. */
+   std::map<unsigned, unsigned> binding_offset;
+   std::map<unsigned, nir_variable *> sorted_var;
+
+   nir_foreach_variable_with_modes_safe(var, shader, nir_var_uniform) {
+      if (var->type->contains_atomic()) {
+         sorted_var(var->data.binding << 16) | var->data.offset = var;
+         exec_node_remove(&var->node);
+      }
+   }
 
-      if (current_binding == (int)var->data.binding) {
-         var->data.index = current_offset;
-         current_offset += var->type->atomic_size() / ATOMIC_COUNTER_SIZE;
-      } else {
-         current_binding = var->data.binding;
+   for (auto& dummy, var : sorted_var) {
+      auto iindex = binding_offset.find(var->data.binding);
+      unsigned offset_update = var->type->atomic_size() / ATOMIC_COUNTER_SIZE;
+      if (iindex == binding_offset.end()) {
          var->data.index = 0;
-         current_offset = var->type->atomic_size() / ATOMIC_COUNTER_SIZE;
+         binding_offsetvar->data.binding = offset_update;
+      } else {
+         var->data.index = iindex->second;
+         iindex->second += offset_update;
       }
+      shader->variables.push_tail(&var->node);
    }
 
    return nir_shader_instructions_pass(shader,

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/r600/sfn/sfn_shader.cpp -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/r600/sfn/sfn_shader.cpp Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/r600/sfn/sfn_shader.h -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/r600/sfn/sfn_shader.h Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/r600/sfn/sfn_valuefactory.cpp -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/r600/sfn/sfn_valuefactory.cpp Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/r600/sfn/sfn_valuefactory.h -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/r600/sfn/sfn_valuefactory.h Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/radeonsi/gfx10_shader_ngg.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/radeonsi/gfx10_shader_ngg.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/radeonsi/radeon_vcn_dec.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/radeonsi/radeon_vcn_dec.c Changed

@@ -278,6 +278,22 @@
       }
    }
 
+   /* if reference picture exists, however no reference picture found at the end
+      curr_pic_ref_frame_num == 0, which is not reasonable, should be corrected. */
+   /* one exeption for I frames which is valid situation and should be skipped. */
+   if ((result.curr_field_order_cnt_list0 == result.curr_field_order_cnt_list1)
+      && result.used_for_reference_flags && (result.curr_pic_ref_frame_num == 0)) {
+      for (i = 0; i < ARRAY_SIZE(result.ref_frame_list); i++) {
+         result.ref_frame_listi = pic->refi ?
+                (uintptr_t)vl_video_buffer_get_associated_data(pic->refi, &dec->base) : 0xff;
+         if (result.ref_frame_listi != 0xff) {
+            result.curr_pic_ref_frame_num++;
+            result.non_existing_frame_flags &= ~(1 << i);
+            break;
+         }
+      }
+   }
+
    for (i = 0; i < ARRAY_SIZE(result.ref_frame_list); i++) {
       if (result.ref_frame_listi != 0xff) {
          dec->h264_valid_ref_numi         = result.frame_num_listi;

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/radeonsi/si_clear.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/radeonsi/si_clear.c Changed

@@ -1077,22 +1077,22 @@
          }
 
          zstex->need_flush_after_depth_decompression = update_db_depth_clear && sctx->gfx_level == GFX10_3;
+      }
 
-         /* Update DB_DEPTH_CLEAR. */
-         if (update_db_depth_clear &&
-             zstex->depth_clear_valuelevel != (float)depth) {
-            zstex->depth_clear_valuelevel = depth;
-            sctx->framebuffer.dirty_zsbuf = true;
-            si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
-         }
+      /* Update DB_DEPTH_CLEAR. */
+      if (update_db_depth_clear &&
+          zstex->depth_clear_valuelevel != (float)depth) {
+         zstex->depth_clear_valuelevel = depth;
+         sctx->framebuffer.dirty_zsbuf = true;
+         si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
+      }
 
-         /* Update DB_STENCIL_CLEAR. */
-         if (update_db_stencil_clear &&
-             zstex->stencil_clear_valuelevel != stencil) {
-            zstex->stencil_clear_valuelevel = stencil;
-            sctx->framebuffer.dirty_zsbuf = true;
-            si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
-         }
+      /* Update DB_STENCIL_CLEAR. */
+      if (update_db_stencil_clear &&
+          zstex->stencil_clear_valuelevel != stencil) {
+         zstex->stencil_clear_valuelevel = stencil;
+         sctx->framebuffer.dirty_zsbuf = true;
+         si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
       }
    }

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/radeonsi/si_pipe.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/radeonsi/si_pipe.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/radeonsi/si_pm4.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/radeonsi/si_pm4.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/radeonsi/si_pm4.h -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/radeonsi/si_pm4.h Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/radeonsi/si_sdma_copy_image.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/radeonsi/si_sdma_copy_image.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/radeonsi/si_state.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/radeonsi/si_state.c Changed

@@ -3299,6 +3299,11 @@
                            S_028C78_DISABLE_CONSTANT_ENCODE_REG(1) |
                            S_028C78_FDCC_ENABLE(vi_dcc_enabled(tex, cb->base.u.tex.level));
 
+         if (sctx->family >= CHIP_GFX1103_R2) {
+            cb_fdcc_control |= S_028C78_ENABLE_MAX_COMP_FRAG_OVERRIDE(1) |
+                               S_028C78_MAX_COMP_FRAGS(cb->base.texture->nr_samples >= 4);
+         }
+
          radeon_set_context_reg_seq(R_028C6C_CB_COLOR0_VIEW + i * 0x3C, 4);
          radeon_emit(cb->cb_color_view);                      /* CB_COLOR0_VIEW */
          radeon_emit(cb_color_info);                          /* CB_COLOR0_INFO */
@@ -5593,9 +5598,9 @@
       si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
       si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
       si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
-      si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
 
       if (sctx->gfx_level < GFX11) {
+         si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
          si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
          si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
       }

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/radeonsi/si_state_shaders.cpp -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/radeonsi/si_state_shaders.cpp Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/radeonsi/si_texture.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/radeonsi/si_texture.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/softpipe/ci/gitlab-ci.yml -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/softpipe/ci/gitlab-ci.yml Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/v3d/v3d_uniforms.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/v3d/v3d_uniforms.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/v3d/v3dx_state.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/v3d/v3dx_state.c Changed

@@ -548,8 +548,9 @@
                 sampler.wrap_r = translate_wrap(cso->wrap_r);
 
                 sampler.fixed_bias = cso->lod_bias;
-                sampler.depth_compare_function = cso->compare_func;
-
+                sampler.depth_compare_function = cso->compare_mode ?
+                                                 cso->compare_func :
+                                                 V3D_COMPARE_FUNC_NEVER;
                 sampler.min_filter_nearest =
                         cso->min_img_filter == PIPE_TEX_FILTER_NEAREST;
                 sampler.mag_filter_nearest =
@@ -792,7 +793,9 @@
         }
 
         v3dx_pack(&so->texture_shader_state, TEXTURE_SHADER_STATE, tex) {
-                tex.depth_compare_function = cso->compare_func;
+                tex.depth_compare_function = cso->compare_mode ?
+                                             cso->compare_func :
+                                             V3D_COMPARE_FUNC_NEVER;
                 tex.fixed_bias = cso->lod_bias;
         }
 #endif /* V3D_VERSION < 40 */

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/virgl/ci/gitlab-ci.yml -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/virgl/ci/gitlab-ci.yml Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/zink/ci/gitlab-ci.yml -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/zink/ci/gitlab-ci.yml Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/zink/ci/zink-lvp-fails.txt -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/zink/ci/zink-lvp-fails.txt Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/zink/zink_batch.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/zink/zink_batch.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/zink/zink_blit.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/zink/zink_blit.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/zink/zink_clear.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/zink/zink_clear.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/zink/zink_compiler.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/zink/zink_compiler.c Changed

@@ -4116,6 +4116,8 @@
       ret->sinfo.sampler_mask = sampler_mask;
    }
 
+   unsigned ubo_binding_mask = 0;
+   unsigned ssbo_binding_mask = 0;
    foreach_list_typed_reverse_safe(nir_variable, var, node, &nir->variables) {
       if (_nir_shader_variable_has_mode(var, nir_var_uniform |
                                         nir_var_image |
@@ -4138,13 +4140,14 @@
 
             if (!var->data.driver_location) {
                ret->has_uniforms = true;
-            } else {
+            } else if (!(ubo_binding_mask & BITFIELD_BIT(binding))) {
                ret->bindingsztyperet->num_bindingsztype.index = var->data.driver_location;
                ret->bindingsztyperet->num_bindingsztype.binding = binding;
                ret->bindingsztyperet->num_bindingsztype.type = vktype;
                ret->bindingsztyperet->num_bindingsztype.size = glsl_get_length(var->type);
                assert(ret->bindingsztyperet->num_bindingsztype.size);
                ret->num_bindingsztype++;
+               ubo_binding_mask |= BITFIELD_BIT(binding);
             }
          } else if (var->data.mode == nir_var_mem_ssbo) {
             ztype = ZINK_DESCRIPTOR_TYPE_SSBO;
@@ -4153,12 +4156,15 @@
                                              VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
                                              var->data.driver_location,
                                              screen->compact_descriptors);
-            ret->bindingsztyperet->num_bindingsztype.index = var->data.driver_location;
-            ret->bindingsztyperet->num_bindingsztype.binding = var->data.binding;
-            ret->bindingsztyperet->num_bindingsztype.type = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER;
-            ret->bindingsztyperet->num_bindingsztype.size = glsl_get_length(var->type);
-            assert(ret->bindingsztyperet->num_bindingsztype.size);
-            ret->num_bindingsztype++;
+            if (!(ssbo_binding_mask & BITFIELD_BIT(var->data.binding))) {
+               ret->bindingsztyperet->num_bindingsztype.index = var->data.driver_location;
+               ret->bindingsztyperet->num_bindingsztype.binding = var->data.binding;
+               ret->bindingsztyperet->num_bindingsztype.type = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER;
+               ret->bindingsztyperet->num_bindingsztype.size = glsl_get_length(var->type);
+               assert(ret->bindingsztyperet->num_bindingsztype.size);
+               ret->num_bindingsztype++;
+               ssbo_binding_mask |= BITFIELD_BIT(var->data.binding);
+            }
          } else {
             assert(var->data.mode == nir_var_uniform ||
                    var->data.mode == nir_var_image);

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/zink/zink_context.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/zink/zink_context.c Changed

@@ -167,6 +167,14 @@
       zink_destroy_render_pass(screen, he->data);
 
    zink_context_destroy_query_pools(ctx);
+   set_foreach(&ctx->gfx_inputs, he) {
+      struct zink_gfx_input_key *ikey = (void*)he->key;
+      VKSCR(DestroyPipeline)(screen->dev, ikey->pipeline, NULL);
+   }
+   set_foreach(&ctx->gfx_outputs, he) {
+      struct zink_gfx_output_key *okey = (void*)he->key;
+      VKSCR(DestroyPipeline)(screen->dev, okey->pipeline, NULL);
+   }
    u_upload_destroy(pctx->stream_uploader);
    u_upload_destroy(pctx->const_uploader);
    slab_destroy_child(&ctx->transfer_pool);
@@ -1482,8 +1490,9 @@
 ALWAYS_INLINE static void
 unbind_descriptor_reads(struct zink_resource *res, gl_shader_stage pstage)
 {
-   if (!res->sampler_bindspstage && !res->image_bindspstage)
-      res->barrier_accesspstage == MESA_SHADER_COMPUTE &= ~VK_ACCESS_SHADER_READ_BIT;
+   bool is_compute = pstage == MESA_SHADER_COMPUTE;
+   if (!res->sampler_bind_countis_compute && !res->image_bind_countis_compute)
+      res->barrier_accessis_compute &= ~VK_ACCESS_SHADER_READ_BIT;
 }
 
 ALWAYS_INLINE static void
@@ -1560,7 +1569,8 @@
          else
             new_res->obj->unordered_read = false;
       } else {
-         update = !!res;
+         if (res)
+            update = true;
          ssbo->buffer_offset = 0;
          ssbo->buffer_size = 0;
          if (res) {
@@ -1623,10 +1633,15 @@
 {
    VkImageLayout layout = res->bind_countis_compute ? zink_descriptor_util_image_layout_eval(ctx, res, is_compute) : VK_IMAGE_LAYOUT_UNDEFINED;
    VkImageLayout other_layout = res->bind_count!is_compute ? zink_descriptor_util_image_layout_eval(ctx, res, !is_compute) : VK_IMAGE_LAYOUT_UNDEFINED;
-   if (res->bind_countis_compute && layout && res->layout != layout)
-      _mesa_set_add(ctx->need_barriersis_compute, res);
-   if (res->bind_count!is_compute && other_layout && (layout != other_layout || res->layout != other_layout))
-      _mesa_set_add(ctx->need_barriers!is_compute, res);
+   if (!is_compute && res->fb_binds && !(ctx->feedback_loops & res->fb_binds)) {
+      /* always double check feedback loops */
+      _mesa_set_add(ctx->need_barriers0, res);
+   } else {
+      if (res->bind_countis_compute && layout && res->layout != layout)
+         _mesa_set_add(ctx->need_barriersis_compute, res);
+      if (res->bind_count!is_compute && other_layout && (layout != other_layout || res->layout != other_layout))
+         _mesa_set_add(ctx->need_barriers!is_compute, res);
+   }
 }
 
 static void
@@ -2945,6 +2960,8 @@
       ctx->rp_changed = true;
    }
    res->fb_bind_count--;
+   if (!res->fb_bind_count && !res->bind_count0)
+      _mesa_set_remove_key(ctx->need_barriers0, res);
    unsigned feedback_loops = ctx->feedback_loops;
    if (ctx->feedback_loops & BITFIELD_BIT(idx)) {
       ctx->dynamic_fb.attachmentsidx.imageLayout = VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL;
@@ -2967,7 +2984,8 @@
       check_resource_for_batch_ref(ctx, res);
       if (res->sampler_bind_count0) {
          update_res_sampler_layouts(ctx, res);
-         _mesa_set_add(ctx->need_barriers0, res);
+         if (res->layout != VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL)
+            _mesa_set_add(ctx->need_barriers0, res);
       }
    }
 }
@@ -3335,7 +3353,7 @@
 bool
 zink_resource_access_is_write(VkAccessFlags flags)
 {
-   return (flags & ALL_READ_ACCESS_FLAGS) != flags;
+   return (flags & ~ALL_READ_ACCESS_FLAGS) > 0;
 }
 
 bool
@@ -3801,10 +3819,13 @@
          *pfence = (struct pipe_fence_handle *)mfence;
       }
 
+      assert(!mfence->fence);
       mfence->fence = fence;
       mfence->sem = export_sem;
-      if (fence)
+      if (fence) {
          mfence->submit_count = submit_count;
+         util_dynarray_append(&fence->mfences, struct zink_tc_fence *, mfence);
+      }
 
       if (deferred_fence) {
          assert(fence);
@@ -4718,6 +4739,7 @@
       zink_batch_reference_resource(&ctx->batch, d);
    /* don't be too creative */
    zink_resource_object_reference(screen, &d->obj, s->obj);
+   d->valid_buffer_range = s->valid_buffer_range;
    /* force counter buffer reset */
    d->so_valid = false;
    if (num_rebinds && rebind_buffer(ctx, d, rebind_mask, num_rebinds) < num_rebinds)

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/zink/zink_descriptors.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/zink/zink_descriptors.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/zink/zink_draw.cpp -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/zink/zink_draw.cpp Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/zink/zink_fence.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/zink/zink_fence.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/zink/zink_program.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/zink/zink_program.c Changed

@@ -566,6 +566,9 @@
       struct hash_table *ht = &ctx->program_cachezink_program_cache_stages(ctx->shader_stages);
       const uint32_t hash = ctx->gfx_hash;
       struct hash_entry *entry = _mesa_hash_table_search_pre_hashed(ht, hash, ctx->gfx_stages);
+      /* this must be done before prog is updated */
+      if (ctx->curr_program)
+         ctx->gfx_pipeline_state.final_hash ^= ctx->curr_program->last_variant_hash;
       if (entry) {
          prog = (struct zink_gfx_program*)entry->data;
          for (unsigned i = 0; i < ZINK_GFX_SHADER_COUNT; i++) {
@@ -585,8 +588,6 @@
       simple_mtx_unlock(&ctx->program_lockzink_program_cache_stages(ctx->shader_stages));
       if (prog && prog != ctx->curr_program)
          zink_batch_reference_program(&ctx->batch, &prog->base);
-      if (ctx->curr_program)
-         ctx->gfx_pipeline_state.final_hash ^= ctx->curr_program->last_variant_hash;
       ctx->curr_program = prog;
       ctx->gfx_pipeline_state.final_hash ^= ctx->curr_program->last_variant_hash;
       ctx->gfx_dirty = false;
@@ -1858,7 +1859,8 @@
       zink_set_gs_key(ctx)->lower_line_stipple = lower_line_stipple;
    }
 
-   bool lower_line_smooth = screen->driver_workarounds.no_linesmooth &&
+   bool lower_line_smooth = ctx->gfx_pipeline_state.rast_prim == PIPE_PRIM_LINES &&
+                            screen->driver_workarounds.no_linesmooth &&
                             ctx->rast_state->base.line_smooth &&
                             !ctx->num_so_targets;

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/zink/zink_query.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/zink/zink_query.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/zink/zink_resource.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/zink/zink_resource.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/zink/zink_state.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/zink/zink_state.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/drivers/zink/zink_types.h -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/drivers/zink/zink_types.h Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/frontends/lavapipe/ci/gitlab-ci.yml -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/frontends/lavapipe/ci/gitlab-ci.yml Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/frontends/lavapipe/lvp_execute.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/frontends/lavapipe/lvp_execute.c Changed

@@ -313,6 +313,9 @@
    if (constbuf_dirty) {
       struct pipe_box box = {0};
       u_foreach_bit(slot, pipeline->inlinesstage.can_inline) {
+         /* this is already inlined above */
+         if (slot == 0)
+            continue;
          unsigned count = pipeline->inlinesstage.countslot;
          struct pipe_constant_buffer *cbuf = &state->const_buffershslot - 1;
          struct pipe_resource *pres = cbuf->buffer;
@@ -744,10 +747,13 @@
       if (BITSET_TEST(ps->dynamic, MESA_VK_DYNAMIC_RS_DEPTH_CLIP_ENABLE)) {
          state->depth_clamp_sets_clip = false;
       } else {
-         state->rs_state.depth_clip_near = state->rs_state.depth_clip_far =
-            vk_rasterization_state_depth_clip_enable(ps->rs);
          state->depth_clamp_sets_clip =
             ps->rs->depth_clip_enable == VK_MESA_DEPTH_CLIP_ENABLE_NOT_CLAMP;
+         if (state->depth_clamp_sets_clip)
+            state->rs_state.depth_clip_near = state->rs_state.depth_clip_far = !state->rs_state.depth_clamp;
+         else
+            state->rs_state.depth_clip_near = state->rs_state.depth_clip_far =
+               vk_rasterization_state_depth_clip_enable(ps->rs);
       }
 
       if (!BITSET_TEST(ps->dynamic, MESA_VK_DYNAMIC_RS_RASTERIZER_DISCARD_ENABLE))
@@ -2991,7 +2997,7 @@
                                           cmd->u.clear_depth_stencil_image.depth_stencil->depth,
                                           cmd->u.clear_depth_stencil_image.depth_stencil->stencil,
                                           0, 0,
-                                          width, height, true);
+                                          width, height, false);
          state->pctx->surface_destroy(state->pctx, surf);
       }
    }

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/frontends/rusticl/api/icd.rs -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/frontends/rusticl/api/icd.rs Changed

@@ -290,26 +290,25 @@
 
 #macro_export
 macro_rules! impl_cl_type_trait {
-    ($cl: ident, $t: ty, $err: ident) => {
+    ($cl: ident, $t: path, $err: ident) => {
         impl $crate::api::icd::ReferenceCountedAPIPointer<$t, $err> for $cl {
             fn get_ptr(&self) -> CLResult<*const $t> {
                 type Base = $crate::api::icd::CLObjectBase<$err>;
                 Base::check_ptr(self.cast())?;
 
-                // Now that we've verified the object, it should be safe to
-                // dereference it.  As one more double check, make sure that
-                // the CLObjectBase is at the start of the object
-                let obj_ptr: *const $t = self.cast();
-                unsafe {
-                    let base_ptr = ::std::ptr::addr_of!((*obj_ptr).base);
-                    assert!((obj_ptr as usize) == (base_ptr as usize));
-                }
-
-                Ok(obj_ptr)
+                let offset = ::mesa_rust_util::offset_of!($t, base);
+                let mut obj_ptr: *const u8 = self.cast();
+                // SAFETY: We offset the pointer back from the ICD specified base type to our
+                //         internal type.
+                unsafe { obj_ptr = obj_ptr.sub(offset) }
+                Ok(obj_ptr.cast())
             }
 
             fn from_ptr(ptr: *const $t) -> Self {
-                ptr as Self
+                let offset = ::mesa_rust_util::offset_of!($t, base);
+                // SAFETY: The resulting pointer is safe as we simply offset into the ICD specified
+                //         base type.
+                unsafe { (ptr as *const u8).add(offset) as Self }
             }
         }

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/frontends/rusticl/api/kernel.rs -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/frontends/rusticl/api/kernel.rs Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/frontends/rusticl/core/event.rs -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/frontends/rusticl/core/event.rs Changed

@@ -29,6 +29,7 @@
     status: cl_int,
     cbs: Vec<(EventCB, *mut c_void)>; 3,
     fence: Option<PipeFence>,
+    work: Option<EventSig>,
 }
 
 #repr(C)
@@ -38,7 +39,6 @@
     pub queue: Option<Arc<Queue>>,
     pub cmd_type: cl_command_type,
     pub deps: Vec<Arc<Event>>,
-    work: Option<EventSig>,
     state: Mutex<EventMutState>,
     cv: Condvar,
 }
@@ -66,8 +66,8 @@
                 status: CL_QUEUED as cl_int,
                 cbs: Vec::new(), Vec::new(), Vec::new(),
                 fence: None,
+                work: Some(work),
             }),
-            work: Some(work),
             cv: Condvar::new(),
         })
     }
@@ -83,8 +83,8 @@
                 status: CL_SUBMITTED as cl_int,
                 cbs: Vec::new(), Vec::new(), Vec::new(),
                 fence: None,
+                work: None,
             }),
-            work: None,
             cv: Condvar::new(),
         })
     }
@@ -161,7 +161,8 @@
         let mut lock = self.state();
         let status = lock.status;
         if status == CL_QUEUED as cl_int {
-            let new = self.work.as_ref().map_or(
+            let work = lock.work.take();
+            let new = work.as_ref().map_or(
                 // if there is no work
                 CL_SUBMITTED as cl_int,
                 |w| {
@@ -174,6 +175,10 @@
                     res
                 },
             );
+            // we have to make sure that the work object is dropped before we notify about the
+            // status change. It's probably fine to move the value above, but we have to be
+            // absolutely sure it happens before the status update.
+            drop(work);
             self.set_status(&mut lock, new);
             new
         } else {

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/frontends/rusticl/mesa/compiler/nir.rs -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/frontends/rusticl/mesa/compiler/nir.rs Changed

@@ -1,5 +1,6 @@
 use mesa_rust_gen::*;
 use mesa_rust_util::bitset;
+use mesa_rust_util::offset_of;
 
 use std::convert::TryInto;
 use std::ffi::c_void;
@@ -9,26 +10,6 @@
 use std::ptr::NonNull;
 use std::slice;
 
-// from https://internals.rust-lang.org/t/discussion-on-offset-of/7440/2
-macro_rules! offset_of {
-    ($Struct:path, $field:ident) => {{
-        // Using a separate function to minimize unhygienic hazards
-        // (e.g. unsafety of #repr(packed) field borrows).
-        // Uncomment `const` when `const fn`s can juggle pointers.
-        /*const*/
-        fn offset() -> usize {
-            let u = std::mem::MaybeUninit::<$Struct>::uninit();
-            // Use pattern-matching to avoid accidentally going through Deref.
-            let &$Struct { $field: ref f, .. } = unsafe { &*u.as_ptr() };
-            let o = (f as *const _ as usize).wrapping_sub(&u as *const _ as usize);
-            // Triple check that we are within `u` still.
-            assert!((0..=std::mem::size_of_val(&u)).contains(&o));
-            o
-        }
-        offset()
-    }};
-}
-
 pub struct ExecListIter<'a, T> {
     n: &'a mut exec_node,
     offset: usize,

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/frontends/rusticl/util/ptr.rs -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/frontends/rusticl/util/ptr.rs Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/frontends/va/picture_h264_enc.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/frontends/va/picture_h264_enc.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/frontends/va/picture_hevc_enc.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/frontends/va/picture_hevc_enc.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/frontends/va/picture_vp9.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/frontends/va/picture_vp9.c Changed

@@ -37,12 +37,15 @@
 
    assert(buf->size >= sizeof(VADecPictureParameterBufferVP9) && buf->num_elements == 1);
 
+   context->desc.vp9.picture_parameter.prev_frame_width = context->desc.vp9.picture_parameter.frame_width;
+   context->desc.vp9.picture_parameter.prev_frame_height = context->desc.vp9.picture_parameter.frame_height;
    context->desc.vp9.picture_parameter.frame_width = vp9->frame_width;
    context->desc.vp9.picture_parameter.frame_height = vp9->frame_height;
 
    context->desc.vp9.picture_parameter.pic_fields.subsampling_x = vp9->pic_fields.bits.subsampling_x;
    context->desc.vp9.picture_parameter.pic_fields.subsampling_y = vp9->pic_fields.bits.subsampling_y;
    context->desc.vp9.picture_parameter.pic_fields.frame_type = vp9->pic_fields.bits.frame_type;
+   context->desc.vp9.picture_parameter.pic_fields.prev_show_frame = context->desc.vp9.picture_parameter.pic_fields.show_frame;
    context->desc.vp9.picture_parameter.pic_fields.show_frame = vp9->pic_fields.bits.show_frame;
    context->desc.vp9.picture_parameter.pic_fields.error_resilient_mode = vp9->pic_fields.bits.error_resilient_mode;
    context->desc.vp9.picture_parameter.pic_fields.intra_only = vp9->pic_fields.bits.intra_only;

_service:tar_scm:mesa-23.0.0.tar.xz/src/gallium/include/pipe/p_video_state.h -> _service:tar_scm:mesa-23.0.3.tar.xz/src/gallium/include/pipe/p_video_state.h Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/glx/glxcmds.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/glx/glxcmds.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/glx/glxext.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/glx/glxext.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/glx/indirect_glx.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/glx/indirect_glx.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/intel/compiler/brw_eu_emit.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/intel/compiler/brw_eu_emit.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/intel/compiler/brw_fs.cpp -> _service:tar_scm:mesa-23.0.3.tar.xz/src/intel/compiler/brw_fs.cpp Changed

@@ -644,10 +644,19 @@
 bool
 fs_inst::is_partial_write() const
 {
-   return ((this->predicate && this->opcode != BRW_OPCODE_SEL) ||
-           (this->exec_size * type_sz(this->dst.type)) < 32 ||
-           !this->dst.is_contiguous() ||
-           this->dst.offset % REG_SIZE != 0);
+   if (this->predicate && !this->predicate_trivial &&
+       this->opcode != BRW_OPCODE_SEL)
+      return true;
+
+   if (this->dst.offset % REG_SIZE != 0)
+      return true;
+
+   /* SEND instructions always write whole registers */
+   if (this->opcode == SHADER_OPCODE_SEND)
+      return false;
+
+   return this->exec_size * type_sz(this->dst.type) < 32 ||
+          !this->dst.is_contiguous();
 }
 
 unsigned
@@ -2626,6 +2635,7 @@
          /* a * 1.0 = a */
          if (inst->src1.is_one()) {
             inst->opcode = BRW_OPCODE_MOV;
+            inst->sources = 1;
             inst->src1 = reg_undef;
             progress = true;
             break;
@@ -2634,6 +2644,7 @@
          /* a * -1.0 = -a */
          if (inst->src1.is_negative_one()) {
             inst->opcode = BRW_OPCODE_MOV;
+            inst->sources = 1;
             inst->src0.negate = !inst->src0.negate;
             inst->src1 = reg_undef;
             progress = true;
@@ -2648,6 +2659,7 @@
          if (brw_reg_type_is_integer(inst->src1.type) &&
              inst->src1.is_zero()) {
             inst->opcode = BRW_OPCODE_MOV;
+            inst->sources = 1;
             inst->src1 = reg_undef;
             progress = true;
             break;
@@ -2656,6 +2668,7 @@
          if (inst->src0.file == IMM) {
             assert(inst->src0.type == BRW_REGISTER_TYPE_F);
             inst->opcode = BRW_OPCODE_MOV;
+            inst->sources = 1;
             inst->src0.f += inst->src1.f;
             inst->src1 = reg_undef;
             progress = true;
@@ -2671,9 +2684,11 @@
              */
             if (inst->src0.negate) {
                inst->opcode = BRW_OPCODE_NOT;
+               inst->sources = 1;
                inst->src0.negate = false;
             } else {
                inst->opcode = BRW_OPCODE_MOV;
+               inst->sources = 1;
             }
             inst->src1 = reg_undef;
             progress = true;
@@ -2720,6 +2735,7 @@
          }
          if (inst->src0.equals(inst->src1)) {
             inst->opcode = BRW_OPCODE_MOV;
+            inst->sources = 1;
             inst->src1 = reg_undef;
             inst->predicate = BRW_PREDICATE_NONE;
             inst->predicate_inverse = false;
@@ -2732,6 +2748,7 @@
                case BRW_REGISTER_TYPE_F:
                   if (inst->src1.f >= 1.0f) {
                      inst->opcode = BRW_OPCODE_MOV;
+                     inst->sources = 1;
                      inst->src1 = reg_undef;
                      inst->conditional_mod = BRW_CONDITIONAL_NONE;
                      progress = true;
@@ -2747,6 +2764,7 @@
                case BRW_REGISTER_TYPE_F:
                   if (inst->src1.f <= 0.0f) {
                      inst->opcode = BRW_OPCODE_MOV;
+                     inst->sources = 1;
                      inst->src1 = reg_undef;
                      inst->conditional_mod = BRW_CONDITIONAL_NONE;
                      progress = true;
@@ -2767,11 +2785,13 @@
             break;
          if (inst->src1.is_one()) {
             inst->opcode = BRW_OPCODE_ADD;
+            inst->sources = 2;
             inst->src1 = inst->src2;
             inst->src2 = reg_undef;
             progress = true;
          } else if (inst->src2.is_one()) {
             inst->opcode = BRW_OPCODE_ADD;
+            inst->sources = 2;
             inst->src2 = reg_undef;
             progress = true;
          }
@@ -6551,15 +6571,18 @@
                 */
                const bool save_flag = flag_liveout &
                                       flag_mask(flag, dispatch_width / 8);
-               const fs_reg tmp = ubld.group(1, 0).vgrf(flag.type);
+               const fs_reg tmp = ubld.group(8, 0).vgrf(flag.type);
 
-               if (save_flag)
+               if (save_flag) {
+                  ubld.group(8, 0).UNDEF(tmp);
                   ubld.group(1, 0).MOV(tmp, flag);
+               }
 
                ubld.emit(FS_OPCODE_LOAD_LIVE_CHANNELS);
 
                set_predicate(pred, inst);
                inst->flag_subreg = 0;
+               inst->predicate_trivial = true;
 
                if (save_flag)
                   ubld.group(1, 0).at(block, inst->next).MOV(flag, tmp);

_service:tar_scm:mesa-23.0.0.tar.xz/src/intel/compiler/brw_fs.h -> _service:tar_scm:mesa-23.0.3.tar.xz/src/intel/compiler/brw_fs.h Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/intel/compiler/brw_fs_nir.cpp -> _service:tar_scm:mesa-23.0.3.tar.xz/src/intel/compiler/brw_fs_nir.cpp Changed

@@ -1065,7 +1065,7 @@
          rnd = brw_rnd_mode_from_nir_op(instr->op);
 
       if (BRW_RND_MODE_UNSPECIFIED != rnd)
-         bld.emit(SHADER_OPCODE_RND_MODE, bld.null_reg_ud(), brw_imm_d(rnd));
+         bld.exec_all().emit(SHADER_OPCODE_RND_MODE, bld.null_reg_ud(), brw_imm_d(rnd));
 
       /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
        * on the HW gen, it is a special hw opcode or just a MOV, and
@@ -1183,8 +1183,8 @@
       if (nir_has_any_rounding_mode_enabled(execution_mode)) {
          brw_rnd_mode rnd =
             brw_rnd_mode_from_execution_mode(execution_mode);
-         bld.emit(SHADER_OPCODE_RND_MODE, bld.null_reg_ud(),
-                  brw_imm_d(rnd));
+         bld.exec_all().emit(SHADER_OPCODE_RND_MODE, bld.null_reg_ud(),
+                             brw_imm_d(rnd));
       }
 
       if (op0.type == BRW_REGISTER_TYPE_HF)
@@ -1236,8 +1236,8 @@
       if (nir_has_any_rounding_mode_enabled(execution_mode)) {
          brw_rnd_mode rnd =
             brw_rnd_mode_from_execution_mode(execution_mode);
-         bld.emit(SHADER_OPCODE_RND_MODE, bld.null_reg_ud(),
-                  brw_imm_d(rnd));
+         bld.exec_all().emit(SHADER_OPCODE_RND_MODE, bld.null_reg_ud(),
+                             brw_imm_d(rnd));
       }
       FALLTHROUGH;
    case nir_op_iadd:
@@ -1302,8 +1302,8 @@
       if (nir_has_any_rounding_mode_enabled(execution_mode)) {
          brw_rnd_mode rnd =
             brw_rnd_mode_from_execution_mode(execution_mode);
-         bld.emit(SHADER_OPCODE_RND_MODE, bld.null_reg_ud(),
-                  brw_imm_d(rnd));
+         bld.exec_all().emit(SHADER_OPCODE_RND_MODE, bld.null_reg_ud(),
+                             brw_imm_d(rnd));
       }
 
       inst = bld.MUL(result, op0, op1);
@@ -1905,8 +1905,8 @@
       if (nir_has_any_rounding_mode_enabled(execution_mode)) {
          brw_rnd_mode rnd =
             brw_rnd_mode_from_execution_mode(execution_mode);
-         bld.emit(SHADER_OPCODE_RND_MODE, bld.null_reg_ud(),
-                  brw_imm_d(rnd));
+         bld.exec_all().emit(SHADER_OPCODE_RND_MODE, bld.null_reg_ud(),
+                             brw_imm_d(rnd));
       }
 
       inst = bld.MAD(result, op2, op1, op0);
@@ -1916,8 +1916,8 @@
       if (nir_has_any_rounding_mode_enabled(execution_mode)) {
          brw_rnd_mode rnd =
             brw_rnd_mode_from_execution_mode(execution_mode);
-         bld.emit(SHADER_OPCODE_RND_MODE, bld.null_reg_ud(),
-                  brw_imm_d(rnd));
+         bld.exec_all().emit(SHADER_OPCODE_RND_MODE, bld.null_reg_ud(),
+                             brw_imm_d(rnd));
       }
 
       inst = bld.LRP(result, op0, op1, op2);
@@ -5416,7 +5416,7 @@
       bld.exec_all().group(1, 0).MOV(flag, brw_imm_ud(0u));
       bld.CMP(bld.null_reg_ud(), value, brw_imm_ud(0u), BRW_CONDITIONAL_NZ);
 
-      if (instr->dest.ssa.bit_size > 32) {
+      if (nir_dest_bit_size(instr->dest) > 32) {
          dest.type = BRW_REGISTER_TYPE_UQ;
       } else {
          dest.type = BRW_REGISTER_TYPE_UD;
@@ -5436,7 +5436,8 @@
        * FS), bound the invocation to the dispatch size.
        */
       fs_reg bound_invocation;
-      if (bld.dispatch_width() < bld.shader->nir->info.subgroup_size) {
+      if (api_subgroup_size == 0 ||
+          bld.dispatch_width() < api_subgroup_size) {
          bound_invocation = bld.vgrf(BRW_REGISTER_TYPE_UD);
          bld.AND(bound_invocation, invocation, brw_imm_ud(dispatch_width - 1));
       } else {

_service:tar_scm:mesa-23.0.0.tar.xz/src/intel/compiler/brw_fs_register_coalesce.cpp -> _service:tar_scm:mesa-23.0.3.tar.xz/src/intel/compiler/brw_fs_register_coalesce.cpp Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/intel/compiler/brw_fs_scoreboard.cpp -> _service:tar_scm:mesa-23.0.3.tar.xz/src/intel/compiler/brw_fs_scoreboard.cpp Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/intel/compiler/brw_fs_visitor.cpp -> _service:tar_scm:mesa-23.0.3.tar.xz/src/intel/compiler/brw_fs_visitor.cpp Changed

@@ -29,6 +29,7 @@
  */
 #include "brw_eu.h"
 #include "brw_fs.h"
+#include "brw_nir.h"
 #include "compiler/glsl_types.h"
 
 using namespace brw;
@@ -1201,9 +1202,14 @@
      live_analysis(this), regpressure_analysis(this),
      performance_analysis(this),
      dispatch_width(dispatch_width),
+     api_subgroup_size(brw_nir_api_subgroup_size(shader, dispatch_width)),
      bld(fs_builder(this, dispatch_width).at_end())
 {
    init();
+   assert(api_subgroup_size == 0 ||
+          api_subgroup_size == 8 ||
+          api_subgroup_size == 16 ||
+          api_subgroup_size == 32);
 }
 
 fs_visitor::fs_visitor(const struct brw_compiler *compiler, void *log_data,
@@ -1219,9 +1225,14 @@
      live_analysis(this), regpressure_analysis(this),
      performance_analysis(this),
      dispatch_width(8),
+     api_subgroup_size(brw_nir_api_subgroup_size(shader, dispatch_width)),
      bld(fs_builder(this, dispatch_width).at_end())
 {
    init();
+   assert(api_subgroup_size == 0 ||
+          api_subgroup_size == 8 ||
+          api_subgroup_size == 16 ||
+          api_subgroup_size == 32);
 }
 
 void

_service:tar_scm:mesa-23.0.0.tar.xz/src/intel/compiler/brw_ir.h -> _service:tar_scm:mesa-23.0.3.tar.xz/src/intel/compiler/brw_ir.h Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/intel/compiler/brw_nir.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/intel/compiler/brw_nir.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/intel/compiler/brw_nir.h -> _service:tar_scm:mesa-23.0.3.tar.xz/src/intel/compiler/brw_nir.h Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/intel/compiler/brw_nir_opt_peephole_ffma.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/intel/compiler/brw_nir_opt_peephole_ffma.c Changed

@@ -68,9 +68,9 @@
 
 static nir_alu_instr *
 get_mul_for_src(nir_alu_src *src, unsigned num_components,
-                uint8_t swizzle4, bool *negate, bool *abs)
+                uint8_t *swizzle, bool *negate, bool *abs)
 {
-   uint8_t swizzle_tmp4;
+   uint8_t swizzle_tmpNIR_MAX_VEC_COMPONENTS;
    assert(src->src.is_ssa && !src->abs && !src->negate);
 
    nir_instr *instr = src->src.ssa->parent_instr;
@@ -133,7 +133,7 @@
     *   Expected output swizzle = zyxx
     *   If we reuse swizzle in the loop, then output swizzle would be zyzz.
     */
-   memcpy(swizzle_tmp, swizzle, 4*sizeof(uint8_t));
+   memcpy(swizzle_tmp, swizzle, NIR_MAX_VEC_COMPONENTS*sizeof(uint8_t));
    for (int i = 0; i < num_components; i++)
       swizzlei = swizzle_tmpsrc->swizzlei;
 
@@ -189,10 +189,10 @@
       return false;
 
    nir_alu_instr *mul;
-   uint8_t add_mul_src, swizzle4;
+   uint8_t add_mul_src, swizzleNIR_MAX_VEC_COMPONENTS;
    bool negate, abs;
    for (add_mul_src = 0; add_mul_src < 2; add_mul_src++) {
-      for (unsigned i = 0; i < 4; i++)
+      for (unsigned i = 0; i < NIR_MAX_VEC_COMPONENTS; i++)
          swizzlei = i;
 
       negate = false;

_service:tar_scm:mesa-23.0.0.tar.xz/src/intel/genxml/gen12.xml -> _service:tar_scm:mesa-23.0.3.tar.xz/src/intel/genxml/gen12.xml Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/intel/genxml/gen125.xml -> _service:tar_scm:mesa-23.0.3.tar.xz/src/intel/genxml/gen125.xml Changed

@@ -938,7 +938,7 @@
     <field name="Return Filter Weight for Null Texels" start="66" end="66" type="uint" />
     <field name="Return Filter Weight for Border Texels" start="67" end="67" type="uint" />
     <field name="Force gather4 Behavior" start="69" end="69" type="bool" />
-    <field name="Border Color Pointer" start="70" end="87" type="offset" />
+    <field name="Border Color Pointer" start="70" end="95" type="offset" />
     <field name="TCZ Address Control Mode" start="96" end="98" type="Texture Coordinate Mode" />
     <field name="TCY Address Control Mode" start="99" end="101" type="Texture Coordinate Mode" />
     <field name="TCX Address Control Mode" start="102" end="104" type="Texture Coordinate Mode" />
@@ -6817,7 +6817,7 @@
     <field name="Bindless Surface State Base Address Modify Enable" start="512" end="512" type="bool" />
     <field name="Bindless Surface State MOCS" start="516" end="522" type="uint" nonzero="true" />
     <field name="Bindless Surface State Base Address" start="524" end="575" type="address" />
-    <field name="Bindless Surface State Size" start="588" end="607" type="uint" />
+    <field name="Bindless Surface State Size" start="576" end="607" type="uint" />
     <field name="Bindless Sampler State Base Address Modify Enable" start="608" end="608" type="bool" />
     <field name="Bindless Sampler State MOCS" start="612" end="618" type="uint" nonzero="true" />
     <field name="Bindless Sampler State Base Address" start="620" end="671" type="address" />

_service:tar_scm:mesa-23.0.0.tar.xz/src/intel/isl/isl.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/intel/isl/isl.c Changed

@@ -313,16 +313,26 @@
       dev->ds.hiz_offset = 0;
    }
 
-   if (ISL_GFX_VER(dev) >= 7) {
-      /* From the IVB PRM, SURFACE_STATE::Height,
-       *
-       *    For typed buffer and structured buffer surfaces, the number
-       *    of entries in the buffer ranges from 1 to 2^27. For raw buffer
-       *    surfaces, the number of entries in the buffer is the number of bytes
-       *    which can range from 1 to 2^30.
-       *
-       * This limit is only concerned with raw buffers.
-       */
+   /* From the IVB PRM, SURFACE_STATE::Height,
+    *
+    *    For typed buffer and structured buffer surfaces, the number
+    *    of entries in the buffer ranges from 1 to 2^27. For raw buffer
+    *    surfaces, the number of entries in the buffer is the number of bytes
+    *    which can range from 1 to 2^30.
+    *
+    * From the SKL PRM, SURFACE_STATE::Width/Height/Depth for RAW buffers,
+    *
+    *    Width  : bits 6:0
+    *    Height : bits 20:7
+    *    Depth  : bits 31:21
+    *
+    *    So we can address 4Gb
+    *
+    * This limit is only concerned with raw buffers.
+    */
+   if (ISL_GFX_VER(dev) >= 9) {
+      dev->max_buffer_size = 1ull << 32;
+   } else if (ISL_GFX_VER(dev) >= 7) {
       dev->max_buffer_size = 1ull << 30;
    } else {
       dev->max_buffer_size = 1ull << 27;
@@ -2234,14 +2244,11 @@
       if (surf->row_pitch_B % 512 != 0)
          return false;
 
-      /* According to Wa_1406738321, 3D textures need a blit to a new
+      /* TODO: According to Wa_1406738321, 3D textures need a blit to a new
        * surface in order to perform a resolve. For now, just disable CCS.
        */
-      if (surf->dim == ISL_SURF_DIM_3D) {
-         isl_finishme("%s:%s: CCS for 3D textures is disabled, but a workaround"
-                      " is available.", __FILE__, __func__);
+      if (surf->dim == ISL_SURF_DIM_3D)
          return false;
-      }
 
       /* Wa_1207137018
        *

_service:tar_scm:mesa-23.0.0.tar.xz/src/intel/isl/isl_surface_state.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/intel/isl/isl_surface_state.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/intel/perf/gen_perf.py -> _service:tar_scm:mesa-23.0.3.tar.xz/src/intel/perf/gen_perf.py Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/intel/perf/intel_perf_setup.h -> _service:tar_scm:mesa-23.0.3.tar.xz/src/intel/perf/intel_perf_setup.h Changed

@@ -38,52 +38,36 @@
    query->n_counters = 0;
    query->oa_metrics_set_id = 0; /* determined at runtime, via sysfs */
    query->counters = rzalloc_array(query, struct intel_perf_query_counter, ncounters);
-   return query;
-}
-
-static struct intel_perf_query_info *
-hsw_query_alloc(struct intel_perf_config *perf, int ncounters)
-{
-   struct intel_perf_query_info *query = intel_query_alloc(perf, ncounters);
-   query->oa_format = I915_OA_FORMAT_A45_B8_C8;
-   /* Accumulation buffer offsets... */
-   query->gpu_time_offset = 0;
-   query->a_offset = query->gpu_time_offset + 1;
-   query->b_offset = query->a_offset + 45;
-   query->c_offset = query->b_offset + 8;
-   query->perfcnt_offset = query->c_offset + 8;
-   query->rpstat_offset = query->perfcnt_offset + 2;
-   return query;
-}
 
-static struct intel_perf_query_info *
-bdw_query_alloc(struct intel_perf_config *perf, int ncounters)
-{
-   struct intel_perf_query_info *query = intel_query_alloc(perf, ncounters);
-   query->oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8;
    /* Accumulation buffer offsets... */
-   query->gpu_time_offset = 0;
-   query->gpu_clock_offset = query->gpu_time_offset + 1;
-   query->a_offset = query->gpu_clock_offset + 1;
-   query->b_offset = query->a_offset + 36;
-   query->c_offset = query->b_offset + 8;
-   query->perfcnt_offset = query->c_offset + 8;
-   query->rpstat_offset = query->perfcnt_offset + 2;
-   return query;
-}
+   if (perf->devinfo.verx10 <= 75) {
+      query->oa_format = I915_OA_FORMAT_A45_B8_C8;
+      query->gpu_time_offset = 0;
+      query->a_offset = query->gpu_time_offset + 1;
+      query->b_offset = query->a_offset + 45;
+      query->c_offset = query->b_offset + 8;
+      query->perfcnt_offset = query->c_offset + 8;
+      query->rpstat_offset = query->perfcnt_offset + 2;
+   } else if (perf->devinfo.verx10 <= 120) {
+      query->oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8;
+      query->gpu_time_offset = 0;
+      query->gpu_clock_offset = query->gpu_time_offset + 1;
+      query->a_offset = query->gpu_clock_offset + 1;
+      query->b_offset = query->a_offset + 36;
+      query->c_offset = query->b_offset + 8;
+      query->perfcnt_offset = query->c_offset + 8;
+      query->rpstat_offset = query->perfcnt_offset + 2;
+   } else {
+      query->oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;
+      query->gpu_time_offset = 0;
+      query->gpu_clock_offset = query->gpu_time_offset + 1;
+      query->a_offset = query->gpu_clock_offset + 1;
+      query->b_offset = query->a_offset + 38;
+      query->c_offset = query->b_offset + 8;
+      query->perfcnt_offset = query->c_offset + 8;
+      query->rpstat_offset = query->perfcnt_offset + 2;
+   }
 
-static struct intel_perf_query_info *
-xehp_query_alloc(struct intel_perf_config *perf, int ncounters)
-{
-   struct intel_perf_query_info *query = intel_query_alloc(perf, ncounters);
-   query->oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;
-   query->gpu_time_offset = 0;
-   query->gpu_clock_offset = query->gpu_time_offset + 1;
-   query->a_offset = query->gpu_clock_offset + 1;
-   query->b_offset = query->a_offset + 38;
-   query->c_offset = query->b_offset + 8;
-   query->perfcnt_offset = query->c_offset + 8;
-   query->rpstat_offset = query->perfcnt_offset + 2;
    return query;
 }

_service:tar_scm:mesa-23.0.0.tar.xz/src/intel/vulkan/anv_descriptor_set.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/intel/vulkan/anv_descriptor_set.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/intel/vulkan/anv_device.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/intel/vulkan/anv_device.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/intel/vulkan/anv_generated_indirect_draws.h -> _service:tar_scm:mesa-23.0.3.tar.xz/src/intel/vulkan/anv_generated_indirect_draws.h Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/intel/vulkan/anv_private.h -> _service:tar_scm:mesa-23.0.3.tar.xz/src/intel/vulkan/anv_private.h Changed

@@ -914,14 +914,6 @@
     struct anv_instance *                       instance;
     char                                        path20;
     struct intel_device_info                      info;
-    /** Amount of "GPU memory" we want to advertise
-     *
-     * Clearly, this value is bogus since Intel is a UMA architecture.  On
-     * gfx7 platforms, we are limited by GTT size unless we want to implement
-     * fine-grained tracking and GTT splitting.  On Broadwell and above we are
-     * practically unlimited.  However, we will never report more than 3/4 of
-     * the total system ram to try and avoid running out of RAM.
-     */
     bool                                        supports_48bit_addresses;
     struct brw_compiler *                       compiler;
     struct isl_device                           isl_dev;
@@ -2209,8 +2201,12 @@
          /* We're transitioning a buffer written either from VS stage or from
           * the command streamer (see CmdEndTransformFeedbackEXT), we just
           * need to stall the CS.
+          *
+          * Streamout writes apparently bypassing L3, in order to make them
+          * visible to the destination, we need to invalidate the other
+          * caches.
           */
-         pipe_bits |= ANV_PIPE_CS_STALL_BIT;
+         pipe_bits |= ANV_PIPE_CS_STALL_BIT | ANV_PIPE_INVALIDATE_BITS;
          break;
       default:
          break; /* Nothing to do */
@@ -2461,7 +2457,6 @@
       return false;
    }
 
-   assert(vb_address.bo);
    bound->start = intel_48b_address(anv_address_physical(vb_address));
    bound->end = bound->start + vb_size;
    assert(bound->end > bound->start); /* No overflow */
@@ -3097,7 +3092,6 @@
       uint32_t                                  sf4;
       uint32_t                                  raster5;
       uint32_t                                  wm2;
-      uint32_t                                  blend_state1 + MAX_RTS * 2;
       uint32_t                                  streamout_state5;
    } gfx8;
 };

_service:tar_scm:mesa-23.0.0.tar.xz/src/intel/vulkan/anv_utrace.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/intel/vulkan/anv_utrace.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/intel/vulkan/genX_acceleration_structure.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/intel/vulkan/genX_acceleration_structure.c Changed

@@ -525,7 +525,9 @@
 static struct Geo
 vk_to_grl_Geo(const VkAccelerationStructureGeometryKHR *pGeometry,
               uint32_t prim_count,
-              uint32_t transform_offset)
+              uint32_t transform_offset,
+              uint32_t primitive_offset,
+              uint32_t first_vertex)
 {
    struct Geo geo = {
       .Flags = vk_to_grl_GeometryFlags(pGeometry->flags),
@@ -553,14 +555,18 @@
          geo.Desc.Triangles.IndexCount = 0;
          geo.Desc.Triangles.VertexCount = prim_count * 3;
          geo.Desc.Triangles.IndexFormat = INDEX_FORMAT_NONE;
+         geo.Desc.Triangles.pVertexBuffer += primitive_offset;
       } else {
          geo.Desc.Triangles.IndexCount = prim_count * 3;
          geo.Desc.Triangles.VertexCount = vk_tri->maxVertex;
          geo.Desc.Triangles.IndexFormat =
             vk_to_grl_IndexFormat(vk_tri->indexType);
+         geo.Desc.Triangles.pIndexBuffer += primitive_offset;
       }
+
       geo.Desc.Triangles.VertexFormat =
          vk_to_grl_VertexFormat(vk_tri->vertexFormat);
+      geo.Desc.Triangles.pVertexBuffer += vk_tri->vertexStride * first_vertex;
       break;
    }
 
@@ -568,7 +574,8 @@
       const VkAccelerationStructureGeometryAabbsDataKHR *vk_aabbs =
          &pGeometry->geometry.aabbs;
       geo.Type = GEOMETRY_TYPE_PROCEDURAL;
-      geo.Desc.Procedural.pAABBs_GPUVA = vk_aabbs->data.deviceAddress;
+      geo.Desc.Procedural.pAABBs_GPUVA =
+         vk_aabbs->data.deviceAddress + primitive_offset;
       geo.Desc.Procedural.AABBByteStride = vk_aabbs->stride;
       geo.Desc.Procedural.AABBCount = prim_count;
       break;
@@ -824,7 +831,9 @@
          const VkAccelerationStructureGeometryKHR *pGeometry = get_geometry(pInfo, g);
          uint32_t prim_count = pBuildRangeInfosg.primitiveCount;
          geosg = vk_to_grl_Geo(pGeometry, prim_count,
-                                 pBuildRangeInfosg.transformOffset);
+                                 pBuildRangeInfosg.transformOffset,
+                                 pBuildRangeInfosg.primitiveOffset,
+                                 pBuildRangeInfosg.firstVertex);
 
          prefixesg = prefix_sum;
          prefix_sum += prim_count;

_service:tar_scm:mesa-23.0.0.tar.xz/src/intel/vulkan/genX_cmd_buffer.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/intel/vulkan/genX_cmd_buffer.c Changed

@@ -1595,9 +1595,27 @@
     *    "Driver must ensure that the engine is IDLE but ensure it doesn't
     *    add extra flushes in the case it knows that the engine is already
     *    IDLE."
+    *
+    * HSD 22012751911: SW Programming sequence when issuing aux invalidation:
+    *
+    *    "Render target Cache Flush + L3 Fabric Flush + State Invalidation + CS Stall"
+    *
+    * Notice we don't set the L3 Fabric Flush here, because we have
+    * ANV_PIPE_END_OF_PIPE_SYNC_BIT which inserts a CS stall. The
+    * PIPE_CONTROL::L3 Fabric Flush documentation says :
+    *
+    *    "L3 Fabric Flush will ensure all the pending transactions in the L3
+    *     Fabric are flushed to global observation point. HW does implicit L3
+    *     Fabric Flush on all stalling flushes (both explicit and implicit)
+    *     and on PIPECONTROL having Post Sync Operation enabled."
+    *
+    * Therefore setting L3 Fabric Flush here would be redundant.
     */
-   if (GFX_VER == 12 && (bits & ANV_PIPE_AUX_TABLE_INVALIDATE_BIT))
-      bits |= ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT;
+   if (GFX_VER == 12 && (bits & ANV_PIPE_AUX_TABLE_INVALIDATE_BIT)) {
+      bits |= (ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT |
+               ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT |
+               ANV_PIPE_STATE_CACHE_INVALIDATE_BIT);
+   }
 
    /* If we're going to do an invalidate and we have a pending end-of-pipe
     * sync that has yet to be resolved, we do the end-of-pipe sync now.
@@ -1816,6 +1834,19 @@
             lri.RegisterOffset = GENX(GFX_CCS_AUX_INV_num);
             lri.DataDWord = 1;
          }
+         /* HSD 22012751911: SW Programming sequence when issuing aux invalidation:
+          *
+          *    "Poll Aux Invalidation bit once the invalidation is set
+          *     (Register 4208 bit 0)"
+          */
+         anv_batch_emit(batch, GENX(MI_SEMAPHORE_WAIT), sem) {
+            sem.CompareOperation = COMPARE_SAD_EQUAL_SDD;
+            sem.WaitMode = PollingMode;
+            sem.RegisterPollMode = true;
+            sem.SemaphoreDataDword = 0x0;
+            sem.SemaphoreAddress =
+               anv_address_from_u64(GENX(GFX_CCS_AUX_INV_num));
+         }
       }
 #endif
 
@@ -4104,12 +4135,15 @@
          prim.ExtendedParameter1       = firstInstance;
          prim.ExtendedParameter2       = i;
       }
-#if GFX_VERx10 == 125
-   genX(emit_dummy_post_sync_op)(cmd_buffer, draw->vertexCount);
-#endif
    }
 #endif
 
+#if GFX_VERx10 == 125
+   genX(emit_dummy_post_sync_op)(cmd_buffer,
+                                 drawCount == 0 ? 0 :
+                                 pVertexInfodrawCount - 1.vertexCount);
+#endif
+
    update_dirty_vbs_for_gfx8_vb_flush(cmd_buffer, SEQUENTIAL);
 
    trace_intel_end_draw_multi(&cmd_buffer->trace, count);
@@ -4305,12 +4339,15 @@
          prim.ExtendedParameter1       = firstInstance;
          prim.ExtendedParameter2       = i;
       }
-#if GFX_VERx10 == 125
-      genX(emit_dummy_post_sync_op)(cmd_buffer, draw->indexCount);
-#endif
    }
 #endif
 
+#if GFX_VERx10 == 125
+   genX(emit_dummy_post_sync_op)(cmd_buffer,
+                                 drawCount == 0 ? 0 :
+                                 pIndexInfodrawCount - 1.indexCount);
+#endif
+
    update_dirty_vbs_for_gfx8_vb_flush(cmd_buffer, RANDOM);
 
    trace_intel_end_draw_indexed_multi(&cmd_buffer->trace, count);
@@ -4551,10 +4588,11 @@
       }
 
 #if GFX_VERx10 == 125
-   genX(emit_dummy_post_sync_op)(cmd_buffer, 1);
+      genX(emit_dummy_post_sync_op)(cmd_buffer, 1);
 #endif
 
-      update_dirty_vbs_for_gfx8_vb_flush(cmd_buffer, SEQUENTIAL);
+      update_dirty_vbs_for_gfx8_vb_flush(cmd_buffer,
+                                         indexed ? RANDOM : SEQUENTIAL);
 
       offset += indirect_data_stride;
    }
@@ -5970,7 +6008,7 @@
 {
    return mi_ior(b,
                  mi_iand(b, mi_mem64(anv_address_from_u64(addr_field_addr)),
-                            mi_imm(0xffffffffff)),
+                            mi_imm(BITFIELD64_BIT(49) - 1)),
                  mi_ishl_imm(b, mi_mem32(anv_address_from_u64(stride_field_addr)),
                                 48));
 }
@@ -6359,28 +6397,20 @@
     */
    if (pipeline == GPGPU)
       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), t);
+#endif
 
-   if (pipeline == _3D) {
-      /* There is a mid-object preemption workaround which requires you to
-       * re-emit MEDIA_VFE_STATE after switching from GPGPU to 3D.  However,
-       * even without preemption, we have issues with geometry flickering when
-       * GPGPU and 3D are back-to-back and this seems to fix it.  We don't
-       * really know why.
-       */
-      anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_VFE_STATE), vfe) {
-         vfe.MaximumNumberofThreads =
-            devinfo->max_cs_threads * devinfo->subslice_total - 1;
-         vfe.NumberofURBEntries     = 2;
-         vfe.URBEntryAllocationSize = 2;
-      }
-
-      /* We just emitted a dummy MEDIA_VFE_STATE so now that packet is
-       * invalid. Set the compute pipeline to dirty to force a re-emit of the
-       * pipeline in case we get back-to-back dispatch calls with the same
-       * pipeline and a PIPELINE_SELECT in between.
-       */
+#if GFX_VERx10 == 120
+   /* Undocumented workaround to force the re-emission of
+    * MEDIA_INTERFACE_DESCRIPTOR_LOAD when switching from 3D to Compute
+    * pipeline without rebinding a pipeline :
+    *    vkCmdBindPipeline(COMPUTE, cs_pipeline);
+    *    vkCmdDispatch(...);
+    *    vkCmdBindPipeline(GRAPHICS, gfx_pipeline);
+    *    vkCmdDraw(...);
+    *    vkCmdDispatch(...);
+    */
+   if (pipeline == _3D)
       cmd_buffer->state.compute.pipeline_dirty = true;
-   }
 #endif
 
 #if GFX_VER >= 12
@@ -6436,6 +6466,37 @@
 #endif
    genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
 
+#if GFX_VER == 9
+   if (pipeline == _3D) {
+      /* There is a mid-object preemption workaround which requires you to
+       * re-emit MEDIA_VFE_STATE after switching from GPGPU to 3D.  However,
+       * even without preemption, we have issues with geometry flickering when
+       * GPGPU and 3D are back-to-back and this seems to fix it.  We don't
+       * really know why.
+       *
+       * Also, from the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
+       *
+       *    "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
+       *    the only bits that are changed are scoreboard related ..."
+       *
+       * This is satisfied by applying pre-PIPELINE_SELECT pipe flushes above.
+       */
+      anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_VFE_STATE), vfe) {
+         vfe.MaximumNumberofThreads =
+            devinfo->max_cs_threads * devinfo->subslice_total - 1;
+         vfe.NumberofURBEntries     = 2;
+         vfe.URBEntryAllocationSize = 2;
+      }
+
+      /* We just emitted a dummy MEDIA_VFE_STATE so now that packet is
+       * invalid. Set the compute pipeline to dirty to force a re-emit of the
+       * pipeline in case we get back-to-back dispatch calls with the same
+       * pipeline and a PIPELINE_SELECT in between.
+       */
+      cmd_buffer->state.compute.pipeline_dirty = true;
+   }
+#endif
+
    genX(emit_pipeline_select)(&cmd_buffer->batch, pipeline);
 
 #if GFX_VER == 9
@@ -7907,7 +7968,7 @@
         primitive_topology == _3DPRIM_POINTLIST_BF ||
         primitive_topology == _3DPRIM_LINESTRIP_CONT ||
         primitive_topology == _3DPRIM_LINESTRIP_BF ||
-        primitive_topology == _3DPRIM_LINESTRIP_CONT_BF) ||
+        primitive_topology == _3DPRIM_LINESTRIP_CONT_BF) &&
        (vertex_count == 1 || vertex_count == 2)) {
       anv_batch_emit(batch, GENX(PIPE_CONTROL), pc) {
          pc.PostSyncOperation = WriteImmediateData;

_service:tar_scm:mesa-23.0.0.tar.xz/src/intel/vulkan/genX_cmd_draw_generated_indirect.h -> _service:tar_scm:mesa-23.0.3.tar.xz/src/intel/vulkan/genX_cmd_draw_generated_indirect.h Changed

@@ -114,9 +114,10 @@
 
    cmd_buffer->state.current_l3_config = device->generated_draw_l3_config;
 
+   enum intel_urb_deref_block_size deref_block_size;
    genX(emit_urb_setup)(device, batch, device->generated_draw_l3_config,
                         VK_SHADER_STAGE_VERTEX_BIT | VK_SHADER_STAGE_FRAGMENT_BIT,
-                        entry_size, NULL);
+                        entry_size, &deref_block_size);
 
    anv_batch_emit(batch, GENX(3DSTATE_PS_BLEND), ps_blend) {
       ps_blend.HasWriteableRT = true;
@@ -152,7 +153,7 @@
 
    anv_batch_emit(batch, GENX(3DSTATE_SF), sf) {
 #if GFX_VER >= 12
-      sf.DerefBlockSize = INTEL_URB_DEREF_BLOCK_SIZE_32; // TODO
+      sf.DerefBlockSize = deref_block_size;
 #endif
    }
 
@@ -171,9 +172,7 @@
          sbe.AttributeActiveComponentFormati = ACF_XYZW;
    }
 
-   anv_batch_emit(batch, GENX(3DSTATE_WM), wm) {
-      //wm.ForceThreadDispatchEnable = ForceON;
-   }
+   anv_batch_emit(batch, GENX(3DSTATE_WM), wm);
 
    anv_batch_emit(batch, GENX(3DSTATE_PS_EXTRA), psx) {
       psx.PixelShaderValid = true;
@@ -226,14 +225,9 @@
    cmd_buffer->state.gfx.vb_dirty = BITFIELD_BIT(0) | BITFIELD_BIT(1);
    cmd_buffer->state.gfx.dirty |= ~(ANV_CMD_DIRTY_INDEX_BUFFER |
                                     ANV_CMD_DIRTY_XFB_ENABLE);
-   cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_ALL_GRAPHICS;
+   cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_FRAGMENT_BIT;
    cmd_buffer->state.gfx.push_constant_stages = VK_SHADER_STAGE_FRAGMENT_BIT;
    vk_dynamic_graphics_state_dirty_all(&cmd_buffer->vk.dynamic_graphics_state);
-
-   anv_add_pending_pipe_bits(cmd_buffer,
-                             ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT |
-                             ANV_PIPE_STALL_AT_SCOREBOARD_BIT,
-                             "after generation batch BTI change");
 }
 
 static void
@@ -318,10 +312,9 @@
    return push_data_state;
 }
 
-static void
+static struct anv_generate_indirect_params *
 genX(cmd_buffer_emit_generate_draws)(struct anv_cmd_buffer *cmd_buffer,
                                      struct anv_address generated_cmds_addr,
-                                     uint32_t generated_cmds_size,
                                      struct anv_address indirect_data_addr,
                                      uint32_t indirect_data_stride,
                                      uint32_t item_base,
@@ -335,7 +328,7 @@
       brw_wm_prog_data_const(draw_kernel->prog_data);
 
    anv_batch_emit(batch, GENX(3DSTATE_PS), ps) {
-      ps.BindingTableEntryCount = 2;
+      ps.BindingTableEntryCount = 0;
       ps.PushConstantEnable     = prog_data->base.nr_params > 0 ||
                                   prog_data->base.ubo_ranges0.length;
 
@@ -389,6 +382,8 @@
       prim.VertexCountPerInstance   = 3;
       prim.InstanceCount            = 1;
    }
+
+   return push_data;
 }
 
 static void
@@ -419,6 +414,22 @@
 }
 
 static void
+genX(cmd_buffer_rewrite_forward_end_addr)(struct anv_cmd_buffer *cmd_buffer,
+                                          struct anv_generate_indirect_params *params)
+{
+   /* We don't know the end_addr until we have emitted all the generation
+    * draws. Go and edit the address of all the push parameters.
+    */
+   uint64_t end_addr =
+      anv_address_physical(anv_batch_current_address(&cmd_buffer->batch));
+   while (params != NULL) {
+      params->draw_count.end_addr_ldw = end_addr & 0xffffffff;
+      params->draw_count.end_addr_udw = end_addr >> 32;
+      params = params->prev;
+   }
+}
+
+static void
 genX(cmd_buffer_emit_indirect_generated_draws)(struct anv_cmd_buffer *cmd_buffer,
                                                struct anv_address indirect_data_addr,
                                                uint32_t indirect_data_stride,
@@ -455,6 +466,7 @@
 
    const uint32_t draw_cmd_stride = 4 * GENX(3DPRIMITIVE_EXTENDED_length);
 
+   struct anv_generate_indirect_params *last_params = NULL;
    uint32_t item_base = 0;
    while (item_base < draw_count) {
       const uint32_t item_count = MIN2(draw_count - item_base,
@@ -473,26 +485,28 @@
       if (result != VK_SUCCESS)
          return;
 
-      genX(cmd_buffer_emit_generate_draws)(
-         cmd_buffer,
-         anv_batch_current_address(&cmd_buffer->batch),
-         draw_cmd_size,
-         indirect_data_addr,
-         indirect_data_stride,
-         item_base,
-         item_count,
-         indexed);
+      struct anv_generate_indirect_params *params =
+         genX(cmd_buffer_emit_generate_draws)(
+            cmd_buffer,
+            anv_batch_current_address(&cmd_buffer->batch),
+            indirect_data_addr,
+            indirect_data_stride,
+            item_base,
+            item_count,
+            indexed);
 
       anv_batch_advance(&cmd_buffer->batch, draw_cmd_size);
 
       item_base += item_count;
+
+      params->prev = last_params;
+      last_params = params;
    }
 }
 
-static void
+static struct anv_generate_indirect_params *
 genX(cmd_buffer_emit_generate_draws_count)(struct anv_cmd_buffer *cmd_buffer,
                                            struct anv_address generated_cmds_addr,
-                                           uint32_t generated_cmds_size,
                                            struct anv_address indirect_data_addr,
                                            uint32_t indirect_data_stride,
                                            uint32_t item_base,
@@ -539,9 +553,6 @@
       genX(cmd_buffer_alloc_generated_push_data)(cmd_buffer);
 
    struct anv_graphics_pipeline *pipeline = cmd_buffer->state.gfx.pipeline;
-   uint64_t end_cmd_addr =
-      anv_address_physical(
-         anv_address_add(generated_cmds_addr, generated_cmds_size));
 
    struct anv_generate_indirect_params *push_data = push_data_state.map;
    *push_data = (struct anv_generate_indirect_params) {
@@ -553,8 +564,6 @@
          .draw_count             = 0, // Edit this through a the command streamer
          .instance_multiplier    = pipeline->instance_multiplier,
          .indirect_data_stride   = indirect_data_stride,
-         .end_addr_ldw           = end_cmd_addr & 0xffffffff,
-         .end_addr_udw           = end_cmd_addr >> 32,
       },
       .indirect_data_addr        = anv_address_physical(indirect_data_addr),
       .generated_cmds_addr       = anv_address_physical(generated_cmds_addr),
@@ -572,6 +581,12 @@
                 },
                 offsetof(struct anv_generate_indirect_params, draw_count.draw_count)),
              count_addr, 4);
+   /* Make sure the memcpy landed for the generating draw call to pick up the
+    * value.
+    */
+   anv_batch_emit(batch, GENX(PIPE_CONTROL), pc) {
+      pc.CommandStreamerStallEnable = true;
+   }
 
    /* Only emit the data after the memcpy above. */
    genX(cmd_buffer_emit_generated_push_data)(cmd_buffer, push_data_state);
@@ -582,6 +597,8 @@
       prim.VertexCountPerInstance   = 3;
       prim.InstanceCount            = 1;
    }
+
+   return push_data;
 }
 
 static void
@@ -622,6 +639,7 @@
 
    const uint32_t draw_cmd_stride = 4 * GENX(3DPRIMITIVE_EXTENDED_length);
 
+   struct anv_generate_indirect_params *last_params = NULL;
    uint32_t item_base = 0;
    while (item_base < max_draw_count) {
       const uint32_t item_count = MIN2(max_draw_count - item_base,
@@ -640,22 +658,27 @@
       if (result != VK_SUCCESS)

_service:tar_scm:mesa-23.0.0.tar.xz/src/intel/vulkan/genX_cmd_draw_helpers.h -> _service:tar_scm:mesa-23.0.3.tar.xz/src/intel/vulkan/genX_cmd_draw_helpers.h Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/intel/vulkan/genX_pipeline.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/intel/vulkan/genX_pipeline.c Changed

@@ -498,6 +498,19 @@
       sbe.VertexURBEntryReadLength = DIV_ROUND_UP(max_source_attr + 1, 2);
       sbe.ForceVertexURBEntryReadOffset = true;
       sbe.ForceVertexURBEntryReadLength = true;
+
+      /* Ask the hardware to supply PrimitiveID if the fragment shader
+       * reads it but a previous stage didn't write one.
+       */
+      if ((wm_prog_data->inputs & VARYING_BIT_PRIMITIVE_ID) &&
+          fs_input_map->varying_to_slotVARYING_SLOT_PRIMITIVE_ID == -1) {
+         sbe.PrimitiveIDOverrideAttributeSelect =
+            wm_prog_data->urb_setupVARYING_SLOT_PRIMITIVE_ID;
+         sbe.PrimitiveIDOverrideComponentX = true;
+         sbe.PrimitiveIDOverrideComponentY = true;
+         sbe.PrimitiveIDOverrideComponentZ = true;
+         sbe.PrimitiveIDOverrideComponentW = true;
+      }
    } else {
       assert(anv_pipeline_is_mesh(pipeline));
 #if GFX_VERx10 >= 125
@@ -828,77 +841,6 @@
    VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY = _3DPRIM_TRISTRIP_ADJ,
 };
 
-static inline uint32_t *
-write_disabled_blend(uint32_t *state)
-{
-   struct GENX(BLEND_STATE_ENTRY) entry = {
-      .WriteDisableAlpha = true,
-      .WriteDisableRed = true,
-      .WriteDisableGreen = true,
-      .WriteDisableBlue = true,
-   };
-   GENX(BLEND_STATE_ENTRY_pack)(NULL, state, &entry);
-   return state + GENX(BLEND_STATE_ENTRY_length);
-}
-
-static void
-emit_cb_state(struct anv_graphics_pipeline *pipeline,
-              const struct vk_color_blend_state *cb,
-              const struct vk_multisample_state *ms)
-{
-   uint32_t surface_count = 0;
-   struct anv_pipeline_bind_map *map;
-   if (anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT)) {
-      map = &pipeline->shadersMESA_SHADER_FRAGMENT->bind_map;
-      surface_count = map->surface_count;
-   }
-
-   uint32_t *state_pos = pipeline->gfx8.blend_state;
-
-   state_pos += GENX(BLEND_STATE_length);
-   for (unsigned i = 0; i < surface_count; i++) {
-      struct anv_pipeline_binding *binding = &map->surface_to_descriptori;
-
-      /* All color attachments are at the beginning of the binding table */
-      if (binding->set != ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS)
-         break;
-
-      /* We can have at most 8 attachments */
-      assert(i < MAX_RTS);
-
-      if (cb == NULL || binding->index >= cb->attachment_count) {
-         state_pos = write_disabled_blend(state_pos);
-         continue;
-      }
-
-      struct GENX(BLEND_STATE_ENTRY) entry = {
-         /* Vulkan specification 1.2.168, VkLogicOp:
-          *
-          *   "Logical operations are controlled by the logicOpEnable and
-          *    logicOp members of VkPipelineColorBlendStateCreateInfo. If
-          *    logicOpEnable is VK_TRUE, then a logical operation selected by
-          *    logicOp is applied between each color attachment and the
-          *    fragment’s corresponding output value, and blending of all
-          *    attachments is treated as if it were disabled."
-          *
-          * From the Broadwell PRM Volume 2d: Command Reference: Structures:
-          * BLEND_STATE_ENTRY:
-          *
-          *   "Enabling LogicOp and Color Buffer Blending at the same time is
-          *    UNDEFINED"
-          *
-          * Above is handled during emit since these states are dynamic.
-          */
-         .ColorClampRange = COLORCLAMP_RTFORMAT,
-         .PreBlendColorClampEnable = true,
-         .PostBlendColorClampEnable = true,
-      };
-
-      GENX(BLEND_STATE_ENTRY_pack)(NULL, state_pos, &entry);
-      state_pos += GENX(BLEND_STATE_ENTRY_length);
-   }
-}
-
 static void
 emit_3dstate_clip(struct anv_graphics_pipeline *pipeline,
                   const struct vk_input_assembly_state *ia,
@@ -1842,7 +1784,6 @@
    emit_rs_state(pipeline, state->ia, state->rs, state->ms, state->rp,
                            urb_deref_block_size);
    emit_ms_state(pipeline, state->ms);
-   emit_cb_state(pipeline, state->cb, state->ms);
    compute_kill_pixel(pipeline, state->ms, state->rp);
 
    emit_3dstate_clip(pipeline, state->ia, state->vp, state->rs);

_service:tar_scm:mesa-23.0.0.tar.xz/src/intel/vulkan/gfx8_cmd_buffer.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/intel/vulkan/gfx8_cmd_buffer.c Changed

@@ -683,7 +683,8 @@
        BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_COLOR_WRITE_ENABLES) ||
        BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_LOGIC_OP_ENABLE) ||
        BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_MS_ALPHA_TO_ONE_ENABLE) ||
-       BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_COLOR_WRITE_ENABLES) ||
+       BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_WRITE_MASKS) ||
+       BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_BLEND_ENABLES) ||
        BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_BLEND_EQUATIONS)) {
       const uint8_t color_writes = dyn->cb.color_write_enables;
       const struct anv_cmd_graphics_state *state = &cmd_buffer->state.gfx;
@@ -692,10 +693,14 @@
          anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT) &&
          (color_writes & ((1u << state->color_att_count) - 1)) != 0;
 
-      uint32_t blend_dwsGENX(BLEND_STATE_length) +
-                         MAX_RTS * GENX(BLEND_STATE_ENTRY_length);
-      uint32_t *dws = blend_dws;
-      memset(blend_dws, 0, sizeof(blend_dws));
+      uint32_t num_dwords = GENX(BLEND_STATE_length) +
+         GENX(BLEND_STATE_ENTRY_length) * MAX_RTS;
+      struct anv_state blend_states =
+         anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
+                                            num_dwords * 4,
+                                            64);
+
+      uint32_t *dws = blend_states.map;
 
       struct GENX(BLEND_STATE) blend_state = {
          .AlphaToCoverageEnable = dyn->ms.alpha_to_coverage_enable,
@@ -724,10 +729,29 @@
             .WriteDisableBlue  = write_disabled ||
                                  (dyn->cb.attachmentsi.write_mask &
                                   VK_COLOR_COMPONENT_B_BIT) == 0,
+            /* Vulkan specification 1.2.168, VkLogicOp:
+             *
+             *   "Logical operations are controlled by the logicOpEnable and
+             *   logicOp members of VkPipelineColorBlendStateCreateInfo. If
+             *   logicOpEnable is VK_TRUE, then a logical operation selected
+             *   by logicOp is applied between each color attachment and the
+             *   fragment’s corresponding output value, and blending of all
+             *   attachments is treated as if it were disabled."
+             *
+             * From the Broadwell PRM Volume 2d: Command Reference:
+             * Structures: BLEND_STATE_ENTRY:
+             *
+             *   "Enabling LogicOp and Color Buffer Blending at the same time
+             *   is UNDEFINED"
+             */
             .LogicOpFunction   = genX(vk_to_intel_logic_op)dyn->cb.logic_op,
             .LogicOpEnable     = dyn->cb.logic_op_enable,
             .ColorBufferBlendEnable =
                !dyn->cb.logic_op_enable && dyn->cb.attachmentsi.blend_enable,
+
+            .ColorClampRange = COLORCLAMP_RTFORMAT,
+            .PreBlendColorClampEnable = true,
+            .PostBlendColorClampEnable = true,
          };
 
          /* Setup blend equation. */
@@ -795,7 +819,7 @@
       }
 
       /* Generate blend state after entries. */
-      GENX(BLEND_STATE_pack)(NULL, blend_dws, &blend_state);
+      GENX(BLEND_STATE_pack)(NULL, blend_states.map, &blend_state);
 
       /* 3DSTATE_PS_BLEND to be consistent with the rest of the
        * BLEND_STATE_ENTRY.
@@ -812,12 +836,6 @@
          blend.AlphaToCoverageEnable         = dyn->ms.alpha_to_coverage_enable;
       }
 
-      uint32_t num_dwords = GENX(BLEND_STATE_length) +
-         GENX(BLEND_STATE_ENTRY_length) * MAX_RTS;
-
-      struct anv_state blend_states =
-         anv_cmd_buffer_merge_dynamic(cmd_buffer, blend_dws,
-                                      pipeline->gfx8.blend_state, num_dwords, 64);
       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_BLEND_STATE_POINTERS), bsp) {
          bsp.BlendStatePointer      = blend_states.offset;
          bsp.BlendStatePointerValid = true;

_service:tar_scm:mesa-23.0.0.tar.xz/src/intel/vulkan/grl/meson.build -> _service:tar_scm:mesa-23.0.3.tar.xz/src/intel/vulkan/grl/meson.build Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/intel/vulkan/shaders/generated_draws_count.glsl -> _service:tar_scm:mesa-23.0.3.tar.xz/src/intel/vulkan/shaders/generated_draws_count.glsl Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/intel/vulkan_hasvk/anv_device.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/intel/vulkan_hasvk/anv_device.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/intel/vulkan_hasvk/anv_image.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/intel/vulkan_hasvk/anv_image.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/intel/vulkan_hasvk/anv_private.h -> _service:tar_scm:mesa-23.0.3.tar.xz/src/intel/vulkan_hasvk/anv_private.h Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/intel/vulkan_hasvk/genX_cmd_buffer.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/intel/vulkan_hasvk/genX_cmd_buffer.c Changed

@@ -510,7 +510,8 @@
 {
    return layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
           layout == VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL ||
-          layout == VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL;
+          layout == VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL ||
+          layout == VK_IMAGE_LAYOUT_ATTACHMENT_OPTIMAL;
 }
 #endif
 
@@ -541,6 +542,7 @@
     *  - VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
     *  - VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
     *  - VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL
+    *  - VK_IMAGE_LAYOUT_ATTACHMENT_OPTIMAL
     *
     * For general, we have no nice opportunity to transition so we do the copy
     * to the shadow unconditionally at the end of the subpass. For transfer
@@ -5724,6 +5726,7 @@
     *  - VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
     *  - VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
     *  - VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL
+    *  - VK_IMAGE_LAYOUT_ATTACHMENT_OPTIMAL
     *  - VK_IMAGE_LAYOUT_ATTACHMENT_FEEDBACK_LOOP_OPTIMAL_EXT
     *
     * For general, we have no nice opportunity to transition so we do the copy

_service:tar_scm:mesa-23.0.0.tar.xz/src/mapi/glapi/gen/meson.build -> _service:tar_scm:mesa-23.0.3.tar.xz/src/mapi/glapi/gen/meson.build Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/mesa/main/attrib.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/mesa/main/attrib.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/mesa/main/consts_exts.h -> _service:tar_scm:mesa-23.0.3.tar.xz/src/mesa/main/consts_exts.h Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/mesa/main/draw.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/mesa/main/draw.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/mesa/main/get.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/mesa/main/get.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/mesa/main/get_hash_params.py -> _service:tar_scm:mesa-23.0.3.tar.xz/src/mesa/main/get_hash_params.py Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/mesa/main/glthread_bufferobj.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/mesa/main/glthread_bufferobj.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/mesa/main/texstate.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/mesa/main/texstate.c Changed

@@ -1032,23 +1032,6 @@
    /* Texture group */
    ctx->Texture.CurrentUnit = 0;      /* multitexture */
 
-   /* Appendix F.2 of the OpenGL ES 3.0 spec says:
-    *
-    *     "OpenGL ES 3.0 requires that all cube map filtering be
-    *     seamless. OpenGL ES 2.0 specified that a single cube map face be
-    *     selected and used for filtering."
-    *
-    * Unfortunatley, a call to _mesa_is_gles3 below will only work if
-    * the driver has already computed and set ctx->Version, however drivers
-    * seem to call _mesa_initialize_context (which calls this) early
-    * in the CreateContext hook and _mesa_compute_version much later (since
-    * it needs information about available extensions). So, we will
-    * enable seamless cubemaps by default since GLES2. This should work
-    * for most implementations and drivers that don't support seamless
-    * cubemaps for GLES2 can still disable it.
-    */
-   ctx->Texture.CubeMapSeamless = ctx->API == API_OPENGLES2;
-
    for (u = 0; u < ARRAY_SIZE(ctx->Texture.Unit); u++) {
       struct gl_texture_unit *texUnit = &ctx->Texture.Unitu;
       GLuint tex;

_service:tar_scm:mesa-23.0.0.tar.xz/src/mesa/main/version.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/mesa/main/version.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/mesa/state_tracker/st_context.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/mesa/state_tracker/st_context.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/mesa/state_tracker/st_extensions.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/mesa/state_tracker/st_extensions.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/mesa/state_tracker/st_extensions.h -> _service:tar_scm:mesa-23.0.3.tar.xz/src/mesa/state_tracker/st_extensions.h Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/mesa/state_tracker/st_manager.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/mesa/state_tracker/st_manager.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/mesa/state_tracker/st_program.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/mesa/state_tracker/st_program.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/mesa/vbo/vbo_exec_api.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/mesa/vbo/vbo_exec_api.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/mesa/vbo/vbo_save_api.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/mesa/vbo/vbo_save_api.c Changed

@@ -625,6 +625,9 @@
       GLubyte mode = original_primsi.mode;
       bool converted_prim = false;
       unsigned index_size;
+      bool outputting_quads = !!(ctx->Const.DriverSupportedPrimMask &
+                                 (BITFIELD_MASK(PIPE_PRIM_QUADS) | BITFIELD_MASK(PIPE_PRIM_QUAD_STRIP)));
+      unsigned verts_per_primitive = outputting_quads ? 4 : 3;
 
       int vertex_count = original_primsi.count;
       if (!vertex_count) {
@@ -632,8 +635,8 @@
       }
 
       /* Increase indices storage if the original estimation was too small. */
-      if (idx + 3 * vertex_count > max_index_count) {
-         max_index_count = max_index_count + 3 * vertex_count;
+      if (idx + verts_per_primitive * vertex_count > max_index_count) {
+         max_index_count = max_index_count + verts_per_primitive * vertex_count;
          indices = (uint32_t*) realloc(indices, max_index_count * sizeof(uint32_t));
          tmp_indices = all_prims_supported ? NULL : realloc(tmp_indices, max_index_count * sizeof(uint32_t));
       }

_service:tar_scm:mesa-23.0.0.tar.xz/src/mesa/vbo/vbo_save_draw.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/mesa/vbo/vbo_save_draw.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/microsoft/compiler/nir_to_dxil.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/microsoft/compiler/nir_to_dxil.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/microsoft/vulkan/dzn_cmd_buffer.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/microsoft/vulkan/dzn_cmd_buffer.c Changed

@@ -211,12 +211,12 @@
 
    dzn_foreach_aspect(aspect, range->aspectMask) {
       D3D12_RESOURCE_STATES after =
-         dzn_image_layout_to_state(image, new_layout, aspect);
+         dzn_image_layout_to_state(image, new_layout, aspect, cmdbuf->type);
       D3D12_RESOURCE_STATES before =
          (old_layout == VK_IMAGE_LAYOUT_UNDEFINED ||
           old_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) ?
          D3D12_RESOURCE_STATE_COMMON :
-         dzn_image_layout_to_state(image, old_layout, aspect);
+         dzn_image_layout_to_state(image, old_layout, aspect, cmdbuf->type);
 
       uint32_t layer_count = dzn_get_layer_count(image, range);
       uint32_t level_count = dzn_get_level_count(image, range);
@@ -4219,8 +4219,8 @@
       .layerCount = MIN2(src->vk.layer_count, dst->vk.layer_count),
    };
 
-   D3D12_RESOURCE_STATES src_state = dzn_image_layout_to_state(src_img, src_layout, aspect);
-   D3D12_RESOURCE_STATES dst_state = dzn_image_layout_to_state(dst_img, dst_layout, aspect);
+   D3D12_RESOURCE_STATES src_state = dzn_image_layout_to_state(src_img, src_layout, aspect, cmdbuf->type);
+   D3D12_RESOURCE_STATES dst_state = dzn_image_layout_to_state(dst_img, dst_layout, aspect, cmdbuf->type);
    D3D12_BARRIER_LAYOUT src_restore_layout = D3D12_BARRIER_LAYOUT_COMMON,
       src_needed_layout = D3D12_BARRIER_LAYOUT_DIRECT_QUEUE_GENERIC_READ;
    D3D12_BARRIER_LAYOUT dst_restore_layout = D3D12_BARRIER_LAYOUT_COMMON,

_service:tar_scm:mesa-23.0.0.tar.xz/src/microsoft/vulkan/dzn_device.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/microsoft/vulkan/dzn_device.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/microsoft/vulkan/dzn_image.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/microsoft/vulkan/dzn_image.c Changed

@@ -580,11 +580,14 @@
 D3D12_RESOURCE_STATES
 dzn_image_layout_to_state(const struct dzn_image *image,
                           VkImageLayout layout,
-                          VkImageAspectFlagBits aspect)
+                          VkImageAspectFlagBits aspect,
+                          D3D12_COMMAND_LIST_TYPE type)
 {
    D3D12_RESOURCE_STATES shaders_access =
       (image->desc.Flags & D3D12_RESOURCE_FLAG_DENY_SHADER_RESOURCE) ?
-      0 : D3D12_RESOURCE_STATE_ALL_SHADER_RESOURCE;
+      0 : (type == D3D12_COMMAND_LIST_TYPE_DIRECT ?
+           D3D12_RESOURCE_STATE_ALL_SHADER_RESOURCE :
+           D3D12_RESOURCE_STATE_NON_PIXEL_SHADER_RESOURCE);
 
    switch (layout) {
    case VK_IMAGE_LAYOUT_PREINITIALIZED:
@@ -623,7 +626,7 @@
              D3D12_RESOURCE_STATE_DEPTH_WRITE;
 
    case VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL:
-      return D3D12_RESOURCE_STATE_ALL_SHADER_RESOURCE;
+      return shaders_access;
 
    case VK_IMAGE_LAYOUT_ATTACHMENT_FEEDBACK_LOOP_OPTIMAL_EXT:
       return D3D12_RESOURCE_STATE_COMMON;

_service:tar_scm:mesa-23.0.0.tar.xz/src/microsoft/vulkan/dzn_pipeline.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/microsoft/vulkan/dzn_pipeline.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/microsoft/vulkan/dzn_private.h -> _service:tar_scm:mesa-23.0.3.tar.xz/src/microsoft/vulkan/dzn_private.h Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/panfrost/ci/panfrost-g52-fails.txt -> _service:tar_scm:mesa-23.0.3.tar.xz/src/panfrost/ci/panfrost-g52-fails.txt Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/panfrost/ci/panfrost-t720-fails.txt -> _service:tar_scm:mesa-23.0.3.tar.xz/src/panfrost/ci/panfrost-t720-fails.txt Changed

@@ -19,26 +19,9 @@
 dEQP-GLES2.functional.fragment_ops.interaction.basic_shader.81,Fail
 dEQP-GLES2.functional.fragment_ops.random.43,Fail
 dEQP-GLES2.functional.fbo.completeness.renderable.texture.color0.rgb_half_float_oes,Fail
-dEQP-GLES2.functional.shaders.texture_functions.vertex.texturecubelod,Fail
-dEQP-GLES2.functional.texture.mipmap.cube.basic.linear_linear,Fail
-dEQP-GLES2.functional.texture.mipmap.cube.basic.linear_nearest,Fail
-dEQP-GLES2.functional.texture.mipmap.cube.bias.linear_linear,Fail
-dEQP-GLES2.functional.texture.mipmap.cube.bias.linear_nearest,Fail
-dEQP-GLES2.functional.texture.mipmap.cube.projected.linear_linear,Fail
-dEQP-GLES2.functional.texture.mipmap.cube.projected.linear_nearest,Fail
-dEQP-GLES2.functional.texture.vertex.cube.filtering.linear_mipmap_linear_linear_clamp,Fail
-dEQP-GLES2.functional.texture.vertex.cube.filtering.linear_mipmap_linear_linear_mirror,Fail
-dEQP-GLES2.functional.texture.vertex.cube.filtering.linear_mipmap_linear_nearest_clamp,Fail
-dEQP-GLES2.functional.texture.vertex.cube.filtering.linear_mipmap_linear_nearest_mirror,Fail
 dEQP-GLES2.functional.texture.vertex.cube.filtering.nearest_mipmap_linear_linear_clamp,Fail
 dEQP-GLES2.functional.texture.vertex.cube.filtering.nearest_mipmap_linear_linear_mirror,Fail
 dEQP-GLES2.functional.texture.vertex.cube.filtering.nearest_mipmap_linear_linear_repeat,Fail
 dEQP-GLES2.functional.texture.vertex.cube.filtering.nearest_mipmap_nearest_linear_clamp,Fail
 dEQP-GLES2.functional.texture.vertex.cube.filtering.nearest_mipmap_nearest_linear_mirror,Fail
 dEQP-GLES2.functional.texture.vertex.cube.filtering.nearest_mipmap_nearest_linear_repeat,Fail
-dEQP-GLES2.functional.texture.vertex.cube.wrap.clamp_clamp,Fail
-dEQP-GLES2.functional.texture.vertex.cube.wrap.clamp_mirror,Fail
-dEQP-GLES2.functional.texture.vertex.cube.wrap.clamp_repeat,Fail
-dEQP-GLES2.functional.texture.vertex.cube.wrap.mirror_clamp,Fail
-dEQP-GLES2.functional.texture.vertex.cube.wrap.mirror_mirror,Fail
-dEQP-GLES2.functional.texture.vertex.cube.wrap.mirror_repeat,Fail

_service:tar_scm:mesa-23.0.0.tar.xz/src/tool/pps/pps_counter.h -> _service:tar_scm:mesa-23.0.3.tar.xz/src/tool/pps/pps_counter.h Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/tool/pps/pps_device.h -> _service:tar_scm:mesa-23.0.3.tar.xz/src/tool/pps/pps_device.h Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/util/00-mesa-defaults.conf -> _service:tar_scm:mesa-23.0.3.tar.xz/src/util/00-mesa-defaults.conf Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/util/hash_table.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/util/hash_table.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/virtio/ci/gitlab-ci.yml -> _service:tar_scm:mesa-23.0.3.tar.xz/src/virtio/ci/gitlab-ci.yml Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/virtio/vulkan/vn_physical_device.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/virtio/vulkan/vn_physical_device.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/vulkan/overlay-layer/overlay.cpp -> _service:tar_scm:mesa-23.0.3.tar.xz/src/vulkan/overlay-layer/overlay.cpp Changed

@@ -89,6 +89,8 @@
    struct queue_data **queues;
    uint32_t n_queues;
 
+   bool pipeline_statistics_enabled;
+
    /* For a single frame */
    struct frame_stat frame_stats;
 };
@@ -290,6 +292,16 @@
    return NULL;
 }
 
+static void
+free_chain(struct VkBaseOutStructure *chain)
+{
+   while (chain) {
+      void *node = chain;
+      chain = chain->pNext;
+      free(node);
+   }
+}
+
 static struct VkBaseOutStructure *
 clone_chain(const struct VkBaseInStructure *chain)
 {
@@ -297,6 +309,11 @@
 
    vk_foreach_struct_const(item, chain) {
       size_t item_size = vk_structure_type_size(item);
+      if (item_size == 0) {
+         free_chain(head);
+         return NULL;
+      }
+
       struct VkBaseOutStructure *new_item =
          (struct VkBaseOutStructure *)malloc(item_size);;
 
@@ -312,16 +329,6 @@
    return head;
 }
 
-static void
-free_chain(struct VkBaseOutStructure *chain)
-{
-   while (chain) {
-      void *node = chain;
-      chain = chain->pNext;
-      free(node);
-   }
-}
-
 /**/
 
 static struct instance_data *new_instance_data(VkInstance instance)
@@ -2203,34 +2210,44 @@
     * we have the right inheritance.
     */
    if (cmd_buffer_data->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY) {
-      VkCommandBufferBeginInfo *begin_info = (VkCommandBufferBeginInfo *)
-         clone_chain((const struct VkBaseInStructure *)pBeginInfo);
-      VkCommandBufferInheritanceInfo *parent_inhe_info = (VkCommandBufferInheritanceInfo *)
-         vk_find_struct(begin_info, COMMAND_BUFFER_INHERITANCE_INFO);
-      VkCommandBufferInheritanceInfo inhe_info = {
-         VK_STRUCTURE_TYPE_COMMAND_BUFFER_INHERITANCE_INFO,
-         NULL,
-         VK_NULL_HANDLE,
-         0,
-         VK_NULL_HANDLE,
-         VK_FALSE,
-         0,
-         overlay_query_flags,
-      };
+      VkCommandBufferBeginInfo begin_info = *pBeginInfo;
 
-      if (parent_inhe_info)
-         parent_inhe_info->pipelineStatistics = overlay_query_flags;
-      else {
-         inhe_info.pNext = begin_info->pNext;
-         begin_info->pNext = &inhe_info;
-      }
+      struct VkBaseOutStructure *new_pnext =
+         clone_chain((const struct VkBaseInStructure *)pBeginInfo->pNext);
+      VkCommandBufferInheritanceInfo inhe_info;
+
+      /* If there was no pNext chain given or we managed to copy it, we can
+       * add our stuff in there.
+       *
+       * Otherwise, keep the old pointer. We failed to copy the pNext chain,
+       * meaning there is an unknown extension somewhere in there.
+       */
+      if (new_pnext || pBeginInfo->pNext == NULL) {
+         begin_info.pNext = new_pnext;
 
-      VkResult result = device_data->vtable.BeginCommandBuffer(commandBuffer, pBeginInfo);
+         VkCommandBufferInheritanceInfo *parent_inhe_info = (VkCommandBufferInheritanceInfo *)
+            vk_find_struct(new_pnext, COMMAND_BUFFER_INHERITANCE_INFO);
+         inhe_info = (VkCommandBufferInheritanceInfo) {
+            VK_STRUCTURE_TYPE_COMMAND_BUFFER_INHERITANCE_INFO,
+            NULL,
+            VK_NULL_HANDLE,
+            0,
+            VK_NULL_HANDLE,
+            VK_FALSE,
+            0,
+            overlay_query_flags,
+         };
+
+         if (parent_inhe_info)
+            parent_inhe_info->pipelineStatistics = overlay_query_flags;
+         else
+            __vk_append_struct(&begin_info, &inhe_info);
+      }
 
-      if (!parent_inhe_info)
-         begin_info->pNext = inhe_info.pNext;
+      VkResult result = device_data->vtable.BeginCommandBuffer(
+         commandBuffer, &begin_info);
 
-      free_chain((struct VkBaseOutStructure *)begin_info);
+      free_chain(new_pnext);
 
       return result;
    }
@@ -2334,7 +2351,7 @@
 
    VkQueryPool pipeline_query_pool = VK_NULL_HANDLE;
    VkQueryPool timestamp_query_pool = VK_NULL_HANDLE;
-   if (device_data->instance->pipeline_statistics_enabled &&
+   if (device_data->pipeline_statistics_enabled &&
        pAllocateInfo->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
       VkQueryPoolCreateInfo pool_info = {
          VK_STRUCTURE_TYPE_QUERY_POOL_CREATE_INFO,
@@ -2517,29 +2534,33 @@
    VkPhysicalDeviceFeatures device_features = {};
    VkPhysicalDeviceFeatures *device_features_ptr = NULL;
 
-   VkDeviceCreateInfo *device_info = (VkDeviceCreateInfo *)
-      clone_chain((const struct VkBaseInStructure *)pCreateInfo);
+   VkDeviceCreateInfo create_info = *pCreateInfo;
 
-   VkPhysicalDeviceFeatures2 *device_features2 = (VkPhysicalDeviceFeatures2 *)
-      vk_find_struct(device_info, PHYSICAL_DEVICE_FEATURES_2);
-   if (device_features2) {
-      /* Can't use device_info->pEnabledFeatures when VkPhysicalDeviceFeatures2 is present */
-      device_features_ptr = &device_features2->features;
-   } else {
-      if (device_info->pEnabledFeatures)
-         device_features = *(device_info->pEnabledFeatures);
-      device_features_ptr = &device_features;
-      device_info->pEnabledFeatures = &device_features;
-   }
+   struct VkBaseOutStructure *new_pnext =
+      clone_chain((const struct VkBaseInStructure *) pCreateInfo->pNext);
+   if (new_pnext != NULL) {
+      create_info.pNext = new_pnext;
+
+      VkPhysicalDeviceFeatures2 *device_features2 = (VkPhysicalDeviceFeatures2 *)
+         vk_find_struct(new_pnext, PHYSICAL_DEVICE_FEATURES_2);
+      if (device_features2) {
+         /* Can't use device_info->pEnabledFeatures when VkPhysicalDeviceFeatures2 is present */
+         device_features_ptr = &device_features2->features;
+      } else {
+         if (create_info.pEnabledFeatures)
+            device_features = *(create_info.pEnabledFeatures);
+         device_features_ptr = &device_features;
+         create_info.pEnabledFeatures = &device_features;
+      }
 
-   if (instance_data->pipeline_statistics_enabled) {
-      device_features_ptr->inheritedQueries = true;
-      device_features_ptr->pipelineStatisticsQuery = true;
+      if (instance_data->pipeline_statistics_enabled) {
+         device_features_ptr->inheritedQueries = true;
+         device_features_ptr->pipelineStatisticsQuery = true;
+      }
    }
 
-
-   VkResult result = fpCreateDevice(physicalDevice, device_info, pAllocator, pDevice);
-   free_chain((struct VkBaseOutStructure *)device_info);
+   VkResult result = fpCreateDevice(physicalDevice, &create_info, pAllocator, pDevice);
+   free_chain(new_pnext);
    if (result != VK_SUCCESS) return result;
 
    struct device_data *device_data = new_device_data(*pDevice, instance_data);
@@ -2556,6 +2577,10 @@
 
    device_map_queues(device_data, pCreateInfo);
 
+   device_data->pipeline_statistics_enabled =
+      new_pnext != NULL &&
+      instance_data->pipeline_statistics_enabled;
+
    return result;
 }

_service:tar_scm:mesa-23.0.0.tar.xz/src/vulkan/runtime/vk_graphics_state.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/vulkan/runtime/vk_graphics_state.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/vulkan/util/gen_enum_to_str.py -> _service:tar_scm:mesa-23.0.3.tar.xz/src/vulkan/util/gen_enum_to_str.py Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/vulkan/wsi/wsi_common_display.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/vulkan/wsi/wsi_common_display.c Changed

_service:tar_scm:mesa-23.0.0.tar.xz/src/vulkan/wsi/wsi_common_wayland.c -> _service:tar_scm:mesa-23.0.3.tar.xz/src/vulkan/wsi/wsi_common_wayland.c Changed

_service:tar_scm:vendor.tar.xz Deleted

Changes of Revision 33