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Changes of Revision 2
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_service:tar_scm:gcc.spec
Changed
@@ -2,7 +2,7 @@ %global gcc_major 12 # Note, gcc_release must be integer, if you want to add suffixes to # %%{release}, append them after %%{gcc_release} on Release: line. -%global gcc_release 16 +%global gcc_release 20 %global _unpackaged_files_terminate_build 0 %global _performance_build 1 @@ -23,38 +23,38 @@ %else %global build_libquadmath 0 %endif -%ifarch %{ix86} x86_64 ppc ppc64 ppc64le ppc64p7 s390 s390x %{arm} aarch64 +%ifarch %{ix86} x86_64 ppc ppc64 ppc64le ppc64p7 s390 s390x %{arm} aarch64 loongarch64 %global build_libasan 1 %else %global build_libasan 0 %endif -%ifarch x86_64 ppc64 ppc64le aarch64 s390x +%ifarch x86_64 ppc64 ppc64le aarch64 s390x loongarch64 %global build_libtsan 1 %else %global build_libtsan 0 %endif -%ifarch x86_64 ppc64 ppc64le aarch64 s390x +%ifarch x86_64 ppc64 ppc64le aarch64 s390x loongarch64 %global build_liblsan 1 %else %global build_liblsan 0 %endif -%ifarch %{ix86} x86_64 ppc ppc64 ppc64le ppc64p7 s390 s390x %{arm} aarch64 +%ifarch %{ix86} x86_64 ppc ppc64 ppc64le ppc64p7 s390 s390x %{arm} aarch64 loongarch64 %global build_libubsan 1 %else %global build_libubsan 0 %endif -%ifarch %{ix86} x86_64 ppc ppc64 ppc64le ppc64p7 s390 s390x %{arm} aarch64 %{mips} riscv64 +%ifarch %{ix86} x86_64 ppc ppc64 ppc64le ppc64p7 s390 s390x %{arm} aarch64 %{mips} riscv64 loongarch64 %global build_libatomic 1 %else %global build_libatomic 0 %endif -%ifarch %{ix86} x86_64 %{arm} alpha ppc ppc64 ppc64le ppc64p7 s390 s390x aarch64 +%ifarch %{ix86} x86_64 %{arm} alpha ppc ppc64 ppc64le ppc64p7 s390 s390x aarch64 loongarch64 %global build_libitm 1 %else %global build_libitm 0 %endif %global build_libstdcxx_docs 0 -%ifarch %{ix86} x86_64 ppc ppc64 ppc64le ppc64p7 s390 s390x %{arm} aarch64 %{mips} +%ifarch %{ix86} x86_64 ppc ppc64 ppc64le ppc64p7 s390 s390x %{arm} aarch64 %{mips} loongarch64 %global attr_ifunc 1 %else %global attr_ifunc 0 @@ -72,6 +72,9 @@ %global _lib lib %global _smp_mflags -j8 %endif +%ifarch loongarch64 +%global _lib lib +%endif %global isl_enable 1 %global check_enable 0 @@ -164,6 +167,135 @@ Patch27: 0027-LoopElim-Redundant-loop-elimination-optimization.patch Patch28: 0028-Array-widen-compare-Fix-the-return-value-match-after.patch +# Part 3000 ~ 4999 +%ifarch loongarch64 +Patch3001: loongarch-add-alternatives-for-idiv-insns-to-improve.patch +Patch3002: loongarch-avoid-unnecessary-sign-extend-after-32-bit.patch +Patch3003: LoongArch-Subdivision-symbol-type-add-SYMBOL_PCREL-s.patch +Patch3004: LoongArch-Support-split-symbol.patch +Patch3005: LoongArch-Modify-the-output-message-string-of-the-wa.patch +Patch3006: LoongArch-adjust-the-default-of-mexplicit-relocs-by-.patch +Patch3007: LoongArch-document-m-no-explicit-relocs.patch +Patch3008: LoongArch-Define-the-macro-ASM_PREFERRED_EH_DATA_FOR.patch +Patch3009: LoongArch-Provide-fmin-fmax-RTL-pattern.patch +Patch3010: LoongArch-Get-__tls_get_addr-address-through-got-tab.patch +Patch3011: LoongArch-Add-support-code-model-extreme.patch +Patch3012: LoongArch-Add-new-code-model-medium.patch +Patch3013: LoongArch-Avoid-RTL-flag-check-failure-in-loongarch_.patch +Patch3014: LoongArch-add-model-attribute.patch +Patch3015: LoongArch-testsuite-refine-__tls_get_addr-tests-with.patch +Patch3016: LoongArch-add-mdirect-extern-access-option.patch +Patch3017: LoongArch-Fix-pr106828-by-define-hook-TARGET_ASAN_SH.patch +Patch3018: LoongArch-Prepare-static-PIE-support.patch +Patch3019: LoongArch-Libitm-add-LoongArch-support.patch +Patch3020: LoongArch-Fixed-a-typo-in-the-comment-information-of.patch +Patch3021: LoongArch-Use-UNSPEC-for-fmin-fmax-RTL-pattern-PR105.patch +Patch3022: LoongArch-Fixed-a-bug-in-the-loongarch-architecture-.patch +Patch3023: LoongArch-implement-count_-leading-trailing-_zeros.patch +Patch3024: Libvtv-Add-loongarch-support.patch +Patch3025: LoongArch-Add-fcopysign-instructions.patch +Patch3026: LoongArch-fix-signed-overflow-in-loongarch_emit_int_.patch +Patch3027: LoongArch-Rename-frint_-fmt-to-rint-mode-2.patch +Patch3028: LoongArch-Add-ftint-rm-rp-.-w-l-.-s-d-instructions.patch +Patch3029: LoongArch-Add-fscaleb.-s-d-instructions-as-ldexp-sf-.patch +Patch3030: LoongArch-Add-flogb.-s-d-instructions-and-expand-log.patch +Patch3031: LoongArch-Add-prefetch-instructions.patch +Patch3032: LoongArch-Optimize-immediate-load.patch +Patch3033: LoongArch-Optimize-the-implementation-of-stack-check.patch +Patch3034: LoongArch-Fixed-a-compilation-failure-with-c-in-inli.patch +Patch3035: LoongArch-Don-t-add-crtfastmath.o-for-shared.patch +Patch3036: LoongArch-Generate-bytepick.-wd-for-suitable-bit-ope.patch +Patch3037: LoongArch-Change-the-value-of-macro-TRY_EMPTY_VM_SPA.patch +Patch3038: LoongArch-testsuite-Disable-stack-protector-for-some.patch +Patch3039: LoongArch-Add-built-in-functions-description-of-Loon.patch +Patch3040: LoongArch-Remove-the-definition-of-the-macro-LOGICAL.patch +Patch3041: LoongArch-Optimize-additions-with-immediates.patch +Patch3042: LoongArch-Improve-GAR-store-for-va_list.patch +Patch3043: LoongArch-Improve-cpymemsi-expansion-PR109465.patch +Patch3044: LoongArch-Fix-MUSL_DYNAMIC_LINKER.patch +Patch3045: LoongArch-Enable-shrink-wrapping.patch +Patch3046: LoongArch-Change-the-default-value-of-LARCH_CALL_RAT.patch +Patch3047: LoongArch-Set-default-alignment-for-functions-and-la.patch +Patch3048: LoongArch-Avoid-non-returning-indirect-jumps-through.patch +Patch3049: Loongarch-Fix-plugin-header-missing-install.patch +Patch3050: libffi-Backport-of-LoongArch-support-for-libffi.patch +Patch3051: LoongArch-Remove-redundant-sign-extension-instructio.patch +Patch3052: LoongArch-Enable-free-starting-at-O2.patch +Patch3053: LoongArch-Fix-bug-in-loongarch_emit_stack_tie-PR1104.patch +Patch3054: LoongArch-Implement-128-bit-floating-point-functions.patch +Patch3056: LoongArch-Optimize-switch-with-sign-extended-index.patch +Patch3057: LoongArch-Support-storing-floating-point-zero-into-M.patch +Patch3058: LoongArch-improved-target-configuration-interface.patch +Patch3059: LoongArch-define-preprocessing-macros-__loongarch_-a.patch +Patch3060: LoongArch-add-new-configure-option-with-strict-align.patch +Patch3061: LoongArch-support-loongarch-elf-target.patch +Patch3062: LoongArch-initial-ada-support-on-linux.patch +Patch3063: LoongArch-Add-Loongson-SX-base-instruction-support.patch +Patch3064: LoongArch-Add-Loongson-SX-directive-builtin-function.patch +Patch3065: LoongArch-Add-Loongson-ASX-base-instruction-support.patch +Patch3066: LoongArch-Add-Loongson-ASX-directive-builtin-functio.patch +Patch3067: LoongArch-Fix-unintentionally-breakage-in-r14-3665.patch +Patch3068: LoongArch-Use-bstrins-instruction-for-a-mask-and-a-m.patch +Patch3069: LoongArch-Adjust-C-multilib-header-layout.patch +Patch3070: LoongArch-Fix-unintentional-bash-ism-in-r14-3665.patch +Patch3071: LoongArch-Enable-fsched-pressure-by-default-at-O1-an.patch +Patch3072: LoongArch-Use-LSX-and-LASX-for-block-move.patch +Patch3073: LoongArch-Slightly-simplify-loongarch_block_move_str.patch +Patch3074: LoongArch-Optimized-multiply-instruction-generation.patch +Patch3075: LoongArch-Fix-up-memcpy-vec-3.c-test-case.patch +Patch3076: LoongArch-Add-tests-of-mstrict-align-option.patch +Patch3077: LoongArch-Add-testsuite-framework-for-Loongson-SX-AS.patch +Patch3078: LoongArch-Add-tests-for-Loongson-SX-builtin-function.patch +Patch3079: LoongArch-Add-tests-for-SX-vector-floating-point-ins.patch +Patch3080: LoongArch-Add-tests-for-SX-vector-addition-instructi.patch +Patch3081: LoongArch-Add-tests-for-SX-vector-subtraction-instru.patch +Patch3082: LoongArch-Add-tests-for-SX-vector-addition-vsadd-ins.patch +Patch3083: LoongArch-Add-tests-for-the-SX-vector-multiplication.patch +Patch3084: LoongArch-Add-tests-for-SX-vector-vavg-vavgr-instruc.patch +Patch3085: LoongArch-Add-tests-for-SX-vector-vmax-vmaxi-vmin-vm.patch +Patch3086: LoongArch-Add-tests-for-SX-vector-vexth-vextl-vldi-v.patch +Patch3087: LoongArch-Add-tests-for-SX-vector-vabsd-vmskgez-vmsk.patch +Patch3088: LoongArch-Add-tests-for-SX-vector-vdiv-vmod-instruct.patch +Patch3089: LoongArch-Add-tests-for-SX-vector-vsll-vslli-vsrl-vs.patch +Patch3090: LoongArch-Add-tests-for-SX-vector-vrotr-vrotri-vsra-.patch +Patch3091: LoongArch-Add-tests-for-SX-vector-vssran-vssrani-vss.patch +Patch3092: LoongArch-Add-tests-for-SX-vector-vbitclr-vbitclri-v.patch +Patch3093: LoongArch-Add-tests-for-SX-vector-floating-point-ari.patch +Patch3094: LoongArch-Add-tests-for-SX-vector-vfrstp-vfrstpi-vse.patch +Patch3095: LoongArch-Add-tests-for-SX-vector-vfcmp-instructions.patch +Patch3096: LoongArch-Add-tests-for-SX-vector-handling-and-shuff.patch +Patch3097: LoongArch-Add-tests-for-SX-vector-vand-vandi-vandn-v.patch +Patch3098: LoongArch-Add-tests-for-SX-vector-vfmadd-vfnmadd-vld.patch +Patch3099: LoongArch-Add-tests-for-ASX-vector-xvadd-xvadda-xvad.patch +Patch3100: LoongArch-Add-tests-for-ASX-vector-xvhadd-xvhaddw-xv.patch +Patch3101: LoongArch-Add-tests-for-ASX-vector-subtraction-instr.patch +Patch3102: LoongArch-Add-tests-for-ASX-vector-xvmul-xvmod-xvdiv.patch +Patch3103: LoongArch-Add-tests-for-ASX-vector-xvmax-xvmaxi-xvmi.patch +Patch3104: LoongArch-Add-tests-for-ASX-vector-xvldi-xvmskgez-xv.patch +Patch3105: LoongArch-Add-tests-for-ASX-vector-xvand-xvandi-xvan.patch +Patch3106: LoongArch-Add-tests-for-ASX-vector-xvsll-xvsrl-instr.patch +Patch3107: LoongArch-Add-tests-for-ASX-vector-xvextl-xvsra-xvsr.patch +Patch3108: LoongArch-Add-tests-for-ASX-vector-xvbitclr-xvbitclr.patch +Patch3109: LoongArch-Add-tests-for-ASX-builtin-functions.patch +Patch3110: LoongArch-Add-tests-for-ASX-xvldrepl-xvstelm-instruc.patch +Patch3111: LoongArch-Add-tests-for-ASX-vector-floating-point-op.patch +Patch3112: LoongArch-Add-tests-for-ASX-vector-floating-point-co.patch +Patch3113: LoongArch-Add-tests-for-ASX-vector-comparison-and-se.patch +Patch3114: LoongArch-Add-tests-for-ASX-vector-xvfnmadd-xvfrstp-.patch +Patch3115: LoongArch-Add-tests-for-ASX-vector-xvabsd-xvavg-xvav.patch +Patch3116: LoongArch-Add-tests-for-ASX-vector-xvfcmp-caf-ceq-cl.patch +Patch3117: LoongArch-Add-tests-for-ASX-vector-xvfcmp-saf-seq-sl.patch +Patch3118: LoongArch-Add-tests-for-ASX-vector-xvext2xv-xvexth-x.patch +Patch3119: LoongArch-Add-tests-for-ASX-vector-xvpackev-xvpackod.patch +Patch3120: LoongArch-Add-tests-for-ASX-vector-xvssrln-xvssrlni-.patch +Patch3121: LoongArch-Add-tests-for-ASX-vector-xvssran-xvssrani-.patch +Patch3122: LoongArch-Fix-bug-of-optab-di3_fake.patch +Patch3123: LoongArch-Change-the-value-of-branch_cost-from-2-to-.patch +Patch3124: libsanitizer-add-LoongArch-support.patch +Patch3125: LoongArch-fix-error-building.patch +Patch3126: libjccjit-do-not-link-objects-contained-same-element.patch +%endif + # On ARM EABI systems, we do want -gnueabi to be part of the # target triple.
View file
_service:tar_scm:Libvtv-Add-loongarch-support.patch
Added
@@ -0,0 +1,59 @@ +From 62ea18c632200edbbf46b4e957bc4d997f1c66f0 Mon Sep 17 00:00:00 2001 +From: Lulu Cheng <chenglulu@loongson.cn> +Date: Tue, 27 Sep 2022 15:28:43 +0800 +Subject: PATCH 024/124 Libvtv: Add loongarch support. + +The loongarch64 specification permits page sizes of 4KiB, 16KiB and 64KiB, +but only 16KiB pages are supported for now. + +Co-Authored-By: qijingwen <qijingwen@loongson.cn> + +include/ChangeLog: + + * vtv-change-permission.h (defined): Determines whether the macro + __loongarch_lp64 is defined + (VTV_PAGE_SIZE): Set VTV_PAGE_SIZE to 16KiB for loongarch64. + +libvtv/ChangeLog: + + * configure.tgt: Add loongarch support. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + include/vtv-change-permission.h | 4 ++++ + libvtv/configure.tgt | 3 +++ + 2 files changed, 7 insertions(+) + +diff --git a/include/vtv-change-permission.h b/include/vtv-change-permission.h +index 70bdad92b..e7b9294a0 100644 +--- a/include/vtv-change-permission.h ++++ b/include/vtv-change-permission.h +@@ -48,6 +48,10 @@ extern void __VLTChangePermission (int); + #else + #if defined(__sun__) && defined(__svr4__) && defined(__sparc__) + #define VTV_PAGE_SIZE 8192 ++#elif defined(__loongarch_lp64) ++/* The page size is configurable by the kernel to be 4, 16 or 64 KiB. ++ For now, only the default page size of 16KiB is supported. */ ++#define VTV_PAGE_SIZE 16384 + #else + #define VTV_PAGE_SIZE 4096 + #endif +diff --git a/libvtv/configure.tgt b/libvtv/configure.tgt +index aa2a3f675..6cdd1e97a 100644 +--- a/libvtv/configure.tgt ++++ b/libvtv/configure.tgt +@@ -50,6 +50,9 @@ case "${target}" in + ;; + x86_64-*-darwin1* | i?86-*-darwin1*) + ;; ++ loongarch*-*-linux*) ++ VTV_SUPPORTED=yes ++ ;; + *) + ;; + esac +-- +2.33.0 +
View file
_service:tar_scm:LoongArch-Add-Loongson-ASX-base-instruction-support.patch
Added
@@ -0,0 +1,8376 @@ +From 2f0874e6e6f5a866e71826983dc18295c408748b Mon Sep 17 00:00:00 2001 +From: Lulu Cheng <chenglulu@loongson.cn> +Date: Thu, 16 Mar 2023 16:34:08 +0800 +Subject: PATCH 065/124 LoongArch: Add Loongson ASX base instruction support. + +gcc/ChangeLog: + + * config/loongarch/loongarch-modes.def + (VECTOR_MODES): Add Loongson ASX instruction support. + * config/loongarch/loongarch-protos.h (loongarch_split_256bit_move): Ditto. + (loongarch_split_256bit_move_p): Ditto. + (loongarch_expand_vector_group_init): Ditto. + (loongarch_expand_vec_perm_1): Ditto. + * config/loongarch/loongarch.cc (loongarch_symbol_insns): Ditto. + (loongarch_valid_offset_p): Ditto. + (loongarch_address_insns): Ditto. + (loongarch_const_insns): Ditto. + (loongarch_legitimize_move): Ditto. + (loongarch_builtin_vectorization_cost): Ditto. + (loongarch_split_move_p): Ditto. + (loongarch_split_move): Ditto. + (loongarch_output_move_index_float): Ditto. + (loongarch_split_256bit_move_p): Ditto. + (loongarch_split_256bit_move): Ditto. + (loongarch_output_move): Ditto. + (loongarch_print_operand_reloc): Ditto. + (loongarch_print_operand): Ditto. + (loongarch_hard_regno_mode_ok_uncached): Ditto. + (loongarch_hard_regno_nregs): Ditto. + (loongarch_class_max_nregs): Ditto. + (loongarch_can_change_mode_class): Ditto. + (loongarch_mode_ok_for_mov_fmt_p): Ditto. + (loongarch_vector_mode_supported_p): Ditto. + (loongarch_preferred_simd_mode): Ditto. + (loongarch_autovectorize_vector_modes): Ditto. + (loongarch_lsx_output_division): Ditto. + (loongarch_expand_lsx_shuffle): Ditto. + (loongarch_expand_vec_perm): Ditto. + (loongarch_expand_vec_perm_interleave): Ditto. + (loongarch_try_expand_lsx_vshuf_const): Ditto. + (loongarch_expand_vec_perm_even_odd_1): Ditto. + (loongarch_expand_vec_perm_even_odd): Ditto. + (loongarch_expand_vec_perm_1): Ditto. + (loongarch_expand_vec_perm_const_2): Ditto. + (loongarch_is_quad_duplicate): Ditto. + (loongarch_is_double_duplicate): Ditto. + (loongarch_is_odd_extraction): Ditto. + (loongarch_is_even_extraction): Ditto. + (loongarch_is_extraction_permutation): Ditto. + (loongarch_is_center_extraction): Ditto. + (loongarch_is_reversing_permutation): Ditto. + (loongarch_is_di_misalign_extract): Ditto. + (loongarch_is_si_misalign_extract): Ditto. + (loongarch_is_lasx_lowpart_interleave): Ditto. + (loongarch_is_lasx_lowpart_interleave_2): Ditto. + (COMPARE_SELECTOR): Ditto. + (loongarch_is_lasx_lowpart_extract): Ditto. + (loongarch_is_lasx_highpart_interleave): Ditto. + (loongarch_is_lasx_highpart_interleave_2): Ditto. + (loongarch_is_elem_duplicate): Ditto. + (loongarch_is_op_reverse_perm): Ditto. + (loongarch_is_single_op_perm): Ditto. + (loongarch_is_divisible_perm): Ditto. + (loongarch_is_triple_stride_extract): Ditto. + (loongarch_vectorize_vec_perm_const): Ditto. + (loongarch_cpu_sched_reassociation_width): Ditto. + (loongarch_expand_vector_extract): Ditto. + (emit_reduc_half): Ditto. + (loongarch_expand_vec_unpack): Ditto. + (loongarch_expand_vector_group_init): Ditto. + (loongarch_expand_vector_init): Ditto. + (loongarch_expand_lsx_cmp): Ditto. + (loongarch_builtin_support_vector_misalignment): Ditto. + * config/loongarch/loongarch.h (UNITS_PER_LASX_REG): Ditto. + (BITS_PER_LASX_REG): Ditto. + (STRUCTURE_SIZE_BOUNDARY): Ditto. + (LASX_REG_FIRST): Ditto. + (LASX_REG_LAST): Ditto. + (LASX_REG_NUM): Ditto. + (LASX_REG_P): Ditto. + (LASX_REG_RTX_P): Ditto. + (LASX_SUPPORTED_MODE_P): Ditto. + * config/loongarch/loongarch.md: Ditto. + * config/loongarch/lasx.md: New file. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/lasx.md | 5104 ++++++++++++++++++++++ + gcc/config/loongarch/loongarch-modes.def | 1 + + gcc/config/loongarch/loongarch-protos.h | 4 + + gcc/config/loongarch/loongarch.cc | 2567 ++++++++++- + gcc/config/loongarch/loongarch.h | 60 +- + gcc/config/loongarch/loongarch.md | 20 +- + 6 files changed, 7637 insertions(+), 119 deletions(-) + create mode 100644 gcc/config/loongarch/lasx.md + +diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md +new file mode 100644 +index 000000000..8111c8bb7 +--- /dev/null ++++ b/gcc/config/loongarch/lasx.md +@@ -0,0 +1,5104 @@ ++;; Machine Description for LARCH Loongson ASX ASE ++;; ++;; Copyright (C) 2018 Free Software Foundation, Inc. ++;; ++;; This file is part of GCC. ++;; ++;; GCC is free software; you can redistribute it and/or modify ++;; it under the terms of the GNU General Public License as published by ++;; the Free Software Foundation; either version 3, or (at your option) ++;; any later version. ++;; ++;; GCC is distributed in the hope that it will be useful, ++;; but WITHOUT ANY WARRANTY; without even the implied warranty of ++;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++;; GNU General Public License for more details. ++;; ++;; You should have received a copy of the GNU General Public License ++;; along with GCC; see the file COPYING3. If not see ++;; <http://www.gnu.org/licenses/>. ++;; ++ ++(define_c_enum "unspec" ++ UNSPEC_LASX_XVABSD_S ++ UNSPEC_LASX_XVABSD_U ++ UNSPEC_LASX_XVAVG_S ++ UNSPEC_LASX_XVAVG_U ++ UNSPEC_LASX_XVAVGR_S ++ UNSPEC_LASX_XVAVGR_U ++ UNSPEC_LASX_XVBITCLR ++ UNSPEC_LASX_XVBITCLRI ++ UNSPEC_LASX_XVBITREV ++ UNSPEC_LASX_XVBITREVI ++ UNSPEC_LASX_XVBITSET ++ UNSPEC_LASX_XVBITSETI ++ UNSPEC_LASX_XVFCMP_CAF ++ UNSPEC_LASX_XVFCLASS ++ UNSPEC_LASX_XVFCMP_CUNE ++ UNSPEC_LASX_XVFCVT ++ UNSPEC_LASX_XVFCVTH ++ UNSPEC_LASX_XVFCVTL ++ UNSPEC_LASX_XVFLOGB ++ UNSPEC_LASX_XVFRECIP ++ UNSPEC_LASX_XVFRINT ++ UNSPEC_LASX_XVFRSQRT ++ UNSPEC_LASX_XVFCMP_SAF ++ UNSPEC_LASX_XVFCMP_SEQ ++ UNSPEC_LASX_XVFCMP_SLE ++ UNSPEC_LASX_XVFCMP_SLT ++ UNSPEC_LASX_XVFCMP_SNE ++ UNSPEC_LASX_XVFCMP_SOR ++ UNSPEC_LASX_XVFCMP_SUEQ ++ UNSPEC_LASX_XVFCMP_SULE ++ UNSPEC_LASX_XVFCMP_SULT ++ UNSPEC_LASX_XVFCMP_SUN ++ UNSPEC_LASX_XVFCMP_SUNE ++ UNSPEC_LASX_XVFTINT_S ++ UNSPEC_LASX_XVFTINT_U ++ UNSPEC_LASX_XVCLO ++ UNSPEC_LASX_XVSAT_S ++ UNSPEC_LASX_XVSAT_U ++ UNSPEC_LASX_XVREPLVE0 ++ UNSPEC_LASX_XVREPL128VEI ++ UNSPEC_LASX_XVSRAR ++ UNSPEC_LASX_XVSRARI ++ UNSPEC_LASX_XVSRLR ++ UNSPEC_LASX_XVSRLRI ++ UNSPEC_LASX_XVSHUF ++ UNSPEC_LASX_XVSHUF_B ++ UNSPEC_LASX_BRANCH ++ UNSPEC_LASX_BRANCH_V ++ ++ UNSPEC_LASX_XVMUH_S ++ UNSPEC_LASX_XVMUH_U ++ UNSPEC_LASX_MXVEXTW_U ++ UNSPEC_LASX_XVSLLWIL_S ++ UNSPEC_LASX_XVSLLWIL_U ++ UNSPEC_LASX_XVSRAN ++ UNSPEC_LASX_XVSSRAN_S ++ UNSPEC_LASX_XVSSRAN_U ++ UNSPEC_LASX_XVSRARN ++ UNSPEC_LASX_XVSSRARN_S ++ UNSPEC_LASX_XVSSRARN_U ++ UNSPEC_LASX_XVSRLN ++ UNSPEC_LASX_XVSSRLN_U ++ UNSPEC_LASX_XVSRLRN ++ UNSPEC_LASX_XVSSRLRN_U ++ UNSPEC_LASX_XVFRSTPI ++ UNSPEC_LASX_XVFRSTP ++ UNSPEC_LASX_XVSHUF4I ++ UNSPEC_LASX_XVBSRL_V ++ UNSPEC_LASX_XVBSLL_V ++ UNSPEC_LASX_XVEXTRINS ++ UNSPEC_LASX_XVMSKLTZ ++ UNSPEC_LASX_XVSIGNCOV ++ UNSPEC_LASX_XVFTINTRNE_W_S ++ UNSPEC_LASX_XVFTINTRNE_L_D
View file
_service:tar_scm:LoongArch-Add-Loongson-ASX-directive-builtin-functio.patch
Added
@@ -0,0 +1,7458 @@ +From 6871a6a4ef5f10bc75a9dd76fff37302057cf528 Mon Sep 17 00:00:00 2001 +From: Lulu Cheng <chenglulu@loongson.cn> +Date: Fri, 25 Nov 2022 11:09:49 +0800 +Subject: PATCH 066/124 LoongArch: Add Loongson ASX directive builtin + function support. + +gcc/ChangeLog: + + * config.gcc: Export the header file lasxintrin.h. + * config/loongarch/loongarch-builtins.cc (enum loongarch_builtin_type): + Add Loongson ASX builtin functions support. + (AVAIL_ALL): Ditto. + (LASX_BUILTIN): Ditto. + (LASX_NO_TARGET_BUILTIN): Ditto. + (LASX_BUILTIN_TEST_BRANCH): Ditto. + (CODE_FOR_lasx_xvsadd_b): Ditto. + (CODE_FOR_lasx_xvsadd_h): Ditto. + (CODE_FOR_lasx_xvsadd_w): Ditto. + (CODE_FOR_lasx_xvsadd_d): Ditto. + (CODE_FOR_lasx_xvsadd_bu): Ditto. + (CODE_FOR_lasx_xvsadd_hu): Ditto. + (CODE_FOR_lasx_xvsadd_wu): Ditto. + (CODE_FOR_lasx_xvsadd_du): Ditto. + (CODE_FOR_lasx_xvadd_b): Ditto. + (CODE_FOR_lasx_xvadd_h): Ditto. + (CODE_FOR_lasx_xvadd_w): Ditto. + (CODE_FOR_lasx_xvadd_d): Ditto. + (CODE_FOR_lasx_xvaddi_bu): Ditto. + (CODE_FOR_lasx_xvaddi_hu): Ditto. + (CODE_FOR_lasx_xvaddi_wu): Ditto. + (CODE_FOR_lasx_xvaddi_du): Ditto. + (CODE_FOR_lasx_xvand_v): Ditto. + (CODE_FOR_lasx_xvandi_b): Ditto. + (CODE_FOR_lasx_xvbitsel_v): Ditto. + (CODE_FOR_lasx_xvseqi_b): Ditto. + (CODE_FOR_lasx_xvseqi_h): Ditto. + (CODE_FOR_lasx_xvseqi_w): Ditto. + (CODE_FOR_lasx_xvseqi_d): Ditto. + (CODE_FOR_lasx_xvslti_b): Ditto. + (CODE_FOR_lasx_xvslti_h): Ditto. + (CODE_FOR_lasx_xvslti_w): Ditto. + (CODE_FOR_lasx_xvslti_d): Ditto. + (CODE_FOR_lasx_xvslti_bu): Ditto. + (CODE_FOR_lasx_xvslti_hu): Ditto. + (CODE_FOR_lasx_xvslti_wu): Ditto. + (CODE_FOR_lasx_xvslti_du): Ditto. + (CODE_FOR_lasx_xvslei_b): Ditto. + (CODE_FOR_lasx_xvslei_h): Ditto. + (CODE_FOR_lasx_xvslei_w): Ditto. + (CODE_FOR_lasx_xvslei_d): Ditto. + (CODE_FOR_lasx_xvslei_bu): Ditto. + (CODE_FOR_lasx_xvslei_hu): Ditto. + (CODE_FOR_lasx_xvslei_wu): Ditto. + (CODE_FOR_lasx_xvslei_du): Ditto. + (CODE_FOR_lasx_xvdiv_b): Ditto. + (CODE_FOR_lasx_xvdiv_h): Ditto. + (CODE_FOR_lasx_xvdiv_w): Ditto. + (CODE_FOR_lasx_xvdiv_d): Ditto. + (CODE_FOR_lasx_xvdiv_bu): Ditto. + (CODE_FOR_lasx_xvdiv_hu): Ditto. + (CODE_FOR_lasx_xvdiv_wu): Ditto. + (CODE_FOR_lasx_xvdiv_du): Ditto. + (CODE_FOR_lasx_xvfadd_s): Ditto. + (CODE_FOR_lasx_xvfadd_d): Ditto. + (CODE_FOR_lasx_xvftintrz_w_s): Ditto. + (CODE_FOR_lasx_xvftintrz_l_d): Ditto. + (CODE_FOR_lasx_xvftintrz_wu_s): Ditto. + (CODE_FOR_lasx_xvftintrz_lu_d): Ditto. + (CODE_FOR_lasx_xvffint_s_w): Ditto. + (CODE_FOR_lasx_xvffint_d_l): Ditto. + (CODE_FOR_lasx_xvffint_s_wu): Ditto. + (CODE_FOR_lasx_xvffint_d_lu): Ditto. + (CODE_FOR_lasx_xvfsub_s): Ditto. + (CODE_FOR_lasx_xvfsub_d): Ditto. + (CODE_FOR_lasx_xvfmul_s): Ditto. + (CODE_FOR_lasx_xvfmul_d): Ditto. + (CODE_FOR_lasx_xvfdiv_s): Ditto. + (CODE_FOR_lasx_xvfdiv_d): Ditto. + (CODE_FOR_lasx_xvfmax_s): Ditto. + (CODE_FOR_lasx_xvfmax_d): Ditto. + (CODE_FOR_lasx_xvfmin_s): Ditto. + (CODE_FOR_lasx_xvfmin_d): Ditto. + (CODE_FOR_lasx_xvfsqrt_s): Ditto. + (CODE_FOR_lasx_xvfsqrt_d): Ditto. + (CODE_FOR_lasx_xvflogb_s): Ditto. + (CODE_FOR_lasx_xvflogb_d): Ditto. + (CODE_FOR_lasx_xvmax_b): Ditto. + (CODE_FOR_lasx_xvmax_h): Ditto. + (CODE_FOR_lasx_xvmax_w): Ditto. + (CODE_FOR_lasx_xvmax_d): Ditto. + (CODE_FOR_lasx_xvmaxi_b): Ditto. + (CODE_FOR_lasx_xvmaxi_h): Ditto. + (CODE_FOR_lasx_xvmaxi_w): Ditto. + (CODE_FOR_lasx_xvmaxi_d): Ditto. + (CODE_FOR_lasx_xvmax_bu): Ditto. + (CODE_FOR_lasx_xvmax_hu): Ditto. + (CODE_FOR_lasx_xvmax_wu): Ditto. + (CODE_FOR_lasx_xvmax_du): Ditto. + (CODE_FOR_lasx_xvmaxi_bu): Ditto. + (CODE_FOR_lasx_xvmaxi_hu): Ditto. + (CODE_FOR_lasx_xvmaxi_wu): Ditto. + (CODE_FOR_lasx_xvmaxi_du): Ditto. + (CODE_FOR_lasx_xvmin_b): Ditto. + (CODE_FOR_lasx_xvmin_h): Ditto. + (CODE_FOR_lasx_xvmin_w): Ditto. + (CODE_FOR_lasx_xvmin_d): Ditto. + (CODE_FOR_lasx_xvmini_b): Ditto. + (CODE_FOR_lasx_xvmini_h): Ditto. + (CODE_FOR_lasx_xvmini_w): Ditto. + (CODE_FOR_lasx_xvmini_d): Ditto. + (CODE_FOR_lasx_xvmin_bu): Ditto. + (CODE_FOR_lasx_xvmin_hu): Ditto. + (CODE_FOR_lasx_xvmin_wu): Ditto. + (CODE_FOR_lasx_xvmin_du): Ditto. + (CODE_FOR_lasx_xvmini_bu): Ditto. + (CODE_FOR_lasx_xvmini_hu): Ditto. + (CODE_FOR_lasx_xvmini_wu): Ditto. + (CODE_FOR_lasx_xvmini_du): Ditto. + (CODE_FOR_lasx_xvmod_b): Ditto. + (CODE_FOR_lasx_xvmod_h): Ditto. + (CODE_FOR_lasx_xvmod_w): Ditto. + (CODE_FOR_lasx_xvmod_d): Ditto. + (CODE_FOR_lasx_xvmod_bu): Ditto. + (CODE_FOR_lasx_xvmod_hu): Ditto. + (CODE_FOR_lasx_xvmod_wu): Ditto. + (CODE_FOR_lasx_xvmod_du): Ditto. + (CODE_FOR_lasx_xvmul_b): Ditto. + (CODE_FOR_lasx_xvmul_h): Ditto. + (CODE_FOR_lasx_xvmul_w): Ditto. + (CODE_FOR_lasx_xvmul_d): Ditto. + (CODE_FOR_lasx_xvclz_b): Ditto. + (CODE_FOR_lasx_xvclz_h): Ditto. + (CODE_FOR_lasx_xvclz_w): Ditto. + (CODE_FOR_lasx_xvclz_d): Ditto. + (CODE_FOR_lasx_xvnor_v): Ditto. + (CODE_FOR_lasx_xvor_v): Ditto. + (CODE_FOR_lasx_xvori_b): Ditto. + (CODE_FOR_lasx_xvnori_b): Ditto. + (CODE_FOR_lasx_xvpcnt_b): Ditto. + (CODE_FOR_lasx_xvpcnt_h): Ditto. + (CODE_FOR_lasx_xvpcnt_w): Ditto. + (CODE_FOR_lasx_xvpcnt_d): Ditto. + (CODE_FOR_lasx_xvxor_v): Ditto. + (CODE_FOR_lasx_xvxori_b): Ditto. + (CODE_FOR_lasx_xvsll_b): Ditto. + (CODE_FOR_lasx_xvsll_h): Ditto. + (CODE_FOR_lasx_xvsll_w): Ditto. + (CODE_FOR_lasx_xvsll_d): Ditto. + (CODE_FOR_lasx_xvslli_b): Ditto. + (CODE_FOR_lasx_xvslli_h): Ditto. + (CODE_FOR_lasx_xvslli_w): Ditto. + (CODE_FOR_lasx_xvslli_d): Ditto. + (CODE_FOR_lasx_xvsra_b): Ditto. + (CODE_FOR_lasx_xvsra_h): Ditto. + (CODE_FOR_lasx_xvsra_w): Ditto. + (CODE_FOR_lasx_xvsra_d): Ditto. + (CODE_FOR_lasx_xvsrai_b): Ditto. + (CODE_FOR_lasx_xvsrai_h): Ditto. + (CODE_FOR_lasx_xvsrai_w): Ditto. + (CODE_FOR_lasx_xvsrai_d): Ditto. + (CODE_FOR_lasx_xvsrl_b): Ditto. + (CODE_FOR_lasx_xvsrl_h): Ditto. + (CODE_FOR_lasx_xvsrl_w): Ditto. + (CODE_FOR_lasx_xvsrl_d): Ditto. + (CODE_FOR_lasx_xvsrli_b): Ditto. + (CODE_FOR_lasx_xvsrli_h): Ditto. + (CODE_FOR_lasx_xvsrli_w): Ditto. + (CODE_FOR_lasx_xvsrli_d): Ditto. + (CODE_FOR_lasx_xvsub_b): Ditto. + (CODE_FOR_lasx_xvsub_h): Ditto. + (CODE_FOR_lasx_xvsub_w): Ditto. + (CODE_FOR_lasx_xvsub_d): Ditto. + (CODE_FOR_lasx_xvsubi_bu): Ditto. + (CODE_FOR_lasx_xvsubi_hu): Ditto. + (CODE_FOR_lasx_xvsubi_wu): Ditto. + (CODE_FOR_lasx_xvsubi_du): Ditto. + (CODE_FOR_lasx_xvpackod_d): Ditto. + (CODE_FOR_lasx_xvpackev_d): Ditto. + (CODE_FOR_lasx_xvpickod_d): Ditto. + (CODE_FOR_lasx_xvpickev_d): Ditto. + (CODE_FOR_lasx_xvrepli_b): Ditto. + (CODE_FOR_lasx_xvrepli_h): Ditto. + (CODE_FOR_lasx_xvrepli_w): Ditto. + (CODE_FOR_lasx_xvrepli_d): Ditto. + (CODE_FOR_lasx_xvandn_v): Ditto. + (CODE_FOR_lasx_xvorn_v): Ditto. + (CODE_FOR_lasx_xvneg_b): Ditto. + (CODE_FOR_lasx_xvneg_h): Ditto. + (CODE_FOR_lasx_xvneg_w): Ditto. + (CODE_FOR_lasx_xvneg_d): Ditto. + (CODE_FOR_lasx_xvbsrl_v): Ditto. + (CODE_FOR_lasx_xvbsll_v): Ditto. + (CODE_FOR_lasx_xvfmadd_s): Ditto. + (CODE_FOR_lasx_xvfmadd_d): Ditto. + (CODE_FOR_lasx_xvfmsub_s): Ditto. + (CODE_FOR_lasx_xvfmsub_d): Ditto. + (CODE_FOR_lasx_xvfnmadd_s): Ditto. + (CODE_FOR_lasx_xvfnmadd_d): Ditto. + (CODE_FOR_lasx_xvfnmsub_s): Ditto.
View file
_service:tar_scm:LoongArch-Add-Loongson-SX-base-instruction-support.patch
Added
@@ -0,0 +1,8433 @@ +From 0b4626bb55886081e90922cf6d6869d551847a47 Mon Sep 17 00:00:00 2001 +From: Lulu Cheng <chenglulu@loongson.cn> +Date: Thu, 16 Mar 2023 16:29:42 +0800 +Subject: PATCH 063/124 LoongArch: Add Loongson SX base instruction support. + +gcc/ChangeLog: + + * config/loongarch/constraints.md (M): Add Loongson LSX base instruction support. + (N): Ditto. + (O): Ditto. + (P): Ditto. + (R): Ditto. + (S): Ditto. + (YG): Ditto. + (YA): Ditto. + (YB): Ditto. + (Yb): Ditto. + (Yh): Ditto. + (Yw): Ditto. + (YI): Ditto. + (YC): Ditto. + (YZ): Ditto. + (Unv5): Ditto. + (Uuv5): Ditto. + (Usv5): Ditto. + (Uuv6): Ditto. + (Urv8): Ditto. + * config/loongarch/genopts/loongarch.opt.in: Ditto. + * config/loongarch/loongarch-builtins.cc (loongarch_gen_const_int_vector): Ditto. + * config/loongarch/loongarch-modes.def (VECTOR_MODES): Ditto. + (VECTOR_MODE): Ditto. + (INT_MODE): Ditto. + * config/loongarch/loongarch-protos.h (loongarch_split_move_insn_p): Ditto. + (loongarch_split_move_insn): Ditto. + (loongarch_split_128bit_move): Ditto. + (loongarch_split_128bit_move_p): Ditto. + (loongarch_split_lsx_copy_d): Ditto. + (loongarch_split_lsx_insert_d): Ditto. + (loongarch_split_lsx_fill_d): Ditto. + (loongarch_expand_vec_cmp): Ditto. + (loongarch_const_vector_same_val_p): Ditto. + (loongarch_const_vector_same_bytes_p): Ditto. + (loongarch_const_vector_same_int_p): Ditto. + (loongarch_const_vector_shuffle_set_p): Ditto. + (loongarch_const_vector_bitimm_set_p): Ditto. + (loongarch_const_vector_bitimm_clr_p): Ditto. + (loongarch_lsx_vec_parallel_const_half): Ditto. + (loongarch_gen_const_int_vector): Ditto. + (loongarch_lsx_output_division): Ditto. + (loongarch_expand_vector_init): Ditto. + (loongarch_expand_vec_unpack): Ditto. + (loongarch_expand_vec_perm): Ditto. + (loongarch_expand_vector_extract): Ditto. + (loongarch_expand_vector_reduc): Ditto. + (loongarch_ldst_scaled_shift): Ditto. + (loongarch_expand_vec_cond_expr): Ditto. + (loongarch_expand_vec_cond_mask_expr): Ditto. + (loongarch_builtin_vectorized_function): Ditto. + (loongarch_gen_const_int_vector_shuffle): Ditto. + (loongarch_build_signbit_mask): Ditto. + * config/loongarch/loongarch.cc (loongarch_pass_aggregate_num_fpr): Ditto. + (loongarch_setup_incoming_varargs): Ditto. + (loongarch_emit_move): Ditto. + (loongarch_const_vector_bitimm_set_p): Ditto. + (loongarch_const_vector_bitimm_clr_p): Ditto. + (loongarch_const_vector_same_val_p): Ditto. + (loongarch_const_vector_same_bytes_p): Ditto. + (loongarch_const_vector_same_int_p): Ditto. + (loongarch_const_vector_shuffle_set_p): Ditto. + (loongarch_symbol_insns): Ditto. + (loongarch_cannot_force_const_mem): Ditto. + (loongarch_valid_offset_p): Ditto. + (loongarch_valid_index_p): Ditto. + (loongarch_classify_address): Ditto. + (loongarch_address_insns): Ditto. + (loongarch_ldst_scaled_shift): Ditto. + (loongarch_const_insns): Ditto. + (loongarch_split_move_insn_p): Ditto. + (loongarch_subword_at_byte): Ditto. + (loongarch_legitimize_move): Ditto. + (loongarch_builtin_vectorization_cost): Ditto. + (loongarch_split_move_p): Ditto. + (loongarch_split_move): Ditto. + (loongarch_split_move_insn): Ditto. + (loongarch_output_move_index_float): Ditto. + (loongarch_split_128bit_move_p): Ditto. + (loongarch_split_128bit_move): Ditto. + (loongarch_split_lsx_copy_d): Ditto. + (loongarch_split_lsx_insert_d): Ditto. + (loongarch_split_lsx_fill_d): Ditto. + (loongarch_output_move): Ditto. + (loongarch_extend_comparands): Ditto. + (loongarch_print_operand_reloc): Ditto. + (loongarch_print_operand): Ditto. + (loongarch_hard_regno_mode_ok_uncached): Ditto. + (loongarch_hard_regno_call_part_clobbered): Ditto. + (loongarch_hard_regno_nregs): Ditto. + (loongarch_class_max_nregs): Ditto. + (loongarch_can_change_mode_class): Ditto. + (loongarch_mode_ok_for_mov_fmt_p): Ditto. + (loongarch_secondary_reload): Ditto. + (loongarch_vector_mode_supported_p): Ditto. + (loongarch_preferred_simd_mode): Ditto. + (loongarch_autovectorize_vector_modes): Ditto. + (loongarch_lsx_output_division): Ditto. + (loongarch_option_override_internal): Ditto. + (loongarch_hard_regno_caller_save_mode): Ditto. + (MAX_VECT_LEN): Ditto. + (loongarch_spill_class): Ditto. + (struct expand_vec_perm_d): Ditto. + (loongarch_promote_function_mode): Ditto. + (loongarch_expand_vselect): Ditto. + (loongarch_starting_frame_offset): Ditto. + (loongarch_expand_vselect_vconcat): Ditto. + (TARGET_ASM_ALIGNED_DI_OP): Ditto. + (TARGET_OPTION_OVERRIDE): Ditto. + (TARGET_LEGITIMIZE_ADDRESS): Ditto. + (TARGET_ASM_SELECT_RTX_SECTION): Ditto. + (TARGET_ASM_FUNCTION_RODATA_SECTION): Ditto. + (loongarch_expand_lsx_shuffle): Ditto. + (TARGET_SCHED_INIT): Ditto. + (TARGET_SCHED_REORDER): Ditto. + (TARGET_SCHED_REORDER2): Ditto. + (TARGET_SCHED_VARIABLE_ISSUE): Ditto. + (TARGET_SCHED_ADJUST_COST): Ditto. + (TARGET_SCHED_ISSUE_RATE): Ditto. + (TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD): Ditto. + (TARGET_FUNCTION_OK_FOR_SIBCALL): Ditto. + (TARGET_VALID_POINTER_MODE): Ditto. + (TARGET_REGISTER_MOVE_COST): Ditto. + (TARGET_MEMORY_MOVE_COST): Ditto. + (TARGET_RTX_COSTS): Ditto. + (TARGET_ADDRESS_COST): Ditto. + (TARGET_IN_SMALL_DATA_P): Ditto. + (TARGET_PREFERRED_RELOAD_CLASS): Ditto. + (TARGET_ASM_FILE_START_FILE_DIRECTIVE): Ditto. + (TARGET_EXPAND_BUILTIN_VA_START): Ditto. + (loongarch_expand_vec_perm): Ditto. + (TARGET_PROMOTE_FUNCTION_MODE): Ditto. + (TARGET_RETURN_IN_MEMORY): Ditto. + (TARGET_FUNCTION_VALUE): Ditto. + (TARGET_LIBCALL_VALUE): Ditto. + (loongarch_try_expand_lsx_vshuf_const): Ditto. + (TARGET_ASM_OUTPUT_MI_THUNK): Ditto. + (TARGET_ASM_CAN_OUTPUT_MI_THUNK): Ditto. + (TARGET_PRINT_OPERAND): Ditto. + (TARGET_PRINT_OPERAND_ADDRESS): Ditto. + (TARGET_PRINT_OPERAND_PUNCT_VALID_P): Ditto. + (TARGET_SETUP_INCOMING_VARARGS): Ditto. + (TARGET_STRICT_ARGUMENT_NAMING): Ditto. + (TARGET_MUST_PASS_IN_STACK): Ditto. + (TARGET_PASS_BY_REFERENCE): Ditto. + (TARGET_ARG_PARTIAL_BYTES): Ditto. + (TARGET_FUNCTION_ARG): Ditto. + (TARGET_FUNCTION_ARG_ADVANCE): Ditto. + (TARGET_FUNCTION_ARG_BOUNDARY): Ditto. + (TARGET_SCALAR_MODE_SUPPORTED_P): Ditto. + (TARGET_INIT_BUILTINS): Ditto. + (loongarch_expand_vec_perm_const_1): Ditto. + (loongarch_expand_vec_perm_const_2): Ditto. + (loongarch_vectorize_vec_perm_const): Ditto. + (loongarch_cpu_sched_reassociation_width): Ditto. + (loongarch_sched_reassociation_width): Ditto. + (loongarch_expand_vector_extract): Ditto. + (emit_reduc_half): Ditto. + (loongarch_expand_vector_reduc): Ditto. + (loongarch_expand_vec_unpack): Ditto. + (loongarch_lsx_vec_parallel_const_half): Ditto. + (loongarch_constant_elt_p): Ditto. + (loongarch_gen_const_int_vector_shuffle): Ditto. + (loongarch_expand_vector_init): Ditto. + (loongarch_expand_lsx_cmp): Ditto. + (loongarch_expand_vec_cond_expr): Ditto. + (loongarch_expand_vec_cond_mask_expr): Ditto. + (loongarch_expand_vec_cmp): Ditto. + (loongarch_case_values_threshold): Ditto. + (loongarch_build_const_vector): Ditto. + (loongarch_build_signbit_mask): Ditto. + (loongarch_builtin_support_vector_misalignment): Ditto. + (TARGET_ASM_ALIGNED_HI_OP): Ditto. + (TARGET_ASM_ALIGNED_SI_OP): Ditto. + (TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST): Ditto. + (TARGET_VECTOR_MODE_SUPPORTED_P): Ditto. + (TARGET_VECTORIZE_PREFERRED_SIMD_MODE): Ditto. + (TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES): Ditto. + (TARGET_VECTORIZE_VEC_PERM_CONST): Ditto. + (TARGET_SCHED_REASSOCIATION_WIDTH): Ditto. + (TARGET_CASE_VALUES_THRESHOLD): Ditto. + (TARGET_HARD_REGNO_CALL_PART_CLOBBERED): Ditto. + (TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT): Ditto. + * config/loongarch/loongarch.h (TARGET_SUPPORTS_WIDE_INT): Ditto. + (UNITS_PER_LSX_REG): Ditto. + (BITS_PER_LSX_REG): Ditto. + (BIGGEST_ALIGNMENT): Ditto. + (LSX_REG_FIRST): Ditto. + (LSX_REG_LAST): Ditto. + (LSX_REG_NUM): Ditto. + (LSX_REG_P): Ditto. + (LSX_REG_RTX_P): Ditto.
View file
_service:tar_scm:LoongArch-Add-Loongson-SX-directive-builtin-function.patch
Added
@@ -0,0 +1,7549 @@ +From aafa5ab8c53dd2919d417b2f47e0c0e63ca7e10d Mon Sep 17 00:00:00 2001 +From: Lulu Cheng <chenglulu@loongson.cn> +Date: Thu, 16 Mar 2023 16:31:04 +0800 +Subject: PATCH 064/124 LoongArch: Add Loongson SX directive builtin function + support. + +gcc/ChangeLog: + + * config.gcc: Export the header file lsxintrin.h. + * config/loongarch/loongarch-builtins.cc (LARCH_FTYPE_NAME4): Add builtin function support. + (enum loongarch_builtin_type): Ditto. + (AVAIL_ALL): Ditto. + (LARCH_BUILTIN): Ditto. + (LSX_BUILTIN): Ditto. + (LSX_BUILTIN_TEST_BRANCH): Ditto. + (LSX_NO_TARGET_BUILTIN): Ditto. + (CODE_FOR_lsx_vsadd_b): Ditto. + (CODE_FOR_lsx_vsadd_h): Ditto. + (CODE_FOR_lsx_vsadd_w): Ditto. + (CODE_FOR_lsx_vsadd_d): Ditto. + (CODE_FOR_lsx_vsadd_bu): Ditto. + (CODE_FOR_lsx_vsadd_hu): Ditto. + (CODE_FOR_lsx_vsadd_wu): Ditto. + (CODE_FOR_lsx_vsadd_du): Ditto. + (CODE_FOR_lsx_vadd_b): Ditto. + (CODE_FOR_lsx_vadd_h): Ditto. + (CODE_FOR_lsx_vadd_w): Ditto. + (CODE_FOR_lsx_vadd_d): Ditto. + (CODE_FOR_lsx_vaddi_bu): Ditto. + (CODE_FOR_lsx_vaddi_hu): Ditto. + (CODE_FOR_lsx_vaddi_wu): Ditto. + (CODE_FOR_lsx_vaddi_du): Ditto. + (CODE_FOR_lsx_vand_v): Ditto. + (CODE_FOR_lsx_vandi_b): Ditto. + (CODE_FOR_lsx_bnz_v): Ditto. + (CODE_FOR_lsx_bz_v): Ditto. + (CODE_FOR_lsx_vbitsel_v): Ditto. + (CODE_FOR_lsx_vseqi_b): Ditto. + (CODE_FOR_lsx_vseqi_h): Ditto. + (CODE_FOR_lsx_vseqi_w): Ditto. + (CODE_FOR_lsx_vseqi_d): Ditto. + (CODE_FOR_lsx_vslti_b): Ditto. + (CODE_FOR_lsx_vslti_h): Ditto. + (CODE_FOR_lsx_vslti_w): Ditto. + (CODE_FOR_lsx_vslti_d): Ditto. + (CODE_FOR_lsx_vslti_bu): Ditto. + (CODE_FOR_lsx_vslti_hu): Ditto. + (CODE_FOR_lsx_vslti_wu): Ditto. + (CODE_FOR_lsx_vslti_du): Ditto. + (CODE_FOR_lsx_vslei_b): Ditto. + (CODE_FOR_lsx_vslei_h): Ditto. + (CODE_FOR_lsx_vslei_w): Ditto. + (CODE_FOR_lsx_vslei_d): Ditto. + (CODE_FOR_lsx_vslei_bu): Ditto. + (CODE_FOR_lsx_vslei_hu): Ditto. + (CODE_FOR_lsx_vslei_wu): Ditto. + (CODE_FOR_lsx_vslei_du): Ditto. + (CODE_FOR_lsx_vdiv_b): Ditto. + (CODE_FOR_lsx_vdiv_h): Ditto. + (CODE_FOR_lsx_vdiv_w): Ditto. + (CODE_FOR_lsx_vdiv_d): Ditto. + (CODE_FOR_lsx_vdiv_bu): Ditto. + (CODE_FOR_lsx_vdiv_hu): Ditto. + (CODE_FOR_lsx_vdiv_wu): Ditto. + (CODE_FOR_lsx_vdiv_du): Ditto. + (CODE_FOR_lsx_vfadd_s): Ditto. + (CODE_FOR_lsx_vfadd_d): Ditto. + (CODE_FOR_lsx_vftintrz_w_s): Ditto. + (CODE_FOR_lsx_vftintrz_l_d): Ditto. + (CODE_FOR_lsx_vftintrz_wu_s): Ditto. + (CODE_FOR_lsx_vftintrz_lu_d): Ditto. + (CODE_FOR_lsx_vffint_s_w): Ditto. + (CODE_FOR_lsx_vffint_d_l): Ditto. + (CODE_FOR_lsx_vffint_s_wu): Ditto. + (CODE_FOR_lsx_vffint_d_lu): Ditto. + (CODE_FOR_lsx_vfsub_s): Ditto. + (CODE_FOR_lsx_vfsub_d): Ditto. + (CODE_FOR_lsx_vfmul_s): Ditto. + (CODE_FOR_lsx_vfmul_d): Ditto. + (CODE_FOR_lsx_vfdiv_s): Ditto. + (CODE_FOR_lsx_vfdiv_d): Ditto. + (CODE_FOR_lsx_vfmax_s): Ditto. + (CODE_FOR_lsx_vfmax_d): Ditto. + (CODE_FOR_lsx_vfmin_s): Ditto. + (CODE_FOR_lsx_vfmin_d): Ditto. + (CODE_FOR_lsx_vfsqrt_s): Ditto. + (CODE_FOR_lsx_vfsqrt_d): Ditto. + (CODE_FOR_lsx_vflogb_s): Ditto. + (CODE_FOR_lsx_vflogb_d): Ditto. + (CODE_FOR_lsx_vmax_b): Ditto. + (CODE_FOR_lsx_vmax_h): Ditto. + (CODE_FOR_lsx_vmax_w): Ditto. + (CODE_FOR_lsx_vmax_d): Ditto. + (CODE_FOR_lsx_vmaxi_b): Ditto. + (CODE_FOR_lsx_vmaxi_h): Ditto. + (CODE_FOR_lsx_vmaxi_w): Ditto. + (CODE_FOR_lsx_vmaxi_d): Ditto. + (CODE_FOR_lsx_vmax_bu): Ditto. + (CODE_FOR_lsx_vmax_hu): Ditto. + (CODE_FOR_lsx_vmax_wu): Ditto. + (CODE_FOR_lsx_vmax_du): Ditto. + (CODE_FOR_lsx_vmaxi_bu): Ditto. + (CODE_FOR_lsx_vmaxi_hu): Ditto. + (CODE_FOR_lsx_vmaxi_wu): Ditto. + (CODE_FOR_lsx_vmaxi_du): Ditto. + (CODE_FOR_lsx_vmin_b): Ditto. + (CODE_FOR_lsx_vmin_h): Ditto. + (CODE_FOR_lsx_vmin_w): Ditto. + (CODE_FOR_lsx_vmin_d): Ditto. + (CODE_FOR_lsx_vmini_b): Ditto. + (CODE_FOR_lsx_vmini_h): Ditto. + (CODE_FOR_lsx_vmini_w): Ditto. + (CODE_FOR_lsx_vmini_d): Ditto. + (CODE_FOR_lsx_vmin_bu): Ditto. + (CODE_FOR_lsx_vmin_hu): Ditto. + (CODE_FOR_lsx_vmin_wu): Ditto. + (CODE_FOR_lsx_vmin_du): Ditto. + (CODE_FOR_lsx_vmini_bu): Ditto. + (CODE_FOR_lsx_vmini_hu): Ditto. + (CODE_FOR_lsx_vmini_wu): Ditto. + (CODE_FOR_lsx_vmini_du): Ditto. + (CODE_FOR_lsx_vmod_b): Ditto. + (CODE_FOR_lsx_vmod_h): Ditto. + (CODE_FOR_lsx_vmod_w): Ditto. + (CODE_FOR_lsx_vmod_d): Ditto. + (CODE_FOR_lsx_vmod_bu): Ditto. + (CODE_FOR_lsx_vmod_hu): Ditto. + (CODE_FOR_lsx_vmod_wu): Ditto. + (CODE_FOR_lsx_vmod_du): Ditto. + (CODE_FOR_lsx_vmul_b): Ditto. + (CODE_FOR_lsx_vmul_h): Ditto. + (CODE_FOR_lsx_vmul_w): Ditto. + (CODE_FOR_lsx_vmul_d): Ditto. + (CODE_FOR_lsx_vclz_b): Ditto. + (CODE_FOR_lsx_vclz_h): Ditto. + (CODE_FOR_lsx_vclz_w): Ditto. + (CODE_FOR_lsx_vclz_d): Ditto. + (CODE_FOR_lsx_vnor_v): Ditto. + (CODE_FOR_lsx_vor_v): Ditto. + (CODE_FOR_lsx_vori_b): Ditto. + (CODE_FOR_lsx_vnori_b): Ditto. + (CODE_FOR_lsx_vpcnt_b): Ditto. + (CODE_FOR_lsx_vpcnt_h): Ditto. + (CODE_FOR_lsx_vpcnt_w): Ditto. + (CODE_FOR_lsx_vpcnt_d): Ditto. + (CODE_FOR_lsx_vxor_v): Ditto. + (CODE_FOR_lsx_vxori_b): Ditto. + (CODE_FOR_lsx_vsll_b): Ditto. + (CODE_FOR_lsx_vsll_h): Ditto. + (CODE_FOR_lsx_vsll_w): Ditto. + (CODE_FOR_lsx_vsll_d): Ditto. + (CODE_FOR_lsx_vslli_b): Ditto. + (CODE_FOR_lsx_vslli_h): Ditto. + (CODE_FOR_lsx_vslli_w): Ditto. + (CODE_FOR_lsx_vslli_d): Ditto. + (CODE_FOR_lsx_vsra_b): Ditto. + (CODE_FOR_lsx_vsra_h): Ditto. + (CODE_FOR_lsx_vsra_w): Ditto. + (CODE_FOR_lsx_vsra_d): Ditto. + (CODE_FOR_lsx_vsrai_b): Ditto. + (CODE_FOR_lsx_vsrai_h): Ditto. + (CODE_FOR_lsx_vsrai_w): Ditto. + (CODE_FOR_lsx_vsrai_d): Ditto. + (CODE_FOR_lsx_vsrl_b): Ditto. + (CODE_FOR_lsx_vsrl_h): Ditto. + (CODE_FOR_lsx_vsrl_w): Ditto. + (CODE_FOR_lsx_vsrl_d): Ditto. + (CODE_FOR_lsx_vsrli_b): Ditto. + (CODE_FOR_lsx_vsrli_h): Ditto. + (CODE_FOR_lsx_vsrli_w): Ditto. + (CODE_FOR_lsx_vsrli_d): Ditto. + (CODE_FOR_lsx_vsub_b): Ditto. + (CODE_FOR_lsx_vsub_h): Ditto. + (CODE_FOR_lsx_vsub_w): Ditto. + (CODE_FOR_lsx_vsub_d): Ditto. + (CODE_FOR_lsx_vsubi_bu): Ditto. + (CODE_FOR_lsx_vsubi_hu): Ditto. + (CODE_FOR_lsx_vsubi_wu): Ditto. + (CODE_FOR_lsx_vsubi_du): Ditto. + (CODE_FOR_lsx_vpackod_d): Ditto. + (CODE_FOR_lsx_vpackev_d): Ditto. + (CODE_FOR_lsx_vpickod_d): Ditto. + (CODE_FOR_lsx_vpickev_d): Ditto. + (CODE_FOR_lsx_vrepli_b): Ditto. + (CODE_FOR_lsx_vrepli_h): Ditto. + (CODE_FOR_lsx_vrepli_w): Ditto. + (CODE_FOR_lsx_vrepli_d): Ditto. + (CODE_FOR_lsx_vsat_b): Ditto. + (CODE_FOR_lsx_vsat_h): Ditto. + (CODE_FOR_lsx_vsat_w): Ditto. + (CODE_FOR_lsx_vsat_d): Ditto. + (CODE_FOR_lsx_vsat_bu): Ditto. + (CODE_FOR_lsx_vsat_hu): Ditto. + (CODE_FOR_lsx_vsat_wu): Ditto. + (CODE_FOR_lsx_vsat_du): Ditto. + (CODE_FOR_lsx_vavg_b): Ditto. + (CODE_FOR_lsx_vavg_h): Ditto. + (CODE_FOR_lsx_vavg_w): Ditto. + (CODE_FOR_lsx_vavg_d): Ditto.
View file
_service:tar_scm:LoongArch-Add-built-in-functions-description-of-Loon.patch
Added
@@ -0,0 +1,166 @@ +From 7cfe6e057045ac794afbe9097b1b211c0e1ea723 Mon Sep 17 00:00:00 2001 +From: Lulu Cheng <chenglulu@loongson.cn> +Date: Thu, 6 Apr 2023 16:02:07 +0800 +Subject: PATCH 039/124 LoongArch: Add built-in functions description of + LoongArch Base instruction set instructions. + +gcc/ChangeLog: + + * doc/extend.texi: Add section for LoongArch Base Built-in functions. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/doc/extend.texi | 129 ++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 129 insertions(+) + +diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi +index 3c101ca89..1d1bac255 100644 +--- a/gcc/doc/extend.texi ++++ b/gcc/doc/extend.texi +@@ -14678,6 +14678,7 @@ instructions, but allow the compiler to schedule those calls. + * Blackfin Built-in Functions:: + * BPF Built-in Functions:: + * FR-V Built-in Functions:: ++* LoongArch Base Built-in Functions:: + * MIPS DSP Built-in Functions:: + * MIPS Paired-Single Support:: + * MIPS Loongson Built-in Functions:: +@@ -16128,6 +16129,134 @@ Use the @code{nldub} instruction to load the contents of address @var{x} + into the data cache. The instruction is issued in slot I1@. + @end table + ++@node LoongArch Base Built-in Functions ++@subsection LoongArch Base Built-in Functions ++ ++These built-in functions are available for LoongArch. ++ ++Data Type Description: ++@itemize ++@item @code{imm0_31}, a compile-time constant in range 0 to 31; ++@item @code{imm0_16383}, a compile-time constant in range 0 to 16383; ++@item @code{imm0_32767}, a compile-time constant in range 0 to 32767; ++@item @code{imm_n2048_2047}, a compile-time constant in range -2048 to 2047; ++@end itemize ++ ++The intrinsics provided are listed below: ++@smallexample ++ unsigned int __builtin_loongarch_movfcsr2gr (imm0_31) ++ void __builtin_loongarch_movgr2fcsr (imm0_31, unsigned int) ++ void __builtin_loongarch_cacop_d (imm0_31, unsigned long int, imm_n2048_2047) ++ unsigned int __builtin_loongarch_cpucfg (unsigned int) ++ void __builtin_loongarch_asrtle_d (long int, long int) ++ void __builtin_loongarch_asrtgt_d (long int, long int) ++ long int __builtin_loongarch_lddir_d (long int, imm0_31) ++ void __builtin_loongarch_ldpte_d (long int, imm0_31) ++ ++ int __builtin_loongarch_crc_w_b_w (char, int) ++ int __builtin_loongarch_crc_w_h_w (short, int) ++ int __builtin_loongarch_crc_w_w_w (int, int) ++ int __builtin_loongarch_crc_w_d_w (long int, int) ++ int __builtin_loongarch_crcc_w_b_w (char, int) ++ int __builtin_loongarch_crcc_w_h_w (short, int) ++ int __builtin_loongarch_crcc_w_w_w (int, int) ++ int __builtin_loongarch_crcc_w_d_w (long int, int) ++ ++ unsigned int __builtin_loongarch_csrrd_w (imm0_16383) ++ unsigned int __builtin_loongarch_csrwr_w (unsigned int, imm0_16383) ++ unsigned int __builtin_loongarch_csrxchg_w (unsigned int, unsigned int, imm0_16383) ++ unsigned long int __builtin_loongarch_csrrd_d (imm0_16383) ++ unsigned long int __builtin_loongarch_csrwr_d (unsigned long int, imm0_16383) ++ unsigned long int __builtin_loongarch_csrxchg_d (unsigned long int, unsigned long int, imm0_16383) ++ ++ unsigned char __builtin_loongarch_iocsrrd_b (unsigned int) ++ unsigned short __builtin_loongarch_iocsrrd_h (unsigned int) ++ unsigned int __builtin_loongarch_iocsrrd_w (unsigned int) ++ unsigned long int __builtin_loongarch_iocsrrd_d (unsigned int) ++ void __builtin_loongarch_iocsrwr_b (unsigned char, unsigned int) ++ void __builtin_loongarch_iocsrwr_h (unsigned short, unsigned int) ++ void __builtin_loongarch_iocsrwr_w (unsigned int, unsigned int) ++ void __builtin_loongarch_iocsrwr_d (unsigned long int, unsigned int) ++ ++ void __builtin_loongarch_dbar (imm0_32767) ++ void __builtin_loongarch_ibar (imm0_32767) ++ ++ void __builtin_loongarch_syscall (imm0_32767) ++ void __builtin_loongarch_break (imm0_32767) ++@end smallexample ++ ++@emph{Note:}Since the control register is divided into 32-bit and 64-bit, ++but the access instruction is not distinguished. So GCC renames the control ++instructions when implementing intrinsics. ++ ++Take the csrrd instruction as an example, built-in functions are implemented as follows: ++@smallexample ++ __builtin_loongarch_csrrd_w // When reading the 32-bit control register use. ++ __builtin_loongarch_csrrd_d // When reading the 64-bit control register use. ++@end smallexample ++ ++For the convenience of use, the built-in functions are encapsulated, ++the encapsulated functions and @code{__drdtime_t, __rdtime_t} are ++defined in the @code{larchintrin.h}. So if you call the following ++function you need to include @code{larchintrin.h}. ++ ++@smallexample ++ typedef struct drdtime@{ ++ unsigned long dvalue; ++ unsigned long dtimeid; ++ @} __drdtime_t; ++ ++ typedef struct rdtime@{ ++ unsigned int value; ++ unsigned int timeid; ++ @} __rdtime_t; ++@end smallexample ++ ++@smallexample ++ __drdtime_t __rdtime_d (void) ++ __rdtime_t __rdtimel_w (void) ++ __rdtime_t __rdtimeh_w (void) ++ unsigned int __movfcsr2gr (imm0_31) ++ void __movgr2fcsr (imm0_31, unsigned int) ++ void __cacop_d (imm0_31, unsigned long, imm_n2048_2047) ++ unsigned int __cpucfg (unsigned int) ++ void __asrtle_d (long int, long int) ++ void __asrtgt_d (long int, long int) ++ long int __lddir_d (long int, imm0_31) ++ void __ldpte_d (long int, imm0_31) ++ ++ int __crc_w_b_w (char, int) ++ int __crc_w_h_w (short, int) ++ int __crc_w_w_w (int, int) ++ int __crc_w_d_w (long int, int) ++ int __crcc_w_b_w (char, int) ++ int __crcc_w_h_w (short, int) ++ int __crcc_w_w_w (int, int) ++ int __crcc_w_d_w (long int, int) ++ ++ unsigned int __csrrd_w (imm0_16383) ++ unsigned int __csrwr_w (unsigned int, imm0_16383) ++ unsigned int __csrxchg_w (unsigned int, unsigned int, imm0_16383) ++ unsigned long __csrrd_d (imm0_16383) ++ unsigned long __csrwr_d (unsigned long, imm0_16383) ++ unsigned long __csrxchg_d (unsigned long, unsigned long, imm0_16383) ++ ++ unsigned char __iocsrrd_b (unsigned int) ++ unsigned short __iocsrrd_h (unsigned int) ++ unsigned int __iocsrrd_w (unsigned int) ++ unsigned long __iocsrrd_d (unsigned int) ++ void __iocsrwr_b (unsigned char, unsigned int) ++ void __iocsrwr_h (unsigned short, unsigned int) ++ void __iocsrwr_w (unsigned int, unsigned int) ++ void __iocsrwr_d (unsigned long, unsigned int) ++ ++ void __dbar (imm0_32767) ++ void __ibar (imm0_32767) ++ ++ void __syscall (imm0_32767) ++ void __break (imm0_32767) ++@end smallexample ++ + @node MIPS DSP Built-in Functions + @subsection MIPS DSP Built-in Functions + +-- +2.33.0 +
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_service:tar_scm:LoongArch-Add-fcopysign-instructions.patch
Added
@@ -0,0 +1,107 @@ +From 41a4945886631a1b2898ae957389d5db18a07141 Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao <xry111@xry111.site> +Date: Fri, 4 Nov 2022 15:12:22 +0800 +Subject: PATCH 025/124 LoongArch: Add fcopysign instructions + +Add fcopysign.{s,d} with the names copysign{sf,df}3 so GCC will expand +__builtin_copysign{f,} to a single instruction. + +Link: https://sourceware.org/pipermail/libc-alpha/2022-November/143177.html + +gcc/ChangeLog: + + * config/loongarch/loongarch.md (UNSPEC_FCOPYSIGN): New unspec. + (type): Add fcopysign. + (copysign<mode>3): New instruction template. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/fcopysign.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/loongarch.md | 22 ++++++++++++++++++- + .../gcc.target/loongarch/fcopysign.c | 16 ++++++++++++++ + 2 files changed, 37 insertions(+), 1 deletion(-) + create mode 100644 gcc/testsuite/gcc.target/loongarch/fcopysign.c + +diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md +index 214b14bdd..bda34d0f3 100644 +--- a/gcc/config/loongarch/loongarch.md ++++ b/gcc/config/loongarch/loongarch.md +@@ -37,6 +37,7 @@ + UNSPEC_FCLASS + UNSPEC_FMAX + UNSPEC_FMIN ++ UNSPEC_FCOPYSIGN + + ;; Override return address for exception handling. + UNSPEC_EH_RETURN +@@ -214,6 +215,7 @@ + ;; fabs floating point absolute value + ;; fneg floating point negation + ;; fcmp floating point compare ++;; fcopysign floating point copysign + ;; fcvt floating point convert + ;; fsqrt floating point square root + ;; frsqrt floating point reciprocal square root +@@ -226,7 +228,7 @@ + "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore, + prefetch,prefetchx,condmove,mgtf,mftg,const,arith,logical, + shift,slt,signext,clz,trap,imul,idiv,move, +- fmove,fadd,fmul,fmadd,fdiv,frdiv,fabs,fneg,fcmp,fcvt,fsqrt, ++ fmove,fadd,fmul,fmadd,fdiv,frdiv,fabs,fneg,fcmp,fcopysign,fcvt,fsqrt, + frsqrt,accext,accmod,multi,atomic,syncloop,nop,ghost" + (cond (eq_attr "jirl" "!unset") (const_string "call") + (eq_attr "got" "load") (const_string "load") +@@ -976,6 +978,24 @@ + (set_attr "mode" "<UNITMODE>")) +  + ;; ++;; .................... ++;; ++;; FLOATING POINT COPYSIGN ++;; ++;; .................... ++ ++(define_insn "copysign<mode>3" ++ (set (match_operand:ANYF 0 "register_operand" "=f") ++ (unspec:ANYF (match_operand:ANYF 1 "register_operand" "f") ++ (match_operand:ANYF 2 "register_operand" "f") ++ UNSPEC_FCOPYSIGN)) ++ "TARGET_HARD_FLOAT" ++ "fcopysign.<fmt>\t%0,%1,%2" ++ (set_attr "type" "fcopysign") ++ (set_attr "mode" "<UNITMODE>")) ++ ++ ++;; + ;; ................... + ;; + ;; Count leading zeroes. +diff --git a/gcc/testsuite/gcc.target/loongarch/fcopysign.c b/gcc/testsuite/gcc.target/loongarch/fcopysign.c +new file mode 100644 +index 000000000..058ba2cf5 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/fcopysign.c +@@ -0,0 +1,16 @@ ++/* { dg-do compile } */ ++/* { dg-options "-mdouble-float" } */ ++/* { dg-final { scan-assembler "fcopysign\\.s" } } */ ++/* { dg-final { scan-assembler "fcopysign\\.d" } } */ ++ ++double ++my_copysign (double a, double b) ++{ ++ return __builtin_copysign (a, b); ++} ++ ++float ++my_copysignf (float a, float b) ++{ ++ return __builtin_copysignf (a, b); ++} +-- +2.33.0 +
View file
_service:tar_scm:LoongArch-Add-flogb.-s-d-instructions-and-expand-log.patch
Added
@@ -0,0 +1,123 @@ +From 2ae587a86bba31b91a127e353c31c9f861ff5326 Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao <xry111@xry111.site> +Date: Tue, 8 Nov 2022 13:42:20 +0800 +Subject: PATCH 030/124 LoongArch: Add flogb.{s,d} instructions and expand + logb{sf,df}2 + +On LoongArch, flogb instructions extract the exponent of a non-negative +floating point value, but produces NaN for negative values. So we need +to add a fabs instruction when we expand logb. + +gcc/ChangeLog: + + * config/loongarch/loongarch.md (UNSPEC_FLOGB): New unspec. + (type): Add flogb. + (logb_non_negative<mode>2): New instruction template. + (logb<mode>2): New define_expand. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/flogb.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/loongarch.md | 35 ++++++++++++++++++++-- + gcc/testsuite/gcc.target/loongarch/flogb.c | 18 +++++++++++ + 2 files changed, 51 insertions(+), 2 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/loongarch/flogb.c + +diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md +index c141c9add..682ab9617 100644 +--- a/gcc/config/loongarch/loongarch.md ++++ b/gcc/config/loongarch/loongarch.md +@@ -42,6 +42,7 @@ + UNSPEC_FTINTRM + UNSPEC_FTINTRP + UNSPEC_FSCALEB ++ UNSPEC_FLOGB + + ;; Override return address for exception handling. + UNSPEC_EH_RETURN +@@ -217,6 +218,7 @@ + ;; fdiv floating point divide + ;; frdiv floating point reciprocal divide + ;; fabs floating point absolute value ++;; flogb floating point exponent extract + ;; fneg floating point negation + ;; fcmp floating point compare + ;; fcopysign floating point copysign +@@ -233,8 +235,8 @@ + "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore, + prefetch,prefetchx,condmove,mgtf,mftg,const,arith,logical, + shift,slt,signext,clz,trap,imul,idiv,move, +- fmove,fadd,fmul,fmadd,fdiv,frdiv,fabs,fneg,fcmp,fcopysign,fcvt,fscaleb, +- fsqrt,frsqrt,accext,accmod,multi,atomic,syncloop,nop,ghost" ++ fmove,fadd,fmul,fmadd,fdiv,frdiv,fabs,flogb,fneg,fcmp,fcopysign,fcvt, ++ fscaleb,fsqrt,frsqrt,accext,accmod,multi,atomic,syncloop,nop,ghost" + (cond (eq_attr "jirl" "!unset") (const_string "call") + (eq_attr "got" "load") (const_string "load") + +@@ -1039,6 +1041,35 @@ + (set_attr "mode" "<UNITMODE>")) +  + ;; ++;; .................... ++;; ++;; FLOATING POINT EXPONENT EXTRACT ++;; ++;; .................... ++ ++(define_insn "logb_non_negative<mode>2" ++ (set (match_operand:ANYF 0 "register_operand" "=f") ++ (unspec:ANYF (match_operand:ANYF 1 "register_operand" "f") ++ UNSPEC_FLOGB)) ++ "TARGET_HARD_FLOAT" ++ "flogb.<fmt>\t%0,%1" ++ (set_attr "type" "flogb") ++ (set_attr "mode" "<UNITMODE>")) ++ ++(define_expand "logb<mode>2" ++ (set (match_operand:ANYF 0 "register_operand") ++ (unspec:ANYF (abs:ANYF (match_operand:ANYF 1 "register_operand")) ++ UNSPEC_FLOGB)) ++ "TARGET_HARD_FLOAT" ++{ ++ rtx tmp = gen_reg_rtx (<MODE>mode); ++ ++ emit_insn (gen_abs<mode>2 (tmp, operands1)); ++ emit_insn (gen_logb_non_negative<mode>2 (operands0, tmp)); ++ DONE; ++}) ++ ++;; + ;; ................... + ;; + ;; Count leading zeroes. +diff --git a/gcc/testsuite/gcc.target/loongarch/flogb.c b/gcc/testsuite/gcc.target/loongarch/flogb.c +new file mode 100644 +index 000000000..1daefe54e +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/flogb.c +@@ -0,0 +1,18 @@ ++/* { dg-do compile } */ ++/* { dg-options "-mdouble-float -fno-math-errno" } */ ++/* { dg-final { scan-assembler "fabs\\.s" } } */ ++/* { dg-final { scan-assembler "fabs\\.d" } } */ ++/* { dg-final { scan-assembler "flogb\\.s" } } */ ++/* { dg-final { scan-assembler "flogb\\.d" } } */ ++ ++double ++my_logb (double a) ++{ ++ return __builtin_logb (a); ++} ++ ++float ++my_logbf (float a) ++{ ++ return __builtin_logbf (a); ++} +-- +2.33.0 +
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_service:tar_scm:LoongArch-Add-fscaleb.-s-d-instructions-as-ldexp-sf-.patch
Added
@@ -0,0 +1,155 @@ +From e3d69a3b7a4e00e8bba88b8b4abaa1c17bc083d5 Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao <xry111@xry111.site> +Date: Tue, 8 Nov 2022 12:14:35 +0800 +Subject: PATCH 029/124 LoongArch: Add fscaleb.{s,d} instructions as + ldexp{sf,df}3 + +This allows optimizing __builtin_ldexp{,f} and __builtin_scalbn{,f} with +-fno-math-errno. + +IMODE is added because we can't hard code SI for operand 2: fscaleb.d +instruction always take the high half of both source registers into +account. See my_ldexp_long in the test case. + +gcc/ChangeLog: + + * config/loongarch/loongarch.md (UNSPEC_FSCALEB): New unspec. + (type): Add fscaleb. + (IMODE): New mode attr. + (ldexp<mode>3): New instruction template. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/fscaleb.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/loongarch.md | 26 ++++++++++- + gcc/testsuite/gcc.target/loongarch/fscaleb.c | 48 ++++++++++++++++++++ + 2 files changed, 72 insertions(+), 2 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/loongarch/fscaleb.c + +diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md +index eb127c346..c141c9add 100644 +--- a/gcc/config/loongarch/loongarch.md ++++ b/gcc/config/loongarch/loongarch.md +@@ -41,6 +41,7 @@ + UNSPEC_FTINT + UNSPEC_FTINTRM + UNSPEC_FTINTRP ++ UNSPEC_FSCALEB + + ;; Override return address for exception handling. + UNSPEC_EH_RETURN +@@ -220,6 +221,7 @@ + ;; fcmp floating point compare + ;; fcopysign floating point copysign + ;; fcvt floating point convert ++;; fscaleb floating point scale + ;; fsqrt floating point square root + ;; frsqrt floating point reciprocal square root + ;; multi multiword sequence (or user asm statements) +@@ -231,8 +233,8 @@ + "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore, + prefetch,prefetchx,condmove,mgtf,mftg,const,arith,logical, + shift,slt,signext,clz,trap,imul,idiv,move, +- fmove,fadd,fmul,fmadd,fdiv,frdiv,fabs,fneg,fcmp,fcopysign,fcvt,fsqrt, +- frsqrt,accext,accmod,multi,atomic,syncloop,nop,ghost" ++ fmove,fadd,fmul,fmadd,fdiv,frdiv,fabs,fneg,fcmp,fcopysign,fcvt,fscaleb, ++ fsqrt,frsqrt,accext,accmod,multi,atomic,syncloop,nop,ghost" + (cond (eq_attr "jirl" "!unset") (const_string "call") + (eq_attr "got" "load") (const_string "load") + +@@ -418,6 +420,10 @@ + ;; the controlling mode. + (define_mode_attr HALFMODE (DF "SI") (DI "SI") (TF "DI")) + ++;; This attribute gives the integer mode that has the same size of a ++;; floating-point mode. ++(define_mode_attr IMODE (SF "SI") (DF "DI")) ++ + ;; This code iterator allows signed and unsigned widening multiplications + ;; to use the same template. + (define_code_iterator any_extend sign_extend zero_extend) +@@ -1014,7 +1020,23 @@ + "fcopysign.<fmt>\t%0,%1,%2" + (set_attr "type" "fcopysign") + (set_attr "mode" "<UNITMODE>")) ++ ++;; ++;; .................... ++;; ++;; FLOATING POINT SCALE ++;; ++;; .................... + ++(define_insn "ldexp<mode>3" ++ (set (match_operand:ANYF 0 "register_operand" "=f") ++ (unspec:ANYF (match_operand:ANYF 1 "register_operand" "f") ++ (match_operand:<IMODE> 2 "register_operand" "f") ++ UNSPEC_FSCALEB)) ++ "TARGET_HARD_FLOAT" ++ "fscaleb.<fmt>\t%0,%1,%2" ++ (set_attr "type" "fscaleb") ++ (set_attr "mode" "<UNITMODE>")) +  + ;; + ;; ................... +diff --git a/gcc/testsuite/gcc.target/loongarch/fscaleb.c b/gcc/testsuite/gcc.target/loongarch/fscaleb.c +new file mode 100644 +index 000000000..f18470fbb +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/fscaleb.c +@@ -0,0 +1,48 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -mabi=lp64d -mdouble-float -fno-math-errno" } */ ++/* { dg-final { scan-assembler-times "fscaleb\\.s" 3 } } */ ++/* { dg-final { scan-assembler-times "fscaleb\\.d" 4 } } */ ++/* { dg-final { scan-assembler-times "slli\\.w" 1 } } */ ++ ++double ++my_scalbln (double a, long b) ++{ ++ return __builtin_scalbln (a, b); ++} ++ ++double ++my_scalbn (double a, int b) ++{ ++ return __builtin_scalbn (a, b); ++} ++ ++double ++my_ldexp (double a, int b) ++{ ++ return __builtin_ldexp (a, b); ++} ++ ++float ++my_scalblnf (float a, long b) ++{ ++ return __builtin_scalblnf (a, b); ++} ++ ++float ++my_scalbnf (float a, int b) ++{ ++ return __builtin_scalbnf (a, b); ++} ++ ++float ++my_ldexpf (float a, int b) ++{ ++ return __builtin_ldexpf (a, b); ++} ++ ++/* b must be sign-extended */ ++double ++my_ldexp_long (double a, long b) ++{ ++ return __builtin_ldexp (a, b); ++} +-- +2.33.0 +
View file
_service:tar_scm:LoongArch-Add-ftint-rm-rp-.-w-l-.-s-d-instructions.patch
Added
@@ -0,0 +1,220 @@ +From 76d599c6d8f9cf78b51cd76a7ca8fbe11e2cda2b Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao <xry111@xry111.site> +Date: Sun, 6 Nov 2022 23:16:49 +0800 +Subject: PATCH 028/124 LoongArch: Add ftint{,rm,rp}.{w,l}.{s,d} instructions + +This allows to optimize the following builtins if -fno-math-errno: + +- __builtin_lrint{,f} +- __builtin_lfloor{,f} +- __builtin_lceil{,f} + +Inspired by +https://gcc.gnu.org/pipermail/gcc-patches/2022-November/605287.html. + +ANYFI is added so the compiler won't try ftint.l.s if -mfpu=32. If we +simply used GPR here an ICE would be triggered with __builtin_lrintf +and -mfpu=32. + +ftint{rm,rp} instructions may raise inexact exception, so they can't be +used if -fno-trapping-math -fno-fp-int-builtin-inexact. + +Note that the .w.{s,d} variants are not tested because we don't support +ILP32 for now. + +gcc/ChangeLog: + + * config/loongarch/loongarch.md (UNSPEC_FTINT): New unspec. + (UNSPEC_FTINTRM): Likewise. + (UNSPEC_FTINTRP): Likewise. + (LRINT): New define_int_iterator. + (lrint_pattern): New define_int_attr. + (lrint_submenmonic): Likewise. + (lrint_allow_inexact): Likewise. + (ANYFI): New define_mode_iterator. + (lrint<ANYF><ANYFI>): New instruction template. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/ftint.c: New test. + * gcc.target/loongarch/ftint-no-inexact.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/loongarch.md | 34 ++++++++++++++ + .../gcc.target/loongarch/ftint-no-inexact.c | 44 +++++++++++++++++++ + gcc/testsuite/gcc.target/loongarch/ftint.c | 44 +++++++++++++++++++ + 3 files changed, 122 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/ftint-no-inexact.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/ftint.c + +diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md +index a14ab14ac..eb127c346 100644 +--- a/gcc/config/loongarch/loongarch.md ++++ b/gcc/config/loongarch/loongarch.md +@@ -38,6 +38,9 @@ + UNSPEC_FMAX + UNSPEC_FMIN + UNSPEC_FCOPYSIGN ++ UNSPEC_FTINT ++ UNSPEC_FTINTRM ++ UNSPEC_FTINTRP + + ;; Override return address for exception handling. + UNSPEC_EH_RETURN +@@ -374,6 +377,11 @@ + (define_mode_iterator ANYF (SF "TARGET_HARD_FLOAT") + (DF "TARGET_DOUBLE_FLOAT")) + ++;; Iterator for fixed-point modes which can be hold by a hardware ++;; floating-point register. ++(define_mode_iterator ANYFI (SI "TARGET_HARD_FLOAT") ++ (DI "TARGET_DOUBLE_FLOAT")) ++ + ;; A mode for which moves involving FPRs may need to be split. + (define_mode_iterator SPLITF + (DF "!TARGET_64BIT && TARGET_DOUBLE_FLOAT") +@@ -515,6 +523,19 @@ + (define_code_attr sel (eq "masknez") (ne "maskeqz")) + (define_code_attr selinv (eq "maskeqz") (ne "masknez")) + ++;; Iterator and attributes for floating-point to fixed-point conversion ++;; instructions. ++(define_int_iterator LRINT UNSPEC_FTINT UNSPEC_FTINTRM UNSPEC_FTINTRP) ++(define_int_attr lrint_pattern (UNSPEC_FTINT "lrint") ++ (UNSPEC_FTINTRM "lfloor") ++ (UNSPEC_FTINTRP "lceil")) ++(define_int_attr lrint_submenmonic (UNSPEC_FTINT "") ++ (UNSPEC_FTINTRM "rm") ++ (UNSPEC_FTINTRP "rp")) ++(define_int_attr lrint_allow_inexact (UNSPEC_FTINT "1") ++ (UNSPEC_FTINTRM "0") ++ (UNSPEC_FTINTRP "0")) ++ + ;; + ;; .................... + ;; +@@ -2022,6 +2043,19 @@ + (set_attr "type" "fcvt") + (set_attr "mode" "<MODE>")) + ++;; Convert floating-point numbers to integers ++(define_insn "<lrint_pattern><ANYF:mode><ANYFI:mode>2" ++ (set (match_operand:ANYFI 0 "register_operand" "=f") ++ (unspec:ANYFI (match_operand:ANYF 1 "register_operand" "f") ++ LRINT)) ++ "TARGET_HARD_FLOAT && ++ (<lrint_allow_inexact> ++ || flag_fp_int_builtin_inexact ++ || !flag_trapping_math)" ++ "ftint<lrint_submenmonic>.<ANYFI:ifmt>.<ANYF:fmt> %0,%1" ++ (set_attr "type" "fcvt") ++ (set_attr "mode" "<ANYF:MODE>")) ++ + ;; Load the low word of operand 0 with operand 1. + (define_insn "load_low<mode>" + (set (match_operand:SPLITF 0 "register_operand" "=f,f") +diff --git a/gcc/testsuite/gcc.target/loongarch/ftint-no-inexact.c b/gcc/testsuite/gcc.target/loongarch/ftint-no-inexact.c +new file mode 100644 +index 000000000..88b83a9c0 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/ftint-no-inexact.c +@@ -0,0 +1,44 @@ ++/* { dg-do compile } */ ++/* { dg-options "-mabi=lp64d -mdouble-float -fno-math-errno -fno-fp-int-builtin-inexact" } */ ++/* { dg-final { scan-assembler "ftint\\.l\\.s" } } */ ++/* { dg-final { scan-assembler "ftint\\.l\\.d" } } */ ++/* { dg-final { scan-assembler-not "ftintrm\\.l\\.s" } } */ ++/* { dg-final { scan-assembler-not "ftintrm\\.l\\.d" } } */ ++/* { dg-final { scan-assembler-not "ftintrp\\.l\\.s" } } */ ++/* { dg-final { scan-assembler-not "ftintrp\\.l\\.d" } } */ ++ ++long ++my_lrint (double a) ++{ ++ return __builtin_lrint (a); ++} ++ ++long ++my_lrintf (float a) ++{ ++ return __builtin_lrintf (a); ++} ++ ++long ++my_lfloor (double a) ++{ ++ return __builtin_lfloor (a); ++} ++ ++long ++my_lfloorf (float a) ++{ ++ return __builtin_lfloorf (a); ++} ++ ++long ++my_lceil (double a) ++{ ++ return __builtin_lceil (a); ++} ++ ++long ++my_lceilf (float a) ++{ ++ return __builtin_lceilf (a); ++} +diff --git a/gcc/testsuite/gcc.target/loongarch/ftint.c b/gcc/testsuite/gcc.target/loongarch/ftint.c +new file mode 100644 +index 000000000..7a326a454 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/ftint.c +@@ -0,0 +1,44 @@ ++/* { dg-do compile } */ ++/* { dg-options "-mabi=lp64d -mdouble-float -fno-math-errno -ffp-int-builtin-inexact" } */ ++/* { dg-final { scan-assembler "ftint\\.l\\.s" } } */ ++/* { dg-final { scan-assembler "ftint\\.l\\.d" } } */ ++/* { dg-final { scan-assembler "ftintrm\\.l\\.s" } } */ ++/* { dg-final { scan-assembler "ftintrm\\.l\\.d" } } */ ++/* { dg-final { scan-assembler "ftintrp\\.l\\.s" } } */ ++/* { dg-final { scan-assembler "ftintrp\\.l\\.d" } } */ ++ ++long ++my_lrint (double a) ++{ ++ return __builtin_lrint (a); ++} ++ ++long ++my_lrintf (float a) ++{ ++ return __builtin_lrintf (a); ++} ++ ++long ++my_lfloor (double a) ++{ ++ return __builtin_lfloor (a); ++}
View file
_service:tar_scm:LoongArch-Add-new-code-model-medium.patch
Added
@@ -0,0 +1,1051 @@ +From 893322f214fbb916dc8eb6be5acbf7bdb7785e77 Mon Sep 17 00:00:00 2001 +From: Lulu Cheng <chenglulu@loongson.cn> +Date: Sat, 20 Aug 2022 15:19:51 +0800 +Subject: PATCH 012/124 LoongArch: Add new code model 'medium'. + +The function jump instruction in normal mode is 'bl', +so the scope of the function jump is +-128MB. + +Now we've added support for 'medium' mode, this mode is +to complete the function jump through two instructions: + pcalau12i + jirl +So in this mode the function jump range is increased to +-2GB. + +Compared with 'normal' mode, 'medium' mode only affects the +jump range of functions. + +gcc/ChangeLog: + + * config/loongarch/genopts/loongarch-strings: Support code model medium. + * config/loongarch/genopts/loongarch.opt.in: Likewise. + * config/loongarch/loongarch-def.c: Likewise. + * config/loongarch/loongarch-def.h (CMODEL_LARGE): Likewise. + (CMODEL_EXTREME): Likewise. + (N_CMODEL_TYPES): Likewise. + (CMODEL_MEDIUM): Likewise. + * config/loongarch/loongarch-opts.cc: Likewise. + * config/loongarch/loongarch-opts.h (TARGET_CMODEL_MEDIUM): Likewise. + * config/loongarch/loongarch-str.h (STR_CMODEL_MEDIUM): Likewise. + * config/loongarch/loongarch.cc (loongarch_call_tls_get_addr): + Tls symbol Loading support medium mode. + (loongarch_legitimize_call_address): When medium mode, make a symbolic + jump with two instructions. + (loongarch_option_override_internal): Support medium. + * config/loongarch/loongarch.md (@pcalau12i<mode>): New template. + (@sibcall_internal_1<mode>): New function call templates added to support + medium mode. + (@sibcall_value_internal_1<mode>): Likewise. + (@sibcall_value_multiple_internal_1<mode>): Likewise. + (@call_internal_1<mode>): Likewise. + (@call_value_internal_1<mode>): Likewise. + (@call_value_multiple_internal_1<mode>): Likewise. + * config/loongarch/loongarch.opt: Support medium. + * config/loongarch/predicates.md: Add processing about medium mode. + * doc/invoke.texi: Document for '-mcmodel=medium'. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/func-call-medium-1.c: New test. + * gcc.target/loongarch/func-call-medium-2.c: New test. + * gcc.target/loongarch/func-call-medium-3.c: New test. + * gcc.target/loongarch/func-call-medium-4.c: New test. + * gcc.target/loongarch/func-call-medium-5.c: New test. + * gcc.target/loongarch/func-call-medium-6.c: New test. + * gcc.target/loongarch/func-call-medium-7.c: New test. + * gcc.target/loongarch/func-call-medium-8.c: New test. + * gcc.target/loongarch/tls-gd-noplt.c: Add compile parameter '-mexplicit-relocs'. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/genopts/loongarch-strings | 1 + + gcc/config/loongarch/genopts/loongarch.opt.in | 3 + + gcc/config/loongarch/loongarch-def.c | 1 + + gcc/config/loongarch/loongarch-def.h | 7 +- + gcc/config/loongarch/loongarch-opts.cc | 15 ++- + gcc/config/loongarch/loongarch-opts.h | 1 + + gcc/config/loongarch/loongarch-str.h | 1 + + gcc/config/loongarch/loongarch.cc | 123 +++++++++++++---- + gcc/config/loongarch/loongarch.md | 125 +++++++++++++++++- + gcc/config/loongarch/loongarch.opt | 3 + + gcc/config/loongarch/predicates.md | 15 ++- + gcc/doc/invoke.texi | 3 + + .../gcc.target/loongarch/func-call-medium-1.c | 41 ++++++ + .../gcc.target/loongarch/func-call-medium-2.c | 41 ++++++ + .../gcc.target/loongarch/func-call-medium-3.c | 41 ++++++ + .../gcc.target/loongarch/func-call-medium-4.c | 41 ++++++ + .../gcc.target/loongarch/func-call-medium-5.c | 42 ++++++ + .../gcc.target/loongarch/func-call-medium-6.c | 42 ++++++ + .../gcc.target/loongarch/func-call-medium-7.c | 43 ++++++ + .../gcc.target/loongarch/func-call-medium-8.c | 42 ++++++ + .../gcc.target/loongarch/tls-gd-noplt.c | 4 +- + 21 files changed, 595 insertions(+), 40 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/loongarch/func-call-medium-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/func-call-medium-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/func-call-medium-3.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/func-call-medium-4.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/func-call-medium-5.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/func-call-medium-6.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/func-call-medium-7.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/func-call-medium-8.c + +diff --git a/gcc/config/loongarch/genopts/loongarch-strings b/gcc/config/loongarch/genopts/loongarch-strings +index cb88ed56b..44ebb7ab1 100644 +--- a/gcc/config/loongarch/genopts/loongarch-strings ++++ b/gcc/config/loongarch/genopts/loongarch-strings +@@ -54,5 +54,6 @@ OPTSTR_CMODEL cmodel + STR_CMODEL_NORMAL normal + STR_CMODEL_TINY tiny + STR_CMODEL_TS tiny-static ++STR_CMODEL_MEDIUM medium + STR_CMODEL_LARGE large + STR_CMODEL_EXTREME extreme +diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in b/gcc/config/loongarch/genopts/loongarch.opt.in +index a571b6b75..ebdd9538d 100644 +--- a/gcc/config/loongarch/genopts/loongarch.opt.in ++++ b/gcc/config/loongarch/genopts/loongarch.opt.in +@@ -172,6 +172,9 @@ Enum(cmodel) String(@@STR_CMODEL_TINY@@) Value(CMODEL_TINY) + EnumValue + Enum(cmodel) String(@@STR_CMODEL_TS@@) Value(CMODEL_TINY_STATIC) + ++EnumValue ++Enum(cmodel) String(@@STR_CMODEL_MEDIUM@@) Value(CMODEL_MEDIUM) ++ + EnumValue + Enum(cmodel) String(@@STR_CMODEL_LARGE@@) Value(CMODEL_LARGE) + +diff --git a/gcc/config/loongarch/loongarch-def.c b/gcc/config/loongarch/loongarch-def.c +index c8769b7d6..cbf995d81 100644 +--- a/gcc/config/loongarch/loongarch-def.c ++++ b/gcc/config/loongarch/loongarch-def.c +@@ -152,6 +152,7 @@ loongarch_cmodel_strings = { + CMODEL_NORMAL = STR_CMODEL_NORMAL, + CMODEL_TINY = STR_CMODEL_TINY, + CMODEL_TINY_STATIC = STR_CMODEL_TS, ++ CMODEL_MEDIUM = STR_CMODEL_MEDIUM, + CMODEL_LARGE = STR_CMODEL_LARGE, + CMODEL_EXTREME = STR_CMODEL_EXTREME, + }; +diff --git a/gcc/config/loongarch/loongarch-def.h b/gcc/config/loongarch/loongarch-def.h +index c2c35b6ba..b5985f070 100644 +--- a/gcc/config/loongarch/loongarch-def.h ++++ b/gcc/config/loongarch/loongarch-def.h +@@ -82,9 +82,10 @@ extern const char* loongarch_cmodel_strings; + #define CMODEL_NORMAL 0 + #define CMODEL_TINY 1 + #define CMODEL_TINY_STATIC 2 +-#define CMODEL_LARGE 3 +-#define CMODEL_EXTREME 4 +-#define N_CMODEL_TYPES 5 ++#define CMODEL_MEDIUM 3 ++#define CMODEL_LARGE 4 ++#define CMODEL_EXTREME 5 ++#define N_CMODEL_TYPES 6 + + /* enum switches */ + /* The "SW_" codes represent command-line switches (options that +diff --git a/gcc/config/loongarch/loongarch-opts.cc b/gcc/config/loongarch/loongarch-opts.cc +index 2ae89f234..e13eafb58 100644 +--- a/gcc/config/loongarch/loongarch-opts.cc ++++ b/gcc/config/loongarch/loongarch-opts.cc +@@ -376,11 +376,24 @@ fallback: + + /* 5. Target code model */ + t.cmodel = constrained.cmodel ? opt_cmodel : CMODEL_NORMAL; +- if (t.cmodel != CMODEL_NORMAL && t.cmodel != CMODEL_EXTREME) ++ ++ switch (t.cmodel) + { ++ case CMODEL_TINY: ++ case CMODEL_TINY_STATIC: ++ case CMODEL_LARGE: + warning (0, "%qs is not supported, now cmodel is set to %qs", + loongarch_cmodel_stringst.cmodel, "normal"); + t.cmodel = CMODEL_NORMAL; ++ break; ++ ++ case CMODEL_NORMAL: ++ case CMODEL_MEDIUM: ++ case CMODEL_EXTREME: ++ break; ++ ++ default: ++ gcc_unreachable (); + } + + /* Cleanup and return. */ +diff --git a/gcc/config/loongarch/loongarch-opts.h b/gcc/config/loongarch/loongarch-opts.h +index da24ecd2b..3523a4cf7 100644 +--- a/gcc/config/loongarch/loongarch-opts.h ++++ b/gcc/config/loongarch/loongarch-opts.h +@@ -46,6 +46,7 @@ loongarch_config_target (struct loongarch_target *target, + #define TARGET_CMODEL_NORMAL (la_target.cmodel == CMODEL_NORMAL) + #define TARGET_CMODEL_TINY (la_target.cmodel == CMODEL_TINY) + #define TARGET_CMODEL_TINY_STATIC (la_target.cmodel == CMODEL_TINY_STATIC) ++#define TARGET_CMODEL_MEDIUM (la_target.cmodel == CMODEL_MEDIUM) + #define TARGET_CMODEL_LARGE (la_target.cmodel == CMODEL_LARGE) + #define TARGET_CMODEL_EXTREME (la_target.cmodel == CMODEL_EXTREME) + +diff --git a/gcc/config/loongarch/loongarch-str.h b/gcc/config/loongarch/loongarch-str.h +index 0e8889b8c..9f1b0989c 100644 +--- a/gcc/config/loongarch/loongarch-str.h ++++ b/gcc/config/loongarch/loongarch-str.h +@@ -53,6 +53,7 @@ along with GCC; see the file COPYING3. If not see + #define STR_CMODEL_NORMAL "normal" + #define STR_CMODEL_TINY "tiny" + #define STR_CMODEL_TS "tiny-static" ++#define STR_CMODEL_MEDIUM "medium" + #define STR_CMODEL_LARGE "large" + #define STR_CMODEL_EXTREME "extreme"
View file
_service:tar_scm:LoongArch-Add-prefetch-instructions.patch
Added
@@ -0,0 +1,158 @@ +From 52a41006c2e8141a42de93ffcc2c040e034244b2 Mon Sep 17 00:00:00 2001 +From: Lulu Cheng <chenglulu@loongson.cn> +Date: Wed, 16 Nov 2022 09:25:14 +0800 +Subject: PATCH 031/124 LoongArch: Add prefetch instructions. + +Enable sw prefetching at -O3 and higher. + +Co-Authored-By: xujiahao <xujiahao@loongson.cn> + +gcc/ChangeLog: + + * config/loongarch/constraints.md (ZD): New constraint. + * config/loongarch/loongarch-def.c: Initial number of parallel prefetch. + * config/loongarch/loongarch-tune.h (struct loongarch_cache): + Define number of parallel prefetch. + * config/loongarch/loongarch.cc (loongarch_option_override_internal): + Set up parameters to be used in prefetching algorithm. + * config/loongarch/loongarch.md (prefetch): New template. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/constraints.md | 10 ++++++++++ + gcc/config/loongarch/loongarch-def.c | 2 ++ + gcc/config/loongarch/loongarch-tune.h | 1 + + gcc/config/loongarch/loongarch.cc | 28 +++++++++++++++++++++++++++ + gcc/config/loongarch/loongarch.md | 14 ++++++++++++++ + 5 files changed, 55 insertions(+) + +diff --git a/gcc/config/loongarch/constraints.md b/gcc/config/loongarch/constraints.md +index 43cb7b5f0..46f7f63ae 100644 +--- a/gcc/config/loongarch/constraints.md ++++ b/gcc/config/loongarch/constraints.md +@@ -86,6 +86,10 @@ + ;; "ZB" + ;; "An address that is held in a general-purpose register. + ;; The offset is zero" ++;; "ZD" ++;; "An address operand whose address is formed by a base register ++;; and offset that is suitable for use in instructions with the same ++;; addressing mode as @code{preld}." + ;; "<" "Matches a pre-dec or post-dec operand." (Global non-architectural) + ;; ">" "Matches a pre-inc or post-inc operand." (Global non-architectural) + +@@ -190,3 +194,9 @@ + The offset is zero" + (and (match_code "mem") + (match_test "REG_P (XEXP (op, 0))"))) ++ ++(define_address_constraint "ZD" ++ "An address operand whose address is formed by a base register ++ and offset that is suitable for use in instructions with the same ++ addressing mode as @code{preld}." ++ (match_test "loongarch_12bit_offset_address_p (op, mode)")) +diff --git a/gcc/config/loongarch/loongarch-def.c b/gcc/config/loongarch/loongarch-def.c +index cbf995d81..80ab10a52 100644 +--- a/gcc/config/loongarch/loongarch-def.c ++++ b/gcc/config/loongarch/loongarch-def.c +@@ -62,11 +62,13 @@ loongarch_cpu_cacheN_TUNE_TYPES = { + .l1d_line_size = 64, + .l1d_size = 64, + .l2d_size = 256, ++ .simultaneous_prefetches = 4, + }, + CPU_LA464 = { + .l1d_line_size = 64, + .l1d_size = 64, + .l2d_size = 256, ++ .simultaneous_prefetches = 4, + }, + }; + +diff --git a/gcc/config/loongarch/loongarch-tune.h b/gcc/config/loongarch/loongarch-tune.h +index 6f3530f5c..8e3eb2947 100644 +--- a/gcc/config/loongarch/loongarch-tune.h ++++ b/gcc/config/loongarch/loongarch-tune.h +@@ -45,6 +45,7 @@ struct loongarch_cache { + int l1d_line_size; /* bytes */ + int l1d_size; /* KiB */ + int l2d_size; /* kiB */ ++ int simultaneous_prefetches; /* number of parallel prefetch */ + }; + + #endif /* LOONGARCH_TUNE_H */ +diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc +index d552b162a..622c9435b 100644 +--- a/gcc/config/loongarch/loongarch.cc ++++ b/gcc/config/loongarch/loongarch.cc +@@ -63,6 +63,7 @@ along with GCC; see the file COPYING3. If not see + #include "context.h" + #include "builtins.h" + #include "rtl-iter.h" ++#include "opts.h" + + /* This file should be included last. */ + #include "target-def.h" +@@ -6099,6 +6100,33 @@ loongarch_option_override_internal (struct gcc_options *opts) + if (loongarch_branch_cost == 0) + loongarch_branch_cost = loongarch_cost->branch_cost; + ++ /* Set up parameters to be used in prefetching algorithm. */ ++ int simultaneous_prefetches ++ = loongarch_cpu_cacheLARCH_ACTUAL_TUNE.simultaneous_prefetches; ++ ++ SET_OPTION_IF_UNSET (opts, &global_options_set, ++ param_simultaneous_prefetches, ++ simultaneous_prefetches); ++ ++ SET_OPTION_IF_UNSET (opts, &global_options_set, ++ param_l1_cache_line_size, ++ loongarch_cpu_cacheLARCH_ACTUAL_TUNE.l1d_line_size); ++ ++ SET_OPTION_IF_UNSET (opts, &global_options_set, ++ param_l1_cache_size, ++ loongarch_cpu_cacheLARCH_ACTUAL_TUNE.l1d_size); ++ ++ SET_OPTION_IF_UNSET (opts, &global_options_set, ++ param_l2_cache_size, ++ loongarch_cpu_cacheLARCH_ACTUAL_TUNE.l2d_size); ++ ++ ++ /* Enable sw prefetching at -O3 and higher. */ ++ if (opts->x_flag_prefetch_loop_arrays < 0 ++ && (opts->x_optimize >= 3 || opts->x_flag_profile_use) ++ && !opts->x_optimize_size) ++ opts->x_flag_prefetch_loop_arrays = 1; ++ + if (TARGET_DIRECT_EXTERN_ACCESS && flag_shlib) + error ("%qs cannot be used for compiling a shared library", + "-mdirect-extern-access"); +diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md +index 682ab9617..2fda53819 100644 +--- a/gcc/config/loongarch/loongarch.md ++++ b/gcc/config/loongarch/loongarch.md +@@ -3282,6 +3282,20 @@ + ;; .................... + ;; + ++(define_insn "prefetch" ++ (prefetch (match_operand 0 "address_operand" "ZD") ++ (match_operand 1 "const_int_operand" "n") ++ (match_operand 2 "const_int_operand" "n")) ++ "" ++{ ++ switch (INTVAL (operands1)) ++ { ++ case 0: return "preld\t0,%a0"; ++ case 1: return "preld\t8,%a0"; ++ default: gcc_unreachable (); ++ } ++}) ++ + (define_insn "nop" + (const_int 0) + "" +-- +2.33.0 +
View file
_service:tar_scm:LoongArch-Add-support-code-model-extreme.patch
Added
@@ -0,0 +1,794 @@ +From b1c92fb9dab678e4c9c23fa77185011494d145b9 Mon Sep 17 00:00:00 2001 +From: Lulu Cheng <chenglulu@loongson.cn> +Date: Thu, 18 Aug 2022 17:26:13 +0800 +Subject: PATCH 011/124 LoongArch: Add support code model extreme. + +Use five instructions to calculate a signed 64-bit offset relative to the pc. + +gcc/ChangeLog: + + * config/loongarch/loongarch-opts.cc: Allow cmodel to be extreme. + * config/loongarch/loongarch.cc (loongarch_call_tls_get_addr): + Add extreme support for TLS GD and LD types. + (loongarch_legitimize_tls_address): Add extreme support for TLS LE + and IE. + (loongarch_split_symbol): When compiling with -mcmodel=extreme, + the symbol address will be obtained through five instructions. + (loongarch_print_operand_reloc): Add support. + (loongarch_print_operand): Add support. + (loongarch_print_operand_address): Add support. + (loongarch_option_override_internal): Set '-mcmodel=extreme' option + incompatible with '-mno-explicit-relocs'. + * config/loongarch/loongarch.md (@lui_l_hi20<mode>): + Loads bits 12-31 of data into registers. + (lui_h_lo20): Load bits 32-51 of the data and spell bits 0-31 of + the source register. + (lui_h_hi12): Load bits 52-63 of the data and spell bits 0-51 of + the source register. + * config/loongarch/predicates.md: Symbols need to be decomposed + when defining the macro TARGET_CMODEL_EXTREME + * doc/invoke.texi: Modify the description information of cmodel in the document. + Document -Wno-extreme-plt. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/func-call-1.c: Add option '-mcmodel=normal'. + * gcc.target/loongarch/func-call-2.c: Likewise. + * gcc.target/loongarch/func-call-3.c: Likewise. + * gcc.target/loongarch/func-call-4.c: Likewise. + * gcc.target/loongarch/func-call-5.c: Likewise. + * gcc.target/loongarch/func-call-6.c: Likewise. + * gcc.target/loongarch/func-call-7.c: Likewise. + * gcc.target/loongarch/func-call-8.c: Likewise. + * gcc.target/loongarch/relocs-symbol-noaddend.c: Likewise. + * gcc.target/loongarch/func-call-extreme-1.c: New test. + * gcc.target/loongarch/func-call-extreme-2.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/loongarch-opts.cc | 3 +- + gcc/config/loongarch/loongarch.cc | 222 +++++++++++++++--- + gcc/config/loongarch/loongarch.md | 34 ++- + gcc/config/loongarch/predicates.md | 9 +- + gcc/doc/invoke.texi | 50 +--- + .../gcc.target/loongarch/func-call-1.c | 2 +- + .../gcc.target/loongarch/func-call-2.c | 2 +- + .../gcc.target/loongarch/func-call-3.c | 2 +- + .../gcc.target/loongarch/func-call-4.c | 2 +- + .../gcc.target/loongarch/func-call-5.c | 2 +- + .../gcc.target/loongarch/func-call-6.c | 2 +- + .../gcc.target/loongarch/func-call-7.c | 2 +- + .../gcc.target/loongarch/func-call-8.c | 2 +- + .../loongarch/func-call-extreme-1.c | 32 +++ + .../loongarch/func-call-extreme-2.c | 32 +++ + .../loongarch/relocs-symbol-noaddend.c | 2 +- + 16 files changed, 318 insertions(+), 82 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/loongarch/func-call-extreme-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/func-call-extreme-2.c + +diff --git a/gcc/config/loongarch/loongarch-opts.cc b/gcc/config/loongarch/loongarch-opts.cc +index 3f70943de..2ae89f234 100644 +--- a/gcc/config/loongarch/loongarch-opts.cc ++++ b/gcc/config/loongarch/loongarch-opts.cc +@@ -376,14 +376,13 @@ fallback: + + /* 5. Target code model */ + t.cmodel = constrained.cmodel ? opt_cmodel : CMODEL_NORMAL; +- if (t.cmodel != CMODEL_NORMAL) ++ if (t.cmodel != CMODEL_NORMAL && t.cmodel != CMODEL_EXTREME) + { + warning (0, "%qs is not supported, now cmodel is set to %qs", + loongarch_cmodel_stringst.cmodel, "normal"); + t.cmodel = CMODEL_NORMAL; + } + +- + /* Cleanup and return. */ + obstack_free (&msg_obstack, NULL); + *target = t; +diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc +index 76bf55ea4..1a33f668f 100644 +--- a/gcc/config/loongarch/loongarch.cc ++++ b/gcc/config/loongarch/loongarch.cc +@@ -2436,7 +2436,19 @@ loongarch_call_tls_get_addr (rtx sym, enum loongarch_symbol_type type, rtx v0) + /* Split tls symbol to high and low. */ + rtx high = gen_rtx_HIGH (Pmode, copy_rtx (loc)); + high = loongarch_force_temporary (tmp, high); +- emit_insn (gen_tls_low (Pmode, a0, high, loc)); ++ ++ if (TARGET_CMODEL_EXTREME) ++ { ++ gcc_assert (TARGET_EXPLICIT_RELOCS); ++ ++ rtx tmp1 = gen_reg_rtx (Pmode); ++ emit_insn (gen_tls_low (Pmode, tmp1, gen_rtx_REG (Pmode, 0), loc)); ++ emit_insn (gen_lui_h_lo20 (tmp1, tmp1, loc)); ++ emit_insn (gen_lui_h_hi12 (tmp1, tmp1, loc)); ++ emit_move_insn (a0, gen_rtx_PLUS (Pmode, high, tmp1)); ++ } ++ else ++ emit_insn (gen_tls_low (Pmode, a0, high, loc)); + } + else + { +@@ -2449,14 +2461,44 @@ loongarch_call_tls_get_addr (rtx sym, enum loongarch_symbol_type type, rtx v0) + } + + if (flag_plt) +- insn = emit_call_insn (gen_call_value_internal (v0, loongarch_tls_symbol, ++ insn = emit_call_insn (gen_call_value_internal (v0, ++ loongarch_tls_symbol, + const0_rtx)); + else + { + rtx dest = gen_reg_rtx (Pmode); +- rtx high = gen_reg_rtx (Pmode); +- loongarch_emit_move (high, gen_rtx_HIGH (Pmode, loongarch_tls_symbol)); +- emit_insn (gen_ld_from_got (Pmode, dest, high, loongarch_tls_symbol)); ++ ++ if (TARGET_CMODEL_EXTREME) ++ { ++ gcc_assert (TARGET_EXPLICIT_RELOCS); ++ ++ rtx tmp1 = gen_reg_rtx (Pmode); ++ rtx high = gen_reg_rtx (Pmode); ++ ++ loongarch_emit_move (high, ++ gen_rtx_HIGH (Pmode, loongarch_tls_symbol)); ++ loongarch_emit_move (tmp1, gen_rtx_LO_SUM (Pmode, ++ gen_rtx_REG (Pmode, 0), ++ loongarch_tls_symbol)); ++ emit_insn (gen_lui_h_lo20 (tmp1, tmp1, loongarch_tls_symbol)); ++ emit_insn (gen_lui_h_hi12 (tmp1, tmp1, loongarch_tls_symbol)); ++ loongarch_emit_move (dest, ++ gen_rtx_MEM (Pmode, ++ gen_rtx_PLUS (Pmode, high, tmp1))); ++ } ++ else ++ { ++ if (TARGET_EXPLICIT_RELOCS) ++ { ++ rtx high = gen_reg_rtx (Pmode); ++ loongarch_emit_move (high, ++ gen_rtx_HIGH (Pmode, loongarch_tls_symbol)); ++ emit_insn (gen_ld_from_got (Pmode, dest, high, ++ loongarch_tls_symbol)); ++ } ++ else ++ loongarch_emit_move (dest, loongarch_tls_symbol); ++ } + insn = emit_call_insn (gen_call_value_internal (v0, dest, const0_rtx)); + } + +@@ -2508,7 +2550,23 @@ loongarch_legitimize_tls_address (rtx loc) + tmp3 = gen_reg_rtx (Pmode); + rtx high = gen_rtx_HIGH (Pmode, copy_rtx (tmp2)); + high = loongarch_force_temporary (tmp3, high); +- emit_insn (gen_ld_from_got (Pmode, tmp1, high, tmp2)); ++ ++ if (TARGET_CMODEL_EXTREME) ++ { ++ gcc_assert (TARGET_EXPLICIT_RELOCS); ++ ++ rtx tmp3 = gen_reg_rtx (Pmode); ++ emit_insn (gen_tls_low (Pmode, tmp3, ++ gen_rtx_REG (Pmode, 0), tmp2)); ++ emit_insn (gen_lui_h_lo20 (tmp3, tmp3, tmp2)); ++ emit_insn (gen_lui_h_hi12 (tmp3, tmp3, tmp2)); ++ emit_move_insn (tmp1, ++ gen_rtx_MEM (Pmode, ++ gen_rtx_PLUS (Pmode, ++ high, tmp3))); ++ } ++ else ++ emit_insn (gen_ld_from_got (Pmode, tmp1, high, tmp2)); + } + else + emit_insn (loongarch_got_load_tls_ie (tmp1, loc)); +@@ -2530,11 +2588,18 @@ loongarch_legitimize_tls_address (rtx loc) + rtx high = gen_rtx_HIGH (Pmode, copy_rtx (tmp2)); + high = loongarch_force_temporary (tmp3, high); + emit_insn (gen_ori_l_lo12 (Pmode, tmp1, high, tmp2)); ++ ++ if (TARGET_CMODEL_EXTREME) ++ { ++ gcc_assert (TARGET_EXPLICIT_RELOCS); ++ ++ emit_insn (gen_lui_h_lo20 (tmp1, tmp1, tmp2)); ++ emit_insn (gen_lui_h_hi12 (tmp1, tmp1, tmp2));
View file
_service:tar_scm:LoongArch-Add-tests-for-ASX-builtin-functions.patch
Added
@@ -0,0 +1,4485 @@ +From fcf63744c4ceaa60cd57ab3c431ec63f690189d4 Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Tue, 12 Sep 2023 15:59:47 +0800 +Subject: PATCH 109/124 LoongArch: Add tests for ASX builtin functions. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/vector/lasx/lasx-builtin.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/vector/lasx/lasx-builtin.c | 4460 +++++++++++++++++ + 1 file changed, 4460 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-builtin.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-builtin.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-builtin.c +new file mode 100644 +index 000000000..b1a903b4a +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-builtin.c +@@ -0,0 +1,4460 @@ ++/* Test builtins for LOONGARCH LASX ASE instructions */ ++/* { dg-do compile } */ ++/* { dg-options "-mlasx" } */ ++/* { dg-final { scan-assembler-times "lasx_xvsll_b:.*xvsll\\.b.*lasx_xvsll_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsll_h:.*xvsll\\.h.*lasx_xvsll_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsll_w:.*xvsll\\.w.*lasx_xvsll_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsll_d:.*xvsll\\.d.*lasx_xvsll_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvslli_b:.*xvslli\\.b.*lasx_xvslli_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvslli_h:.*xvslli\\.h.*lasx_xvslli_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvslli_w:.*xvslli\\.w.*lasx_xvslli_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvslli_d:.*xvslli\\.d.*lasx_xvslli_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsra_b:.*xvsra\\.b.*lasx_xvsra_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsra_h:.*xvsra\\.h.*lasx_xvsra_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsra_w:.*xvsra\\.w.*lasx_xvsra_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsra_d:.*xvsra\\.d.*lasx_xvsra_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsrai_b:.*xvsrai\\.b.*lasx_xvsrai_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsrai_h:.*xvsrai\\.h.*lasx_xvsrai_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsrai_w:.*xvsrai\\.w.*lasx_xvsrai_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsrai_d:.*xvsrai\\.d.*lasx_xvsrai_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsrar_b:.*xvsrar\\.b.*lasx_xvsrar_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsrar_h:.*xvsrar\\.h.*lasx_xvsrar_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsrar_w:.*xvsrar\\.w.*lasx_xvsrar_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsrar_d:.*xvsrar\\.d.*lasx_xvsrar_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsrari_b:.*xvsrari\\.b.*lasx_xvsrari_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsrari_h:.*xvsrari\\.h.*lasx_xvsrari_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsrari_w:.*xvsrari\\.w.*lasx_xvsrari_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsrari_d:.*xvsrari\\.d.*lasx_xvsrari_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsrl_b:.*xvsrl\\.b.*lasx_xvsrl_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsrl_h:.*xvsrl\\.h.*lasx_xvsrl_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsrl_w:.*xvsrl\\.w.*lasx_xvsrl_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsrl_d:.*xvsrl\\.d.*lasx_xvsrl_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsrli_b:.*xvsrli\\.b.*lasx_xvsrli_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsrli_h:.*xvsrli\\.h.*lasx_xvsrli_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsrli_w:.*xvsrli\\.w.*lasx_xvsrli_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsrli_d:.*xvsrli\\.d.*lasx_xvsrli_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsrlr_b:.*xvsrlr\\.b.*lasx_xvsrlr_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsrlr_h:.*xvsrlr\\.h.*lasx_xvsrlr_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsrlr_w:.*xvsrlr\\.w.*lasx_xvsrlr_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsrlr_d:.*xvsrlr\\.d.*lasx_xvsrlr_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsrlri_b:.*xvsrlri\\.b.*lasx_xvsrlri_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsrlri_h:.*xvsrlri\\.h.*lasx_xvsrlri_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsrlri_w:.*xvsrlri\\.w.*lasx_xvsrlri_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsrlri_d:.*xvsrlri\\.d.*lasx_xvsrlri_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvbitclr_b:.*xvbitclr\\.b.*lasx_xvbitclr_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvbitclr_h:.*xvbitclr\\.h.*lasx_xvbitclr_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvbitclr_w:.*xvbitclr\\.w.*lasx_xvbitclr_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvbitclr_d:.*xvbitclr\\.d.*lasx_xvbitclr_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvbitclri_b:.*xvbitclri\\.b.*lasx_xvbitclri_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvbitclri_h:.*xvbitclri\\.h.*lasx_xvbitclri_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvbitclri_w:.*xvbitclri\\.w.*lasx_xvbitclri_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvbitclri_d:.*xvbitclri\\.d.*lasx_xvbitclri_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvbitset_b:.*xvbitset\\.b.*lasx_xvbitset_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvbitset_h:.*xvbitset\\.h.*lasx_xvbitset_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvbitset_w:.*xvbitset\\.w.*lasx_xvbitset_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvbitset_d:.*xvbitset\\.d.*lasx_xvbitset_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvbitseti_b:.*xvbitseti\\.b.*lasx_xvbitseti_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvbitseti_h:.*xvbitseti\\.h.*lasx_xvbitseti_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvbitseti_w:.*xvbitseti\\.w.*lasx_xvbitseti_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvbitseti_d:.*xvbitseti\\.d.*lasx_xvbitseti_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvbitrev_b:.*xvbitrev\\.b.*lasx_xvbitrev_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvbitrev_h:.*xvbitrev\\.h.*lasx_xvbitrev_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvbitrev_w:.*xvbitrev\\.w.*lasx_xvbitrev_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvbitrev_d:.*xvbitrev\\.d.*lasx_xvbitrev_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvbitrevi_b:.*xvbitrevi\\.b.*lasx_xvbitrevi_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvbitrevi_h:.*xvbitrevi\\.h.*lasx_xvbitrevi_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvbitrevi_w:.*xvbitrevi\\.w.*lasx_xvbitrevi_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvbitrevi_d:.*xvbitrevi\\.d.*lasx_xvbitrevi_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvadd_b:.*xvadd\\.b.*lasx_xvadd_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvadd_h:.*xvadd\\.h.*lasx_xvadd_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvadd_w:.*xvadd\\.w.*lasx_xvadd_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvadd_d:.*xvadd\\.d.*lasx_xvadd_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvaddi_bu:.*xvaddi\\.bu.*lasx_xvaddi_bu" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvaddi_hu:.*xvaddi\\.hu.*lasx_xvaddi_hu" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvaddi_wu:.*xvaddi\\.wu.*lasx_xvaddi_wu" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvaddi_du:.*xvaddi\\.du.*lasx_xvaddi_du" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsub_b:.*xvsub\\.b.*lasx_xvsub_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsub_h:.*xvsub\\.h.*lasx_xvsub_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsub_w:.*xvsub\\.w.*lasx_xvsub_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsub_d:.*xvsub\\.d.*lasx_xvsub_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsubi_bu:.*xvsubi\\.bu.*lasx_xvsubi_bu" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsubi_hu:.*xvsubi\\.hu.*lasx_xvsubi_hu" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsubi_wu:.*xvsubi\\.wu.*lasx_xvsubi_wu" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsubi_du:.*xvsubi\\.du.*lasx_xvsubi_du" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvmax_b:.*xvmax\\.b.*lasx_xvmax_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvmax_h:.*xvmax\\.h.*lasx_xvmax_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvmax_w:.*xvmax\\.w.*lasx_xvmax_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvmax_d:.*xvmax\\.d.*lasx_xvmax_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvmaxi_b:.*xvmaxi\\.b.*lasx_xvmaxi_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvmaxi_h:.*xvmaxi\\.h.*lasx_xvmaxi_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvmaxi_w:.*xvmaxi\\.w.*lasx_xvmaxi_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvmaxi_d:.*xvmaxi\\.d.*lasx_xvmaxi_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvmax_bu:.*xvmax\\.bu.*lasx_xvmax_bu" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvmax_hu:.*xvmax\\.hu.*lasx_xvmax_hu" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvmax_wu:.*xvmax\\.wu.*lasx_xvmax_wu" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvmax_du:.*xvmax\\.du.*lasx_xvmax_du" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvmaxi_bu:.*xvmaxi\\.bu.*lasx_xvmaxi_bu" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvmaxi_hu:.*xvmaxi\\.hu.*lasx_xvmaxi_hu" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvmaxi_wu:.*xvmaxi\\.wu.*lasx_xvmaxi_wu" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvmaxi_du:.*xvmaxi\\.du.*lasx_xvmaxi_du" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvmin_b:.*xvmin\\.b.*lasx_xvmin_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvmin_h:.*xvmin\\.h.*lasx_xvmin_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvmin_w:.*xvmin\\.w.*lasx_xvmin_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvmin_d:.*xvmin\\.d.*lasx_xvmin_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvmini_b:.*xvmini\\.b.*lasx_xvmini_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvmini_h:.*xvmini\\.h.*lasx_xvmini_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvmini_w:.*xvmini\\.w.*lasx_xvmini_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvmini_d:.*xvmini\\.d.*lasx_xvmini_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvmin_bu:.*xvmin\\.bu.*lasx_xvmin_bu" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvmin_hu:.*xvmin\\.hu.*lasx_xvmin_hu" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvmin_wu:.*xvmin\\.wu.*lasx_xvmin_wu" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvmin_du:.*xvmin\\.du.*lasx_xvmin_du" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvmini_bu:.*xvmini\\.bu.*lasx_xvmini_bu" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvmini_hu:.*xvmini\\.hu.*lasx_xvmini_hu" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvmini_wu:.*xvmini\\.wu.*lasx_xvmini_wu" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvmini_du:.*xvmini\\.du.*lasx_xvmini_du" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvseq_b:.*xvseq\\.b.*lasx_xvseq_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvseq_h:.*xvseq\\.h.*lasx_xvseq_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvseq_w:.*xvseq\\.w.*lasx_xvseq_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvseq_d:.*xvseq\\.d.*lasx_xvseq_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvseqi_b:.*xvseqi\\.b.*lasx_xvseqi_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvseqi_h:.*xvseqi\\.h.*lasx_xvseqi_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvseqi_w:.*xvseqi\\.w.*lasx_xvseqi_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvseqi_d:.*xvseqi\\.d.*lasx_xvseqi_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvslt_b:.*xvslt\\.b.*lasx_xvslt_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvslt_h:.*xvslt\\.h.*lasx_xvslt_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvslt_w:.*xvslt\\.w.*lasx_xvslt_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvslt_d:.*xvslt\\.d.*lasx_xvslt_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvslti_b:.*xvslti\\.b.*lasx_xvslti_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvslti_h:.*xvslti\\.h.*lasx_xvslti_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvslti_w:.*xvslti\\.w.*lasx_xvslti_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvslti_d:.*xvslti\\.d.*lasx_xvslti_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvslt_bu:.*xvslt\\.bu.*lasx_xvslt_bu" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvslt_hu:.*xvslt\\.hu.*lasx_xvslt_hu" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvslt_wu:.*xvslt\\.wu.*lasx_xvslt_wu" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvslt_du:.*xvslt\\.du.*lasx_xvslt_du" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvslti_bu:.*xvslti\\.bu.*lasx_xvslti_bu" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvslti_hu:.*xvslti\\.hu.*lasx_xvslti_hu" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvslti_wu:.*xvslti\\.wu.*lasx_xvslti_wu" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvslti_du:.*xvslti\\.du.*lasx_xvslti_du" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsle_b:.*xvsle\\.b.*lasx_xvsle_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsle_h:.*xvsle\\.h.*lasx_xvsle_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsle_w:.*xvsle\\.w.*lasx_xvsle_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsle_d:.*xvsle\\.d.*lasx_xvsle_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvslei_b:.*xvslei\\.b.*lasx_xvslei_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvslei_h:.*xvslei\\.h.*lasx_xvslei_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvslei_w:.*xvslei\\.w.*lasx_xvslei_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvslei_d:.*xvslei\\.d.*lasx_xvslei_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsle_bu:.*xvsle\\.bu.*lasx_xvsle_bu" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsle_hu:.*xvsle\\.hu.*lasx_xvsle_hu" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsle_wu:.*xvsle\\.wu.*lasx_xvsle_wu" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsle_du:.*xvsle\\.du.*lasx_xvsle_du" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvslei_bu:.*xvslei\\.bu.*lasx_xvslei_bu" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvslei_hu:.*xvslei\\.hu.*lasx_xvslei_hu" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvslei_wu:.*xvslei\\.wu.*lasx_xvslei_wu" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvslei_du:.*xvslei\\.du.*lasx_xvslei_du" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsat_b:.*xvsat\\.b.*lasx_xvsat_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsat_h:.*xvsat\\.h.*lasx_xvsat_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsat_w:.*xvsat\\.w.*lasx_xvsat_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsat_d:.*xvsat\\.d.*lasx_xvsat_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsat_bu:.*xvsat\\.bu.*lasx_xvsat_bu" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsat_hu:.*xvsat\\.hu.*lasx_xvsat_hu" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsat_wu:.*xvsat\\.wu.*lasx_xvsat_wu" 1 } } */ ++/* { dg-final { scan-assembler-times "lasx_xvsat_du:.*xvsat\\.du.*lasx_xvsat_du" 1 } } */
View file
_service:tar_scm:LoongArch-Add-tests-for-ASX-vector-comparison-and-se.patch
Added
@@ -0,0 +1,5363 @@ +From 9ccb5fcabdf69160eb360da7eab06a207f59334c Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Tue, 12 Sep 2023 16:11:04 +0800 +Subject: PATCH 113/124 LoongArch: Add tests for ASX vector comparison and + selection instruction. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/vector/lasx/lasx-xvseq.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvseqi.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvsle-1.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvsle-2.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvslei-1.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvslei-2.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvslt-1.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvslt-2.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvslti-1.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvslti-2.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/vector/lasx/lasx-xvseq.c | 650 ++++++++++++++++++ + .../loongarch/vector/lasx/lasx-xvseqi.c | 449 ++++++++++++ + .../loongarch/vector/lasx/lasx-xvsle-1.c | 575 ++++++++++++++++ + .../loongarch/vector/lasx/lasx-xvsle-2.c | 590 ++++++++++++++++ + .../loongarch/vector/lasx/lasx-xvslei-1.c | 515 ++++++++++++++ + .../loongarch/vector/lasx/lasx-xvslei-2.c | 438 ++++++++++++ + .../loongarch/vector/lasx/lasx-xvslt-1.c | 455 ++++++++++++ + .../loongarch/vector/lasx/lasx-xvslt-2.c | 620 +++++++++++++++++ + .../loongarch/vector/lasx/lasx-xvslti-1.c | 548 +++++++++++++++ + .../loongarch/vector/lasx/lasx-xvslti-2.c | 416 +++++++++++ + 10 files changed, 5256 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvseq.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvseqi.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvsle-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvsle-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvslei-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvslei-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvslt-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvslt-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvslti-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvslti-2.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvseq.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvseq.c +new file mode 100644 +index 000000000..2a42386ce +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvseq.c +@@ -0,0 +1,650 @@ ++/* { dg-do run } */ ++/* { dg-options "-mlasx -w -fno-strict-aliasing" } */ ++#include "../simd_correctness_check.h" ++#include <lasxintrin.h> ++ ++int ++main () ++{ ++ __m256i __m256i_op0, __m256i_op1, __m256i_op2, __m256i_out, __m256i_result; ++ __m256 __m256_op0, __m256_op1, __m256_op2, __m256_out, __m256_result; ++ __m256d __m256d_op0, __m256d_op1, __m256d_op2, __m256d_out, __m256d_result; ++ ++ int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail; ++ long int long_op0, long_op1, long_op2, lont_out, lont_result; ++ long int long_int_out, long_int_result; ++ unsigned int unsigned_int_out, unsigned_int_result; ++ unsigned long int unsigned_long_int_out, unsigned_long_int_result; ++ ++ *((unsigned long *)&__m256i_op03) = 0xfffe000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000ffff00010000; ++ *((unsigned long *)&__m256i_op01) = 0x0001000100020001; ++ *((unsigned long *)&__m256i_op00) = 0x0000fffffffffffe; ++ *((unsigned long *)&__m256i_op13) = 0xffff000000010000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000095120000; ++ *((unsigned long *)&__m256i_op11) = 0xc9da000063f50000; ++ *((unsigned long *)&__m256i_op10) = 0xc7387fff6bbfffff; ++ *((unsigned long *)&__m256i_result3) = 0x0000ffff0000ffff; ++ *((unsigned long *)&__m256i_result2) = 0xffff00000000ffff; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvseq_h (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x7f0000007f000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x7f0000007f000000; ++ *((unsigned long *)&__m256i_op13) = 0x1555156a1555156a; ++ *((unsigned long *)&__m256i_op12) = 0x1555156a1555156a; ++ *((unsigned long *)&__m256i_op11) = 0x1555156a1555156a; ++ *((unsigned long *)&__m256i_op10) = 0x1555156a1555156a; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvseq_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x6100000800060005; ++ *((unsigned long *)&__m256i_op02) = 0x5ee1c073b800c916; ++ *((unsigned long *)&__m256i_op01) = 0x7ff0000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x5ff00007fff9fff3; ++ *((unsigned long *)&__m256i_op13) = 0x000000000000ffff; ++ *((unsigned long *)&__m256i_op12) = 0x0209fefb08140000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0003fffc00060000; ++ *((unsigned long *)&__m256i_result3) = 0x00ffff00ff000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000ffffffffffff; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvseq_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x00000000ffffffff; ++ *((unsigned long *)&__m256i_op02) = 0x00000000fffffefd; ++ *((unsigned long *)&__m256i_op01) = 0x00000000ffffffff; ++ *((unsigned long *)&__m256i_op00) = 0x00000000fffffefd; ++ *((unsigned long *)&__m256i_op13) = 0x0101010101010101; ++ *((unsigned long *)&__m256i_op12) = 0xfffffffffffffefd; ++ *((unsigned long *)&__m256i_op11) = 0x0101010101010101; ++ *((unsigned long *)&__m256i_op10) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvseq_d (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000080000000800; ++ *((unsigned long *)&__m256i_op02) = 0xfffcf800fffcf800; ++ *((unsigned long *)&__m256i_op01) = 0x0000080000000800; ++ *((unsigned long *)&__m256i_op00) = 0x0000080000000800; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvseq_w (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x00000000ffffffff; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0xffffff00fffffff0; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x00000000ffffffff; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0xffffff00fffffff0; ++ *((unsigned long *)&__m256i_result3) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_result2) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_result1) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_result0) = 0xffffffffffffffff; ++ __m256i_out = __lasx_xvseq_h (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_result2) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_result1) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_result0) = 0xffffffffffffffff; ++ __m256i_out = __lasx_xvseq_w (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000001; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000001; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000001; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000001; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvseq_d (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op02) = 0xfffffefefffffefe; ++ *((unsigned long *)&__m256i_op01) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op00) = 0xfffffefe00000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000;
View file
_service:tar_scm:LoongArch-Add-tests-for-ASX-vector-floating-point-co.patch
Added
@@ -0,0 +1,7291 @@ +From 5a014f35ac194402adc08945480da44e2c0a772a Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Tue, 12 Sep 2023 16:06:04 +0800 +Subject: PATCH 112/124 LoongArch: Add tests for ASX vector floating-point + conversion instruction. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/vector/lasx/lasx-xvfcvt.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvfcvth.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvffint-1.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvffint-2.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvffinth.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvfrint_d.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvfrint_s.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvftint-1.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvftint-2.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvftint-3.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvftintl.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/vector/lasx/lasx-xvfcvt.c | 528 ++++++ + .../loongarch/vector/lasx/lasx-xvfcvth.c | 485 +++++ + .../loongarch/vector/lasx/lasx-xvffint-1.c | 375 ++++ + .../loongarch/vector/lasx/lasx-xvffint-2.c | 246 +++ + .../loongarch/vector/lasx/lasx-xvffinth.c | 262 +++ + .../loongarch/vector/lasx/lasx-xvfrint_d.c | 429 +++++ + .../loongarch/vector/lasx/lasx-xvfrint_s.c | 723 ++++++++ + .../loongarch/vector/lasx/lasx-xvftint-1.c | 471 +++++ + .../loongarch/vector/lasx/lasx-xvftint-2.c | 1565 ++++++++++++++++ + .../loongarch/vector/lasx/lasx-xvftint-3.c | 511 ++++++ + .../loongarch/vector/lasx/lasx-xvftintl.c | 1580 +++++++++++++++++ + 11 files changed, 7175 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfcvt.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfcvth.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvffint-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvffint-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvffinth.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfrint_d.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfrint_s.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvftint-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvftint-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvftint-3.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvftintl.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfcvt.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfcvt.c +new file mode 100644 +index 000000000..116399a7c +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfcvt.c +@@ -0,0 +1,528 @@ ++/* { dg-do run } */ ++/* { dg-options "-mlasx -w -fno-strict-aliasing" } */ ++#include "../simd_correctness_check.h" ++#include <lasxintrin.h> ++ ++int ++main () ++{ ++ __m256i __m256i_op0, __m256i_op1, __m256i_op2, __m256i_out, __m256i_result; ++ __m256 __m256_op0, __m256_op1, __m256_op2, __m256_out, __m256_result; ++ __m256d __m256d_op0, __m256d_op1, __m256d_op2, __m256d_out, __m256d_result; ++ ++ int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail; ++ long int long_op0, long_op1, long_op2, lont_out, lont_result; ++ long int long_int_out, long_int_result; ++ unsigned int unsigned_int_out, unsigned_int_result; ++ unsigned long int unsigned_long_int_out, unsigned_long_int_result; ++ ++ *((int *)&__m256_op07) = 0x00000000; ++ *((int *)&__m256_op06) = 0x00000000; ++ *((int *)&__m256_op05) = 0x00000000; ++ *((int *)&__m256_op04) = 0x00000000; ++ *((int *)&__m256_op03) = 0x00000000; ++ *((int *)&__m256_op02) = 0x00000000; ++ *((int *)&__m256_op01) = 0x00000000; ++ *((int *)&__m256_op00) = 0x00000000; ++ *((int *)&__m256_op17) = 0x00000000; ++ *((int *)&__m256_op16) = 0x00000000; ++ *((int *)&__m256_op15) = 0x00000000; ++ *((int *)&__m256_op14) = 0x00000000; ++ *((int *)&__m256_op13) = 0x00000000; ++ *((int *)&__m256_op12) = 0x00000000; ++ *((int *)&__m256_op11) = 0x00000000; ++ *((int *)&__m256_op10) = 0x00000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvfcvt_h_s (__m256_op0, __m256_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((int *)&__m256_op07) = 0x00000000; ++ *((int *)&__m256_op06) = 0x00000000; ++ *((int *)&__m256_op05) = 0x00000000; ++ *((int *)&__m256_op04) = 0x00000000; ++ *((int *)&__m256_op03) = 0x00000000; ++ *((int *)&__m256_op02) = 0x00000000; ++ *((int *)&__m256_op01) = 0x00000000; ++ *((int *)&__m256_op00) = 0x00000000; ++ *((int *)&__m256_op17) = 0x00000000; ++ *((int *)&__m256_op16) = 0x00000000; ++ *((int *)&__m256_op15) = 0x00000000; ++ *((int *)&__m256_op14) = 0x00000000; ++ *((int *)&__m256_op13) = 0x00000000; ++ *((int *)&__m256_op12) = 0x00000000; ++ *((int *)&__m256_op11) = 0x00000000; ++ *((int *)&__m256_op10) = 0x00000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvfcvt_h_s (__m256_op0, __m256_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((int *)&__m256_op07) = 0x00000000; ++ *((int *)&__m256_op06) = 0x00000000; ++ *((int *)&__m256_op05) = 0x00000000; ++ *((int *)&__m256_op04) = 0x00000000; ++ *((int *)&__m256_op03) = 0x00000000; ++ *((int *)&__m256_op02) = 0x00000000; ++ *((int *)&__m256_op01) = 0x00000000; ++ *((int *)&__m256_op00) = 0x00000000; ++ *((int *)&__m256_op17) = 0x00000003; ++ *((int *)&__m256_op16) = 0x0000000c; ++ *((int *)&__m256_op15) = 0x00000011; ++ *((int *)&__m256_op14) = 0x00000000; ++ *((int *)&__m256_op13) = 0x00000005; ++ *((int *)&__m256_op12) = 0x00000000; ++ *((int *)&__m256_op11) = 0x00000008; ++ *((int *)&__m256_op10) = 0x00000010; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvfcvt_h_s (__m256_op0, __m256_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((int *)&__m256_op07) = 0x6d6d6d6d; ++ *((int *)&__m256_op06) = 0x6d6d6d6d; ++ *((int *)&__m256_op05) = 0x6d6d6d6d; ++ *((int *)&__m256_op04) = 0x6d6d6d6d; ++ *((int *)&__m256_op03) = 0x6d6d6d6d; ++ *((int *)&__m256_op02) = 0x6d6d6d6d; ++ *((int *)&__m256_op01) = 0x6d6d6d6d; ++ *((int *)&__m256_op00) = 0x6d6d6d6d; ++ *((int *)&__m256_op17) = 0x6d6d6d6d; ++ *((int *)&__m256_op16) = 0x6d6d6d6d; ++ *((int *)&__m256_op15) = 0x6d6d6d6d; ++ *((int *)&__m256_op14) = 0x6d6d6d6d; ++ *((int *)&__m256_op13) = 0x6d6d6d6d; ++ *((int *)&__m256_op12) = 0x6d6d6d6d; ++ *((int *)&__m256_op11) = 0x6d6d6d6d; ++ *((int *)&__m256_op10) = 0x6d6d6d6d; ++ *((unsigned long *)&__m256i_result3) = 0x7c007c007c007c00; ++ *((unsigned long *)&__m256i_result2) = 0x7c007c007c007c00; ++ *((unsigned long *)&__m256i_result1) = 0x7c007c007c007c00; ++ *((unsigned long *)&__m256i_result0) = 0x7c007c007c007c00; ++ __m256i_out = __lasx_xvfcvt_h_s (__m256_op0, __m256_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((int *)&__m256_op07) = 0x00000000; ++ *((int *)&__m256_op06) = 0x00000000; ++ *((int *)&__m256_op05) = 0x00000000; ++ *((int *)&__m256_op04) = 0x00000000; ++ *((int *)&__m256_op03) = 0x00000000; ++ *((int *)&__m256_op02) = 0x00000000; ++ *((int *)&__m256_op01) = 0x00000000; ++ *((int *)&__m256_op00) = 0x00000000; ++ *((int *)&__m256_op17) = 0x00000000; ++ *((int *)&__m256_op16) = 0x00000000; ++ *((int *)&__m256_op15) = 0x00000000; ++ *((int *)&__m256_op14) = 0x00000000; ++ *((int *)&__m256_op13) = 0x00000000; ++ *((int *)&__m256_op12) = 0x00000000; ++ *((int *)&__m256_op11) = 0x00000000; ++ *((int *)&__m256_op10) = 0x00000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvfcvt_h_s (__m256_op0, __m256_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((int *)&__m256_op07) = 0xffffffff; ++ *((int *)&__m256_op06) = 0xffffffff; ++ *((int *)&__m256_op05) = 0xffffffff; ++ *((int *)&__m256_op04) = 0xffffffff; ++ *((int *)&__m256_op03) = 0xffffffff; ++ *((int *)&__m256_op02) = 0xffffffff; ++ *((int *)&__m256_op01) = 0xffffffff; ++ *((int *)&__m256_op00) = 0xffffffff; ++ *((int *)&__m256_op17) = 0x00000000; ++ *((int *)&__m256_op16) = 0x00000000; ++ *((int *)&__m256_op15) = 0x00000000; ++ *((int *)&__m256_op14) = 0x00000000; ++ *((int *)&__m256_op13) = 0x00000000;
View file
_service:tar_scm:LoongArch-Add-tests-for-ASX-vector-floating-point-op.patch
Added
@@ -0,0 +1,5614 @@ +From 9a9935e736a9289e0a1c0a77f4110c206ce36bd2 Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Tue, 12 Sep 2023 16:03:17 +0800 +Subject: PATCH 111/124 LoongArch: Add tests for ASX vector floating-point + operation instruction. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/vector/lasx/lasx-xvfadd_d.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvfadd_s.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvfclass_d.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvfclass_s.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvflogb_d.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvflogb_s.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvfmadd_d.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvfmadd_s.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvfmax_d.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvfmax_s.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvfmaxa_d.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvfmaxa_s.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvfsqrt_d.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvfsqrt_s.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/vector/lasx/lasx-xvfadd_d.c | 545 +++++++++++ + .../loongarch/vector/lasx/lasx-xvfadd_s.c | 911 ++++++++++++++++++ + .../loongarch/vector/lasx/lasx-xvfclass_d.c | 152 +++ + .../loongarch/vector/lasx/lasx-xvfclass_s.c | 95 ++ + .../loongarch/vector/lasx/lasx-xvflogb_d.c | 86 ++ + .../loongarch/vector/lasx/lasx-xvflogb_s.c | 115 +++ + .../loongarch/vector/lasx/lasx-xvfmadd_d.c | 382 ++++++++ + .../loongarch/vector/lasx/lasx-xvfmadd_s.c | 720 ++++++++++++++ + .../loongarch/vector/lasx/lasx-xvfmax_d.c | 230 +++++ + .../loongarch/vector/lasx/lasx-xvfmax_s.c | 560 +++++++++++ + .../loongarch/vector/lasx/lasx-xvfmaxa_d.c | 230 +++++ + .../loongarch/vector/lasx/lasx-xvfmaxa_s.c | 506 ++++++++++ + .../loongarch/vector/lasx/lasx-xvfsqrt_d.c | 482 +++++++++ + .../loongarch/vector/lasx/lasx-xvfsqrt_s.c | 457 +++++++++ + 14 files changed, 5471 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfadd_d.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfadd_s.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfclass_d.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfclass_s.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvflogb_d.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvflogb_s.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfmadd_d.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfmadd_s.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfmax_d.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfmax_s.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfmaxa_d.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfmaxa_s.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfsqrt_d.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfsqrt_s.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfadd_d.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfadd_d.c +new file mode 100644 +index 000000000..657a19e58 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfadd_d.c +@@ -0,0 +1,545 @@ ++/* { dg-do run } */ ++/* { dg-options "-mlasx -w -fno-strict-aliasing" } */ ++#include "../simd_correctness_check.h" ++#include <lasxintrin.h> ++ ++int ++main () ++{ ++ __m256i __m256i_op0, __m256i_op1, __m256i_op2, __m256i_out, __m256i_result; ++ __m256 __m256_op0, __m256_op1, __m256_op2, __m256_out, __m256_result; ++ __m256d __m256d_op0, __m256d_op1, __m256d_op2, __m256d_out, __m256d_result; ++ ++ int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail; ++ long int long_op0, long_op1, long_op2, lont_out, lont_result; ++ long int long_int_out, long_int_result; ++ unsigned int unsigned_int_out, unsigned_int_result; ++ unsigned long int unsigned_long_int_out, unsigned_long_int_result; ++ ++ *((unsigned long *)&__m256d_op03) = 0x0000ffff0000ffff; ++ *((unsigned long *)&__m256d_op02) = 0xffff00000000ffff; ++ *((unsigned long *)&__m256d_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op13) = 0x7ffffffffffff7ff; ++ *((unsigned long *)&__m256d_op12) = 0xffffffffe06df0d7; ++ *((unsigned long *)&__m256d_op11) = 0x7ffffffffffff7ff; ++ *((unsigned long *)&__m256d_op10) = 0xffffffffbe8b470f; ++ *((unsigned long *)&__m256d_result3) = 0x7ffffffffffff7ff; ++ *((unsigned long *)&__m256d_result2) = 0xffff00000000ffff; ++ *((unsigned long *)&__m256d_result1) = 0x7ffffffffffff7ff; ++ *((unsigned long *)&__m256d_result0) = 0xffffffffbe8b470f; ++ __m256d_out = __lasx_xvfadd_d (__m256d_op0, __m256d_op1); ++ ASSERTEQ_64 (__LINE__, __m256d_result, __m256d_out); ++ ++ *((unsigned long *)&__m256d_op03) = 0x41d6600000000000; ++ *((unsigned long *)&__m256d_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op01) = 0x41d6600000000000; ++ *((unsigned long *)&__m256d_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op12) = 0x7fffffffffffffff; ++ *((unsigned long *)&__m256d_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op10) = 0x7fffffffffffffff; ++ *((unsigned long *)&__m256d_result3) = 0x41d6600000000000; ++ *((unsigned long *)&__m256d_result2) = 0x7fffffffffffffff; ++ *((unsigned long *)&__m256d_result1) = 0x41d6600000000000; ++ *((unsigned long *)&__m256d_result0) = 0x7fffffffffffffff; ++ __m256d_out = __lasx_xvfadd_d (__m256d_op0, __m256d_op1); ++ ASSERTEQ_64 (__LINE__, __m256d_result, __m256d_out); ++ ++ *((unsigned long *)&__m256d_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op13) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256d_op12) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256d_op11) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256d_op10) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256d_result3) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256d_result2) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256d_result1) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256d_result0) = 0xffffffffffffffff; ++ __m256d_out = __lasx_xvfadd_d (__m256d_op0, __m256d_op1); ++ ASSERTEQ_64 (__LINE__, __m256d_result, __m256d_out); ++ ++ *((unsigned long *)&__m256d_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_result0) = 0x0000000000000000; ++ __m256d_out = __lasx_xvfadd_d (__m256d_op0, __m256d_op1); ++ ASSERTEQ_64 (__LINE__, __m256d_result, __m256d_out); ++ ++ *((unsigned long *)&__m256d_op03) = 0x00007fff00007fff; ++ *((unsigned long *)&__m256d_op02) = 0x00007fff00007fff; ++ *((unsigned long *)&__m256d_op01) = 0x00007fff00007fff; ++ *((unsigned long *)&__m256d_op00) = 0x00007fff00007fff; ++ *((unsigned long *)&__m256d_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_result3) = 0x00007fff00007fff; ++ *((unsigned long *)&__m256d_result2) = 0x00007fff00007fff; ++ *((unsigned long *)&__m256d_result1) = 0x00007fff00007fff; ++ *((unsigned long *)&__m256d_result0) = 0x00007fff00007fff; ++ __m256d_out = __lasx_xvfadd_d (__m256d_op0, __m256d_op1); ++ ASSERTEQ_64 (__LINE__, __m256d_result, __m256d_out); ++ ++ *((unsigned long *)&__m256d_op03) = 0x0000000022beb03f; ++ *((unsigned long *)&__m256d_op02) = 0x7fffffffa2beb040; ++ *((unsigned long *)&__m256d_op01) = 0x0000000022beb03f; ++ *((unsigned long *)&__m256d_op00) = 0x7fffffffa2beb040; ++ *((unsigned long *)&__m256d_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op12) = 0x000f000000000000; ++ *((unsigned long *)&__m256d_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op10) = 0x000f000000000000; ++ *((unsigned long *)&__m256d_result3) = 0x0000000022beb03f; ++ *((unsigned long *)&__m256d_result2) = 0x7fffffffa2beb040; ++ *((unsigned long *)&__m256d_result1) = 0x0000000022beb03f; ++ *((unsigned long *)&__m256d_result0) = 0x7fffffffa2beb040; ++ __m256d_out = __lasx_xvfadd_d (__m256d_op0, __m256d_op1); ++ ASSERTEQ_64 (__LINE__, __m256d_result, __m256d_out); ++ ++ *((unsigned long *)&__m256d_op03) = 0x000001c000000134; ++ *((unsigned long *)&__m256d_op02) = 0x7fff7fff7fff7fff; ++ *((unsigned long *)&__m256d_op01) = 0x000001c000000134; ++ *((unsigned long *)&__m256d_op00) = 0x7fff7fff7fff7fff; ++ *((unsigned long *)&__m256d_op13) = 0x000001c000000134; ++ *((unsigned long *)&__m256d_op12) = 0x7fff7fff7fff7fff; ++ *((unsigned long *)&__m256d_op11) = 0x000001c000000134; ++ *((unsigned long *)&__m256d_op10) = 0x7fff7fff7fff7fff; ++ *((unsigned long *)&__m256d_result3) = 0x0000038000000268; ++ *((unsigned long *)&__m256d_result2) = 0x7fff7fff7fff7fff; ++ *((unsigned long *)&__m256d_result1) = 0x0000038000000268; ++ *((unsigned long *)&__m256d_result0) = 0x7fff7fff7fff7fff; ++ __m256d_out = __lasx_xvfadd_d (__m256d_op0, __m256d_op1); ++ ASSERTEQ_64 (__LINE__, __m256d_result, __m256d_out); ++ ++ *((unsigned long *)&__m256d_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_result0) = 0x0000000000000000; ++ __m256d_out = __lasx_xvfadd_d (__m256d_op0, __m256d_op1); ++ ASSERTEQ_64 (__LINE__, __m256d_result, __m256d_out);
View file
_service:tar_scm:LoongArch-Add-tests-for-ASX-vector-subtraction-instr.patch
Added
@@ -0,0 +1,4566 @@ +From dcd9959504b5e8a0d9346d9ffb45542c1250c538 Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Tue, 12 Sep 2023 15:21:25 +0800 +Subject: PATCH 101/124 LoongArch: Add tests for ASX vector subtraction + instructions. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/vector/lasx/lasx-xvssub-1.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvssub-2.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvsub.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvsubi.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvsubwev-1.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvsubwev-2.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvsubwod-1.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvsubwod-2.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/vector/lasx/lasx-xvssub-1.c | 425 +++++++++++ + .../loongarch/vector/lasx/lasx-xvssub-2.c | 695 ++++++++++++++++++ + .../loongarch/vector/lasx/lasx-xvsub.c | 590 +++++++++++++++ + .../loongarch/vector/lasx/lasx-xvsubi.c | 482 ++++++++++++ + .../loongarch/vector/lasx/lasx-xvsubwev-1.c | 530 +++++++++++++ + .../loongarch/vector/lasx/lasx-xvsubwev-2.c | 440 +++++++++++ + .../loongarch/vector/lasx/lasx-xvsubwod-1.c | 695 ++++++++++++++++++ + .../loongarch/vector/lasx/lasx-xvsubwod-2.c | 620 ++++++++++++++++ + 8 files changed, 4477 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvssub-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvssub-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvsub.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvsubi.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvsubwev-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvsubwev-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvsubwod-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvsubwod-2.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvssub-1.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvssub-1.c +new file mode 100644 +index 000000000..ada72a16a +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvssub-1.c +@@ -0,0 +1,425 @@ ++/* { dg-do run } */ ++/* { dg-options "-mlasx -w -fno-strict-aliasing" } */ ++#include "../simd_correctness_check.h" ++#include <lasxintrin.h> ++ ++int ++main () ++{ ++ __m256i __m256i_op0, __m256i_op1, __m256i_op2, __m256i_out, __m256i_result; ++ __m256 __m256_op0, __m256_op1, __m256_op2, __m256_out, __m256_result; ++ __m256d __m256d_op0, __m256d_op1, __m256d_op2, __m256d_out, __m256d_result; ++ ++ int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail; ++ long int long_op0, long_op1, long_op2, lont_out, lont_result; ++ long int long_int_out, long_int_result; ++ unsigned int unsigned_int_out, unsigned_int_result; ++ unsigned long int unsigned_long_int_out, unsigned_long_int_result; ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x00000000000001dc; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x00000000000001dc; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x000000000000ff24; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x000000000000ff24; ++ __m256i_out = __lasx_xvssub_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x2020202020202020; ++ *((unsigned long *)&__m256i_op02) = 0x2020202020202020; ++ *((unsigned long *)&__m256i_op01) = 0x2020202020202020; ++ *((unsigned long *)&__m256i_op00) = 0x2020202020202020; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x2020202020202020; ++ *((unsigned long *)&__m256i_result2) = 0x2020202020202020; ++ *((unsigned long *)&__m256i_result1) = 0x2020202020202020; ++ *((unsigned long *)&__m256i_result0) = 0x2020202020202020; ++ __m256i_out = __lasx_xvssub_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvssub_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x000000430207f944; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x000000430207f944; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x000000bdfef907bc; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x000000bdfef907bc; ++ __m256i_out = __lasx_xvssub_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000010101010101; ++ *((unsigned long *)&__m256i_op02) = 0x0101000000010000; ++ *((unsigned long *)&__m256i_op01) = 0x0000010101010101; ++ *((unsigned long *)&__m256i_op00) = 0x0101000000010000; ++ *((unsigned long *)&__m256i_op13) = 0x0000010101010101; ++ *((unsigned long *)&__m256i_op12) = 0x0101000000010000; ++ *((unsigned long *)&__m256i_op11) = 0x0000010101010101; ++ *((unsigned long *)&__m256i_op10) = 0x0101000000010000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvssub_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000080; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000040; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x000000000000ff80; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x000000000000ffc0; ++ __m256i_out = __lasx_xvssub_h (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x2b2b2b2b1bd68080; ++ *((unsigned long *)&__m256i_op12) = 0x2a2ad4d4f2d8807e; ++ *((unsigned long *)&__m256i_op11) = 0x2b2b2b2b1bd68080; ++ *((unsigned long *)&__m256i_op10) = 0x2a2ad4d4f2d8807e; ++ *((unsigned long *)&__m256i_result3) = 0xd4d5d4d5e42a7f80; ++ *((unsigned long *)&__m256i_result2) = 0xd5d62b2c0d287f82; ++ *((unsigned long *)&__m256i_result1) = 0xd4d5d4d5e42a7f80; ++ *((unsigned long *)&__m256i_result0) = 0xd5d62b2c0d287f82; ++ __m256i_out = __lasx_xvssub_h (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x8000000080000001; ++ *((unsigned long *)&__m256i_op02) = 0x8000000080000001; ++ *((unsigned long *)&__m256i_op01) = 0x8000000080000001; ++ *((unsigned long *)&__m256i_op00) = 0x8000000080000001; ++ *((unsigned long *)&__m256i_op13) = 0x8000000080000001; ++ *((unsigned long *)&__m256i_op12) = 0x8000000080000001; ++ *((unsigned long *)&__m256i_op11) = 0x8000000080000001; ++ *((unsigned long *)&__m256i_op10) = 0x8000000080000001; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvssub_h (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0xffff07b4ffff0707; ++ *((unsigned long *)&__m256i_op02) = 0x0000b8070000a787; ++ *((unsigned long *)&__m256i_op01) = 0xffff07b4ffff0707; ++ *((unsigned long *)&__m256i_op00) = 0x0000b8070000a787; ++ *((unsigned long *)&__m256i_op13) = 0x0000504fffff3271; ++ *((unsigned long *)&__m256i_op12) = 0xffff47b4ffff5879; ++ *((unsigned long *)&__m256i_op11) = 0x0000504fffff3271; ++ *((unsigned long *)&__m256i_op10) = 0xffff47b4ffff5879; ++ *((unsigned long *)&__m256i_result3) = 0xffffb7650000d496; ++ *((unsigned long *)&__m256i_result2) = 0x0001800000018000; ++ *((unsigned long *)&__m256i_result1) = 0xffffb7650000d496; ++ *((unsigned long *)&__m256i_result0) = 0x0001800000018000; ++ __m256i_out = __lasx_xvssub_h (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000;
View file
_service:tar_scm:LoongArch-Add-tests-for-ASX-vector-xvabsd-xvavg-xvav.patch
Added
@@ -0,0 +1,5595 @@ +From 02a3c7b1dc6b66bad2d7eca396176cb9fd731a79 Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Tue, 12 Sep 2023 16:42:49 +0800 +Subject: PATCH 115/124 LoongArch: Add tests for ASX vector + xvabsd/xvavg/xvavgr/xvbsll/xvbsrl/xvneg/ xvsat instructions. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/vector/lasx/lasx-xvabsd-1.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvabsd-2.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvavg-1.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvavg-2.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvavgr-1.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvavgr-2.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvbsll_v.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvbsrl_v.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvneg.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvsat-1.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvsat-2.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/vector/lasx/lasx-xvabsd-1.c | 485 +++++++++++ + .../loongarch/vector/lasx/lasx-xvabsd-2.c | 650 +++++++++++++++ + .../loongarch/vector/lasx/lasx-xvavg-1.c | 680 ++++++++++++++++ + .../loongarch/vector/lasx/lasx-xvavg-2.c | 560 +++++++++++++ + .../loongarch/vector/lasx/lasx-xvavgr-1.c | 770 ++++++++++++++++++ + .../loongarch/vector/lasx/lasx-xvavgr-2.c | 650 +++++++++++++++ + .../loongarch/vector/lasx/lasx-xvbsll_v.c | 130 +++ + .../loongarch/vector/lasx/lasx-xvbsrl_v.c | 64 ++ + .../loongarch/vector/lasx/lasx-xvneg.c | 526 ++++++++++++ + .../loongarch/vector/lasx/lasx-xvsat-1.c | 537 ++++++++++++ + .../loongarch/vector/lasx/lasx-xvsat-2.c | 427 ++++++++++ + 11 files changed, 5479 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvabsd-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvabsd-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvavg-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvavg-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvavgr-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvavgr-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvbsll_v.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvbsrl_v.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvneg.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvsat-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvsat-2.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvabsd-1.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvabsd-1.c +new file mode 100644 +index 000000000..41fae32df +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvabsd-1.c +@@ -0,0 +1,485 @@ ++/* { dg-do run } */ ++/* { dg-options "-mlasx -w -fno-strict-aliasing" } */ ++#include "../simd_correctness_check.h" ++#include <lasxintrin.h> ++ ++int ++main () ++{ ++ __m256i __m256i_op0, __m256i_op1, __m256i_op2, __m256i_out, __m256i_result; ++ __m256 __m256_op0, __m256_op1, __m256_op2, __m256_out, __m256_result; ++ __m256d __m256d_op0, __m256d_op1, __m256d_op2, __m256d_out, __m256d_result; ++ ++ int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail; ++ long int long_op0, long_op1, long_op2, lont_out, lont_result; ++ long int long_int_out, long_int_result; ++ unsigned int unsigned_int_out, unsigned_int_result; ++ unsigned long int unsigned_long_int_out, unsigned_long_int_result; ++ ++ *((unsigned long *)&__m256i_op03) = 0x34598d0fd19314cb; ++ *((unsigned long *)&__m256i_op02) = 0x1820939b2280fa86; ++ *((unsigned long *)&__m256i_op01) = 0x4a1c269b8e892a3a; ++ *((unsigned long *)&__m256i_op00) = 0x063f2bb758abc664; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0xffffc0fcffffcf83; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000288a00003c1c; ++ *((unsigned long *)&__m256i_result3) = 0x3459730f2f6d1435; ++ *((unsigned long *)&__m256i_result2) = 0x19212d61237f2b03; ++ *((unsigned long *)&__m256i_result1) = 0x4a1c266572772a3a; ++ *((unsigned long *)&__m256i_result0) = 0x063f032d58557648; ++ __m256i_out = __lasx_xvabsd_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvabsd_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0xfe00000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x1cfd000000000000; ++ *((unsigned long *)&__m256i_op01) = 0xfe00000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x1cfd000000000000; ++ *((unsigned long *)&__m256i_op13) = 0xfe00000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x1cfd000000000000; ++ *((unsigned long *)&__m256i_op11) = 0xfe00000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x1cfd000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvabsd_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvabsd_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x000000007fff7fff; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x000000007fff7fff; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x000000007f017f01; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x000000007f017f01; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvabsd_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvabsd_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvabsd_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x000050504c4c2362; ++ *((unsigned long *)&__m256i_op02) = 0x000b2673a90896a4; ++ *((unsigned long *)&__m256i_op01) = 0x000050504c4c2362; ++ *((unsigned long *)&__m256i_op00) = 0x000b2673a90896a4; ++ *((unsigned long *)&__m256i_op13) = 0x0001000100010001; ++ *((unsigned long *)&__m256i_op12) = 0xd0d8eecf383fdf0d; ++ *((unsigned long *)&__m256i_op11) = 0x0001000100010001; ++ *((unsigned long *)&__m256i_op10) = 0xd0d8eecf383fdf0d; ++ *((unsigned long *)&__m256i_result3) = 0x0001504f4c4b2361; ++ *((unsigned long *)&__m256i_result2) = 0x303338a48f374969; ++ *((unsigned long *)&__m256i_result1) = 0x0001504f4c4b2361; ++ *((unsigned long *)&__m256i_result0) = 0x303338a48f374969; ++ __m256i_out = __lasx_xvabsd_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000002; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000002; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000002; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000002; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000;
View file
_service:tar_scm:LoongArch-Add-tests-for-ASX-vector-xvadd-xvadda-xvad.patch
Added
@@ -0,0 +1,6368 @@ +From a6d51c0d69572f800f63c3215b7de6665024104c Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Tue, 12 Sep 2023 15:15:40 +0800 +Subject: PATCH 099/124 LoongArch: Add tests for ASX vector + xvadd/xvadda/xvaddi/xvaddwev/ xvaddwodxvsadd instructions. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/vector/lasx/lasx-xvadd.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvadda.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvaddi.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvaddwev-1.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvaddwev-2.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvaddwev-3.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvaddwod-1.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvaddwod-2.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvaddwod-3.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvsadd-1.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvsadd-2.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/vector/lasx/lasx-xvadd.c | 725 ++++++++++++++++ + .../loongarch/vector/lasx/lasx-xvadda.c | 785 ++++++++++++++++++ + .../loongarch/vector/lasx/lasx-xvaddi.c | 427 ++++++++++ + .../loongarch/vector/lasx/lasx-xvaddwev-1.c | 740 +++++++++++++++++ + .../loongarch/vector/lasx/lasx-xvaddwev-2.c | 485 +++++++++++ + .../loongarch/vector/lasx/lasx-xvaddwev-3.c | 515 ++++++++++++ + .../loongarch/vector/lasx/lasx-xvaddwod-1.c | 530 ++++++++++++ + .../loongarch/vector/lasx/lasx-xvaddwod-2.c | 560 +++++++++++++ + .../loongarch/vector/lasx/lasx-xvaddwod-3.c | 485 +++++++++++ + .../loongarch/vector/lasx/lasx-xvsadd-1.c | 650 +++++++++++++++ + .../loongarch/vector/lasx/lasx-xvsadd-2.c | 350 ++++++++ + 11 files changed, 6252 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvadd.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvadda.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvaddi.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvaddwev-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvaddwev-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvaddwev-3.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvaddwod-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvaddwod-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvaddwod-3.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvsadd-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvsadd-2.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvadd.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvadd.c +new file mode 100644 +index 000000000..293295723 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvadd.c +@@ -0,0 +1,725 @@ ++/* { dg-do run } */ ++/* { dg-options "-mlasx -w -fno-strict-aliasing" } */ ++#include "../simd_correctness_check.h" ++#include <lasxintrin.h> ++ ++int ++main () ++{ ++ __m256i __m256i_op0, __m256i_op1, __m256i_op2, __m256i_out, __m256i_result; ++ __m256 __m256_op0, __m256_op1, __m256_op2, __m256_out, __m256_result; ++ __m256d __m256d_op0, __m256d_op1, __m256d_op2, __m256d_out, __m256d_result; ++ ++ int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail; ++ long int long_op0, long_op1, long_op2, lont_out, lont_result; ++ long int long_int_out, long_int_result; ++ unsigned int unsigned_int_out, unsigned_int_result; ++ unsigned long int unsigned_long_int_out, unsigned_long_int_result; ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvadd_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvadd_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op12) = 0xffffffff00000000; ++ *((unsigned long *)&__m256i_op11) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op10) = 0xffffffff00000000; ++ *((unsigned long *)&__m256i_result3) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_result2) = 0xffffffff00000000; ++ *((unsigned long *)&__m256i_result1) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_result0) = 0xffffffff00000000; ++ __m256i_out = __lasx_xvadd_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op02) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op01) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op00) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000ffff0000ffff; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000ffff0000ffff; ++ *((unsigned long *)&__m256i_result3) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_result2) = 0xfffffefefffffefe; ++ *((unsigned long *)&__m256i_result1) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_result0) = 0xfffffefefffffefe; ++ __m256i_out = __lasx_xvadd_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0xffffffffffffffff; ++ __m256i_out = __lasx_xvadd_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x41cfe01dde000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x41cfe01dde000000; ++ *((unsigned long *)&__m256i_op13) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_result2) = 0x41cfe01dde000000; ++ *((unsigned long *)&__m256i_result1) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_result0) = 0x41cfe01dde000000; ++ __m256i_out = __lasx_xvadd_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000004000000040; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000004000000040; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000004000000040; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000004000000040; ++ __m256i_out = __lasx_xvadd_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvadd_h (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000;
View file
_service:tar_scm:LoongArch-Add-tests-for-ASX-vector-xvand-xvandi-xvan.patch
Added
@@ -0,0 +1,1854 @@ +From ceef99197d4db1d34e5c8aeae2b5492d831685d0 Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Tue, 12 Sep 2023 15:42:34 +0800 +Subject: PATCH 105/124 LoongArch: Add tests for ASX vector + xvand/xvandi/xvandn/xvor/xvori/ xvnor/xvnori/xvxor/xvxori instructions. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/vector/lasx/lasx-xvand.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvandi.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvandn.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvnor.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvnori.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvor.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvori.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvorn.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvxor.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvxori.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/vector/lasx/lasx-xvand.c | 155 +++++++++++ + .../loongarch/vector/lasx/lasx-xvandi.c | 196 ++++++++++++++ + .../loongarch/vector/lasx/lasx-xvandn.c | 125 +++++++++ + .../loongarch/vector/lasx/lasx-xvnor.c | 170 ++++++++++++ + .../loongarch/vector/lasx/lasx-xvnori.c | 152 +++++++++++ + .../loongarch/vector/lasx/lasx-xvor.c | 215 +++++++++++++++ + .../loongarch/vector/lasx/lasx-xvori.c | 141 ++++++++++ + .../loongarch/vector/lasx/lasx-xvorn.c | 245 ++++++++++++++++++ + .../loongarch/vector/lasx/lasx-xvxor.c | 185 +++++++++++++ + .../loongarch/vector/lasx/lasx-xvxori.c | 163 ++++++++++++ + 10 files changed, 1747 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvand.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvandi.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvandn.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvnor.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvnori.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvor.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvori.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvorn.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvxor.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvxori.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvand.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvand.c +new file mode 100644 +index 000000000..e485786dd +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvand.c +@@ -0,0 +1,155 @@ ++/* { dg-do run } */ ++/* { dg-options "-mlasx -w -fno-strict-aliasing" } */ ++#include "../simd_correctness_check.h" ++#include <lasxintrin.h> ++ ++int ++main () ++{ ++ __m256i __m256i_op0, __m256i_op1, __m256i_op2, __m256i_out, __m256i_result; ++ __m256 __m256_op0, __m256_op1, __m256_op2, __m256_out, __m256_result; ++ __m256d __m256d_op0, __m256d_op1, __m256d_op2, __m256d_out, __m256d_result; ++ ++ int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail; ++ long int long_op0, long_op1, long_op2, lont_out, lont_result; ++ long int long_int_out, long_int_result; ++ unsigned int unsigned_int_out, unsigned_int_result; ++ unsigned long int unsigned_long_int_out, unsigned_long_int_result; ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0010001000100010; ++ *((unsigned long *)&__m256i_op12) = 0x0010001000100010; ++ *((unsigned long *)&__m256i_op11) = 0x0010001000100010; ++ *((unsigned long *)&__m256i_op10) = 0x0010001000100010; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvand_v (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvand_v (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvand_v (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x2020202020202020; ++ *((unsigned long *)&__m256i_op02) = 0x2020202020202020; ++ *((unsigned long *)&__m256i_op01) = 0x2020202020202020; ++ *((unsigned long *)&__m256i_op00) = 0x2020202020202020; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvand_v (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x000000000000ffff; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x000000000000ffff; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvand_v (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvand_v (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0xfefee00000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0xfefee00000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0xfffffffe00000001; ++ *((unsigned long *)&__m256i_op12) = 0xfffffffe00000001; ++ *((unsigned long *)&__m256i_op11) = 0xfffffffe00000001; ++ *((unsigned long *)&__m256i_op10) = 0xfffffffe00000001; ++ *((unsigned long *)&__m256i_result3) = 0xfefee00000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0xfefee00000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvand_v (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x00000004843ffdff; ++ *((unsigned long *)&__m256i_op02) = 0x8000000080000000; ++ *((unsigned long *)&__m256i_op01) = 0x00000004843ffdff; ++ *((unsigned long *)&__m256i_op00) = 0x8000000080000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvand_v (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x00000000000000ff; ++ *((unsigned long *)&__m256i_op13) = 0xff1cff1cff1cff1c; ++ *((unsigned long *)&__m256i_op12) = 0xff1cff1cff1cff1c; ++ *((unsigned long *)&__m256i_op11) = 0xff1cff1cff1cff1c; ++ *((unsigned long *)&__m256i_op10) = 0xff1cff1cff1cff1c; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000;
View file
_service:tar_scm:LoongArch-Add-tests-for-ASX-vector-xvbitclr-xvbitclr.patch
Added
@@ -0,0 +1,5057 @@ +From a6390d1a6619b6bee4fc87b15ffd25936704eb21 Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Tue, 12 Sep 2023 15:57:18 +0800 +Subject: PATCH 108/124 LoongArch: Add tests for ASX vector + xvbitclr/xvbitclri/xvbitrev/xvbitrevi/ + xvbitsel/xvbitseli/xvbitset/xvbitseti/xvclo/xvclz/xvpcnt instructions. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/vector/lasx/lasx-xvbitclr.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvbitclri.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvbitrev.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvbitrevi.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvbitsel.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvbitseli.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvbitset.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvbitseti.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvclo.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvclz.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvpcnt.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/vector/lasx/lasx-xvbitclr.c | 635 +++++++++++++++++ + .../loongarch/vector/lasx/lasx-xvbitclri.c | 515 ++++++++++++++ + .../loongarch/vector/lasx/lasx-xvbitrev.c | 650 ++++++++++++++++++ + .../loongarch/vector/lasx/lasx-xvbitrevi.c | 317 +++++++++ + .../loongarch/vector/lasx/lasx-xvbitsel.c | 134 ++++ + .../loongarch/vector/lasx/lasx-xvbitseli.c | 185 +++++ + .../loongarch/vector/lasx/lasx-xvbitset.c | 620 +++++++++++++++++ + .../loongarch/vector/lasx/lasx-xvbitseti.c | 405 +++++++++++ + .../loongarch/vector/lasx/lasx-xvclo.c | 449 ++++++++++++ + .../loongarch/vector/lasx/lasx-xvclz.c | 504 ++++++++++++++ + .../loongarch/vector/lasx/lasx-xvpcnt.c | 526 ++++++++++++++ + 11 files changed, 4940 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvbitclr.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvbitclri.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvbitrev.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvbitrevi.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvbitsel.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvbitseli.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvbitset.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvbitseti.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvclo.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvclz.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvpcnt.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvbitclr.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvbitclr.c +new file mode 100644 +index 000000000..def7b588e +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvbitclr.c +@@ -0,0 +1,635 @@ ++/* { dg-do run } */ ++/* { dg-options "-mlasx -w -fno-strict-aliasing" } */ ++#include "../simd_correctness_check.h" ++#include <lasxintrin.h> ++ ++int ++main () ++{ ++ __m256i __m256i_op0, __m256i_op1, __m256i_op2, __m256i_out, __m256i_result; ++ __m256 __m256_op0, __m256_op1, __m256_op2, __m256_out, __m256_result; ++ __m256d __m256d_op0, __m256d_op1, __m256d_op2, __m256d_out, __m256d_result; ++ ++ int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail; ++ long int long_op0, long_op1, long_op2, lont_out, lont_result; ++ long int long_int_out, long_int_result; ++ unsigned int unsigned_int_out, unsigned_int_result; ++ unsigned long int unsigned_long_int_out, unsigned_long_int_result; ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x000000040000fff8; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvbitclr_w (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvbitclr_d (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0xffffffffffffff1f; ++ *((unsigned long *)&__m256i_op02) = 0xfffffffffffffeff; ++ *((unsigned long *)&__m256i_op01) = 0xffffffffffffff1f; ++ *((unsigned long *)&__m256i_op00) = 0xfffffffffffffeff; ++ *((unsigned long *)&__m256i_op13) = 0x00000105fffffefb; ++ *((unsigned long *)&__m256i_op12) = 0xffffff02000000fe; ++ *((unsigned long *)&__m256i_op11) = 0x00000105fffffefb; ++ *((unsigned long *)&__m256i_op10) = 0xffffff02000000fe; ++ *((unsigned long *)&__m256i_result3) = 0xf7ffffffffffff1f; ++ *((unsigned long *)&__m256i_result2) = 0xbffffffffffffeff; ++ *((unsigned long *)&__m256i_result1) = 0xf7ffffffffffff1f; ++ *((unsigned long *)&__m256i_result0) = 0xbffffffffffffeff; ++ __m256i_out = __lasx_xvbitclr_d (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0xfffffffffffffefd; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000101; ++ *((unsigned long *)&__m256i_op01) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op00) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op13) = 0xfffffffffffffefd; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000101; ++ *((unsigned long *)&__m256i_op11) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op10) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_result3) = 0x7fff7fff7fffdefd; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000101; ++ *((unsigned long *)&__m256i_result1) = 0x7fff7fff7fff7fff; ++ *((unsigned long *)&__m256i_result0) = 0x7fff7fff7fff7fff; ++ __m256i_out = __lasx_xvbitclr_h (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvbitclr_w (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvbitclr_d (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x00000000f0000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x00000000f0000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x1fe01e0000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x1fe01e0000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x00000000f0000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x00000000f0000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvbitclr_w (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0006000000040000; ++ *((unsigned long *)&__m256i_op02) = 0x0002555500000000; ++ *((unsigned long *)&__m256i_op01) = 0x0006000000040000; ++ *((unsigned long *)&__m256i_op00) = 0x0002555500000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0006000000040000; ++ *((unsigned long *)&__m256i_result2) = 0x0002555400000000; ++ *((unsigned long *)&__m256i_result1) = 0x0006000000040000; ++ *((unsigned long *)&__m256i_result0) = 0x0002555400000000; ++ __m256i_out = __lasx_xvbitclr_w (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000;
View file
_service:tar_scm:LoongArch-Add-tests-for-ASX-vector-xvext2xv-xvexth-x.patch
Added
@@ -0,0 +1,4600 @@ +From 5cf957f25df755431bc77845fecb5bec0624c097 Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Tue, 12 Sep 2023 16:51:19 +0800 +Subject: PATCH 118/124 LoongArch: Add tests for ASX vector + xvext2xv/xvexth/xvextins/xvilvh/xvilvl/xvinsgr2vr/ xvinsve0/xvprem/xvpremi + instructions. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/vector/lasx/lasx-xvext2xv-1.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvext2xv-2.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvexth-1.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvexth-2.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvextrins.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvilvh.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvilvl.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvinsgr2vr.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvinsve0.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvprem.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvpremi.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/vector/lasx/lasx-xvext2xv-1.c | 515 ++++++++++++++ + .../loongarch/vector/lasx/lasx-xvext2xv-2.c | 669 ++++++++++++++++++ + .../loongarch/vector/lasx/lasx-xvexth-1.c | 350 +++++++++ + .../loongarch/vector/lasx/lasx-xvexth-2.c | 592 ++++++++++++++++ + .../loongarch/vector/lasx/lasx-xvextrins.c | 515 ++++++++++++++ + .../loongarch/vector/lasx/lasx-xvilvh.c | 530 ++++++++++++++ + .../loongarch/vector/lasx/lasx-xvilvl.c | 620 ++++++++++++++++ + .../loongarch/vector/lasx/lasx-xvinsgr2vr.c | 272 +++++++ + .../loongarch/vector/lasx/lasx-xvinsve0.c | 380 ++++++++++ + .../loongarch/vector/lasx/lasx-xvprem.c | 20 + + .../loongarch/vector/lasx/lasx-xvpremi.c | 20 + + 11 files changed, 4483 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvext2xv-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvext2xv-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvexth-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvexth-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvextrins.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvilvh.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvilvl.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvinsgr2vr.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvinsve0.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvprem.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvpremi.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvext2xv-1.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvext2xv-1.c +new file mode 100644 +index 000000000..94f31019c +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvext2xv-1.c +@@ -0,0 +1,515 @@ ++/* { dg-do run } */ ++/* { dg-options "-mlasx -w -fno-strict-aliasing" } */ ++#include "../simd_correctness_check.h" ++#include <lasxintrin.h> ++ ++int ++main () ++{ ++ __m256i __m256i_op0, __m256i_op1, __m256i_op2, __m256i_out, __m256i_result; ++ __m256 __m256_op0, __m256_op1, __m256_op2, __m256_out, __m256_result; ++ __m256d __m256d_op0, __m256d_op1, __m256d_op2, __m256d_out, __m256d_result; ++ ++ int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail; ++ long int long_op0, long_op1, long_op2, lont_out, lont_result; ++ long int long_int_out, long_int_result; ++ unsigned int unsigned_int_out, unsigned_int_result; ++ unsigned long int unsigned_long_int_out, unsigned_long_int_result; ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_vext2xv_h_b (__m256i_op0); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_vext2xv_h_b (__m256i_op0); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_vext2xv_h_b (__m256i_op0); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_vext2xv_h_b (__m256i_op0); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_vext2xv_h_b (__m256i_op0); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_vext2xv_h_b (__m256i_op0); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x2b2b2b2b1bd5d5d6; ++ *((unsigned long *)&__m256i_op02) = 0x2a2a2a2af2d5d5d6; ++ *((unsigned long *)&__m256i_op01) = 0x2b2b2b2b1bd5d5d6; ++ *((unsigned long *)&__m256i_op00) = 0x2a2a2a2af2d5d5d6; ++ *((unsigned long *)&__m256i_result3) = 0x0000002a0000002a; ++ *((unsigned long *)&__m256i_result2) = 0x0000002a0000002a; ++ *((unsigned long *)&__m256i_result1) = 0xfffffff2ffffffd5; ++ *((unsigned long *)&__m256i_result0) = 0xffffffd5ffffffd6; ++ __m256i_out = __lasx_vext2xv_w_b (__m256i_op0); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_result3) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_result2) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_result1) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_result0) = 0xffffffffffffffff; ++ __m256i_out = __lasx_vext2xv_w_b (__m256i_op0); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op02) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op01) = 0x00000000ffffffff; ++ *((unsigned long *)&__m256i_op00) = 0xffffffff00000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_vext2xv_d_b (__m256i_op0); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x000000007fffffff; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x000000007fffffff; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_vext2xv_d_b (__m256i_op0); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_vext2xv_d_b (__m256i_op0); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x007f00ff007f00ff; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x007f00ff007f00ff; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x000000000000007f;
View file
_service:tar_scm:LoongArch-Add-tests-for-ASX-vector-xvextl-xvsra-xvsr.patch
Added
@@ -0,0 +1,4737 @@ +From bf5805833fc26d26a1fbbdc7dfe10109c0c676f9 Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Tue, 12 Sep 2023 15:49:41 +0800 +Subject: PATCH 107/124 LoongArch: Add tests for ASX vector + xvextl/xvsra/xvsran/xvsrarn instructions. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/vector/lasx/lasx-xvextl-1.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvextl-2.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvsra.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvsrai.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvsran.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvsrani.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvsrar.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvsrari.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvsrarn.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvsrarni.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/vector/lasx/lasx-xvextl-1.c | 86 +++ + .../loongarch/vector/lasx/lasx-xvextl-2.c | 163 ++++ + .../loongarch/vector/lasx/lasx-xvsra.c | 545 +++++++++++++ + .../loongarch/vector/lasx/lasx-xvsrai.c | 504 ++++++++++++ + .../loongarch/vector/lasx/lasx-xvsran.c | 455 +++++++++++ + .../loongarch/vector/lasx/lasx-xvsrani.c | 545 +++++++++++++ + .../loongarch/vector/lasx/lasx-xvsrar.c | 725 ++++++++++++++++++ + .../loongarch/vector/lasx/lasx-xvsrari.c | 471 ++++++++++++ + .../loongarch/vector/lasx/lasx-xvsrarn.c | 500 ++++++++++++ + .../loongarch/vector/lasx/lasx-xvsrarni.c | 636 +++++++++++++++ + 10 files changed, 4630 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvextl-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvextl-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvsra.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvsrai.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvsran.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvsrani.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvsrar.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvsrari.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvsrarn.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvsrarni.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvextl-1.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvextl-1.c +new file mode 100644 +index 000000000..c0d3e8e75 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvextl-1.c +@@ -0,0 +1,86 @@ ++/* { dg-do run } */ ++/* { dg-options "-mlasx -w -fno-strict-aliasing" } */ ++#include "../simd_correctness_check.h" ++#include <lasxintrin.h> ++ ++int ++main () ++{ ++ __m256i __m256i_op0, __m256i_op1, __m256i_op2, __m256i_out, __m256i_result; ++ __m256 __m256_op0, __m256_op1, __m256_op2, __m256_out, __m256_result; ++ __m256d __m256d_op0, __m256d_op1, __m256d_op2, __m256d_out, __m256d_result; ++ ++ int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail; ++ long int long_op0, long_op1, long_op2, lont_out, lont_result; ++ long int long_int_out, long_int_result; ++ unsigned int unsigned_int_out, unsigned_int_result; ++ unsigned long int unsigned_long_int_out, unsigned_long_int_result; ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvextl_q_d (__m256i_op0); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvextl_q_d (__m256i_op0); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvextl_q_d (__m256i_op0); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x43ef878780000009; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x43ef878780000009; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x43ef878780000009; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x43ef878780000009; ++ __m256i_out = __lasx_xvextl_q_d (__m256i_op0); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x000201220001011c; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x000201220001011c; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x000201220001011c; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x000201220001011c; ++ __m256i_out = __lasx_xvextl_q_d (__m256i_op0); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvextl_q_d (__m256i_op0); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ return 0; ++} +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvextl-2.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvextl-2.c +new file mode 100644 +index 000000000..8c7ab4ed3 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvextl-2.c +@@ -0,0 +1,163 @@ ++/* { dg-do run } */ ++/* { dg-options "-mlasx -w -fno-strict-aliasing" } */ ++#include "../simd_correctness_check.h" ++#include <lasxintrin.h> ++ ++int ++main () ++{ ++ __m256i __m256i_op0, __m256i_op1, __m256i_op2, __m256i_out, __m256i_result; ++ __m256 __m256_op0, __m256_op1, __m256_op2, __m256_out, __m256_result; ++ __m256d __m256d_op0, __m256d_op1, __m256d_op2, __m256d_out, __m256d_result; ++ ++ int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail; ++ long int long_op0, long_op1, long_op2, lont_out, lont_result; ++ long int long_int_out, long_int_result; ++ unsigned int unsigned_int_out, unsigned_int_result; ++ unsigned long int unsigned_long_int_out, unsigned_long_int_result; ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x8000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x8000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x8000000000000000; ++ __m256i_out = __lasx_xvextl_qu_du (__m256i_op0); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0101010101010101; ++ *((unsigned long *)&__m256i_op02) = 0x0101010101010101; ++ *((unsigned long *)&__m256i_op01) = 0x0101010101010101; ++ *((unsigned long *)&__m256i_op00) = 0x0101010101010101; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0101010101010101; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0101010101010101; ++ __m256i_out = __lasx_xvextl_qu_du (__m256i_op0); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000001010101; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000001010101; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvextl_qu_du (__m256i_op0); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000100000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000;
View file
_service:tar_scm:LoongArch-Add-tests-for-ASX-vector-xvfcmp-caf-ceq-cl.patch
Added
@@ -0,0 +1,4510 @@ +From ab8716fe8109c738ac02b641160350d2b351466b Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Tue, 12 Sep 2023 16:45:33 +0800 +Subject: PATCH 116/124 LoongArch: Add tests for ASX vector + xvfcmp{caf/ceq/cle/clt/cne/cor/cun} instructions. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/vector/lasx/lasx-xvfcmp_caf_s.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvfcmp_ceq_s.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvfcmp_cle_s.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvfcmp_clt_s.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvfcmp_cne_s.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvfcmp_cor_s.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvfcmp_cun_s.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/vector/lasx/lasx-xvfcmp_caf_s.c | 446 ++++++++ + .../loongarch/vector/lasx/lasx-xvfcmp_ceq_s.c | 977 ++++++++++++++++++ + .../loongarch/vector/lasx/lasx-xvfcmp_cle_s.c | 759 ++++++++++++++ + .../loongarch/vector/lasx/lasx-xvfcmp_clt_s.c | 675 ++++++++++++ + .../loongarch/vector/lasx/lasx-xvfcmp_cne_s.c | 872 ++++++++++++++++ + .../loongarch/vector/lasx/lasx-xvfcmp_cor_s.c | 340 ++++++ + .../loongarch/vector/lasx/lasx-xvfcmp_cun_s.c | 361 +++++++ + 7 files changed, 4430 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfcmp_caf_s.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfcmp_ceq_s.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfcmp_cle_s.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfcmp_clt_s.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfcmp_cne_s.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfcmp_cor_s.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfcmp_cun_s.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfcmp_caf_s.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfcmp_caf_s.c +new file mode 100644 +index 000000000..fa3372358 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfcmp_caf_s.c +@@ -0,0 +1,446 @@ ++/* { dg-do run } */ ++/* { dg-options "-mlasx -w -fno-strict-aliasing" } */ ++#include "../simd_correctness_check.h" ++#include <lasxintrin.h> ++ ++int ++main () ++{ ++ __m256i __m256i_op0, __m256i_op1, __m256i_op2, __m256i_out, __m256i_result; ++ __m256 __m256_op0, __m256_op1, __m256_op2, __m256_out, __m256_result; ++ __m256d __m256d_op0, __m256d_op1, __m256d_op2, __m256d_out, __m256d_result; ++ ++ int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail; ++ long int long_op0, long_op1, long_op2, lont_out, lont_result; ++ long int long_int_out, long_int_result; ++ unsigned int unsigned_int_out, unsigned_int_result; ++ unsigned long int unsigned_long_int_out, unsigned_long_int_result; ++ ++ *((int *)&__m256_op07) = 0x00000000; ++ *((int *)&__m256_op06) = 0x00000000; ++ *((int *)&__m256_op05) = 0x00000000; ++ *((int *)&__m256_op04) = 0x00000000; ++ *((int *)&__m256_op03) = 0x00000000; ++ *((int *)&__m256_op02) = 0x00000000; ++ *((int *)&__m256_op01) = 0x00000000; ++ *((int *)&__m256_op00) = 0x00000000; ++ *((int *)&__m256_op17) = 0x00000000; ++ *((int *)&__m256_op16) = 0x00000000; ++ *((int *)&__m256_op15) = 0x00000000; ++ *((int *)&__m256_op14) = 0x00000000; ++ *((int *)&__m256_op13) = 0x00000000; ++ *((int *)&__m256_op12) = 0x00000000; ++ *((int *)&__m256_op11) = 0x00000000; ++ *((int *)&__m256_op10) = 0x00000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvfcmp_caf_s (__m256_op0, __m256_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((int *)&__m256_op07) = 0x00000000; ++ *((int *)&__m256_op06) = 0x00000000; ++ *((int *)&__m256_op05) = 0x00000000; ++ *((int *)&__m256_op04) = 0x00000000; ++ *((int *)&__m256_op03) = 0x00000000; ++ *((int *)&__m256_op02) = 0x00000000; ++ *((int *)&__m256_op01) = 0x00000000; ++ *((int *)&__m256_op00) = 0x00000000; ++ *((int *)&__m256_op17) = 0x00000000; ++ *((int *)&__m256_op16) = 0x00000000; ++ *((int *)&__m256_op15) = 0x00000000; ++ *((int *)&__m256_op14) = 0x00000000; ++ *((int *)&__m256_op13) = 0x00000000; ++ *((int *)&__m256_op12) = 0x00000000; ++ *((int *)&__m256_op11) = 0x00000000; ++ *((int *)&__m256_op10) = 0x00000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvfcmp_caf_s (__m256_op0, __m256_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((int *)&__m256_op07) = 0x00000000; ++ *((int *)&__m256_op06) = 0x00000000; ++ *((int *)&__m256_op05) = 0xff56ff55; ++ *((int *)&__m256_op04) = 0xff01ff01; ++ *((int *)&__m256_op03) = 0x00000000; ++ *((int *)&__m256_op02) = 0x00000000; ++ *((int *)&__m256_op01) = 0xff56ff55; ++ *((int *)&__m256_op00) = 0xff01ff01; ++ *((int *)&__m256_op17) = 0x00000000; ++ *((int *)&__m256_op16) = 0x00000000; ++ *((int *)&__m256_op15) = 0x0000abff; ++ *((int *)&__m256_op14) = 0x0000abff; ++ *((int *)&__m256_op13) = 0x00000000; ++ *((int *)&__m256_op12) = 0x00000000; ++ *((int *)&__m256_op11) = 0x0000abff; ++ *((int *)&__m256_op10) = 0x0000abff; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvfcmp_caf_s (__m256_op0, __m256_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((int *)&__m256_op07) = 0x00000000; ++ *((int *)&__m256_op06) = 0x00000000; ++ *((int *)&__m256_op05) = 0x00000001; ++ *((int *)&__m256_op04) = 0x0000000a; ++ *((int *)&__m256_op03) = 0x00000000; ++ *((int *)&__m256_op02) = 0x00000000; ++ *((int *)&__m256_op01) = 0x00000001; ++ *((int *)&__m256_op00) = 0x0000000a; ++ *((int *)&__m256_op17) = 0x00000000; ++ *((int *)&__m256_op16) = 0x00000000; ++ *((int *)&__m256_op15) = 0x00000000; ++ *((int *)&__m256_op14) = 0x00000040; ++ *((int *)&__m256_op13) = 0x00000000; ++ *((int *)&__m256_op12) = 0x00000000; ++ *((int *)&__m256_op11) = 0x00000000; ++ *((int *)&__m256_op10) = 0x00000040; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvfcmp_caf_s (__m256_op0, __m256_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((int *)&__m256_op07) = 0x00000000; ++ *((int *)&__m256_op06) = 0x00000000; ++ *((int *)&__m256_op05) = 0x00000000; ++ *((int *)&__m256_op04) = 0x00000000; ++ *((int *)&__m256_op03) = 0x00000000; ++ *((int *)&__m256_op02) = 0x00000000; ++ *((int *)&__m256_op01) = 0x00000000; ++ *((int *)&__m256_op00) = 0x00000000; ++ *((int *)&__m256_op17) = 0x5d20a0a1; ++ *((int *)&__m256_op16) = 0x5d20a0a1; ++ *((int *)&__m256_op15) = 0x00000000; ++ *((int *)&__m256_op14) = 0x00000000; ++ *((int *)&__m256_op13) = 0x5d20a0a1; ++ *((int *)&__m256_op12) = 0x5d20a0a1; ++ *((int *)&__m256_op11) = 0x00000000; ++ *((int *)&__m256_op10) = 0x00000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvfcmp_caf_s (__m256_op0, __m256_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((int *)&__m256_op07) = 0x00000000; ++ *((int *)&__m256_op06) = 0x00000000; ++ *((int *)&__m256_op05) = 0x00000000; ++ *((int *)&__m256_op04) = 0x0003ffff; ++ *((int *)&__m256_op03) = 0x00000000; ++ *((int *)&__m256_op02) = 0x00000000; ++ *((int *)&__m256_op01) = 0x00000000; ++ *((int *)&__m256_op00) = 0x00000000; ++ *((int *)&__m256_op17) = 0x00000000; ++ *((int *)&__m256_op16) = 0x00000000; ++ *((int *)&__m256_op15) = 0x00000000; ++ *((int *)&__m256_op14) = 0x00000000; ++ *((int *)&__m256_op13) = 0x00000000; ++ *((int *)&__m256_op12) = 0x00000000; ++ *((int *)&__m256_op11) = 0x00000000; ++ *((int *)&__m256_op10) = 0x00000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvfcmp_caf_s (__m256_op0, __m256_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((int *)&__m256_op07) = 0xffff8000; ++ *((int *)&__m256_op06) = 0x00000000;
View file
_service:tar_scm:LoongArch-Add-tests-for-ASX-vector-xvfcmp-saf-seq-sl.patch
Added
@@ -0,0 +1,4824 @@ +From beaeb3f05a71c637d47a0e5f86f5781345e10f97 Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Tue, 12 Sep 2023 16:48:35 +0800 +Subject: PATCH 117/124 LoongArch: Add tests for ASX vector + xvfcmp{saf/seq/sle/slt/sne/sor/sun} instructions. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/vector/lasx/lasx-xvfcmp_saf_s.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvfcmp_seq_s.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvfcmp_sle_s.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvfcmp_slt_s.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvfcmp_sne_s.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvfcmp_sor_s.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvfcmp_sun_s.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/vector/lasx/lasx-xvfcmp_saf_s.c | 424 ++++++ + .../loongarch/vector/lasx/lasx-xvfcmp_seq_s.c | 924 +++++++++++++ + .../loongarch/vector/lasx/lasx-xvfcmp_sle_s.c | 627 +++++++++ + .../loongarch/vector/lasx/lasx-xvfcmp_slt_s.c | 1212 +++++++++++++++++ + .../loongarch/vector/lasx/lasx-xvfcmp_sne_s.c | 756 ++++++++++ + .../loongarch/vector/lasx/lasx-xvfcmp_sor_s.c | 438 ++++++ + .../loongarch/vector/lasx/lasx-xvfcmp_sun_s.c | 363 +++++ + 7 files changed, 4744 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfcmp_saf_s.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfcmp_seq_s.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfcmp_sle_s.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfcmp_slt_s.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfcmp_sne_s.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfcmp_sor_s.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfcmp_sun_s.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfcmp_saf_s.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfcmp_saf_s.c +new file mode 100644 +index 000000000..23cbc4bf0 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfcmp_saf_s.c +@@ -0,0 +1,424 @@ ++/* { dg-do run } */ ++/* { dg-options "-mlasx -w -fno-strict-aliasing" } */ ++#include "../simd_correctness_check.h" ++#include <lasxintrin.h> ++ ++int ++main () ++{ ++ __m256i __m256i_op0, __m256i_op1, __m256i_op2, __m256i_out, __m256i_result; ++ __m256 __m256_op0, __m256_op1, __m256_op2, __m256_out, __m256_result; ++ __m256d __m256d_op0, __m256d_op1, __m256d_op2, __m256d_out, __m256d_result; ++ ++ int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail; ++ long int long_op0, long_op1, long_op2, lont_out, lont_result; ++ long int long_int_out, long_int_result; ++ unsigned int unsigned_int_out, unsigned_int_result; ++ unsigned long int unsigned_long_int_out, unsigned_long_int_result; ++ ++ *((int *)&__m256_op07) = 0x00000000; ++ *((int *)&__m256_op06) = 0x00000000; ++ *((int *)&__m256_op05) = 0x00000000; ++ *((int *)&__m256_op04) = 0x00000000; ++ *((int *)&__m256_op03) = 0x00000000; ++ *((int *)&__m256_op02) = 0x00000000; ++ *((int *)&__m256_op01) = 0x00000000; ++ *((int *)&__m256_op00) = 0x00000000; ++ *((int *)&__m256_op17) = 0x00000000; ++ *((int *)&__m256_op16) = 0x00000000; ++ *((int *)&__m256_op15) = 0x00000000; ++ *((int *)&__m256_op14) = 0x00000000; ++ *((int *)&__m256_op13) = 0x00000000; ++ *((int *)&__m256_op12) = 0x00000000; ++ *((int *)&__m256_op11) = 0x00000000; ++ *((int *)&__m256_op10) = 0x00000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvfcmp_saf_s (__m256_op0, __m256_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((int *)&__m256_op07) = 0x00000000; ++ *((int *)&__m256_op06) = 0x00000000; ++ *((int *)&__m256_op05) = 0x0000ffff; ++ *((int *)&__m256_op04) = 0x0000ffff; ++ *((int *)&__m256_op03) = 0x00000000; ++ *((int *)&__m256_op02) = 0x00000000; ++ *((int *)&__m256_op01) = 0x0000ffff; ++ *((int *)&__m256_op00) = 0x0000ffff; ++ *((int *)&__m256_op17) = 0x0eb7aaaa; ++ *((int *)&__m256_op16) = 0xa6e6ac80; ++ *((int *)&__m256_op15) = 0x00000000; ++ *((int *)&__m256_op14) = 0x00000000; ++ *((int *)&__m256_op13) = 0x0eb7aaaa; ++ *((int *)&__m256_op12) = 0xa6e6ac80; ++ *((int *)&__m256_op11) = 0x00000000; ++ *((int *)&__m256_op10) = 0x00000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvfcmp_saf_s (__m256_op0, __m256_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((int *)&__m256_op07) = 0x3fff3fff; ++ *((int *)&__m256_op06) = 0x3fff3fff; ++ *((int *)&__m256_op05) = 0x00000000; ++ *((int *)&__m256_op04) = 0x3fff3fff; ++ *((int *)&__m256_op03) = 0x3fff3fff; ++ *((int *)&__m256_op02) = 0x3fff3fff; ++ *((int *)&__m256_op01) = 0x00000000; ++ *((int *)&__m256_op00) = 0x3fff3fff; ++ *((int *)&__m256_op17) = 0x017e01fe; ++ *((int *)&__m256_op16) = 0x01fe01fe; ++ *((int *)&__m256_op15) = 0x05860606; ++ *((int *)&__m256_op14) = 0x01fe0202; ++ *((int *)&__m256_op13) = 0x017e01fe; ++ *((int *)&__m256_op12) = 0x01fe0000; ++ *((int *)&__m256_op11) = 0x05860606; ++ *((int *)&__m256_op10) = 0x01fe0004; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvfcmp_saf_s (__m256_op0, __m256_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((int *)&__m256_op07) = 0x0000003f; ++ *((int *)&__m256_op06) = 0x00390035; ++ *((int *)&__m256_op05) = 0x8015003f; ++ *((int *)&__m256_op04) = 0x0006001f; ++ *((int *)&__m256_op03) = 0x0000003f; ++ *((int *)&__m256_op02) = 0x00390035; ++ *((int *)&__m256_op01) = 0x8015003f; ++ *((int *)&__m256_op00) = 0x0006001f; ++ *((int *)&__m256_op17) = 0xffffffff; ++ *((int *)&__m256_op16) = 0xffffffff; ++ *((int *)&__m256_op15) = 0xffffffff; ++ *((int *)&__m256_op14) = 0xffffffff; ++ *((int *)&__m256_op13) = 0xffffffff; ++ *((int *)&__m256_op12) = 0xffffffff; ++ *((int *)&__m256_op11) = 0xffffffff; ++ *((int *)&__m256_op10) = 0xffffffff; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvfcmp_saf_s (__m256_op0, __m256_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((int *)&__m256_op07) = 0x00000000; ++ *((int *)&__m256_op06) = 0x00000000; ++ *((int *)&__m256_op05) = 0x00000000; ++ *((int *)&__m256_op04) = 0x00000000; ++ *((int *)&__m256_op03) = 0x00000000; ++ *((int *)&__m256_op02) = 0x00000000; ++ *((int *)&__m256_op01) = 0x00000000; ++ *((int *)&__m256_op00) = 0x00000000; ++ *((int *)&__m256_op17) = 0xefdfefdf; ++ *((int *)&__m256_op16) = 0x00000000; ++ *((int *)&__m256_op15) = 0xefdfefdf; ++ *((int *)&__m256_op14) = 0xefdfefdf; ++ *((int *)&__m256_op13) = 0xefdfefdf; ++ *((int *)&__m256_op12) = 0x00000000; ++ *((int *)&__m256_op11) = 0xefdfefdf; ++ *((int *)&__m256_op10) = 0xefdfefdf; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvfcmp_saf_s (__m256_op0, __m256_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((int *)&__m256_op07) = 0x00000000; ++ *((int *)&__m256_op06) = 0x00000000; ++ *((int *)&__m256_op05) = 0x00000000; ++ *((int *)&__m256_op04) = 0x00000000; ++ *((int *)&__m256_op03) = 0x00000000; ++ *((int *)&__m256_op02) = 0x00000000; ++ *((int *)&__m256_op01) = 0x00000000; ++ *((int *)&__m256_op00) = 0x00000000; ++ *((int *)&__m256_op17) = 0x00ff00ff; ++ *((int *)&__m256_op16) = 0x00ff00ff; ++ *((int *)&__m256_op15) = 0x00ff00ff; ++ *((int *)&__m256_op14) = 0x00ff00ff; ++ *((int *)&__m256_op13) = 0x00ff00ff; ++ *((int *)&__m256_op12) = 0x00ff00ff; ++ *((int *)&__m256_op11) = 0x00ff00ff; ++ *((int *)&__m256_op10) = 0x00ff00ff; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvfcmp_saf_s (__m256_op0, __m256_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((int *)&__m256_op07) = 0x00000001; ++ *((int *)&__m256_op06) = 0x7bfffff0;
View file
_service:tar_scm:LoongArch-Add-tests-for-ASX-vector-xvfnmadd-xvfrstp-.patch
Added
@@ -0,0 +1,4991 @@ +From d0108f9375bd6eede5f7f4e289dce580b180848d Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Tue, 12 Sep 2023 16:22:49 +0800 +Subject: PATCH 114/124 LoongArch: Add tests for ASX vector + xvfnmadd/xvfrstp/xvfstpi/xvhsubw/ xvmsub/xvrotr/xvrotri/xvld/xvst + instructions. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/vector/lasx/lasx-xvfnmadd_d.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvfnmadd_s.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvfrstp.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvfrstpi.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvhsubw-1.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvhsubw-2.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvld.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvmsub.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvrotr.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvrotri.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvst.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/vector/lasx/lasx-xvfnmadd_d.c | 324 +++++++ + .../loongarch/vector/lasx/lasx-xvfnmadd_s.c | 895 ++++++++++++++++++ + .../loongarch/vector/lasx/lasx-xvfrstp.c | 381 ++++++++ + .../loongarch/vector/lasx/lasx-xvfrstpi.c | 350 +++++++ + .../loongarch/vector/lasx/lasx-xvhsubw-1.c | 620 ++++++++++++ + .../loongarch/vector/lasx/lasx-xvhsubw-2.c | 545 +++++++++++ + .../loongarch/vector/lasx/lasx-xvld.c | 86 ++ + .../loongarch/vector/lasx/lasx-xvmsub.c | 647 +++++++++++++ + .../loongarch/vector/lasx/lasx-xvrotr.c | 530 +++++++++++ + .../loongarch/vector/lasx/lasx-xvrotri.c | 394 ++++++++ + .../loongarch/vector/lasx/lasx-xvst.c | 102 ++ + 11 files changed, 4874 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfnmadd_d.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfnmadd_s.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfrstp.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfrstpi.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvhsubw-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvhsubw-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvld.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvmsub.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvrotr.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvrotri.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvst.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfnmadd_d.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfnmadd_d.c +new file mode 100644 +index 000000000..d161c850c +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfnmadd_d.c +@@ -0,0 +1,324 @@ ++/* { dg-do run } */ ++/* { dg-options "-mlasx -w -fno-strict-aliasing" } */ ++#include "../simd_correctness_check.h" ++#include <lasxintrin.h> ++ ++int ++main () ++{ ++ __m256i __m256i_op0, __m256i_op1, __m256i_op2, __m256i_out, __m256i_result; ++ __m256 __m256_op0, __m256_op1, __m256_op2, __m256_out, __m256_result; ++ __m256d __m256d_op0, __m256d_op1, __m256d_op2, __m256d_out, __m256d_result; ++ ++ int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail; ++ long int long_op0, long_op1, long_op2, lont_out, lont_result; ++ long int long_int_out, long_int_result; ++ unsigned int unsigned_int_out, unsigned_int_result; ++ unsigned long int unsigned_long_int_out, unsigned_long_int_result; ++ ++ *((unsigned long *)&__m256d_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op13) = 0x0001010101010101; ++ *((unsigned long *)&__m256d_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op11) = 0x0000000000010100; ++ *((unsigned long *)&__m256d_op10) = 0x0001000001000100; ++ *((unsigned long *)&__m256d_op23) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256d_op22) = 0xffffffffbf7f7fff; ++ *((unsigned long *)&__m256d_op21) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256d_op20) = 0xffffffffe651bfff; ++ *((unsigned long *)&__m256d_result3) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256d_result2) = 0xffffffffbf7f7fff; ++ *((unsigned long *)&__m256d_result1) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256d_result0) = 0xffffffffe651bfff; ++ __m256d_out = __lasx_xvfnmadd_d (__m256d_op0, __m256d_op1, __m256d_op2); ++ ASSERTEQ_64 (__LINE__, __m256d_result, __m256d_out); ++ ++ *((unsigned long *)&__m256d_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op13) = 0x3ff73ff83ff73ff8; ++ *((unsigned long *)&__m256d_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op11) = 0x3ff73ff83ff73ff8; ++ *((unsigned long *)&__m256d_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op23) = 0x2020202020202020; ++ *((unsigned long *)&__m256d_op22) = 0x2020202020206431; ++ *((unsigned long *)&__m256d_op21) = 0x2020202020202020; ++ *((unsigned long *)&__m256d_op20) = 0x2020202020206431; ++ *((unsigned long *)&__m256d_result3) = 0xa020202020202020; ++ *((unsigned long *)&__m256d_result2) = 0xa020202020206431; ++ *((unsigned long *)&__m256d_result1) = 0xa020202020202020; ++ *((unsigned long *)&__m256d_result0) = 0xa020202020206431; ++ __m256d_out = __lasx_xvfnmadd_d (__m256d_op0, __m256d_op1, __m256d_op2); ++ ASSERTEQ_64 (__LINE__, __m256d_result, __m256d_out); ++ ++ *((unsigned long *)&__m256d_op03) = 0x00000000f0f0f0f0; ++ *((unsigned long *)&__m256d_op02) = 0xf0f0f0f0f0f0f0f0; ++ *((unsigned long *)&__m256d_op01) = 0x00000000f0f0f0f0; ++ *((unsigned long *)&__m256d_op00) = 0xf0f0f0f0f0f0f0f0; ++ *((unsigned long *)&__m256d_op13) = 0x00000000ffffffff; ++ *((unsigned long *)&__m256d_op12) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256d_op11) = 0x00000000ffffffff; ++ *((unsigned long *)&__m256d_op10) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256d_op23) = 0x0001b0b1b4b5dd9f; ++ *((unsigned long *)&__m256d_op22) = 0x7f7f7f5c8f374980; ++ *((unsigned long *)&__m256d_op21) = 0x0001b0b1b4b5dd9f; ++ *((unsigned long *)&__m256d_op20) = 0x7f7f7f5c8f374980; ++ *((unsigned long *)&__m256d_result3) = 0x8001b0b1b4b5dd9f; ++ *((unsigned long *)&__m256d_result2) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256d_result1) = 0x8001b0b1b4b5dd9f; ++ *((unsigned long *)&__m256d_result0) = 0xffffffffffffffff; ++ __m256d_out = __lasx_xvfnmadd_d (__m256d_op0, __m256d_op1, __m256d_op2); ++ ASSERTEQ_64 (__LINE__, __m256d_result, __m256d_out); ++ ++ *((unsigned long *)&__m256d_op03) = 0xff21ff21ff21ff21; ++ *((unsigned long *)&__m256d_op02) = 0xff21ff21ff21ff21; ++ *((unsigned long *)&__m256d_op01) = 0xff21ff21ff21ff21; ++ *((unsigned long *)&__m256d_op00) = 0xff21ff21ff21ff21; ++ *((unsigned long *)&__m256d_op13) = 0xff21c241ff21c241; ++ *((unsigned long *)&__m256d_op12) = 0xff21c241ff21c241; ++ *((unsigned long *)&__m256d_op11) = 0xff21c241ff21c241; ++ *((unsigned long *)&__m256d_op10) = 0xff21c241ff21c241; ++ *((unsigned long *)&__m256d_op23) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op22) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op21) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op20) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_result3) = 0xfff0000000000000; ++ *((unsigned long *)&__m256d_result2) = 0xfff0000000000000; ++ *((unsigned long *)&__m256d_result1) = 0xfff0000000000000; ++ *((unsigned long *)&__m256d_result0) = 0xfff0000000000000; ++ __m256d_out = __lasx_xvfnmadd_d (__m256d_op0, __m256d_op1, __m256d_op2); ++ ASSERTEQ_64 (__LINE__, __m256d_result, __m256d_out); ++ ++ *((unsigned long *)&__m256d_op03) = 0x0000000000000040; ++ *((unsigned long *)&__m256d_op02) = 0x0000000000000007; ++ *((unsigned long *)&__m256d_op01) = 0x0000000000000040; ++ *((unsigned long *)&__m256d_op00) = 0x0000000000000007; ++ *((unsigned long *)&__m256d_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op12) = 0x0000ffff0000ffff; ++ *((unsigned long *)&__m256d_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op10) = 0x0000ffff0000ffff; ++ *((unsigned long *)&__m256d_op23) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op22) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op21) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op20) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_result3) = 0x8000000000000000; ++ *((unsigned long *)&__m256d_result2) = 0x8000000000000000; ++ *((unsigned long *)&__m256d_result1) = 0x8000000000000000; ++ *((unsigned long *)&__m256d_result0) = 0x8000000000000000; ++ __m256d_out = __lasx_xvfnmadd_d (__m256d_op0, __m256d_op1, __m256d_op2); ++ ASSERTEQ_64 (__LINE__, __m256d_result, __m256d_out); ++ ++ *((unsigned long *)&__m256d_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op02) = 0x1080108010060002; ++ *((unsigned long *)&__m256d_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op00) = 0x1080108010060002; ++ *((unsigned long *)&__m256d_op13) = 0xffffffe4ffffffe4; ++ *((unsigned long *)&__m256d_op12) = 0xffffffe4ffffffe4; ++ *((unsigned long *)&__m256d_op11) = 0xffffffe4ffffffe4; ++ *((unsigned long *)&__m256d_op10) = 0xffffffe4ffffffe4; ++ *((unsigned long *)&__m256d_op23) = 0x7fff00017fff0000; ++ *((unsigned long *)&__m256d_op22) = 0x7fff00017fff0000; ++ *((unsigned long *)&__m256d_op21) = 0x7fff00017fff0000; ++ *((unsigned long *)&__m256d_op20) = 0x7fff00017fff0000; ++ *((unsigned long *)&__m256d_result3) = 0x7fff00017fff0000; ++ *((unsigned long *)&__m256d_result2) = 0x7fff00017fff0000; ++ *((unsigned long *)&__m256d_result1) = 0x7fff00017fff0000; ++ *((unsigned long *)&__m256d_result0) = 0x7fff00017fff0000; ++ __m256d_out = __lasx_xvfnmadd_d (__m256d_op0, __m256d_op1, __m256d_op2); ++ ASSERTEQ_64 (__LINE__, __m256d_result, __m256d_out); ++ ++ *((unsigned long *)&__m256d_op03) = 0x1716151417161514; ++ *((unsigned long *)&__m256d_op02) = 0x1716151417161514; ++ *((unsigned long *)&__m256d_op01) = 0x1716151417161514; ++ *((unsigned long *)&__m256d_op00) = 0x1716151417161514; ++ *((unsigned long *)&__m256d_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op12) = 0x0000000000002780; ++ *((unsigned long *)&__m256d_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op10) = 0x0000000000002780; ++ *((unsigned long *)&__m256d_op23) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op22) = 0x0000000000002780; ++ *((unsigned long *)&__m256d_op21) = 0x0000000000000000; ++ *((unsigned long *)&__m256d_op20) = 0x0000000000002780; ++ *((unsigned long *)&__m256d_result3) = 0x8000000000000000;
View file
_service:tar_scm:LoongArch-Add-tests-for-ASX-vector-xvhadd-xvhaddw-xv.patch
Added
@@ -0,0 +1,6930 @@ +From 03f7a61fa5efb197cdd66014552aa8727677b891 Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Tue, 12 Sep 2023 15:19:28 +0800 +Subject: PATCH 100/124 LoongArch: Add tests for ASX vector + xvhadd/xvhaddw/xvmaddwev/xvmaddwod instructions. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/vector/lasx/lasx-xvhaddw-1.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvhaddw-2.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvmadd.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvmaddwev-1.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvmaddwev-2.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvmaddwev-3.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvmaddwod-1.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvmaddwod-2.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvmaddwod-3.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/vector/lasx/lasx-xvhaddw-1.c | 560 +++++++++++ + .../loongarch/vector/lasx/lasx-xvhaddw-2.c | 650 ++++++++++++ + .../loongarch/vector/lasx/lasx-xvmadd.c | 742 ++++++++++++++ + .../loongarch/vector/lasx/lasx-xvmaddwev-1.c | 856 ++++++++++++++++ + .../loongarch/vector/lasx/lasx-xvmaddwev-2.c | 723 ++++++++++++++ + .../loongarch/vector/lasx/lasx-xvmaddwev-3.c | 940 ++++++++++++++++++ + .../loongarch/vector/lasx/lasx-xvmaddwod-1.c | 742 ++++++++++++++ + .../loongarch/vector/lasx/lasx-xvmaddwod-2.c | 799 +++++++++++++++ + .../loongarch/vector/lasx/lasx-xvmaddwod-3.c | 820 +++++++++++++++ + 9 files changed, 6832 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvhaddw-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvhaddw-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvmadd.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvmaddwev-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvmaddwev-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvmaddwev-3.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvmaddwod-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvmaddwod-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvmaddwod-3.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvhaddw-1.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvhaddw-1.c +new file mode 100644 +index 000000000..1cf0ec698 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvhaddw-1.c +@@ -0,0 +1,560 @@ ++/* { dg-do run } */ ++/* { dg-options "-mlasx -w -fno-strict-aliasing" } */ ++#include "../simd_correctness_check.h" ++#include <lasxintrin.h> ++ ++int ++main () ++{ ++ __m256i __m256i_op0, __m256i_op1, __m256i_op2, __m256i_out, __m256i_result; ++ __m256 __m256_op0, __m256_op1, __m256_op2, __m256_out, __m256_result; ++ __m256d __m256d_op0, __m256d_op1, __m256d_op2, __m256d_out, __m256d_result; ++ ++ int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail; ++ long int long_op0, long_op1, long_op2, lont_out, lont_result; ++ long int long_int_out, long_int_result; ++ unsigned int unsigned_int_out, unsigned_int_result; ++ unsigned long int unsigned_long_int_out, unsigned_long_int_result; ++ ++ *((unsigned long *)&__m256i_op03) = 0xf7ffffffffffff1f; ++ *((unsigned long *)&__m256i_op02) = 0xbffffffffffffeff; ++ *((unsigned long *)&__m256i_op01) = 0xf7ffffffffffff1f; ++ *((unsigned long *)&__m256i_op00) = 0xbffffffffffffeff; ++ *((unsigned long *)&__m256i_op13) = 0xffffffffffff5f5c; ++ *((unsigned long *)&__m256i_op12) = 0xffffffffffff5f5c; ++ *((unsigned long *)&__m256i_op11) = 0xffffffffffff5f5c; ++ *((unsigned long *)&__m256i_op10) = 0xffffffffffff5f5c; ++ *((unsigned long *)&__m256i_result3) = 0xfff6fffefffe005b; ++ *((unsigned long *)&__m256i_result2) = 0xffbefffefffe005a; ++ *((unsigned long *)&__m256i_result1) = 0xfff6fffefffe005b; ++ *((unsigned long *)&__m256i_result0) = 0xffbefffefffe005a; ++ __m256i_out = __lasx_xvhaddw_h_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0101000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0101000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0001000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0001000000000000; ++ __m256i_out = __lasx_xvhaddw_h_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000060000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000060000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000060000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000060000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvhaddw_h_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000ffffffffffff; ++ *((unsigned long *)&__m256i_op01) = 0x8000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000ffffffffffff; ++ *((unsigned long *)&__m256i_op13) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op12) = 0x00000000ffffffff; ++ *((unsigned long *)&__m256i_op11) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op10) = 0x00000000ffffffff; ++ *((unsigned long *)&__m256i_result3) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_result2) = 0x0000fffffffefffe; ++ *((unsigned long *)&__m256i_result1) = 0xff7fffffffffffff; ++ *((unsigned long *)&__m256i_result0) = 0x0000fffffffefffe; ++ __m256i_out = __lasx_xvhaddw_h_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvhaddw_h_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000023; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000023; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000023; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000023; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000023; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000023; ++ __m256i_out = __lasx_xvhaddw_h_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000033; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000033; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvhaddw_h_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0xffff0607ffff0607; ++ *((unsigned long *)&__m256i_op02) = 0xffff0607ffff0607; ++ *((unsigned long *)&__m256i_op01) = 0xffff0607ffff0607; ++ *((unsigned long *)&__m256i_op00) = 0xffff0607ffff0607; ++ *((unsigned long *)&__m256i_op13) = 0xf9f9f9f9f9f9f9f9; ++ *((unsigned long *)&__m256i_op12) = 0xf9f9f9f9f9f9f9f9; ++ *((unsigned long *)&__m256i_op11) = 0xf9f9f9f9f9f9f9f9; ++ *((unsigned long *)&__m256i_op10) = 0xf9f9f9f9f9f9f9f9; ++ *((unsigned long *)&__m256i_result3) = 0xfff8fffffff8ffff; ++ *((unsigned long *)&__m256i_result2) = 0xfff8fffffff8ffff; ++ *((unsigned long *)&__m256i_result1) = 0xfff8fffffff8ffff; ++ *((unsigned long *)&__m256i_result0) = 0xfff8fffffff8ffff; ++ __m256i_out = __lasx_xvhaddw_h_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvhaddw_h_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out);
View file
_service:tar_scm:LoongArch-Add-tests-for-ASX-vector-xvldi-xvmskgez-xv.patch
Added
@@ -0,0 +1,2735 @@ +From 8d8564be4eaa8134acab6a184da36f3620a82f6f Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Tue, 12 Sep 2023 15:39:31 +0800 +Subject: PATCH 104/124 LoongArch: Add tests for ASX vector + xvldi/xvmskgez/xvmskltz/xvmsknz/xvmuh /xvsigncov instructions. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/vector/lasx/lasx-xvldi.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvmskgez.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvmskltz.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvmsknz.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvmuh-1.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvmuh-2.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvsigncov.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/vector/lasx/lasx-xvldi.c | 83 +++ + .../loongarch/vector/lasx/lasx-xvmskgez.c | 86 +++ + .../loongarch/vector/lasx/lasx-xvmskltz.c | 373 ++++++++++ + .../loongarch/vector/lasx/lasx-xvmsknz.c | 163 +++++ + .../loongarch/vector/lasx/lasx-xvmuh-1.c | 650 +++++++++++++++++ + .../loongarch/vector/lasx/lasx-xvmuh-2.c | 635 +++++++++++++++++ + .../loongarch/vector/lasx/lasx-xvsigncov.c | 665 ++++++++++++++++++ + 7 files changed, 2655 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvldi.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvmskgez.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvmskltz.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvmsknz.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvmuh-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvmuh-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvsigncov.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvldi.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvldi.c +new file mode 100644 +index 000000000..84b3c6599 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvldi.c +@@ -0,0 +1,83 @@ ++/* { dg-do run } */ ++/* { dg-options "-mlasx -w -fno-strict-aliasing" } */ ++#include "../simd_correctness_check.h" ++#include <lasxintrin.h> ++ ++int ++main () ++{ ++ __m256i __m256i_op0, __m256i_op1, __m256i_op2, __m256i_out, __m256i_result; ++ __m256 __m256_op0, __m256_op1, __m256_op2, __m256_out, __m256_result; ++ __m256d __m256d_op0, __m256d_op1, __m256d_op2, __m256d_out, __m256d_result; ++ ++ int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail; ++ long int long_op0, long_op1, long_op2, lont_out, lont_result; ++ long int long_int_out, long_int_result; ++ unsigned int unsigned_int_out, unsigned_int_result; ++ unsigned long int unsigned_long_int_out, unsigned_long_int_result; ++ ++ *((unsigned long *)&__m256i_result3) = 0x0000001000000010; ++ *((unsigned long *)&__m256i_result2) = 0x0000001000000010; ++ *((unsigned long *)&__m256i_result1) = 0x0000001000000010; ++ *((unsigned long *)&__m256i_result0) = 0x0000001000000010; ++ __m256i_out = __lasx_xvldi (-4080); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_result3) = 0xfebcfebcfebcfebc; ++ *((unsigned long *)&__m256i_result2) = 0xfebcfebcfebcfebc; ++ *((unsigned long *)&__m256i_result1) = 0xfebcfebcfebcfebc; ++ *((unsigned long *)&__m256i_result0) = 0xfebcfebcfebcfebc; ++ __m256i_out = __lasx_xvldi (1724); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_result3) = 0x3fd1000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x3fd1000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x3fd1000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x3fd1000000000000; ++ __m256i_out = __lasx_xvldi (-943); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_result3) = 0xff1cff1cff1cff1c; ++ *((unsigned long *)&__m256i_result2) = 0xff1cff1cff1cff1c; ++ *((unsigned long *)&__m256i_result1) = 0xff1cff1cff1cff1c; ++ *((unsigned long *)&__m256i_result0) = 0xff1cff1cff1cff1c; ++ __m256i_out = __lasx_xvldi (1820); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_result3) = 0x7200000072000000; ++ *((unsigned long *)&__m256i_result2) = 0x7200000072000000; ++ *((unsigned long *)&__m256i_result1) = 0x7200000072000000; ++ *((unsigned long *)&__m256i_result0) = 0x7200000072000000; ++ __m256i_out = __lasx_xvldi (-3214); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_result3) = 0xffffff1dffffff1d; ++ *((unsigned long *)&__m256i_result2) = 0xffffff1dffffff1d; ++ *((unsigned long *)&__m256i_result1) = 0xffffff1dffffff1d; ++ *((unsigned long *)&__m256i_result0) = 0xffffff1dffffff1d; ++ __m256i_out = __lasx_xvldi (2845); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_result3) = 0x0000001000000010; ++ *((unsigned long *)&__m256i_result2) = 0x0000001000000010; ++ *((unsigned long *)&__m256i_result1) = 0x0000001000000010; ++ *((unsigned long *)&__m256i_result0) = 0x0000001000000010; ++ __m256i_out = __lasx_xvldi (-4080); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_result3) = 0x3fd1000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x3fd1000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x3fd1000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x3fd1000000000000; ++ __m256i_out = __lasx_xvldi (-943); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_result3) = 0x7200000072000000; ++ *((unsigned long *)&__m256i_result2) = 0x7200000072000000; ++ *((unsigned long *)&__m256i_result1) = 0x7200000072000000; ++ *((unsigned long *)&__m256i_result0) = 0x7200000072000000; ++ __m256i_out = __lasx_xvldi (-3214); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ return 0; ++} +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvmskgez.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvmskgez.c +new file mode 100644 +index 000000000..15e66ae38 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvmskgez.c +@@ -0,0 +1,86 @@ ++/* { dg-do run } */ ++/* { dg-options "-mlasx -w -fno-strict-aliasing" } */ ++#include "../simd_correctness_check.h" ++#include <lasxintrin.h> ++ ++int ++main () ++{ ++ __m256i __m256i_op0, __m256i_op1, __m256i_op2, __m256i_out, __m256i_result; ++ __m256 __m256_op0, __m256_op1, __m256_op2, __m256_out, __m256_result; ++ __m256d __m256d_op0, __m256d_op1, __m256d_op2, __m256d_out, __m256d_result; ++ ++ int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail; ++ long int long_op0, long_op1, long_op2, lont_out, lont_result; ++ long int long_int_out, long_int_result; ++ unsigned int unsigned_int_out, unsigned_int_result; ++ unsigned long int unsigned_long_int_out, unsigned_long_int_result; ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x000000000000ff00; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x000000000000ff00; ++ __m256i_out = __lasx_xvmskgez_b (__m256i_op0); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x000000000000ffff; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x000000000000ffff; ++ __m256i_out = __lasx_xvmskgez_b (__m256i_op0); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op02) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op01) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op00) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvmskgez_b (__m256i_op0); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op02) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op01) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op00) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvmskgez_b (__m256i_op0); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000001ff03ff; ++ *((unsigned long *)&__m256i_op02) = 0x00000000000203ff; ++ *((unsigned long *)&__m256i_op01) = 0x0000000001ff03ff; ++ *((unsigned long *)&__m256i_op00) = 0x00000000000203ff; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x000000000000fafe; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000;
View file
_service:tar_scm:LoongArch-Add-tests-for-ASX-vector-xvmax-xvmaxi-xvmi.patch
Added
@@ -0,0 +1,4124 @@ +From 00deb43164bce9740d6e2e103afce647bebc6ee3 Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Tue, 12 Sep 2023 15:31:02 +0800 +Subject: PATCH 103/124 LoongArch: Add tests for ASX vector + xvmax/xvmaxi/xvmin/xvmini instructions. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/vector/lasx/lasx-xvmax-1.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvmax-2.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvmaxi-1.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvmaxi-2.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvmin-1.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvmin-2.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvmini-1.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvmini-2.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/vector/lasx/lasx-xvmax-1.c | 545 ++++++++++++++ + .../loongarch/vector/lasx/lasx-xvmax-2.c | 560 +++++++++++++++ + .../loongarch/vector/lasx/lasx-xvmaxi-1.c | 471 ++++++++++++ + .../loongarch/vector/lasx/lasx-xvmaxi-2.c | 504 +++++++++++++ + .../loongarch/vector/lasx/lasx-xvmin-1.c | 575 +++++++++++++++ + .../loongarch/vector/lasx/lasx-xvmin-2.c | 680 ++++++++++++++++++ + .../loongarch/vector/lasx/lasx-xvmini-1.c | 416 +++++++++++ + .../loongarch/vector/lasx/lasx-xvmini-2.c | 284 ++++++++ + 8 files changed, 4035 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvmax-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvmax-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvmaxi-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvmaxi-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvmin-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvmin-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvmini-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvmini-2.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvmax-1.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvmax-1.c +new file mode 100644 +index 000000000..96c6671f2 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvmax-1.c +@@ -0,0 +1,545 @@ ++/* { dg-do run } */ ++/* { dg-options "-mlasx -w -fno-strict-aliasing" } */ ++#include "../simd_correctness_check.h" ++#include <lasxintrin.h> ++ ++int ++main () ++{ ++ __m256i __m256i_op0, __m256i_op1, __m256i_op2, __m256i_out, __m256i_result; ++ __m256 __m256_op0, __m256_op1, __m256_op2, __m256_out, __m256_result; ++ __m256d __m256d_op0, __m256d_op1, __m256d_op2, __m256d_out, __m256d_result; ++ ++ int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail; ++ long int long_op0, long_op1, long_op2, lont_out, lont_result; ++ long int long_int_out, long_int_result; ++ unsigned int unsigned_int_out, unsigned_int_result; ++ unsigned long int unsigned_long_int_out, unsigned_long_int_result; ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x7fffffff7fffffff; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x7fffffff7fffffff; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x7f0000007f000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x7f0000007f000000; ++ __m256i_out = __lasx_xvmax_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0xffffffffe0000000; ++ *((unsigned long *)&__m256i_op02) = 0xffffffffe0000000; ++ *((unsigned long *)&__m256i_op01) = 0xffffffffe0000000; ++ *((unsigned long *)&__m256i_op00) = 0xffffffffe0000000; ++ *((unsigned long *)&__m256i_op13) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op12) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op11) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op10) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_result3) = 0xffffffffff000000; ++ *((unsigned long *)&__m256i_result2) = 0xffffffffff000000; ++ *((unsigned long *)&__m256i_result1) = 0xffffffffff000000; ++ *((unsigned long *)&__m256i_result0) = 0xffffffffff000000; ++ __m256i_out = __lasx_xvmax_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x7ff0000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x7ff0000000000000; ++ *((unsigned long *)&__m256i_op01) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op00) = 0x7ff0000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_result3) = 0x7f00000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x7fff000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x7fff000000000000; ++ __m256i_out = __lasx_xvmax_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0004000400040004; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0004000400040004; ++ __m256i_out = __lasx_xvmax_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x5980000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x5980000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x5900000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x5900000000000000; ++ __m256i_out = __lasx_xvmax_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x00ff00ff00ff00ff; ++ *((unsigned long *)&__m256i_op02) = 0x00ff00ff00ffce20; ++ *((unsigned long *)&__m256i_op01) = 0x00ff00ff00ff00ff; ++ *((unsigned long *)&__m256i_op00) = 0x00ff00ff00ffce20; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000ee1100; ++ *((unsigned long *)&__m256i_op12) = 0x0000000004560408; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000ee1100; ++ *((unsigned long *)&__m256i_op10) = 0x0000000004560408; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000ff1100; ++ *((unsigned long *)&__m256i_result2) = 0x0000000004560420; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000ff1100; ++ *((unsigned long *)&__m256i_result0) = 0x0000000004560420; ++ __m256i_out = __lasx_xvmax_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x00000001ffffffff; ++ *((unsigned long *)&__m256i_op02) = 0x00000001ffffffff; ++ *((unsigned long *)&__m256i_op01) = 0x00000001ffffffff; ++ *((unsigned long *)&__m256i_op00) = 0x00000001ffffffff; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000100000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000100000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000100000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000100000000; ++ __m256i_out = __lasx_xvmax_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000200; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000100; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000200; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000100; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000200; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000100; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000200; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000100; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000200; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000100; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000200; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000100; ++ __m256i_out = __lasx_xvmax_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x000000007f433c78; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x000000007f433c78; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x000000007f433c78; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x000000007f433c78; ++ __m256i_out = __lasx_xvmax_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0xff01ff01ff01ff01; ++ *((unsigned long *)&__m256i_op02) = 0xff01ff01ff01ff01;
View file
_service:tar_scm:LoongArch-Add-tests-for-ASX-vector-xvmul-xvmod-xvdiv.patch
Added
@@ -0,0 +1,5766 @@ +From 95ce2bef98ebcebebcdb3a9411d1c9783935ac89 Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Tue, 12 Sep 2023 15:23:35 +0800 +Subject: PATCH 102/124 LoongArch: Add tests for ASX vector xvmul/xvmod/xvdiv + instructions. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/vector/lasx/lasx-xvdiv-1.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvdiv-2.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvmod-1.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvmod-2.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvmul.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvmulwev-1.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvmulwev-2.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvmulwev-3.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvmulwod-1.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvmulwod-2.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvmulwod-3.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/vector/lasx/lasx-xvdiv-1.c | 485 ++++++++++++++ + .../loongarch/vector/lasx/lasx-xvdiv-2.c | 500 ++++++++++++++ + .../loongarch/vector/lasx/lasx-xvmod-1.c | 395 +++++++++++ + .../loongarch/vector/lasx/lasx-xvmod-2.c | 410 ++++++++++++ + .../loongarch/vector/lasx/lasx-xvmul.c | 620 ++++++++++++++++++ + .../loongarch/vector/lasx/lasx-xvmulwev-1.c | 590 +++++++++++++++++ + .../loongarch/vector/lasx/lasx-xvmulwev-2.c | 590 +++++++++++++++++ + .../loongarch/vector/lasx/lasx-xvmulwev-3.c | 605 +++++++++++++++++ + .../loongarch/vector/lasx/lasx-xvmulwod-1.c | 545 +++++++++++++++ + .../loongarch/vector/lasx/lasx-xvmulwod-2.c | 470 +++++++++++++ + .../loongarch/vector/lasx/lasx-xvmulwod-3.c | 440 +++++++++++++ + 11 files changed, 5650 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvdiv-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvdiv-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvmod-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvmod-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvmul.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvmulwev-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvmulwev-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvmulwev-3.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvmulwod-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvmulwod-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvmulwod-3.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvdiv-1.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvdiv-1.c +new file mode 100644 +index 000000000..0d7c67703 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvdiv-1.c +@@ -0,0 +1,485 @@ ++/* { dg-do run } */ ++/* { dg-options "-mlasx -w -fno-strict-aliasing" } */ ++#include "../simd_correctness_check.h" ++#include <lasxintrin.h> ++ ++int ++main () ++{ ++ __m256i __m256i_op0, __m256i_op1, __m256i_op2, __m256i_out, __m256i_result; ++ __m256 __m256_op0, __m256_op1, __m256_op2, __m256_out, __m256_result; ++ __m256d __m256d_op0, __m256d_op1, __m256d_op2, __m256d_out, __m256d_result; ++ ++ int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail; ++ long int long_op0, long_op1, long_op2, lont_out, lont_result; ++ long int long_int_out, long_int_result; ++ unsigned int unsigned_int_out, unsigned_int_result; ++ unsigned long int unsigned_long_int_out, unsigned_long_int_result; ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op12) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op11) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op10) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvdiv_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x00080000000cc916; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x000000000006fff3; ++ *((unsigned long *)&__m256i_op13) = 0xfffffffffffffffe; ++ *((unsigned long *)&__m256i_op12) = 0xfffffffefffffefc; ++ *((unsigned long *)&__m256i_op11) = 0xfffffffffffffffe; ++ *((unsigned long *)&__m256i_op10) = 0xfffffffffffffffe; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x00f8000000f41bfb; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000fa0106; ++ __m256i_out = __lasx_xvdiv_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0101010101010101; ++ *((unsigned long *)&__m256i_op12) = 0x0101010101010101; ++ *((unsigned long *)&__m256i_op11) = 0x0101010101010101; ++ *((unsigned long *)&__m256i_op10) = 0x0101010101010101; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvdiv_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000200000002; ++ *((unsigned long *)&__m256i_op02) = 0x0000000200000002; ++ *((unsigned long *)&__m256i_op01) = 0x0000000200000002; ++ *((unsigned long *)&__m256i_op00) = 0x0000000200000002; ++ *((unsigned long *)&__m256i_op13) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op12) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op11) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op10) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_result3) = 0x000000fe000000fe; ++ *((unsigned long *)&__m256i_result2) = 0x000000fe000000fe; ++ *((unsigned long *)&__m256i_result1) = 0x000000fe000000fe; ++ *((unsigned long *)&__m256i_result0) = 0x000000fe000000fe; ++ __m256i_out = __lasx_xvdiv_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x01fe01fe01fe01fe; ++ *((unsigned long *)&__m256i_op12) = 0x01fe01fe01fe01fe; ++ *((unsigned long *)&__m256i_op11) = 0x01fe01fe01fe01fe; ++ *((unsigned long *)&__m256i_op10) = 0x01fe01fe01fe01fe; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvdiv_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x01fe8001b72e0001; ++ *((unsigned long *)&__m256i_op02) = 0xb72e8001b72eaf12; ++ *((unsigned long *)&__m256i_op01) = 0x01fe000247639d9c; ++ *((unsigned long *)&__m256i_op00) = 0xb5308001b72eaf12; ++ *((unsigned long *)&__m256i_op13) = 0x00ff00ff00ff00ff; ++ *((unsigned long *)&__m256i_op12) = 0x00ff00ff017e01fe; ++ *((unsigned long *)&__m256i_op11) = 0x017e00ff017e00ff; ++ *((unsigned long *)&__m256i_op10) = 0x00ff00ff017e01fe; ++ *((unsigned long *)&__m256i_result3) = 0x0002ff80ffb70000; ++ *((unsigned long *)&__m256i_result2) = 0xffb7ff80ffd0ffd8; ++ *((unsigned long *)&__m256i_result1) = 0x00010000002fff9e; ++ *((unsigned long *)&__m256i_result0) = 0xffb5ff80ffd0ffd8; ++ __m256i_out = __lasx_xvdiv_h (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x8091811081118110; ++ *((unsigned long *)&__m256i_op02) = 0x80a6802680208015; ++ *((unsigned long *)&__m256i_op01) = 0x8091811081110013; ++ *((unsigned long *)&__m256i_op00) = 0x80a6802680200018; ++ *((unsigned long *)&__m256i_op13) = 0x8091811081118110; ++ *((unsigned long *)&__m256i_op12) = 0x80a6802680208015; ++ *((unsigned long *)&__m256i_op11) = 0x8091811081110013; ++ *((unsigned long *)&__m256i_op10) = 0x80a6802680200018; ++ *((unsigned long *)&__m256i_result3) = 0x0001000100010001; ++ *((unsigned long *)&__m256i_result2) = 0x0001000100010001; ++ *((unsigned long *)&__m256i_result1) = 0x0001000100010001; ++ *((unsigned long *)&__m256i_result0) = 0x0001000100010001; ++ __m256i_out = __lasx_xvdiv_h (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op12) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op11) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op10) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvdiv_h (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op02) = 0xe07de0801f20607a; ++ *((unsigned long *)&__m256i_op01) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op00) = 0xe07de0801f20607a; ++ *((unsigned long *)&__m256i_op13) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op12) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op11) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op10) = 0xffffffffffffffff;
View file
_service:tar_scm:LoongArch-Add-tests-for-ASX-vector-xvpackev-xvpackod.patch
Added
@@ -0,0 +1,5364 @@ +From 9789698300a07a107bf78cd1c7fb9cf8fbddfca1 Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Tue, 12 Sep 2023 17:07:28 +0800 +Subject: PATCH 119/124 LoongArch: Add tests for ASX vector + xvpackev/xvpackod/xvpickev/xvpickod/ + xvpickve2gr/xvreplgr2vr/xvreplve/xvreplve0/xvreplvei/xvshuf4i/xvshuf + instructions. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/vector/lasx/lasx-xvpackev.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvpackod.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvpickev.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvpickod.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvpickve.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvpickve2gr.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvreplgr2vr.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvreplve.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvreplve0.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvreplvei.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvshuf4i_b.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvshuf_b.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/vector/lasx/lasx-xvpackev.c | 501 ++++++++++++ + .../loongarch/vector/lasx/lasx-xvpackod.c | 575 +++++++++++++ + .../loongarch/vector/lasx/lasx-xvpickev.c | 515 ++++++++++++ + .../loongarch/vector/lasx/lasx-xvpickod.c | 530 ++++++++++++ + .../loongarch/vector/lasx/lasx-xvpickve.c | 130 +++ + .../loongarch/vector/lasx/lasx-xvpickve2gr.c | 388 +++++++++ + .../loongarch/vector/lasx/lasx-xvreplgr2vr.c | 380 +++++++++ + .../loongarch/vector/lasx/lasx-xvreplve.c | 536 ++++++++++++ + .../loongarch/vector/lasx/lasx-xvreplve0.c | 471 +++++++++++ + .../loongarch/vector/lasx/lasx-xvreplvei.c | 20 + + .../loongarch/vector/lasx/lasx-xvshuf4i_b.c | 430 ++++++++++ + .../loongarch/vector/lasx/lasx-xvshuf_b.c | 761 ++++++++++++++++++ + 12 files changed, 5237 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvpackev.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvpackod.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvpickev.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvpickod.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvpickve.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvpickve2gr.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvreplgr2vr.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvreplve.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvreplve0.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvreplvei.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvshuf4i_b.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvshuf_b.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvpackev.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvpackev.c +new file mode 100644 +index 000000000..33b96d657 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvpackev.c +@@ -0,0 +1,501 @@ ++/* { dg-do run } */ ++/* { dg-options "-mlasx -w -fno-strict-aliasing" } */ ++#include "../simd_correctness_check.h" ++#include <lasxintrin.h> ++ ++int ++main () ++{ ++ __m256i __m256i_op0, __m256i_op1, __m256i_op2, __m256i_out, __m256i_result; ++ __m256 __m256_op0, __m256_op1, __m256_op2, __m256_out, __m256_result; ++ __m256d __m256d_op0, __m256d_op1, __m256d_op2, __m256d_out, __m256d_result; ++ ++ int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail; ++ long int long_op0, long_op1, long_op2, lont_out, lont_result; ++ long int long_int_out, long_int_result; ++ unsigned int unsigned_int_out, unsigned_int_result; ++ unsigned long int unsigned_long_int_out, unsigned_long_int_result; ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x81f7f2599f0509c2; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x51136d3c78388916; ++ *((unsigned long *)&__m256i_op13) = 0x044819410d87e69a; ++ *((unsigned long *)&__m256i_op12) = 0x21d3905ae3e93be0; ++ *((unsigned long *)&__m256i_op11) = 0x5125883a30da0f20; ++ *((unsigned long *)&__m256i_op10) = 0x6d7b2d3ac2777aeb; ++ *((unsigned long *)&__m256i_result3) = 0x000019410000e69a; ++ *((unsigned long *)&__m256i_result2) = 0xf259905a09c23be0; ++ *((unsigned long *)&__m256i_result1) = 0x0000883a00000f20; ++ *((unsigned long *)&__m256i_result0) = 0x6d3c2d3a89167aeb; ++ __m256i_out = __lasx_xvpackev_h (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x4f8000004f800000; ++ *((unsigned long *)&__m256i_op02) = 0x4f7fffbf0000fe00; ++ *((unsigned long *)&__m256i_op01) = 0x000000004f800000; ++ *((unsigned long *)&__m256i_op00) = 0x4f7fffe64f7fffc0; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0xfe02fe02fee5fe22; ++ *((unsigned long *)&__m256i_op10) = 0xff49fe4200000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0xffbf0000fe000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000fe020000fe22; ++ *((unsigned long *)&__m256i_result0) = 0xffe6fe42ffc00000; ++ __m256i_out = __lasx_xvpackev_h (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x000000000000ffff; ++ *((unsigned long *)&__m256i_op02) = 0x000000000000ff80; ++ *((unsigned long *)&__m256i_op01) = 0x0000ffff0000ffff; ++ *((unsigned long *)&__m256i_op00) = 0x000000000000ffff; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x000000000000ff80; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x000000000000ffff; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvpackev_d (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op02) = 0xc06500550055ffab; ++ *((unsigned long *)&__m256i_op01) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op00) = 0xc06500550055ffab; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000001; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000001; ++ *((unsigned long *)&__m256i_result3) = 0xffff0000ffff0000; ++ *((unsigned long *)&__m256i_result2) = 0x00550000ffab0001; ++ *((unsigned long *)&__m256i_result1) = 0xffff0000ffff0000; ++ *((unsigned long *)&__m256i_result0) = 0x00550000ffab0001; ++ __m256i_out = __lasx_xvpackev_h (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000001000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000001000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000001000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000001000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000401000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000401000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000401000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000401000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000400000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000400000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000400000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000400000000; ++ __m256i_out = __lasx_xvpackev_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0xff00000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0xff00000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x7fffffffffffffff; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x7fffffffffffffff; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000ffff0000ffff; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000ffff0000ffff; ++ __m256i_out = __lasx_xvpackev_h (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x01fe01fe01fe01fe; ++ *((unsigned long *)&__m256i_op12) = 0x01fe01fe01fe01fe; ++ *((unsigned long *)&__m256i_op11) = 0x01fe01fe01fe01fe; ++ *((unsigned long *)&__m256i_op10) = 0x01fe01fe00000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x01fe01fe01fe01fe; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x01fe01fe00000000; ++ __m256i_out = __lasx_xvpackev_d (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvpackev_w (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x00000000ffffffff; ++ *((unsigned long *)&__m256i_op02) = 0x00000000ffffffff; ++ *((unsigned long *)&__m256i_op01) = 0x00000000ffffffff;
View file
_service:tar_scm:LoongArch-Add-tests-for-ASX-vector-xvsll-xvsrl-instr.patch
Added
@@ -0,0 +1,5611 @@ +From e90910ab68c43259f898fb7b2cba02d4eb457428 Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Tue, 12 Sep 2023 15:44:49 +0800 +Subject: PATCH 106/124 LoongArch: Add tests for ASX vector xvsll/xvsrl + instructions. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/vector/lasx/lasx-xvsll.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvslli.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvsllwil-1.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvsllwil-2.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvsrl.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvsrli.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvsrln.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvsrlni.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvsrlr.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvsrlri.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvsrlrn.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvsrlrni.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/vector/lasx/lasx-xvsll.c | 425 +++++++++++ + .../loongarch/vector/lasx/lasx-xvslli.c | 416 +++++++++++ + .../loongarch/vector/lasx/lasx-xvsllwil-1.c | 339 +++++++++ + .../loongarch/vector/lasx/lasx-xvsllwil-2.c | 350 +++++++++ + .../loongarch/vector/lasx/lasx-xvsrl.c | 650 +++++++++++++++++ + .../loongarch/vector/lasx/lasx-xvsrli.c | 405 +++++++++++ + .../loongarch/vector/lasx/lasx-xvsrln.c | 425 +++++++++++ + .../loongarch/vector/lasx/lasx-xvsrlni.c | 680 ++++++++++++++++++ + .../loongarch/vector/lasx/lasx-xvsrlr.c | 515 +++++++++++++ + .../loongarch/vector/lasx/lasx-xvsrlri.c | 416 +++++++++++ + .../loongarch/vector/lasx/lasx-xvsrlrn.c | 410 +++++++++++ + .../loongarch/vector/lasx/lasx-xvsrlrni.c | 455 ++++++++++++ + 12 files changed, 5486 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvsll.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvslli.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvsllwil-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvsllwil-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvsrl.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvsrli.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvsrln.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvsrlni.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvsrlr.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvsrlri.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvsrlrn.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvsrlrni.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvsll.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvsll.c +new file mode 100644 +index 000000000..7179e715c +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvsll.c +@@ -0,0 +1,425 @@ ++/* { dg-do run } */ ++/* { dg-options "-mlasx -w -fno-strict-aliasing" } */ ++#include "../simd_correctness_check.h" ++#include <lasxintrin.h> ++ ++int ++main () ++{ ++ __m256i __m256i_op0, __m256i_op1, __m256i_op2, __m256i_out, __m256i_result; ++ __m256 __m256_op0, __m256_op1, __m256_op2, __m256_out, __m256_result; ++ __m256d __m256d_op0, __m256d_op1, __m256d_op2, __m256d_out, __m256d_result; ++ ++ int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail; ++ long int long_op0, long_op1, long_op2, lont_out, lont_result; ++ long int long_int_out, long_int_result; ++ unsigned int unsigned_int_out, unsigned_int_result; ++ unsigned long int unsigned_long_int_out, unsigned_long_int_result; ++ ++ *((unsigned long *)&__m256i_op03) = 0x00000000ffffffff; ++ *((unsigned long *)&__m256i_op02) = 0x00000000ffffffff; ++ *((unsigned long *)&__m256i_op01) = 0x00000000ffffffff; ++ *((unsigned long *)&__m256i_op00) = 0xffffffff00000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x00000000ffffffff; ++ *((unsigned long *)&__m256i_result2) = 0x00000000ffffffff; ++ *((unsigned long *)&__m256i_result1) = 0x00000000ffffffff; ++ *((unsigned long *)&__m256i_result0) = 0xffffffff00000000; ++ __m256i_out = __lasx_xvsll_w (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x00001f41ffffbf00; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x00001f41ffffbf00; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvsll_d (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvsll_w (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0xffffffffe0000000; ++ *((unsigned long *)&__m256i_op02) = 0xffffffffe0000000; ++ *((unsigned long *)&__m256i_op01) = 0xffffffffe0000000; ++ *((unsigned long *)&__m256i_op00) = 0xffffffffe0000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0xffffffffe0000000; ++ *((unsigned long *)&__m256i_result2) = 0xffffffffe0000000; ++ *((unsigned long *)&__m256i_result1) = 0xffffffffe0000000; ++ *((unsigned long *)&__m256i_result0) = 0xffffffffe0000000; ++ __m256i_out = __lasx_xvsll_w (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvsll_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x7f00000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x7fff000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x7fff000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvsll_h (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000fffefe; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000fffefe; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000808080; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvsll_b (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0xfffffefefffffefe; ++ *((unsigned long *)&__m256i_op02) = 0xfffffefefffffcfa; ++ *((unsigned long *)&__m256i_op01) = 0xfffffefefffffefe; ++ *((unsigned long *)&__m256i_op00) = 0xfffffefefffffefe; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_result3) = 0xfffffefefffffefe; ++ *((unsigned long *)&__m256i_result2) = 0xfffffefefffffcfa; ++ *((unsigned long *)&__m256i_result1) = 0xfffffefefffffefe; ++ *((unsigned long *)&__m256i_result0) = 0x8000000080000000; ++ __m256i_out = __lasx_xvsll_h (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x7fffffff7fffffff; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x000000007fffffff; ++ *((unsigned long *)&__m256i_op13) = 0xfff2f7bcfff2f7bd;
View file
_service:tar_scm:LoongArch-Add-tests-for-ASX-vector-xvssran-xvssrani-.patch
Added
@@ -0,0 +1,4258 @@ +From 445ae07ab55a647f7aec97c2334fb276a44f2af1 Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Wed, 13 Sep 2023 12:37:41 +0800 +Subject: PATCH 121/124 LoongArch: Add tests for ASX vector + xvssran/xvssrani/xvssrarn/xvssrarni instructions. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/vector/lasx/lasx-xvssran.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvssrani.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvssrarn.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvssrarni.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/vector/lasx/lasx-xvssran.c | 905 ++++++++++++ + .../loongarch/vector/lasx/lasx-xvssrani.c | 1235 +++++++++++++++++ + .../loongarch/vector/lasx/lasx-xvssrarn.c | 905 ++++++++++++ + .../loongarch/vector/lasx/lasx-xvssrarni.c | 1160 ++++++++++++++++ + 4 files changed, 4205 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvssran.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvssrani.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvssrarn.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvssrarni.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvssran.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvssran.c +new file mode 100644 +index 000000000..fdb0c25f1 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvssran.c +@@ -0,0 +1,905 @@ ++/* { dg-do run } */ ++/* { dg-options "-mlasx -w -fno-strict-aliasing" } */ ++#include "../simd_correctness_check.h" ++#include <lasxintrin.h> ++ ++int ++main () ++{ ++ __m256i __m256i_op0, __m256i_op1, __m256i_op2, __m256i_out, __m256i_result; ++ __m256 __m256_op0, __m256_op1, __m256_op2, __m256_out, __m256_result; ++ __m256d __m256d_op0, __m256d_op1, __m256d_op2, __m256d_out, __m256d_result; ++ ++ int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail; ++ long int long_op0, long_op1, long_op2, lont_out, lont_result; ++ long int long_int_out, long_int_result; ++ unsigned int unsigned_int_out, unsigned_int_result; ++ unsigned long int unsigned_long_int_out, unsigned_long_int_result; ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x00007ffe81fdfe03; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x7ffe800000000000; ++ __m256i_out = __lasx_xvssran_h_w (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvssran_wu_d (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvssran_b_h (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvssran_wu_d (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0xffffffefffffffef; ++ *((unsigned long *)&__m256i_op02) = 0xffffffef000004ea; ++ *((unsigned long *)&__m256i_op01) = 0xffffffefffffffef; ++ *((unsigned long *)&__m256i_op00) = 0xffffffefffffffef; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x00000000000000ff; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvssran_bu_h (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x1717171717171717; ++ *((unsigned long *)&__m256i_op02) = 0x000607f700000001; ++ *((unsigned long *)&__m256i_op01) = 0x1717171717171717; ++ *((unsigned long *)&__m256i_op00) = 0x000607f700000001; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op10) = 0xfffffffffffffe81; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x7fffffff7fffffff; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x000000007fffffff; ++ __m256i_out = __lasx_xvssran_w_d (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x00f9f90079f9f9f9; ++ *((unsigned long *)&__m256i_op12) = 0x79f9f9f900000000; ++ *((unsigned long *)&__m256i_op11) = 0x00f9f90079f9f9f9; ++ *((unsigned long *)&__m256i_op10) = 0x79f9f9f900000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvssran_w_d (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000007f7f; ++ *((unsigned long *)&__m256i_op02) = 0x00000000007f7f7f; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000007f7f; ++ *((unsigned long *)&__m256i_op00) = 0x000000007f007f78; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x000000000033007e; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000021; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x00007f7f00000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x00007f7f00007fff; ++ __m256i_out = __lasx_xvssran_h_w (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0xfff0000000000000; ++ *((unsigned long *)&__m256i_op02) = 0xfff0000000000080; ++ *((unsigned long *)&__m256i_op01) = 0xfff0000000000000; ++ *((unsigned long *)&__m256i_op00) = 0xfff0000000000080; ++ *((unsigned long *)&__m256i_op13) = 0xfff0000000000000; ++ *((unsigned long *)&__m256i_op12) = 0xfff0000000000000; ++ *((unsigned long *)&__m256i_op11) = 0xfff0000000000000; ++ *((unsigned long *)&__m256i_op10) = 0xfff0000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x8000000080000080; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x8000000080000080; ++ __m256i_out = __lasx_xvssran_h_w (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x00000000000000ff; ++ *((unsigned long *)&__m256i_op02) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op01) = 0x00000000000000ff; ++ *((unsigned long *)&__m256i_op00) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x000000ff00000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x000000ff00000000; ++ __m256i_out = __lasx_xvssran_wu_d (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out);
View file
_service:tar_scm:LoongArch-Add-tests-for-ASX-vector-xvssrln-xvssrlni-.patch
Added
@@ -0,0 +1,4123 @@ +From 983fd43b599dd252bc7f869be27bf1677f8eeca7 Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Wed, 13 Sep 2023 12:35:41 +0800 +Subject: PATCH 120/124 LoongArch: Add tests for ASX vector + xvssrln/xvssrlni/xvssrlrn/xvssrlrni instructions. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/vector/lasx/lasx-xvssrln.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvssrlni.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvssrlrn.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvssrlrni.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/vector/lasx/lasx-xvssrln.c | 965 ++++++++++++++ + .../loongarch/vector/lasx/lasx-xvssrlni.c | 1130 ++++++++++++++++ + .../loongarch/vector/lasx/lasx-xvssrlrn.c | 815 ++++++++++++ + .../loongarch/vector/lasx/lasx-xvssrlrni.c | 1160 +++++++++++++++++ + 4 files changed, 4070 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvssrln.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvssrlni.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvssrlrn.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvssrlrni.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvssrln.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvssrln.c +new file mode 100644 +index 000000000..356eb2182 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvssrln.c +@@ -0,0 +1,965 @@ ++/* { dg-do run } */ ++/* { dg-options "-mlasx -w -fno-strict-aliasing" } */ ++#include "../simd_correctness_check.h" ++#include <lasxintrin.h> ++ ++int ++main () ++{ ++ __m256i __m256i_op0, __m256i_op1, __m256i_op2, __m256i_out, __m256i_result; ++ __m256 __m256_op0, __m256_op1, __m256_op2, __m256_out, __m256_result; ++ __m256d __m256d_op0, __m256d_op1, __m256d_op2, __m256d_out, __m256d_result; ++ ++ int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail; ++ long int long_op0, long_op1, long_op2, lont_out, lont_result; ++ long int long_int_out, long_int_result; ++ unsigned int unsigned_int_out, unsigned_int_result; ++ unsigned long int unsigned_long_int_out, unsigned_long_int_result; ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x44bb2cd3a35c2fd0; ++ *((unsigned long *)&__m256i_op00) = 0xca355ba46a95e31c; ++ *((unsigned long *)&__m256i_op13) = 0x000100ab000500a0; ++ *((unsigned long *)&__m256i_op12) = 0x000200b800080124; ++ *((unsigned long *)&__m256i_op11) = 0x0001011b000200aa; ++ *((unsigned long *)&__m256i_op10) = 0x00150118008f0091; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x7f057f0b7f5b007f; ++ __m256i_out = __lasx_xvssrln_b_h (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x00000000ffffffff; ++ *((unsigned long *)&__m256i_op02) = 0x00000000ffffffff; ++ *((unsigned long *)&__m256i_op01) = 0x00000000ffffffff; ++ *((unsigned long *)&__m256i_op00) = 0xffffffff00000000; ++ *((unsigned long *)&__m256i_op13) = 0x00000000ffffffff; ++ *((unsigned long *)&__m256i_op12) = 0x00000000ffffffff; ++ *((unsigned long *)&__m256i_op11) = 0x00000000ffffffff; ++ *((unsigned long *)&__m256i_op10) = 0xffffffff00000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x000000007fffffff; ++ __m256i_out = __lasx_xvssrln_w_d (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000020000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000020000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000007; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000ffff0000ffff; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvssrln_hu_w (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000007f00; ++ *((unsigned long *)&__m256i_op02) = 0x7fff7ffe7fffeffe; ++ *((unsigned long *)&__m256i_op01) = 0xffffd84900000849; ++ *((unsigned long *)&__m256i_op00) = 0x07fffc670800f086; ++ *((unsigned long *)&__m256i_op13) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op12) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op11) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op10) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000100000000; ++ __m256i_out = __lasx_xvssrln_w_d (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvssrln_bu_h (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op13) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op12) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op11) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_op10) = 0xffffffffffffffff; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000000000000; ++ __m256i_out = __lasx_xvssrln_hu_w (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x000000017ffffffe; ++ *((unsigned long *)&__m256i_op02) = 0x000000017ffffffe; ++ *((unsigned long *)&__m256i_op01) = 0x000000017ffffffe; ++ *((unsigned long *)&__m256i_op00) = 0x000000017ffffffe; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0xfffffff0ffff0000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0xfffffff0ffff0000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x7fffffff7fffffff; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x7fffffff7fffffff; ++ __m256i_out = __lasx_xvssrln_w_d (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000017000000080; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0x0000017000000080; ++ *((unsigned long *)&__m256i_op13) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op12) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000001700080; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x0000000001700080; ++ __m256i_out = __lasx_xvssrln_h_w (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x2000200020002000; ++ *((unsigned long *)&__m256i_op02) = 0x2000200020002000; ++ *((unsigned long *)&__m256i_op01) = 0x2000200020002000; ++ *((unsigned long *)&__m256i_op00) = 0x2000200020002000; ++ *((unsigned long *)&__m256i_op13) = 0x0101010101010101; ++ *((unsigned long *)&__m256i_op12) = 0x0101010101010101; ++ *((unsigned long *)&__m256i_op11) = 0x0101010101010101; ++ *((unsigned long *)&__m256i_op10) = 0x0101010101010101; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x7f7f7f7f7f7f7f7f; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x7f7f7f7f7f7f7f7f; ++ __m256i_out = __lasx_xvssrln_b_h (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); ++ ++ *((unsigned long *)&__m256i_op03) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op02) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_op00) = 0xfffffffffffbfffc; ++ *((unsigned long *)&__m256i_op13) = 0x00000000ffffffff; ++ *((unsigned long *)&__m256i_op12) = 0x00000000ffff8c80; ++ *((unsigned long *)&__m256i_op11) = 0x00000000ffffffff; ++ *((unsigned long *)&__m256i_op10) = 0x00000000fff0e400; ++ *((unsigned long *)&__m256i_result3) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result2) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m256i_result0) = 0x00000000ffffffff; ++ __m256i_out = __lasx_xvssrln_wu_d (__m256i_op0, __m256i_op1); ++ ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out);
View file
_service:tar_scm:LoongArch-Add-tests-for-ASX-xvldrepl-xvstelm-instruc.patch
Added
@@ -0,0 +1,65 @@ +From 2ef90d604d7bae207d5b2067b4ce38d04d4835be Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Tue, 12 Sep 2023 16:00:48 +0800 +Subject: PATCH 110/124 LoongArch: Add tests for ASX xvldrepl/xvstelm + instruction generation. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/vector/lasx/lasx-xvldrepl.c: New test. + * gcc.target/loongarch/vector/lasx/lasx-xvstelm.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/vector/lasx/lasx-xvldrepl.c | 16 ++++++++++++++++ + .../loongarch/vector/lasx/lasx-xvstelm.c | 14 ++++++++++++++ + 2 files changed, 30 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvldrepl.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvstelm.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvldrepl.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvldrepl.c +new file mode 100644 +index 000000000..105567951 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvldrepl.c +@@ -0,0 +1,16 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O3 -mlasx" } */ ++/* { dg-final { scan-assembler-times "xvldrepl.w" 2} } */ ++ ++#define N 258 ++ ++float aN, bN, cN; ++ ++void ++test () ++{ ++ for (int i = 0; i < 256; i++) ++ { ++ ai = c0 * bi + c1; ++ } ++} +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvstelm.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvstelm.c +new file mode 100644 +index 000000000..1a7b0e86f +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvstelm.c +@@ -0,0 +1,14 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O3 -mlasx" } */ ++/* { dg-final { scan-assembler-times "xvstelm.w" 8} } */ ++ ++#define LEN 256 ++ ++float aLEN, bLEN, cLEN; ++ ++void ++test () ++{ ++ for (int i = 0; i < LEN; i += 2) ++ ai = bi + ci; ++} +-- +2.33.0 +
View file
_service:tar_scm:LoongArch-Add-tests-for-Loongson-SX-builtin-function.patch
Added
@@ -0,0 +1,4354 @@ +From 1e9d9ec99e65201d8d926fddc89b6176abe9a4e6 Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Mon, 11 Sep 2023 09:38:42 +0800 +Subject: PATCH 078/124 LoongArch: Add tests for Loongson SX builtin + functions. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/vector/lsx/lsx-builtin.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/vector/lsx/lsx-builtin.c | 4328 +++++++++++++++++ + 1 file changed, 4328 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-builtin.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-builtin.c b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-builtin.c +new file mode 100644 +index 000000000..13013114d +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-builtin.c +@@ -0,0 +1,4328 @@ ++/* Test builtins for LOONGARCH LSX ASE instructions */ ++/* { dg-do compile } */ ++/* { dg-options "-mlsx" } */ ++/* { dg-final { scan-assembler-times "lsx_vsll_b:.*vsll\\.b.*lsx_vsll_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsll_h:.*vsll\\.h.*lsx_vsll_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsll_w:.*vsll\\.w.*lsx_vsll_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsll_d:.*vsll\\.d.*lsx_vsll_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vslli_b:.*vslli\\.b.*lsx_vslli_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vslli_h:.*vslli\\.h.*lsx_vslli_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vslli_w:.*vslli\\.w.*lsx_vslli_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vslli_d:.*vslli\\.d.*lsx_vslli_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsra_b:.*vsra\\.b.*lsx_vsra_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsra_h:.*vsra\\.h.*lsx_vsra_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsra_w:.*vsra\\.w.*lsx_vsra_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsra_d:.*vsra\\.d.*lsx_vsra_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsrai_b:.*vsrai\\.b.*lsx_vsrai_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsrai_h:.*vsrai\\.h.*lsx_vsrai_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsrai_w:.*vsrai\\.w.*lsx_vsrai_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsrai_d:.*vsrai\\.d.*lsx_vsrai_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsrar_b:.*vsrar\\.b.*lsx_vsrar_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsrar_h:.*vsrar\\.h.*lsx_vsrar_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsrar_w:.*vsrar\\.w.*lsx_vsrar_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsrar_d:.*vsrar\\.d.*lsx_vsrar_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsrari_b:.*vsrari\\.b.*lsx_vsrari_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsrari_h:.*vsrari\\.h.*lsx_vsrari_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsrari_w:.*vsrari\\.w.*lsx_vsrari_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsrari_d:.*vsrari\\.d.*lsx_vsrari_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsrl_b:.*vsrl\\.b.*lsx_vsrl_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsrl_h:.*vsrl\\.h.*lsx_vsrl_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsrl_w:.*vsrl\\.w.*lsx_vsrl_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsrl_d:.*vsrl\\.d.*lsx_vsrl_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsrli_b:.*vsrli\\.b.*lsx_vsrli_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsrli_h:.*vsrli\\.h.*lsx_vsrli_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsrli_w:.*vsrli\\.w.*lsx_vsrli_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsrli_d:.*vsrli\\.d.*lsx_vsrli_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsrlr_b:.*vsrlr\\.b.*lsx_vsrlr_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsrlr_h:.*vsrlr\\.h.*lsx_vsrlr_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsrlr_w:.*vsrlr\\.w.*lsx_vsrlr_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsrlr_d:.*vsrlr\\.d.*lsx_vsrlr_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsrlri_b:.*vsrlri\\.b.*lsx_vsrlri_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsrlri_h:.*vsrlri\\.h.*lsx_vsrlri_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsrlri_w:.*vsrlri\\.w.*lsx_vsrlri_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsrlri_d:.*vsrlri\\.d.*lsx_vsrlri_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vbitclr_b:.*vbitclr\\.b.*lsx_vbitclr_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vbitclr_h:.*vbitclr\\.h.*lsx_vbitclr_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vbitclr_w:.*vbitclr\\.w.*lsx_vbitclr_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vbitclr_d:.*vbitclr\\.d.*lsx_vbitclr_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vbitclri_b:.*vbitclri\\.b.*lsx_vbitclri_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vbitclri_h:.*vbitclri\\.h.*lsx_vbitclri_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vbitclri_w:.*vbitclri\\.w.*lsx_vbitclri_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vbitclri_d:.*vbitclri\\.d.*lsx_vbitclri_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vbitset_b:.*vbitset\\.b.*lsx_vbitset_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vbitset_h:.*vbitset\\.h.*lsx_vbitset_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vbitset_w:.*vbitset\\.w.*lsx_vbitset_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vbitset_d:.*vbitset\\.d.*lsx_vbitset_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vbitseti_b:.*vbitseti\\.b.*lsx_vbitseti_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vbitseti_h:.*vbitseti\\.h.*lsx_vbitseti_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vbitseti_w:.*vbitseti\\.w.*lsx_vbitseti_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vbitseti_d:.*vbitseti\\.d.*lsx_vbitseti_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vbitrev_b:.*vbitrev\\.b.*lsx_vbitrev_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vbitrev_h:.*vbitrev\\.h.*lsx_vbitrev_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vbitrev_w:.*vbitrev\\.w.*lsx_vbitrev_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vbitrev_d:.*vbitrev\\.d.*lsx_vbitrev_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vbitrevi_b:.*vbitrevi\\.b.*lsx_vbitrevi_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vbitrevi_h:.*vbitrevi\\.h.*lsx_vbitrevi_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vbitrevi_w:.*vbitrevi\\.w.*lsx_vbitrevi_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vbitrevi_d:.*vbitrevi\\.d.*lsx_vbitrevi_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vadd_b:.*vadd\\.b.*lsx_vadd_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vadd_h:.*vadd\\.h.*lsx_vadd_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vadd_w:.*vadd\\.w.*lsx_vadd_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vadd_d:.*vadd\\.d.*lsx_vadd_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vaddi_bu:.*vaddi\\.bu.*lsx_vaddi_bu" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vaddi_hu:.*vaddi\\.hu.*lsx_vaddi_hu" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vaddi_wu:.*vaddi\\.wu.*lsx_vaddi_wu" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vaddi_du:.*vaddi\\.du.*lsx_vaddi_du" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsub_b:.*vsub\\.b.*lsx_vsub_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsub_h:.*vsub\\.h.*lsx_vsub_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsub_w:.*vsub\\.w.*lsx_vsub_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsub_d:.*vsub\\.d.*lsx_vsub_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsubi_bu:.*vsubi\\.bu.*lsx_vsubi_bu" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsubi_hu:.*vsubi\\.hu.*lsx_vsubi_hu" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsubi_wu:.*vsubi\\.wu.*lsx_vsubi_wu" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsubi_du:.*vsubi\\.du.*lsx_vsubi_du" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vmax_b:.*vmax\\.b.*lsx_vmax_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vmax_h:.*vmax\\.h.*lsx_vmax_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vmax_w:.*vmax\\.w.*lsx_vmax_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vmax_d:.*vmax\\.d.*lsx_vmax_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vmaxi_b:.*vmaxi\\.b.*lsx_vmaxi_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vmaxi_h:.*vmaxi\\.h.*lsx_vmaxi_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vmaxi_w:.*vmaxi\\.w.*lsx_vmaxi_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vmaxi_d:.*vmaxi\\.d.*lsx_vmaxi_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vmax_bu:.*vmax\\.bu.*lsx_vmax_bu" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vmax_hu:.*vmax\\.hu.*lsx_vmax_hu" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vmax_wu:.*vmax\\.wu.*lsx_vmax_wu" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vmax_du:.*vmax\\.du.*lsx_vmax_du" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vmaxi_bu:.*vmaxi\\.bu.*lsx_vmaxi_bu" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vmaxi_hu:.*vmaxi\\.hu.*lsx_vmaxi_hu" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vmaxi_wu:.*vmaxi\\.wu.*lsx_vmaxi_wu" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vmaxi_du:.*vmaxi\\.du.*lsx_vmaxi_du" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vmin_b:.*vmin\\.b.*lsx_vmin_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vmin_h:.*vmin\\.h.*lsx_vmin_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vmin_w:.*vmin\\.w.*lsx_vmin_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vmin_d:.*vmin\\.d.*lsx_vmin_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vmini_b:.*vmini\\.b.*lsx_vmini_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vmini_h:.*vmini\\.h.*lsx_vmini_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vmini_w:.*vmini\\.w.*lsx_vmini_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vmini_d:.*vmini\\.d.*lsx_vmini_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vmin_bu:.*vmin\\.bu.*lsx_vmin_bu" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vmin_hu:.*vmin\\.hu.*lsx_vmin_hu" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vmin_wu:.*vmin\\.wu.*lsx_vmin_wu" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vmin_du:.*vmin\\.du.*lsx_vmin_du" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vmini_bu:.*vmini\\.bu.*lsx_vmini_bu" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vmini_hu:.*vmini\\.hu.*lsx_vmini_hu" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vmini_wu:.*vmini\\.wu.*lsx_vmini_wu" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vmini_du:.*vmini\\.du.*lsx_vmini_du" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vseq_b:.*vseq\\.b.*lsx_vseq_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vseq_h:.*vseq\\.h.*lsx_vseq_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vseq_w:.*vseq\\.w.*lsx_vseq_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vseq_d:.*vseq\\.d.*lsx_vseq_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vseqi_b:.*vseqi\\.b.*lsx_vseqi_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vseqi_h:.*vseqi\\.h.*lsx_vseqi_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vseqi_w:.*vseqi\\.w.*lsx_vseqi_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vseqi_d:.*vseqi\\.d.*lsx_vseqi_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vslti_b:.*vslti\\.b.*lsx_vslti_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vslt_b:.*vslt\\.b.*lsx_vslt_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vslt_h:.*vslt\\.h.*lsx_vslt_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vslt_w:.*vslt\\.w.*lsx_vslt_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vslt_d:.*vslt\\.d.*lsx_vslt_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vslti_h:.*vslti\\.h.*lsx_vslti_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vslti_w:.*vslti\\.w.*lsx_vslti_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vslti_d:.*vslti\\.d.*lsx_vslti_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vslt_bu:.*vslt\\.bu.*lsx_vslt_bu" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vslt_hu:.*vslt\\.hu.*lsx_vslt_hu" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vslt_wu:.*vslt\\.wu.*lsx_vslt_wu" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vslt_du:.*vslt\\.du.*lsx_vslt_du" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vslti_bu:.*vslti\\.bu.*lsx_vslti_bu" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vslti_hu:.*vslti\\.hu.*lsx_vslti_hu" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vslti_wu:.*vslti\\.wu.*lsx_vslti_wu" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vslti_du:.*vslti\\.du.*lsx_vslti_du" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsle_b:.*vsle\\.b.*lsx_vsle_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsle_h:.*vsle\\.h.*lsx_vsle_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsle_w:.*vsle\\.w.*lsx_vsle_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsle_d:.*vsle\\.d.*lsx_vsle_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vslei_b:.*vslei\\.b.*lsx_vslei_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vslei_h:.*vslei\\.h.*lsx_vslei_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vslei_w:.*vslei\\.w.*lsx_vslei_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vslei_d:.*vslei\\.d.*lsx_vslei_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsle_bu:.*vsle\\.bu.*lsx_vsle_bu" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsle_hu:.*vsle\\.hu.*lsx_vsle_hu" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsle_wu:.*vsle\\.wu.*lsx_vsle_wu" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsle_du:.*vsle\\.du.*lsx_vsle_du" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vslei_bu:.*vslei\\.bu.*lsx_vslei_bu" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vslei_hu:.*vslei\\.hu.*lsx_vslei_hu" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vslei_wu:.*vslei\\.wu.*lsx_vslei_wu" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vslei_du:.*vslei\\.du.*lsx_vslei_du" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsat_b:.*vsat\\.b.*lsx_vsat_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsat_h:.*vsat\\.h.*lsx_vsat_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsat_w:.*vsat\\.w.*lsx_vsat_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsat_d:.*vsat\\.d.*lsx_vsat_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsat_bu:.*vsat\\.bu.*lsx_vsat_bu" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsat_hu:.*vsat\\.hu.*lsx_vsat_hu" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsat_wu:.*vsat\\.wu.*lsx_vsat_wu" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsat_du:.*vsat\\.du.*lsx_vsat_du" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vadda_b:.*vadda\\.b.*lsx_vadda_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vadda_h:.*vadda\\.h.*lsx_vadda_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vadda_w:.*vadda\\.w.*lsx_vadda_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vadda_d:.*vadda\\.d.*lsx_vadda_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsadd_b:.*vsadd\\.b.*lsx_vsadd_b" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsadd_h:.*vsadd\\.h.*lsx_vsadd_h" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsadd_w:.*vsadd\\.w.*lsx_vsadd_w" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsadd_d:.*vsadd\\.d.*lsx_vsadd_d" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsadd_bu:.*vsadd\\.bu.*lsx_vsadd_bu" 1 } } */ ++/* { dg-final { scan-assembler-times "lsx_vsadd_hu:.*vsadd\\.hu.*lsx_vsadd_hu" 1 } } */
View file
_service:tar_scm:LoongArch-Add-tests-for-SX-vector-addition-instructi.patch
Added
@@ -0,0 +1,7181 @@ +From 2cb3122527add8fee54dca91824d82a02d5602e3 Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Mon, 11 Sep 2023 09:58:48 +0800 +Subject: PATCH 080/124 LoongArch: Add tests for SX vector addition + instructions. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/vector/lsx/lsx-vadd.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vadda.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vaddi.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vaddwev-1.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vaddwev-2.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vaddwev-3.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vaddwod-1.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vaddwod-2.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vaddwod-3.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vhaddw-1.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vhaddw-2.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vmadd.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vmaddwev-1.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vmaddwev-2.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vmaddwev-3.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vmaddwod-1.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vmaddwod-2.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vmaddwod-3.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/vector/lsx/lsx-vadd.c | 416 +++++++++++++++ + .../loongarch/vector/lsx/lsx-vadda.c | 344 ++++++++++++ + .../loongarch/vector/lsx/lsx-vaddi.c | 251 +++++++++ + .../loongarch/vector/lsx/lsx-vaddwev-1.c | 335 ++++++++++++ + .../loongarch/vector/lsx/lsx-vaddwev-2.c | 344 ++++++++++++ + .../loongarch/vector/lsx/lsx-vaddwev-3.c | 425 +++++++++++++++ + .../loongarch/vector/lsx/lsx-vaddwod-1.c | 408 +++++++++++++++ + .../loongarch/vector/lsx/lsx-vaddwod-2.c | 344 ++++++++++++ + .../loongarch/vector/lsx/lsx-vaddwod-3.c | 237 +++++++++ + .../loongarch/vector/lsx/lsx-vhaddw-1.c | 488 ++++++++++++++++++ + .../loongarch/vector/lsx/lsx-vhaddw-2.c | 452 ++++++++++++++++ + .../loongarch/vector/lsx/lsx-vmadd.c | 450 ++++++++++++++++ + .../loongarch/vector/lsx/lsx-vmaddwev-1.c | 472 +++++++++++++++++ + .../loongarch/vector/lsx/lsx-vmaddwev-2.c | 383 ++++++++++++++ + .../loongarch/vector/lsx/lsx-vmaddwev-3.c | 383 ++++++++++++++ + .../loongarch/vector/lsx/lsx-vmaddwod-1.c | 372 +++++++++++++ + .../loongarch/vector/lsx/lsx-vmaddwod-2.c | 438 ++++++++++++++++ + .../loongarch/vector/lsx/lsx-vmaddwod-3.c | 460 +++++++++++++++++ + 18 files changed, 7002 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vadd.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vadda.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vaddi.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vaddwev-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vaddwev-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vaddwev-3.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vaddwod-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vaddwod-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vaddwod-3.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vhaddw-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vhaddw-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmadd.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmaddwev-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmaddwev-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmaddwev-3.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmaddwod-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmaddwod-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmaddwod-3.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vadd.c b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vadd.c +new file mode 100644 +index 000000000..7cfb989e4 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vadd.c +@@ -0,0 +1,416 @@ ++/* { dg-do run } */ ++/* { dg-options "-mlsx -w -fno-strict-aliasing" } */ ++#include "../simd_correctness_check.h" ++#include <lsxintrin.h> ++ ++int ++main () ++{ ++ __m128i __m128i_op0, __m128i_op1, __m128i_op2, __m128i_out, __m128i_result; ++ __m128 __m128_op0, __m128_op1, __m128_op2, __m128_out, __m128_result; ++ __m128d __m128d_op0, __m128d_op1, __m128d_op2, __m128d_out, __m128d_result; ++ ++ int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail; ++ long int long_op0, long_op1, long_op2, lont_out, lont_result; ++ long int long_int_out, long_int_result; ++ unsigned int unsigned_int_out, unsigned_int_result; ++ unsigned long int unsigned_long_int_out, unsigned_long_int_result; ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vadd_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000b0000000b; ++ *((unsigned long *)&__m128i_op00) = 0x000201000000000b; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000fc0000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000b0000000b; ++ *((unsigned long *)&__m128i_result0) = 0x0002010000fc000b; ++ __m128i_out = __lsx_vadd_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000017fda829; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000017fda829; ++ __m128i_out = __lsx_vadd_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0xffffffffffff0000; ++ *((unsigned long *)&__m128i_op00) = 0x000000000001fffe; ++ *((unsigned long *)&__m128i_op11) = 0x7f7f7f7f00107f04; ++ *((unsigned long *)&__m128i_op10) = 0x7f0000fd7f0000fd; ++ *((unsigned long *)&__m128i_result1) = 0x7e7e7e7eff0f7f04; ++ *((unsigned long *)&__m128i_result0) = 0x7f0000fd7f01fffb; ++ __m128i_out = __lsx_vadd_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vadd_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0080000000000000; ++ *((unsigned long *)&__m128i_op00) = 0xf4b6f3f52f4ef4a8; ++ *((unsigned long *)&__m128i_op11) = 0x195f307a5d04acbb; ++ *((unsigned long *)&__m128i_op10) = 0x6a1a3fbb3c90260e; ++ *((unsigned long *)&__m128i_result1) = 0x19df307a5d04acbb; ++ *((unsigned long *)&__m128i_result0) = 0x5ed032b06bde1ab6; ++ __m128i_out = __lsx_vadd_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x5555001400005111; ++ *((unsigned long *)&__m128i_op00) = 0xffabbeab55110140; ++ *((unsigned long *)&__m128i_op11) = 0x5555001400005111; ++ *((unsigned long *)&__m128i_op10) = 0xffabbeab55110140; ++ *((unsigned long *)&__m128i_result1) = 0xaaaa00280000a222; ++ *((unsigned long *)&__m128i_result0) = 0xfe567c56aa220280; ++ __m128i_out = __lsx_vadd_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0xf51cf8dad6040188; ++ *((unsigned long *)&__m128i_op10) = 0x0982e2daf234ed87; ++ *((unsigned long *)&__m128i_result1) = 0xf51cf8dad6040188; ++ *((unsigned long *)&__m128i_result0) = 0x0982e2daf234ed87; ++ __m128i_out = __lsx_vadd_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x000000490000004d; ++ *((unsigned long *)&__m128i_op00) = 0x00000001ffffffff; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000073; ++ *((unsigned long *)&__m128i_op10) = 0x000000000000002a; ++ *((unsigned long *)&__m128i_result1) = 0x00000049000000c0; ++ *((unsigned long *)&__m128i_result0) = 0x00000001ffffff29; ++ __m128i_out = __lsx_vadd_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x000000000000bd3d; ++ *((unsigned long *)&__m128i_op00) = 0x000000007fff0000; ++ *((unsigned long *)&__m128i_op11) = 0x000000000000bd30; ++ *((unsigned long *)&__m128i_op10) = 0x0000000d7fff0000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000007a6d; ++ *((unsigned long *)&__m128i_result0) = 0x0000000dfefe0000; ++ __m128i_out = __lsx_vadd_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0xfffd000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0xfffd000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0xfefa000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vadd_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op00) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op11) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op10) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_result1) = 0xfefefefefefefefe; ++ *((unsigned long *)&__m128i_result0) = 0xfefefefefefefefe; ++ __m128i_out = __lsx_vadd_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out);
View file
_service:tar_scm:LoongArch-Add-tests-for-SX-vector-addition-vsadd-ins.patch
Added
@@ -0,0 +1,715 @@ +From 243656b5b87a3125c2a885d11f022a79cca98b39 Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Mon, 11 Sep 2023 10:07:24 +0800 +Subject: PATCH 082/124 LoongArch: Add tests for SX vector addition vsadd + instructions. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/vector/lsx/lsx-vsadd-1.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vsadd-2.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/vector/lsx/lsx-vsadd-1.c | 335 +++++++++++++++++ + .../loongarch/vector/lsx/lsx-vsadd-2.c | 345 ++++++++++++++++++ + 2 files changed, 680 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsadd-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsadd-2.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsadd-1.c b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsadd-1.c +new file mode 100644 +index 000000000..1bc27c983 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsadd-1.c +@@ -0,0 +1,335 @@ ++/* { dg-do run } */ ++/* { dg-options "-mlsx -w -fno-strict-aliasing" } */ ++#include "../simd_correctness_check.h" ++#include <lsxintrin.h> ++ ++int ++main () ++{ ++ __m128i __m128i_op0, __m128i_op1, __m128i_op2, __m128i_out, __m128i_result; ++ __m128 __m128_op0, __m128_op1, __m128_op2, __m128_out, __m128_result; ++ __m128d __m128d_op0, __m128d_op1, __m128d_op2, __m128d_out, __m128d_result; ++ ++ int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail; ++ long int long_op0, long_op1, long_op2, lont_out, lont_result; ++ long int long_int_out, long_int_result; ++ unsigned int unsigned_int_out, unsigned_int_result; ++ unsigned long int unsigned_long_int_out, unsigned_long_int_result; ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x00000000ffffffff; ++ *((unsigned long *)&__m128i_op10) = 0x00000000ffffffff; ++ *((unsigned long *)&__m128i_result1) = 0x00000000ffffffff; ++ *((unsigned long *)&__m128i_result0) = 0x00000000ffffffff; ++ __m128i_out = __lsx_vsadd_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op11) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op10) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_result1) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_result0) = 0xfefefefefefefefe; ++ __m128i_out = __lsx_vsadd_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0xffffffff3c992b2e; ++ *((unsigned long *)&__m128i_op10) = 0xffffffffffff730f; ++ *((unsigned long *)&__m128i_result1) = 0xffffffff3c992b2e; ++ *((unsigned long *)&__m128i_result0) = 0xffffffffffff730f; ++ __m128i_out = __lsx_vsadd_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vsadd_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vsadd_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x00007fff00007fff; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x000000002bfd9461; ++ *((unsigned long *)&__m128i_result1) = 0x00007fff00007fff; ++ *((unsigned long *)&__m128i_result0) = 0x000000002bfd9461; ++ __m128i_out = __lsx_vsadd_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x00d3012acc56f9bb; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000001021; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x00d3012acc56f9bb; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000001021; ++ __m128i_out = __lsx_vsadd_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000001000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000001000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000001000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000001000; ++ __m128i_out = __lsx_vsadd_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x80808080806b000b; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x80808080806b000b; ++ __m128i_out = __lsx_vsadd_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op00) = 0xffffffffff01ff01; ++ *((unsigned long *)&__m128i_op11) = 0x3c600000ff800000; ++ *((unsigned long *)&__m128i_op10) = 0xfffffffffffffffe; ++ *((unsigned long *)&__m128i_result1) = 0x3c5fffffff7fffff; ++ *((unsigned long *)&__m128i_result0) = 0xfffefffeff00feff; ++ __m128i_out = __lsx_vsadd_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vsadd_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x00ff00ff00ff00ff; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x00ff00ff00ff00ff; ++ __m128i_out = __lsx_vsadd_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x00000000ffffffff; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x00000000ffffffff; ++ __m128i_out = __lsx_vsadd_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x3ff0000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x40f3fa0000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x3ff0000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x40f3fa0000000000; ++ __m128i_out = __lsx_vsadd_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000008a0000008a; ++ *((unsigned long *)&__m128i_op00) = 0x0000008900000009; ++ *((unsigned long *)&__m128i_op11) = 0x63637687636316bb; ++ *((unsigned long *)&__m128i_op10) = 0x6363636363636363; ++ *((unsigned long *)&__m128i_result1) = 0x6363771163631745; ++ *((unsigned long *)&__m128i_result0) = 0x636363ec6363636c; ++ __m128i_out = __lsx_vsadd_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000004; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000004; ++ __m128i_out = __lsx_vsadd_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000080000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000080000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000080000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000080000000; ++ __m128i_out = __lsx_vsadd_w (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0xfffffffffefefe6a; ++ *((unsigned long *)&__m128i_op00) = 0x00000000c2bac2c2;
View file
_service:tar_scm:LoongArch-Add-tests-for-SX-vector-floating-point-ari.patch
Added
@@ -0,0 +1,2928 @@ +From 4ccb21b6d2d23046c6a71c4540a1eb288609f041 Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Tue, 12 Sep 2023 11:25:20 +0800 +Subject: PATCH 093/124 LoongArch: Add tests for SX vector floating point + arithmetic instructions. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/vector/lsx/lsx-vfadd_d.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vfadd_s.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vfclass_d.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vfclass_s.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vflogb_d.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vflogb_s.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vfmax_d.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vfmax_s.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vfmaxa_d.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vfmaxa_s.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vfsqrt_d.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vfsqrt_s.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/vector/lsx/lsx-vfadd_d.c | 407 +++++++++++++++ + .../loongarch/vector/lsx/lsx-vfadd_s.c | 470 ++++++++++++++++++ + .../loongarch/vector/lsx/lsx-vfclass_d.c | 83 ++++ + .../loongarch/vector/lsx/lsx-vfclass_s.c | 74 +++ + .../loongarch/vector/lsx/lsx-vflogb_d.c | 76 +++ + .../loongarch/vector/lsx/lsx-vflogb_s.c | 185 +++++++ + .../loongarch/vector/lsx/lsx-vfmax_d.c | 200 ++++++++ + .../loongarch/vector/lsx/lsx-vfmax_s.c | 335 +++++++++++++ + .../loongarch/vector/lsx/lsx-vfmaxa_d.c | 155 ++++++ + .../loongarch/vector/lsx/lsx-vfmaxa_s.c | 230 +++++++++ + .../loongarch/vector/lsx/lsx-vfsqrt_d.c | 216 ++++++++ + .../loongarch/vector/lsx/lsx-vfsqrt_s.c | 372 ++++++++++++++ + 12 files changed, 2803 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfadd_d.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfadd_s.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfclass_d.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfclass_s.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vflogb_d.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vflogb_s.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfmax_d.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfmax_s.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfmaxa_d.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfmaxa_s.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfsqrt_d.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfsqrt_s.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfadd_d.c b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfadd_d.c +new file mode 100644 +index 000000000..7ffbd385e +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfadd_d.c +@@ -0,0 +1,407 @@ ++/* { dg-do run } */ ++/* { dg-options "-mlsx -w -fno-strict-aliasing" } */ ++#include "../simd_correctness_check.h" ++#include <lsxintrin.h> ++ ++int ++main () ++{ ++ __m128i __m128i_op0, __m128i_op1, __m128i_op2, __m128i_out, __m128i_result; ++ __m128 __m128_op0, __m128_op1, __m128_op2, __m128_out, __m128_result; ++ __m128d __m128d_op0, __m128d_op1, __m128d_op2, __m128d_out, __m128d_result; ++ ++ int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail; ++ long int long_op0, long_op1, long_op2, lont_out, lont_result; ++ long int long_int_out, long_int_result; ++ unsigned int unsigned_int_out, unsigned_int_result; ++ unsigned long int unsigned_long_int_out, unsigned_long_int_result; ++ ++ *((unsigned long *)&__m128d_op01) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128d_op00) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128d_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_result1) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128d_result0) = 0xffffffffffffffff; ++ __m128d_out = __lsx_vfadd_d (__m128d_op0, __m128d_op1); ++ ASSERTEQ_64 (__LINE__, __m128d_result, __m128d_out); ++ ++ *((unsigned long *)&__m128d_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op00) = 0x00000000fea8ff44; ++ *((unsigned long *)&__m128d_op11) = 0x2020202020202020; ++ *((unsigned long *)&__m128d_op10) = 0x2020202020202020; ++ *((unsigned long *)&__m128d_result1) = 0x2020202020202020; ++ *((unsigned long *)&__m128d_result0) = 0x2020202020202020; ++ __m128d_out = __lsx_vfadd_d (__m128d_op0, __m128d_op1); ++ ASSERTEQ_64 (__LINE__, __m128d_result, __m128d_out); ++ ++ *((unsigned long *)&__m128d_op01) = 0x1000100010001000; ++ *((unsigned long *)&__m128d_op00) = 0x1000100010001000; ++ *((unsigned long *)&__m128d_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_result1) = 0x1000100010001000; ++ *((unsigned long *)&__m128d_result0) = 0x1000100010001000; ++ __m128d_out = __lsx_vfadd_d (__m128d_op0, __m128d_op1); ++ ASSERTEQ_64 (__LINE__, __m128d_result, __m128d_out); ++ ++ *((unsigned long *)&__m128d_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op10) = 0x000000000000000f; ++ *((unsigned long *)&__m128d_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_result0) = 0x000000000000000f; ++ __m128d_out = __lsx_vfadd_d (__m128d_op0, __m128d_op1); ++ ASSERTEQ_64 (__LINE__, __m128d_result, __m128d_out); ++ ++ *((unsigned long *)&__m128d_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_result0) = 0x0000000000000000; ++ __m128d_out = __lsx_vfadd_d (__m128d_op0, __m128d_op1); ++ ASSERTEQ_64 (__LINE__, __m128d_result, __m128d_out); ++ ++ *((unsigned long *)&__m128d_op01) = 0x0000010100fe0101; ++ *((unsigned long *)&__m128d_op00) = 0xffff0200ffff01ff; ++ *((unsigned long *)&__m128d_op11) = 0x0000ffffffffffff; ++ *((unsigned long *)&__m128d_op10) = 0x0000ffffffffffff; ++ *((unsigned long *)&__m128d_result1) = 0x0001010100fe0100; ++ *((unsigned long *)&__m128d_result0) = 0xffff0200ffff01ff; ++ __m128d_out = __lsx_vfadd_d (__m128d_op0, __m128d_op1); ++ ASSERTEQ_64 (__LINE__, __m128d_result, __m128d_out); ++ ++ *((unsigned long *)&__m128d_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_result0) = 0x0000000000000000; ++ __m128d_out = __lsx_vfadd_d (__m128d_op0, __m128d_op1); ++ ASSERTEQ_64 (__LINE__, __m128d_result, __m128d_out); ++ ++ *((unsigned long *)&__m128d_op01) = 0x7fff0101ffffe000; ++ *((unsigned long *)&__m128d_op00) = 0x7fffffffa0204000; ++ *((unsigned long *)&__m128d_op11) = 0x7f370101ff04ffff; ++ *((unsigned long *)&__m128d_op10) = 0x7f3bffffa0226021; ++ *((unsigned long *)&__m128d_result1) = 0x7fff0101ffffe000; ++ *((unsigned long *)&__m128d_result0) = 0x7fffffffa0204000; ++ __m128d_out = __lsx_vfadd_d (__m128d_op0, __m128d_op1); ++ ASSERTEQ_64 (__LINE__, __m128d_result, __m128d_out); ++ ++ *((unsigned long *)&__m128d_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_result0) = 0x0000000000000000; ++ __m128d_out = __lsx_vfadd_d (__m128d_op0, __m128d_op1); ++ ASSERTEQ_64 (__LINE__, __m128d_result, __m128d_out); ++ ++ *((unsigned long *)&__m128d_op01) = 0x0000ebd20000714f; ++ *((unsigned long *)&__m128d_op00) = 0x00012c8a0000a58a; ++ *((unsigned long *)&__m128d_op11) = 0xf654ad7447e59090; ++ *((unsigned long *)&__m128d_op10) = 0x27b1b106b8145f50; ++ *((unsigned long *)&__m128d_result1) = 0xf654ad7447e59090; ++ *((unsigned long *)&__m128d_result0) = 0x27b1b106b8145f50; ++ __m128d_out = __lsx_vfadd_d (__m128d_op0, __m128d_op1); ++ ASSERTEQ_64 (__LINE__, __m128d_result, __m128d_out); ++ ++ *((unsigned long *)&__m128d_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_result0) = 0x0000000000000000; ++ __m128d_out = __lsx_vfmul_d (__m128d_op0, __m128d_op1); ++ ASSERTEQ_64 (__LINE__, __m128d_result, __m128d_out); ++ ++ *((unsigned long *)&__m128d_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_result0) = 0x0000000000000000; ++ __m128d_out = __lsx_vfmul_d (__m128d_op0, __m128d_op1); ++ ASSERTEQ_64 (__LINE__, __m128d_result, __m128d_out); ++ ++ *((unsigned long *)&__m128d_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op11) = 0x0000001300000013; ++ *((unsigned long *)&__m128d_op10) = 0x0000001300000013; ++ *((unsigned long *)&__m128d_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_result0) = 0x0000000000000000; ++ __m128d_out = __lsx_vfmul_d (__m128d_op0, __m128d_op1); ++ ASSERTEQ_64 (__LINE__, __m128d_result, __m128d_out); ++ ++ *((unsigned long *)&__m128d_op01) = 0x0000100000000000; ++ *((unsigned long *)&__m128d_op00) = 0x1000100000001000; ++ *((unsigned long *)&__m128d_op11) = 0x0000100000000000; ++ *((unsigned long *)&__m128d_op10) = 0x1000100000001000; ++ *((unsigned long *)&__m128d_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_result0) = 0x0000000000000000; ++ __m128d_out = __lsx_vfmul_d (__m128d_op0, __m128d_op1); ++ ASSERTEQ_64 (__LINE__, __m128d_result, __m128d_out);
View file
_service:tar_scm:LoongArch-Add-tests-for-SX-vector-floating-point-ins.patch
Added
@@ -0,0 +1,4316 @@ +From f9098b58fe79ba960e41b7ec6a05ba2ea18ca02e Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Mon, 11 Sep 2023 09:42:39 +0800 +Subject: PATCH 079/124 LoongArch: Add tests for SX vector floating-point + instructions. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/vector/lsx/lsx-vfcvt-1.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vfcvt-2.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vffint-1.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vffint-2.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vffint-3.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vfrint_d.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vfrint_s.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vftint-1.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vftint-2.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vftint-3.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vftint-4.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/vector/lsx/lsx-vfcvt-1.c | 398 +++++++ + .../loongarch/vector/lsx/lsx-vfcvt-2.c | 278 +++++ + .../loongarch/vector/lsx/lsx-vffint-1.c | 161 +++ + .../loongarch/vector/lsx/lsx-vffint-2.c | 264 +++++ + .../loongarch/vector/lsx/lsx-vffint-3.c | 102 ++ + .../loongarch/vector/lsx/lsx-vfrint_d.c | 230 ++++ + .../loongarch/vector/lsx/lsx-vfrint_s.c | 350 ++++++ + .../loongarch/vector/lsx/lsx-vftint-1.c | 349 ++++++ + .../loongarch/vector/lsx/lsx-vftint-2.c | 695 +++++++++++ + .../loongarch/vector/lsx/lsx-vftint-3.c | 1028 +++++++++++++++++ + .../loongarch/vector/lsx/lsx-vftint-4.c | 345 ++++++ + 11 files changed, 4200 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcvt-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcvt-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vffint-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vffint-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vffint-3.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfrint_d.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfrint_s.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vftint-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vftint-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vftint-3.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vftint-4.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcvt-1.c b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcvt-1.c +new file mode 100644 +index 000000000..d4a86e262 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcvt-1.c +@@ -0,0 +1,398 @@ ++/* { dg-do run } */ ++/* { dg-options "-mlsx -w -fno-strict-aliasing" } */ ++#include "../simd_correctness_check.h" ++#include <lsxintrin.h> ++ ++int ++main () ++{ ++ __m128i __m128i_op0, __m128i_op1, __m128i_op2, __m128i_out, __m128i_result; ++ __m128 __m128_op0, __m128_op1, __m128_op2, __m128_out, __m128_result; ++ __m128d __m128d_op0, __m128d_op1, __m128d_op2, __m128d_out, __m128d_result; ++ ++ int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail; ++ long int long_op0, long_op1, long_op2, lont_out, lont_result; ++ long int long_int_out, long_int_result; ++ unsigned int unsigned_int_out, unsigned_int_result; ++ unsigned long int unsigned_long_int_out, unsigned_long_int_result; ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x00e0000000e00000; ++ *((int *)&__m128_result3) = 0x00000000; ++ *((int *)&__m128_result2) = 0x00000000; ++ *((int *)&__m128_result1) = 0x00000000; ++ *((int *)&__m128_result0) = 0x00000000; ++ __m128_out = __lsx_vfcvth_s_h (__m128i_op0); ++ ASSERTEQ_32 (__LINE__, __m128_result, __m128_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000002a55005501; ++ *((unsigned long *)&__m128i_op00) = 0x0000002a55000001; ++ *((int *)&__m128_result3) = 0x00000000; ++ *((int *)&__m128_result2) = 0x36280000; ++ *((int *)&__m128_result1) = 0x42a00000; ++ *((int *)&__m128_result0) = 0x42a02000; ++ __m128_out = __lsx_vfcvth_s_h (__m128i_op0); ++ ASSERTEQ_32 (__LINE__, __m128_result, __m128_out); ++ ++ *((int *)&__m128_op03) = 0x00000000; ++ *((int *)&__m128_op02) = 0x00000000; ++ *((int *)&__m128_op01) = 0xf436f3f5; ++ *((int *)&__m128_op00) = 0x2f4ef4a8; ++ *((unsigned long *)&__m128d_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_result0) = 0x0000000000000000; ++ __m128d_out = __lsx_vfcvth_d_s (__m128_op0); ++ ASSERTEQ_64 (__LINE__, __m128d_result, __m128d_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0xffffffffcfb799f1; ++ *((unsigned long *)&__m128i_op00) = 0x0282800002828282; ++ *((int *)&__m128_result3) = 0xffffe000; ++ *((int *)&__m128_result2) = 0xffffe000; ++ *((int *)&__m128_result1) = 0xc1f6e000; ++ *((int *)&__m128_result0) = 0xbb3e2000; ++ __m128_out = __lsx_vfcvth_s_h (__m128i_op0); ++ ASSERTEQ_32 (__LINE__, __m128_result, __m128_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000040004000100; ++ *((int *)&__m128_result3) = 0x00000000; ++ *((int *)&__m128_result2) = 0x00000000; ++ *((int *)&__m128_result1) = 0x00000000; ++ *((int *)&__m128_result0) = 0x00000000; ++ __m128_out = __lsx_vfcvth_s_h (__m128i_op0); ++ ASSERTEQ_32 (__LINE__, __m128_result, __m128_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((int *)&__m128_result3) = 0x00000000; ++ *((int *)&__m128_result2) = 0x00000000; ++ *((int *)&__m128_result1) = 0x00000000; ++ *((int *)&__m128_result0) = 0x00000000; ++ __m128_out = __lsx_vfcvth_s_h (__m128i_op0); ++ ASSERTEQ_32 (__LINE__, __m128_result, __m128_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((int *)&__m128_result3) = 0x00000000; ++ *((int *)&__m128_result2) = 0x00000000; ++ *((int *)&__m128_result1) = 0x00000000; ++ *((int *)&__m128_result0) = 0x00000000; ++ __m128_out = __lsx_vfcvth_s_h (__m128i_op0); ++ ASSERTEQ_32 (__LINE__, __m128_result, __m128_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000006f00001f0a; ++ *((unsigned long *)&__m128i_op00) = 0x0000958affff995d; ++ *((int *)&__m128_result3) = 0x00000000; ++ *((int *)&__m128_result2) = 0x36de0000; ++ *((int *)&__m128_result1) = 0x00000000; ++ *((int *)&__m128_result0) = 0x3be14000; ++ __m128_out = __lsx_vfcvth_s_h (__m128i_op0); ++ ASSERTEQ_32 (__LINE__, __m128_result, __m128_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x41dfffff00000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((int *)&__m128_result3) = 0x403be000; ++ *((int *)&__m128_result2) = 0xffffe000; ++ *((int *)&__m128_result1) = 0x00000000; ++ *((int *)&__m128_result0) = 0x00000000; ++ __m128_out = __lsx_vfcvth_s_h (__m128i_op0); ++ ASSERTEQ_32 (__LINE__, __m128_result, __m128_out); ++ ++ *((int *)&__m128_op03) = 0x63637687; ++ *((int *)&__m128_op02) = 0x636316bb; ++ *((int *)&__m128_op01) = 0x63636363; ++ *((int *)&__m128_op00) = 0x63636363; ++ *((unsigned long *)&__m128d_result1) = 0x446c6ed0e0000000; ++ *((unsigned long *)&__m128d_result0) = 0x446c62d760000000; ++ __m128d_out = __lsx_vfcvth_d_s (__m128_op0); ++ ASSERTEQ_64 (__LINE__, __m128d_result, __m128d_out); ++ ++ *((int *)&__m128_op03) = 0x00000000; ++ *((int *)&__m128_op02) = 0x00000000; ++ *((int *)&__m128_op01) = 0x00000000; ++ *((int *)&__m128_op00) = 0x00000000; ++ *((unsigned long *)&__m128d_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_result0) = 0x0000000000000000; ++ __m128d_out = __lsx_vfcvth_d_s (__m128_op0); ++ ASSERTEQ_64 (__LINE__, __m128d_result, __m128d_out); ++ ++ *((int *)&__m128_op03) = 0x000000ff; ++ *((int *)&__m128_op02) = 0x000000ff; ++ *((int *)&__m128_op01) = 0x00000000; ++ *((int *)&__m128_op00) = 0x00000000; ++ *((unsigned long *)&__m128d_result1) = 0x371fe00000000000; ++ *((unsigned long *)&__m128d_result0) = 0x371fe00000000000; ++ __m128d_out = __lsx_vfcvth_d_s (__m128_op0); ++ ASSERTEQ_64 (__LINE__, __m128d_result, __m128d_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x6363636363636363; ++ *((int *)&__m128_result3) = 0x00000000; ++ *((int *)&__m128_result2) = 0x00000000; ++ *((int *)&__m128_result1) = 0x00000000; ++ *((int *)&__m128_result0) = 0x00000000; ++ __m128_out = __lsx_vfcvth_s_h (__m128i_op0); ++ ASSERTEQ_32 (__LINE__, __m128_result, __m128_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0xfffffffff7fff7ef; ++ *((unsigned long *)&__m128i_op00) = 0x80808080ffffffff; ++ *((int *)&__m128_result3) = 0xffffe000; ++ *((int *)&__m128_result2) = 0xffffe000; ++ *((int *)&__m128_result1) = 0xc6ffe000; ++ *((int *)&__m128_result0) = 0xc6fde000; ++ __m128_out = __lsx_vfcvth_s_h (__m128i_op0); ++ ASSERTEQ_32 (__LINE__, __m128_result, __m128_out); ++ ++ *((int *)&__m128_op03) = 0xffffffff; ++ *((int *)&__m128_op02) = 0xffffffff;
View file
_service:tar_scm:LoongArch-Add-tests-for-SX-vector-handling-and-shuff.patch
Added
@@ -0,0 +1,5411 @@ +From ab7f1db887733fabf41c7a39730c48376e29100c Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Tue, 12 Sep 2023 11:34:56 +0800 +Subject: PATCH 096/124 LoongArch: Add tests for SX vector handling and + shuffle instructions. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/vector/lsx/lsx-vbsll.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vbsrl.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vextrins.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vilvh.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vilvl.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vinsgr2vr.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vpackev.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vpackod.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vpickev.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vpickod.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vpickve2gr.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vpremi.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vreplgr2vr.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vreplve.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vreplvei.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vshuf.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vshuf4i.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/vector/lsx/lsx-vbsll.c | 83 +++ + .../loongarch/vector/lsx/lsx-vbsrl.c | 55 ++ + .../loongarch/vector/lsx/lsx-vextrins.c | 479 +++++++++++++++++ + .../loongarch/vector/lsx/lsx-vilvh.c | 353 +++++++++++++ + .../loongarch/vector/lsx/lsx-vilvl.c | 327 ++++++++++++ + .../loongarch/vector/lsx/lsx-vinsgr2vr.c | 278 ++++++++++ + .../loongarch/vector/lsx/lsx-vpackev.c | 452 ++++++++++++++++ + .../loongarch/vector/lsx/lsx-vpackod.c | 461 +++++++++++++++++ + .../loongarch/vector/lsx/lsx-vpickev.c | 362 +++++++++++++ + .../loongarch/vector/lsx/lsx-vpickod.c | 336 ++++++++++++ + .../loongarch/vector/lsx/lsx-vpickve2gr.c | 488 ++++++++++++++++++ + .../loongarch/vector/lsx/lsx-vpremi.c | 20 + + .../loongarch/vector/lsx/lsx-vreplgr2vr.c | 212 ++++++++ + .../loongarch/vector/lsx/lsx-vreplve.c | 300 +++++++++++ + .../loongarch/vector/lsx/lsx-vreplvei.c | 293 +++++++++++ + .../loongarch/vector/lsx/lsx-vshuf.c | 394 ++++++++++++++ + .../loongarch/vector/lsx/lsx-vshuf4i.c | 348 +++++++++++++ + 17 files changed, 5241 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vbsll.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vbsrl.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vextrins.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vilvh.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vilvl.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vinsgr2vr.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vpackev.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vpackod.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vpickev.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vpickod.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vpickve2gr.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vpremi.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vreplgr2vr.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vreplve.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vreplvei.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vshuf.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vshuf4i.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vbsll.c b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vbsll.c +new file mode 100644 +index 000000000..34246c551 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vbsll.c +@@ -0,0 +1,83 @@ ++/* { dg-do run } */ ++/* { dg-options "-mlsx -w -fno-strict-aliasing" } */ ++#include "../simd_correctness_check.h" ++#include <lsxintrin.h> ++ ++int ++main () ++{ ++ __m128i __m128i_op0, __m128i_op1, __m128i_op2, __m128i_out, __m128i_result; ++ __m128 __m128_op0, __m128_op1, __m128_op2, __m128_out, __m128_result; ++ __m128d __m128d_op0, __m128d_op1, __m128d_op2, __m128d_out, __m128d_result; ++ ++ int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail; ++ long int long_op0, long_op1, long_op2, lont_out, lont_result; ++ long int long_int_out, long_int_result; ++ unsigned int unsigned_int_out, unsigned_int_result; ++ unsigned long int unsigned_long_int_out, unsigned_long_int_result; ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x00ffffff000000ff; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0xffffff000000ff00; ++ __m128i_out = __lsx_vbsll_v (__m128i_op0, 0x1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x00ff00ff00ff00ff; ++ *((unsigned long *)&__m128i_op00) = 0x00ff00ff00ff00ff; ++ *((unsigned long *)&__m128i_result1) = 0xff00ff00ff00ff00; ++ *((unsigned long *)&__m128i_result0) = 0xff00000000000000; ++ __m128i_out = __lsx_vbsll_v (__m128i_op0, 0x17); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000800; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0008000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vbsll_v (__m128i_op0, 0x15); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x000a000a000a000a; ++ *((unsigned long *)&__m128i_op00) = 0x000a000a000a000a; ++ *((unsigned long *)&__m128i_result1) = 0x0a00000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vbsll_v (__m128i_op0, 0xf); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0141010101410101; ++ *((unsigned long *)&__m128i_op00) = 0x0141010101410101; ++ *((unsigned long *)&__m128i_result1) = 0x4101010141010100; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vbsll_v (__m128i_op0, 0x19); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vbsll_v (__m128i_op0, 0x2); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000001; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000001; ++ *((unsigned long *)&__m128i_result1) = 0x0000000100000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vbsll_v (__m128i_op0, 0xc); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000001; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vbsll_v (__m128i_op0, 0xb); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000158; ++ *((unsigned long *)&__m128i_result1) = 0x0000000001580000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vbsll_v (__m128i_op0, 0xa); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ return 0; ++} +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vbsrl.c b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vbsrl.c +new file mode 100644 +index 000000000..986b7d566 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vbsrl.c +@@ -0,0 +1,55 @@ ++/* { dg-do run } */ ++/* { dg-options "-mlsx -w -fno-strict-aliasing" } */ ++#include "../simd_correctness_check.h" ++#include <lsxintrin.h> ++ ++int ++main () ++{ ++ __m128i __m128i_op0, __m128i_op1, __m128i_op2, __m128i_out, __m128i_result; ++ __m128 __m128_op0, __m128_op1, __m128_op2, __m128_out, __m128_result; ++ __m128d __m128d_op0, __m128d_op1, __m128d_op2, __m128d_out, __m128d_result; ++ ++ int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail; ++ long int long_op0, long_op1, long_op2, lont_out, lont_result; ++ long int long_int_out, long_int_result; ++ unsigned int unsigned_int_out, unsigned_int_result; ++ unsigned long int unsigned_long_int_out, unsigned_long_int_result; ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000401000001; ++ *((unsigned long *)&__m128i_op00) = 0x0001000100000004; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000040100; ++ *((unsigned long *)&__m128i_result0) = 0x0001000100010000; ++ __m128i_out = __lsx_vbsrl_v (__m128i_op0, 0x2); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x000000003fffffff; ++ *((unsigned long *)&__m128i_op00) = 0x000000003fffffff; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x003fffffff000000; ++ __m128i_out = __lsx_vbsrl_v (__m128i_op0, 0x5); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0005fe0300010101; ++ *((unsigned long *)&__m128i_op00) = 0x0000000100010001; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000005; ++ *((unsigned long *)&__m128i_result0) = 0xfe03000101010000; ++ __m128i_out = __lsx_vbsrl_v (__m128i_op0, 0x6); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++
View file
_service:tar_scm:LoongArch-Add-tests-for-SX-vector-subtraction-instru.patch
Added
@@ -0,0 +1,4150 @@ +From dc800193eb03dc87e702d4f3aeb886337b6be870 Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Mon, 11 Sep 2023 10:05:37 +0800 +Subject: PATCH 081/124 LoongArch: Add tests for SX vector subtraction + instructions. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/vector/lsx/lsx-vhsubw-1.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vhsubw-2.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vmsub.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vssub-1.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vssub-2.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vsub.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vsubi.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vsubwev-1.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vsubwev-2.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vsubwod-1.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vsubwod-2.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/vector/lsx/lsx-vhsubw-1.c | 327 +++++++++++++ + .../loongarch/vector/lsx/lsx-vhsubw-2.c | 353 ++++++++++++++ + .../loongarch/vector/lsx/lsx-vmsub.c | 461 ++++++++++++++++++ + .../loongarch/vector/lsx/lsx-vssub-1.c | 398 +++++++++++++++ + .../loongarch/vector/lsx/lsx-vssub-2.c | 408 ++++++++++++++++ + .../loongarch/vector/lsx/lsx-vsub.c | 381 +++++++++++++++ + .../loongarch/vector/lsx/lsx-vsubi.c | 329 +++++++++++++ + .../loongarch/vector/lsx/lsx-vsubwev-1.c | 326 +++++++++++++ + .../loongarch/vector/lsx/lsx-vsubwev-2.c | 417 ++++++++++++++++ + .../loongarch/vector/lsx/lsx-vsubwod-1.c | 326 +++++++++++++ + .../loongarch/vector/lsx/lsx-vsubwod-2.c | 308 ++++++++++++ + 11 files changed, 4034 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vhsubw-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vhsubw-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmsub.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vssub-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vssub-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsub.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsubi.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsubwev-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsubwev-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsubwod-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsubwod-2.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vhsubw-1.c b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vhsubw-1.c +new file mode 100644 +index 000000000..0b51cb8cf +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vhsubw-1.c +@@ -0,0 +1,327 @@ ++/* { dg-do run } */ ++/* { dg-options "-mlsx -w -fno-strict-aliasing" } */ ++#include "../simd_correctness_check.h" ++#include <lsxintrin.h> ++ ++int ++main () ++{ ++ __m128i __m128i_op0, __m128i_op1, __m128i_op2, __m128i_out, __m128i_result; ++ __m128 __m128_op0, __m128_op1, __m128_op2, __m128_out, __m128_result; ++ __m128d __m128d_op0, __m128d_op1, __m128d_op2, __m128d_out, __m128d_result; ++ ++ int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail; ++ long int long_op0, long_op1, long_op2, lont_out, lont_result; ++ long int long_int_out, long_int_result; ++ unsigned int unsigned_int_out, unsigned_int_result; ++ unsigned long int unsigned_long_int_out, unsigned_long_int_result; ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x00000000fffffc00; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000010000; ++ __m128i_out = __lsx_vhsubw_h_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x00007f8000007f80; ++ *((unsigned long *)&__m128i_op10) = 0x00007f8000007f80; ++ *((unsigned long *)&__m128i_result1) = 0x0000008000000080; ++ *((unsigned long *)&__m128i_result0) = 0x0000008000000080; ++ __m128i_out = __lsx_vhsubw_h_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0xffffffffffffff00; ++ *((unsigned long *)&__m128i_op10) = 0xffffffff07effffe; ++ *((unsigned long *)&__m128i_result1) = 0x0001000100010000; ++ *((unsigned long *)&__m128i_result0) = 0x0001000100110002; ++ __m128i_out = __lsx_vhsubw_h_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ unsigned_int_out = __lsx_vpickve2gr_wu (__m128i_op0, 0x2); ++ *((unsigned long *)&__m128i_op01) = 0x00000000ffffff01; ++ *((unsigned long *)&__m128i_op00) = 0xffffeff400000df4; ++ *((unsigned long *)&__m128i_op11) = 0x0000006f00001f0a; ++ *((unsigned long *)&__m128i_op10) = 0x0000958affff995d; ++ *((unsigned long *)&__m128i_result1) = 0x0000ff91fffffff5; ++ *((unsigned long *)&__m128i_result0) = 0xffff00650001ffb0; ++ __m128i_out = __lsx_vhsubw_h_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000bfffffffe0f6; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x000000010001000a; ++ __m128i_out = __lsx_vhsubw_h_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x41dfffffffc00000; ++ *((unsigned long *)&__m128i_op00) = 0xbff0000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0008000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0101010101010101; ++ *((unsigned long *)&__m128i_result1) = 0x0039ffffffff0000; ++ *((unsigned long *)&__m128i_result0) = 0xffbeffffffffffff; ++ __m128i_out = __lsx_vhsubw_h_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x370bdfecffecffec; ++ *((unsigned long *)&__m128i_op00) = 0x370bdfecffecffec; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000008140c80; ++ *((unsigned long *)&__m128i_result1) = 0x0037ffdfffffffff; ++ *((unsigned long *)&__m128i_result0) = 0x0037ffdfffeb007f; ++ __m128i_out = __lsx_vhsubw_h_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vhsubw_h_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x98147a504d145000; ++ *((unsigned long *)&__m128i_op00) = 0x377b810912c0e000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x4e3e133738bb47d2; ++ *((unsigned long *)&__m128i_result1) = 0xff98007a004d0050; ++ *((unsigned long *)&__m128i_result0) = 0xfff9ff4a0057000e; ++ __m128i_out = __lsx_vhsubw_h_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x00000501ffff0005; ++ *((unsigned long *)&__m128i_op11) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op10) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_result1) = 0x0001000100010001; ++ *((unsigned long *)&__m128i_result0) = 0x0001000600000001; ++ __m128i_out = __lsx_vhsubw_h_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x00020000ffff0001; ++ *((unsigned long *)&__m128i_op11) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op10) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_result1) = 0x0001000100010001; ++ *((unsigned long *)&__m128i_result0) = 0x0001000100000001; ++ __m128i_out = __lsx_vhsubw_h_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000ffae001effae; ++ *((unsigned long *)&__m128i_op00) = 0x001effae001effae; ++ *((unsigned long *)&__m128i_op11) = 0x5252525252525252; ++ *((unsigned long *)&__m128i_op10) = 0x5252525252525252; ++ *((unsigned long *)&__m128i_result1) = 0xffaeffadffaeffad; ++ *((unsigned long *)&__m128i_result0) = 0xffaeffadffaeffad; ++ __m128i_out = __lsx_vhsubw_h_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x000201000000000b; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000fc0000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000200000000; ++ __m128i_out = __lsx_vhsubw_w_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op00) = 0xffffffffff01ff01; ++ *((unsigned long *)&__m128i_op11) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op10) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x00000000ffffff02; ++ __m128i_out = __lsx_vhsubw_w_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000;
View file
_service:tar_scm:LoongArch-Add-tests-for-SX-vector-vabsd-vmskgez-vmsk.patch
Added
@@ -0,0 +1,1710 @@ +From 7fc7953897e6ff488eebd5ea769447b7a1a7a0ed Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Mon, 11 Sep 2023 18:48:08 +0800 +Subject: PATCH 087/124 LoongArch: Add tests for SX vector + vabsd/vmskgez/vmskltz/vmsknz/vsigncov instructions. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/vector/lsx/lsx-vabsd-1.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vabsd-2.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vmskgez.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vmskltz.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vmsknz.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vsigncov.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/vector/lsx/lsx-vabsd-1.c | 272 +++++++++++ + .../loongarch/vector/lsx/lsx-vabsd-2.c | 398 ++++++++++++++++ + .../loongarch/vector/lsx/lsx-vmskgez.c | 119 +++++ + .../loongarch/vector/lsx/lsx-vmskltz.c | 321 +++++++++++++ + .../loongarch/vector/lsx/lsx-vmsknz.c | 104 +++++ + .../loongarch/vector/lsx/lsx-vsigncov.c | 425 ++++++++++++++++++ + 6 files changed, 1639 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vabsd-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vabsd-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmskgez.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmskltz.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmsknz.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsigncov.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vabsd-1.c b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vabsd-1.c +new file mode 100644 +index 000000000..e336581f3 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vabsd-1.c +@@ -0,0 +1,272 @@ ++/* { dg-do run } */ ++/* { dg-options "-mlsx -w -fno-strict-aliasing" } */ ++#include "../simd_correctness_check.h" ++#include <lsxintrin.h> ++ ++int ++main () ++{ ++ __m128i __m128i_op0, __m128i_op1, __m128i_op2, __m128i_out, __m128i_result; ++ __m128 __m128_op0, __m128_op1, __m128_op2, __m128_out, __m128_result; ++ __m128d __m128d_op0, __m128d_op1, __m128d_op2, __m128d_out, __m128d_result; ++ ++ int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail; ++ long int long_op0, long_op1, long_op2, lont_out, lont_result; ++ long int long_int_out, long_int_result; ++ unsigned int unsigned_int_out, unsigned_int_result; ++ unsigned long int unsigned_long_int_out, unsigned_long_int_result; ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vabsd_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0xfda9b23a624082fd; ++ *((unsigned long *)&__m128i_op10) = 0x00000000ffff0000; ++ *((unsigned long *)&__m128i_result1) = 0x03574e3a62407e03; ++ *((unsigned long *)&__m128i_result0) = 0x0000000001010000; ++ __m128i_out = __lsx_vabsd_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x8000000080000000; ++ *((unsigned long *)&__m128i_op00) = 0x7fffffff7fffffff; ++ *((unsigned long *)&__m128i_op11) = 0xfffd000700000000; ++ *((unsigned long *)&__m128i_op10) = 0x0014fff500000000; ++ *((unsigned long *)&__m128i_result1) = 0x7f03000780000000; ++ *((unsigned long *)&__m128i_result0) = 0x7f15000a7f010101; ++ __m128i_out = __lsx_vabsd_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vabsd_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x7fffffffffffffff; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x000000060000000e; ++ *((unsigned long *)&__m128i_op10) = 0x000000127fffffea; ++ *((unsigned long *)&__m128i_result1) = 0x7f0101070101010f; ++ *((unsigned long *)&__m128i_result0) = 0x000000127f010116; ++ __m128i_out = __lsx_vabsd_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x000000000000000b; ++ *((unsigned long *)&__m128i_op00) = 0x000000000000000b; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x000000000000000b; ++ *((unsigned long *)&__m128i_result0) = 0x000000000000000b; ++ __m128i_out = __lsx_vabsd_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x67eb85af0000b000; ++ *((unsigned long *)&__m128i_op10) = 0xc8847ef6ed3f2000; ++ *((unsigned long *)&__m128i_result1) = 0x67157b5100005000; ++ *((unsigned long *)&__m128i_result0) = 0x387c7e0a133f2000; ++ __m128i_out = __lsx_vabsd_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0xfff7fffefffa01ff; ++ *((unsigned long *)&__m128i_op00) = 0xfffbfffefffe01ff; ++ *((unsigned long *)&__m128i_op11) = 0xfcfcfcfcfcfcfcfd; ++ *((unsigned long *)&__m128i_op10) = 0xfcfcfcfcfcfcfcfd; ++ *((unsigned long *)&__m128i_result1) = 0x0305030203020502; ++ *((unsigned long *)&__m128i_result0) = 0x0301030203020502; ++ __m128i_out = __lsx_vabsd_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x4ee376188658d85f; ++ *((unsigned long *)&__m128i_op00) = 0x5728dcc85ac760d2; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x4e1d76187a58285f; ++ *((unsigned long *)&__m128i_result0) = 0x572824385a39602e; ++ __m128i_out = __lsx_vabsd_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vabsd_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0xf654ad7447e59090; ++ *((unsigned long *)&__m128i_op10) = 0x27b1b106b8145f50; ++ *((unsigned long *)&__m128i_result1) = 0x0a545374471b7070; ++ *((unsigned long *)&__m128i_result0) = 0x274f4f0648145f50; ++ __m128i_out = __lsx_vabsd_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vabsd_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x21f32eafa486fd38; ++ *((unsigned long *)&__m128i_op00) = 0x407c2ca3d3430357; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x21f32eaf5b7a02c8; ++ *((unsigned long *)&__m128i_result0) = 0x407c2ca32cbd0357; ++ __m128i_out = __lsx_vabsd_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vabsd_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x000000003bfb4000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x000000003bfb4000; ++ __m128i_out = __lsx_vabsd_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000ffffffffffff; ++ *((unsigned long *)&__m128i_op10) = 0x0000ffffffffffff; ++ *((unsigned long *)&__m128i_result1) = 0x0000000100010001; ++ *((unsigned long *)&__m128i_result0) = 0x0000000100010001; ++ __m128i_out = __lsx_vabsd_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out);
View file
_service:tar_scm:LoongArch-Add-tests-for-SX-vector-vand-vandi-vandn-v.patch
Added
@@ -0,0 +1,1209 @@ +From ea0d56b6569735448905780fe8468c9b3c6aad14 Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Mon, 11 Sep 2023 18:58:17 +0800 +Subject: PATCH 097/124 LoongArch: Add tests for SX vector + vand/vandi/vandn/vor/vori/vnor/ vnori/vxor/vxori instructions. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/vector/lsx/lsx-vand.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vandi.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vandn.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vnor.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vnori.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vor.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vori.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vorn.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vxor.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vxori.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/vector/lsx/lsx-vand.c | 159 ++++++++++++++++ + .../loongarch/vector/lsx/lsx-vandi.c | 67 +++++++ + .../loongarch/vector/lsx/lsx-vandn.c | 129 +++++++++++++ + .../loongarch/vector/lsx/lsx-vnor.c | 109 +++++++++++ + .../loongarch/vector/lsx/lsx-vnori.c | 91 ++++++++++ + .../gcc.target/loongarch/vector/lsx/lsx-vor.c | 169 ++++++++++++++++++ + .../loongarch/vector/lsx/lsx-vori.c | 123 +++++++++++++ + .../loongarch/vector/lsx/lsx-vorn.c | 109 +++++++++++ + .../loongarch/vector/lsx/lsx-vxor.c | 79 ++++++++ + .../loongarch/vector/lsx/lsx-vxori.c | 67 +++++++ + 10 files changed, 1102 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vand.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vandi.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vandn.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vnor.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vnori.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vor.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vori.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vorn.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vxor.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vxori.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vand.c b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vand.c +new file mode 100644 +index 000000000..1597749b5 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vand.c +@@ -0,0 +1,159 @@ ++/* { dg-do run } */ ++/* { dg-options "-mlsx -w -fno-strict-aliasing" } */ ++#include "../simd_correctness_check.h" ++#include <lsxintrin.h> ++ ++int main () ++{ ++ __m128i __m128i_op0, __m128i_op1, __m128i_op2, __m128i_out, __m128i_result; ++ __m128 __m128_op0, __m128_op1, __m128_op2, __m128_out, __m128_result; ++ __m128d __m128d_op0, __m128d_op1, __m128d_op2, __m128d_out, __m128d_result; ++ ++ int int_op0, int_op1, int_op2, int_out, int_result, i=1, fail; ++ long int long_op0, long_op1, long_op2, lont_out, lont_result; ++ long int long_int_out, long_int_result; ++ unsigned int unsigned_int_out, unsigned_int_result; ++ unsigned long int unsigned_long_int_out, unsigned_long_int_result; ++ ++ *((unsigned long*)& __m128i_op01) = 0x0000000000000000; ++ *((unsigned long*)& __m128i_op00) = 0x0000000000000000; ++ *((unsigned long*)& __m128i_op11) = 0x0000000000000000; ++ *((unsigned long*)& __m128i_op10) = 0x0000000000000000; ++ *((unsigned long*)& __m128i_result1) = 0x0000000000000000; ++ *((unsigned long*)& __m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vand_v(__m128i_op0,__m128i_op1); ++ ASSERTEQ_64(__LINE__, __m128i_result, __m128i_out); ++ ++ ++ *((unsigned long*)& __m128i_op01) = 0xffffffffffffffff; ++ *((unsigned long*)& __m128i_op00) = 0x0000000000000000; ++ *((unsigned long*)& __m128i_op11) = 0x03574e3a62407e03; ++ *((unsigned long*)& __m128i_op10) = 0x0000000001010000; ++ *((unsigned long*)& __m128i_result1) = 0x03574e3a62407e03; ++ *((unsigned long*)& __m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vand_v(__m128i_op0,__m128i_op1); ++ ASSERTEQ_64(__LINE__, __m128i_result, __m128i_out); ++ ++ ++ *((unsigned long*)& __m128i_op01) = 0xffffffffffffffff; ++ *((unsigned long*)& __m128i_op00) = 0xffffffffffffffff; ++ *((unsigned long*)& __m128i_op11) = 0x001fffff001fffff; ++ *((unsigned long*)& __m128i_op10) = 0x001fffff001fffff; ++ *((unsigned long*)& __m128i_result1) = 0x001fffff001fffff; ++ *((unsigned long*)& __m128i_result0) = 0x001fffff001fffff; ++ __m128i_out = __lsx_vand_v(__m128i_op0,__m128i_op1); ++ ASSERTEQ_64(__LINE__, __m128i_result, __m128i_out); ++ ++ ++ *((unsigned long*)& __m128i_op01) = 0x00000000003dffc2; ++ *((unsigned long*)& __m128i_op00) = 0x00000000003dffc2; ++ *((unsigned long*)& __m128i_op11) = 0x0008000000000000; ++ *((unsigned long*)& __m128i_op10) = 0x0000000000000000; ++ *((unsigned long*)& __m128i_result1) = 0x0000000000000000; ++ *((unsigned long*)& __m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vand_v(__m128i_op0,__m128i_op1); ++ ASSERTEQ_64(__LINE__, __m128i_result, __m128i_out); ++ ++ ++ *((unsigned long*)& __m128i_op01) = 0x0000000000000000; ++ *((unsigned long*)& __m128i_op00) = 0x0000000000000000; ++ *((unsigned long*)& __m128i_op11) = 0x0000000000000000; ++ *((unsigned long*)& __m128i_op10) = 0x0000000000000000; ++ *((unsigned long*)& __m128i_result1) = 0x0000000000000000; ++ *((unsigned long*)& __m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vand_v(__m128i_op0,__m128i_op1); ++ ASSERTEQ_64(__LINE__, __m128i_result, __m128i_out); ++ ++ ++ *((unsigned long*)& __m128i_op01) = 0x00000000ffff53d9; ++ *((unsigned long*)& __m128i_op00) = 0xffff0001ffff9515; ++ *((unsigned long*)& __m128i_op11) = 0x00000000ffff53d9; ++ *((unsigned long*)& __m128i_op10) = 0xffff0001ffff9515; ++ *((unsigned long*)& __m128i_result1) = 0x00000000ffff53d9; ++ *((unsigned long*)& __m128i_result0) = 0xffff0001ffff9515; ++ __m128i_out = __lsx_vand_v(__m128i_op0,__m128i_op1); ++ ASSERTEQ_64(__LINE__, __m128i_result, __m128i_out); ++ ++ ++ *((unsigned long*)& __m128i_op01) = 0x0000000000000000; ++ *((unsigned long*)& __m128i_op00) = 0x0000000000000000; ++ *((unsigned long*)& __m128i_op11) = 0x0000000000000000; ++ *((unsigned long*)& __m128i_op10) = 0x0000000000000000; ++ *((unsigned long*)& __m128i_result1) = 0x0000000000000000; ++ *((unsigned long*)& __m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vand_v(__m128i_op0,__m128i_op1); ++ ASSERTEQ_64(__LINE__, __m128i_result, __m128i_out); ++ ++ ++ *((unsigned long*)& __m128i_op01) = 0xffffffffffffffff; ++ *((unsigned long*)& __m128i_op00) = 0x0000000000000000; ++ *((unsigned long*)& __m128i_op11) = 0xffffffffffffffff; ++ *((unsigned long*)& __m128i_op10) = 0xffffffffffffffff; ++ *((unsigned long*)& __m128i_result1) = 0xffffffffffffffff; ++ *((unsigned long*)& __m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vand_v(__m128i_op0,__m128i_op1); ++ ASSERTEQ_64(__LINE__, __m128i_result, __m128i_out); ++ ++ ++ *((unsigned long*)& __m128i_op01) = 0x0000000000000000; ++ *((unsigned long*)& __m128i_op00) = 0x0000000000000000; ++ *((unsigned long*)& __m128i_op11) = 0x0000000000000000; ++ *((unsigned long*)& __m128i_op10) = 0x0000000000000000; ++ *((unsigned long*)& __m128i_result1) = 0x0000000000000000; ++ *((unsigned long*)& __m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vand_v(__m128i_op0,__m128i_op1); ++ ASSERTEQ_64(__LINE__, __m128i_result, __m128i_out); ++ ++ ++ *((unsigned long*)& __m128i_op01) = 0x67eb85af0000b000; ++ *((unsigned long*)& __m128i_op00) = 0xc8847ef6ed3f2000; ++ *((unsigned long*)& __m128i_op11) = 0x67eb85af0000b000; ++ *((unsigned long*)& __m128i_op10) = 0xc8847ef6ed3f2000; ++ *((unsigned long*)& __m128i_result1) = 0x67eb85af0000b000; ++ *((unsigned long*)& __m128i_result0) = 0xc8847ef6ed3f2000; ++ __m128i_out = __lsx_vand_v(__m128i_op0,__m128i_op1); ++ ASSERTEQ_64(__LINE__, __m128i_result, __m128i_out); ++ ++ ++ *((unsigned long*)& __m128i_op01) = 0x0000000000000000; ++ *((unsigned long*)& __m128i_op00) = 0x0000000000000000; ++ *((unsigned long*)& __m128i_op11) = 0x0000000000000000; ++ *((unsigned long*)& __m128i_op10) = 0x0000000000000000; ++ *((unsigned long*)& __m128i_result1) = 0x0000000000000000; ++ *((unsigned long*)& __m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vand_v(__m128i_op0,__m128i_op1); ++ ASSERTEQ_64(__LINE__, __m128i_result, __m128i_out); ++ ++ ++ *((unsigned long*)& __m128i_op01) = 0x0000000000000000; ++ *((unsigned long*)& __m128i_op00) = 0x0000000000000000; ++ *((unsigned long*)& __m128i_op11) = 0x0313100003131000; ++ *((unsigned long*)& __m128i_op10) = 0x0313100003131000; ++ *((unsigned long*)& __m128i_result1) = 0x0000000000000000; ++ *((unsigned long*)& __m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vand_v(__m128i_op0,__m128i_op1); ++ ASSERTEQ_64(__LINE__, __m128i_result, __m128i_out); ++ ++ ++ *((unsigned long*)& __m128i_op01) = 0x0000000000000000; ++ *((unsigned long*)& __m128i_op00) = 0x0000000200000002; ++ *((unsigned long*)& __m128i_op11) = 0x0007000000050000; ++ *((unsigned long*)& __m128i_op10) = 0x0003000100010001; ++ *((unsigned long*)& __m128i_result1) = 0x0000000000000000; ++ *((unsigned long*)& __m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vand_v(__m128i_op0,__m128i_op1); ++ ASSERTEQ_64(__LINE__, __m128i_result, __m128i_out); ++ ++ ++ *((unsigned long*)& __m128i_op01) = 0x00007a8000000480; ++ *((unsigned long*)& __m128i_op00) = 0x00000485000004cc;
View file
_service:tar_scm:LoongArch-Add-tests-for-SX-vector-vavg-vavgr-instruc.patch
Added
@@ -0,0 +1,1375 @@ +From 4fba531ee417a29234e8be84e17cddc7dd9ec343 Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Mon, 11 Sep 2023 18:35:55 +0800 +Subject: PATCH 084/124 LoongArch: Add tests for SX vector vavg/vavgr + instructions. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/vector/lsx/lsx-vavg-1.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vavg-2.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vavgr-1.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vavgr-2.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/vector/lsx/lsx-vavg-1.c | 398 ++++++++++++++++++ + .../loongarch/vector/lsx/lsx-vavg-2.c | 308 ++++++++++++++ + .../loongarch/vector/lsx/lsx-vavgr-1.c | 299 +++++++++++++ + .../loongarch/vector/lsx/lsx-vavgr-2.c | 317 ++++++++++++++ + 4 files changed, 1322 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vavg-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vavg-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vavgr-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vavgr-2.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vavg-1.c b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vavg-1.c +new file mode 100644 +index 000000000..2177ca3f6 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vavg-1.c +@@ -0,0 +1,398 @@ ++/* { dg-do run } */ ++/* { dg-options "-mlsx -w -fno-strict-aliasing" } */ ++#include "../simd_correctness_check.h" ++#include <lsxintrin.h> ++ ++int ++main () ++{ ++ __m128i __m128i_op0, __m128i_op1, __m128i_op2, __m128i_out, __m128i_result; ++ __m128 __m128_op0, __m128_op1, __m128_op2, __m128_out, __m128_result; ++ __m128d __m128d_op0, __m128d_op1, __m128d_op2, __m128d_out, __m128d_result; ++ ++ int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail; ++ long int long_op0, long_op1, long_op2, lont_out, lont_result; ++ long int long_int_out, long_int_result; ++ unsigned int unsigned_int_out, unsigned_int_result; ++ unsigned long int unsigned_long_int_out, unsigned_long_int_result; ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vavg_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0xfff8fff8fff8fff8; ++ *((unsigned long *)&__m128i_op00) = 0xfff8fff8fff8fff8; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0xfffcfffcfffcfffc; ++ *((unsigned long *)&__m128i_result0) = 0xfffcfffcfffcfffc; ++ __m128i_out = __lsx_vavg_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vavg_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vavg_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x4050000000000000; ++ *((unsigned long *)&__m128i_result1) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_result0) = 0x2028000000000000; ++ __m128i_out = __lsx_vavg_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vavg_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op10) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_result1) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_result0) = 0xffffffffffffffff; ++ __m128i_out = __lsx_vavg_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vavg_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x67eb85afb2ebb000; ++ *((unsigned long *)&__m128i_op00) = 0xc8847ef6ed3f2000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000014155445; ++ *((unsigned long *)&__m128i_result1) = 0x33f5c2d7d9f5d800; ++ *((unsigned long *)&__m128i_result0) = 0xe4c23ffb002a3a22; ++ __m128i_out = __lsx_vavg_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vavg_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vavg_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x007fffff00000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x00000000000f000e; ++ *((unsigned long *)&__m128i_op10) = 0x00000000000ffffe; ++ *((unsigned long *)&__m128i_result1) = 0x003fffff00070007; ++ *((unsigned long *)&__m128i_result0) = 0x000000000007ffff; ++ __m128i_out = __lsx_vavg_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vavg_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000040; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000040; ++ *((unsigned long *)&__m128i_op11) = 0x0000000400028000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000004; ++ *((unsigned long *)&__m128i_result1) = 0x000000020001c020; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000022; ++ __m128i_out = __lsx_vavg_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x08080807f5f5f5f8; ++ *((unsigned long *)&__m128i_op10) = 0x000000000000ff00; ++ *((unsigned long *)&__m128i_result1) = 0x04040403fafafafc; ++ *((unsigned long *)&__m128i_result0) = 0x000000000000ff80; ++ __m128i_out = __lsx_vavg_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x10f8000100000001; ++ *((unsigned long *)&__m128i_op00) = 0x00000001000010f8; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x087c000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x000000000000087c; ++ __m128i_out = __lsx_vavg_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000;
View file
_service:tar_scm:LoongArch-Add-tests-for-SX-vector-vbitclr-vbitclri-v.patch
Added
@@ -0,0 +1,3324 @@ +From 0b75b581703b0eb1eb9ca9e898255de7f4cb51ad Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Tue, 12 Sep 2023 11:20:44 +0800 +Subject: PATCH 092/124 LoongArch: Add tests for SX vector + vbitclr/vbitclri/vbitrev/vbitrevi/ + vbitsel/vbitseli/vbitset/vbitseti/vclo/vclz/vpcnt instructions. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/vector/lsx/lsx-vbitclr.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vbitclri.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vbitrev.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vbitrevi.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vbitsel.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vbitseli.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vbitset.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vbitseti.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vclo.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vclz.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vpcnt.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/vector/lsx/lsx-vbitclr.c | 461 ++++++++++++++++++ + .../loongarch/vector/lsx/lsx-vbitclri.c | 279 +++++++++++ + .../loongarch/vector/lsx/lsx-vbitrev.c | 407 ++++++++++++++++ + .../loongarch/vector/lsx/lsx-vbitrevi.c | 336 +++++++++++++ + .../loongarch/vector/lsx/lsx-vbitsel.c | 109 +++++ + .../loongarch/vector/lsx/lsx-vbitseli.c | 84 ++++ + .../loongarch/vector/lsx/lsx-vbitset.c | 371 ++++++++++++++ + .../loongarch/vector/lsx/lsx-vbitseti.c | 279 +++++++++++ + .../loongarch/vector/lsx/lsx-vclo.c | 266 ++++++++++ + .../loongarch/vector/lsx/lsx-vclz.c | 265 ++++++++++ + .../loongarch/vector/lsx/lsx-vpcnt.c | 350 +++++++++++++ + 11 files changed, 3207 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vbitclr.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vbitclri.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vbitrev.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vbitrevi.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vbitsel.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vbitseli.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vbitset.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vbitseti.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vclo.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vclz.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vpcnt.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vbitclr.c b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vbitclr.c +new file mode 100644 +index 000000000..411dcaa40 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vbitclr.c +@@ -0,0 +1,461 @@ ++/* { dg-do run } */ ++/* { dg-options "-mlsx -w -fno-strict-aliasing" } */ ++#include "../simd_correctness_check.h" ++#include <lsxintrin.h> ++ ++int ++main () ++{ ++ __m128i __m128i_op0, __m128i_op1, __m128i_op2, __m128i_out, __m128i_result; ++ __m128 __m128_op0, __m128_op1, __m128_op2, __m128_out, __m128_result; ++ __m128d __m128d_op0, __m128d_op1, __m128d_op2, __m128d_out, __m128d_result; ++ ++ int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail; ++ long int long_op0, long_op1, long_op2, lont_out, lont_result; ++ long int long_int_out, long_int_result; ++ unsigned int unsigned_int_out, unsigned_int_result; ++ unsigned long int unsigned_long_int_out, unsigned_long_int_result; ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vbitclr_d (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x000000e0000000e0; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x00e0000000e00000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x000000e0000000e0; ++ __m128i_out = __lsx_vbitclr_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vbitclr_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000004000; ++ *((unsigned long *)&__m128i_op10) = 0xfff8004000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vbitclr_d (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vbitclr_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x19df307a5d04acbb; ++ *((unsigned long *)&__m128i_op00) = 0x5ed032b06bde1ab6; ++ *((unsigned long *)&__m128i_op11) = 0x0080000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0080000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x19de307a5d04acba; ++ *((unsigned long *)&__m128i_result0) = 0x5ed032b06bde1ab6; ++ __m128i_out = __lsx_vbitclr_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0018001800180018; ++ *((unsigned long *)&__m128i_op10) = 0x0018001800180018; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vbitclr_w (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0xd8248069ffe78077; ++ *((unsigned long *)&__m128i_op11) = 0x85bd6b0e94d89998; ++ *((unsigned long *)&__m128i_op10) = 0xd83c8081ffff808f; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0xd82480697f678077; ++ __m128i_out = __lsx_vbitclr_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x000000006597cc3d; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000001; ++ *((unsigned long *)&__m128i_op11) = 0x7505853d654185f5; ++ *((unsigned long *)&__m128i_op10) = 0x01010000fefe0101; ++ *((unsigned long *)&__m128i_result1) = 0x000000006595cc1d; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000001; ++ __m128i_out = __lsx_vbitclr_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0xffff0000ffff0000; ++ *((unsigned long *)&__m128i_op00) = 0xffff0000ffff0000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0xfffe0000fffe0000; ++ *((unsigned long *)&__m128i_result0) = 0xfffe0000fffe0000; ++ __m128i_out = __lsx_vbitclr_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000001; ++ *((unsigned long *)&__m128i_op00) = 0x80000000fff7fc01; ++ *((unsigned long *)&__m128i_op11) = 0x0000000100000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000080000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x80000000fff6fc00; ++ __m128i_out = __lsx_vbitclr_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vbitclr_w (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x00000000ffffffff; ++ *((unsigned long *)&__m128i_op00) = 0x00000000fffff800; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x00000000fffefffe; ++ *((unsigned long *)&__m128i_result0) = 0x00000000fffef800; ++ __m128i_out = __lsx_vbitclr_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op00) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op11) = 0x0000000001000100; ++ *((unsigned long *)&__m128i_op10) = 0x0000000001000100; ++ *((unsigned long *)&__m128i_result1) = 0xfffffffefffffffe; ++ *((unsigned long *)&__m128i_result0) = 0xfffffffefffffffe; ++ __m128i_out = __lsx_vbitclr_w (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x4101010141010100;
View file
_service:tar_scm:LoongArch-Add-tests-for-SX-vector-vdiv-vmod-instruct.patch
Added
@@ -0,0 +1,1114 @@ +From 1a3f6886143b0fd334d1d7530bce0a746b106b27 Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Mon, 11 Sep 2023 18:51:44 +0800 +Subject: PATCH 088/124 LoongArch: Add tests for SX vector vdiv/vmod + instructions. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/vector/lsx/lsx-vdiv-1.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vdiv-2.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vmod-1.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vmod-2.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/vector/lsx/lsx-vdiv-1.c | 299 ++++++++++++++++++ + .../loongarch/vector/lsx/lsx-vdiv-2.c | 254 +++++++++++++++ + .../loongarch/vector/lsx/lsx-vmod-1.c | 254 +++++++++++++++ + .../loongarch/vector/lsx/lsx-vmod-2.c | 254 +++++++++++++++ + 4 files changed, 1061 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vdiv-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vdiv-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmod-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmod-2.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vdiv-1.c b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vdiv-1.c +new file mode 100644 +index 000000000..cb4be0475 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vdiv-1.c +@@ -0,0 +1,299 @@ ++/* { dg-do run } */ ++/* { dg-options "-mlsx -w -fno-strict-aliasing" } */ ++#include "../simd_correctness_check.h" ++#include <lsxintrin.h> ++ ++int ++main () ++{ ++ __m128i __m128i_op0, __m128i_op1, __m128i_op2, __m128i_out, __m128i_result; ++ __m128 __m128_op0, __m128_op1, __m128_op2, __m128_out, __m128_result; ++ __m128d __m128d_op0, __m128d_op1, __m128d_op2, __m128d_out, __m128d_result; ++ ++ int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail; ++ long int long_op0, long_op1, long_op2, lont_out, lont_result; ++ long int long_int_out, long_int_result; ++ unsigned int unsigned_int_out, unsigned_int_result; ++ unsigned long int unsigned_long_int_out, unsigned_long_int_result; ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op10) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vdiv_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x3ff0000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x40f3fa0000000000; ++ *((unsigned long *)&__m128i_op11) = 0xffffffffffffb4ff; ++ *((unsigned long *)&__m128i_op10) = 0xffffffffffffb4ff; ++ *((unsigned long *)&__m128i_result1) = 0xc110000000000000; ++ *((unsigned long *)&__m128i_result0) = 0xc00d060000000000; ++ __m128i_out = __lsx_vdiv_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op11) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op10) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0101010101010101; ++ __m128i_out = __lsx_vdiv_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000020000; ++ *((unsigned long *)&__m128i_op00) = 0x0101000101010001; ++ *((unsigned long *)&__m128i_op11) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op10) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000fe0000; ++ *((unsigned long *)&__m128i_result0) = 0xffff00ffffff00ff; ++ __m128i_out = __lsx_vdiv_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0xffffffff00000000; ++ *((unsigned long *)&__m128i_op00) = 0xffffffff00000000; ++ *((unsigned long *)&__m128i_op11) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op10) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_result1) = 0x0101010100000000; ++ *((unsigned long *)&__m128i_result0) = 0x0101010100000000; ++ __m128i_out = __lsx_vdiv_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x00000000ffffffff; ++ *((unsigned long *)&__m128i_op11) = 0xd3259a2984048c23; ++ *((unsigned long *)&__m128i_op10) = 0xf9796558e39953fd; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vdiv_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0xffff9727ffff9727; ++ *((unsigned long *)&__m128i_op00) = 0xfffffe79ffffba5f; ++ *((unsigned long *)&__m128i_op11) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op10) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_result1) = 0x010169d9010169d9; ++ *((unsigned long *)&__m128i_result0) = 0x01010287010146a1; ++ __m128i_out = __lsx_vdiv_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000897957687; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000408; ++ *((unsigned long *)&__m128i_op11) = 0x80010001b57fc565; ++ *((unsigned long *)&__m128i_op10) = 0x8001000184000be0; ++ *((unsigned long *)&__m128i_result1) = 0x000000080001fffe; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vdiv_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op10) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vdiv_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0xffffffff9cf0d77b; ++ *((unsigned long *)&__m128i_op10) = 0xc1000082b0fb585b; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vdiv_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x000000ff000000ff; ++ *((unsigned long *)&__m128i_op00) = 0x000000ff000000ff; ++ *((unsigned long *)&__m128i_op11) = 0x33f5c2d7d975d7fe; ++ *((unsigned long *)&__m128i_op10) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000ff010000ff01; ++ __m128i_out = __lsx_vdiv_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000feff23560000; ++ *((unsigned long *)&__m128i_op00) = 0x0000fd1654860000; ++ *((unsigned long *)&__m128i_op11) = 0x6363636363abdf16; ++ *((unsigned long *)&__m128i_op10) = 0x41f8e08016161198; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000030000; ++ __m128i_out = __lsx_vdiv_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x4f4f4f4f4f4f4f4f; ++ *((unsigned long *)&__m128i_op10) = 0x4f4f4f4f4f4f4f4f; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vdiv_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x00003ff000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000fffc00000000; ++ *((unsigned long *)&__m128i_op11) = 0x00001ff800000001; ++ *((unsigned long *)&__m128i_op10) = 0x7ffe800e80000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000200000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vdiv_w (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x195f307a5d04acbb; ++ *((unsigned long *)&__m128i_op00) = 0x6a1a3fbb3c90260e; ++ *((unsigned long *)&__m128i_op11) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op10) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_result1) = 0xe6a0cf86a2fb5345; ++ *((unsigned long *)&__m128i_result0) = 0x95e5c045c36fd9f2; ++ __m128i_out = __lsx_vdiv_w (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op00) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op11) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op10) = 0xfffffffffffffffe; ++ *((unsigned long *)&__m128i_result1) = 0x0000000100000001; ++ *((unsigned long *)&__m128i_result0) = 0x0000000100000000; ++ __m128i_out = __lsx_vdiv_w (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x4f804f804f804f80; ++ *((unsigned long *)&__m128i_op10) = 0x4f804f804f804f80; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000;
View file
_service:tar_scm:LoongArch-Add-tests-for-SX-vector-vexth-vextl-vldi-v.patch
Added
@@ -0,0 +1,1664 @@ +From ed55869f2ae380ac36d09746e7e04ce675e197b0 Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Mon, 11 Sep 2023 18:44:16 +0800 +Subject: PATCH 086/124 LoongArch: Add tests for SX vector + vexth/vextl/vldi/vneg/vsat instructions. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/vector/lsx/lsx-vexth-1.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vexth-2.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vextl-1.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vextl-2.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vldi.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vneg.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vsat-1.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vsat-2.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/vector/lsx/lsx-vexth-1.c | 342 ++++++++++++++++++ + .../loongarch/vector/lsx/lsx-vexth-2.c | 182 ++++++++++ + .../loongarch/vector/lsx/lsx-vextl-1.c | 83 +++++ + .../loongarch/vector/lsx/lsx-vextl-2.c | 83 +++++ + .../loongarch/vector/lsx/lsx-vldi.c | 61 ++++ + .../loongarch/vector/lsx/lsx-vneg.c | 321 ++++++++++++++++ + .../loongarch/vector/lsx/lsx-vsat-1.c | 231 ++++++++++++ + .../loongarch/vector/lsx/lsx-vsat-2.c | 272 ++++++++++++++ + 8 files changed, 1575 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vexth-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vexth-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vextl-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vextl-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vldi.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vneg.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsat-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsat-2.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vexth-1.c b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vexth-1.c +new file mode 100644 +index 000000000..f6390800d +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vexth-1.c +@@ -0,0 +1,342 @@ ++/* { dg-do run } */ ++/* { dg-options "-mlsx -w -fno-strict-aliasing" } */ ++#include "../simd_correctness_check.h" ++#include <lsxintrin.h> ++ ++int ++main () ++{ ++ __m128i __m128i_op0, __m128i_op1, __m128i_op2, __m128i_out, __m128i_result; ++ __m128 __m128_op0, __m128_op1, __m128_op2, __m128_out, __m128_result; ++ __m128d __m128d_op0, __m128d_op1, __m128d_op2, __m128d_out, __m128d_result; ++ ++ int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail; ++ long int long_op0, long_op1, long_op2, lont_out, lont_result; ++ long int long_int_out, long_int_result; ++ unsigned int unsigned_int_out, unsigned_int_result; ++ unsigned long int unsigned_long_int_out, unsigned_long_int_result; ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vexth_h_b (__m128i_op0); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x7fff000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x007fffff00000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vexth_h_b (__m128i_op0); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op00) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_result1) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_result0) = 0xffffffffffffffff; ++ __m128i_out = __lsx_vexth_h_b (__m128i_op0); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vexth_h_b (__m128i_op0); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x000000000000f909; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vexth_h_b (__m128i_op0); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x000000000000ffff; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vexth_h_b (__m128i_op0); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op00) = 0xffffffffff01ff01; ++ *((unsigned long *)&__m128i_result1) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_result0) = 0xffffffffffffffff; ++ __m128i_out = __lsx_vexth_h_b (__m128i_op0); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vexth_h_b (__m128i_op0); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op00) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_result1) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_result0) = 0xffffffffffffffff; ++ __m128i_out = __lsx_vexth_h_b (__m128i_op0); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vexth_h_b (__m128i_op0); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vexth_h_b (__m128i_op0); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vexth_h_b (__m128i_op0); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vexth_h_b (__m128i_op0); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vexth_h_b (__m128i_op0); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vexth_h_b (__m128i_op0); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vexth_h_b (__m128i_op0); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vexth_h_b (__m128i_op0); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x1010111105050000; ++ *((unsigned long *)&__m128i_op00) = 0x4040000041410101; ++ *((unsigned long *)&__m128i_result1) = 0x0010001000110011; ++ *((unsigned long *)&__m128i_result0) = 0x0005000500000000; ++ __m128i_out = __lsx_vexth_h_b (__m128i_op0); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x00000000000003e2; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x000000000003ffe2; ++ __m128i_out = __lsx_vexth_h_b (__m128i_op0); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0xfffffffffffffffe; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_result0) = 0xfffffffffffffffe;
View file
_service:tar_scm:LoongArch-Add-tests-for-SX-vector-vfcmp-instructions.patch
Added
@@ -0,0 +1,5295 @@ +From 8cea23eb3f7e7aee77d0cf87581754c017691b91 Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Tue, 12 Sep 2023 11:31:16 +0800 +Subject: PATCH 095/124 LoongArch: Add tests for SX vector vfcmp + instructions. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/vector/lsx/lsx-vfcmp_caf.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vfcmp_ceq.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vfcmp_cle.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vfcmp_clt.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vfcmp_cne.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vfcmp_cor.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vfcmp_cun.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vfcmp_saf.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vfcmp_seq.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vfcmp_sle.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vfcmp_slt.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vfcmp_sne.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vfcmp_sor.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vfcmp_sun.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/vector/lsx/lsx-vfcmp_caf.c | 244 ++++++++ + .../loongarch/vector/lsx/lsx-vfcmp_ceq.c | 516 +++++++++++++++++ + .../loongarch/vector/lsx/lsx-vfcmp_cle.c | 530 ++++++++++++++++++ + .../loongarch/vector/lsx/lsx-vfcmp_clt.c | 476 ++++++++++++++++ + .../loongarch/vector/lsx/lsx-vfcmp_cne.c | 378 +++++++++++++ + .../loongarch/vector/lsx/lsx-vfcmp_cor.c | 170 ++++++ + .../loongarch/vector/lsx/lsx-vfcmp_cun.c | 253 +++++++++ + .../loongarch/vector/lsx/lsx-vfcmp_saf.c | 214 +++++++ + .../loongarch/vector/lsx/lsx-vfcmp_seq.c | 450 +++++++++++++++ + .../loongarch/vector/lsx/lsx-vfcmp_sle.c | 407 ++++++++++++++ + .../loongarch/vector/lsx/lsx-vfcmp_slt.c | 512 +++++++++++++++++ + .../loongarch/vector/lsx/lsx-vfcmp_sne.c | 398 +++++++++++++ + .../loongarch/vector/lsx/lsx-vfcmp_sor.c | 269 +++++++++ + .../loongarch/vector/lsx/lsx-vfcmp_sun.c | 335 +++++++++++ + 14 files changed, 5152 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcmp_caf.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcmp_ceq.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcmp_cle.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcmp_clt.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcmp_cne.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcmp_cor.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcmp_cun.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcmp_saf.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcmp_seq.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcmp_sle.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcmp_slt.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcmp_sne.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcmp_sor.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcmp_sun.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcmp_caf.c b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcmp_caf.c +new file mode 100644 +index 000000000..b448c2076 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcmp_caf.c +@@ -0,0 +1,244 @@ ++/* { dg-do run } */ ++/* { dg-options "-mlsx -w -fno-strict-aliasing" } */ ++#include "../simd_correctness_check.h" ++#include <lsxintrin.h> ++ ++int ++main () ++{ ++ __m128i __m128i_op0, __m128i_op1, __m128i_op2, __m128i_out, __m128i_result; ++ __m128 __m128_op0, __m128_op1, __m128_op2, __m128_out, __m128_result; ++ __m128d __m128d_op0, __m128d_op1, __m128d_op2, __m128d_out, __m128d_result; ++ ++ int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail; ++ long int long_op0, long_op1, long_op2, lont_out, lont_result; ++ long int long_int_out, long_int_result; ++ unsigned int unsigned_int_out, unsigned_int_result; ++ unsigned long int unsigned_long_int_out, unsigned_long_int_result; ++ ++ *((int *)&__m128_op03) = 0x00000000; ++ *((int *)&__m128_op02) = 0x00000000; ++ *((int *)&__m128_op01) = 0x01010101; ++ *((int *)&__m128_op00) = 0x01010101; ++ *((int *)&__m128_op13) = 0x00000000; ++ *((int *)&__m128_op12) = 0x00000000; ++ *((int *)&__m128_op11) = 0x00000000; ++ *((int *)&__m128_op10) = 0x00000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vfcmp_caf_s (__m128_op0, __m128_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((int *)&__m128_op03) = 0x7ef400ad; ++ *((int *)&__m128_op02) = 0x21fc7081; ++ *((int *)&__m128_op01) = 0x28bf0351; ++ *((int *)&__m128_op00) = 0xec69b5f2; ++ *((int *)&__m128_op13) = 0xff800000; ++ *((int *)&__m128_op12) = 0xff800000; ++ *((int *)&__m128_op11) = 0xff800000; ++ *((int *)&__m128_op10) = 0x7fc00000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vfcmp_caf_s (__m128_op0, __m128_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((int *)&__m128_op03) = 0x00000000; ++ *((int *)&__m128_op02) = 0x00000000; ++ *((int *)&__m128_op01) = 0x00000000; ++ *((int *)&__m128_op00) = 0x00000000; ++ *((int *)&__m128_op13) = 0x00000000; ++ *((int *)&__m128_op12) = 0x00000000; ++ *((int *)&__m128_op11) = 0x00000000; ++ *((int *)&__m128_op10) = 0x00000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vfcmp_caf_s (__m128_op0, __m128_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((int *)&__m128_op03) = 0x00000000; ++ *((int *)&__m128_op02) = 0x00000000; ++ *((int *)&__m128_op01) = 0x01000100; ++ *((int *)&__m128_op00) = 0x01000100; ++ *((int *)&__m128_op13) = 0xffffffff; ++ *((int *)&__m128_op12) = 0xffffffff; ++ *((int *)&__m128_op11) = 0x64e464e4; ++ *((int *)&__m128_op10) = 0x64e464e4; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vfcmp_caf_s (__m128_op0, __m128_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((int *)&__m128_op03) = 0x00000000; ++ *((int *)&__m128_op02) = 0x00000000; ++ *((int *)&__m128_op01) = 0x00000000; ++ *((int *)&__m128_op00) = 0x00000000; ++ *((int *)&__m128_op13) = 0xffc0ff80; ++ *((int *)&__m128_op12) = 0xff800000; ++ *((int *)&__m128_op11) = 0x00000000; ++ *((int *)&__m128_op10) = 0x00000005; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vfcmp_caf_s (__m128_op0, __m128_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((int *)&__m128_op03) = 0x00000000; ++ *((int *)&__m128_op02) = 0x00000000; ++ *((int *)&__m128_op01) = 0x00000000; ++ *((int *)&__m128_op00) = 0x00000000; ++ *((int *)&__m128_op13) = 0x00000000; ++ *((int *)&__m128_op12) = 0x00000000; ++ *((int *)&__m128_op11) = 0x00000000; ++ *((int *)&__m128_op10) = 0x00000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vfcmp_caf_s (__m128_op0, __m128_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((int *)&__m128_op03) = 0x00000000; ++ *((int *)&__m128_op02) = 0x00000000; ++ *((int *)&__m128_op01) = 0xffffffff; ++ *((int *)&__m128_op00) = 0xc0800000; ++ *((int *)&__m128_op13) = 0x0000001b; ++ *((int *)&__m128_op12) = 0x0000001b; ++ *((int *)&__m128_op11) = 0x0000001b; ++ *((int *)&__m128_op10) = 0x0000001b; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vfcmp_caf_s (__m128_op0, __m128_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((int *)&__m128_op03) = 0x00000002; ++ *((int *)&__m128_op02) = 0x00000000; ++ *((int *)&__m128_op01) = 0x00000002; ++ *((int *)&__m128_op00) = 0x00000000; ++ *((int *)&__m128_op13) = 0x00000000; ++ *((int *)&__m128_op12) = 0x00000000; ++ *((int *)&__m128_op11) = 0x34500292; ++ *((int *)&__m128_op10) = 0x0f3017d6; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vfcmp_caf_s (__m128_op0, __m128_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((int *)&__m128_op03) = 0x00000000; ++ *((int *)&__m128_op02) = 0x00000000; ++ *((int *)&__m128_op01) = 0x00830029; ++ *((int *)&__m128_op00) = 0x0038ff50; ++ *((int *)&__m128_op13) = 0x00000000; ++ *((int *)&__m128_op12) = 0x00000000; ++ *((int *)&__m128_op11) = 0x00000000; ++ *((int *)&__m128_op10) = 0x00000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vfcmp_caf_s (__m128_op0, __m128_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((int *)&__m128_op03) = 0xff7fff80; ++ *((int *)&__m128_op02) = 0xff800001;
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_service:tar_scm:LoongArch-Add-tests-for-SX-vector-vfmadd-vfnmadd-vld.patch
Added
@@ -0,0 +1,1412 @@ +From 5cc6bce7753e1029149839d58ed81f046087ad31 Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Tue, 12 Sep 2023 15:05:09 +0800 +Subject: PATCH 098/124 LoongArch: Add tests for SX vector + vfmadd/vfnmadd/vld/vst instructions. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/vector/lsx/lsx-vfmadd_d.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vfmadd_s.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vfnmadd_d.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vfnmadd_s.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vld.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vst.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/vector/lsx/lsx-vfmadd_d.c | 251 ++++++++++++ + .../loongarch/vector/lsx/lsx-vfmadd_s.c | 381 ++++++++++++++++++ + .../loongarch/vector/lsx/lsx-vfnmadd_d.c | 196 +++++++++ + .../loongarch/vector/lsx/lsx-vfnmadd_s.c | 381 ++++++++++++++++++ + .../gcc.target/loongarch/vector/lsx/lsx-vld.c | 62 +++ + .../gcc.target/loongarch/vector/lsx/lsx-vst.c | 70 ++++ + 6 files changed, 1341 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfmadd_d.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfmadd_s.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfnmadd_d.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfnmadd_s.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vld.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vst.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfmadd_d.c b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfmadd_d.c +new file mode 100644 +index 000000000..c5de1ac7a +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfmadd_d.c +@@ -0,0 +1,251 @@ ++/* { dg-do run } */ ++/* { dg-options "-mlsx -w -fno-strict-aliasing" } */ ++#include "../simd_correctness_check.h" ++#include <lsxintrin.h> ++ ++int ++main () ++{ ++ __m128i __m128i_op0, __m128i_op1, __m128i_op2, __m128i_out, __m128i_result; ++ __m128 __m128_op0, __m128_op1, __m128_op2, __m128_out, __m128_result; ++ __m128d __m128d_op0, __m128d_op1, __m128d_op2, __m128d_out, __m128d_result; ++ ++ int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail; ++ long int long_op0, long_op1, long_op2, lont_out, lont_result; ++ long int long_int_out, long_int_result; ++ unsigned int unsigned_int_out, unsigned_int_result; ++ unsigned long int unsigned_long_int_out, unsigned_long_int_result; ++ ++ *((unsigned long *)&__m128d_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op11) = 0x8a228acac14e440a; ++ *((unsigned long *)&__m128d_op10) = 0xc77c47cdc0f16549; ++ *((unsigned long *)&__m128d_op21) = 0xffffffffd24271c4; ++ *((unsigned long *)&__m128d_op20) = 0x2711bad1e8e309ed; ++ *((unsigned long *)&__m128d_result1) = 0xffffffffd24271c4; ++ *((unsigned long *)&__m128d_result0) = 0x2711bad1e8e309ed; ++ __m128d_out = __lsx_vfmadd_d (__m128d_op0, __m128d_op1, __m128d_op2); ++ ASSERTEQ_64 (__LINE__, __m128d_result, __m128d_out); ++ ++ *((unsigned long *)&__m128d_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op11) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128d_op10) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128d_op21) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128d_op20) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128d_result1) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128d_result0) = 0xffffffffffffffff; ++ __m128d_out = __lsx_vfmadd_d (__m128d_op0, __m128d_op1, __m128d_op2); ++ ASSERTEQ_64 (__LINE__, __m128d_result, __m128d_out); ++ ++ *((unsigned long *)&__m128d_op01) = 0x0000040400000383; ++ *((unsigned long *)&__m128d_op00) = 0xffffe000ffff1fff; ++ *((unsigned long *)&__m128d_op11) = 0x0000040400000383; ++ *((unsigned long *)&__m128d_op10) = 0xffffe000ffff1fff; ++ *((unsigned long *)&__m128d_op21) = 0x0000000001000001; ++ *((unsigned long *)&__m128d_op20) = 0x0001000100000000; ++ *((unsigned long *)&__m128d_result1) = 0x0000000001000001; ++ *((unsigned long *)&__m128d_result0) = 0xffffe000ffff1fff; ++ __m128d_out = __lsx_vfmadd_d (__m128d_op0, __m128d_op1, __m128d_op2); ++ ASSERTEQ_64 (__LINE__, __m128d_result, __m128d_out); ++ ++ *((unsigned long *)&__m128d_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op11) = 0x00000000003f80b0; ++ *((unsigned long *)&__m128d_op10) = 0x00000000ff800000; ++ *((unsigned long *)&__m128d_op21) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128d_op20) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128d_result1) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128d_result0) = 0xffffffffffffffff; ++ __m128d_out = __lsx_vfmadd_d (__m128d_op0, __m128d_op1, __m128d_op2); ++ ASSERTEQ_64 (__LINE__, __m128d_result, __m128d_out); ++ ++ *((unsigned long *)&__m128d_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op00) = 0x0080200000000000; ++ *((unsigned long *)&__m128d_op11) = 0x0000000000401000; ++ *((unsigned long *)&__m128d_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op21) = 0x0000080000000000; ++ *((unsigned long *)&__m128d_op20) = 0x0000080000000000; ++ *((unsigned long *)&__m128d_result1) = 0x0000080000000000; ++ *((unsigned long *)&__m128d_result0) = 0x0000080000000000; ++ __m128d_out = __lsx_vfmadd_d (__m128d_op0, __m128d_op1, __m128d_op2); ++ ASSERTEQ_64 (__LINE__, __m128d_result, __m128d_out); ++ ++ *((unsigned long *)&__m128d_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op21) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op20) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_result0) = 0x0000000000000000; ++ __m128d_out = __lsx_vfmadd_d (__m128d_op0, __m128d_op1, __m128d_op2); ++ ASSERTEQ_64 (__LINE__, __m128d_result, __m128d_out); ++ ++ *((unsigned long *)&__m128d_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op10) = 0x000000000000001e; ++ *((unsigned long *)&__m128d_op21) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op20) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_result0) = 0x0000000000000000; ++ __m128d_out = __lsx_vfmadd_d (__m128d_op0, __m128d_op1, __m128d_op2); ++ ASSERTEQ_64 (__LINE__, __m128d_result, __m128d_out); ++ ++ *((unsigned long *)&__m128d_op01) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128d_op00) = 0x7fff7fff7fff7fff; ++ *((unsigned long *)&__m128d_op11) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128d_op10) = 0x3fff3fff3fff3fff; ++ *((unsigned long *)&__m128d_op21) = 0xfffb00fdfdf7ffff; ++ *((unsigned long *)&__m128d_op20) = 0xfff8000000000000; ++ *((unsigned long *)&__m128d_result1) = 0xfffb00fdfdf7ffff; ++ *((unsigned long *)&__m128d_result0) = 0xfff8000000000000; ++ __m128d_out = __lsx_vfmadd_d (__m128d_op0, __m128d_op1, __m128d_op2); ++ ASSERTEQ_64 (__LINE__, __m128d_result, __m128d_out); ++ ++ *((unsigned long *)&__m128d_op01) = 0x8000000000000000; ++ *((unsigned long *)&__m128d_op00) = 0x8000000000000000; ++ *((unsigned long *)&__m128d_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op21) = 0x0000000009000900; ++ *((unsigned long *)&__m128d_op20) = 0x0000000009000900; ++ *((unsigned long *)&__m128d_result1) = 0x0000000009000900; ++ *((unsigned long *)&__m128d_result0) = 0x0000000009000900; ++ __m128d_out = __lsx_vfmadd_d (__m128d_op0, __m128d_op1, __m128d_op2); ++ ASSERTEQ_64 (__LINE__, __m128d_result, __m128d_out); ++ ++ *((unsigned long *)&__m128d_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op00) = 0x0000000200000002; ++ *((unsigned long *)&__m128d_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op10) = 0x0000000200000002; ++ *((unsigned long *)&__m128d_op21) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128d_op20) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128d_result1) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128d_result0) = 0xffffffffffffffff; ++ __m128d_out = __lsx_vfmadd_d (__m128d_op0, __m128d_op1, __m128d_op2); ++ ASSERTEQ_64 (__LINE__, __m128d_result, __m128d_out); ++ ++ *((unsigned long *)&__m128d_op01) = 0x9c83e21a22001818; ++ *((unsigned long *)&__m128d_op00) = 0xdd3b8b02563b2d7b; ++ *((unsigned long *)&__m128d_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op10) = 0x7f7f7f007f7f7f00; ++ *((unsigned long *)&__m128d_op21) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op20) = 0x7f7f7f007f7f7f00; ++ *((unsigned long *)&__m128d_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_result0) = 0xfff0000000000000; ++ __m128d_out = __lsx_vfmadd_d (__m128d_op0, __m128d_op1, __m128d_op2); ++ ASSERTEQ_64 (__LINE__, __m128d_result, __m128d_out); ++ ++ *((unsigned long *)&__m128d_op01) = 0xff00e400ff00e400; ++ *((unsigned long *)&__m128d_op00) = 0xff01e41ffff0ffff; ++ *((unsigned long *)&__m128d_op11) = 0x5555000054100000; ++ *((unsigned long *)&__m128d_op10) = 0x5555000154100155; ++ *((unsigned long *)&__m128d_op21) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op20) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_result1) = 0xfff0000000000000; ++ *((unsigned long *)&__m128d_result0) = 0xfff0000000000000; ++ __m128d_out = __lsx_vfmadd_d (__m128d_op0, __m128d_op1, __m128d_op2); ++ ASSERTEQ_64 (__LINE__, __m128d_result, __m128d_out); ++ ++ *((unsigned long *)&__m128d_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op00) = 0x0000000000000010; ++ *((unsigned long *)&__m128d_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op21) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_op20) = 0x0000000000000010; ++ *((unsigned long *)&__m128d_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128d_result0) = 0x8000000000000010; ++ __m128d_out = __lsx_vfmsub_d (__m128d_op0, __m128d_op1, __m128d_op2); ++ ASSERTEQ_64 (__LINE__, __m128d_result, __m128d_out); ++
View file
_service:tar_scm:LoongArch-Add-tests-for-SX-vector-vfrstp-vfrstpi-vse.patch
Added
@@ -0,0 +1,3926 @@ +From 06a477566d282d87ce187901904c4bae2c2c4aaf Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Tue, 12 Sep 2023 11:28:29 +0800 +Subject: PATCH 094/124 LoongArch: Add tests for SX vector + vfrstp/vfrstpi/vseq/vseqi/vsle /vslei/vslt/vslti instructions. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/vector/lsx/lsx-vfrstp.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vfrstpi.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vseq.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vseqi.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vsle-1.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vsle-2.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vslei-1.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vslei-2.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vslt-1.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vslt-2.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vslti-1.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vslti-2.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/vector/lsx/lsx-vfrstp.c | 218 ++++++++ + .../loongarch/vector/lsx/lsx-vfrstpi.c | 209 ++++++++ + .../loongarch/vector/lsx/lsx-vseq.c | 470 ++++++++++++++++++ + .../loongarch/vector/lsx/lsx-vseqi.c | 328 ++++++++++++ + .../loongarch/vector/lsx/lsx-vsle-1.c | 290 +++++++++++ + .../loongarch/vector/lsx/lsx-vsle-2.c | 444 +++++++++++++++++ + .../loongarch/vector/lsx/lsx-vslei-1.c | 258 ++++++++++ + .../loongarch/vector/lsx/lsx-vslei-2.c | 293 +++++++++++ + .../loongarch/vector/lsx/lsx-vslt-1.c | 434 ++++++++++++++++ + .../loongarch/vector/lsx/lsx-vslt-2.c | 236 +++++++++ + .../loongarch/vector/lsx/lsx-vslti-1.c | 328 ++++++++++++ + .../loongarch/vector/lsx/lsx-vslti-2.c | 293 +++++++++++ + 12 files changed, 3801 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfrstp.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfrstpi.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vseq.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vseqi.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsle-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsle-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vslei-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vslei-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vslt-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vslt-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vslti-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vslti-2.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfrstp.c b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfrstp.c +new file mode 100644 +index 000000000..ac0ade8b1 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfrstp.c +@@ -0,0 +1,218 @@ ++/* { dg-do run } */ ++/* { dg-options "-mlsx -w -fno-strict-aliasing" } */ ++#include "../simd_correctness_check.h" ++#include <lsxintrin.h> ++ ++int ++main () ++{ ++ __m128i __m128i_op0, __m128i_op1, __m128i_op2, __m128i_out, __m128i_result; ++ __m128 __m128_op0, __m128_op1, __m128_op2, __m128_out, __m128_result; ++ __m128d __m128d_op0, __m128d_op1, __m128d_op2, __m128d_out, __m128d_result; ++ ++ int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail; ++ long int long_op0, long_op1, long_op2, lont_out, lont_result; ++ long int long_int_out, long_int_result; ++ unsigned int unsigned_int_out, unsigned_int_result; ++ unsigned long int unsigned_long_int_out, unsigned_long_int_result; ++ ++ *((unsigned long *)&__m128i_op01) = 0xfe07e5fefefdddfe; ++ *((unsigned long *)&__m128i_op00) = 0x00020100fedd0c00; ++ *((unsigned long *)&__m128i_op11) = 0x0005000501800005; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op21) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op20) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0xfe07e5fefefdddfe; ++ *((unsigned long *)&__m128i_result0) = 0x00020100fedd0008; ++ __m128i_out = __lsx_vfrstp_h (__m128i_op0, __m128i_op1, __m128i_op2); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0404038383838404; ++ *((unsigned long *)&__m128i_op10) = 0x0404038383838404; ++ *((unsigned long *)&__m128i_op21) = 0x03ff03ff03ff03ff; ++ *((unsigned long *)&__m128i_op20) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000001; ++ __m128i_out = __lsx_vfrstp_b (__m128i_op0, __m128i_op1, __m128i_op2); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000200010; ++ *((unsigned long *)&__m128i_op21) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op20) = 0x0000000000200010; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000010; ++ __m128i_out = __lsx_vfrstp_b (__m128i_op0, __m128i_op1, __m128i_op2); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op21) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op20) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000010; ++ __m128i_out = __lsx_vfrstp_b (__m128i_op0, __m128i_op1, __m128i_op2); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0e7ffffc01fffffc; ++ *((unsigned long *)&__m128i_op00) = 0x0000000003f803f4; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op21) = 0x0e7ffffc01fffffc; ++ *((unsigned long *)&__m128i_op20) = 0x0000000003f803f4; ++ *((unsigned long *)&__m128i_result1) = 0x0e7ffffc01fffffc; ++ *((unsigned long *)&__m128i_result0) = 0x0000001003f803f4; ++ __m128i_out = __lsx_vfrstp_b (__m128i_op0, __m128i_op1, __m128i_op2); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000800; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op21) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op20) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000800; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000010; ++ __m128i_out = __lsx_vfrstp_b (__m128i_op0, __m128i_op1, __m128i_op2); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000200000002; ++ *((unsigned long *)&__m128i_op00) = 0x000000020000007d; ++ *((unsigned long *)&__m128i_op11) = 0x0000746400016388; ++ *((unsigned long *)&__m128i_op10) = 0x0000586100015567; ++ *((unsigned long *)&__m128i_op21) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op20) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_result1) = 0x0800000200000002; ++ *((unsigned long *)&__m128i_result0) = 0x000000020000007d; ++ __m128i_out = __lsx_vfrstp_b (__m128i_op0, __m128i_op1, __m128i_op2); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op00) = 0xfffffffffffffffe; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op21) = 0x0000000000000010; ++ *((unsigned long *)&__m128i_op20) = 0x0000000000000010; ++ *((unsigned long *)&__m128i_result1) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_result0) = 0xffffffffffff0008; ++ __m128i_out = __lsx_vfrstp_h (__m128i_op0, __m128i_op1, __m128i_op2); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x00000000ffffffff; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x00000000ffffffff; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op21) = 0x7ff0000000000000; ++ *((unsigned long *)&__m128i_op20) = 0x61608654a2d4f6da; ++ *((unsigned long *)&__m128i_result1) = 0x00000000ff08ffff; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vfrstp_b (__m128i_op0, __m128i_op1, __m128i_op2); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x36fbdfdcffdcffdc; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000008140c80; ++ *((unsigned long *)&__m128i_op21) = 0x1f1f1f1f1f1f1f00; ++ *((unsigned long *)&__m128i_op20) = 0x1f1f1f27332b9f00; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x36fbdfdcffdc0008; ++ __m128i_out = __lsx_vfrstp_h (__m128i_op0, __m128i_op1, __m128i_op2); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x000000000000aaaa; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x00000000545cab1d; ++ *((unsigned long *)&__m128i_op10) = 0x0000000081a83bea; ++ *((unsigned long *)&__m128i_op21) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op20) = 0x00d3007c014e00bd; ++ *((unsigned long *)&__m128i_result1) = 0x000000000000aaaa; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vfrstp_b (__m128i_op0, __m128i_op1, __m128i_op2); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x37c0001000000000; ++ *((unsigned long *)&__m128i_op00) = 0x37c0001000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000003a0000003a;
View file
_service:tar_scm:LoongArch-Add-tests-for-SX-vector-vmax-vmaxi-vmin-vm.patch
Added
@@ -0,0 +1,2578 @@ +From dd0b9d05c2e18dc8082931dbfe612bb1acf9e5e9 Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Mon, 11 Sep 2023 18:38:46 +0800 +Subject: PATCH 085/124 LoongArch: Add tests for SX vector + vmax/vmaxi/vmin/vmini instructions. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/vector/lsx/lsx-vmax-1.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vmax-2.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vmaxi-1.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vmaxi-2.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vmin-1.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vmin-2.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vmini-1.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vmini-2.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/vector/lsx/lsx-vmax-1.c | 317 +++++++++++++ + .../loongarch/vector/lsx/lsx-vmax-2.c | 362 +++++++++++++++ + .../loongarch/vector/lsx/lsx-vmaxi-1.c | 279 +++++++++++ + .../loongarch/vector/lsx/lsx-vmaxi-2.c | 223 +++++++++ + .../loongarch/vector/lsx/lsx-vmin-1.c | 434 ++++++++++++++++++ + .../loongarch/vector/lsx/lsx-vmin-2.c | 344 ++++++++++++++ + .../loongarch/vector/lsx/lsx-vmini-1.c | 314 +++++++++++++ + .../loongarch/vector/lsx/lsx-vmini-2.c | 216 +++++++++ + 8 files changed, 2489 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmax-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmax-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmaxi-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmaxi-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmin-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmin-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmini-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmini-2.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmax-1.c b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmax-1.c +new file mode 100644 +index 000000000..b0e22f955 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmax-1.c +@@ -0,0 +1,317 @@ ++/* { dg-do run } */ ++/* { dg-options "-mlsx -w -fno-strict-aliasing" } */ ++#include "../simd_correctness_check.h" ++#include <lsxintrin.h> ++ ++int ++main () ++{ ++ __m128i __m128i_op0, __m128i_op1, __m128i_op2, __m128i_out, __m128i_result; ++ __m128 __m128_op0, __m128_op1, __m128_op2, __m128_out, __m128_result; ++ __m128d __m128d_op0, __m128d_op1, __m128d_op2, __m128d_out, __m128d_result; ++ ++ int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail; ++ long int long_op0, long_op1, long_op2, lont_out, lont_result; ++ long int long_int_out, long_int_result; ++ unsigned int unsigned_int_out, unsigned_int_result; ++ unsigned long int unsigned_long_int_out, unsigned_long_int_result; ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000ffff00000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vmax_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op00) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op11) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op10) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_result1) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_result0) = 0xffffffffffffffff; ++ __m128i_out = __lsx_vmax_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vmax_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x7fff7fff7fff7fff; ++ *((unsigned long *)&__m128i_op00) = 0x000000010000003f; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x7f007f007f007f00; ++ *((unsigned long *)&__m128i_result0) = 0x000000010000003f; ++ __m128i_out = __lsx_vmax_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000001; ++ *((unsigned long *)&__m128i_op11) = 0xfffff00010000fff; ++ *((unsigned long *)&__m128i_op10) = 0xfffff00010000fff; ++ *((unsigned long *)&__m128i_result1) = 0x0000000010000f00; ++ *((unsigned long *)&__m128i_result0) = 0x0000000010000f01; ++ __m128i_out = __lsx_vmax_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0xfffcfffcfffcfffd; ++ *((unsigned long *)&__m128i_op00) = 0xfffcfffdfffcfffd; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vmax_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0xffff80df00000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0010100000100000; ++ *((unsigned long *)&__m128i_op10) = 0x1000100000101000; ++ *((unsigned long *)&__m128i_result1) = 0x0010100000100000; ++ *((unsigned long *)&__m128i_result0) = 0x1000100000101000; ++ __m128i_out = __lsx_vmax_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vmax_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0040000000ff00ff; ++ *((unsigned long *)&__m128i_op00) = 0x0040000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0040000000ff00ff; ++ *((unsigned long *)&__m128i_result0) = 0x0040000000000000; ++ __m128i_out = __lsx_vmax_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op00) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vmax_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000001000001; ++ *((unsigned long *)&__m128i_op10) = 0x0001000100000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000001000001; ++ *((unsigned long *)&__m128i_result0) = 0x0001000100000000; ++ __m128i_out = __lsx_vmax_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vmax_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op00) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op11) = 0xb327b9363c992b2e; ++ *((unsigned long *)&__m128i_op10) = 0xa1e7b475d925730f; ++ *((unsigned long *)&__m128i_result1) = 0xffffffff3c992b2e; ++ *((unsigned long *)&__m128i_result0) = 0xffffffffffff730f; ++ __m128i_out = __lsx_vmax_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x4101010141010100; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x00000000000001ff; ++ *((unsigned long *)&__m128i_result1) = 0x4101010141010100; ++ *((unsigned long *)&__m128i_result0) = 0x00000000000001ff; ++ __m128i_out = __lsx_vmax_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vmax_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000;
View file
_service:tar_scm:LoongArch-Add-tests-for-SX-vector-vrotr-vrotri-vsra-.patch
Added
@@ -0,0 +1,3173 @@ +From 67c36add58d634551a200f1473be3c7368530da1 Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Tue, 12 Sep 2023 11:13:32 +0800 +Subject: PATCH 090/124 LoongArch: Add tests for SX vector + vrotr/vrotri/vsra/vsrai/vsran/vsrani /vsrarn/vsrarni instructions. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/vector/lsx/lsx-vrotr.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vrotri.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vsra.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vsrai.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vsran.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vsrani.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vsrar.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vsrari.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vsrarn.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vsrarni.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/vector/lsx/lsx-vrotr.c | 381 +++++++++++++++++ + .../loongarch/vector/lsx/lsx-vrotri.c | 294 +++++++++++++ + .../loongarch/vector/lsx/lsx-vsra.c | 344 +++++++++++++++ + .../loongarch/vector/lsx/lsx-vsrai.c | 258 ++++++++++++ + .../loongarch/vector/lsx/lsx-vsran.c | 290 +++++++++++++ + .../loongarch/vector/lsx/lsx-vsrani.c | 246 +++++++++++ + .../loongarch/vector/lsx/lsx-vsrar.c | 354 ++++++++++++++++ + .../loongarch/vector/lsx/lsx-vsrari.c | 265 ++++++++++++ + .../loongarch/vector/lsx/lsx-vsrarn.c | 236 +++++++++++ + .../loongarch/vector/lsx/lsx-vsrarni.c | 398 ++++++++++++++++++ + 10 files changed, 3066 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vrotr.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vrotri.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsra.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsrai.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsran.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsrani.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsrar.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsrari.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsrarn.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsrarni.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vrotr.c b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vrotr.c +new file mode 100644 +index 000000000..c42440cea +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vrotr.c +@@ -0,0 +1,381 @@ ++/* { dg-do run } */ ++/* { dg-options "-mlsx -w -fno-strict-aliasing" } */ ++#include "../simd_correctness_check.h" ++#include <lsxintrin.h> ++ ++int ++main () ++{ ++ __m128i __m128i_op0, __m128i_op1, __m128i_op2, __m128i_out, __m128i_result; ++ __m128 __m128_op0, __m128_op1, __m128_op2, __m128_out, __m128_result; ++ __m128d __m128d_op0, __m128d_op1, __m128d_op2, __m128d_out, __m128d_result; ++ ++ int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail; ++ long int long_op0, long_op1, long_op2, lont_out, lont_result; ++ long int long_int_out, long_int_result; ++ unsigned int unsigned_int_out, unsigned_int_result; ++ unsigned long int unsigned_long_int_out, unsigned_long_int_result; ++ ++ *((unsigned long *)&__m128i_op01) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vrotr_w (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vrotr_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000001; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vrotr_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0xfffefffefffffffc; ++ *((unsigned long *)&__m128i_op11) = 0x2001240128032403; ++ *((unsigned long *)&__m128i_op10) = 0x288b248c00010401; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0xffdfffefffff7ffe; ++ __m128i_out = __lsx_vrotr_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ unsigned_int_out = __lsx_vpickve2gr_hu (__m128i_op0, 0x5); ++ *((unsigned long *)&__m128i_op01) = 0x2700000000002727; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000002727; ++ *((unsigned long *)&__m128i_op11) = 0x697eba2bedfa9c82; ++ *((unsigned long *)&__m128i_op10) = 0xd705c77a7025c899; ++ *((unsigned long *)&__m128i_result1) = 0xc9c00000000009c9; ++ *((unsigned long *)&__m128i_result0) = 0x0013938000000000; ++ __m128i_out = __lsx_vrotr_d (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x1000000010000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000100100000; ++ *((unsigned long *)&__m128i_op11) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op10) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_result1) = 0x2000000020000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000200200000; ++ __m128i_out = __lsx_vrotr_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vrotr_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x10f917d72d3d01e4; ++ *((unsigned long *)&__m128i_op00) = 0x203e16d116de012b; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x10f917d72d3d01e4; ++ *((unsigned long *)&__m128i_result0) = 0x203e16d116de012b; ++ __m128i_out = __lsx_vrotr_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op00) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op11) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op10) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_result1) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_result0) = 0xffffffffffffffff; ++ __m128i_out = __lsx_vrotr_w (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000100000001; ++ *((unsigned long *)&__m128i_op10) = 0x0000000100000001; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vrotr_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x4f804f804f804f80; ++ *((unsigned long *)&__m128i_op00) = 0x4f804f804f804f80; ++ *((unsigned long *)&__m128i_op11) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op10) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_result1) = 0x9f009f009f009f00; ++ *((unsigned long *)&__m128i_result0) = 0x9f009f009f009f00; ++ __m128i_out = __lsx_vrotr_w (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x000000004fc04f81; ++ *((unsigned long *)&__m128i_op00) = 0x000000004fc04f80; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x000000004fc04f81; ++ *((unsigned long *)&__m128i_result0) = 0x000000004fc04f80; ++ __m128i_out = __lsx_vrotr_d (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000ff000000ff00; ++ *((unsigned long *)&__m128i_op11) = 0x00000000ffffffff; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000ff000000ff00; ++ __m128i_out = __lsx_vrotr_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000006f00001f0a; ++ *((unsigned long *)&__m128i_op00) = 0x0000958affff995d; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000006f00001f0a; ++ *((unsigned long *)&__m128i_result0) = 0x0000958affff995d; ++ __m128i_out = __lsx_vrotr_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x000000000000006f; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000001f0a; ++ *((unsigned long *)&__m128i_op11) = 0x000000000000006f; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000;
View file
_service:tar_scm:LoongArch-Add-tests-for-SX-vector-vsll-vslli-vsrl-vs.patch
Added
@@ -0,0 +1,4023 @@ +From 64d3c9507fdf2829659affdb7d0490e7b2888787 Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Tue, 12 Sep 2023 10:55:35 +0800 +Subject: PATCH 089/124 LoongArch: Add tests for SX vector + vsll/vslli/vsrl/vsrli/vsrln/vsrlni/vsrlr /vsrlri/vslrlrn/vsrlrni + instructions. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/vector/lsx/lsx-vsll.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vslli.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vsllwil-1.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vsllwil-2.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vsrl.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vsrli.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vsrln.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vsrlni.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vsrlr.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vsrlri.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vsrlrn.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vsrlrni.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/vector/lsx/lsx-vsll.c | 254 +++++++ + .../loongarch/vector/lsx/lsx-vslli.c | 293 ++++++++ + .../loongarch/vector/lsx/lsx-vsllwil-1.c | 244 +++++++ + .../loongarch/vector/lsx/lsx-vsllwil-2.c | 189 +++++ + .../loongarch/vector/lsx/lsx-vsrl.c | 389 ++++++++++ + .../loongarch/vector/lsx/lsx-vsrli.c | 328 +++++++++ + .../loongarch/vector/lsx/lsx-vsrln.c | 335 +++++++++ + .../loongarch/vector/lsx/lsx-vsrlni.c | 281 +++++++ + .../loongarch/vector/lsx/lsx-vsrlr.c | 434 +++++++++++ + .../loongarch/vector/lsx/lsx-vsrlri.c | 300 ++++++++ + .../loongarch/vector/lsx/lsx-vsrlrn.c | 164 +++++ + .../loongarch/vector/lsx/lsx-vsrlrni.c | 686 ++++++++++++++++++ + 12 files changed, 3897 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsll.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vslli.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsllwil-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsllwil-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsrl.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsrli.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsrln.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsrlni.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsrlr.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsrlri.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsrlrn.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsrlrni.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsll.c b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsll.c +new file mode 100644 +index 000000000..7b8ad7d5a +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsll.c +@@ -0,0 +1,254 @@ ++/* { dg-do run } */ ++/* { dg-options "-mlsx -w -fno-strict-aliasing" } */ ++#include "../simd_correctness_check.h" ++#include <lsxintrin.h> ++ ++int ++main () ++{ ++ __m128i __m128i_op0, __m128i_op1, __m128i_op2, __m128i_out, __m128i_result; ++ __m128 __m128_op0, __m128_op1, __m128_op2, __m128_out, __m128_result; ++ __m128d __m128d_op0, __m128d_op1, __m128d_op2, __m128d_out, __m128d_result; ++ ++ int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail; ++ long int long_op0, long_op1, long_op2, lont_out, lont_result; ++ long int long_int_out, long_int_result; ++ unsigned int unsigned_int_out, unsigned_int_result; ++ unsigned long int unsigned_long_int_out, unsigned_long_int_result; ++ ++ *((unsigned long *)&__m128i_op01) = 0x1dcc4255c9d85c05; ++ *((unsigned long *)&__m128i_op00) = 0x3ab7a3fc47a5c31a; ++ *((unsigned long *)&__m128i_op11) = 0x1dcc4255c9d85c05; ++ *((unsigned long *)&__m128i_op10) = 0x3ab7a3fc47a5c31a; ++ *((unsigned long *)&__m128i_result1) = 0xb9884ab93b0b80a0; ++ *((unsigned long *)&__m128i_result0) = 0xf11e970c68000000; ++ __m128i_out = __lsx_vsll_d (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0101010101010101; ++ *((unsigned long *)&__m128i_op00) = 0x0100000100010001; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0101010101010101; ++ *((unsigned long *)&__m128i_result0) = 0x0100000100010001; ++ __m128i_out = __lsx_vsll_d (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vsll_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vsll_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vsll_w (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vsll_w (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vsll_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vsll_w (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x00307028003f80b0; ++ *((unsigned long *)&__m128i_op00) = 0x0040007fff800000; ++ *((unsigned long *)&__m128i_op11) = 0xffffffc0ffffff81; ++ *((unsigned long *)&__m128i_op10) = 0xffff008000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0060e050007f0160; ++ *((unsigned long *)&__m128i_result0) = 0x0040007fff800000; ++ __m128i_out = __lsx_vsll_d (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000401000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000401000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vsll_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x3fffffff80000000; ++ *((unsigned long *)&__m128i_op00) = 0x00003ffd000a4000; ++ *((unsigned long *)&__m128i_op11) = 0xfffcffff00000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000fffd000a0000; ++ *((unsigned long *)&__m128i_result1) = 0xf000800080000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000a00028004000; ++ __m128i_out = __lsx_vsll_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x6b9fe3649c9d6363; ++ *((unsigned long *)&__m128i_op00) = 0x6363bc9e8b696363; ++ *((unsigned long *)&__m128i_op11) = 0x6b9fe3649c9d6363; ++ *((unsigned long *)&__m128i_op10) = 0x6363bc9e8b696363; ++ *((unsigned long *)&__m128i_result1) = 0xb9fe3640e4eb1b18; ++ *((unsigned long *)&__m128i_result0) = 0x800000005b4b1b18; ++ __m128i_out = __lsx_vsll_w (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op00) = 0x80001b155b4b0000; ++ *((unsigned long *)&__m128i_op11) = 0xffffffff00006c82; ++ *((unsigned long *)&__m128i_op10) = 0x00009b140000917b; ++ *((unsigned long *)&__m128i_result1) = 0x80000000fffffffc; ++ *((unsigned long *)&__m128i_result0) = 0xb150000000000000; ++ __m128i_out = __lsx_vsll_w (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vsll_h (__m128i_op0, __m128i_op1);
View file
_service:tar_scm:LoongArch-Add-tests-for-SX-vector-vssran-vssrani-vss.patch
Added
@@ -0,0 +1,4954 @@ +From 1009120c617c050d02a6d2abe786728dccf5cb5b Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Tue, 12 Sep 2023 11:17:38 +0800 +Subject: PATCH 091/124 LoongArch: Add tests for SX vector + vssran/vssrani/vssrarn/vssrarni/vssrln /vssrlni/vssrlrn/vssrlrni + instructions. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/vector/lsx/lsx-vssran.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vssrani.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vssrarn.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vssrarni.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vssrln.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vssrlni.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vssrlrn.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vssrlrni.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/vector/lsx/lsx-vssran.c | 390 ++++++++ + .../loongarch/vector/lsx/lsx-vssrani.c | 679 ++++++++++++++ + .../loongarch/vector/lsx/lsx-vssrarn.c | 669 ++++++++++++++ + .../loongarch/vector/lsx/lsx-vssrarni.c | 848 ++++++++++++++++++ + .../loongarch/vector/lsx/lsx-vssrln.c | 543 +++++++++++ + .../loongarch/vector/lsx/lsx-vssrlni.c | 668 ++++++++++++++ + .../loongarch/vector/lsx/lsx-vssrlrn.c | 470 ++++++++++ + .../loongarch/vector/lsx/lsx-vssrlrni.c | 597 ++++++++++++ + 8 files changed, 4864 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vssran.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vssrani.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vssrarn.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vssrarni.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vssrln.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vssrlni.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vssrlrn.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vssrlrni.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vssran.c b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vssran.c +new file mode 100644 +index 000000000..e45ca36f0 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vssran.c +@@ -0,0 +1,390 @@ ++/* { dg-do run } */ ++/* { dg-options "-mlsx -w -fno-strict-aliasing" } */ ++#include "../simd_correctness_check.h" ++#include <lsxintrin.h> ++ ++int ++main () ++{ ++ __m128i __m128i_op0, __m128i_op1, __m128i_op2, __m128i_out, __m128i_result; ++ __m128 __m128_op0, __m128_op1, __m128_op2, __m128_out, __m128_result; ++ __m128d __m128d_op0, __m128d_op1, __m128d_op2, __m128d_out, __m128d_result; ++ ++ int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail; ++ long int long_op0, long_op1, long_op2, lont_out, lont_result; ++ long int long_int_out, long_int_result; ++ unsigned int unsigned_int_out, unsigned_int_result; ++ unsigned long int unsigned_long_int_out, unsigned_long_int_result; ++ ++ *((unsigned long *)&__m128i_op01) = 0xbf8000000000ffff; ++ *((unsigned long *)&__m128i_op00) = 0xcf00000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vssran_wu_d (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op00) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op11) = 0x003f00000000003f; ++ *((unsigned long *)&__m128i_op10) = 0x003f000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vssran_bu_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vssran_w_d (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x000000017fff9000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000210011084; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vssran_b_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000001; ++ *((unsigned long *)&__m128i_op11) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op10) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vssran_h_w (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000001000001; ++ *((unsigned long *)&__m128i_op00) = 0x0001000100000000; ++ *((unsigned long *)&__m128i_op11) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op10) = 0xffffffc000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x000000007fff0000; ++ __m128i_out = __lsx_vssran_h_w (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0xfffffefffffffeff; ++ *((unsigned long *)&__m128i_op00) = 0xfffffffffffffcff; ++ *((unsigned long *)&__m128i_op11) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op10) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0xffffffffffffffff; ++ __m128i_out = __lsx_vssran_b_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x8000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x8000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x8000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x8000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x8000000080000000; ++ __m128i_out = __lsx_vssran_w_d (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vssran_b_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x02b504f305a5c091; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x02b504f305a5c091; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x00000000005602d2; ++ __m128i_out = __lsx_vssran_h_w (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x00000000003f80b0; ++ *((unsigned long *)&__m128i_op00) = 0x00000000ff800000; ++ *((unsigned long *)&__m128i_op11) = 0xb327b9363c992b2e; ++ *((unsigned long *)&__m128i_op10) = 0xa1e7b475d925730f; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x000000000001ff00; ++ __m128i_out = __lsx_vssran_wu_d (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op00) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op11) = 0x0060e050007f0160; ++ *((unsigned long *)&__m128i_op10) = 0x0040007fff800000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0xffffffffffffffff; ++ __m128i_out = __lsx_vssran_h_w (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x00ffffff00ff00ff; ++ *((unsigned long *)&__m128i_op00) = 0x00ff00ffffffffff; ++ *((unsigned long *)&__m128i_op11) = 0x1268f057137a0267; ++ *((unsigned long *)&__m128i_op10) = 0x0048137ef886fae0; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000100000000; ++ __m128i_out = __lsx_vssran_bu_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vssran_w_d (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0141010101410101; ++ *((unsigned long *)&__m128i_op10) = 0x0141010101410101; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vssran_wu_d (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000;
View file
_service:tar_scm:LoongArch-Add-tests-for-the-SX-vector-multiplication.patch
Added
@@ -0,0 +1,2990 @@ +From 239d4bdbbc72f83efba3830203443b0b2ba4f2ca Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Mon, 11 Sep 2023 10:15:12 +0800 +Subject: PATCH 083/124 LoongArch: Add tests for the SX vector multiplication + instruction. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/vector/lsx/lsx-vmuh-1.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vmuh-2.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vmul.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vmulwev-1.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vmulwev-2.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vmulwev-3.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vmulwod-1.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vmulwod-2.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vmulwod-3.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/vector/lsx/lsx-vmuh-1.c | 353 ++++++++++++++ + .../loongarch/vector/lsx/lsx-vmuh-2.c | 372 +++++++++++++++ + .../loongarch/vector/lsx/lsx-vmul.c | 282 ++++++++++++ + .../loongarch/vector/lsx/lsx-vmulwev-1.c | 434 ++++++++++++++++++ + .../loongarch/vector/lsx/lsx-vmulwev-2.c | 344 ++++++++++++++ + .../loongarch/vector/lsx/lsx-vmulwev-3.c | 245 ++++++++++ + .../loongarch/vector/lsx/lsx-vmulwod-1.c | 272 +++++++++++ + .../loongarch/vector/lsx/lsx-vmulwod-2.c | 282 ++++++++++++ + .../loongarch/vector/lsx/lsx-vmulwod-3.c | 308 +++++++++++++ + 9 files changed, 2892 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmuh-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmuh-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmul.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmulwev-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmulwev-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmulwev-3.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmulwod-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmulwod-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmulwod-3.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmuh-1.c b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmuh-1.c +new file mode 100644 +index 000000000..ab650a024 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmuh-1.c +@@ -0,0 +1,353 @@ ++/* { dg-do run } */ ++/* { dg-options "-mlsx -w -fno-strict-aliasing" } */ ++#include "../simd_correctness_check.h" ++#include <lsxintrin.h> ++ ++int ++main () ++{ ++ __m128i __m128i_op0, __m128i_op1, __m128i_op2, __m128i_out, __m128i_result; ++ __m128 __m128_op0, __m128_op1, __m128_op2, __m128_out, __m128_result; ++ __m128d __m128d_op0, __m128d_op1, __m128d_op2, __m128d_out, __m128d_result; ++ ++ int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail; ++ long int long_op0, long_op1, long_op2, lont_out, lont_result; ++ long int long_int_out, long_int_result; ++ unsigned int unsigned_int_out, unsigned_int_result; ++ unsigned long int unsigned_long_int_out, unsigned_long_int_result; ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vmuh_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op00) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vmuh_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vmuh_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x059a35ef139a8e00; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000001; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vmuh_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vmuh_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x8080808080808080; ++ *((unsigned long *)&__m128i_op00) = 0x8080808080808080; ++ *((unsigned long *)&__m128i_op11) = 0x8080808080808080; ++ *((unsigned long *)&__m128i_op10) = 0x8080808080808080; ++ *((unsigned long *)&__m128i_result1) = 0x4040404040404040; ++ *((unsigned long *)&__m128i_result0) = 0x4040404040404040; ++ __m128i_out = __lsx_vmuh_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vmuh_b (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0xc0c00000c0c00000; ++ *((unsigned long *)&__m128i_op10) = 0xc0c00c01c2cd0009; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vmuh_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000800; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op10) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_result1) = 0x000000000000ffff; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vmuh_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op00) = 0xffffffffffffffff; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vmuh_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vmuh_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0xc0fffff000000000; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x00000000ffe00000; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vmuh_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0xffffffff0000ac26; ++ *((unsigned long *)&__m128i_op10) = 0x00ff000000000001; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vmuh_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x000000ffffff81fe; ++ *((unsigned long *)&__m128i_op00) = 0xffffff00ffff7e01; ++ *((unsigned long *)&__m128i_op11) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op10) = 0x000000fffe01fd02; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000ffff0000fe86; ++ __m128i_out = __lsx_vmuh_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); ++ ++ *((unsigned long *)&__m128i_op01) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op00) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_op11) = 0x7f7f7f7f7f7f7f7f; ++ *((unsigned long *)&__m128i_op10) = 0x7f7f7f7f7f7f7f7f; ++ *((unsigned long *)&__m128i_result1) = 0x0000000000000000; ++ *((unsigned long *)&__m128i_result0) = 0x0000000000000000; ++ __m128i_out = __lsx_vmuh_h (__m128i_op0, __m128i_op1); ++ ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out);
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_service:tar_scm:LoongArch-Add-tests-of-mstrict-align-option.patch
Added
@@ -0,0 +1,37 @@ +From f07b91862055533d779fbf76c12cb7c0ae75b53d Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Mon, 11 Sep 2023 09:35:24 +0800 +Subject: PATCH 076/124 LoongArch: Add tests of -mstrict-align option. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/strict-align.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/testsuite/gcc.target/loongarch/strict-align.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/strict-align.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/strict-align.c b/gcc/testsuite/gcc.target/loongarch/strict-align.c +new file mode 100644 +index 000000000..040d84958 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/strict-align.c +@@ -0,0 +1,12 @@ ++/* { dg-do compile } */ ++/* { dg-options "-Ofast -mstrict-align -mlasx" } */ ++/* { dg-final { scan-assembler-not "vfadd.s" } } */ ++ ++void ++foo (float *restrict x, float *restrict y) ++{ ++ x0 = x0 + y0; ++ x1 = x1 + y1; ++ x2 = x2 + y2; ++ x3 = x3 + y3; ++} +-- +2.33.0 +
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_service:tar_scm:LoongArch-Add-testsuite-framework-for-Loongson-SX-AS.patch
Added
@@ -0,0 +1,131 @@ +From aebd03c944312be767f03d129eeebc0c4cdf5b4a Mon Sep 17 00:00:00 2001 +From: Xiaolong Chen <chenxiaolong@loongson.cn> +Date: Mon, 11 Sep 2023 09:36:35 +0800 +Subject: PATCH 077/124 LoongArch: Add testsuite framework for Loongson + SX/ASX. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/vector/loongarch-vector.exp: New test. + * gcc.target/loongarch/vector/simd_correctness_check.h: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../loongarch/vector/loongarch-vector.exp | 42 +++++++++++++++ + .../loongarch/vector/simd_correctness_check.h | 54 +++++++++++++++++++ + 2 files changed, 96 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp + create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/simd_correctness_check.h + +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp b/gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp +new file mode 100644 +index 000000000..2c37aa91d +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp +@@ -0,0 +1,42 @@ ++#Copyright(C) 2023 Free Software Foundation, Inc. ++ ++#This program is free software; you can redistribute it and / or modify ++#it under the terms of the GNU General Public License as published by ++#the Free Software Foundation; either version 3 of the License, or ++#(at your option) any later version. ++# ++#This program is distributed in the hope that it will be useful, ++#but WITHOUT ANY WARRANTY; without even the implied warranty of ++#MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the ++#GNU General Public License for more details. ++# ++#You should have received a copy of the GNU General Public License ++#along with GCC; see the file COPYING3.If not see ++# <http: //www.gnu.org/licenses/>. ++ ++#GCC testsuite that uses the `dg.exp' driver. ++ ++#Exit immediately if this isn't a LoongArch target. ++if !istarget loongarch*-*-* then { ++ return ++} ++ ++#Load support procs. ++load_lib gcc-dg.exp ++ ++#If a testcase doesn't have special options, use these. ++global DEFAULT_CFLAGS ++if !info exists DEFAULT_CFLAGS then { ++ set DEFAULT_CFLAGS " " ++} ++ ++#Initialize `dg'. ++dg-init ++ ++#Main loop. ++dg-runtest lsort glob -nocomplain $srcdir/$subdir/lsx/*.\cS\ \ ++ " -mlsx" $DEFAULT_CFLAGS ++dg-runtest lsort glob -nocomplain $srcdir/$subdir/lasx/*.\cS\ \ ++ " -mlasx" $DEFAULT_CFLAGS ++# All done. ++dg-finish +diff --git a/gcc/testsuite/gcc.target/loongarch/vector/simd_correctness_check.h b/gcc/testsuite/gcc.target/loongarch/vector/simd_correctness_check.h +new file mode 100644 +index 000000000..eb7fbd59c +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/vector/simd_correctness_check.h +@@ -0,0 +1,54 @@ ++#include <stdio.h> ++#include <stdlib.h> ++#include <string.h> ++ ++#define ASSERTEQ_64(line, ref, res) \ ++ do \ ++ { \ ++ int fail = 0; \ ++ for (size_t i = 0; i < sizeof (res) / sizeof (res0); ++i) \ ++ { \ ++ long *temp_ref = &refi, *temp_res = &resi; \ ++ if (abs (*temp_ref - *temp_res) > 0) \ ++ { \ ++ printf (" error: %s at line %ld , expected " #ref \ ++ "%ld:0x%lx, got: 0x%lx\n", \ ++ __FILE__, line, i, *temp_ref, *temp_res); \ ++ fail = 1; \ ++ } \ ++ } \ ++ if (fail == 1) \ ++ abort (); \ ++ } \ ++ while (0) ++ ++#define ASSERTEQ_32(line, ref, res) \ ++ do \ ++ { \ ++ int fail = 0; \ ++ for (size_t i = 0; i < sizeof (res) / sizeof (res0); ++i) \ ++ { \ ++ int *temp_ref = &refi, *temp_res = &resi; \ ++ if (abs (*temp_ref - *temp_res) > 0) \ ++ { \ ++ printf (" error: %s at line %ld , expected " #ref \ ++ "%ld:0x%x, got: 0x%x\n", \ ++ __FILE__, line, i, *temp_ref, *temp_res); \ ++ fail = 1; \ ++ } \ ++ } \ ++ if (fail == 1) \ ++ abort (); \ ++ } \ ++ while (0) ++ ++#define ASSERTEQ_int(line, ref, res) \ ++ do \ ++ { \ ++ if (ref != res) \ ++ { \ ++ printf (" error: %s at line %ld , expected %d, got %d\n", __FILE__, \ ++ line, ref, res); \ ++ } \ ++ } \ ++ while (0) +-- +2.33.0 +
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_service:tar_scm:LoongArch-Adjust-C-multilib-header-layout.patch
Added
@@ -0,0 +1,53 @@ +From a4bf17e87a965ed7f2bb1d2921fb9dd820c79a96 Mon Sep 17 00:00:00 2001 +From: Yang Yujie <yangyujie@loongson.cn> +Date: Thu, 7 Sep 2023 14:50:10 +0800 +Subject: PATCH 069/124 LoongArch: Adjust C++ multilib header layout. + +For LoongArch, the toplevel library build is always aliased to +one of the multilib variants. This patch installs it with the +actual MULTISUBDIR (instead of ".") so that the headers can be +reached by the compiler. + +This patch is an update of +https://gcc.gnu.org/pipermail/gcc-patches/2023-September/629435.html + +libstdc++-v3/ChangeLog: + + * configure.host: Register t-loongarch in tmake_file. + * config/cpu/loongarch/t-loongarch: New file. Manually refresh + MULTISUBDIR with $(shell $(CXX) --print-multi-directory). + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + libstdc++-v3/config/cpu/loongarch/t-loongarch | 1 + + libstdc++-v3/configure.host | 5 ++++- + 2 files changed, 5 insertions(+), 1 deletion(-) + create mode 100644 libstdc++-v3/config/cpu/loongarch/t-loongarch + +diff --git a/libstdc++-v3/config/cpu/loongarch/t-loongarch b/libstdc++-v3/config/cpu/loongarch/t-loongarch +new file mode 100644 +index 000000000..adfc8ebb9 +--- /dev/null ++++ b/libstdc++-v3/config/cpu/loongarch/t-loongarch +@@ -0,0 +1 @@ ++AM_MAKEFLAGS += " MULTISUBDIR=/$(shell $(CXX) --print-multi-directory)" +diff --git a/libstdc++-v3/configure.host b/libstdc++-v3/configure.host +index ec32980aa..592160e6d 100644 +--- a/libstdc++-v3/configure.host ++++ b/libstdc++-v3/configure.host +@@ -315,7 +315,10 @@ esac + # Set any OS-dependent and CPU-dependent bits. + # THIS TABLE IS SORTED. KEEP IT THAT WAY. + case "${host}" in +- *-*-linux* | *-*-uclinux*) ++ loongarch*) ++ tmake_file="cpu/loongarch/t-loongarch" ++ ;; ++ *-*-linux* | *-*-uclinux*) + case "${host_cpu}" in + i56786) + abi_baseline_pair=i486-linux-gnu +-- +2.33.0 +
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_service:tar_scm:LoongArch-Avoid-RTL-flag-check-failure-in-loongarch_.patch
Added
@@ -0,0 +1,55 @@ +From e82403e918e18fa8e8ecd0c9e26f2657cc814e12 Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao <xry111@xry111.site> +Date: Wed, 24 Aug 2022 21:31:34 +0800 +Subject: PATCH 013/124 LoongArch: Avoid RTL flag check failure in + loongarch_classify_symbol + +SYMBOL_REF_TLS_MODEL invokes SYMBOL_REF_FLAGS, and SYMBOL_REF_FLAGS +invokes RTL_FLAG_CHECK1 and aborts when RTL code is not SYMBOL_REF. + +r13-1833 removed "gcc_assert (SYMBOL_REF_P (x))" before invoking +"SYMBOL_REF_TLS_MODEL (x)", indicating that it's now possible that "x" +is not a SYMBOL_REF. So we need to check if "x" is SYMBOL_REF first. + +This fixes a test failure happening with r13-2173 with RTL flag +checking enabled: + + pr106096.C:26:1: internal compiler error: RTL flag check: + SYMBOL_REF_FLAGS used with unexpected rtx code 'const' in + loongarch_classify_symbol + +gcc/ChangeLog: + + * config/loongarch/loongarch.cc (loongarch_classify_symbol): + Return early if the rtx is not SYMBOL_REF. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/loongarch.cc | 5 ++--- + 1 file changed, 2 insertions(+), 3 deletions(-) + +diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc +index 04c4ddaed..452aba9d4 100644 +--- a/gcc/config/loongarch/loongarch.cc ++++ b/gcc/config/loongarch/loongarch.cc +@@ -1633,14 +1633,13 @@ loongarch_rtx_constant_in_small_data_p (machine_mode mode) + static enum loongarch_symbol_type + loongarch_classify_symbol (const_rtx x) + { +- if (LABEL_REF_P (x)) ++ if (!SYMBOL_REF_P (x)) + return SYMBOL_PCREL; + + if (SYMBOL_REF_TLS_MODEL (x)) + return SYMBOL_TLS; + +- if (SYMBOL_REF_P (x) +- && !loongarch_symbol_binds_local_p (x)) ++ if (!loongarch_symbol_binds_local_p (x)) + return SYMBOL_GOT_DISP; + + return SYMBOL_PCREL; +-- +2.33.0 +
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_service:tar_scm:LoongArch-Avoid-non-returning-indirect-jumps-through.patch
Added
@@ -0,0 +1,62 @@ +From 7e759740048ee6f24c1055c32868fa21cabb4f75 Mon Sep 17 00:00:00 2001 +From: Lulu Cheng <chenglulu@loongson.cn> +Date: Wed, 7 Jun 2023 10:21:58 +0800 +Subject: PATCH 048/124 LoongArch: Avoid non-returning indirect jumps through + $ra PR110136 + +Micro-architecture unconditionally treats a "jr $ra" as "return from subroutine", +hence doing "jr $ra" would interfere with both subroutine return prediction and +the more general indirect branch prediction. + +Therefore, a problem like PR110136 can cause a significant increase in branch error +prediction rate and affect performance. The same problem exists with "indirect_jump". + +gcc/ChangeLog: + + PR target/110136 + * config/loongarch/loongarch.md: Modify the register constraints for template + "jumptable" and "indirect_jump" from "r" to "e". + +Co-authored-by: Andrew Pinski <apinski@marvell.com> +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/loongarch.md | 8 ++++++-- + 1 file changed, 6 insertions(+), 2 deletions(-) + +diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md +index b23248c33..c79951c1d 100644 +--- a/gcc/config/loongarch/loongarch.md ++++ b/gcc/config/loongarch/loongarch.md +@@ -2895,6 +2895,10 @@ + } + (set_attr "type" "branch")) + ++;; Micro-architecture unconditionally treats a "jr $ra" as "return from subroutine", ++;; non-returning indirect jumps through $ra would interfere with both subroutine ++;; return prediction and the more general indirect branch prediction. ++ + (define_expand "indirect_jump" + (set (pc) (match_operand 0 "register_operand")) + "" +@@ -2905,7 +2909,7 @@ + }) + + (define_insn "@indirect_jump<mode>" +- (set (pc) (match_operand:P 0 "register_operand" "r")) ++ (set (pc) (match_operand:P 0 "register_operand" "e")) + "" + "jr\t%0" + (set_attr "type" "jump") +@@ -2928,7 +2932,7 @@ + + (define_insn "@tablejump<mode>" + (set (pc) +- (match_operand:P 0 "register_operand" "r")) ++ (match_operand:P 0 "register_operand" "e")) + (use (label_ref (match_operand 1 "" ""))) + "" + "jr\t%0" +-- +2.33.0 +
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_service:tar_scm:LoongArch-Change-the-default-value-of-LARCH_CALL_RAT.patch
Added
@@ -0,0 +1,41 @@ +From 59824f1062d77d0e02ea82d47415bf95c235de87 Mon Sep 17 00:00:00 2001 +From: chenxiaolong <chenxl04200420@163.com> +Date: Thu, 15 Jun 2023 02:46:24 +0000 +Subject: PATCH 046/124 LoongArch: Change the default value of + LARCH_CALL_RATIO to 6. + +During the regression testing of the LoongArch architecture GCC, it was found +that the tests in the pr90883.C file failed. The problem was modulated and +found that the error was caused by setting the macro LARCH_CALL_RATIO to a too +large value. Combined with the actual LoongArch architecture, the different +thresholds for meeting the test conditions were tested using the engineering method +(SPEC CPU 2006), and the results showed that its optimal threshold should be set +to 6. + +gcc/ChangeLog: + + * config/loongarch/loongarch.h (LARCH_CALL_RATIO): Modify the value + of macro LARCH_CALL_RATIO on LoongArch to make it perform optimally. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/loongarch.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/gcc/config/loongarch/loongarch.h b/gcc/config/loongarch/loongarch.h +index 44ebadfaa..0e35d4dec 100644 +--- a/gcc/config/loongarch/loongarch.h ++++ b/gcc/config/loongarch/loongarch.h +@@ -1073,7 +1073,7 @@ typedef struct { + /* The base cost of a memcpy call, for MOVE_RATIO and friends. These + values were determined experimentally by benchmarking with CSiBE. + */ +-#define LARCH_CALL_RATIO 8 ++#define LARCH_CALL_RATIO 6 + + /* Any loop-based implementation of cpymemsi will have at least + LARCH_MAX_MOVE_OPS_PER_LOOP_ITER memory-to-memory +-- +2.33.0 +
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_service:tar_scm:LoongArch-Change-the-value-of-branch_cost-from-2-to-.patch
Added
@@ -0,0 +1,69 @@ +From 7e843ed8da168a05eb04eee0b14cbe681bf798fe Mon Sep 17 00:00:00 2001 +From: Lulu Cheng <chenglulu@loongson.cn> +Date: Wed, 13 Sep 2023 11:01:34 +0800 +Subject: PATCH 123/124 LoongArch: Change the value of branch_cost from 2 to + 6. + +gcc/ChangeLog: + + * config/loongarch/loongarch-def.c: Modify the default value of + branch_cost. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/cmov_ii.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/loongarch-def.c | 4 ++-- + gcc/testsuite/gcc.target/loongarch/cmov_ii.c | 15 +++++++++++++++ + 2 files changed, 17 insertions(+), 2 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/loongarch/cmov_ii.c + +diff --git a/gcc/config/loongarch/loongarch-def.c b/gcc/config/loongarch/loongarch-def.c +index d29d5f001..eeb32dbf6 100644 +--- a/gcc/config/loongarch/loongarch-def.c ++++ b/gcc/config/loongarch/loongarch-def.c +@@ -85,7 +85,7 @@ loongarch_cpu_alignN_TUNE_TYPES = { + .int_mult_di = COSTS_N_INSNS (1), \ + .int_div_si = COSTS_N_INSNS (4), \ + .int_div_di = COSTS_N_INSNS (6), \ +- .branch_cost = 2, \ ++ .branch_cost = 6, \ + .memory_latency = 4 + + /* The following properties cannot be looked up directly using "cpucfg". +@@ -118,7 +118,7 @@ loongarch_rtx_cost_optimize_size = { + .int_mult_di = 4, + .int_div_si = 4, + .int_div_di = 4, +- .branch_cost = 2, ++ .branch_cost = 6, + .memory_latency = 4, + }; + +diff --git a/gcc/testsuite/gcc.target/loongarch/cmov_ii.c b/gcc/testsuite/gcc.target/loongarch/cmov_ii.c +new file mode 100644 +index 000000000..21b468e8a +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/cmov_ii.c +@@ -0,0 +1,15 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2" } */ ++/* { dg-final { scan-assembler "test:.*xor.*maskeqz.*masknez.*or.*" } } */ ++ ++extern void foo_ii (int *, int *, int *, int *); ++ ++int ++test (void) ++{ ++ int a, b; ++ int c, d, out; ++ foo_ii (&a, &b, &c, &d); ++ out = a == b ? c : d; ++ return out; ++} +-- +2.33.0 +
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_service:tar_scm:LoongArch-Change-the-value-of-macro-TRY_EMPTY_VM_SPA.patch
Added
@@ -0,0 +1,49 @@ +From 6e9265e571a63deb2584704a0b088a6d67ec8af5 Mon Sep 17 00:00:00 2001 +From: Lulu Cheng <chenglulu@loongson.cn> +Date: Mon, 20 Feb 2023 16:47:11 +0800 +Subject: PATCH 037/124 LoongArch: Change the value of macro + TRY_EMPTY_VM_SPACE from 0x8000000000 to 0x1000000000. + +The PCH mechanism first tries to map the .gch file to the virtual memory +space pointed to by TRY_EMPTY_VM_SPACE during the compilation process. + +The original value of TRY_EMPTY_VM_SPACE macro is 0x8000000000, +but like la464 only has 40 bits of virtual address space, this value +just exceeds the address range. + +If we want to support chips with less than 40 bits virtual addresses, +then the value of this macro needs to be set small. I think setting +this value small will increase the probability of virtual address +mapping failure. And the purpose of pch is to make compilation faster, +but I think we rarely compile on embedded systems. So this situation +may not be within our consideration. + +So change the value of this macro to 0x1000000000. + +gcc/ChangeLog: + + * config/host-linux.cc (TRY_EMPTY_VM_SPACE): Modify the value of + the macro to 0x1000000000. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/host-linux.cc | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/gcc/config/host-linux.cc b/gcc/config/host-linux.cc +index 817d3c087..d93cfc064 100644 +--- a/gcc/config/host-linux.cc ++++ b/gcc/config/host-linux.cc +@@ -99,7 +99,7 @@ + #elif defined(__riscv) && defined (__LP64__) + # define TRY_EMPTY_VM_SPACE 0x1000000000 + #elif defined(__loongarch__) && defined(__LP64__) +-# define TRY_EMPTY_VM_SPACE 0x8000000000 ++# define TRY_EMPTY_VM_SPACE 0x1000000000 + #else + # define TRY_EMPTY_VM_SPACE 0 + #endif +-- +2.33.0 +
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_service:tar_scm:LoongArch-Define-the-macro-ASM_PREFERRED_EH_DATA_FOR.patch
Added
@@ -0,0 +1,139 @@ +From 05c1df09c70cd0ed48f0644890f69a0128b17a98 Mon Sep 17 00:00:00 2001 +From: Lulu Cheng <chenglulu@loongson.cn> +Date: Fri, 29 Jul 2022 09:44:52 +0800 +Subject: PATCH 008/124 LoongArch: Define the macro + ASM_PREFERRED_EH_DATA_FORMAT by checking the assembler's support for eh_frame + encoding. + +.eh_frame DW_EH_PE_pcrel encoding format is not supported by gas <= 2.39. +Check if the assembler support DW_EH_PE_PCREL encoding and define .eh_frame +encoding type. + +gcc/ChangeLog: + + * config.in: Regenerate. + * config/loongarch/loongarch.h (ASM_PREFERRED_EH_DATA_FORMAT): + Select the value of the macro definition according to whether + HAVE_AS_EH_FRAME_PCREL_ENCODING_SUPPORT is defined. + * configure: Regenerate. + * configure.ac: Reinstate HAVE_AS_EH_FRAME_PCREL_ENCODING_SUPPORT test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config.in | 8 +++++++- + gcc/config/loongarch/loongarch.h | 5 +++++ + gcc/configure | 34 ++++++++++++++++++++++++++++++++ + gcc/configure.ac | 8 ++++++++ + 4 files changed, 54 insertions(+), 1 deletion(-) + +diff --git a/gcc/config.in b/gcc/config.in +index 64c27c9cf..67ce422f2 100644 +--- a/gcc/config.in ++++ b/gcc/config.in +@@ -404,13 +404,19 @@ + #endif + + ++/* Define if your assembler supports eh_frame pcrel encoding. */ ++#ifndef USED_FOR_TARGET ++#undef HAVE_AS_EH_FRAME_PCREL_ENCODING_SUPPORT ++#endif ++ ++ + /* Define if your assembler supports the R_PPC64_ENTRY relocation. */ + #ifndef USED_FOR_TARGET + #undef HAVE_AS_ENTRY_MARKERS + #endif + + +-/* Define if your assembler supports explicit relocations. */ ++/* Define if your assembler supports explicit relocation. */ + #ifndef USED_FOR_TARGET + #undef HAVE_AS_EXPLICIT_RELOCS + #endif +diff --git a/gcc/config/loongarch/loongarch.h b/gcc/config/loongarch/loongarch.h +index 12f209047..a52a81adf 100644 +--- a/gcc/config/loongarch/loongarch.h ++++ b/gcc/config/loongarch/loongarch.h +@@ -1130,8 +1130,13 @@ struct GTY (()) machine_function + }; + #endif + ++#ifdef HAVE_AS_EH_FRAME_PCREL_ENCODING_SUPPORT ++#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ ++ (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4) ++#else + #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ + (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr) ++#endif + + /* Do emit .note.GNU-stack by default. */ + #ifndef NEED_INDICATE_EXEC_STACK +diff --git a/gcc/configure b/gcc/configure +index 840eddc7c..3788e240a 100755 +--- a/gcc/configure ++++ b/gcc/configure +@@ -28857,6 +28857,40 @@ if test $gcc_cv_as_loongarch_explicit_relocs = yes; then + + $as_echo "#define HAVE_AS_EXPLICIT_RELOCS 1" >>confdefs.h + ++fi ++ ++ { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for eh_frame pcrel encoding support" >&5 ++$as_echo_n "checking assembler for eh_frame pcrel encoding support... " >&6; } ++if ${gcc_cv_as_loongarch_eh_frame_pcrel_encoding_support+:} false; then : ++ $as_echo_n "(cached) " >&6 ++else ++ gcc_cv_as_loongarch_eh_frame_pcrel_encoding_support=no ++ if test x$gcc_cv_as != x; then ++ $as_echo '.cfi_startproc ++ .cfi_personality 0x9b,a ++ .cfi_lsda 0x1b,b ++ .cfi_endproc' > conftest.s ++ if { ac_try='$gcc_cv_as $gcc_cv_as_flags -o conftest.o conftest.s >&5' ++ { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5 ++ (eval $ac_try) 2>&5 ++ ac_status=$? ++ $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 ++ test $ac_status = 0; }; } ++ then ++ gcc_cv_as_loongarch_eh_frame_pcrel_encoding_support=yes ++ else ++ echo "configure: failed program was" >&5 ++ cat conftest.s >&5 ++ fi ++ rm -f conftest.o conftest.s ++ fi ++fi ++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_loongarch_eh_frame_pcrel_encoding_support" >&5 ++$as_echo "$gcc_cv_as_loongarch_eh_frame_pcrel_encoding_support" >&6; } ++if test $gcc_cv_as_loongarch_eh_frame_pcrel_encoding_support = yes; then ++ ++$as_echo "#define HAVE_AS_EH_FRAME_PCREL_ENCODING_SUPPORT 1" >>confdefs.h ++ + fi + + ;; +diff --git a/gcc/configure.ac b/gcc/configure.ac +index 975c852c6..1c376e0d4 100644 +--- a/gcc/configure.ac ++++ b/gcc/configure.ac +@@ -5324,6 +5324,14 @@ x: + a:pcalau12i $t0,%pc_hi20(a),, + AC_DEFINE(HAVE_AS_EXPLICIT_RELOCS, 1, + Define if your assembler supports explicit relocation.)) ++ gcc_GAS_CHECK_FEATURE(eh_frame pcrel encoding support, ++ gcc_cv_as_loongarch_eh_frame_pcrel_encoding_support,, ++ .cfi_startproc ++ .cfi_personality 0x9b,a ++ .cfi_lsda 0x1b,b ++ .cfi_endproc,, ++ AC_DEFINE(HAVE_AS_EH_FRAME_PCREL_ENCODING_SUPPORT, 1, ++ Define if your assembler supports eh_frame pcrel encoding.)) + ;; + s390*-*-*) + gcc_GAS_CHECK_FEATURE(.gnu_attribute support, +-- +2.33.0 +
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_service:tar_scm:LoongArch-Don-t-add-crtfastmath.o-for-shared.patch
Added
@@ -0,0 +1,34 @@ +From 2e19311d1bf4f932f5e67f6866123b895b12c97f Mon Sep 17 00:00:00 2001 +From: Richard Biener <rguenther@suse.de> +Date: Fri, 13 Jan 2023 09:01:12 +0100 +Subject: PATCH 035/124 LoongArch: Don't add crtfastmath.o for -shared + +Don't add crtfastmath.o for -shared to avoid altering the FP +environment when loading a shared library. + + PR target/55522 + * config/loongarch/gnu-user.h (GNU_USER_TARGET_MATHFILE_SPEC): + Don't add crtfastmath.o for -shared. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/gnu-user.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/gcc/config/loongarch/gnu-user.h b/gcc/config/loongarch/gnu-user.h +index c5b1afe53..1dc6add62 100644 +--- a/gcc/config/loongarch/gnu-user.h ++++ b/gcc/config/loongarch/gnu-user.h +@@ -49,7 +49,7 @@ along with GCC; see the file COPYING3. If not see + /* Similar to standard Linux, but adding -ffast-math support. */ + #undef GNU_USER_TARGET_MATHFILE_SPEC + #define GNU_USER_TARGET_MATHFILE_SPEC \ +- "%{Ofast|ffast-math|funsafe-math-optimizations:crtfastmath.o%s}" ++ "%{Ofast|ffast-math|funsafe-math-optimizations:%{!shared:crtfastmath.o%s}}" + + #undef LIB_SPEC + #define LIB_SPEC GNU_USER_TARGET_LIB_SPEC +-- +2.33.0 +
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_service:tar_scm:LoongArch-Enable-free-starting-at-O2.patch
Added
@@ -0,0 +1,71 @@ +From 0369836718ffb25ac64c135e748f409302068a56 Mon Sep 17 00:00:00 2001 +From: Lulu Cheng <chenglulu@loongson.cn> +Date: Mon, 28 Aug 2023 11:30:21 +0800 +Subject: PATCH 052/124 LoongArch: Enable '-free' starting at -O2. + +gcc/ChangeLog: + + * common/config/loongarch/loongarch-common.cc: + Enable '-free' on O2 and above. + * doc/invoke.texi: Modify the description information + of the '-free' compilation option and add the LoongArch + description. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/sign-extend.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../config/loongarch/loongarch-common.cc | 1 + + .../gcc.target/loongarch/sign-extend.c | 25 +++++++++++++++++++ + 2 files changed, 26 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/sign-extend.c + +diff --git a/gcc/common/config/loongarch/loongarch-common.cc b/gcc/common/config/loongarch/loongarch-common.cc +index f8b4660fa..309fcb280 100644 +--- a/gcc/common/config/loongarch/loongarch-common.cc ++++ b/gcc/common/config/loongarch/loongarch-common.cc +@@ -35,6 +35,7 @@ static const struct default_options loongarch_option_optimization_table = + { + { OPT_LEVELS_ALL, OPT_fasynchronous_unwind_tables, NULL, 1 }, + { OPT_LEVELS_1_PLUS, OPT_fsection_anchors, NULL, 1 }, ++ { OPT_LEVELS_2_PLUS, OPT_free, NULL, 1 }, + { OPT_LEVELS_NONE, 0, NULL, 0 } + }; + +diff --git a/gcc/testsuite/gcc.target/loongarch/sign-extend.c b/gcc/testsuite/gcc.target/loongarch/sign-extend.c +new file mode 100644 +index 000000000..3f339d06b +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/sign-extend.c +@@ -0,0 +1,25 @@ ++/* { dg-do compile } */ ++/* { dg-options "-mabi=lp64d -O2" } */ ++/* { dg-final { scan-assembler-times "slli.w" 1 } } */ ++ ++extern int PL_savestack_ix; ++extern int PL_regsize; ++extern int PL_savestack_max; ++void Perl_savestack_grow_cnt (int need); ++extern void Perl_croak (char *); ++ ++int ++S_regcppush(int parenfloor) ++{ ++ int retval = PL_savestack_ix; ++ int paren_elems_to_push = (PL_regsize - parenfloor) * 4; ++ int p; ++ ++ if (paren_elems_to_push < 0) ++ Perl_croak ("panic: paren_elems_to_push < 0"); ++ ++ if (PL_savestack_ix + (paren_elems_to_push + 6) > PL_savestack_max) ++ Perl_savestack_grow_cnt (paren_elems_to_push + 6); ++ ++ return retval; ++} +-- +2.33.0 +
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_service:tar_scm:LoongArch-Enable-fsched-pressure-by-default-at-O1-an.patch
Added
@@ -0,0 +1,33 @@ +From a9f72e237d5c176e4ef8ba03a8b4ee5c5daa25fb Mon Sep 17 00:00:00 2001 +From: Guo Jie <guojie@loongson.cn> +Date: Fri, 8 Sep 2023 10:00:21 +0800 +Subject: PATCH 071/124 LoongArch: Enable -fsched-pressure by default at -O1 + and higher. + +gcc/ChangeLog: + + * common/config/loongarch/loongarch-common.cc: + (default_options loongarch_option_optimization_table): + Default to -fsched-pressure. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/common/config/loongarch/loongarch-common.cc | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/gcc/common/config/loongarch/loongarch-common.cc b/gcc/common/config/loongarch/loongarch-common.cc +index 309fcb280..c8bc5718d 100644 +--- a/gcc/common/config/loongarch/loongarch-common.cc ++++ b/gcc/common/config/loongarch/loongarch-common.cc +@@ -36,6 +36,7 @@ static const struct default_options loongarch_option_optimization_table = + { OPT_LEVELS_ALL, OPT_fasynchronous_unwind_tables, NULL, 1 }, + { OPT_LEVELS_1_PLUS, OPT_fsection_anchors, NULL, 1 }, + { OPT_LEVELS_2_PLUS, OPT_free, NULL, 1 }, ++ { OPT_LEVELS_1_PLUS, OPT_fsched_pressure, NULL, 1 }, + { OPT_LEVELS_NONE, 0, NULL, 0 } + }; + +-- +2.33.0 +
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_service:tar_scm:LoongArch-Enable-shrink-wrapping.patch
Added
@@ -0,0 +1,309 @@ +From e86c9ece7ae922fe80017ba2ffe22f6267531682 Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao <xry111@xry111.site> +Date: Sun, 23 Apr 2023 20:52:22 +0800 +Subject: PATCH 045/124 LoongArch: Enable shrink wrapping + +This commit implements the target macros for shrink wrapping of function +prologues/epilogues shrink wrapping on LoongArch. + +Bootstrapped and regtested on loongarch64-linux-gnu. I don't have an +access to SPEC CPU so I hope the reviewer can perform a benchmark to see +if there is real benefit. + +gcc/ChangeLog: + + * config/loongarch/loongarch.h (struct machine_function): Add + reg_is_wrapped_separately array for register wrapping + information. + * config/loongarch/loongarch.cc + (loongarch_get_separate_components): New function. + (loongarch_components_for_bb): Likewise. + (loongarch_disqualify_components): Likewise. + (loongarch_process_components): Likewise. + (loongarch_emit_prologue_components): Likewise. + (loongarch_emit_epilogue_components): Likewise. + (loongarch_set_handled_components): Likewise. + (TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS): Define. + (TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB): Likewise. + (TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS): Likewise. + (TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS): Likewise. + (TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS): Likewise. + (TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS): Likewise. + (loongarch_for_each_saved_reg): Skip registers that are wrapped + separately. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/shrink-wrap.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/loongarch.cc | 179 +++++++++++++++++- + gcc/config/loongarch/loongarch.h | 2 + + .../gcc.target/loongarch/shrink-wrap.c | 19 ++ + 3 files changed, 197 insertions(+), 3 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/loongarch/shrink-wrap.c + +diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc +index d3c6f22ad..4c0f393b6 100644 +--- a/gcc/config/loongarch/loongarch.cc ++++ b/gcc/config/loongarch/loongarch.cc +@@ -64,6 +64,7 @@ along with GCC; see the file COPYING3. If not see + #include "builtins.h" + #include "rtl-iter.h" + #include "opts.h" ++#include "function-abi.h" + + /* This file should be included last. */ + #include "target-def.h" +@@ -1014,19 +1015,23 @@ loongarch_for_each_saved_reg (HOST_WIDE_INT sp_offset, + for (int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) + if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST)) + { +- loongarch_save_restore_reg (word_mode, regno, offset, fn); ++ if (!cfun->machine->reg_is_wrapped_separatelyregno) ++ loongarch_save_restore_reg (word_mode, regno, offset, fn); ++ + offset -= UNITS_PER_WORD; + } + + /* This loop must iterate over the same space as its companion in + loongarch_compute_frame_info. */ + offset = cfun->machine->frame.fp_sp_offset - sp_offset; ++ machine_mode mode = TARGET_DOUBLE_FLOAT ? DFmode : SFmode; ++ + for (int regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) + if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST)) + { +- machine_mode mode = TARGET_DOUBLE_FLOAT ? DFmode : SFmode; ++ if (!cfun->machine->reg_is_wrapped_separatelyregno) ++ loongarch_save_restore_reg (word_mode, regno, offset, fn); + +- loongarch_save_restore_reg (mode, regno, offset, fn); + offset -= GET_MODE_SIZE (mode); + } + } +@@ -6630,6 +6635,151 @@ loongarch_asan_shadow_offset (void) + return TARGET_64BIT ? (HOST_WIDE_INT_1 << 46) : 0; + } + ++static sbitmap ++loongarch_get_separate_components (void) ++{ ++ HOST_WIDE_INT offset; ++ sbitmap components = sbitmap_alloc (FIRST_PSEUDO_REGISTER); ++ bitmap_clear (components); ++ offset = cfun->machine->frame.gp_sp_offset; ++ ++ /* The stack should be aligned to 16-bytes boundary, so we can make the use ++ of ldptr instructions. */ ++ gcc_assert (offset % UNITS_PER_WORD == 0); ++ ++ for (unsigned int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) ++ if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST)) ++ { ++ /* We can wrap general registers saved at sp, sp + 32768) using the ++ ldptr/stptr instructions. For large offsets a pseudo register ++ might be needed which cannot be created during the shrink ++ wrapping pass. ++ ++ TODO: This may need a revise when we add LA32 as ldptr.w is not ++ guaranteed available by the manual. */ ++ if (offset < 32768) ++ bitmap_set_bit (components, regno); ++ ++ offset -= UNITS_PER_WORD; ++ } ++ ++ offset = cfun->machine->frame.fp_sp_offset; ++ for (unsigned int regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) ++ if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST)) ++ { ++ /* We can only wrap FP registers with imm12 offsets. For large ++ offsets a pseudo register might be needed which cannot be ++ created during the shrink wrapping pass. */ ++ if (IMM12_OPERAND (offset)) ++ bitmap_set_bit (components, regno); ++ ++ offset -= UNITS_PER_FPREG; ++ } ++ ++ /* Don't mess with the hard frame pointer. */ ++ if (frame_pointer_needed) ++ bitmap_clear_bit (components, HARD_FRAME_POINTER_REGNUM); ++ ++ bitmap_clear_bit (components, RETURN_ADDR_REGNUM); ++ ++ return components; ++} ++ ++static sbitmap ++loongarch_components_for_bb (basic_block bb) ++{ ++ /* Registers are used in a bb if they are in the IN, GEN, or KILL sets. */ ++ auto_bitmap used; ++ bitmap_copy (used, DF_LIVE_IN (bb)); ++ bitmap_ior_into (used, &DF_LIVE_BB_INFO (bb)->gen); ++ bitmap_ior_into (used, &DF_LIVE_BB_INFO (bb)->kill); ++ ++ sbitmap components = sbitmap_alloc (FIRST_PSEUDO_REGISTER); ++ bitmap_clear (components); ++ ++ function_abi_aggregator callee_abis; ++ rtx_insn *insn; ++ FOR_BB_INSNS (bb, insn) ++ if (CALL_P (insn)) ++ callee_abis.note_callee_abi (insn_callee_abi (insn)); ++ ++ HARD_REG_SET extra_caller_saves = ++ callee_abis.caller_save_regs (*crtl->abi); ++ ++ for (unsigned int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) ++ if (!fixed_regsregno ++ && !crtl->abi->clobbers_full_reg_p (regno) ++ && (TEST_HARD_REG_BIT (extra_caller_saves, regno) || ++ bitmap_bit_p (used, regno))) ++ bitmap_set_bit (components, regno); ++ ++ for (unsigned int regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) ++ if (!fixed_regsregno ++ && !crtl->abi->clobbers_full_reg_p (regno) ++ && (TEST_HARD_REG_BIT (extra_caller_saves, regno) || ++ bitmap_bit_p (used, regno))) ++ bitmap_set_bit (components, regno); ++ ++ return components; ++} ++ ++static void ++loongarch_disqualify_components (sbitmap, edge, sbitmap, bool) ++{ ++ /* Do nothing. */ ++} ++ ++static void ++loongarch_process_components (sbitmap components, loongarch_save_restore_fn fn) ++{ ++ HOST_WIDE_INT offset = cfun->machine->frame.gp_sp_offset; ++ ++ for (unsigned int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) ++ if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST)) ++ { ++ if (bitmap_bit_p (components, regno)) ++ loongarch_save_restore_reg (word_mode, regno, offset, fn); ++ ++ offset -= UNITS_PER_WORD; ++ } ++ ++ offset = cfun->machine->frame.fp_sp_offset;
View file
_service:tar_scm:LoongArch-Fix-MUSL_DYNAMIC_LINKER.patch
Added
@@ -0,0 +1,43 @@ +From 3db61acfbaa773568fad2bc31d950c6d9b3729b0 Mon Sep 17 00:00:00 2001 +From: Peng Fan <fanpeng@loongson.cn> +Date: Wed, 19 Apr 2023 16:23:42 +0800 +Subject: PATCH 044/124 LoongArch: Fix MUSL_DYNAMIC_LINKER + +The system based on musl has no '/lib64', so change it. + +https://wiki.musl-libc.org/guidelines-for-distributions.html, +"Multilib/multi-arch" section of this introduces it. + +gcc/ + * config/loongarch/gnu-user.h (MUSL_DYNAMIC_LINKER): Redefine. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Suggested-by: Xi Ruoyao <xry111@xry111.site> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/gnu-user.h | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +diff --git a/gcc/config/loongarch/gnu-user.h b/gcc/config/loongarch/gnu-user.h +index 1dc6add62..44e4f2575 100644 +--- a/gcc/config/loongarch/gnu-user.h ++++ b/gcc/config/loongarch/gnu-user.h +@@ -33,9 +33,14 @@ along with GCC; see the file COPYING3. If not see + #define GLIBC_DYNAMIC_LINKER \ + "/lib" ABI_GRLEN_SPEC "/ld-linux-loongarch-" ABI_SPEC ".so.1" + ++#define MUSL_ABI_SPEC \ ++ "%{mabi=lp64d:-lp64d}" \ ++ "%{mabi=lp64f:-lp64f}" \ ++ "%{mabi=lp64s:-lp64s}" ++ + #undef MUSL_DYNAMIC_LINKER + #define MUSL_DYNAMIC_LINKER \ +- "/lib" ABI_GRLEN_SPEC "/ld-musl-loongarch-" ABI_SPEC ".so.1" ++ "/lib/ld-musl-loongarch" ABI_GRLEN_SPEC MUSL_ABI_SPEC ".so.1" + + #undef GNU_USER_TARGET_LINK_SPEC + #define GNU_USER_TARGET_LINK_SPEC \ +-- +2.33.0 +
View file
_service:tar_scm:LoongArch-Fix-bug-in-loongarch_emit_stack_tie-PR1104.patch
Added
@@ -0,0 +1,43 @@ +From 7c8fc6b414dc1718e71e0d05c7a78498e06eb499 Mon Sep 17 00:00:00 2001 +From: Lulu Cheng <chenglulu@loongson.cn> +Date: Thu, 29 Jun 2023 19:30:59 +0800 +Subject: PATCH 053/124 LoongArch: Fix bug in loongarch_emit_stack_tie + PR110484. + +Which may result in implicit references to $fp when frame_pointer_needed is false, +causing regs_ever_live$fp to be true when $fp is not explicitly used, +resulting in $fp being used as the target replacement register in the rnreg pass. + +The bug originates from SPEC2017 541.leela_r(-flto). + +gcc/ChangeLog: + + PR target/110484 + * config/loongarch/loongarch.cc (loongarch_emit_stack_tie): Use the + frame_pointer_needed to determine whether to use the $fp register. + +Co-authored-by: Guo Jie <guojie@loongson.cn> +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/loongarch.cc | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc +index caacfa8a3..7b48e3216 100644 +--- a/gcc/config/loongarch/loongarch.cc ++++ b/gcc/config/loongarch/loongarch.cc +@@ -1109,7 +1109,9 @@ loongarch_first_stack_step (struct loongarch_frame_info *frame) + static void + loongarch_emit_stack_tie (void) + { +- emit_insn (gen_stack_tie (Pmode, stack_pointer_rtx, hard_frame_pointer_rtx)); ++ emit_insn (gen_stack_tie (Pmode, stack_pointer_rtx, ++ frame_pointer_needed ? hard_frame_pointer_rtx ++ : stack_pointer_rtx)); + } + + #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP) +-- +2.33.0 +
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_service:tar_scm:LoongArch-Fix-bug-of-optab-di3_fake.patch
Added
@@ -0,0 +1,123 @@ +From df1df2e7b7e27bd9fba77f572d74d833aff4a202 Mon Sep 17 00:00:00 2001 +From: Lulu Cheng <chenglulu@loongson.cn> +Date: Mon, 11 Sep 2023 16:20:29 +0800 +Subject: PATCH 122/124 LoongArch: Fix bug of '<optab>di3_fake'. + + PR target/111334 + +gcc/ChangeLog: + + * config/loongarch/loongarch.md: Fix bug of '<optab>di3_fake'. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/pr111334.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/loongarch.md | 20 ++++++---- + gcc/testsuite/gcc.target/loongarch/pr111334.c | 39 +++++++++++++++++++ + 2 files changed, 52 insertions(+), 7 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/loongarch/pr111334.c + +diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md +index 264cd325c..7746116e6 100644 +--- a/gcc/config/loongarch/loongarch.md ++++ b/gcc/config/loongarch/loongarch.md +@@ -72,6 +72,9 @@ + UNSPEC_LUI_H_HI12 + UNSPEC_TLS_LOW + ++ ;; Fake div.wu mod.wu ++ UNSPEC_FAKE_ANY_DIV ++ + UNSPEC_SIBCALL_VALUE_MULTIPLE_INTERNAL_1 + UNSPEC_CALL_VALUE_MULTIPLE_INTERNAL_1 + ) +@@ -900,7 +903,7 @@ + (match_operand:GPR 2 "register_operand"))) + "" + { +- if (GET_MODE (operands0) == SImode) ++ if (GET_MODE (operands0) == SImode && TARGET_64BIT) + { + rtx reg1 = gen_reg_rtx (DImode); + rtx reg2 = gen_reg_rtx (DImode); +@@ -920,9 +923,9 @@ + }) + + (define_insn "*<optab><mode>3" +- (set (match_operand:GPR 0 "register_operand" "=r,&r,&r") +- (any_div:GPR (match_operand:GPR 1 "register_operand" "r,r,0") +- (match_operand:GPR 2 "register_operand" "r,r,r"))) ++ (set (match_operand:X 0 "register_operand" "=r,&r,&r") ++ (any_div:X (match_operand:X 1 "register_operand" "r,r,0") ++ (match_operand:X 2 "register_operand" "r,r,r"))) + "" + { + return loongarch_output_division ("<insn>.<d><u>\t%0,%1,%2", operands); +@@ -938,9 +941,12 @@ + (define_insn "<optab>di3_fake" + (set (match_operand:DI 0 "register_operand" "=r,&r,&r") + (sign_extend:DI +- (any_div:SI (match_operand:DI 1 "register_operand" "r,r,0") +- (match_operand:DI 2 "register_operand" "r,r,r")))) +- "" ++ (unspec:SI ++ (subreg:SI ++ (any_div:DI (match_operand:DI 1 "register_operand" "r,r,0") ++ (match_operand:DI 2 "register_operand" "r,r,r")) 0) ++ UNSPEC_FAKE_ANY_DIV))) ++ "TARGET_64BIT" + { + return loongarch_output_division ("<insn>.w<u>\t%0,%1,%2", operands); + } +diff --git a/gcc/testsuite/gcc.target/loongarch/pr111334.c b/gcc/testsuite/gcc.target/loongarch/pr111334.c +new file mode 100644 +index 000000000..47366afcb +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/pr111334.c +@@ -0,0 +1,39 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2" } */ ++ ++unsigned ++util_next_power_of_two (unsigned x) ++{ ++ return (1 << __builtin_clz (x - 1)); ++} ++ ++extern int create_vec_from_array (void); ++ ++struct ac_shader_args { ++ struct { ++ unsigned char offset; ++ unsigned char size; ++ } args384; ++}; ++ ++struct isel_context { ++ const struct ac_shader_args* args; ++ int arg_temps384; ++}; ++ ++ ++void ++add_startpgm (struct isel_context* ctx, unsigned short arg_count) ++{ ++ ++ for (unsigned i = 0, arg = 0; i < arg_count; i++) ++ { ++ unsigned size = ctx->args->argsi.size; ++ unsigned reg = ctx->args->argsi.offset; ++ ++ if (reg % ( 4 < util_next_power_of_two (size) ++ ? 4 : util_next_power_of_two (size))) ++ ctx->arg_tempsi = create_vec_from_array (); ++ } ++} ++ +-- +2.33.0 +
View file
_service:tar_scm:LoongArch-Fix-pr106828-by-define-hook-TARGET_ASAN_SH.patch
Added
@@ -0,0 +1,69 @@ +From a70fe51d9813d490a89cbc8da1ae4b040bf8b37e Mon Sep 17 00:00:00 2001 +From: Lulu Cheng <chenglulu@loongson.cn> +Date: Wed, 7 Sep 2022 11:25:45 +0800 +Subject: PATCH 017/124 LoongArch: Fix pr106828 by define hook + TARGET_ASAN_SHADOW_OFFSET in loongarch backend PR106828. + +gcc/ChangeLog: + + PR target/106828 + * config/loongarch/loongarch.cc (loongarch_asan_shadow_offset): New. + (TARGET_ASAN_SHADOW_OFFSET): New. + +gcc/testsuite/ChangeLog: + + PR target/106828 + * g++.target/loongarch/pr106828.C: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/loongarch.cc | 13 +++++++++++++ + gcc/testsuite/g++.target/loongarch/pr106828.C | 4 ++++ + 2 files changed, 17 insertions(+) + create mode 100644 gcc/testsuite/g++.target/loongarch/pr106828.C + +diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc +index c9187bf81..98c0e26cd 100644 +--- a/gcc/config/loongarch/loongarch.cc ++++ b/gcc/config/loongarch/loongarch.cc +@@ -6466,6 +6466,16 @@ loongarch_use_anchors_for_symbol_p (const_rtx symbol) + return default_use_anchors_for_symbol_p (symbol); + } + ++/* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */ ++ ++static unsigned HOST_WIDE_INT ++loongarch_asan_shadow_offset (void) ++{ ++ /* We only have libsanitizer support for LOONGARCH64 at present. ++ This value is taken from the file libsanitizer/asan/asan_mappint.h. */ ++ return TARGET_64BIT ? (HOST_WIDE_INT_1 << 46) : 0; ++} ++ + /* Initialize the GCC target structure. */ + #undef TARGET_ASM_ALIGNED_HI_OP + #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" +@@ -6660,6 +6670,9 @@ loongarch_use_anchors_for_symbol_p (const_rtx symbol) + #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P + #define TARGET_USE_ANCHORS_FOR_SYMBOL_P loongarch_use_anchors_for_symbol_p + ++#undef TARGET_ASAN_SHADOW_OFFSET ++#define TARGET_ASAN_SHADOW_OFFSET loongarch_asan_shadow_offset ++ + struct gcc_target targetm = TARGET_INITIALIZER; + + #include "gt-loongarch.h" +diff --git a/gcc/testsuite/g++.target/loongarch/pr106828.C b/gcc/testsuite/g++.target/loongarch/pr106828.C +new file mode 100644 +index 000000000..190c1db71 +--- /dev/null ++++ b/gcc/testsuite/g++.target/loongarch/pr106828.C +@@ -0,0 +1,4 @@ ++/* { dg-do-preprocess } */ ++/* { dg-options "-mabi=lp64d -fsanitize=address" } */ ++ ++/* Tests whether the compiler supports compile option '-fsanitize=address'. */ +-- +2.33.0 +
View file
_service:tar_scm:LoongArch-Fix-unintentional-bash-ism-in-r14-3665.patch
Added
@@ -0,0 +1,31 @@ +From 8e5c9f349877af07dde4804974d47625c1292956 Mon Sep 17 00:00:00 2001 +From: Yang Yujie <yangyujie@loongson.cn> +Date: Wed, 6 Sep 2023 17:57:47 +0800 +Subject: PATCH 070/124 LoongArch: Fix unintentional bash-ism in r14-3665. + +gcc/ChangeLog: + + * config.gcc: remove non-POSIX syntax "<<<". + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config.gcc | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/gcc/config.gcc b/gcc/config.gcc +index 19f584344..57e724080 100644 +--- a/gcc/config.gcc ++++ b/gcc/config.gcc +@@ -5263,7 +5263,7 @@ case "${target}" in + if test x${parse_state} = x"abi-base"; then + # Base ABI type + case ${component} in +- lp64d | lp64f | lp64s) elem_tmp="ABI_BASE_$(tr a-z A-Z <<< ${component}),";; ++ lp64d | lp64f | lp64s) elem_tmp="ABI_BASE_$(echo ${component} | tr a-z A-Z),";; + *) + echo "Unknown base ABI \"${component}\" in --with-multilib-list." 1>&2 + exit 1 +-- +2.33.0 +
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_service:tar_scm:LoongArch-Fix-unintentionally-breakage-in-r14-3665.patch
Added
@@ -0,0 +1,34 @@ +From 8de6f5e1aad2a1ff85ff3a4b732055d625c61139 Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao <xry111@xry111.site> +Date: Tue, 5 Sep 2023 20:02:51 +0800 +Subject: PATCH 067/124 LoongArch: Fix unintentionally breakage in r14-3665 + +Fix a build failure with no system assembler or system old assembler. + +gcc/ChangeLog: + + * config/loongarch/loongarch-opts.h (HAVE_AS_EXPLICIT_RELOCS): + Define to 0 if not defined yet. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/loongarch-opts.h | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/gcc/config/loongarch/loongarch-opts.h b/gcc/config/loongarch/loongarch-opts.h +index e3f9b6f99..0d148e43b 100644 +--- a/gcc/config/loongarch/loongarch-opts.h ++++ b/gcc/config/loongarch/loongarch-opts.h +@@ -93,4 +93,8 @@ loongarch_update_gcc_opt_status (struct loongarch_target *target, + while -mno-memcpy imposes a global constraint. */ + #define TARGET_DO_OPTIMIZE_BLOCK_MOVE_P loongarch_do_optimize_block_move_p() + ++#ifndef HAVE_AS_EXPLICIT_RELOCS ++#define HAVE_AS_EXPLICIT_RELOCS 0 ++#endif ++ + #endif /* LOONGARCH_OPTS_H */ +-- +2.33.0 +
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_service:tar_scm:LoongArch-Fix-up-memcpy-vec-3.c-test-case.patch
Added
@@ -0,0 +1,33 @@ +From 78896e68f50164af7827e8da01a7220764d1e296 Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao <xry111@xry111.site> +Date: Sat, 9 Sep 2023 16:18:06 +0800 +Subject: PATCH 075/124 LoongArch: Fix up memcpy-vec-3.c test case + +The generic code will split 16-byte copy into two 8-byte copies, so the +vector code wouldn't be used even if -mno-strict-align. This +contradicted with the purpose of this test case. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/memcpy-vec-3.c: Increase the amount of + copied bytes to 32. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/testsuite/gcc.target/loongarch/memcpy-vec-3.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/gcc/testsuite/gcc.target/loongarch/memcpy-vec-3.c b/gcc/testsuite/gcc.target/loongarch/memcpy-vec-3.c +index 233ed2150..db2ea510b 100644 +--- a/gcc/testsuite/gcc.target/loongarch/memcpy-vec-3.c ++++ b/gcc/testsuite/gcc.target/loongarch/memcpy-vec-3.c +@@ -3,4 +3,4 @@ + /* { dg-final { scan-assembler-not "vst" } } */ + + extern char a, b; +-void test() { __builtin_memcpy(a, b, 16); } ++void test() { __builtin_memcpy(a, b, 32); } +-- +2.33.0 +
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_service:tar_scm:LoongArch-Fixed-a-bug-in-the-loongarch-architecture-.patch
Added
@@ -0,0 +1,43 @@ +From 80ed9ab39d9b1b08ad9d054f16d65b2a249a89e5 Mon Sep 17 00:00:00 2001 +From: Lulu Cheng <chenglulu@loongson.cn> +Date: Wed, 12 Oct 2022 11:02:11 +0800 +Subject: PATCH 022/124 LoongArch: Fixed a bug in the loongarch architecture + of libitm package. + +Add a soft floating point condition to the register recovery part of the code. + +libitm/ChangeLog: + + * config/loongarch/sjlj.S: Add a soft floating point condition to the + register recovery part of the code. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + libitm/config/loongarch/sjlj.S | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/libitm/config/loongarch/sjlj.S b/libitm/config/loongarch/sjlj.S +index a5f9fadde..f896e400e 100644 +--- a/libitm/config/loongarch/sjlj.S ++++ b/libitm/config/loongarch/sjlj.S +@@ -104,6 +104,8 @@ GTM_longjmp: + GPR_L $s7, $r5, 10*SZ_GPR + GPR_L $s8, $r5, 11*SZ_GPR + ++#if !defined(__loongarch_soft_float) ++ /* Callee-saved scratch FPRs (f24-f31) */ + FPR_L $f24, $r5, 12*SZ_GPR + 0*SZ_FPR + FPR_L $f25, $r5, 12*SZ_GPR + 1*SZ_FPR + FPR_L $f26, $r5, 12*SZ_GPR + 2*SZ_FPR +@@ -112,6 +114,7 @@ GTM_longjmp: + FPR_L $f29, $r5, 12*SZ_GPR + 5*SZ_FPR + FPR_L $f30, $r5, 12*SZ_GPR + 6*SZ_FPR + FPR_L $f31, $r5, 12*SZ_GPR + 7*SZ_FPR ++#endif + + GPR_L $r7, $r5, 2*SZ_GPR + GPR_L $fp, $r5, 0*SZ_GPR +-- +2.33.0 +
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_service:tar_scm:LoongArch-Fixed-a-compilation-failure-with-c-in-inli.patch
Added
@@ -0,0 +1,182 @@ +From 49a63dbaf3b4296f0b1f8a0e11790cc3455aeec7 Mon Sep 17 00:00:00 2001 +From: Lulu Cheng <chenglulu@loongson.cn> +Date: Wed, 18 Jan 2023 11:06:56 +0800 +Subject: PATCH 034/124 LoongArch: Fixed a compilation failure with '%c' in + inline assembly PR107731. + +Co-authored-by: Yang Yujie <yangyujie@loongson.cn> + + PR target/107731 + +gcc/ChangeLog: + + * config/loongarch/loongarch.cc (loongarch_classify_address): + Add precessint for CONST_INT. + (loongarch_print_operand_reloc): Operand modifier 'c' is supported. + (loongarch_print_operand): Increase the processing of '%c'. + * doc/extend.texi: Adds documents for LoongArch operand modifiers. + And port the public operand modifiers information to this document. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/tst-asm-const.c: Moved to... + * gcc.target/loongarch/pr107731.c: ...here. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/loongarch.cc | 14 +++++ + gcc/doc/extend.texi | 51 +++++++++++++++++-- + .../loongarch/{tst-asm-const.c => pr107731.c} | 6 +-- + 3 files changed, 64 insertions(+), 7 deletions(-) + rename gcc/testsuite/gcc.target/loongarch/{tst-asm-const.c => pr107731.c} (78%) + +diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc +index e59edc4cd..1a4686f03 100644 +--- a/gcc/config/loongarch/loongarch.cc ++++ b/gcc/config/loongarch/loongarch.cc +@@ -2074,6 +2074,11 @@ loongarch_classify_address (struct loongarch_address_info *info, rtx x, + return (loongarch_valid_base_register_p (info->reg, mode, strict_p) + && loongarch_valid_lo_sum_p (info->symbol_type, mode, + info->offset)); ++ case CONST_INT: ++ /* Small-integer addresses don't occur very often, but they ++ are legitimate if $r0 is a valid base register. */ ++ info->type = ADDRESS_CONST_INT; ++ return IMM12_OPERAND (INTVAL (x)); + + default: + return false; +@@ -4932,6 +4937,7 @@ loongarch_print_operand_reloc (FILE *file, rtx op, bool hi64_part, + + 'A' Print a _DB suffix if the memory model requires a release. + 'b' Print the address of a memory operand, without offset. ++ 'c' Print an integer. + 'C' Print the integer branch condition for comparison OP. + 'd' Print CONST_INT OP in decimal. + 'F' Print the FPU branch condition for comparison OP. +@@ -4978,6 +4984,14 @@ loongarch_print_operand (FILE *file, rtx op, int letter) + fputs ("_db", file); + break; + ++ case 'c': ++ if (CONST_INT_P (op)) ++ fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op)); ++ else ++ output_operand_lossage ("unsupported operand for code '%c'", letter); ++ ++ break; ++ + case 'C': + loongarch_print_int_branch_condition (file, code, letter); + break; +diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi +index da2840c23..3c101ca89 100644 +--- a/gcc/doc/extend.texi ++++ b/gcc/doc/extend.texi +@@ -10414,8 +10414,10 @@ ensures that modifying @var{a} does not affect the address referenced by + is undefined if @var{a} is modified before using @var{b}. + + @code{asm} supports operand modifiers on operands (for example @samp{%k2} +-instead of simply @samp{%2}). Typically these qualifiers are hardware +-dependent. The list of supported modifiers for x86 is found at ++instead of simply @samp{%2}). @ref{GenericOperandmodifiers, ++Generic Operand modifiers} lists the modifiers that are available ++on all targets. Other modifiers are hardware dependent. ++For example, the list of supported modifiers for x86 is found at + @ref{x86Operandmodifiers,x86 Operand modifiers}. + + If the C code that follows the @code{asm} makes no use of any of the output +@@ -10683,8 +10685,10 @@ optimizers may discard the @code{asm} statement as unneeded + (see @ref{Volatile}). + + @code{asm} supports operand modifiers on operands (for example @samp{%k2} +-instead of simply @samp{%2}). Typically these qualifiers are hardware +-dependent. The list of supported modifiers for x86 is found at ++instead of simply @samp{%2}). @ref{GenericOperandmodifiers, ++Generic Operand modifiers} lists the modifiers that are available ++on all targets. Other modifiers are hardware dependent. ++For example, the list of supported modifiers for x86 is found at + @ref{x86Operandmodifiers,x86 Operand modifiers}. + + In this example using the fictitious @code{combine} instruction, the +@@ -11036,6 +11040,30 @@ lab: + @} + @end example + ++@anchor{GenericOperandmodifiers} ++@subsubsection Generic Operand Modifiers ++@noindent ++The following table shows the modifiers supported by all targets and their effects: ++ ++@multitable {Modifier} {Description} {Example} ++@headitem Modifier @tab Description @tab Example ++@item @code{c} ++@tab Require a constant operand and print the constant expression with no punctuation. ++@tab @code{%c0} ++@item @code{n} ++@tab Like @samp{%c} except that the value of the constant is negated before printing. ++@tab @code{%n0} ++@item @code{a} ++@tab Substitute a memory reference, with the actual operand treated as the address. ++This may be useful when outputting a ``load address'' instruction, because ++often the assembler syntax for such an instruction requires you to write the ++operand as if it were a memory reference. ++@tab @code{%a0} ++@item @code{l} ++@tab Print the label name with no punctuation. ++@tab @code{%l0} ++@end multitable ++ + @anchor{x86Operandmodifiers} + @subsubsection x86 Operand Modifiers + +@@ -11386,6 +11414,21 @@ constant. Used to select the specified bit position. + @item @code{x} @tab Equivialent to @code{X}, but only for pointers. + @end multitable + ++@anchor{loongarchOperandmodifiers} ++@subsubsection LoongArch Operand Modifiers ++ ++The list below describes the supported modifiers and their effects for LoongArch. ++ ++@multitable @columnfractions .10 .90 ++@headitem Modifier @tab Description ++@item @code{d} @tab Same as @code{c}. ++@item @code{i} @tab Print the character ''@code{i}'' if the operand is not a register. ++@item @code{m} @tab Same as @code{c}, but the printed value is @code{operand - 1}. ++@item @code{X} @tab Print a constant integer operand in hexadecimal. ++@item @code{z} @tab Print the operand in its unmodified form, followed by a comma. ++@end multitable ++ ++ + @lowersections + @include md.texi + @raisesections +diff --git a/gcc/testsuite/gcc.target/loongarch/tst-asm-const.c b/gcc/testsuite/gcc.target/loongarch/pr107731.c +similarity index 78% +rename from gcc/testsuite/gcc.target/loongarch/tst-asm-const.c +rename to gcc/testsuite/gcc.target/loongarch/pr107731.c +index 2e04b99e3..80d84c48c 100644 +--- a/gcc/testsuite/gcc.target/loongarch/tst-asm-const.c ++++ b/gcc/testsuite/gcc.target/loongarch/pr107731.c +@@ -1,13 +1,13 @@ +-/* Test asm const. */ + /* { dg-do compile } */ + /* { dg-final { scan-assembler-times "foo:.*\\.long 1061109567.*\\.long 52" 1 } } */ ++ + int foo () + { + __asm__ volatile ( + "foo:" + "\n\t" +- ".long %a0\n\t" +- ".long %a1\n\t" ++ ".long %c0\n\t" ++ ".long %c1\n\t" + : + :"i"(0x3f3f3f3f), "i"(52) + : +-- +2.33.0 +
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_service:tar_scm:LoongArch-Fixed-a-typo-in-the-comment-information-of.patch
Added
@@ -0,0 +1,33 @@ +From cbb5f181544e35b119fee4ed150bec24eee7179c Mon Sep 17 00:00:00 2001 +From: Lulu Cheng <chenglulu@loongson.cn> +Date: Wed, 28 Sep 2022 16:35:06 +0800 +Subject: PATCH 020/124 LoongArch: Fixed a typo in the comment information of + the function loongarch_asan_shadow_offset. + +gcc/ChangeLog: + + * config/loongarch/loongarch.cc (loongarch_asan_shadow_offset): + Fixed typo in "asan_mapping.h". + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/loongarch.cc | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc +index 98c0e26cd..e9ba3374e 100644 +--- a/gcc/config/loongarch/loongarch.cc ++++ b/gcc/config/loongarch/loongarch.cc +@@ -6472,7 +6472,7 @@ static unsigned HOST_WIDE_INT + loongarch_asan_shadow_offset (void) + { + /* We only have libsanitizer support for LOONGARCH64 at present. +- This value is taken from the file libsanitizer/asan/asan_mappint.h. */ ++ This value is taken from the file libsanitizer/asan/asan_mapping.h. */ + return TARGET_64BIT ? (HOST_WIDE_INT_1 << 46) : 0; + } + +-- +2.33.0 +
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_service:tar_scm:LoongArch-Generate-bytepick.-wd-for-suitable-bit-ope.patch
Added
@@ -0,0 +1,196 @@ +From 9311c0f56086e38fe5e9bf4bbfc2e37d0f18347c Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao <xry111@xry111.site> +Date: Fri, 3 Feb 2023 17:06:06 +0800 +Subject: PATCH 036/124 LoongArch: Generate bytepick.wd for suitable bit + operation pattern + +We can use bytepick.wd for + + a << (8 * x) | b >> (8 * (sizeof(a) - x)) + +while a and b are uint32_t or uint64_t. This is useful for some cases, +for example: +https://sourceware.org/pipermail/libc-alpha/2023-February/145203.html + +gcc/ChangeLog: + + * config/loongarch/loongarch.md (bytepick_w_ashift_amount): + New define_int_iterator. + (bytepick_d_ashift_amount): Likewise. + (bytepick_imm): New define_int_attr. + (bytepick_w_lshiftrt_amount): Likewise. + (bytepick_d_lshiftrt_amount): Likewise. + (bytepick_w_<bytepick_imm>): New define_insn template. + (bytepick_w_<bytepick_imm>_extend): Likewise. + (bytepick_d_<bytepick_imm>): Likewise. + (bytepick_w): Remove unused define_insn. + (bytepick_d): Likewise. + (UNSPEC_BYTEPICK_W): Remove unused unspec. + (UNSPEC_BYTEPICK_D): Likewise. + * config/loongarch/predicates.md (const_0_to_3_operand): + Remove unused define_predicate. + (const_0_to_7_operand): Likewise. + +gcc/testsuite/ChangeLog: + + * g++.target/loongarch/bytepick.C: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/loongarch.md | 60 ++++++++++++++----- + gcc/config/loongarch/predicates.md | 8 --- + gcc/testsuite/g++.target/loongarch/bytepick.C | 32 ++++++++++ + 3 files changed, 77 insertions(+), 23 deletions(-) + create mode 100644 gcc/testsuite/g++.target/loongarch/bytepick.C + +diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md +index f61db66d5..833b94753 100644 +--- a/gcc/config/loongarch/loongarch.md ++++ b/gcc/config/loongarch/loongarch.md +@@ -48,8 +48,6 @@ + UNSPEC_EH_RETURN + + ;; Bit operation +- UNSPEC_BYTEPICK_W +- UNSPEC_BYTEPICK_D + UNSPEC_BITREV_4B + UNSPEC_BITREV_8B + +@@ -544,6 +542,27 @@ + (UNSPEC_FTINTRM "0") + (UNSPEC_FTINTRP "0")) + ++;; Iterator and attributes for bytepick.d ++(define_int_iterator bytepick_w_ashift_amount 8 16 24) ++(define_int_attr bytepick_w_lshiftrt_amount (8 "24") ++ (16 "16") ++ (24 "8")) ++(define_int_iterator bytepick_d_ashift_amount 8 16 24 32 40 48 56) ++(define_int_attr bytepick_d_lshiftrt_amount (8 "56") ++ (16 "48") ++ (24 "40") ++ (32 "32") ++ (40 "24") ++ (48 "16") ++ (56 "8")) ++(define_int_attr bytepick_imm (8 "1") ++ (16 "2") ++ (24 "3") ++ (32 "4") ++ (40 "5") ++ (48 "6") ++ (56 "7")) ++ + ;; + ;; .................... + ;; +@@ -3364,24 +3383,35 @@ + (set_attr "type" "unknown") + (set_attr "mode" "<MODE>")) + +-(define_insn "bytepick_w" ++(define_insn "bytepick_w_<bytepick_imm>" + (set (match_operand:SI 0 "register_operand" "=r") +- (unspec:SI (match_operand:SI 1 "register_operand" "r") +- (match_operand:SI 2 "register_operand" "r") +- (match_operand:SI 3 "const_0_to_3_operand" "n") +- UNSPEC_BYTEPICK_W)) ++ (ior:SI (lshiftrt (match_operand:SI 1 "register_operand" "r") ++ (const_int <bytepick_w_lshiftrt_amount>)) ++ (ashift (match_operand:SI 2 "register_operand" "r") ++ (const_int bytepick_w_ashift_amount)))) + "" +- "bytepick.w\t%0,%1,%2,%z3" ++ "bytepick.w\t%0,%1,%2,<bytepick_imm>" + (set_attr "mode" "SI")) + +-(define_insn "bytepick_d" ++(define_insn "bytepick_w_<bytepick_imm>_extend" + (set (match_operand:DI 0 "register_operand" "=r") +- (unspec:DI (match_operand:DI 1 "register_operand" "r") +- (match_operand:DI 2 "register_operand" "r") +- (match_operand:DI 3 "const_0_to_7_operand" "n") +- UNSPEC_BYTEPICK_D)) +- "" +- "bytepick.d\t%0,%1,%2,%z3" ++ (sign_extend:DI ++ (ior:SI (lshiftrt (match_operand:SI 1 "register_operand" "r") ++ (const_int <bytepick_w_lshiftrt_amount>)) ++ (ashift (match_operand:SI 2 "register_operand" "r") ++ (const_int bytepick_w_ashift_amount))))) ++ "TARGET_64BIT" ++ "bytepick.w\t%0,%1,%2,<bytepick_imm>" ++ (set_attr "mode" "SI")) ++ ++(define_insn "bytepick_d_<bytepick_imm>" ++ (set (match_operand:DI 0 "register_operand" "=r") ++ (ior:DI (lshiftrt (match_operand:DI 1 "register_operand" "r") ++ (const_int <bytepick_d_lshiftrt_amount>)) ++ (ashift (match_operand:DI 2 "register_operand" "r") ++ (const_int bytepick_d_ashift_amount)))) ++ "TARGET_64BIT" ++ "bytepick.d\t%0,%1,%2,<bytepick_imm>" + (set_attr "mode" "DI")) + + (define_insn "bitrev_4b" +diff --git a/gcc/config/loongarch/predicates.md b/gcc/config/loongarch/predicates.md +index 58c3dc226..3c32b2987 100644 +--- a/gcc/config/loongarch/predicates.md ++++ b/gcc/config/loongarch/predicates.md +@@ -91,14 +91,6 @@ + (ior (match_operand 0 "const_1_operand") + (match_operand 0 "register_operand"))) + +-(define_predicate "const_0_to_3_operand" +- (and (match_code "const_int") +- (match_test "IN_RANGE (INTVAL (op), 0, 3)"))) +- +-(define_predicate "const_0_to_7_operand" +- (and (match_code "const_int") +- (match_test "IN_RANGE (INTVAL (op), 0, 7)"))) +- + (define_predicate "lu52i_mask_operand" + (and (match_code "const_int") + (match_test "UINTVAL (op) == 0xfffffffffffff"))) +diff --git a/gcc/testsuite/g++.target/loongarch/bytepick.C b/gcc/testsuite/g++.target/loongarch/bytepick.C +new file mode 100644 +index 000000000..a39e2fa65 +--- /dev/null ++++ b/gcc/testsuite/g++.target/loongarch/bytepick.C +@@ -0,0 +1,32 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -mabi=lp64d" } */ ++/* { dg-final { scan-assembler-times "bytepick.w\t\\\$r4,\\\$r5,\\\$r4" 3 } } */ ++/* { dg-final { scan-assembler-times "bytepick.d\t\\\$r4,\\\$r5,\\\$r4" 7 } } */ ++/* { dg-final { scan-assembler-not "slli.w" } } */ ++ ++template <class T, int offs> ++T ++merge (T a, T b) ++{ ++ return a << offs | b >> (8 * sizeof (T) - offs); ++} ++ ++using u32 = __UINT32_TYPE__; ++using u64 = __UINT64_TYPE__; ++using i64 = __INT64_TYPE__; ++ ++template u32 merge<u32, 8> (u32, u32); ++template u32 merge<u32, 16> (u32, u32); ++template u32 merge<u32, 24> (u32, u32); ++ ++template u64 merge<u64, 8> (u64, u64); ++template u64 merge<u64, 16> (u64, u64); ++template u64 merge<u64, 24> (u64, u64); ++template u64 merge<u64, 32> (u64, u64); ++template u64 merge<u64, 40> (u64, u64); ++template u64 merge<u64, 48> (u64, u64); ++template u64 merge<u64, 56> (u64, u64); ++ ++/* we cannot use bytepick for the following cases */ ++template i64 merge<i64, 8> (i64, i64); ++template u64 merge<u64, 42> (u64, u64); +-- +2.33.0 +
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_service:tar_scm:LoongArch-Get-__tls_get_addr-address-through-got-tab.patch
Added
@@ -0,0 +1,71 @@ +From a96dee6ba3c916f9a4329b196a0c5a1652fe294f Mon Sep 17 00:00:00 2001 +From: Lulu Cheng <chenglulu@loongson.cn> +Date: Thu, 18 Aug 2022 09:57:14 +0800 +Subject: PATCH 010/124 LoongArch: Get __tls_get_addr address through got + table when disable plt. + +Fix bug, ICE with tls gd/ld var with -fno-plt. + +gcc/ChangeLog: + + * config/loongarch/loongarch.cc (loongarch_call_tls_get_addr): + Get __tls_get_addr address through got table when disable plt. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/tls-gd-noplt.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/loongarch.cc | 14 ++++++++++++-- + gcc/testsuite/gcc.target/loongarch/tls-gd-noplt.c | 12 ++++++++++++ + 2 files changed, 24 insertions(+), 2 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/loongarch/tls-gd-noplt.c + +diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc +index 1b5af2c7d..76bf55ea4 100644 +--- a/gcc/config/loongarch/loongarch.cc ++++ b/gcc/config/loongarch/loongarch.cc +@@ -2448,8 +2448,18 @@ loongarch_call_tls_get_addr (rtx sym, enum loongarch_symbol_type type, rtx v0) + gcc_unreachable (); + } + +- insn = emit_call_insn (gen_call_value_internal (v0, loongarch_tls_symbol, +- const0_rtx)); ++ if (flag_plt) ++ insn = emit_call_insn (gen_call_value_internal (v0, loongarch_tls_symbol, ++ const0_rtx)); ++ else ++ { ++ rtx dest = gen_reg_rtx (Pmode); ++ rtx high = gen_reg_rtx (Pmode); ++ loongarch_emit_move (high, gen_rtx_HIGH (Pmode, loongarch_tls_symbol)); ++ emit_insn (gen_ld_from_got (Pmode, dest, high, loongarch_tls_symbol)); ++ insn = emit_call_insn (gen_call_value_internal (v0, dest, const0_rtx)); ++ } ++ + RTL_CONST_CALL_P (insn) = 1; + use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0); + insn = get_insns (); +diff --git a/gcc/testsuite/gcc.target/loongarch/tls-gd-noplt.c b/gcc/testsuite/gcc.target/loongarch/tls-gd-noplt.c +new file mode 100644 +index 000000000..32a0acf9b +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/tls-gd-noplt.c +@@ -0,0 +1,12 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -fno-plt -mcmodel=normal" } */ ++/* { dg-final { scan-assembler "pcalau12i\t.*%got_pc_hi20\\(__tls_get_addr\\)" } } */ ++ ++__attribute__ ((tls_model ("global-dynamic"))) __thread int a; ++ ++void ++test (void) ++{ ++ a = 10; ++} ++ +-- +2.33.0 +
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_service:tar_scm:LoongArch-Implement-128-bit-floating-point-functions.patch
Added
@@ -0,0 +1,204 @@ +From 12ab9eae9e8a5b83c778182f15c6216bcbc3dc36 Mon Sep 17 00:00:00 2001 +From: chenxiaolong <chenxiaolong@loongson.cn> +Date: Fri, 1 Sep 2023 11:22:42 +0800 +Subject: PATCH 054/124 LoongArch: Implement 128-bit floating point functions + in gcc. + +During implementation, float128_type_node is bound with the type "__float128" +so that the compiler can correctly identify the type of the function. The +"q" suffix is associated with the "f128" function, which makes GCC more +flexible to support different user input cases, implementing functions such +as __builtin_{huge_valq, infq, fabsq, copysignq, nanq, nansq}. + +gcc/ChangeLog: + + * config/loongarch/loongarch-builtins.cc (loongarch_init_builtins): + Associate the __float128 type to float128_type_node so that it can + be recognized by the compiler. + * config/loongarch/loongarch-c.cc (loongarch_cpu_cpp_builtins): + Add the flag "FLOAT128_TYPE" to gcc and associate a function + with the suffix "q" to "f128". + * doc/extend.texi:Added support for 128-bit floating-point functions on + the LoongArch architecture. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/math-float-128.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/loongarch-builtins.cc | 5 ++ + gcc/config/loongarch/loongarch-c.cc | 11 +++ + gcc/doc/extend.texi | 20 ++++- + .../gcc.target/loongarch/math-float-128.c | 81 +++++++++++++++++++ + 4 files changed, 114 insertions(+), 3 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/loongarch/math-float-128.c + +diff --git a/gcc/config/loongarch/loongarch-builtins.cc b/gcc/config/loongarch/loongarch-builtins.cc +index 64fe11168..cb0ea1664 100644 +--- a/gcc/config/loongarch/loongarch-builtins.cc ++++ b/gcc/config/loongarch/loongarch-builtins.cc +@@ -256,6 +256,11 @@ loongarch_init_builtins (void) + unsigned int i; + tree type; + ++ /* Register the type float128_type_node as a built-in type and ++ give it an alias "__float128". */ ++ (*lang_hooks.types.register_builtin_type) (float128_type_node, ++ "__float128"); ++ + /* Iterate through all of the bdesc arrays, initializing all of the + builtin functions. */ + for (i = 0; i < ARRAY_SIZE (loongarch_builtins); i++) +diff --git a/gcc/config/loongarch/loongarch-c.cc b/gcc/config/loongarch/loongarch-c.cc +index d6e3e19f0..f779a7355 100644 +--- a/gcc/config/loongarch/loongarch-c.cc ++++ b/gcc/config/loongarch/loongarch-c.cc +@@ -99,6 +99,17 @@ loongarch_cpu_cpp_builtins (cpp_reader *pfile) + else + builtin_define ("__loongarch_frlen=0"); + ++ /* Add support for FLOAT128_TYPE on the LoongArch architecture. */ ++ builtin_define ("__FLOAT128_TYPE__"); ++ ++ /* Map the old _Float128 'q' builtins into the new 'f128' builtins. */ ++ builtin_define ("__builtin_fabsq=__builtin_fabsf128"); ++ builtin_define ("__builtin_copysignq=__builtin_copysignf128"); ++ builtin_define ("__builtin_nanq=__builtin_nanf128"); ++ builtin_define ("__builtin_nansq=__builtin_nansf128"); ++ builtin_define ("__builtin_infq=__builtin_inff128"); ++ builtin_define ("__builtin_huge_valq=__builtin_huge_valf128"); ++ + /* Native Data Sizes. */ + builtin_define_with_int_value ("_LOONGARCH_SZINT", INT_TYPE_SIZE); + builtin_define_with_int_value ("_LOONGARCH_SZLONG", LONG_TYPE_SIZE); +diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi +index 1d1bac255..bb19d0f27 100644 +--- a/gcc/doc/extend.texi ++++ b/gcc/doc/extend.texi +@@ -1085,10 +1085,10 @@ types. + As an extension, GNU C and GNU C++ support additional floating + types, which are not supported by all targets. + @itemize @bullet +-@item @code{__float128} is available on i386, x86_64, IA-64, and +-hppa HP-UX, as well as on PowerPC GNU/Linux targets that enable ++@item @code{__float128} is available on i386, x86_64, IA-64, LoongArch ++and hppa HP-UX, as well as on PowerPC GNU/Linux targets that enable + the vector scalar (VSX) instruction set. @code{__float128} supports +-the 128-bit floating type. On i386, x86_64, PowerPC, and IA-64 ++the 128-bit floating type. On i386, x86_64, PowerPC, LoongArch and IA-64, + other than HP-UX, @code{__float128} is an alias for @code{_Float128}. + On hppa and IA-64 HP-UX, @code{__float128} is an alias for @code{long + double}. +@@ -16257,6 +16257,20 @@ function you need to include @code{larchintrin.h}. + void __break (imm0_32767) + @end smallexample + ++Additional built-in functions are available for LoongArch family ++processors to efficiently use 128-bit floating-point (__float128) ++values. ++ ++The following are the basic built-in functions supported. ++@smallexample ++__float128 __builtin_fabsq (__float128); ++__float128 __builtin_copysignq (__float128, __float128); ++__float128 __builtin_infq (void); ++__float128 __builtin_huge_valq (void); ++__float128 __builtin_nanq (void); ++__float128 __builtin_nansq (void); ++@end smallexample ++ + @node MIPS DSP Built-in Functions + @subsection MIPS DSP Built-in Functions + +diff --git a/gcc/testsuite/gcc.target/loongarch/math-float-128.c b/gcc/testsuite/gcc.target/loongarch/math-float-128.c +new file mode 100644 +index 000000000..387566a57 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/math-float-128.c +@@ -0,0 +1,81 @@ ++/* { dg-do compile } */ ++/* { dg-options " -march=loongarch64 -O2 " } */ ++/* { dg-final { scan-assembler-not "my_fabsq2:.*\\bl\t%plt\\(__builtin_fabsq\\).*my_fabsq2" } } */ ++/* { dg-final { scan-assembler-not "my_copysignq2:.*\\bl\t%plt\\(__builtin_copysignq\\).*my_copysignq2" } } */ ++/* { dg-final { scan-assembler-not "my_infq2:.*\\bl\t%plt\\(__builtin_infq\\).*my_infq2" } } */ ++/* { dg-final { scan-assembler-not "my_huge_valq2:.*\\bl\t%plt\\(__builtin_huge_valq\\).*my_huge_valq2" } } */ ++/* { dg-final { scan-assembler-not "my_nanq2:.*\\bl\t%plt\\(__builtin_nanq\\).*my_nanq2" } } */ ++/* { dg-final { scan-assembler-not "my_nansq2:.*\\bl\t%plt\\(__builtin_nansq\\).*my_nansq2" } } */ ++ ++__float128 ++my_fabsq1 (__float128 a) ++{ ++ return __builtin_fabsq (a); ++} ++ ++_Float128 ++my_fabsq2 (_Float128 a) ++{ ++ return __builtin_fabsq (a); ++} ++ ++__float128 ++my_copysignq1 (__float128 a, __float128 b) ++{ ++ return __builtin_copysignq (a, b); ++} ++ ++_Float128 ++my_copysignq2 (_Float128 a, _Float128 b) ++{ ++ return __builtin_copysignq (a, b); ++} ++ ++__float128 ++my_infq1 (void) ++{ ++ return __builtin_infq (); ++} ++ ++_Float128 ++my_infq2 (void) ++{ ++ return __builtin_infq (); ++} ++ ++__float128 ++my_huge_valq1 (void) ++{ ++ return __builtin_huge_valq (); ++} ++ ++_Float128 ++my_huge_valq2 (void) ++{ ++ return __builtin_huge_valq (); ++} ++ ++__float128 ++my_nanq1 (void) ++{ ++ return __builtin_nanq (""); ++} ++ ++_Float128 ++my_nanq2 (void) ++{ ++ return __builtin_nanq (""); ++} ++ ++__float128 ++my_nansq1 (void) ++{ ++ return __builtin_nansq (""); ++} ++ ++_Float128 ++my_nansq2 (void) ++{ ++ return __builtin_nansq ("");
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_service:tar_scm:LoongArch-Improve-GAR-store-for-va_list.patch
Added
@@ -0,0 +1,83 @@ +From 4075f299ca6a5d15fdb46f877cbe11b7166a19ff Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao <xry111@xry111.site> +Date: Wed, 29 Mar 2023 01:36:09 +0800 +Subject: PATCH 042/124 LoongArch: Improve GAR store for va_list + +LoongArch backend used to save all GARs for a function with variable +arguments. But sometimes a function only accepts variable arguments for +a purpose like C++ function overloading. For example, POSIX defines +open() as: + + int open(const char *path, int oflag, ...); + +But only two forms are actually used: + + int open(const char *pathname, int flags); + int open(const char *pathname, int flags, mode_t mode); + +So it's obviously a waste to save all 8 GARs in open(). We can use the +cfun->va_list_gpr_size field set by the stdarg pass to only save the +GARs necessary to be saved. + +If the va_list escapes (for example, in fprintf() we pass it to +vfprintf()), stdarg would set cfun->va_list_gpr_size to 255 so we +don't need a special case. + +With this patch, only one GAR ($a2/$r6) is saved in open(). Ideally +even this stack store should be omitted too, but doing so is not trivial +and AFAIK there are no compilers (for any target) performing the "ideal" +optimization here, see https://godbolt.org/z/n1YqWq9c9. + +Bootstrapped and regtested on loongarch64-linux-gnu. Ok for trunk +(GCC 14 or now)? + +gcc/ChangeLog: + + * config/loongarch/loongarch.cc + (loongarch_setup_incoming_varargs): Don't save more GARs than + cfun->va_list_gpr_size / UNITS_PER_WORD. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/va_arg.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/testsuite/gcc.target/loongarch/va_arg.c | 24 +++++++++++++++++++++ + 1 file changed, 24 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/va_arg.c + +diff --git a/gcc/testsuite/gcc.target/loongarch/va_arg.c b/gcc/testsuite/gcc.target/loongarch/va_arg.c +new file mode 100644 +index 000000000..980c96d0e +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/va_arg.c +@@ -0,0 +1,24 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2" } */ ++ ++/* Technically we shouldn't save any register for this function: it should be ++ compiled as if it accepts 3 named arguments. But AFAIK no compilers can ++ achieve this "perfect" optimization now, so just ensure we are using the ++ knowledge provided by stdarg pass and we won't save GARs impossible to be ++ accessed with __builtin_va_arg () when the va_list does not escape. */ ++ ++/* { dg-final { scan-assembler-not "st.*r7" } } */ ++ ++int ++test (int a0, ...) ++{ ++ void *arg; ++ int a1, a2; ++ ++ __builtin_va_start (arg, a0); ++ a1 = __builtin_va_arg (arg, int); ++ a2 = __builtin_va_arg (arg, int); ++ __builtin_va_end (arg); ++ ++ return a0 + a1 + a2; ++} +-- +2.33.0 +
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_service:tar_scm:LoongArch-Improve-cpymemsi-expansion-PR109465.patch
Added
@@ -0,0 +1,339 @@ +From 33fff578e7df7aa7e236efc6c9c85c595918d86a Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao <xry111@xry111.site> +Date: Wed, 12 Apr 2023 11:45:48 +0000 +Subject: PATCH 043/124 LoongArch: Improve cpymemsi expansion PR109465 + +We'd been generating really bad block move sequences which is recently +complained by kernel developers who tried __builtin_memcpy. To improve +it: + +1. Take the advantage of -mno-strict-align. When it is set, set mode + size to UNITS_PER_WORD regardless of the alignment. +2. Half the mode size when (block size) % (mode size) != 0, instead of + falling back to ld.bu/st.b at once. +3. Limit the length of block move sequence considering the number of + instructions, not the size of block. When -mstrict-align is set and + the block is not aligned, the old size limit for straight-line + implementation (64 bytes) was definitely too large (we don't have 64 + registers anyway). + +Change since v1: add a comment about the calculation of num_reg. + +gcc/ChangeLog: + + PR target/109465 + * config/loongarch/loongarch-protos.h + (loongarch_expand_block_move): Add a parameter as alignment RTX. + * config/loongarch/loongarch.h: + (LARCH_MAX_MOVE_BYTES_PER_LOOP_ITER): Remove. + (LARCH_MAX_MOVE_BYTES_STRAIGHT): Remove. + (LARCH_MAX_MOVE_OPS_PER_LOOP_ITER): Define. + (LARCH_MAX_MOVE_OPS_STRAIGHT): Define. + (MOVE_RATIO): Use LARCH_MAX_MOVE_OPS_PER_LOOP_ITER instead of + LARCH_MAX_MOVE_BYTES_PER_LOOP_ITER. + * config/loongarch/loongarch.cc (loongarch_expand_block_move): + Take the alignment from the parameter, but set it to + UNITS_PER_WORD if !TARGET_STRICT_ALIGN. Limit the length of + straight-line implementation with LARCH_MAX_MOVE_OPS_STRAIGHT + instead of LARCH_MAX_MOVE_BYTES_STRAIGHT. + (loongarch_block_move_straight): When there are left-over bytes, + half the mode size instead of falling back to byte mode at once. + (loongarch_block_move_loop): Limit the length of loop body with + LARCH_MAX_MOVE_OPS_PER_LOOP_ITER instead of + LARCH_MAX_MOVE_BYTES_PER_LOOP_ITER. + * config/loongarch/loongarch.md (cpymemsi): Pass the alignment + to loongarch_expand_block_move. + +gcc/testsuite/ChangeLog: + + PR target/109465 + * gcc.target/loongarch/pr109465-1.c: New test. + * gcc.target/loongarch/pr109465-2.c: New test. + * gcc.target/loongarch/pr109465-3.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/loongarch-protos.h | 2 +- + gcc/config/loongarch/loongarch.cc | 95 +++++++++++-------- + gcc/config/loongarch/loongarch.h | 10 +- + gcc/config/loongarch/loongarch.md | 3 +- + .../gcc.target/loongarch/pr109465-1.c | 9 ++ + .../gcc.target/loongarch/pr109465-2.c | 9 ++ + .../gcc.target/loongarch/pr109465-3.c | 12 +++ + 7 files changed, 91 insertions(+), 49 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/loongarch/pr109465-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/pr109465-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/pr109465-3.c + +diff --git a/gcc/config/loongarch/loongarch-protos.h b/gcc/config/loongarch/loongarch-protos.h +index 0a9b47722..3ac3b5e19 100644 +--- a/gcc/config/loongarch/loongarch-protos.h ++++ b/gcc/config/loongarch/loongarch-protos.h +@@ -95,7 +95,7 @@ extern void loongarch_expand_conditional_trap (rtx); + #endif + extern void loongarch_set_return_address (rtx, rtx); + extern bool loongarch_move_by_pieces_p (unsigned HOST_WIDE_INT, unsigned int); +-extern bool loongarch_expand_block_move (rtx, rtx, rtx); ++extern bool loongarch_expand_block_move (rtx, rtx, rtx, rtx); + extern bool loongarch_do_optimize_block_move_p (void); + + extern bool loongarch_expand_ext_as_unaligned_load (rtx, rtx, HOST_WIDE_INT, +diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc +index 233dddbac..d3c6f22ad 100644 +--- a/gcc/config/loongarch/loongarch.cc ++++ b/gcc/config/loongarch/loongarch.cc +@@ -4456,41 +4456,46 @@ loongarch_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED, + Assume that the areas do not overlap. */ + + static void +-loongarch_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length) ++loongarch_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length, ++ HOST_WIDE_INT delta) + { +- HOST_WIDE_INT offset, delta; +- unsigned HOST_WIDE_INT bits; ++ HOST_WIDE_INT offs, delta_cur; + int i; + machine_mode mode; + rtx *regs; + +- bits = MIN (BITS_PER_WORD, MIN (MEM_ALIGN (src), MEM_ALIGN (dest))); +- +- mode = int_mode_for_size (bits, 0).require (); +- delta = bits / BITS_PER_UNIT; ++ /* Calculate how many registers we'll need for the block move. ++ We'll emit length / delta move operations with delta as the size ++ first. Then we may still have length % delta bytes not copied. ++ We handle these remaining bytes by move operations with smaller ++ (halfed) sizes. For example, if length = 21 and delta = 8, we'll ++ emit two ld.d/st.d pairs, one ld.w/st.w pair, and one ld.b/st.b ++ pair. For each load/store pair we use a dedicated register to keep ++ the pipeline as populated as possible. */ ++ HOST_WIDE_INT num_reg = length / delta; ++ for (delta_cur = delta / 2; delta_cur != 0; delta_cur /= 2) ++ num_reg += !!(length & delta_cur); + + /* Allocate a buffer for the temporary registers. */ +- regs = XALLOCAVEC (rtx, length / delta); ++ regs = XALLOCAVEC (rtx, num_reg); + +- /* Load as many BITS-sized chunks as possible. Use a normal load if +- the source has enough alignment, otherwise use left/right pairs. */ +- for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++) ++ for (delta_cur = delta, i = 0, offs = 0; offs < length; delta_cur /= 2) + { +- regsi = gen_reg_rtx (mode); +- loongarch_emit_move (regsi, adjust_address (src, mode, offset)); +- } ++ mode = int_mode_for_size (delta_cur * BITS_PER_UNIT, 0).require (); + +- for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++) +- loongarch_emit_move (adjust_address (dest, mode, offset), regsi); ++ for (; offs + delta_cur <= length; offs += delta_cur, i++) ++ { ++ regsi = gen_reg_rtx (mode); ++ loongarch_emit_move (regsi, adjust_address (src, mode, offs)); ++ } ++ } + +- /* Mop up any left-over bytes. */ +- if (offset < length) ++ for (delta_cur = delta, i = 0, offs = 0; offs < length; delta_cur /= 2) + { +- src = adjust_address (src, BLKmode, offset); +- dest = adjust_address (dest, BLKmode, offset); +- move_by_pieces (dest, src, length - offset, +- MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), +- (enum memop_ret) 0); ++ mode = int_mode_for_size (delta_cur * BITS_PER_UNIT, 0).require (); ++ ++ for (; offs + delta_cur <= length; offs += delta_cur, i++) ++ loongarch_emit_move (adjust_address (dest, mode, offs), regsi); + } + } + +@@ -4520,10 +4525,11 @@ loongarch_adjust_block_mem (rtx mem, HOST_WIDE_INT length, rtx *loop_reg, + + static void + loongarch_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length, +- HOST_WIDE_INT bytes_per_iter) ++ HOST_WIDE_INT align) + { + rtx_code_label *label; + rtx src_reg, dest_reg, final_src, test; ++ HOST_WIDE_INT bytes_per_iter = align * LARCH_MAX_MOVE_OPS_PER_LOOP_ITER; + HOST_WIDE_INT leftover; + + leftover = length % bytes_per_iter; +@@ -4543,7 +4549,7 @@ loongarch_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length, + emit_label (label); + + /* Emit the loop body. */ +- loongarch_block_move_straight (dest, src, bytes_per_iter); ++ loongarch_block_move_straight (dest, src, bytes_per_iter, align); + + /* Move on to the next block. */ + loongarch_emit_move (src_reg, +@@ -4560,7 +4566,7 @@ loongarch_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length, + + /* Mop up any left-over bytes. */ + if (leftover) +- loongarch_block_move_straight (dest, src, leftover); ++ loongarch_block_move_straight (dest, src, leftover, align); + else + /* Temporary fix for PR79150. */ + emit_insn (gen_nop ()); +@@ -4570,25 +4576,32 @@ loongarch_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length, + memory reference SRC to memory reference DEST. */ + + bool +-loongarch_expand_block_move (rtx dest, rtx src, rtx length) ++loongarch_expand_block_move (rtx dest, rtx src, rtx r_length, rtx r_align) + { +- int max_move_bytes = LARCH_MAX_MOVE_BYTES_STRAIGHT; ++ if (!CONST_INT_P (r_length)) ++ return false; ++ ++ HOST_WIDE_INT length = INTVAL (r_length); ++ if (length > loongarch_max_inline_memcpy_size)
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_service:tar_scm:LoongArch-Libitm-add-LoongArch-support.patch
Added
@@ -0,0 +1,291 @@ +From 7f9f1dd3c87cffeab58150997e22e8fff707646b Mon Sep 17 00:00:00 2001 +From: Lulu Cheng <chenglulu@loongson.cn> +Date: Mon, 26 Sep 2022 09:42:51 +0800 +Subject: PATCH 019/124 LoongArch: Libitm add LoongArch support. + +Co-Authored-By: Yang Yujie <yangyujie@loongson.cn> + +libitm/ChangeLog: + + * configure.tgt: Add loongarch support. + * config/loongarch/asm.h: New file. + * config/loongarch/sjlj.S: New file. + * config/loongarch/target.h: New file. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + libitm/config/loongarch/asm.h | 54 +++++++++++++ + libitm/config/loongarch/sjlj.S | 127 +++++++++++++++++++++++++++++++ + libitm/config/loongarch/target.h | 50 ++++++++++++ + libitm/configure.tgt | 2 + + 4 files changed, 233 insertions(+) + create mode 100644 libitm/config/loongarch/asm.h + create mode 100644 libitm/config/loongarch/sjlj.S + create mode 100644 libitm/config/loongarch/target.h + +diff --git a/libitm/config/loongarch/asm.h b/libitm/config/loongarch/asm.h +new file mode 100644 +index 000000000..a8e3304bb +--- /dev/null ++++ b/libitm/config/loongarch/asm.h +@@ -0,0 +1,54 @@ ++/* Copyright (C) 2022 Free Software Foundation, Inc. ++ Contributed by Loongson Co. Ltd. ++ ++ This file is part of the GNU Transactional Memory Library (libitm). ++ ++ Libitm is free software; you can redistribute it and/or modify it ++ under the terms of the GNU General Public License as published by ++ the Free Software Foundation; either version 3 of the License, or ++ (at your option) any later version. ++ ++ Libitm is distributed in the hope that it will be useful, but WITHOUT ANY ++ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS ++ FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ Under Section 7 of GPL version 3, you are granted additional ++ permissions described in the GCC Runtime Library Exception, version ++ 3.1, as published by the Free Software Foundation. ++ ++ You should have received a copy of the GNU General Public License and ++ a copy of the GCC Runtime Library Exception along with this program; ++ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see ++ <http://www.gnu.org/licenses/>. */ ++ ++#ifndef _LA_ASM_H ++#define _LA_ASM_H ++ ++#if defined(__loongarch_lp64) ++# define GPR_L ld.d ++# define GPR_S st.d ++# define SZ_GPR 8 ++# define ADDSP(si) addi.d $sp, $sp, si ++#elif defined(__loongarch64_ilp32) ++# define GPR_L ld.w ++# define GPR_S st.w ++# define SZ_GPR 4 ++# define ADDSP(si) addi.w $sp, $sp, si ++#else ++# error Unsupported GPR size (must be 64-bit or 32-bit). ++#endif ++ ++#if defined(__loongarch_double_float) ++# define FPR_L fld.d ++# define FPR_S fst.d ++# define SZ_FPR 8 ++#elif defined(__loongarch_single_float) ++# define FPR_L fld.s ++# define FPR_S fst.s ++# define SZ_FPR 4 ++#else ++# define SZ_FPR 0 ++#endif ++ ++#endif /* _LA_ASM_H */ +diff --git a/libitm/config/loongarch/sjlj.S b/libitm/config/loongarch/sjlj.S +new file mode 100644 +index 000000000..a5f9fadde +--- /dev/null ++++ b/libitm/config/loongarch/sjlj.S +@@ -0,0 +1,127 @@ ++/* Copyright (C) 2022 Free Software Foundation, Inc. ++ Contributed by Loongson Co. Ltd. ++ ++ This file is part of the GNU Transactional Memory Library (libitm). ++ ++ Libitm is free software; you can redistribute it and/or modify it ++ under the terms of the GNU General Public License as published by ++ the Free Software Foundation; either version 3 of the License, or ++ (at your option) any later version. ++ ++ Libitm is distributed in the hope that it will be useful, but WITHOUT ANY ++ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS ++ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. ++ ++ Under Section 7 of GPL version 3, you are granted additional ++ permissions described in the GCC Runtime Library Exception, version ++ 3.1, as published by the Free Software Foundation. ++ ++ You should have received a copy of the GNU General Public License and ++ a copy of the GCC Runtime Library Exception along with this program; ++ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see ++ <http://www.gnu.org/licenses/>. */ ++ ++#include "asmcfi.h" ++#include "asm.h" ++ ++ .text ++ .align 2 ++ .global _ITM_beginTransaction ++ .type _ITM_beginTransaction, @function ++ ++_ITM_beginTransaction: ++ cfi_startproc ++ move $r5, $sp ++ ADDSP(-(12*SZ_GPR+8*SZ_FPR)) ++ cfi_adjust_cfa_offset(12*SZ_GPR+8*SZ_FPR) ++ ++ /* Frame Pointer */ ++ GPR_S $fp, $sp, 0*SZ_GPR ++ cfi_rel_offset(22, 0) ++ ++ /* Return Address */ ++ GPR_S $r1, $sp, 1*SZ_GPR ++ cfi_rel_offset(1, SZ_GPR) ++ ++ /* Caller's $sp */ ++ GPR_S $r5, $sp, 2*SZ_GPR ++ ++ /* Callee-saved scratch GPRs (r23-r31) */ ++ GPR_S $s0, $sp, 3*SZ_GPR ++ GPR_S $s1, $sp, 4*SZ_GPR ++ GPR_S $s2, $sp, 5*SZ_GPR ++ GPR_S $s3, $sp, 6*SZ_GPR ++ GPR_S $s4, $sp, 7*SZ_GPR ++ GPR_S $s5, $sp, 8*SZ_GPR ++ GPR_S $s6, $sp, 9*SZ_GPR ++ GPR_S $s7, $sp, 10*SZ_GPR ++ GPR_S $s8, $sp, 11*SZ_GPR ++ ++#if !defined(__loongarch_soft_float) ++ /* Callee-saved scratch FPRs (f24-f31) */ ++ FPR_S $f24, $sp, 12*SZ_GPR + 0*SZ_FPR ++ FPR_S $f25, $sp, 12*SZ_GPR + 1*SZ_FPR ++ FPR_S $f26, $sp, 12*SZ_GPR + 2*SZ_FPR ++ FPR_S $f27, $sp, 12*SZ_GPR + 3*SZ_FPR ++ FPR_S $f28, $sp, 12*SZ_GPR + 4*SZ_FPR ++ FPR_S $f29, $sp, 12*SZ_GPR + 5*SZ_FPR ++ FPR_S $f30, $sp, 12*SZ_GPR + 6*SZ_FPR ++ FPR_S $f31, $sp, 12*SZ_GPR + 7*SZ_FPR ++#endif ++ move $fp, $sp ++ ++ /* Invoke GTM_begin_transaction with the struct we've just built. */ ++ move $r5, $sp ++ bl %plt(GTM_begin_transaction) ++ ++ /* Return. (no call-saved scratch reg needs to be restored here) */ ++ GPR_L $fp, $sp, 0*SZ_GPR ++ cfi_restore(22) ++ GPR_L $r1, $sp, 1*SZ_GPR ++ cfi_restore(1) ++ ++ ADDSP(12*SZ_GPR+8*SZ_FPR) ++ cfi_adjust_cfa_offset(-(12*SZ_GPR+8*SZ_FPR)) ++ ++ jr $r1 ++ cfi_endproc ++ .size _ITM_beginTransaction, . - _ITM_beginTransaction ++ ++ .align 2 ++ .global GTM_longjmp ++ .hidden GTM_longjmp ++ .type GTM_longjmp, @function ++ ++GTM_longjmp: ++ cfi_startproc ++ GPR_L $s0, $r5, 3*SZ_GPR ++ GPR_L $s1, $r5, 4*SZ_GPR ++ GPR_L $s2, $r5, 5*SZ_GPR ++ GPR_L $s3, $r5, 6*SZ_GPR ++ GPR_L $s4, $r5, 7*SZ_GPR ++ GPR_L $s5, $r5, 8*SZ_GPR ++ GPR_L $s6, $r5, 9*SZ_GPR ++ GPR_L $s7, $r5, 10*SZ_GPR ++ GPR_L $s8, $r5, 11*SZ_GPR ++ ++ FPR_L $f24, $r5, 12*SZ_GPR + 0*SZ_FPR
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_service:tar_scm:LoongArch-Modify-the-output-message-string-of-the-wa.patch
Added
@@ -0,0 +1,37 @@ +From 83d6cfbbdc41766af9d7941d00204cc0f26ff40c Mon Sep 17 00:00:00 2001 +From: Lulu Cheng <chenglulu@loongson.cn> +Date: Tue, 26 Jul 2022 21:03:52 +0800 +Subject: PATCH 005/124 LoongArch: Modify the output message string of the + warning. + +Fix bug for "error: spurious trailing punctuation sequence '.' in format -Werror=format-diag". + +gcc/ChangeLog: + + * config/loongarch/loongarch-opts.cc: Modify the output message string + of the warning. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/loongarch-opts.cc | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/gcc/config/loongarch/loongarch-opts.cc b/gcc/config/loongarch/loongarch-opts.cc +index fc477bfd4..3f70943de 100644 +--- a/gcc/config/loongarch/loongarch-opts.cc ++++ b/gcc/config/loongarch/loongarch-opts.cc +@@ -378,8 +378,8 @@ fallback: + t.cmodel = constrained.cmodel ? opt_cmodel : CMODEL_NORMAL; + if (t.cmodel != CMODEL_NORMAL) + { +- warning (0, "%qs is not supported, now cmodel is set to 'normal'.", +- loongarch_cmodel_stringst.cmodel); ++ warning (0, "%qs is not supported, now cmodel is set to %qs", ++ loongarch_cmodel_stringst.cmodel, "normal"); + t.cmodel = CMODEL_NORMAL; + } + +-- +2.33.0 +
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_service:tar_scm:LoongArch-Optimize-additions-with-immediates.patch
Added
@@ -0,0 +1,445 @@ +From a31baa1e437fa4acedfaf03db91c1d6e5ce78013 Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao <xry111@xry111.site> +Date: Sun, 2 Apr 2023 21:37:49 +0800 +Subject: PATCH 041/124 LoongArch: Optimize additions with immediates + +1. Use addu16i.d for TARGET_64BIT and suitable immediates. +2. Split one addition with immediate into two addu16i.d or addi.{d/w} + instructions if possible. This can avoid using a temp register w/o + increase the count of instructions. + +Inspired by https://reviews.llvm.org/D143710 and +https://reviews.llvm.org/D147222. + +Bootstrapped and regtested on loongarch64-linux-gnu. Ok for GCC 14? + +gcc/ChangeLog: + + * config/loongarch/loongarch-protos.h + (loongarch_addu16i_imm12_operand_p): New function prototype. + (loongarch_split_plus_constant): Likewise. + * config/loongarch/loongarch.cc + (loongarch_addu16i_imm12_operand_p): New function. + (loongarch_split_plus_constant): Likewise. + * config/loongarch/loongarch.h (ADDU16I_OPERAND): New macro. + (DUAL_IMM12_OPERAND): Likewise. + (DUAL_ADDU16I_OPERAND): Likewise. + * config/loongarch/constraints.md (La, Lb, Lc, Ld, Le): New + constraint. + * config/loongarch/predicates.md (const_dual_imm12_operand): New + predicate. + (const_addu16i_operand): Likewise. + (const_addu16i_imm12_di_operand): Likewise. + (const_addu16i_imm12_si_operand): Likewise. + (plus_di_operand): Likewise. + (plus_si_operand): Likewise. + (plus_si_extend_operand): Likewise. + * config/loongarch/loongarch.md (add<mode>3): Convert to + define_insn_and_split. Use plus_<mode>_operand predicate + instead of arith_operand. Add alternatives for La, Lb, Lc, Ld, + and Le constraints. + (*addsi3_extended): Convert to define_insn_and_split. Use + plus_si_extend_operand instead of arith_operand. Add + alternatives for La and Le alternatives. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/add-const.c: New test. + * gcc.target/loongarch/stack-check-cfa-1.c: Adjust for stack + frame size change. + * gcc.target/loongarch/stack-check-cfa-2.c: Likewise. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/constraints.md | 46 ++++++++++++- + gcc/config/loongarch/loongarch-protos.h | 2 + + gcc/config/loongarch/loongarch.cc | 44 +++++++++++++ + gcc/config/loongarch/loongarch.h | 19 ++++++ + gcc/config/loongarch/loongarch.md | 66 +++++++++++++++---- + gcc/config/loongarch/predicates.md | 36 ++++++++++ + .../gcc.target/loongarch/add-const.c | 45 +++++++++++++ + .../gcc.target/loongarch/stack-check-cfa-1.c | 2 +- + .../gcc.target/loongarch/stack-check-cfa-2.c | 2 +- + 9 files changed, 246 insertions(+), 16 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/loongarch/add-const.c + +diff --git a/gcc/config/loongarch/constraints.md b/gcc/config/loongarch/constraints.md +index 46f7f63ae..25f3cda35 100644 +--- a/gcc/config/loongarch/constraints.md ++++ b/gcc/config/loongarch/constraints.md +@@ -60,7 +60,22 @@ + ;; "I" "A signed 12-bit constant (for arithmetic instructions)." + ;; "J" "Integer zero." + ;; "K" "An unsigned 12-bit constant (for logic instructions)." +-;; "L" <-----unused ++;; "L" - ++;; "La" ++;; "A signed constant in -4096, 2048) or (2047, 4094." ++;; "Lb" ++;; "A signed 32-bit constant and low 16-bit is zero, which can be ++;; added onto a register with addu16i.d. It matches nothing if ++;; the addu16i.d instruction is not available." ++;; "Lc" ++;; "A signed 64-bit constant can be expressed as Lb + I, but not a ++;; single Lb or I." ++;; "Ld" ++;; "A signed 64-bit constant can be expressed as Lb + Lb, but not a ++;; single Lb." ++;; "Le" ++;; "A signed 32-bit constant can be expressed as Lb + I, but not a ++;; single Lb or I." + ;; "M" <-----unused + ;; "N" <-----unused + ;; "O" <-----unused +@@ -170,6 +185,35 @@ + (and (match_code "const_int") + (match_test "IMM12_OPERAND_UNSIGNED (ival)"))) + ++(define_constraint "La" ++ "A signed constant in -4096, 2048) or (2047, 4094." ++ (and (match_code "const_int") ++ (match_test "DUAL_IMM12_OPERAND (ival)"))) ++ ++(define_constraint "Lb" ++ "A signed 32-bit constant and low 16-bit is zero, which can be added ++ onto a register with addu16i.d." ++ (and (match_code "const_int") ++ (match_test "ADDU16I_OPERAND (ival)"))) ++ ++(define_constraint "Lc" ++ "A signed 64-bit constant can be expressed as Lb + I, but not a single Lb ++ or I." ++ (and (match_code "const_int") ++ (match_test "loongarch_addu16i_imm12_operand_p (ival, DImode)"))) ++ ++(define_constraint "Ld" ++ "A signed 64-bit constant can be expressed as Lb + Lb, but not a single ++ Lb." ++ (and (match_code "const_int") ++ (match_test "DUAL_ADDU16I_OPERAND (ival)"))) ++ ++(define_constraint "Le" ++ "A signed 32-bit constant can be expressed as Lb + I, but not a single Lb ++ or I." ++ (and (match_code "const_int") ++ (match_test "loongarch_addu16i_imm12_operand_p (ival, SImode)"))) ++ + (define_constraint "Yd" + "@internal + A constant @code{move_operand} that can be safely loaded using +diff --git a/gcc/config/loongarch/loongarch-protos.h b/gcc/config/loongarch/loongarch-protos.h +index 77b221724..0a9b47722 100644 +--- a/gcc/config/loongarch/loongarch-protos.h ++++ b/gcc/config/loongarch/loongarch-protos.h +@@ -83,6 +83,8 @@ extern rtx loongarch_legitimize_call_address (rtx); + extern rtx loongarch_subword (rtx, bool); + extern bool loongarch_split_move_p (rtx, rtx); + extern void loongarch_split_move (rtx, rtx, rtx); ++extern bool loongarch_addu16i_imm12_operand_p (HOST_WIDE_INT, machine_mode); ++extern void loongarch_split_plus_constant (rtx *, machine_mode); + extern const char *loongarch_output_move (rtx, rtx); + extern bool loongarch_cfun_has_cprestore_slot_p (void); + #ifdef RTX_CODE +diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc +index 1a4686f03..233dddbac 100644 +--- a/gcc/config/loongarch/loongarch.cc ++++ b/gcc/config/loongarch/loongarch.cc +@@ -3753,6 +3753,50 @@ loongarch_split_move (rtx dest, rtx src, rtx insn_) + } + } + ++/* Check if adding an integer constant value for a specific mode can be ++ performed with an addu16i.d instruction and an addi.{w/d} ++ instruction. */ ++ ++bool ++loongarch_addu16i_imm12_operand_p (HOST_WIDE_INT value, machine_mode mode) ++{ ++ /* Not necessary, but avoid unnecessary calculation if !TARGET_64BIT. */ ++ if (!TARGET_64BIT) ++ return false; ++ ++ if ((value & 0xffff) == 0) ++ return false; ++ ++ if (IMM12_OPERAND (value)) ++ return false; ++ ++ value = (value & ~HWIT_UC_0xFFF) + ((value & 0x800) << 1); ++ return ADDU16I_OPERAND (trunc_int_for_mode (value, mode)); ++} ++ ++/* Split one integer constant op0 into two (op1 and op2) for constant ++ plus operation in a specific mode. The splitted constants can be added ++ onto a register with a single instruction (addi.{d/w} or addu16i.d). */ ++ ++void ++loongarch_split_plus_constant (rtx *op, machine_mode mode) ++{ ++ HOST_WIDE_INT v = INTVAL (op0), a; ++ ++ if (DUAL_IMM12_OPERAND (v)) ++ a = (v > 0 ? 2047 : -2048); ++ else if (loongarch_addu16i_imm12_operand_p (v, mode)) ++ a = (v & ~HWIT_UC_0xFFF) + ((v & 0x800) << 1); ++ else if (mode == DImode && DUAL_ADDU16I_OPERAND (v)) ++ a = (v > 0 ? 0x7fff : -0x8000) << 16; ++ else ++ gcc_unreachable (); ++ ++ op1 = gen_int_mode (a, mode); ++ v = v - (unsigned HOST_WIDE_INT) a; ++ op2 = gen_int_mode (v, mode); ++} ++ + /* Return true if a move from SRC to DEST in INSN should be split. */ + + static bool +diff --git a/gcc/config/loongarch/loongarch.h b/gcc/config/loongarch/loongarch.h
View file
_service:tar_scm:LoongArch-Optimize-immediate-load.patch
Added
@@ -0,0 +1,338 @@ +From b533b615ae47b97d51eeb83e1a63f7c72407430f Mon Sep 17 00:00:00 2001 +From: Lulu Cheng <chenglulu@loongson.cn> +Date: Thu, 17 Nov 2022 17:08:36 +0800 +Subject: PATCH 032/124 LoongArch: Optimize immediate load. + +The immediate number is split in the Split pass, not in the expand pass. + +Because loop2_invariant pass will extract the instructions that do not change +in the loop out of the loop, some instructions will not meet the extraction +conditions if the machine performs immediate decomposition while expand pass, +so the immediate decomposition will be transferred to the split process. + +gcc/ChangeLog: + + * config/loongarch/loongarch.cc (enum loongarch_load_imm_method): + Remove the member METHOD_INSV that is not currently used. + (struct loongarch_integer_op): Define a new member curr_value, + that records the value of the number stored in the destination + register immediately after the current instruction has run. + (loongarch_build_integer): Assign a value to the curr_value member variable. + (loongarch_move_integer): Adds information for the immediate load instruction. + * config/loongarch/loongarch.md (*movdi_32bit): Redefine as define_insn_and_split. + (*movdi_64bit): Likewise. + (*movsi_internal): Likewise. + (*movhi_internal): Likewise. + * config/loongarch/predicates.md: Return true as long as it is CONST_INT, ensure + that the immediate number is not optimized by decomposition during expand + optimization loop. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/imm-load.c: New test. + * gcc.target/loongarch/imm-load1.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/loongarch.cc | 62 ++++++++++--------- + gcc/config/loongarch/loongarch.md | 44 +++++++++++-- + gcc/config/loongarch/predicates.md | 2 +- + gcc/testsuite/gcc.target/loongarch/imm-load.c | 10 +++ + .../gcc.target/loongarch/imm-load1.c | 26 ++++++++ + 5 files changed, 110 insertions(+), 34 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/loongarch/imm-load.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/imm-load1.c + +diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc +index 622c9435b..f45a49f90 100644 +--- a/gcc/config/loongarch/loongarch.cc ++++ b/gcc/config/loongarch/loongarch.cc +@@ -139,22 +139,21 @@ struct loongarch_address_info + + METHOD_LU52I: + Load 52-63 bit of the immediate number. +- +- METHOD_INSV: +- immediate like 0xfff00000fffffxxx +- */ ++*/ + enum loongarch_load_imm_method + { + METHOD_NORMAL, + METHOD_LU32I, +- METHOD_LU52I, +- METHOD_INSV ++ METHOD_LU52I + }; + + struct loongarch_integer_op + { + enum rtx_code code; + HOST_WIDE_INT value; ++ /* Represent the result of the immediate count of the load instruction at ++ each step. */ ++ HOST_WIDE_INT curr_value; + enum loongarch_load_imm_method method; + }; + +@@ -1474,24 +1473,27 @@ loongarch_build_integer (struct loongarch_integer_op *codes, + { + /* The value of the lower 32 bit be loaded with one instruction. + lu12i.w. */ +- codes0.code = UNKNOWN; +- codes0.method = METHOD_NORMAL; +- codes0.value = low_part; ++ codescost.code = UNKNOWN; ++ codescost.method = METHOD_NORMAL; ++ codescost.value = low_part; ++ codescost.curr_value = low_part; + cost++; + } + else + { + /* lu12i.w + ior. */ +- codes0.code = UNKNOWN; +- codes0.method = METHOD_NORMAL; +- codes0.value = low_part & ~(IMM_REACH - 1); ++ codescost.code = UNKNOWN; ++ codescost.method = METHOD_NORMAL; ++ codescost.value = low_part & ~(IMM_REACH - 1); ++ codescost.curr_value = codescost.value; + cost++; + HOST_WIDE_INT iorv = low_part & (IMM_REACH - 1); + if (iorv != 0) + { +- codes1.code = IOR; +- codes1.method = METHOD_NORMAL; +- codes1.value = iorv; ++ codescost.code = IOR; ++ codescost.method = METHOD_NORMAL; ++ codescost.value = iorv; ++ codescost.curr_value = low_part; + cost++; + } + } +@@ -1514,11 +1516,14 @@ loongarch_build_integer (struct loongarch_integer_op *codes, + { + codescost.method = METHOD_LU52I; + codescost.value = value & LU52I_B; ++ codescost.curr_value = value; + return cost + 1; + } + + codescost.method = METHOD_LU32I; + codescost.value = (value & LU32I_B) | (sign51 ? LU52I_B : 0); ++ codescost.curr_value = (value & 0xfffffffffffff) ++ | (sign51 ? LU52I_B : 0); + cost++; + + /* Determine whether the 52-61 bits are sign-extended from the low order, +@@ -1527,6 +1532,7 @@ loongarch_build_integer (struct loongarch_integer_op *codes, + { + codescost.method = METHOD_LU52I; + codescost.value = value & LU52I_B; ++ codescost.curr_value = value; + cost++; + } + } +@@ -2910,6 +2916,9 @@ loongarch_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value) + else + x = force_reg (mode, x); + ++ set_unique_reg_note (get_last_insn (), REG_EQUAL, ++ GEN_INT (codesi-1.curr_value)); ++ + switch (codesi.method) + { + case METHOD_NORMAL: +@@ -2917,22 +2926,17 @@ loongarch_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value) + GEN_INT (codesi.value)); + break; + case METHOD_LU32I: +- emit_insn ( +- gen_rtx_SET (x, +- gen_rtx_IOR (DImode, +- gen_rtx_ZERO_EXTEND ( +- DImode, gen_rtx_SUBREG (SImode, x, 0)), +- GEN_INT (codesi.value)))); ++ gcc_assert (mode == DImode); ++ x = gen_rtx_IOR (DImode, ++ gen_rtx_ZERO_EXTEND (DImode, ++ gen_rtx_SUBREG (SImode, x, 0)), ++ GEN_INT (codesi.value)); + break; + case METHOD_LU52I: +- emit_insn (gen_lu52i_d (x, x, GEN_INT (0xfffffffffffff), +- GEN_INT (codesi.value))); +- break; +- case METHOD_INSV: +- emit_insn ( +- gen_rtx_SET (gen_rtx_ZERO_EXTRACT (DImode, x, GEN_INT (20), +- GEN_INT (32)), +- gen_rtx_REG (DImode, 0))); ++ gcc_assert (mode == DImode); ++ x = gen_rtx_IOR (DImode, ++ gen_rtx_AND (DImode, x, GEN_INT (0xfffffffffffff)), ++ GEN_INT (codesi.value)); + break; + default: + gcc_unreachable (); +diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md +index 2fda53819..f61db66d5 100644 +--- a/gcc/config/loongarch/loongarch.md ++++ b/gcc/config/loongarch/loongarch.md +@@ -1718,23 +1718,41 @@ + DONE; + }) + +-(define_insn "*movdi_32bit" ++(define_insn_and_split "*movdi_32bit" + (set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,w,*f,*f,*r,*m") + (match_operand:DI 1 "move_operand" "r,i,w,r,*J*r,*m,*f,*f")) + "!TARGET_64BIT + && (register_operand (operands0, DImode) + || reg_or_0_operand (operands1, DImode))" + { return loongarch_output_move (operands0, operands1); } ++ "CONST_INT_P (operands1) && REG_P (operands0) && GP_REG_P (REGNO ++ (operands0))" ++ (const_int 0)
View file
_service:tar_scm:LoongArch-Optimize-switch-with-sign-extended-index.patch
Added
@@ -0,0 +1,114 @@ +From c6d4efda0fa064dfe1d3cc1b9abf8051a82cd74f Mon Sep 17 00:00:00 2001 +From: Lulu Cheng <chenglulu@loongson.cn> +Date: Sat, 2 Sep 2023 10:59:55 +0800 +Subject: PATCH 056/124 LoongArch: Optimize switch with sign-extended index. + +The patch refers to the submission of RISCV +7bbce9b50302959286381d9177818642bceaf301. + +gcc/ChangeLog: + + * config/loongarch/loongarch.cc (loongarch_extend_comparands): + In unsigned QImode test, check for sign extended subreg and/or + constant operands, and do a sign extension in that case. + * config/loongarch/loongarch.md (TARGET_64BIT): Define + template cbranchqi4. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/switch-qi.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/loongarch.cc | 16 +++++++++++++--- + gcc/config/loongarch/loongarch.md | 10 +++++++--- + gcc/testsuite/gcc.target/loongarch/switch-qi.c | 16 ++++++++++++++++ + 3 files changed, 36 insertions(+), 6 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/loongarch/switch-qi.c + +diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc +index 7b48e3216..41d344b82 100644 +--- a/gcc/config/loongarch/loongarch.cc ++++ b/gcc/config/loongarch/loongarch.cc +@@ -4221,11 +4221,21 @@ loongarch_allocate_fcc (machine_mode mode) + static void + loongarch_extend_comparands (rtx_code code, rtx *op0, rtx *op1) + { +- /* Comparisons consider all XLEN bits, so extend sub-XLEN values. */ ++ /* Comparisons consider all GRLEN bits, so extend sub-GRLEN values. */ + if (GET_MODE_SIZE (word_mode) > GET_MODE_SIZE (GET_MODE (*op0))) + { +- /* TODO: checkout It is more profitable to zero-extend QImode values. */ +- if (unsigned_condition (code) == code && GET_MODE (*op0) == QImode) ++ /* It is more profitable to zero-extend QImode values. But not if the ++ first operand has already been sign-extended, and the second one is ++ is a constant or has already been sign-extended also. */ ++ if (unsigned_condition (code) == code ++ && (GET_MODE (*op0) == QImode ++ && ! (GET_CODE (*op0) == SUBREG ++ && SUBREG_PROMOTED_VAR_P (*op0) ++ && SUBREG_PROMOTED_SIGNED_P (*op0) ++ && (CONST_INT_P (*op1) ++ || (GET_CODE (*op1) == SUBREG ++ && SUBREG_PROMOTED_VAR_P (*op1) ++ && SUBREG_PROMOTED_SIGNED_P (*op1)))))) + { + *op0 = gen_rtx_ZERO_EXTEND (word_mode, *op0); + if (CONST_INT_P (*op1)) +diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md +index cf7441e0b..a5e9352ca 100644 +--- a/gcc/config/loongarch/loongarch.md ++++ b/gcc/config/loongarch/loongarch.md +@@ -357,7 +357,7 @@ + ;; pointer-sized quantities. Exactly one of the two alternatives will match. + (define_mode_iterator P (SI "Pmode == SImode") (DI "Pmode == DImode")) + +-;; Likewise, but for XLEN-sized quantities. ++;; Likewise, but for GRLEN-sized quantities. + (define_mode_iterator X (SI "!TARGET_64BIT") (DI "TARGET_64BIT")) + + ;; 64-bit modes for which we provide move patterns. +@@ -2733,11 +2733,15 @@ + (set_attr "type" "branch")) + + ++;; Branches operate on GRLEN-sized quantities, but for LoongArch64 we accept ++;; QImode values so we can force zero-extension. ++(define_mode_iterator BR (QI "TARGET_64BIT") SI (DI "TARGET_64BIT")) ++ + (define_expand "cbranch<mode>4" + (set (pc) + (if_then_else (match_operator 0 "comparison_operator" +- (match_operand:GPR 1 "register_operand") +- (match_operand:GPR 2 "nonmemory_operand")) ++ (match_operand:BR 1 "register_operand") ++ (match_operand:BR 2 "nonmemory_operand")) + (label_ref (match_operand 3 "")) + (pc))) + "" +diff --git a/gcc/testsuite/gcc.target/loongarch/switch-qi.c b/gcc/testsuite/gcc.target/loongarch/switch-qi.c +new file mode 100644 +index 000000000..dd192fd49 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/switch-qi.c +@@ -0,0 +1,16 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=loongarch64 -mabi=lp64d" } */ ++/* { dg-final { scan-assembler-not "bstrpick" } } */ ++ ++/* Test for loongarch_extend_comparands patch. */ ++extern void asdf (int); ++void ++foo (signed char x) { ++ switch (x) { ++ case 0: asdf (10); break; ++ case 1: asdf (11); break; ++ case 2: asdf (12); break; ++ case 3: asdf (13); break; ++ case 4: asdf (14); break; ++ } ++} +-- +2.33.0 +
View file
_service:tar_scm:LoongArch-Optimize-the-implementation-of-stack-check.patch
Added
@@ -0,0 +1,810 @@ +From d3615b555d6885dba298f7b339740be11cb65a8f Mon Sep 17 00:00:00 2001 +From: Lulu Cheng <chenglulu@loongson.cn> +Date: Tue, 29 Nov 2022 16:06:12 +0800 +Subject: PATCH 033/124 LoongArch: Optimize the implementation of stack + check. + +The old stack check was performed before the stack was dropped, +which would cause the detection tool to report a memory leak. + +The current stack check scheme is as follows: + +'-fstack-clash-protection': +1. When the frame->total_size is smaller than the guard page size, + the stack is dropped according to the original scheme, and there + is no need to perform stack detection in the prologue. +2. When frame->total_size is greater than or equal to guard page size, + the first step to drop the stack is to drop the space required by + the caller-save registers. This space needs to save the caller-save + registers, so an implicit stack check is performed. + So just need to check the rest of the stack space. + +'-fstack-check': +There is no one-time stack drop and then page-by-page detection as +described in the document. It is also the same as +'-fstack-clash-protection', which is detected immediately after page drop. + +It is judged that when frame->total_size is not 0, only the size required +to save the s register is dropped for the first stack down. + +The test cases are referenced from aarch64. + +gcc/ChangeLog: + + * config/loongarch/linux.h (STACK_CHECK_MOVING_SP): + Define this macro to 1. + * config/loongarch/loongarch.cc (STACK_CLASH_PROTECTION_GUARD_SIZE): + Size of guard page. + (loongarch_first_stack_step): Return the size of the first drop stack + according to whether stack checking is performed. + (loongarch_emit_probe_stack_range): Adjust the method of stack checking in prologue. + (loongarch_output_probe_stack_range): Delete useless code. + (loongarch_expand_prologue): Adjust the method of stack checking in prologue. + (loongarch_option_override_internal): Enforce that interval is the same + size as size so the mid-end does the right thing. + * config/loongarch/loongarch.h (STACK_CLASH_MAX_UNROLL_PAGES): + New macro decide whether to loop stack detection. + +gcc/testsuite/ChangeLog: + + * lib/target-supports.exp: + * gcc.target/loongarch/stack-check-alloca-1.c: New test. + * gcc.target/loongarch/stack-check-alloca-2.c: New test. + * gcc.target/loongarch/stack-check-alloca-3.c: New test. + * gcc.target/loongarch/stack-check-alloca-4.c: New test. + * gcc.target/loongarch/stack-check-alloca-5.c: New test. + * gcc.target/loongarch/stack-check-alloca-6.c: New test. + * gcc.target/loongarch/stack-check-alloca.h: New test. + * gcc.target/loongarch/stack-check-cfa-1.c: New test. + * gcc.target/loongarch/stack-check-cfa-2.c: New test. + * gcc.target/loongarch/stack-check-prologue-1.c: New test. + * gcc.target/loongarch/stack-check-prologue-2.c: New test. + * gcc.target/loongarch/stack-check-prologue-3.c: New test. + * gcc.target/loongarch/stack-check-prologue-4.c: New test. + * gcc.target/loongarch/stack-check-prologue-5.c: New test. + * gcc.target/loongarch/stack-check-prologue-6.c: New test. + * gcc.target/loongarch/stack-check-prologue-7.c: New test. + * gcc.target/loongarch/stack-check-prologue.h: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/linux.h | 3 + + gcc/config/loongarch/loongarch.cc | 248 +++++++++++------- + gcc/config/loongarch/loongarch.h | 4 + + .../loongarch/stack-check-alloca-1.c | 15 ++ + .../loongarch/stack-check-alloca-2.c | 12 + + .../loongarch/stack-check-alloca-3.c | 12 + + .../loongarch/stack-check-alloca-4.c | 12 + + .../loongarch/stack-check-alloca-5.c | 13 + + .../loongarch/stack-check-alloca-6.c | 13 + + .../gcc.target/loongarch/stack-check-alloca.h | 15 ++ + .../gcc.target/loongarch/stack-check-cfa-1.c | 12 + + .../gcc.target/loongarch/stack-check-cfa-2.c | 12 + + .../loongarch/stack-check-prologue-1.c | 11 + + .../loongarch/stack-check-prologue-2.c | 11 + + .../loongarch/stack-check-prologue-3.c | 11 + + .../loongarch/stack-check-prologue-4.c | 11 + + .../loongarch/stack-check-prologue-5.c | 12 + + .../loongarch/stack-check-prologue-6.c | 11 + + .../loongarch/stack-check-prologue-7.c | 12 + + .../loongarch/stack-check-prologue.h | 5 + + gcc/testsuite/lib/target-supports.exp | 7 +- + 21 files changed, 361 insertions(+), 101 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/loongarch/stack-check-alloca-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/stack-check-alloca-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/stack-check-alloca-3.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/stack-check-alloca-4.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/stack-check-alloca-5.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/stack-check-alloca-6.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/stack-check-alloca.h + create mode 100644 gcc/testsuite/gcc.target/loongarch/stack-check-cfa-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/stack-check-cfa-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/stack-check-prologue-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/stack-check-prologue-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/stack-check-prologue-3.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/stack-check-prologue-4.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/stack-check-prologue-5.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/stack-check-prologue-6.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/stack-check-prologue-7.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/stack-check-prologue.h + +diff --git a/gcc/config/loongarch/linux.h b/gcc/config/loongarch/linux.h +index 110d0fab9..00039ac18 100644 +--- a/gcc/config/loongarch/linux.h ++++ b/gcc/config/loongarch/linux.h +@@ -48,3 +48,6 @@ along with GCC; see the file COPYING3. If not see + #define STACK_CHECK_PROTECT (TARGET_64BIT ? 16 * 1024 : 12 * 1024) + + #define TARGET_ASM_FILE_END file_end_indicate_exec_stack ++ ++/* The stack pointer needs to be moved while checking the stack. */ ++#define STACK_CHECK_MOVING_SP 1 +diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc +index f45a49f90..e59edc4cd 100644 +--- a/gcc/config/loongarch/loongarch.cc ++++ b/gcc/config/loongarch/loongarch.cc +@@ -257,6 +257,10 @@ const char *const + loongarch_fp_conditions16= {LARCH_FP_CONDITIONS (STRINGIFY)}; + #undef STRINGIFY + ++/* Size of guard page. */ ++#define STACK_CLASH_PROTECTION_GUARD_SIZE \ ++ (1 << param_stack_clash_protection_guard_size) ++ + /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at + least PARM_BOUNDARY bits of alignment, but will be given anything up + to PREFERRED_STACK_BOUNDARY bits if the type requires it. */ +@@ -1069,11 +1073,20 @@ loongarch_restore_reg (rtx reg, rtx mem) + static HOST_WIDE_INT + loongarch_first_stack_step (struct loongarch_frame_info *frame) + { ++ HOST_WIDE_INT min_first_step ++ = LARCH_STACK_ALIGN (frame->total_size - frame->fp_sp_offset); ++ ++ /* When stack checking is required, if the sum of frame->total_size ++ and stack_check_protect is greater than stack clash protection guard ++ size, then return min_first_step. */ ++ if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK ++ || (flag_stack_clash_protection ++ && frame->total_size > STACK_CLASH_PROTECTION_GUARD_SIZE)) ++ return min_first_step; ++ + if (IMM12_OPERAND (frame->total_size)) + return frame->total_size; + +- HOST_WIDE_INT min_first_step +- = LARCH_STACK_ALIGN (frame->total_size - frame->fp_sp_offset); + HOST_WIDE_INT max_first_step = IMM_REACH / 2 - PREFERRED_STACK_BOUNDARY / 8; + HOST_WIDE_INT min_second_step = frame->total_size - max_first_step; + gcc_assert (min_first_step <= max_first_step); +@@ -1106,103 +1119,109 @@ loongarch_emit_stack_tie (void) + static void + loongarch_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size) + { +- /* See if we have a constant small number of probes to generate. If so, +- that's the easy case. */ +- if ((TARGET_64BIT && (first + size <= 32768)) +- || (!TARGET_64BIT && (first + size <= 2048))) +- { +- HOST_WIDE_INT i; ++ HOST_WIDE_INT rounded_size; ++ HOST_WIDE_INT interval; + +- /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until +- it exceeds SIZE. If only one probe is needed, this will not +- generate any code. Then probe at FIRST + SIZE. */ +- for (i = PROBE_INTERVAL; i < size; i += PROBE_INTERVAL) +- emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx, +- -(first + i))); ++ if (flag_stack_clash_protection) ++ interval = STACK_CLASH_PROTECTION_GUARD_SIZE; ++ else ++ interval = PROBE_INTERVAL; + +- emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx, +- -(first + size))); +- } ++ rtx r12 = LARCH_PROLOGUE_TEMP2 (Pmode); ++ rtx r14 = LARCH_PROLOGUE_TEMP3 (Pmode); + +- /* Otherwise, do the same as above, but in a loop. Note that we must be +- extra careful with variables wrapping around because we might be at +- the very top (or the very bottom) of the address space and we have +- to be able to handle this case properly; in particular, we use an +- equality test for the loop condition. */ +- else +- { +- HOST_WIDE_INT rounded_size; +- rtx r13 = LARCH_PROLOGUE_TEMP (Pmode);
View file
_service:tar_scm:LoongArch-Optimized-multiply-instruction-generation.patch
Added
@@ -0,0 +1,232 @@ +From aa1dc79c9a5ff3df241a94cbfb1c857cfa89c686 Mon Sep 17 00:00:00 2001 +From: Lulu Cheng <chenglulu@loongson.cn> +Date: Tue, 5 Sep 2023 11:09:03 +0800 +Subject: PATCH 074/124 LoongArch: Optimized multiply instruction generation. + + 1. Can generate mulh.wu instruction. + 2. Can generate mulw.d.wu instruction. + +gcc/ChangeLog: + + * config/loongarch/loongarch.md (mulsidi3_64bit): + Field unsigned extension support. + (<u>muldi3_highpart): Modify template name. + (<u>mulsi3_highpart): Likewise. + (<u>mulsidi3_64bit): Field unsigned extension support. + (<su>muldi3_highpart): Modify muldi3_highpart to + smuldi3_highpart. + (<su>mulsi3_highpart): Modify mulsi3_highpart to + smulsi3_highpart. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/mulw_d_wu.c: New test. + * gcc.target/loongarch/smuldi3_highpart.c: New test. + * gcc.target/loongarch/smulsi3_highpart.c: New test. + * gcc.target/loongarch/umulsi3_highpart.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/loongarch.md | 66 ++++++++++++------- + .../gcc.target/loongarch/mulw_d_wu.c | 9 +++ + .../gcc.target/loongarch/smuldi3_highpart.c | 13 ++++ + .../gcc.target/loongarch/smulsi3_highpart.c | 15 +++++ + .../gcc.target/loongarch/umulsi3_highpart.c | 14 ++++ + 5 files changed, 94 insertions(+), 23 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/loongarch/mulw_d_wu.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/smuldi3_highpart.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/smulsi3_highpart.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/umulsi3_highpart.c + +diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md +index 11c18bf15..264cd325c 100644 +--- a/gcc/config/loongarch/loongarch.md ++++ b/gcc/config/loongarch/loongarch.md +@@ -750,15 +750,6 @@ + (set_attr "type" "imul") + (set_attr "mode" "<MODE>")) + +-(define_insn "mulsidi3_64bit" +- (set (match_operand:DI 0 "register_operand" "=r") +- (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r")) +- (sign_extend:DI (match_operand:SI 2 "register_operand" "r")))) +- "TARGET_64BIT" +- "mulw.d.w\t%0,%1,%2" +- (set_attr "type" "imul") +- (set_attr "mode" "DI")) +- + (define_insn "*mulsi3_extended" + (set (match_operand:DI 0 "register_operand" "=r") + (sign_extend:DI +@@ -787,14 +778,14 @@ + emit_insn (gen_muldi3 (low, operands1, operands2)); + + rtx high = gen_reg_rtx (DImode); +- emit_insn (gen_<u>muldi3_highpart (high, operands1, operands2)); ++ emit_insn (gen_<su>muldi3_highpart (high, operands1, operands2)); + + emit_move_insn (gen_lowpart (DImode, operands0), low); + emit_move_insn (gen_highpart (DImode, operands0), high); + DONE; + }) + +-(define_insn "<u>muldi3_highpart" ++(define_insn "<su>muldi3_highpart" + (set (match_operand:DI 0 "register_operand" "=r") + (truncate:DI + (lshiftrt:TI +@@ -809,22 +800,34 @@ + (set_attr "mode" "DI")) + + (define_expand "<u>mulsidi3" +- (set (match_operand:DI 0 "register_operand" "=r") ++ (set (match_operand:DI 0 "register_operand") + (mult:DI (any_extend:DI +- (match_operand:SI 1 "register_operand" " r")) ++ (match_operand:SI 1 "register_operand")) + (any_extend:DI +- (match_operand:SI 2 "register_operand" " r")))) +- "!TARGET_64BIT" ++ (match_operand:SI 2 "register_operand")))) ++ "" + { +- rtx temp = gen_reg_rtx (SImode); +- emit_insn (gen_mulsi3 (temp, operands1, operands2)); +- emit_insn (gen_<u>mulsi3_highpart (loongarch_subword (operands0, true), +- operands1, operands2)); +- emit_insn (gen_movsi (loongarch_subword (operands0, false), temp)); +- DONE; ++ if (!TARGET_64BIT) ++ { ++ rtx temp = gen_reg_rtx (SImode); ++ emit_insn (gen_mulsi3 (temp, operands1, operands2)); ++ emit_insn (gen_<su>mulsi3_highpart (loongarch_subword (operands0, true), ++ operands1, operands2)); ++ emit_insn (gen_movsi (loongarch_subword (operands0, false), temp)); ++ DONE; ++ } + }) + +-(define_insn "<u>mulsi3_highpart" ++(define_insn "<u>mulsidi3_64bit" ++ (set (match_operand:DI 0 "register_operand" "=r") ++ (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "r")) ++ (any_extend:DI (match_operand:SI 2 "register_operand" "r")))) ++ "TARGET_64BIT" ++ "mulw.d.w<u>\t%0,%1,%2" ++ (set_attr "type" "imul") ++ (set_attr "mode" "DI")) ++ ++(define_insn "<su>mulsi3_highpart" + (set (match_operand:SI 0 "register_operand" "=r") + (truncate:SI + (lshiftrt:DI +@@ -833,11 +836,28 @@ + (any_extend:DI + (match_operand:SI 2 "register_operand" " r"))) + (const_int 32)))) +- "!TARGET_64BIT" ++ "" + "mulh.w<u>\t%0,%1,%2" + (set_attr "type" "imul") + (set_attr "mode" "SI")) + ++;; Under the LoongArch architecture, the mulh.wu instruction performs ++;; sign extension by default, so the sign extension instruction can be ++;; eliminated. ++(define_peephole ++ (set (match_operand:SI 0 "register_operand") ++ (truncate:SI ++ (lshiftrt:DI ++ (mult:DI (any_extend:DI ++ (match_operand:SI 1 "register_operand")) ++ (any_extend:DI ++ (match_operand:SI 2 "register_operand"))) ++ (const_int 32)))) ++ (set (match_operand:DI 3 "register_operand") ++ (sign_extend:DI (match_dup 0))) ++ "TARGET_64BIT && REGNO (operands0) == REGNO (operands3)" ++ "mulh.w<u>\t%0,%1,%2") ++ + ;; + ;; .................... + ;; +diff --git a/gcc/testsuite/gcc.target/loongarch/mulw_d_wu.c b/gcc/testsuite/gcc.target/loongarch/mulw_d_wu.c +new file mode 100644 +index 000000000..16163d667 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/mulw_d_wu.c +@@ -0,0 +1,9 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -mabi=lp64d" } */ ++/* { dg-final { scan-assembler "mulw.d.wu" } } */ ++ ++__attribute__((noipa, noinline)) unsigned long ++f(unsigned long a, unsigned long b) ++{ ++ return (unsigned long)(unsigned int)a * (unsigned long)(unsigned int)b; ++} +diff --git a/gcc/testsuite/gcc.target/loongarch/smuldi3_highpart.c b/gcc/testsuite/gcc.target/loongarch/smuldi3_highpart.c +new file mode 100644 +index 000000000..6f5c686ca +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/smuldi3_highpart.c +@@ -0,0 +1,13 @@ ++/* { dg-do compile } */ ++/* { dg-options "-mabi=lp64d -O2 -fdump-rtl-expand-all" } */ ++ ++typedef int TI __attribute ((mode(TI))); ++typedef int DI __attribute__((mode(DI))); ++ ++DI ++test (DI x, DI y) ++{ ++ return ((TI)x * y) >> 64; ++} ++ ++/* { dg-final { scan-rtl-dump "highparttmp" "expand" } } */ +diff --git a/gcc/testsuite/gcc.target/loongarch/smulsi3_highpart.c b/gcc/testsuite/gcc.target/loongarch/smulsi3_highpart.c +new file mode 100644 +index 000000000..c4dbf8afc +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/smulsi3_highpart.c +@@ -0,0 +1,15 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -fdump-rtl-expand-all" } */ ++ ++typedef unsigned int DI __attribute__((mode(DI))); ++typedef unsigned int SI __attribute__((mode(SI)));
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_service:tar_scm:LoongArch-Prepare-static-PIE-support.patch
Added
@@ -0,0 +1,44 @@ +From aa2d9e0e1dc4bf0b612618cf0e3fcea514f92f95 Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao <xry111@xry111.site> +Date: Tue, 13 Sep 2022 23:21:39 +0800 +Subject: PATCH 018/124 LoongArch: Prepare static PIE support + +Static PIE allows us to extend the ASLR to cover static executables and +it's not too difficult to support it. On GCC side, we just pass a group +of options to the linker, like other ports with static PIE support. + +The real implementation of static PIE (rcrt1.o) will be added into Glibc +later. + +gcc/ChangeLog: + + * config/loongarch/gnu-user.h (GNU_USER_TARGET_LINK_SPEC): For + -static-pie, pass -static -pie --no-dynamic-linker -z text to + the linker, and do not pass --dynamic-linker. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/gnu-user.h | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/gcc/config/loongarch/gnu-user.h b/gcc/config/loongarch/gnu-user.h +index 664dc9206..c5b1afe53 100644 +--- a/gcc/config/loongarch/gnu-user.h ++++ b/gcc/config/loongarch/gnu-user.h +@@ -40,8 +40,10 @@ along with GCC; see the file COPYING3. If not see + #undef GNU_USER_TARGET_LINK_SPEC + #define GNU_USER_TARGET_LINK_SPEC \ + "%{G*} %{shared} -m " GNU_USER_LINK_EMULATION \ +- "%{!shared: %{static} %{!static: %{rdynamic:-export-dynamic} " \ +- "-dynamic-linker " GNU_USER_DYNAMIC_LINKER "}}" ++ "%{!shared: %{static} " \ ++ "%{!static: %{!static-pie: %{rdynamic:-export-dynamic} " \ ++ "-dynamic-linker " GNU_USER_DYNAMIC_LINKER "}} " \ ++ "%{static-pie: -static -pie --no-dynamic-linker -z text}}" + + + /* Similar to standard Linux, but adding -ffast-math support. */ +-- +2.33.0 +
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_service:tar_scm:LoongArch-Provide-fmin-fmax-RTL-pattern.patch
Added
@@ -0,0 +1,100 @@ +From b065c84206cdf463a377ca28f719dae7acbed0f7 Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao <xry111@xry111.site> +Date: Tue, 16 Aug 2022 15:34:36 +0800 +Subject: PATCH 009/124 LoongArch: Provide fmin/fmax RTL pattern + +We already had smin/smax RTL pattern using fmin/fmax instruction. But +for smin/smax, it's unspecified what will happen if either operand is +NaN. So we would generate calls to libc fmin/fmax functions with +-fno-finite-math-only (the default for all optimization levels expect +-Ofast). + +But, LoongArch fmin/fmax instruction is IEEE-754-2008 conformant so we +can also use the instruction for fmin/fmax pattern and avoid the library +function call. + +gcc/ChangeLog: + + * config/loongarch/loongarch.md (fmax<mode>3): New RTL pattern. + (fmin<mode>3): Likewise. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/fmax-fmin.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/loongarch.md | 18 +++++++++++ + .../gcc.target/loongarch/fmax-fmin.c | 30 +++++++++++++++++++ + 2 files changed, 48 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/fmax-fmin.c + +diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md +index 6b6df22a5..8e8868de9 100644 +--- a/gcc/config/loongarch/loongarch.md ++++ b/gcc/config/loongarch/loongarch.md +@@ -1023,6 +1023,24 @@ + (set_attr "type" "fmove") + (set_attr "mode" "<MODE>")) + ++(define_insn "fmax<mode>3" ++ (set (match_operand:ANYF 0 "register_operand" "=f") ++ (smax:ANYF (match_operand:ANYF 1 "register_operand" "f") ++ (match_operand:ANYF 2 "register_operand" "f"))) ++ "" ++ "fmax.<fmt>\t%0,%1,%2" ++ (set_attr "type" "fmove") ++ (set_attr "mode" "<MODE>")) ++ ++(define_insn "fmin<mode>3" ++ (set (match_operand:ANYF 0 "register_operand" "=f") ++ (smin:ANYF (match_operand:ANYF 1 "register_operand" "f") ++ (match_operand:ANYF 2 "register_operand" "f"))) ++ "" ++ "fmin.<fmt>\t%0,%1,%2" ++ (set_attr "type" "fmove") ++ (set_attr "mode" "<MODE>")) ++ + (define_insn "smaxa<mode>3" + (set (match_operand:ANYF 0 "register_operand" "=f") + (if_then_else:ANYF +diff --git a/gcc/testsuite/gcc.target/loongarch/fmax-fmin.c b/gcc/testsuite/gcc.target/loongarch/fmax-fmin.c +new file mode 100644 +index 000000000..92cf8a150 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/fmax-fmin.c +@@ -0,0 +1,30 @@ ++/* { dg-do compile } */ ++/* { dg-options "-mdouble-float -fno-finite-math-only" } */ ++/* { dg-final { scan-assembler "fmin\\.s" } } */ ++/* { dg-final { scan-assembler "fmin\\.d" } } */ ++/* { dg-final { scan-assembler "fmax\\.s" } } */ ++/* { dg-final { scan-assembler "fmax\\.d" } } */ ++ ++double ++_fmax(double a, double b) ++{ ++ return __builtin_fmax(a, b); ++} ++ ++float ++_fmaxf(float a, float b) ++{ ++ return __builtin_fmaxf(a, b); ++} ++ ++double ++_fmin(double a, double b) ++{ ++ return __builtin_fmin(a, b); ++} ++ ++float ++_fminf(float a, float b) ++{ ++ return __builtin_fminf(a, b); ++} +-- +2.33.0 +
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_service:tar_scm:LoongArch-Remove-redundant-sign-extension-instructio.patch
Added
@@ -0,0 +1,180 @@ +From fbe6421c5600a151dbae96d18db2fd31aca2fe7c Mon Sep 17 00:00:00 2001 +From: Lulu Cheng <chenglulu@loongson.cn> +Date: Thu, 24 Aug 2023 16:44:56 +0800 +Subject: PATCH 051/124 LoongArch: Remove redundant sign extension + instructions caused by SLT instructions. + +Since the SLT instruction does not distinguish between 64-bit operations and 32-bit +operations under the 64-bit LoongArch architecture, if the operand of slt is SImode, +the sign extension of the operand needs to be displayed. + +But similar to the test case below, the sign extension is redundant: + + extern int src1, src2, src3; + + int + test (void) + { + int data1 = src1 + src2; + int data2 = src1 + src3; + return data1 > data2 ? data1 : data2; + } +Assembly code before optimization: + ... + add.w $r4,$r4,$r14 + add.w $r13,$r13,$r14 + slli.w $r12,$r4,0 + slli.w $r14,$r13,0 + slt $r12,$r12,$r14 + masknez $r4,$r4,$r12 + maskeqz $r12,$r13,$r12 + or $r4,$r4,$r12 + slli.w $r4,$r4,0 + ... + +After optimization: + ... + add.w $r12,$r12,$r14 + add.w $r13,$r13,$r14 + slt $r4,$r12,$r13 + masknez $r12,$r12,$r4 + maskeqz $r4,$r13,$r4 + or $r4,$r12,$r4 + ... + +Similar to this test example, the two operands of SLT are obtained by the +addition operation, and add.w implicitly sign-extends, so the two operands +of SLT do not require sign-extend. + +gcc/ChangeLog: + + * config/loongarch/loongarch.cc (loongarch_expand_conditional_move): + Optimize the function implementation. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/slt-sign-extend.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/loongarch.cc | 53 +++++++++++++++++-- + .../gcc.target/loongarch/slt-sign-extend.c | 14 +++++ + 2 files changed, 63 insertions(+), 4 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/loongarch/slt-sign-extend.c + +diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc +index f14de5cce..caacfa8a3 100644 +--- a/gcc/config/loongarch/loongarch.cc ++++ b/gcc/config/loongarch/loongarch.cc +@@ -4380,14 +4380,30 @@ loongarch_expand_conditional_move (rtx *operands) + enum rtx_code code = GET_CODE (operands1); + rtx op0 = XEXP (operands1, 0); + rtx op1 = XEXP (operands1, 1); ++ rtx op0_extend = op0; ++ rtx op1_extend = op1; ++ ++ /* Record whether operands2 and operands3 modes are promoted to word_mode. */ ++ bool promote_p = false; ++ machine_mode mode = GET_MODE (operands0); + + if (FLOAT_MODE_P (GET_MODE (op1))) + loongarch_emit_float_compare (&code, &op0, &op1); + else + { ++ if ((REGNO (op0) == REGNO (operands2) ++ || (REGNO (op1) == REGNO (operands3) && (op1 != const0_rtx))) ++ && (GET_MODE_SIZE (GET_MODE (op0)) < word_mode)) ++ { ++ mode = word_mode; ++ promote_p = true; ++ } ++ + loongarch_extend_comparands (code, &op0, &op1); + + op0 = force_reg (word_mode, op0); ++ op0_extend = op0; ++ op1_extend = force_reg (word_mode, op1); + + if (code == EQ || code == NE) + { +@@ -4414,23 +4430,52 @@ loongarch_expand_conditional_move (rtx *operands) + && register_operand (operands2, VOIDmode) + && register_operand (operands3, VOIDmode)) + { +- machine_mode mode = GET_MODE (operands0); ++ rtx op2 = operands2; ++ rtx op3 = operands3; ++ ++ if (promote_p) ++ { ++ if (REGNO (XEXP (operands1, 0)) == REGNO (operands2)) ++ op2 = op0_extend; ++ else ++ { ++ loongarch_extend_comparands (code, &op2, &const0_rtx); ++ op2 = force_reg (mode, op2); ++ } ++ ++ if (REGNO (XEXP (operands1, 1)) == REGNO (operands3)) ++ op3 = op1_extend; ++ else ++ { ++ loongarch_extend_comparands (code, &op3, &const0_rtx); ++ op3 = force_reg (mode, op3); ++ } ++ } ++ + rtx temp = gen_reg_rtx (mode); + rtx temp2 = gen_reg_rtx (mode); + + emit_insn (gen_rtx_SET (temp, + gen_rtx_IF_THEN_ELSE (mode, cond, +- operands2, const0_rtx))); ++ op2, const0_rtx))); + + /* Flip the test for the second operand. */ + cond = gen_rtx_fmt_ee ((code == EQ) ? NE : EQ, GET_MODE (op0), op0, op1); + + emit_insn (gen_rtx_SET (temp2, + gen_rtx_IF_THEN_ELSE (mode, cond, +- operands3, const0_rtx))); ++ op3, const0_rtx))); + + /* Merge the two results, at least one is guaranteed to be zero. */ +- emit_insn (gen_rtx_SET (operands0, gen_rtx_IOR (mode, temp, temp2))); ++ if (promote_p) ++ { ++ rtx temp3 = gen_reg_rtx (mode); ++ emit_insn (gen_rtx_SET (temp3, gen_rtx_IOR (mode, temp, temp2))); ++ temp3 = gen_lowpart (GET_MODE (operands0), temp3); ++ loongarch_emit_move (operands0, temp3); ++ } ++ else ++ emit_insn (gen_rtx_SET (operands0, gen_rtx_IOR (mode, temp, temp2))); + } + else + emit_insn (gen_rtx_SET (operands0, +diff --git a/gcc/testsuite/gcc.target/loongarch/slt-sign-extend.c b/gcc/testsuite/gcc.target/loongarch/slt-sign-extend.c +new file mode 100644 +index 000000000..ea6b28b7c +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/slt-sign-extend.c +@@ -0,0 +1,14 @@ ++/* { dg-do compile } */ ++/* { dg-options "-mabi=lp64d -O2" } */ ++/* { dg-final { scan-assembler-not "slli.w" } } */ ++ ++extern int src1, src2, src3; ++ ++int ++test (void) ++{ ++ int data1 = src1 + src2; ++ int data2 = src1 + src3; ++ ++ return data1 > data2 ? data1 : data2; ++} +-- +2.33.0 +
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_service:tar_scm:LoongArch-Remove-the-definition-of-the-macro-LOGICAL.patch
Added
@@ -0,0 +1,36 @@ +From 297b8c5770ad85bf468526602e28aff8a66dc01a Mon Sep 17 00:00:00 2001 +From: Lulu Cheng <chenglulu@loongson.cn> +Date: Thu, 13 Apr 2023 19:24:38 +0800 +Subject: PATCH 040/124 LoongArch: Remove the definition of the macro + LOGICAL_OP_NON_SHORT_CIRCUIT under the architecture and use the default + definition instead. + +In some cases, setting this macro as the default can reduce the number of conditional +branch instructions. + +gcc/ChangeLog: + + * config/loongarch/loongarch.h (LOGICAL_OP_NON_SHORT_CIRCUIT): Remove the macro + definition. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/loongarch.h | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/gcc/config/loongarch/loongarch.h b/gcc/config/loongarch/loongarch.h +index 392597943..c6e37b1b4 100644 +--- a/gcc/config/loongarch/loongarch.h ++++ b/gcc/config/loongarch/loongarch.h +@@ -836,7 +836,6 @@ typedef struct { + 1 is the default; other values are interpreted relative to that. */ + + #define BRANCH_COST(speed_p, predictable_p) loongarch_branch_cost +-#define LOGICAL_OP_NON_SHORT_CIRCUIT 0 + + /* Return the asm template for a conditional branch instruction. + OPCODE is the opcode's mnemonic and OPERANDS is the asm template for +-- +2.33.0 +
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_service:tar_scm:LoongArch-Rename-frint_-fmt-to-rint-mode-2.patch
Added
@@ -0,0 +1,65 @@ +From 7584716b03b13c06b8bb9956b9f49e0cfc29c6b3 Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao <xry111@xry111.site> +Date: Sun, 6 Nov 2022 20:41:38 +0800 +Subject: PATCH 027/124 LoongArch: Rename frint_<fmt> to rint<mode>2 + +Use standard name so __builtin_rint{,f} can be expanded to one +instruction. + +gcc/ChangeLog: + + * config/loongarch/loongarch.md (frint_<fmt>): Rename to .. + (rint<mode>2): .. this. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/frint.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/loongarch.md | 4 ++-- + gcc/testsuite/gcc.target/loongarch/frint.c | 16 ++++++++++++++++ + 2 files changed, 18 insertions(+), 2 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/loongarch/frint.c + +diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md +index bda34d0f3..a14ab14ac 100644 +--- a/gcc/config/loongarch/loongarch.md ++++ b/gcc/config/loongarch/loongarch.md +@@ -2012,8 +2012,8 @@ + (set_attr "type" "move") + ) + +-;; Convert floating-point numbers to integers +-(define_insn "frint_<fmt>" ++;; Round floating-point numbers to integers ++(define_insn "rint<mode>2" + (set (match_operand:ANYF 0 "register_operand" "=f") + (unspec:ANYF (match_operand:ANYF 1 "register_operand" "f") + UNSPEC_FRINT)) +diff --git a/gcc/testsuite/gcc.target/loongarch/frint.c b/gcc/testsuite/gcc.target/loongarch/frint.c +new file mode 100644 +index 000000000..3ee6a8f97 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/frint.c +@@ -0,0 +1,16 @@ ++/* { dg-do compile } */ ++/* { dg-options "-mdouble-float" } */ ++/* { dg-final { scan-assembler "frint\\.s" } } */ ++/* { dg-final { scan-assembler "frint\\.d" } } */ ++ ++double ++my_rint (double a) ++{ ++ return __builtin_rint (a); ++} ++ ++float ++my_rintf (float a) ++{ ++ return __builtin_rintf (a); ++} +-- +2.33.0 +
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_service:tar_scm:LoongArch-Set-default-alignment-for-functions-and-la.patch
Added
@@ -0,0 +1,113 @@ +From 129d96b9ab5a2445d0fc2c3f7b72baa0453bd93f Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao <xry111@xry111.site> +Date: Wed, 14 Jun 2023 08:24:05 +0800 +Subject: PATCH 047/124 LoongArch: Set default alignment for functions and + labels with -mtune + +The LA464 micro-architecture is sensitive to alignment of code. The +Loongson team has benchmarked various combinations of function, the +results 1 show that 16-byte label alignment together with 32-byte +function alignment gives best results in terms of SPEC score. + +Add a mtune-based table-driven mechanism to set the default of +-falign-{functions,labels}. As LA464 is the first (and the only for +now) uarch supported by GCC, the same setting is also used for +the "generic" -mtune=loongarch64. In the future we may set different +settings for LA{2,3,6}64 once we add the support for them. + +Bootstrapped and regtested on loongarch64-linux-gnu. Ok for trunk? + +gcc/ChangeLog: + + * config/loongarch/loongarch-tune.h (loongarch_align): New + struct. + * config/loongarch/loongarch-def.h (loongarch_cpu_align): New + array. + * config/loongarch/loongarch-def.c (loongarch_cpu_align): Define + the array. + * config/loongarch/loongarch.cc + (loongarch_option_override_internal): Set the value of + -falign-functions= if -falign-functions is enabled but no value + is given. Likewise for -falign-labels=. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/loongarch-def.c | 12 ++++++++++++ + gcc/config/loongarch/loongarch-def.h | 1 + + gcc/config/loongarch/loongarch-tune.h | 8 ++++++++ + gcc/config/loongarch/loongarch.cc | 6 ++++++ + 4 files changed, 27 insertions(+) + +diff --git a/gcc/config/loongarch/loongarch-def.c b/gcc/config/loongarch/loongarch-def.c +index 80ab10a52..74d422ce0 100644 +--- a/gcc/config/loongarch/loongarch-def.c ++++ b/gcc/config/loongarch/loongarch-def.c +@@ -72,6 +72,18 @@ loongarch_cpu_cacheN_TUNE_TYPES = { + }, + }; + ++struct loongarch_align ++loongarch_cpu_alignN_TUNE_TYPES = { ++ CPU_LOONGARCH64 = { ++ .function = "32", ++ .label = "16", ++ }, ++ CPU_LA464 = { ++ .function = "32", ++ .label = "16", ++ }, ++}; ++ + /* The following properties cannot be looked up directly using "cpucfg". + So it is necessary to provide a default value for "unknown native" + tune targets (i.e. -mtune=native while PRID does not correspond to +diff --git a/gcc/config/loongarch/loongarch-def.h b/gcc/config/loongarch/loongarch-def.h +index b5985f070..eb87a79a5 100644 +--- a/gcc/config/loongarch/loongarch-def.h ++++ b/gcc/config/loongarch/loongarch-def.h +@@ -144,6 +144,7 @@ extern int loongarch_cpu_issue_rate; + extern int loongarch_cpu_multipass_dfa_lookahead; + + extern struct loongarch_cache loongarch_cpu_cache; ++extern struct loongarch_align loongarch_cpu_align; + extern struct loongarch_rtx_cost_data loongarch_cpu_rtx_cost_data; + + #ifdef __cplusplus +diff --git a/gcc/config/loongarch/loongarch-tune.h b/gcc/config/loongarch/loongarch-tune.h +index 8e3eb2947..d961963f0 100644 +--- a/gcc/config/loongarch/loongarch-tune.h ++++ b/gcc/config/loongarch/loongarch-tune.h +@@ -48,4 +48,12 @@ struct loongarch_cache { + int simultaneous_prefetches; /* number of parallel prefetch */ + }; + ++/* Alignment for functions and labels for best performance. For new uarchs ++ the value should be measured via benchmarking. See the documentation for ++ -falign-functions and -falign-labels in invoke.texi for the format. */ ++struct loongarch_align { ++ const char *function; /* default value for -falign-functions */ ++ const char *label; /* default value for -falign-labels */ ++}; ++ + #endif /* LOONGARCH_TUNE_H */ +diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc +index 4c0f393b6..f14de5cce 100644 +--- a/gcc/config/loongarch/loongarch.cc ++++ b/gcc/config/loongarch/loongarch.cc +@@ -6246,6 +6246,12 @@ loongarch_option_override_internal (struct gcc_options *opts) + && !opts->x_optimize_size) + opts->x_flag_prefetch_loop_arrays = 1; + ++ if (opts->x_flag_align_functions && !opts->x_str_align_functions) ++ opts->x_str_align_functions = loongarch_cpu_alignLARCH_ACTUAL_TUNE.function; ++ ++ if (opts->x_flag_align_labels && !opts->x_str_align_labels) ++ opts->x_str_align_labels = loongarch_cpu_alignLARCH_ACTUAL_TUNE.label; ++ + if (TARGET_DIRECT_EXTERN_ACCESS && flag_shlib) + error ("%qs cannot be used for compiling a shared library", + "-mdirect-extern-access"); +-- +2.33.0 +
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_service:tar_scm:LoongArch-Slightly-simplify-loongarch_block_move_str.patch
Added
@@ -0,0 +1,37 @@ +From f4a0248c80fedff3a6841407ff95b732dfbb93a1 Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao <xry111@xry111.site> +Date: Fri, 8 Sep 2023 00:29:57 +0800 +Subject: PATCH 073/124 LoongArch: Slightly simplify + loongarch_block_move_straight + +gcc/ChangeLog: + + * config/loongarch/loongarch.cc (loongarch_block_move_straight): + Check precondition (delta must be a power of 2) and use + popcount_hwi instead of a homebrew loop. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/loongarch.cc | 5 ++--- + 1 file changed, 2 insertions(+), 3 deletions(-) + +diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc +index baa5c2354..baa9831aa 100644 +--- a/gcc/config/loongarch/loongarch.cc ++++ b/gcc/config/loongarch/loongarch.cc +@@ -5221,9 +5221,8 @@ loongarch_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length, + emit two ld.d/st.d pairs, one ld.w/st.w pair, and one ld.b/st.b + pair. For each load/store pair we use a dedicated register to keep + the pipeline as populated as possible. */ +- HOST_WIDE_INT num_reg = length / delta; +- for (delta_cur = delta / 2; delta_cur != 0; delta_cur /= 2) +- num_reg += !!(length & delta_cur); ++ gcc_assert (pow2p_hwi (delta)); ++ HOST_WIDE_INT num_reg = length / delta + popcount_hwi (length % delta); + + /* Allocate a buffer for the temporary registers. */ + regs = XALLOCAVEC (rtx, num_reg); +-- +2.33.0 +
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_service:tar_scm:LoongArch-Subdivision-symbol-type-add-SYMBOL_PCREL-s.patch
Added
@@ -0,0 +1,1234 @@ +From 68bb2a2d0b94b9bde3c22ff1dfe08abb6f036e7f Mon Sep 17 00:00:00 2001 +From: Lulu Cheng <chenglulu@loongson.cn> +Date: Thu, 21 Jul 2022 10:32:51 +0800 +Subject: PATCH 003/124 LoongArch: Subdivision symbol type, add SYMBOL_PCREL + support. + +1. Remove cModel type support other than normal. +2. The method for calling global functions changed from 'la.global + jirl' to 'bl' + when complied add '-fplt'. + +gcc/ChangeLog: + + * config/loongarch/constraints.md (a): Delete the constraint. + (b): A constant call not local address. + (h): Delete the constraint. + (t): Delete the constraint. + * config/loongarch/loongarch-opts.cc (loongarch_config_target): + Remove cModel type support other than normal. + * config/loongarch/loongarch-protos.h (enum loongarch_symbol_type): + Add new symbol type 'SYMBOL_PCREL', 'SYMBOL_TLS_IE' and 'SYMBOL_TLS_LE'. + (loongarch_split_symbol): Delete useless function declarations. + (loongarch_split_symbol_type): Delete useless function declarations. + * config/loongarch/loongarch.cc (enum loongarch_address_type): + Delete unnecessary comment information. + (loongarch_symbol_binds_local_p): Modified the judgment order of label + and symbol. + (loongarch_classify_symbol): Return symbol type. If symbol is a label, + or symbol is a local symbol return SYMBOL_PCREL. If is a tls symbol, + return SYMBOL_TLS. If is a not local symbol return SYMBOL_GOT_DISP. + (loongarch_symbolic_constant_p): Add handling of 'SYMBOL_TLS_IE' + 'SYMBOL_TLS_LE' and 'SYMBOL_PCREL'. + (loongarch_symbol_insns): Add handling of 'SYMBOL_TLS_IE' 'SYMBOL_TLS_LE' + and 'SYMBOL_PCREL'. + (loongarch_address_insns): Sort code. + (loongarch_12bit_offset_address_p): Sort code. + (loongarch_14bit_shifted_offset_address_p): Sort code. + (loongarch_call_tls_get_addr): Sort code. + (loongarch_legitimize_tls_address): Sort code. + (loongarch_output_move): Remove schema support for cmodel other than normal. + (loongarch_memmodel_needs_release_fence): Sort code. + (loongarch_print_operand): Sort code. + * config/loongarch/loongarch.h (LARCH_U12BIT_OFFSET_P): + Rename to LARCH_12BIT_OFFSET_P. + (LARCH_12BIT_OFFSET_P): New macro. + * config/loongarch/loongarch.md: Reimplement the function call. Remove schema + support for cmodel other than normal. + * config/loongarch/predicates.md (is_const_call_weak_symbol): Delete this predicate. + (is_const_call_plt_symbol): Delete this predicate. + (is_const_call_global_noplt_symbol): Delete this predicate. + (is_const_call_no_local_symbol): New predicate, determines whether it is a local + symbol or label. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/func-call-1.c: New test. + * gcc.target/loongarch/func-call-2.c: New test. + * gcc.target/loongarch/func-call-3.c: New test. + * gcc.target/loongarch/func-call-4.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/constraints.md | 24 +- + gcc/config/loongarch/loongarch-opts.cc | 7 + + gcc/config/loongarch/loongarch-protos.h | 9 +- + gcc/config/loongarch/loongarch.cc | 256 +++++++--------- + gcc/config/loongarch/loongarch.h | 2 +- + gcc/config/loongarch/loongarch.md | 279 +++--------------- + gcc/config/loongarch/predicates.md | 40 ++- + .../gcc.target/loongarch/func-call-1.c | 32 ++ + .../gcc.target/loongarch/func-call-2.c | 32 ++ + .../gcc.target/loongarch/func-call-3.c | 32 ++ + .../gcc.target/loongarch/func-call-4.c | 32 ++ + 11 files changed, 312 insertions(+), 433 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/loongarch/func-call-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/func-call-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/func-call-3.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/func-call-4.c + +diff --git a/gcc/config/loongarch/constraints.md b/gcc/config/loongarch/constraints.md +index d0bfddbd5..43cb7b5f0 100644 +--- a/gcc/config/loongarch/constraints.md ++++ b/gcc/config/loongarch/constraints.md +@@ -20,14 +20,14 @@ + + ;; Register constraints + +-;; "a" "A constant call global and noplt address." +-;; "b" <-----unused ++;; "a" <-----unused ++;; "b" "A constant call not local address." + ;; "c" "A constant call local address." + ;; "d" <-----unused + ;; "e" JIRL_REGS + ;; "f" FP_REGS + ;; "g" <-----unused +-;; "h" "A constant call plt address." ++;; "h" <-----unused + ;; "i" "Matches a general integer constant." (Global non-architectural) + ;; "j" SIBCALL_REGS + ;; "k" "A memory operand whose address is formed by a base register and +@@ -42,7 +42,7 @@ + ;; "q" CSR_REGS + ;; "r" GENERAL_REGS (Global non-architectural) + ;; "s" "Matches a symbolic integer constant." (Global non-architectural) +-;; "t" "A constant call weak address" ++;; "t" <-----unused + ;; "u" "A signed 52bit constant and low 32-bit is zero (for logic instructions)" + ;; "v" "A signed 64-bit constant and low 44-bit is zero (for logic instructions)." + ;; "w" "Matches any valid memory." +@@ -89,10 +89,10 @@ + ;; "<" "Matches a pre-dec or post-dec operand." (Global non-architectural) + ;; ">" "Matches a pre-inc or post-inc operand." (Global non-architectural) + +-(define_constraint "a" ++(define_constraint "b" + "@internal +- A constant call global and noplt address." +- (match_operand 0 "is_const_call_global_noplt_symbol")) ++ A constant call no local address." ++ (match_operand 0 "is_const_call_no_local_symbol")) + + (define_constraint "c" + "@internal +@@ -105,11 +105,6 @@ + (define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS" + "A floating-point register (if available).") + +-(define_constraint "h" +- "@internal +- A constant call plt address." +- (match_operand 0 "is_const_call_plt_symbol")) +- + (define_register_constraint "j" "SIBCALL_REGS" + "@internal") + +@@ -134,11 +129,6 @@ + (define_register_constraint "q" "CSR_REGS" + "A general-purpose register except for $r0 and $r1 for lcsr.") + +-(define_constraint "t" +- "@internal +- A constant call weak address." +- (match_operand 0 "is_const_call_weak_symbol")) +- + (define_constraint "u" + "A signed 52bit constant and low 32-bit is zero (for logic instructions)." + (and (match_code "const_int") +diff --git a/gcc/config/loongarch/loongarch-opts.cc b/gcc/config/loongarch/loongarch-opts.cc +index eb9c2a52f..fc477bfd4 100644 +--- a/gcc/config/loongarch/loongarch-opts.cc ++++ b/gcc/config/loongarch/loongarch-opts.cc +@@ -376,6 +376,13 @@ fallback: + + /* 5. Target code model */ + t.cmodel = constrained.cmodel ? opt_cmodel : CMODEL_NORMAL; ++ if (t.cmodel != CMODEL_NORMAL) ++ { ++ warning (0, "%qs is not supported, now cmodel is set to 'normal'.", ++ loongarch_cmodel_stringst.cmodel); ++ t.cmodel = CMODEL_NORMAL; ++ } ++ + + /* Cleanup and return. */ + obstack_free (&msg_obstack, NULL); +diff --git a/gcc/config/loongarch/loongarch-protos.h b/gcc/config/loongarch/loongarch-protos.h +index 2287fd376..080766250 100644 +--- a/gcc/config/loongarch/loongarch-protos.h ++++ b/gcc/config/loongarch/loongarch-protos.h +@@ -27,9 +27,13 @@ along with GCC; see the file COPYING3. If not see + SYMBOL_GOT_DISP + The symbol's value will be loaded directly from the GOT. + ++ SYMBOL_PCREL ++ The symbol's value will be loaded directly from data section. ++ + SYMBOL_TLS + A thread-local symbol. + ++ SYMBOL_TLS_IE + SYMBOL_TLSGD + SYMBOL_TLSLDM + UNSPEC wrappers around SYMBOL_TLS, corresponding to the +@@ -37,7 +41,10 @@ along with GCC; see the file COPYING3. If not see + */ + enum loongarch_symbol_type { + SYMBOL_GOT_DISP, ++ SYMBOL_PCREL, + SYMBOL_TLS, ++ SYMBOL_TLS_IE, ++ SYMBOL_TLS_LE, + SYMBOL_TLSGD, + SYMBOL_TLSLDM, + }; +@@ -61,7 +68,6 @@ extern int loongarch_idiv_insns (machine_mode); + #ifdef RTX_CODE + extern void loongarch_emit_binary (enum rtx_code, rtx, rtx, rtx); + #endif
View file
_service:tar_scm:LoongArch-Support-split-symbol.patch
Added
@@ -0,0 +1,1238 @@ +From 078261cabef370e7f3201980d03bd54a049290e9 Mon Sep 17 00:00:00 2001 +From: Lulu Cheng <chenglulu@loongson.cn> +Date: Thu, 21 Jul 2022 11:04:08 +0800 +Subject: PATCH 004/124 LoongArch: Support split symbol. + +Add compilation option '-mexplicit-relocs', and if enable '-mexplicit-relocs' +the symbolic address load instruction 'la.*' will be split into two instructions. +This compilation option enabled by default. + +gcc/ChangeLog: + + * common/config/loongarch/loongarch-common.cc: + Enable '-fsection-anchors' when O1 and more advanced optimization. + * config/loongarch/genopts/loongarch.opt.in: Add new option + '-mexplicit-relocs', and enable by default. + * config/loongarch/loongarch-protos.h (loongarch_split_move_insn_p): + Delete function declaration. + (loongarch_split_move_insn): Delete function declaration. + (loongarch_split_symbol_type): Add function declaration. + * config/loongarch/loongarch.cc (enum loongarch_address_type): + Add new address type 'ADDRESS_LO_SUM'. + (loongarch_classify_symbolic_expression): New function definitions. + Classify the base of symbolic expression X, given that X appears in + context CONTEXT. + (loongarch_symbol_insns): Add a judgment condition TARGET_EXPLICIT_RELOCS. + (loongarch_split_symbol_type): New function definitions. + Determines whether the symbol load should be split into two instructions. + (loongarch_valid_lo_sum_p): New function definitions. + Return true if a LO_SUM can address a value of mode MODE when the LO_SUM + symbol has type SYMBOL_TYPE. + (loongarch_classify_address): Add handling of 'LO_SUM'. + (loongarch_address_insns): Add handling of 'ADDRESS_LO_SUM'. + (loongarch_signed_immediate_p): Sort code. + (loongarch_12bit_offset_address_p): Return true if address type is ADDRESS_LO_SUM. + (loongarch_const_insns): Add handling of 'HIGH'. + (loongarch_split_move_insn_p): Add the static attribute to the function. + (loongarch_emit_set): New function definitions. + (loongarch_call_tls_get_addr): Add symbol handling when defining TARGET_EXPLICIT_RELOCS. + (loongarch_legitimize_tls_address): Add symbol handling when defining the + TARGET_EXPLICIT_RELOCS macro. + (loongarch_split_symbol): New function definitions. Split symbol. + (loongarch_legitimize_address): Add codes see if the address can split into a high part + and a LO_SUM. + (loongarch_legitimize_const_move): Add codes split moves of symbolic constants into + high and low. + (loongarch_split_move_insn): Delete function definitions. + (loongarch_output_move): Add support for HIGH and LO_SUM. + (loongarch_print_operand_reloc): New function definitions. + Print symbolic operand OP, which is part of a HIGH or LO_SUM in context CONTEXT. + (loongarch_memmodel_needs_release_fence): Sort code. + (loongarch_print_operand): Rearrange alphabetical order and add H and L to support HIGH + and LOW output. + (loongarch_print_operand_address): Add handling of 'ADDRESS_LO_SUM'. + (TARGET_MIN_ANCHOR_OFFSET): Define macro to -IMM_REACH/2. + (TARGET_MAX_ANCHOR_OFFSET): Define macro to IMM_REACH/2-1. + * config/loongarch/loongarch.md (movti): Delete the template. + (*movti): Delete the template. + (movtf): Delete the template. + (*movtf): Delete the template. + (*low<mode>): New template of normal symbol low address. + (@tls_low<mode>): New template of tls symbol low address. + (@ld_from_got<mode>): New template load address from got table. + (@ori_l_lo12<mode>): New template. + * config/loongarch/loongarch.opt: Update from loongarch.opt.in. + * config/loongarch/predicates.md: Add support for symbol_type HIGH. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/func-call-1.c: Add build option '-mno-explicit-relocs'. + * gcc.target/loongarch/func-call-2.c: Add build option '-mno-explicit-relocs'. + * gcc.target/loongarch/func-call-3.c: Add build option '-mno-explicit-relocs'. + * gcc.target/loongarch/func-call-4.c: Add build option '-mno-explicit-relocs'. + * gcc.target/loongarch/func-call-5.c: New test. + * gcc.target/loongarch/func-call-6.c: New test. + * gcc.target/loongarch/func-call-7.c: New test. + * gcc.target/loongarch/func-call-8.c: New test. + * gcc.target/loongarch/relocs-symbol-noaddend.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + .../config/loongarch/loongarch-common.cc | 1 + + gcc/config/loongarch/genopts/loongarch.opt.in | 4 + + gcc/config/loongarch/loongarch-protos.h | 3 +- + gcc/config/loongarch/loongarch.cc | 412 ++++++++++++++++-- + gcc/config/loongarch/loongarch.md | 122 +++--- + gcc/config/loongarch/loongarch.opt | 4 + + gcc/config/loongarch/predicates.md | 20 +- + .../gcc.target/loongarch/func-call-1.c | 2 +- + .../gcc.target/loongarch/func-call-2.c | 2 +- + .../gcc.target/loongarch/func-call-3.c | 2 +- + .../gcc.target/loongarch/func-call-4.c | 2 +- + .../gcc.target/loongarch/func-call-5.c | 33 ++ + .../gcc.target/loongarch/func-call-6.c | 33 ++ + .../gcc.target/loongarch/func-call-7.c | 34 ++ + .../gcc.target/loongarch/func-call-8.c | 33 ++ + .../loongarch/relocs-symbol-noaddend.c | 23 + + 16 files changed, 614 insertions(+), 116 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/loongarch/func-call-5.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/func-call-6.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/func-call-7.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/func-call-8.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/relocs-symbol-noaddend.c + +diff --git a/gcc/common/config/loongarch/loongarch-common.cc b/gcc/common/config/loongarch/loongarch-common.cc +index ed3730fce..f8b4660fa 100644 +--- a/gcc/common/config/loongarch/loongarch-common.cc ++++ b/gcc/common/config/loongarch/loongarch-common.cc +@@ -34,6 +34,7 @@ along with GCC; see the file COPYING3. If not see + static const struct default_options loongarch_option_optimization_table = + { + { OPT_LEVELS_ALL, OPT_fasynchronous_unwind_tables, NULL, 1 }, ++ { OPT_LEVELS_1_PLUS, OPT_fsection_anchors, NULL, 1 }, + { OPT_LEVELS_NONE, 0, NULL, 0 } + }; + +diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in b/gcc/config/loongarch/genopts/loongarch.opt.in +index 61e7d72a0..6f3950093 100644 +--- a/gcc/config/loongarch/genopts/loongarch.opt.in ++++ b/gcc/config/loongarch/genopts/loongarch.opt.in +@@ -154,6 +154,10 @@ mmax-inline-memcpy-size= + Target Joined RejectNegative UInteger Var(loongarch_max_inline_memcpy_size) Init(1024) + -mmax-inline-memcpy-size=SIZE Set the max size of memcpy to inline, default is 1024. + ++mexplicit-relocs ++Target Var(TARGET_EXPLICIT_RELOCS) Init(1) ++Use %reloc() assembly operators. ++ + ; The code model option names for -mcmodel. + Enum + Name(cmodel) Type(int) +diff --git a/gcc/config/loongarch/loongarch-protos.h b/gcc/config/loongarch/loongarch-protos.h +index 080766250..cadaad751 100644 +--- a/gcc/config/loongarch/loongarch-protos.h ++++ b/gcc/config/loongarch/loongarch-protos.h +@@ -77,8 +77,6 @@ extern rtx loongarch_legitimize_call_address (rtx); + extern rtx loongarch_subword (rtx, bool); + extern bool loongarch_split_move_p (rtx, rtx); + extern void loongarch_split_move (rtx, rtx, rtx); +-extern bool loongarch_split_move_insn_p (rtx, rtx); +-extern void loongarch_split_move_insn (rtx, rtx, rtx); + extern const char *loongarch_output_move (rtx, rtx); + extern bool loongarch_cfun_has_cprestore_slot_p (void); + #ifdef RTX_CODE +@@ -160,6 +158,7 @@ extern rtx loongarch_expand_thread_pointer (rtx); + extern bool loongarch_eh_uses (unsigned int); + extern bool loongarch_epilogue_uses (unsigned int); + extern bool loongarch_load_store_bonding_p (rtx *, machine_mode, bool); ++extern bool loongarch_split_symbol_type (enum loongarch_symbol_type); + + typedef rtx (*mulsidi3_gen_fn) (rtx, rtx, rtx); + +diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc +index 2e2f16e72..1b5af2c7d 100644 +--- a/gcc/config/loongarch/loongarch.cc ++++ b/gcc/config/loongarch/loongarch.cc +@@ -100,6 +100,10 @@ along with GCC; see the file COPYING3. If not see + ADDRESS_REG_REG + A base register indexed by (optionally scaled) register. + ++ ADDRESS_LO_SUM ++ A LO_SUM rtx. The first operand is a valid base register and the second ++ operand is a symbolic address. ++ + ADDRESS_CONST_INT + A signed 16-bit constant address. + +@@ -109,6 +113,7 @@ enum loongarch_address_type + { + ADDRESS_REG, + ADDRESS_REG_REG, ++ ADDRESS_LO_SUM, + ADDRESS_CONST_INT, + ADDRESS_SYMBOLIC + }; +@@ -1641,6 +1646,21 @@ loongarch_classify_symbol (const_rtx x) + return SYMBOL_PCREL; + } + ++/* Classify the base of symbolic expression X, given that X appears in ++ context CONTEXT. */ ++ ++static enum loongarch_symbol_type ++loongarch_classify_symbolic_expression (rtx x) ++{ ++ rtx offset; ++ ++ split_const (x, &x, &offset); ++ if (UNSPEC_ADDRESS_P (x)) ++ return UNSPEC_ADDRESS_TYPE (x); ++ ++ return loongarch_classify_symbol (x); ++} ++ + /* Return true if X is a symbolic constant. If it is, + store the type of the symbol in *SYMBOL_TYPE. */ + +@@ -1696,7 +1716,7 @@ loongarch_symbol_insns (enum loongarch_symbol_type type, machine_mode mode) + case SYMBOL_GOT_DISP:
View file
_service:tar_scm:LoongArch-Support-storing-floating-point-zero-into-M.patch
Added
@@ -0,0 +1,90 @@ +From de803130fa7d33afaf6e2fc42ef1cd97e45edf96 Mon Sep 17 00:00:00 2001 +From: Guo Jie <guojie@loongson.cn> +Date: Fri, 1 Sep 2023 16:35:05 +0800 +Subject: PATCH 057/124 LoongArch: Support storing floating-point zero into + MEMbase + index. + +v2: Modify commit message. + +gcc/ChangeLog: + + * config/loongarch/loongarch.md: Support 'G' -> 'k' in + movsf_hardfloat and movdf_hardfloat. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/const-double-zero-stx.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/loongarch.md | 12 ++++++------ + .../loongarch/const-double-zero-stx.c | 18 ++++++++++++++++++ + 2 files changed, 24 insertions(+), 6 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/loongarch/const-double-zero-stx.c + +diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md +index a5e9352ca..2d269794f 100644 +--- a/gcc/config/loongarch/loongarch.md ++++ b/gcc/config/loongarch/loongarch.md +@@ -1915,13 +1915,13 @@ + }) + + (define_insn "*movsf_hardfloat" +- (set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,f,k,m,*f,*r,*r,*r,*m") +- (match_operand:SF 1 "move_operand" "f,G,m,f,k,f,G,*r,*f,*G*r,*m,*r")) ++ (set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,f,k,m,k,*f,*r,*r,*r,*m") ++ (match_operand:SF 1 "move_operand" "f,G,m,f,k,f,G,G,*r,*f,*G*r,*m,*r")) + "TARGET_HARD_FLOAT + && (register_operand (operands0, SFmode) + || reg_or_0_operand (operands1, SFmode))" + { return loongarch_output_move (operands0, operands1); } +- (set_attr "move_type" "fmove,mgtf,fpload,fpstore,fpload,fpstore,store,mgtf,mftg,move,load,store") ++ (set_attr "move_type" "fmove,mgtf,fpload,fpstore,fpload,fpstore,store,store,mgtf,mftg,move,load,store") + (set_attr "mode" "SF")) + + (define_insn "*movsf_softfloat" +@@ -1946,13 +1946,13 @@ + }) + + (define_insn "*movdf_hardfloat" +- (set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,f,k,m,*f,*r,*r,*r,*m") +- (match_operand:DF 1 "move_operand" "f,G,m,f,k,f,G,*r,*f,*r*G,*m,*r")) ++ (set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,f,k,m,k,*f,*r,*r,*r,*m") ++ (match_operand:DF 1 "move_operand" "f,G,m,f,k,f,G,G,*r,*f,*r*G,*m,*r")) + "TARGET_DOUBLE_FLOAT + && (register_operand (operands0, DFmode) + || reg_or_0_operand (operands1, DFmode))" + { return loongarch_output_move (operands0, operands1); } +- (set_attr "move_type" "fmove,mgtf,fpload,fpstore,fpload,fpstore,store,mgtf,mftg,move,load,store") ++ (set_attr "move_type" "fmove,mgtf,fpload,fpstore,fpload,fpstore,store,store,mgtf,mftg,move,load,store") + (set_attr "mode" "DF")) + + (define_insn "*movdf_softfloat" +diff --git a/gcc/testsuite/gcc.target/loongarch/const-double-zero-stx.c b/gcc/testsuite/gcc.target/loongarch/const-double-zero-stx.c +new file mode 100644 +index 000000000..8fb04be8f +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/const-double-zero-stx.c +@@ -0,0 +1,18 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2" } */ ++/* { dg-final { scan-assembler-times {stx\..\t\$r0} 2 } } */ ++ ++extern float arr_f; ++extern double arr_d; ++ ++void ++test_f (int base, int index) ++{ ++ arr_fbase + index = 0.0; ++} ++ ++void ++test_d (int base, int index) ++{ ++ arr_dbase + index = 0.0; ++} +-- +2.33.0 +
View file
_service:tar_scm:LoongArch-Use-LSX-and-LASX-for-block-move.patch
Added
@@ -0,0 +1,154 @@ +From 01b932dead0e7bcc05aae2ac742c76b5fcac5ae7 Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao <xry111@xry111.site> +Date: Tue, 5 Sep 2023 21:02:38 +0800 +Subject: PATCH 072/124 LoongArch: Use LSX and LASX for block move + +gcc/ChangeLog: + + * config/loongarch/loongarch.h (LARCH_MAX_MOVE_PER_INSN): + Define to the maximum amount of bytes able to be loaded or + stored with one machine instruction. + * config/loongarch/loongarch.cc (loongarch_mode_for_move_size): + New static function. + (loongarch_block_move_straight): Call + loongarch_mode_for_move_size for machine_mode to be moved. + (loongarch_expand_block_move): Use LARCH_MAX_MOVE_PER_INSN + instead of UNITS_PER_WORD. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/memcpy-vec-1.c: New test. + * gcc.target/loongarch/memcpy-vec-2.c: New test. + * gcc.target/loongarch/memcpy-vec-3.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/loongarch.cc | 22 +++++++++++++++---- + gcc/config/loongarch/loongarch.h | 3 +++ + .../gcc.target/loongarch/memcpy-vec-1.c | 11 ++++++++++ + .../gcc.target/loongarch/memcpy-vec-2.c | 12 ++++++++++ + .../gcc.target/loongarch/memcpy-vec-3.c | 6 +++++ + 5 files changed, 50 insertions(+), 4 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/loongarch/memcpy-vec-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/memcpy-vec-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/memcpy-vec-3.c + +diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc +index 4b0944d56..baa5c2354 100644 +--- a/gcc/config/loongarch/loongarch.cc ++++ b/gcc/config/loongarch/loongarch.cc +@@ -5187,6 +5187,20 @@ loongarch_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED, + return true; + } + ++static machine_mode ++loongarch_mode_for_move_size (HOST_WIDE_INT size) ++{ ++ switch (size) ++ { ++ case 32: ++ return V32QImode; ++ case 16: ++ return V16QImode; ++ } ++ ++ return int_mode_for_size (size * BITS_PER_UNIT, 0).require (); ++} ++ + /* Emit straight-line code to move LENGTH bytes from SRC to DEST. + Assume that the areas do not overlap. */ + +@@ -5216,7 +5230,7 @@ loongarch_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length, + + for (delta_cur = delta, i = 0, offs = 0; offs < length; delta_cur /= 2) + { +- mode = int_mode_for_size (delta_cur * BITS_PER_UNIT, 0).require (); ++ mode = loongarch_mode_for_move_size (delta_cur); + + for (; offs + delta_cur <= length; offs += delta_cur, i++) + { +@@ -5227,7 +5241,7 @@ loongarch_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length, + + for (delta_cur = delta, i = 0, offs = 0; offs < length; delta_cur /= 2) + { +- mode = int_mode_for_size (delta_cur * BITS_PER_UNIT, 0).require (); ++ mode = loongarch_mode_for_move_size (delta_cur); + + for (; offs + delta_cur <= length; offs += delta_cur, i++) + loongarch_emit_move (adjust_address (dest, mode, offs), regsi); +@@ -5322,8 +5336,8 @@ loongarch_expand_block_move (rtx dest, rtx src, rtx r_length, rtx r_align) + + HOST_WIDE_INT align = INTVAL (r_align); + +- if (!TARGET_STRICT_ALIGN || align > UNITS_PER_WORD) +- align = UNITS_PER_WORD; ++ if (!TARGET_STRICT_ALIGN || align > LARCH_MAX_MOVE_PER_INSN) ++ align = LARCH_MAX_MOVE_PER_INSN; + + if (length <= align * LARCH_MAX_MOVE_OPS_STRAIGHT) + { +diff --git a/gcc/config/loongarch/loongarch.h b/gcc/config/loongarch/loongarch.h +index b2295c589..c7e91a06d 100644 +--- a/gcc/config/loongarch/loongarch.h ++++ b/gcc/config/loongarch/loongarch.h +@@ -1181,6 +1181,9 @@ typedef struct { + least twice. */ + #define LARCH_MAX_MOVE_OPS_STRAIGHT (LARCH_MAX_MOVE_OPS_PER_LOOP_ITER * 2) + ++#define LARCH_MAX_MOVE_PER_INSN \ ++ (ISA_HAS_LASX ? 32 : (ISA_HAS_LSX ? 16 : UNITS_PER_WORD)) ++ + /* The base cost of a memcpy call, for MOVE_RATIO and friends. These + values were determined experimentally by benchmarking with CSiBE. + */ +diff --git a/gcc/testsuite/gcc.target/loongarch/memcpy-vec-1.c b/gcc/testsuite/gcc.target/loongarch/memcpy-vec-1.c +new file mode 100644 +index 000000000..8d9fedc9e +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/memcpy-vec-1.c +@@ -0,0 +1,11 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -mabi=lp64d -march=la464 -mno-strict-align" } */ ++/* { dg-final { scan-assembler-times "xvst" 2 } } */ ++/* { dg-final { scan-assembler-times "\tvst" 1 } } */ ++/* { dg-final { scan-assembler-times "st\\.d|stptr\\.d" 1 } } */ ++/* { dg-final { scan-assembler-times "st\\.w|stptr\\.w" 1 } } */ ++/* { dg-final { scan-assembler-times "st\\.h" 1 } } */ ++/* { dg-final { scan-assembler-times "st\\.b" 1 } } */ ++ ++extern char a, b; ++void test() { __builtin_memcpy(a, b, 95); } +diff --git a/gcc/testsuite/gcc.target/loongarch/memcpy-vec-2.c b/gcc/testsuite/gcc.target/loongarch/memcpy-vec-2.c +new file mode 100644 +index 000000000..6b28b884d +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/memcpy-vec-2.c +@@ -0,0 +1,12 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -mabi=lp64d -march=la464 -mno-strict-align" } */ ++/* { dg-final { scan-assembler-times "xvst" 2 } } */ ++/* { dg-final { scan-assembler-times "\tvst" 1 } } */ ++/* { dg-final { scan-assembler-times "st\\.d|stptr\\.d" 1 } } */ ++/* { dg-final { scan-assembler-times "st\\.w|stptr\\.w" 1 } } */ ++/* { dg-final { scan-assembler-times "st\\.h" 1 } } */ ++/* { dg-final { scan-assembler-times "st\\.b" 1 } } */ ++ ++typedef char __attribute__ ((vector_size (32), aligned (32))) vec; ++extern vec a, b; ++void test() { __builtin_memcpy(a, b, 95); } +diff --git a/gcc/testsuite/gcc.target/loongarch/memcpy-vec-3.c b/gcc/testsuite/gcc.target/loongarch/memcpy-vec-3.c +new file mode 100644 +index 000000000..233ed2150 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/memcpy-vec-3.c +@@ -0,0 +1,6 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -march=la464 -mabi=lp64d -mstrict-align" } */ ++/* { dg-final { scan-assembler-not "vst" } } */ ++ ++extern char a, b; ++void test() { __builtin_memcpy(a, b, 16); } +-- +2.33.0 +
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_service:tar_scm:LoongArch-Use-UNSPEC-for-fmin-fmax-RTL-pattern-PR105.patch
Added
@@ -0,0 +1,68 @@ +From d6c7fe54314f7633d779da1a635a8f0832b8f4f6 Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao <xry111@xry111.site> +Date: Sat, 24 Sep 2022 20:47:22 +0800 +Subject: PATCH 021/124 LoongArch: Use UNSPEC for fmin/fmax RTL pattern + PR105414 + +I made a mistake defining fmin/fmax RTL patterns in r13-2085: I used +smin and smax in the definition mistakenly. This causes the optimizer +to perform constant folding as if fmin/fmax was "really" smin/smax +operations even with -fsignaling-nans. Then pr105414.c fails. + +We don't have fmin/fmax RTL codes for now (PR107013) so we can only use +an UNSPEC for fmin and fmax patterns. + +gcc/ChangeLog: + + PR tree-optimization/105414 + * config/loongarch/loongarch.md (UNSPEC_FMAX): New unspec. + (UNSPEC_FMIN): Likewise. + (fmax<mode>3): Use UNSPEC_FMAX instead of smax. + (fmin<mode>3): Use UNSPEC_FMIN instead of smin. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/loongarch.md | 12 ++++++++---- + 1 file changed, 8 insertions(+), 4 deletions(-) + +diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md +index 3787fd823..214b14bdd 100644 +--- a/gcc/config/loongarch/loongarch.md ++++ b/gcc/config/loongarch/loongarch.md +@@ -35,6 +35,8 @@ + ;; Floating point unspecs. + UNSPEC_FRINT + UNSPEC_FCLASS ++ UNSPEC_FMAX ++ UNSPEC_FMIN + + ;; Override return address for exception handling. + UNSPEC_EH_RETURN +@@ -1032,8 +1034,9 @@ + + (define_insn "fmax<mode>3" + (set (match_operand:ANYF 0 "register_operand" "=f") +- (smax:ANYF (match_operand:ANYF 1 "register_operand" "f") +- (match_operand:ANYF 2 "register_operand" "f"))) ++ (unspec:ANYF (use (match_operand:ANYF 1 "register_operand" "f")) ++ (use (match_operand:ANYF 2 "register_operand" "f")) ++ UNSPEC_FMAX)) + "" + "fmax.<fmt>\t%0,%1,%2" + (set_attr "type" "fmove") +@@ -1041,8 +1044,9 @@ + + (define_insn "fmin<mode>3" + (set (match_operand:ANYF 0 "register_operand" "=f") +- (smin:ANYF (match_operand:ANYF 1 "register_operand" "f") +- (match_operand:ANYF 2 "register_operand" "f"))) ++ (unspec:ANYF (use (match_operand:ANYF 1 "register_operand" "f")) ++ (use (match_operand:ANYF 2 "register_operand" "f")) ++ UNSPEC_FMIN)) + "" + "fmin.<fmt>\t%0,%1,%2" + (set_attr "type" "fmove") +-- +2.33.0 +
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_service:tar_scm:LoongArch-Use-bstrins-instruction-for-a-mask-and-a-m.patch
Added
@@ -0,0 +1,336 @@ +From 1c63c61f6508e3c718be79dd27dda25db2b291ee Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao <xry111@xry111.site> +Date: Tue, 5 Sep 2023 19:42:30 +0800 +Subject: PATCH 068/124 LoongArch: Use bstrins instruction for (a & ~mask) + and (a & mask) | (b & ~mask) PR111252 + +If mask is a constant with value ((1 << N) - 1) << M we can perform this +optimization. + +gcc/ChangeLog: + + PR target/111252 + * config/loongarch/loongarch-protos.h + (loongarch_pre_reload_split): Declare new function. + (loongarch_use_bstrins_for_ior_with_mask): Likewise. + * config/loongarch/loongarch.cc + (loongarch_pre_reload_split): Implement. + (loongarch_use_bstrins_for_ior_with_mask): Likewise. + * config/loongarch/predicates.md (ins_zero_bitmask_operand): + New predicate. + * config/loongarch/loongarch.md (bstrins_<mode>_for_mask): + New define_insn_and_split. + (bstrins_<mode>_for_ior_mask): Likewise. + (define_peephole2): Further optimize code sequence produced by + bstrins_<mode>_for_ior_mask if possible. + +gcc/testsuite/ChangeLog: + + * g++.target/loongarch/bstrins-compile.C: New test. + * g++.target/loongarch/bstrins-run.C: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/loongarch-protos.h | 4 +- + gcc/config/loongarch/loongarch.cc | 36 ++++++++ + gcc/config/loongarch/loongarch.md | 91 +++++++++++++++++++ + gcc/config/loongarch/predicates.md | 8 ++ + .../g++.target/loongarch/bstrins-compile.C | 22 +++++ + .../g++.target/loongarch/bstrins-run.C | 65 +++++++++++++ + 6 files changed, 225 insertions(+), 1 deletion(-) + create mode 100644 gcc/testsuite/g++.target/loongarch/bstrins-compile.C + create mode 100644 gcc/testsuite/g++.target/loongarch/bstrins-run.C + +diff --git a/gcc/config/loongarch/loongarch-protos.h b/gcc/config/loongarch/loongarch-protos.h +index 133ec9fa8..ea61cf567 100644 +--- a/gcc/config/loongarch/loongarch-protos.h ++++ b/gcc/config/loongarch/loongarch-protos.h +@@ -56,7 +56,7 @@ enum loongarch_symbol_type { + }; + #define NUM_SYMBOL_TYPES (SYMBOL_TLSLDM + 1) + +-/* Routines implemented in loongarch.c. */ ++/* Routines implemented in loongarch.cc. */ + extern rtx loongarch_emit_move (rtx, rtx); + extern HOST_WIDE_INT loongarch_initial_elimination_offset (int, int); + extern void loongarch_expand_prologue (void); +@@ -163,6 +163,8 @@ extern const char *current_section_name (void); + extern unsigned int current_section_flags (void); + extern bool loongarch_use_ins_ext_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT); + extern bool loongarch_check_zero_div_p (void); ++extern bool loongarch_pre_reload_split (void); ++extern int loongarch_use_bstrins_for_ior_with_mask (machine_mode, rtx *); + + union loongarch_gen_fn_ptrs + { +diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc +index dae35a479..4b0944d56 100644 +--- a/gcc/config/loongarch/loongarch.cc ++++ b/gcc/config/loongarch/loongarch.cc +@@ -5478,6 +5478,42 @@ loongarch_use_ins_ext_p (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos) + return true; + } + ++/* Predicate for pre-reload splitters with associated instructions, ++ which can match any time before the split1 pass (usually combine), ++ then are unconditionally split in that pass and should not be ++ matched again afterwards. */ ++ ++bool loongarch_pre_reload_split (void) ++{ ++ return (can_create_pseudo_p () ++ && !(cfun->curr_properties & PROP_rtl_split_insns)); ++} ++ ++/* Check if we can use bstrins.<d> for ++ op0 = (op1 & op2) | (op3 & op4) ++ where op0, op1, op3 are regs, and op2, op4 are integer constants. */ ++int ++loongarch_use_bstrins_for_ior_with_mask (machine_mode mode, rtx *op) ++{ ++ unsigned HOST_WIDE_INT mask1 = UINTVAL (op2); ++ unsigned HOST_WIDE_INT mask2 = UINTVAL (op4); ++ ++ if (mask1 != ~mask2 || !mask1 || !mask2) ++ return 0; ++ ++ /* Try to avoid a right-shift. */ ++ if (low_bitmask_len (mode, mask1) != -1) ++ return -1; ++ ++ if (low_bitmask_len (mode, mask2 >> (ffs_hwi (mask2) - 1)) != -1) ++ return 1; ++ ++ if (low_bitmask_len (mode, mask1 >> (ffs_hwi (mask1) - 1)) != -1) ++ return -1; ++ ++ return 0; ++} ++ + /* Print the text for PRINT_OPERAND punctation character CH to FILE. + The punctuation characters are: + +diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md +index 3dde0ceb1..11c18bf15 100644 +--- a/gcc/config/loongarch/loongarch.md ++++ b/gcc/config/loongarch/loongarch.md +@@ -1322,6 +1322,97 @@ + (set_attr "move_type" "pick_ins") + (set_attr "mode" "<MODE>")) + ++(define_insn_and_split "*bstrins_<mode>_for_mask" ++ (set (match_operand:GPR 0 "register_operand") ++ (and:GPR (match_operand:GPR 1 "register_operand") ++ (match_operand:GPR 2 "ins_zero_bitmask_operand"))) ++ "" ++ "#" ++ "" ++ (set (match_dup 0) (match_dup 1)) ++ (set (zero_extract:GPR (match_dup 0) (match_dup 2) (match_dup 3)) ++ (const_int 0)) ++ { ++ unsigned HOST_WIDE_INT mask = ~UINTVAL (operands2); ++ int lo = ffs_hwi (mask) - 1; ++ int len = low_bitmask_len (<MODE>mode, mask >> lo); ++ ++ len = MIN (len, GET_MODE_BITSIZE (<MODE>mode) - lo); ++ operands2 = GEN_INT (len); ++ operands3 = GEN_INT (lo); ++ }) ++ ++(define_insn_and_split "*bstrins_<mode>_for_ior_mask" ++ (set (match_operand:GPR 0 "register_operand") ++ (ior:GPR (and:GPR (match_operand:GPR 1 "register_operand") ++ (match_operand:GPR 2 "const_int_operand")) ++ (and:GPR (match_operand:GPR 3 "register_operand") ++ (match_operand:GPR 4 "const_int_operand")))) ++ "loongarch_pre_reload_split () && \ ++ loongarch_use_bstrins_for_ior_with_mask (<MODE>mode, operands)" ++ "#" ++ "" ++ (set (match_dup 0) (match_dup 1)) ++ (set (zero_extract:GPR (match_dup 0) (match_dup 2) (match_dup 4)) ++ (match_dup 3)) ++ { ++ if (loongarch_use_bstrins_for_ior_with_mask (<MODE>mode, operands) < 0) ++ { ++ std::swap (operands1, operands3); ++ std::swap (operands2, operands4); ++ } ++ ++ unsigned HOST_WIDE_INT mask = ~UINTVAL (operands2); ++ int lo = ffs_hwi (mask) - 1; ++ int len = low_bitmask_len (<MODE>mode, mask >> lo); ++ ++ len = MIN (len, GET_MODE_BITSIZE (<MODE>mode) - lo); ++ operands2 = GEN_INT (len); ++ operands4 = GEN_INT (lo); ++ ++ if (lo) ++ { ++ rtx tmp = gen_reg_rtx (<MODE>mode); ++ emit_move_insn (tmp, gen_rtx_ASHIFTRT(<MODE>mode, operands3, ++ GEN_INT (lo))); ++ operands3 = tmp; ++ } ++ }) ++ ++;; We always avoid the shift operation in bstrins_<mode>_for_ior_mask ++;; if possible, but the result may be sub-optimal when one of the masks ++;; is (1 << N) - 1 and one of the src register is the dest register. ++;; For example: ++;; move t0, a0 ++;; move a0, a1 ++;; bstrins.d a0, t0, 42, 0 ++;; ret ++;; using a shift operation would be better: ++;; srai.d t0, a1, 43 ++;; bstrins.d a0, t0, 63, 43 ++;; ret ++;; unfortunately we cannot figure it out in split1: before reload we cannot ++;; know if the dest register is one of the src register. Fix it up in ++;; peephole2. ++(define_peephole2 ++ (set (match_operand:GPR 0 "register_operand") ++ (match_operand:GPR 1 "register_operand")) ++ (set (match_dup 1) (match_operand:GPR 2 "register_operand")) ++ (set (zero_extract:GPR (match_dup 1) ++ (match_operand:SI 3 "const_int_operand")
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_service:tar_scm:LoongArch-add-mdirect-extern-access-option.patch
Added
@@ -0,0 +1,157 @@ +From 22f6d3fad184d87f3dac7634537fdbc24846bab9 Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao <xry111@xry111.site> +Date: Thu, 1 Sep 2022 18:38:14 +0800 +Subject: PATCH 016/124 LoongArch: add -mdirect-extern-access option + +As a new target, LoongArch does not use copy relocation as it's +problematic in some circumstances. One bad consequence is we are +emitting GOT for all accesses to all extern objects with default +visibility. The use of GOT is not needed in statically linked +executables, OS kernels etc. The GOT entry just wastes space, and the +GOT access just slow down the execution in those environments. + +Before -mexplicit-relocs, we used "-Wa,-mla-global-with-pcrel" to tell +the assembler not to use GOT for extern access. But with +-mexplicit-relocs, we have to opt the logic in GCC. + +The name "-mdirect-extern-access" is learnt from x86 port. + +gcc/ChangeLog: + + * config/loongarch/genopts/loongarch.opt.in: Add + -mdirect-extern-access option. + * config/loongarch/loongarch.opt: Regenerate. + * config/loongarch/loongarch.cc + (loongarch_symbol_binds_local_p): Return true if + TARGET_DIRECT_EXTERN_ACCESS. + (loongarch_option_override_internal): Complain if + -mdirect-extern-access is used with -fPIC or -fpic. + * doc/invoke.texi: Document -mdirect-extern-access for + LoongArch. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/direct-extern-1.c: New test. + * gcc.target/loongarch/direct-extern-2.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/genopts/loongarch.opt.in | 4 ++++ + gcc/config/loongarch/loongarch.cc | 6 ++++++ + gcc/config/loongarch/loongarch.opt | 4 ++++ + gcc/doc/invoke.texi | 15 +++++++++++++++ + .../gcc.target/loongarch/direct-extern-1.c | 6 ++++++ + .../gcc.target/loongarch/direct-extern-2.c | 6 ++++++ + 6 files changed, 41 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/loongarch/direct-extern-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/direct-extern-2.c + +diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in b/gcc/config/loongarch/genopts/loongarch.opt.in +index ebdd9538d..e10618777 100644 +--- a/gcc/config/loongarch/genopts/loongarch.opt.in ++++ b/gcc/config/loongarch/genopts/loongarch.opt.in +@@ -184,3 +184,7 @@ Enum(cmodel) String(@@STR_CMODEL_EXTREME@@) Value(CMODEL_EXTREME) + mcmodel= + Target RejectNegative Joined Enum(cmodel) Var(la_opt_cmodel) Init(CMODEL_NORMAL) + Specify the code model. ++ ++mdirect-extern-access ++Target Var(TARGET_DIRECT_EXTERN_ACCESS) Init(0) ++Avoid using the GOT to access external symbols. +diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc +index 77e3a1053..c9187bf81 100644 +--- a/gcc/config/loongarch/loongarch.cc ++++ b/gcc/config/loongarch/loongarch.cc +@@ -1610,6 +1610,9 @@ loongarch_weak_symbol_p (const_rtx x) + bool + loongarch_symbol_binds_local_p (const_rtx x) + { ++ if (TARGET_DIRECT_EXTERN_ACCESS) ++ return true; ++ + if (SYMBOL_REF_P (x)) + return (SYMBOL_REF_DECL (x) + ? targetm.binds_local_p (SYMBOL_REF_DECL (x)) +@@ -6093,6 +6096,9 @@ loongarch_option_override_internal (struct gcc_options *opts) + if (loongarch_branch_cost == 0) + loongarch_branch_cost = loongarch_cost->branch_cost; + ++ if (TARGET_DIRECT_EXTERN_ACCESS && flag_shlib) ++ error ("%qs cannot be used for compiling a shared library", ++ "-mdirect-extern-access"); + + switch (la_target.cmodel) + { +diff --git a/gcc/config/loongarch/loongarch.opt b/gcc/config/loongarch/loongarch.opt +index 639523421..96c811c85 100644 +--- a/gcc/config/loongarch/loongarch.opt ++++ b/gcc/config/loongarch/loongarch.opt +@@ -191,3 +191,7 @@ Enum(cmodel) String(extreme) Value(CMODEL_EXTREME) + mcmodel= + Target RejectNegative Joined Enum(cmodel) Var(la_opt_cmodel) Init(CMODEL_NORMAL) + Specify the code model. ++ ++mdirect-extern-access ++Target Var(TARGET_DIRECT_EXTERN_ACCESS) Init(0) ++Avoid using the GOT to access external symbols. +diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi +index 2a5592516..9ec937b84 100644 +--- a/gcc/doc/invoke.texi ++++ b/gcc/doc/invoke.texi +@@ -1007,6 +1007,7 @@ Objective-C and Objective-C++ Dialects}. + -memcpy -mno-memcpy -mstrict-align -mno-strict-align @gol + -mmax-inline-memcpy-size=@var{n} @gol + -mexplicit-relocs -mno-explicit-relocs @gol ++-mdirect-extern-access -mno-direct-extern-access @gol + -mcmodel=@var{code-model}} + + @emph{M32R/D Options} +@@ -24649,6 +24650,20 @@ GCC build-time by detecting corresponding assembler support: + @code{-mno-explicit-relocs} otherwise. This option is mostly useful for + debugging, or interoperation with assemblers different from the build-time + one. ++ ++@item -mdirect-extern-access ++@itemx -mno-direct-extern-access ++@opindex mdirect-extern-access ++Do not use or use GOT to access external symbols. The default is ++@option{-mno-direct-extern-access}: GOT is used for external symbols with ++default visibility, but not used for other external symbols. ++ ++With @option{-mdirect-extern-access}, GOT is not used and all external ++symbols are PC-relatively addressed. It is @strong{only} suitable for ++environments where no dynamic link is performed, like firmwares, OS ++kernels, executables linked with @option{-static} or @option{-static-pie}. ++@option{-mdirect-extern-access} is not compatible with @option{-fPIC} or ++@option{-fpic}. + @end table + + @node M32C Options +diff --git a/gcc/testsuite/gcc.target/loongarch/direct-extern-1.c b/gcc/testsuite/gcc.target/loongarch/direct-extern-1.c +new file mode 100644 +index 000000000..85c6c1e8a +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/direct-extern-1.c +@@ -0,0 +1,6 @@ ++/* { dg-do compile } */ ++/* { dg-options "-mexplicit-relocs -mdirect-extern-access" } */ ++/* { dg-final { scan-assembler-not "got" } } */ ++ ++extern int x; ++int f() { return x; } +diff --git a/gcc/testsuite/gcc.target/loongarch/direct-extern-2.c b/gcc/testsuite/gcc.target/loongarch/direct-extern-2.c +new file mode 100644 +index 000000000..58d8bd68a +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/direct-extern-2.c +@@ -0,0 +1,6 @@ ++/* { dg-do compile } */ ++/* { dg-options "-mno-explicit-relocs -mdirect-extern-access" } */ ++/* { dg-final { scan-assembler-not "la.global" } } */ ++ ++extern int x; ++int f() { return x; } +-- +2.33.0 +
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_service:tar_scm:LoongArch-add-model-attribute.patch
Added
@@ -0,0 +1,477 @@ +From 859ed9ee2dc28b98e11b2bfdeabb0bda7dc921b0 Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao <xry111@xry111.site> +Date: Fri, 29 Jul 2022 21:45:40 +0800 +Subject: PATCH 014/124 LoongArch: add model attribute + +A linker script and/or a section attribute may locate some object +specially, so we need to handle the code model for such objects +differently than the -mcmodel setting. This happens when the Linux +kernel loads a module with per-CPU variables. + +Add an attribute to override the code model for a specific variable. + +gcc/ChangeLog: + + * config/loongarch/loongarch-protos.h (loongarch_symbol_type): + Add SYMBOL_PCREL64 and change the description for SYMBOL_PCREL. + * config/loongarch/loongarch.cc (loongarch_attribute_table): + New attribute table. + (TARGET_ATTRIBUTE_TABLE): Define the target hook. + (loongarch_handle_model_attribute): New static function. + (loongarch_classify_symbol): Take TARGET_CMODEL_EXTREME and the + model attribute of SYMBOL_REF_DECL into account returning + SYMBOL_PCREL or SYMBOL_PCREL64. + (loongarch_use_anchors_for_symbol_p): New static function. + (TARGET_USE_ANCHORS_FOR_SYMBOL_P): Define the target hook. + (loongarch_symbol_extreme_p): New static function. + (loongarch_symbolic_constant_p): Handle SYMBOL_PCREL64. + (loongarch_symbol_insns): Likewise. + (loongarch_split_symbol_type): Likewise. + (loongarch_split_symbol): Check SYMBOL_PCREL64 instead of + TARGET_CMODEL_EXTREME for PC-relative addressing. + (loongarch_print_operand_reloc): Likewise. + * doc/extend.texi (Variable Attributes): Document new + LoongArch specific attribute. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/attr-model-test.c: New test. + * gcc.target/loongarch/attr-model-1.c: New test. + * gcc.target/loongarch/attr-model-2.c: New test. + * gcc.target/loongarch/attr-model-diag.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/loongarch-protos.h | 8 +- + gcc/config/loongarch/loongarch.cc | 190 ++++++++++++++++-- + gcc/doc/extend.texi | 17 ++ + .../gcc.target/loongarch/attr-model-1.c | 6 + + .../gcc.target/loongarch/attr-model-2.c | 6 + + .../gcc.target/loongarch/attr-model-diag.c | 7 + + .../gcc.target/loongarch/attr-model-test.c | 25 +++ + 7 files changed, 238 insertions(+), 21 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/loongarch/attr-model-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/attr-model-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/attr-model-diag.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/attr-model-test.c + +diff --git a/gcc/config/loongarch/loongarch-protos.h b/gcc/config/loongarch/loongarch-protos.h +index cadaad751..77b221724 100644 +--- a/gcc/config/loongarch/loongarch-protos.h ++++ b/gcc/config/loongarch/loongarch-protos.h +@@ -28,7 +28,12 @@ along with GCC; see the file COPYING3. If not see + The symbol's value will be loaded directly from the GOT. + + SYMBOL_PCREL +- The symbol's value will be loaded directly from data section. ++ The symbol's value will be loaded directly from data section within ++ +/- 2GiB range. ++ ++ SYMBOL_PCREL64 ++ The symbol's value will be loaded directly from data section within ++ +/- 8EiB range. + + SYMBOL_TLS + A thread-local symbol. +@@ -42,6 +47,7 @@ along with GCC; see the file COPYING3. If not see + enum loongarch_symbol_type { + SYMBOL_GOT_DISP, + SYMBOL_PCREL, ++ SYMBOL_PCREL64, + SYMBOL_TLS, + SYMBOL_TLS_IE, + SYMBOL_TLS_LE, +diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc +index 452aba9d4..77e3a1053 100644 +--- a/gcc/config/loongarch/loongarch.cc ++++ b/gcc/config/loongarch/loongarch.cc +@@ -1633,8 +1633,11 @@ loongarch_rtx_constant_in_small_data_p (machine_mode mode) + static enum loongarch_symbol_type + loongarch_classify_symbol (const_rtx x) + { ++ enum loongarch_symbol_type pcrel = ++ TARGET_CMODEL_EXTREME ? SYMBOL_PCREL64 : SYMBOL_PCREL; ++ + if (!SYMBOL_REF_P (x)) +- return SYMBOL_PCREL; ++ return pcrel; + + if (SYMBOL_REF_TLS_MODEL (x)) + return SYMBOL_TLS; +@@ -1642,7 +1645,28 @@ loongarch_classify_symbol (const_rtx x) + if (!loongarch_symbol_binds_local_p (x)) + return SYMBOL_GOT_DISP; + +- return SYMBOL_PCREL; ++ tree t = SYMBOL_REF_DECL (x); ++ if (!t) ++ return pcrel; ++ ++ t = lookup_attribute ("model", DECL_ATTRIBUTES (t)); ++ if (!t) ++ return pcrel; ++ ++ t = TREE_VALUE (TREE_VALUE (t)); ++ ++ /* loongarch_handle_model_attribute should reject other values. */ ++ gcc_assert (TREE_CODE (t) == STRING_CST); ++ ++ const char *model = TREE_STRING_POINTER (t); ++ if (strcmp (model, "normal") == 0) ++ return SYMBOL_PCREL; ++ if (strcmp (model, "extreme") == 0) ++ return SYMBOL_PCREL64; ++ ++ /* loongarch_handle_model_attribute should reject unknown model ++ name. */ ++ gcc_unreachable (); + } + + /* Classify the base of symbolic expression X, given that X appears in +@@ -1695,6 +1719,7 @@ loongarch_symbolic_constant_p (rtx x, enum loongarch_symbol_type *symbol_type) + case SYMBOL_TLSGD: + case SYMBOL_TLSLDM: + case SYMBOL_PCREL: ++ case SYMBOL_PCREL64: + /* GAS rejects offsets outside the range -2^31, 2^31-1. */ + return sext_hwi (INTVAL (offset), 32) == INTVAL (offset); + +@@ -1729,6 +1754,9 @@ loongarch_symbol_insns (enum loongarch_symbol_type type, machine_mode mode) + case SYMBOL_TLSLDM: + return 3; + ++ case SYMBOL_PCREL64: ++ return 5; ++ + case SYMBOL_TLS: + /* We don't treat a bare TLS symbol as a constant. */ + return 0; +@@ -1833,7 +1861,7 @@ loongarch_valid_offset_p (rtx x, machine_mode mode) + return true; + } + +-/* Should a symbol of type SYMBOL_TYPE should be split in two? */ ++/* Should a symbol of type SYMBOL_TYPE should be split in two or more? */ + + bool + loongarch_split_symbol_type (enum loongarch_symbol_type symbol_type) +@@ -1841,6 +1869,7 @@ loongarch_split_symbol_type (enum loongarch_symbol_type symbol_type) + switch (symbol_type) + { + case SYMBOL_PCREL: ++ case SYMBOL_PCREL64: + case SYMBOL_GOT_DISP: + case SYMBOL_TLS_IE: + case SYMBOL_TLS_LE: +@@ -2718,6 +2747,20 @@ loongarch_force_address (rtx x, machine_mode mode) + return x; + } + ++static bool ++loongarch_symbol_extreme_p (enum loongarch_symbol_type type) ++{ ++ switch (type) ++ { ++ case SYMBOL_PCREL: ++ return false; ++ case SYMBOL_PCREL64: ++ return true; ++ default: ++ return TARGET_CMODEL_EXTREME; ++ } ++} ++ + /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise + it appears in a MEM of that mode. Return true if ADDR is a legitimate + constant in that context and can be split into high and low parts. +@@ -2757,7 +2800,7 @@ loongarch_split_symbol (rtx temp, rtx addr, machine_mode mode, rtx *low_out) + high = gen_rtx_HIGH (Pmode, copy_rtx (addr)); + high = loongarch_force_temporary (temp, high); + +- if (TARGET_CMODEL_EXTREME && can_create_pseudo_p ()) ++ if (loongarch_symbol_extreme_p (symbol_type) && can_create_pseudo_p ()) + { + gcc_assert (TARGET_EXPLICIT_RELOCS); + +@@ -2771,14 +2814,16 @@ loongarch_split_symbol (rtx temp, rtx addr, machine_mode mode, rtx *low_out) + if (low_out) + switch (symbol_type)
View file
_service:tar_scm:LoongArch-add-new-configure-option-with-strict-align.patch
Added
@@ -0,0 +1,86 @@ +From da22606529688b125e6e08589a6dfe741b8dd18d Mon Sep 17 00:00:00 2001 +From: Yang Yujie <yangyujie@loongson.cn> +Date: Mon, 28 Aug 2023 10:20:12 +0800 +Subject: PATCH 060/124 LoongArch: add new configure option + --with-strict-align-lib + +LoongArch processors may not support memory accesses without natural +alignments. Building libraries with -mstrict-align may help with +toolchain binary compatiblity and performance on these implementations +(e.g. Loongson 2K1000LA). + +No significant performance degredation is observed on current mainstream +LoongArch processors when the option is enabled. + +gcc/ChangeLog: + + * config.gcc: use -mstrict-align for building libraries + if --with-strict-align-lib is given. + * doc/install.texi: likewise. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config.gcc | 16 +++++++++++++++- + gcc/doc/install.texi | 4 ++++ + 2 files changed, 19 insertions(+), 1 deletion(-) + +diff --git a/gcc/config.gcc b/gcc/config.gcc +index 62525c296..16bbaea45 100644 +--- a/gcc/config.gcc ++++ b/gcc/config.gcc +@@ -4966,7 +4966,7 @@ case "${target}" in + ;; + + loongarch*-*) +- supported_defaults="abi arch tune fpu simd multilib-default" ++ supported_defaults="abi arch tune fpu simd multilib-default strict-align-lib" + + # Local variables + unset \ +@@ -5163,6 +5163,17 @@ case "${target}" in + ;; + esac + ++ # Build libraries with -mstrict-align if --with-strict-align-lib is given. ++ case ${with_strict_align_lib} in ++ yes) strict_align_opt="/mstrict-align" ;; ++ ""|no) ;; ++ *) ++ echo "Unknown option: --with-strict-align-lib=${with_strict_align_lib}" 1>&2 ++ exit 1 ++ ;; ++ esac ++ ++ + # Handle --with-multilib-default + if echo "${with_multilib_default}" \ + | grep -E -e ':space:' -e '//' -e '/$' -e '^/' > /dev/null 2>&1; then +@@ -5324,6 +5335,9 @@ case "${target}" in + ;; + esac + ++ # Use mstrict-align for building libraries if --with-strict-align-lib is given. ++ loongarch_multilib_list_make="${loongarch_multilib_list_make}${strict_align_opt}" ++ + # Check for repeated configuration of the same multilib variant. + if echo "${elem_abi_base}/${elem_abi_ext}" \ + | grep -E "^(${all_abis%|})$" >/dev/null 2>&1; then +diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi +index 1fc5f0bfa..a8851e8bd 100644 +--- a/gcc/doc/install.texi ++++ b/gcc/doc/install.texi +@@ -1353,6 +1353,10 @@ Multiple @var{option}s may appear consecutively while @var{arch} may only + appear in the beginning or be omitted (which means @option{-march=abi-default} + is applied when building the libraries). + ++@item --with-strict-align-lib ++On LoongArch targets, build all enabled multilibs with @option{-mstrict-align} ++(Not enabled by default). ++ + @item --with-multilib-generator=@var{config} + Specify what multilibs to build. @var{config} is a semicolon separated list of + values, possibly consisting of a single value. Currently only implemented +-- +2.33.0 +
View file
_service:tar_scm:LoongArch-adjust-the-default-of-mexplicit-relocs-by-.patch
Added
@@ -0,0 +1,149 @@ +From aa10a2949c86e46b7952acbb58599e9bfdeabdfb Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao <xry111@xry111.site> +Date: Tue, 26 Jul 2022 21:46:20 +0800 +Subject: PATCH 006/124 LoongArch: adjust the default of -mexplicit-relocs by + checking gas feature + +The assembly produced with -mexplicit-relocs is not supported by gas <= +2.39. Check if the assembler supports explicit relocations and set the +default accordingly. + +gcc/ChangeLog: + + * configure.ac (HAVE_AS_EXPLICIT_RELOCS): Define to 1 if the + assembler supports explicit relocation for LoongArch. + * configure: Regenerate. + * config/loongarch/loongarch-opts.h (HAVE_AS_EXPLICIT_RELOCS): + Define to 0 if not defined. + * config/loongarch/genopts/loongarch.opt.in + (TARGET_EXPLICIT_RELOCS): Default to HAVE_AS_EXPLICIT_RELOCS. + * config/loongarch/loongarch.opt: Regenerate. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/genopts/loongarch.opt.in | 2 +- + gcc/config/loongarch/loongarch-opts.h | 4 +++ + gcc/config/loongarch/loongarch.opt | 2 +- + gcc/configure | 33 ++++++++++++++++++- + gcc/configure.ac | 7 +++- + 5 files changed, 44 insertions(+), 4 deletions(-) + +diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in b/gcc/config/loongarch/genopts/loongarch.opt.in +index 6f3950093..a571b6b75 100644 +--- a/gcc/config/loongarch/genopts/loongarch.opt.in ++++ b/gcc/config/loongarch/genopts/loongarch.opt.in +@@ -155,7 +155,7 @@ Target Joined RejectNegative UInteger Var(loongarch_max_inline_memcpy_size) Init + -mmax-inline-memcpy-size=SIZE Set the max size of memcpy to inline, default is 1024. + + mexplicit-relocs +-Target Var(TARGET_EXPLICIT_RELOCS) Init(1) ++Target Var(TARGET_EXPLICIT_RELOCS) Init(HAVE_AS_EXPLICIT_RELOCS) + Use %reloc() assembly operators. + + ; The code model option names for -mcmodel. +diff --git a/gcc/config/loongarch/loongarch-opts.h b/gcc/config/loongarch/loongarch-opts.h +index eaa6fc074..da24ecd2b 100644 +--- a/gcc/config/loongarch/loongarch-opts.h ++++ b/gcc/config/loongarch/loongarch-opts.h +@@ -87,4 +87,8 @@ loongarch_config_target (struct loongarch_target *target, + while -mno-memcpy imposes a global constraint. */ + #define TARGET_DO_OPTIMIZE_BLOCK_MOVE_P loongarch_do_optimize_block_move_p() + ++#ifndef HAVE_AS_EXPLICIT_RELOCS ++#define HAVE_AS_EXPLICIT_RELOCS 0 ++#endif ++ + #endif /* LOONGARCH_OPTS_H */ +diff --git a/gcc/config/loongarch/loongarch.opt b/gcc/config/loongarch/loongarch.opt +index 7a8c5b444..9df7e1872 100644 +--- a/gcc/config/loongarch/loongarch.opt ++++ b/gcc/config/loongarch/loongarch.opt +@@ -162,7 +162,7 @@ Target Joined RejectNegative UInteger Var(loongarch_max_inline_memcpy_size) Init + -mmax-inline-memcpy-size=SIZE Set the max size of memcpy to inline, default is 1024. + + mexplicit-relocs +-Target Var(TARGET_EXPLICIT_RELOCS) Init(1) ++Target Var(TARGET_EXPLICIT_RELOCS) Init(HAVE_AS_EXPLICIT_RELOCS) + Use %reloc() assembly operators. + + ; The code model option names for -mcmodel. +diff --git a/gcc/configure b/gcc/configure +index 98bbf0f85..840eddc7c 100755 +--- a/gcc/configure ++++ b/gcc/configure +@@ -28792,7 +28792,7 @@ $as_echo "#define HAVE_AS_MARCH_ZIFENCEI 1" >>confdefs.h + fi + + ;; +- loongarch*-*-*) ++ loongarch*-*-*) + { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for .dtprelword support" >&5 + $as_echo_n "checking assembler for .dtprelword support... " >&6; } + if ${gcc_cv_as_loongarch_dtprelword+:} false; then : +@@ -28828,6 +28828,37 @@ if test $gcc_cv_as_loongarch_dtprelword != yes; then + $as_echo "#define HAVE_AS_DTPRELWORD 1" >>confdefs.h + + fi ++ { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for explicit relocation support" >&5 ++$as_echo_n "checking assembler for explicit relocation support... " >&6; } ++if ${gcc_cv_as_loongarch_explicit_relocs+:} false; then : ++ $as_echo_n "(cached) " >&6 ++else ++ gcc_cv_as_loongarch_explicit_relocs=no ++ if test x$gcc_cv_as != x; then ++ $as_echo 'a:pcalau12i $t0,%pc_hi20(a)' > conftest.s ++ if { ac_try='$gcc_cv_as $gcc_cv_as_flags -o conftest.o conftest.s >&5' ++ { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5 ++ (eval $ac_try) 2>&5 ++ ac_status=$? ++ $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 ++ test $ac_status = 0; }; } ++ then ++ gcc_cv_as_loongarch_explicit_relocs=yes ++ else ++ echo "configure: failed program was" >&5 ++ cat conftest.s >&5 ++ fi ++ rm -f conftest.o conftest.s ++ fi ++fi ++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_loongarch_explicit_relocs" >&5 ++$as_echo "$gcc_cv_as_loongarch_explicit_relocs" >&6; } ++if test $gcc_cv_as_loongarch_explicit_relocs = yes; then ++ ++$as_echo "#define HAVE_AS_EXPLICIT_RELOCS 1" >>confdefs.h ++ ++fi ++ + ;; + s390*-*-*) + { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for .gnu_attribute support" >&5 +diff --git a/gcc/configure.ac b/gcc/configure.ac +index c74f4b555..975c852c6 100644 +--- a/gcc/configure.ac ++++ b/gcc/configure.ac +@@ -5309,7 +5309,7 @@ configured with --enable-newlib-nano-formatted-io.) + AC_DEFINE(HAVE_AS_MARCH_ZIFENCEI, 1, + Define if the assembler understands -march=rv*_zifencei.)) + ;; +- loongarch*-*-*) ++ loongarch*-*-*) + gcc_GAS_CHECK_FEATURE(.dtprelword support, + gcc_cv_as_loongarch_dtprelword, 2,18,0,, + .section .tdata,"awT",@progbits +@@ -5319,6 +5319,11 @@ x: + .dtprelword x+0x8000,, + AC_DEFINE(HAVE_AS_DTPRELWORD, 1, + Define if your assembler supports .dtprelword.)) ++ gcc_GAS_CHECK_FEATURE(explicit relocation support, ++ gcc_cv_as_loongarch_explicit_relocs,, ++ a:pcalau12i $t0,%pc_hi20(a),, ++ AC_DEFINE(HAVE_AS_EXPLICIT_RELOCS, 1, ++ Define if your assembler supports explicit relocation.)) + ;; + s390*-*-*) + gcc_GAS_CHECK_FEATURE(.gnu_attribute support, +-- +2.33.0 +
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_service:tar_scm:LoongArch-define-preprocessing-macros-__loongarch_-a.patch
Added
@@ -0,0 +1,42 @@ +From 41b01fb34126d8b40635af1847b21716f62e5388 Mon Sep 17 00:00:00 2001 +From: Yang Yujie <yangyujie@loongson.cn> +Date: Mon, 28 Aug 2023 09:32:16 +0800 +Subject: PATCH 059/124 LoongArch: define preprocessing macros + "__loongarch_{arch,tune}" + +These are exported according to the LoongArch Toolchain Conventions1 +as a replacement of the obsolete "_LOONGARCH_{ARCH,TUNE}" macros, +which are expanded to strings representing the actual architecture +and microarchitecture of the target. + +1 currently relased at https://github.com/loongson/LoongArch-Documentation + /blob/main/docs/LoongArch-toolchain-conventions-EN.adoc + +gcc/ChangeLog: + + * config/loongarch/loongarch-c.cc: Export macros + "__loongarch_{arch,tune}" in the preprocessor. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/loongarch-c.cc | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/gcc/config/loongarch/loongarch-c.cc b/gcc/config/loongarch/loongarch-c.cc +index 2cf84eec7..c9b11a042 100644 +--- a/gcc/config/loongarch/loongarch-c.cc ++++ b/gcc/config/loongarch/loongarch-c.cc +@@ -64,6 +64,9 @@ loongarch_cpu_cpp_builtins (cpp_reader *pfile) + LARCH_CPP_SET_PROCESSOR ("_LOONGARCH_ARCH", la_target.cpu_arch); + LARCH_CPP_SET_PROCESSOR ("_LOONGARCH_TUNE", la_target.cpu_tune); + ++ LARCH_CPP_SET_PROCESSOR ("__loongarch_arch", la_target.cpu_arch); ++ LARCH_CPP_SET_PROCESSOR ("__loongarch_tune", la_target.cpu_tune); ++ + /* Base architecture / ABI. */ + if (TARGET_64BIT) + { +-- +2.33.0 +
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_service:tar_scm:LoongArch-document-m-no-explicit-relocs.patch
Added
@@ -0,0 +1,43 @@ +From 3742550e00bf0401ead01cde64fc1571ffa075fc Mon Sep 17 00:00:00 2001 +From: WANG Xuerui <i@xen0n.name> +Date: Wed, 27 Jul 2022 15:01:17 +0800 +Subject: PATCH 007/124 LoongArch: document -mno-explicit-relocs + +gcc/ChangeLog: + + * doc/invoke.texi: Document -mno-explicit-relocs for + LoongArch. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/doc/invoke.texi | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi +index 2b376e0e9..1de2b2bd4 100644 +--- a/gcc/doc/invoke.texi ++++ b/gcc/doc/invoke.texi +@@ -24663,6 +24663,19 @@ global symbol: The data got table must be within +/-8EiB addressing space. + @end itemize + @end table + The default code model is @code{normal}. ++ ++@item -mexplicit-relocs ++@itemx -mno-explicit-relocs ++@opindex mexplicit-relocs ++@opindex mno-explicit-relocs ++Use or do not use assembler relocation operators when dealing with symbolic ++addresses. The alternative is to use assembler macros instead, which may ++limit optimization. The default value for the option is determined during ++GCC build-time by detecting corresponding assembler support: ++@code{-mexplicit-relocs} if said support is present, ++@code{-mno-explicit-relocs} otherwise. This option is mostly useful for ++debugging, or interoperation with assemblers different from the build-time ++one. + @end table + + @node M32C Options +-- +2.33.0 +
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_service:tar_scm:LoongArch-fix-error-building.patch
Added
@@ -0,0 +1,183 @@ +diff --git a/gcc/config/loongarch/loongarch-builtins.cc b/gcc/config/loongarch/loongarch-builtins.cc +index a4a7dbec9..2d9743d86 100644 +--- a/gcc/config/loongarch/loongarch-builtins.cc ++++ b/gcc/config/loongarch/loongarch-builtins.cc +@@ -2440,11 +2440,6 @@ loongarch_init_builtins (void) + unsigned int i; + tree type; + +- /* Register the type float128_type_node as a built-in type and +- give it an alias "__float128". */ +- (*lang_hooks.types.register_builtin_type) (float128_type_node, +- "__float128"); +- + /* Iterate through all of the bdesc arrays, initializing all of the + builtin functions. */ + for (i = 0; i < ARRAY_SIZE (loongarch_builtins); i++) +diff --git a/gcc/config/loongarch/loongarch-c.cc b/gcc/config/loongarch/loongarch-c.cc +index c9b11a042..76c8ea8db 100644 +--- a/gcc/config/loongarch/loongarch-c.cc ++++ b/gcc/config/loongarch/loongarch-c.cc +@@ -117,17 +117,6 @@ loongarch_cpu_cpp_builtins (cpp_reader *pfile) + builtin_define ("__loongarch_simd_width=256"); + } + +- /* Add support for FLOAT128_TYPE on the LoongArch architecture. */ +- builtin_define ("__FLOAT128_TYPE__"); +- +- /* Map the old _Float128 'q' builtins into the new 'f128' builtins. */ +- builtin_define ("__builtin_fabsq=__builtin_fabsf128"); +- builtin_define ("__builtin_copysignq=__builtin_copysignf128"); +- builtin_define ("__builtin_nanq=__builtin_nanf128"); +- builtin_define ("__builtin_nansq=__builtin_nansf128"); +- builtin_define ("__builtin_infq=__builtin_inff128"); +- builtin_define ("__builtin_huge_valq=__builtin_huge_valf128"); +- + /* Native Data Sizes. */ + builtin_define_with_int_value ("_LOONGARCH_SZINT", INT_TYPE_SIZE); + builtin_define_with_int_value ("_LOONGARCH_SZLONG", LONG_TYPE_SIZE); +diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc +index baa9831aa..ae074edbd 100644 +--- a/gcc/config/loongarch/loongarch.cc ++++ b/gcc/config/loongarch/loongarch.cc +@@ -9712,13 +9712,10 @@ expand_perm_const_2_end: + /* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */ + + static bool +-loongarch_vectorize_vec_perm_const (machine_mode vmode, machine_mode op_mode, ++loongarch_vectorize_vec_perm_const (machine_mode vmode, + rtx target, rtx op0, rtx op1, + const vec_perm_indices &sel) + { +- if (vmode != op_mode) +- return false; +- + struct expand_vec_perm_d d; + int i, nelt, which; + unsigned char orig_permMAX_VECT_LEN; +diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi +index bb19d0f27..1d1bac255 100644 +--- a/gcc/doc/extend.texi ++++ b/gcc/doc/extend.texi +@@ -1085,10 +1085,10 @@ types. + As an extension, GNU C and GNU C++ support additional floating + types, which are not supported by all targets. + @itemize @bullet +-@item @code{__float128} is available on i386, x86_64, IA-64, LoongArch +-and hppa HP-UX, as well as on PowerPC GNU/Linux targets that enable ++@item @code{__float128} is available on i386, x86_64, IA-64, and ++hppa HP-UX, as well as on PowerPC GNU/Linux targets that enable + the vector scalar (VSX) instruction set. @code{__float128} supports +-the 128-bit floating type. On i386, x86_64, PowerPC, LoongArch and IA-64, ++the 128-bit floating type. On i386, x86_64, PowerPC, and IA-64 + other than HP-UX, @code{__float128} is an alias for @code{_Float128}. + On hppa and IA-64 HP-UX, @code{__float128} is an alias for @code{long + double}. +@@ -16257,20 +16257,6 @@ function you need to include @code{larchintrin.h}. + void __break (imm0_32767) + @end smallexample + +-Additional built-in functions are available for LoongArch family +-processors to efficiently use 128-bit floating-point (__float128) +-values. +- +-The following are the basic built-in functions supported. +-@smallexample +-__float128 __builtin_fabsq (__float128); +-__float128 __builtin_copysignq (__float128, __float128); +-__float128 __builtin_infq (void); +-__float128 __builtin_huge_valq (void); +-__float128 __builtin_nanq (void); +-__float128 __builtin_nansq (void); +-@end smallexample +- + @node MIPS DSP Built-in Functions + @subsection MIPS DSP Built-in Functions + +diff --git a/gcc/testsuite/gcc.target/loongarch/math-float-128.c b/gcc/testsuite/gcc.target/loongarch/math-float-128.c +deleted file mode 100644 +index 387566a57..000000000 +--- a/gcc/testsuite/gcc.target/loongarch/math-float-128.c ++++ /dev/null +@@ -1,81 +0,0 @@ +-/* { dg-do compile } */ +-/* { dg-options " -march=loongarch64 -O2 " } */ +-/* { dg-final { scan-assembler-not "my_fabsq2:.*\\bl\t%plt\\(__builtin_fabsq\\).*my_fabsq2" } } */ +-/* { dg-final { scan-assembler-not "my_copysignq2:.*\\bl\t%plt\\(__builtin_copysignq\\).*my_copysignq2" } } */ +-/* { dg-final { scan-assembler-not "my_infq2:.*\\bl\t%plt\\(__builtin_infq\\).*my_infq2" } } */ +-/* { dg-final { scan-assembler-not "my_huge_valq2:.*\\bl\t%plt\\(__builtin_huge_valq\\).*my_huge_valq2" } } */ +-/* { dg-final { scan-assembler-not "my_nanq2:.*\\bl\t%plt\\(__builtin_nanq\\).*my_nanq2" } } */ +-/* { dg-final { scan-assembler-not "my_nansq2:.*\\bl\t%plt\\(__builtin_nansq\\).*my_nansq2" } } */ +- +-__float128 +-my_fabsq1 (__float128 a) +-{ +- return __builtin_fabsq (a); +-} +- +-_Float128 +-my_fabsq2 (_Float128 a) +-{ +- return __builtin_fabsq (a); +-} +- +-__float128 +-my_copysignq1 (__float128 a, __float128 b) +-{ +- return __builtin_copysignq (a, b); +-} +- +-_Float128 +-my_copysignq2 (_Float128 a, _Float128 b) +-{ +- return __builtin_copysignq (a, b); +-} +- +-__float128 +-my_infq1 (void) +-{ +- return __builtin_infq (); +-} +- +-_Float128 +-my_infq2 (void) +-{ +- return __builtin_infq (); +-} +- +-__float128 +-my_huge_valq1 (void) +-{ +- return __builtin_huge_valq (); +-} +- +-_Float128 +-my_huge_valq2 (void) +-{ +- return __builtin_huge_valq (); +-} +- +-__float128 +-my_nanq1 (void) +-{ +- return __builtin_nanq (""); +-} +- +-_Float128 +-my_nanq2 (void) +-{ +- return __builtin_nanq (""); +-} +- +-__float128 +-my_nansq1 (void) +-{ +- return __builtin_nansq (""); +-} +- +-_Float128 +-my_nansq2 (void) +-{ +- return __builtin_nansq (""); +-} +-
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_service:tar_scm:LoongArch-fix-signed-overflow-in-loongarch_emit_int_.patch
Added
@@ -0,0 +1,43 @@ +From 15f1e94ddd7128f407ada43fd9e4b26d4a8bba8d Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao <xry111@xry111.site> +Date: Fri, 4 Nov 2022 01:35:25 +0800 +Subject: PATCH 026/124 LoongArch: fix signed overflow in + loongarch_emit_int_compare + +Signed overflow is an undefined behavior, so we need to prevent it from +happening, instead of "checking" the result. + +gcc/ChangeLog: + + * config/loongarch/loongarch.cc (loongarch_emit_int_compare): + Avoid signed overflow. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/loongarch.cc | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc +index e9ba3374e..d552b162a 100644 +--- a/gcc/config/loongarch/loongarch.cc ++++ b/gcc/config/loongarch/loongarch.cc +@@ -4177,10 +4177,13 @@ loongarch_emit_int_compare (enum rtx_code *code, rtx *op0, rtx *op1) + if (!increment && !decrement) + continue; + ++ if ((increment && rhs == HOST_WIDE_INT_MAX) ++ || (decrement && rhs == HOST_WIDE_INT_MIN)) ++ break; ++ + new_rhs = rhs + (increment ? 1 : -1); + if (loongarch_integer_cost (new_rhs) +- < loongarch_integer_cost (rhs) +- && (rhs < 0) == (new_rhs < 0)) ++ < loongarch_integer_cost (rhs)) + { + *op1 = GEN_INT (new_rhs); + *code = mag_comparisonsiincrement; +-- +2.33.0 +
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_service:tar_scm:LoongArch-implement-count_-leading-trailing-_zeros.patch
Added
@@ -0,0 +1,50 @@ +From ad6541a22dd909a04d745b42c8da5e04733efec4 Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao <xry111@xry111.site> +Date: Wed, 12 Oct 2022 22:06:07 +0800 +Subject: PATCH 023/124 LoongArch: implement count_{leading,trailing}_zeros + +LoongArch always support clz and ctz instructions, so we can always use +__builtin_{clz,ctz} for count_{leading,trailing}_zeros. This improves +the code of libgcc, and also benefits Glibc once we merge longlong.h +there. + +Bootstrapped and regtested on loongarch64-linux-gnu. + +include/ChangeLog: + + * longlong.h __loongarch__ (count_leading_zeros): Define. + __loongarch__ (count_trailing_zeros): Likewise. + __loongarch__ (COUNT_LEADING_ZEROS_0): Likewise. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + include/longlong.h | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/include/longlong.h b/include/longlong.h +index 64a7b10f9..c3a6f1e7e 100644 +--- a/include/longlong.h ++++ b/include/longlong.h +@@ -593,6 +593,18 @@ extern UDItype __umulsidi3 (USItype, USItype); + #define UMUL_TIME 14 + #endif + ++#ifdef __loongarch__ ++# if W_TYPE_SIZE == 32 ++# define count_leading_zeros(count, x) ((count) = __builtin_clz (x)) ++# define count_trailing_zeros(count, x) ((count) = __builtin_ctz (x)) ++# define COUNT_LEADING_ZEROS_0 32 ++# elif W_TYPE_SIZE == 64 ++# define count_leading_zeros(count, x) ((count) = __builtin_clzll (x)) ++# define count_trailing_zeros(count, x) ((count) = __builtin_ctzll (x)) ++# define COUNT_LEADING_ZEROS_0 64 ++# endif ++#endif ++ + #if defined (__M32R__) && W_TYPE_SIZE == 32 + #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ + /* The cmp clears the condition bit. */ \ +-- +2.33.0 +
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_service:tar_scm:LoongArch-improved-target-configuration-interface.patch
Added
@@ -0,0 +1,3024 @@ +From b980a32eabcbd34e8f8e6a245dbba1898256555e Mon Sep 17 00:00:00 2001 +From: Yang Yujie <yangyujie@loongson.cn> +Date: Wed, 23 Aug 2023 15:16:21 +0800 +Subject: PATCH 058/124 LoongArch: improved target configuration interface + +The configure script and the GCC driver are updated so that +it is easier to customize and control GCC builds for targeting +different LoongArch implementations. + +* Make --with-abi obsolete, since it might cause different default ABI + under the same target triplet, which is undesirable. The default ABI + is now purely decided by the target triplet. + +* Support options for LoongArch SIMD extensions: + new configure options --with-simd={none,lsx,lasx}; + new compiler option -msimd={none,lsx,lasx}; + new driver options -mno-lasx. + +* Enforce the priority of configuration paths (for <parm>={fpu,tune,simd}): + -m<parm> > -march-implied > --with-<parm> > --with-arch-implied. + +* Allow the user to control the compiler options used when building + GCC libraries for each multilib variant via --with-multilib-list + and --with-multilib-default. This could become more useful when + we have 32-bit support later. + + Example 1: the following configure option + --with-multilib-list=lp64d/la464/mno-strict-align/msimd=lsx,lp64s/mfpu=32 + | | | | + -mabi=ABI -march=ARCH a list of other options + (mandatory) (optional) (optional) + + builds two sets of libraries: + 1. lp64d/base ABI (built with "-march=la464 -mno-strict-align -msimd=lsx") + 2. lp64s/base ABI (built with "-march=abi-default -mfpu=32") + + Example 2: the following 3 configure options + + --with-arch=loongarch64 + --with-multilib-list=lp64d,lp64f,lp64s/la464 + --with-multilib-default=fixed/mno-strict-align/mfpu=64 + | | | + -march=ARCH a list of other options + (optional) (optional) + + is equivalent to (in terms of building libraries): + + --with-multilib-list=\ + lp64d/loongarch64/mno-strict-align/mfpu=64,\ + lp64f/loongarch64/mno-strict-align/mfpu=64,\ + lp64s/la464 + + Note: + 1. the GCC driver and compiler proper does not support + "-march=fixed". "fixed" that appear here acts as a placeholder for + "use whatever ARCH in --with-arch=ARCH" (or the default value + of --with-arch=ARCH if --with-arch is not explicitly configured). + + 2. if the ARCH part is omitted, "-march=abi-default" + is used for building all library variants, which + practically means enabling the minimal ISA features + that can support the given ABI. + +ChangeLog: + + * config-ml.in: Do not build the multilib library variant + that is duplicate with the toplevel one. + +gcc/ChangeLog: + + * config.gcc: Make --with-abi= obsolete, decide the default ABI + with target triplet. Allow specifying multilib library build + options with --with-multilib-list and --with-multilib-default. + * config/loongarch/t-linux: Likewise. + * config/loongarch/genopts/loongarch-strings: Likewise. + * config/loongarch/loongarch-str.h: Likewise. + * doc/install.texi: Likewise. + * config/loongarch/genopts/loongarch.opt.in: Introduce + -mno-lasx options. Only process -m*-float and + -mno-lasx in the GCC driver. + * config/loongarch/loongarch.opt: Likewise. + * config/loongarch/la464.md: Likewise. + * config/loongarch/loongarch-c.cc: Likewise. + * config/loongarch/loongarch-cpu.cc: Likewise. + * config/loongarch/loongarch-cpu.h: Likewise. + * config/loongarch/loongarch-def.c: Likewise. + * config/loongarch/loongarch-def.h: Likewise. + * config/loongarch/loongarch-driver.cc: Likewise. + * config/loongarch/loongarch-driver.h: Likewise. + * config/loongarch/loongarch-opts.cc: Likewise. + * config/loongarch/loongarch-opts.h: Likewise. + * config/loongarch/loongarch.cc: Likewise. + * doc/invoke.texi: Likewise. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + config-ml.in | 10 + + gcc/config.gcc | 379 ++++++++++-------- + .../loongarch/genopts/loongarch-strings | 8 +- + gcc/config/loongarch/genopts/loongarch.opt.in | 62 +-- + gcc/config/loongarch/la464.md | 32 +- + gcc/config/loongarch/loongarch-c.cc | 19 +- + gcc/config/loongarch/loongarch-cpu.cc | 263 +++++++----- + gcc/config/loongarch/loongarch-cpu.h | 3 +- + gcc/config/loongarch/loongarch-def.c | 67 ++-- + gcc/config/loongarch/loongarch-def.h | 57 +-- + gcc/config/loongarch/loongarch-driver.cc | 208 +++++----- + gcc/config/loongarch/loongarch-driver.h | 40 +- + gcc/config/loongarch/loongarch-opts.cc | 372 ++++++++++++----- + gcc/config/loongarch/loongarch-opts.h | 59 +-- + gcc/config/loongarch/loongarch-str.h | 7 +- + gcc/config/loongarch/loongarch.cc | 87 ++-- + gcc/config/loongarch/loongarch.opt | 60 ++- + gcc/config/loongarch/t-linux | 32 +- + gcc/doc/install.texi | 52 ++- + 19 files changed, 1136 insertions(+), 681 deletions(-) + +diff --git a/config-ml.in b/config-ml.in +index 68854a4f1..ad0db0781 100644 +--- a/config-ml.in ++++ b/config-ml.in +@@ -301,6 +301,16 @@ arm-*-*) + done + fi + ;; ++loongarch*-*) ++ old_multidirs="${multidirs}" ++ multidirs="" ++ for x in ${old_multidirs}; do ++ case "$x" in ++ `${CC-gcc} --print-multi-directory`) : ;; ++ *) multidirs="${multidirs} ${x}" ;; ++ esac ++ done ++ ;; + m68*-*-*) + if x$enable_softfloat = xno + then +diff --git a/gcc/config.gcc b/gcc/config.gcc +index 5c378c698..62525c296 100644 +--- a/gcc/config.gcc ++++ b/gcc/config.gcc +@@ -4965,43 +4965,46 @@ case "${target}" in + esac + ;; + +- loongarch*-*-*) +- supported_defaults="abi arch tune fpu" ++ loongarch*-*) ++ supported_defaults="abi arch tune fpu simd multilib-default" + + # Local variables + unset \ +- abi_pattern abi_default \ +- abiext_pattern abiext_default \ +- arch_pattern arch_default \ +- fpu_pattern fpu_default \ +- tune_pattern tune_default \ +- triplet_os triplet_abi ++ abi_base abi_ext \ ++ arch_pattern arch_default \ ++ fpu_pattern fpu_default \ ++ triplet_os triplet_abi \ ++ strict_align_opt ++ ++ # --with-abi is now obsolete, emit a warning if given. ++ case ${with_abi} in ++ "") ;; ++ *) ++ echo "warning: --with-abi= is now obsolete," \ ++ "the default ABI is derived from your target" \ ++ "triplet ${target}" 1>&2 ++ ;; ++ esac + + # Infer ABI from the triplet. + case ${target} in +- loongarch64-*-*-*f64) +- abi_pattern="lp64d" +- ;; +- loongarch64-*-*-*f32) +- abi_pattern="lp64f" +- ;; +- loongarch64-*-*-*sf) +- abi_pattern="lp64s" +- ;; +- loongarch64-*-*-*) +- abi_pattern="lp64dfs" +- abi_default="lp64d" +- ;; ++ loongarch64-*f64) abi_base="lp64d"; abi_ext="base" ;; ++ loongarch64-*f32) abi_base="lp64f"; abi_ext="base" ;; ++ loongarch64-*sf) abi_base="lp64s"; abi_ext="base" ;; ++ loongarch64-*) abi_base="lp64d"; abi_ext="base" ;; + *) + echo "Unsupported target ${target}." 1>&2 + exit 1 + ;;
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_service:tar_scm:LoongArch-initial-ada-support-on-linux.patch
Added
@@ -0,0 +1,397 @@ +From 7fa71be34052de9bdd9f7bdf625ceeaabc7f16f0 Mon Sep 17 00:00:00 2001 +From: Yang Yujie <yangyujie@loongson.cn> +Date: Tue, 5 Sep 2023 11:50:07 +0800 +Subject: PATCH 062/124 LoongArch: initial ada support on linux + +gcc/ada/ChangeLog: + + * Makefile.rtl: Add LoongArch support. + * libgnarl/s-linux__loongarch.ads: New file. + * libgnat/system-linux-loongarch.ads: New file. + +gcc/ChangeLog: + + * config/loongarch/loongarch.h (CC1_SPEC): Mark normalized + options passed from driver to gnat1 as explicit for multilib. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/ada/Makefile.rtl | 49 +++++++ + gcc/ada/libgnarl/s-linux__loongarch.ads | 134 +++++++++++++++++++ + gcc/ada/libgnat/system-linux-loongarch.ads | 145 +++++++++++++++++++++ + gcc/config/loongarch/loongarch.h | 4 +- + 4 files changed, 330 insertions(+), 2 deletions(-) + create mode 100644 gcc/ada/libgnarl/s-linux__loongarch.ads + create mode 100644 gcc/ada/libgnat/system-linux-loongarch.ads + +diff --git a/gcc/ada/Makefile.rtl b/gcc/ada/Makefile.rtl +index aaf853e3a..579645d95 100644 +--- a/gcc/ada/Makefile.rtl ++++ b/gcc/ada/Makefile.rtl +@@ -2195,6 +2195,55 @@ ifeq ($(strip $(filter-out cygwin% mingw32% pe,$(target_os))),) + LIBRARY_VERSION := $(LIB_VERSION) + endif + ++# LoongArch Linux ++ifeq ($(strip $(filter-out loongarch% linux%,$(target_cpu) $(target_os))),) ++ LIBGNAT_TARGET_PAIRS = \ ++ a-exetim.adb<libgnarl/a-exetim__posix.adb \ ++ a-exetim.ads<libgnarl/a-exetim__default.ads \ ++ a-intnam.ads<libgnarl/a-intnam__linux.ads \ ++ a-nallfl.ads<libgnat/a-nallfl__wraplf.ads \ ++ a-synbar.adb<libgnarl/a-synbar__posix.adb \ ++ a-synbar.ads<libgnarl/a-synbar__posix.ads \ ++ s-inmaop.adb<libgnarl/s-inmaop__posix.adb \ ++ s-intman.adb<libgnarl/s-intman__posix.adb \ ++ s-linux.ads<libgnarl/s-linux__loongarch.ads \ ++ s-mudido.adb<libgnarl/s-mudido__affinity.adb \ ++ s-osinte.ads<libgnarl/s-osinte__linux.ads \ ++ s-osinte.adb<libgnarl/s-osinte__posix.adb \ ++ s-osprim.adb<libgnat/s-osprim__posix.adb \ ++ s-taprop.adb<libgnarl/s-taprop__linux.adb \ ++ s-tasinf.ads<libgnarl/s-tasinf__linux.ads \ ++ s-tasinf.adb<libgnarl/s-tasinf__linux.adb \ ++ s-tpopsp.adb<libgnarl/s-tpopsp__tls.adb \ ++ s-taspri.ads<libgnarl/s-taspri__posix.ads \ ++ g-sercom.adb<libgnat/g-sercom__linux.adb \ ++ $(TRASYM_DWARF_UNIX_PAIRS) \ ++ $(GNATRTL_128BIT_PAIRS) \ ++ s-tsmona.adb<libgnat/s-tsmona__linux.adb \ ++ $(ATOMICS_TARGET_PAIRS) \ ++ $(ATOMICS_BUILTINS_TARGET_PAIRS) \ ++ system.ads<libgnat/system-linux-loongarch.ads ++ ++ TOOLS_TARGET_PAIRS = indepsw.adb<indepsw-gnu.adb ++ ++ EXTRA_GNATRTL_NONTASKING_OBJS += $(TRASYM_DWARF_UNIX_OBJS) ++ EXTRA_GNATRTL_NONTASKING_OBJS += $(GNATRTL_128BIT_OBJS) ++ EXTRA_GNATRTL_TASKING_OBJS = s-linux.o a-exetim.o ++ ++ EH_MECHANISM = -gcc ++ THREADSLIB = -lpthread ++ MISCLIB = -ldl ++ GNATLIB_SHARED = gnatlib-shared-dual ++ GMEM_LIB = gmemlib ++ LIBRARY_VERSION := $(LIB_VERSION) ++ # Temporarily disable strict alignment -- for some reason, it causes ++ # infinite loops during stack unwinding (libgcc) and indefinite hang ++ # in some futex system calls. ++ GNATLIBCFLAGS += -mno-strict-align ++ GNATLIBCFLAGS_FOR_C += -mno-strict-align ++endif ++ ++ + # Mips Linux + ifeq ($(strip $(filter-out mips% linux%,$(target_cpu) $(target_os))),) + LIBGNAT_TARGET_PAIRS = \ +diff --git a/gcc/ada/libgnarl/s-linux__loongarch.ads b/gcc/ada/libgnarl/s-linux__loongarch.ads +new file mode 100644 +index 000000000..9773ec0ad +--- /dev/null ++++ b/gcc/ada/libgnarl/s-linux__loongarch.ads +@@ -0,0 +1,134 @@ ++------------------------------------------------------------------------------ ++-- -- ++-- GNU ADA RUN-TIME LIBRARY (GNARL) COMPONENTS -- ++-- -- ++-- S Y S T E M . L I N U X -- ++-- -- ++-- S p e c -- ++-- -- ++-- Copyright (C) 2009-2023, Free Software Foundation, Inc. -- ++-- -- ++-- GNARL is free software; you can redistribute it and/or modify it under -- ++-- terms of the GNU General Public License as published by the Free Soft- -- ++-- ware Foundation; either version 3, or (at your option) any later ver- -- ++-- sion. GNAT is distributed in the hope that it will be useful, but WITH- -- ++-- OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -- ++-- or FITNESS FOR A PARTICULAR PURPOSE. -- ++-- -- ++-- As a special exception under Section 7 of GPL version 3, you are granted -- ++-- additional permissions described in the GCC Runtime Library Exception, -- ++-- version 3.1, as published by the Free Software Foundation. -- ++-- -- ++-- You should have received a copy of the GNU General Public License and -- ++-- a copy of the GCC Runtime Library Exception along with this program; -- ++-- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -- ++-- <http://www.gnu.org/licenses/>. -- ++-- -- ++------------------------------------------------------------------------------ ++ ++-- This is the LoongArch version of this package ++ ++-- This package encapsulates cpu specific differences between implementations ++-- of GNU/Linux, in order to share s-osinte-linux.ads. ++ ++-- PLEASE DO NOT add any with-clauses to this package or remove the pragma ++-- Preelaborate. This package is designed to be a bottom-level (leaf) package ++ ++with Interfaces.C; ++with System.Parameters; ++ ++package System.Linux is ++ pragma Preelaborate; ++ ++ ---------- ++ -- Time -- ++ ---------- ++ ++ subtype int is Interfaces.C.int; ++ subtype long is Interfaces.C.long; ++ subtype suseconds_t is Interfaces.C.long; ++ type time_t is range -2 ** (System.Parameters.time_t_bits - 1) ++ .. 2 ** (System.Parameters.time_t_bits - 1) - 1; ++ subtype clockid_t is Interfaces.C.int; ++ ++ type timespec is record ++ tv_sec : time_t; ++ tv_nsec : long; ++ end record; ++ pragma Convention (C, timespec); ++ ++ type timeval is record ++ tv_sec : time_t; ++ tv_usec : suseconds_t; ++ end record; ++ pragma Convention (C, timeval); ++ ++ ----------- ++ -- Errno -- ++ ----------- ++ ++ EAGAIN : constant := 11; ++ EINTR : constant := 4; ++ EINVAL : constant := 22; ++ ENOMEM : constant := 12; ++ EPERM : constant := 1; ++ ETIMEDOUT : constant := 110; ++ ++ ------------- ++ -- Signals -- ++ ------------- ++ ++ SIGHUP : constant := 1; -- hangup ++ SIGINT : constant := 2; -- interrupt (rubout) ++ SIGQUIT : constant := 3; -- quit (ASCD FS) ++ SIGILL : constant := 4; -- illegal instruction (not reset) ++ SIGTRAP : constant := 5; -- trace trap (not reset) ++ SIGIOT : constant := 6; -- IOT instruction ++ SIGABRT : constant := 6; -- used by abort, replace SIGIOT in the future ++ SIGBUS : constant := 7; -- bus error ++ SIGFPE : constant := 8; -- floating point exception ++ SIGKILL : constant := 9; -- kill (cannot be caught or ignored) ++ SIGUSR1 : constant := 10; -- user defined signal 1 ++ SIGSEGV : constant := 11; -- segmentation violation ++ SIGUSR2 : constant := 12; -- user defined signal 2 ++ SIGPIPE : constant := 13; -- write on a pipe with no one to read it ++ SIGALRM : constant := 14; -- alarm clock ++ SIGTERM : constant := 15; -- software termination signal from kill ++ SIGSTKFLT : constant := 16; -- coprocessor stack fault (Linux) ++ SIGCLD : constant := 17; -- alias for SIGCHLD ++ SIGCHLD : constant := 17; -- child status change ++ SIGCONT : constant := 18; -- stopped process has been continued ++ SIGSTOP : constant := 19; -- stop (cannot be caught or ignored) ++ SIGTSTP : constant := 20; -- user stop requested from tty ++ SIGTTIN : constant := 21; -- background tty read attempted ++ SIGTTOU : constant := 22; -- background tty write attempted ++ SIGURG : constant := 23; -- urgent condition on IO channel ++ SIGXCPU : constant := 24; -- CPU time limit exceeded
View file
_service:tar_scm:LoongArch-support-loongarch-elf-target.patch
Added
@@ -0,0 +1,152 @@ +From 71cfcadb647026ced3c99688793a2f8e5d5f0039 Mon Sep 17 00:00:00 2001 +From: Yang Yujie <yangyujie@loongson.cn> +Date: Fri, 30 Jun 2023 17:07:59 +0800 +Subject: PATCH 061/124 LoongArch: support loongarch*-elf target + +gcc/ChangeLog: + + * config.gcc: add loongarch*-elf target. + * config/loongarch/elf.h: New file. + Link against newlib by default. + +libgcc/ChangeLog: + + * config.host: add loongarch*-elf target. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config.gcc | 15 ++++++++++- + gcc/config/loongarch/elf.h | 51 ++++++++++++++++++++++++++++++++++++++ + libgcc/config.host | 9 +++++-- + 3 files changed, 72 insertions(+), 3 deletions(-) + create mode 100644 gcc/config/loongarch/elf.h + +diff --git a/gcc/config.gcc b/gcc/config.gcc +index 16bbaea45..61d81d8d8 100644 +--- a/gcc/config.gcc ++++ b/gcc/config.gcc +@@ -2519,6 +2519,18 @@ loongarch*-*-linux*) + gcc_cv_initfini_array=yes + ;; + ++loongarch*-*-elf*) ++ tm_file="elfos.h newlib-stdint.h ${tm_file}" ++ tm_file="${tm_file} loongarch/elf.h loongarch/linux.h" ++ tmake_file="${tmake_file} loongarch/t-linux" ++ gnu_ld=yes ++ gas=yes ++ ++ # For .init_array support. The configure script cannot always ++ # automatically detect that GAS supports it, yet we require it. ++ gcc_cv_initfini_array=yes ++ ;; ++ + mips*-*-netbsd*) # NetBSD/mips, either endian. + target_cpu_default="MASK_ABICALLS" + tm_file="elfos.h ${tm_file} mips/elf.h ${nbsd_tm_file} mips/netbsd.h" +@@ -5006,8 +5018,9 @@ case "${target}" in + esac + + case ${target} in +- *-linux-gnu*) triplet_os="linux-gnu";; ++ *-linux-gnu*) triplet_os="linux-gnu";; + *-linux-musl*) triplet_os="linux-musl";; ++ *-elf*) triplet_os="elf";; + *) + echo "Unsupported target ${target}." 1>&2 + exit 1 +diff --git a/gcc/config/loongarch/elf.h b/gcc/config/loongarch/elf.h +new file mode 100644 +index 000000000..523d5c756 +--- /dev/null ++++ b/gcc/config/loongarch/elf.h +@@ -0,0 +1,51 @@ ++/* Definitions for LoongArch ELF-based systems. ++ Copyright (C) 2023 Free Software Foundation, Inc. ++ ++This file is part of GCC. ++ ++GCC is free software; you can redistribute it and/or modify ++it under the terms of the GNU General Public License as published by ++the Free Software Foundation; either version 3, or (at your option) ++any later version. ++ ++GCC is distributed in the hope that it will be useful, ++but WITHOUT ANY WARRANTY; without even the implied warranty of ++MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++GNU General Public License for more details. ++ ++You should have received a copy of the GNU General Public License ++along with GCC; see the file COPYING3. If not see ++<http://www.gnu.org/licenses/>. */ ++ ++/* Define the size of the wide character type. */ ++#undef WCHAR_TYPE ++#define WCHAR_TYPE "int" ++ ++#undef WCHAR_TYPE_SIZE ++#define WCHAR_TYPE_SIZE 32 ++ ++ ++/* GNU-specific SPEC definitions. */ ++#define GNU_USER_LINK_EMULATION "elf" ABI_GRLEN_SPEC "loongarch" ++ ++#undef GNU_USER_TARGET_LINK_SPEC ++#define GNU_USER_TARGET_LINK_SPEC \ ++ "%{shared} -m " GNU_USER_LINK_EMULATION ++ ++ ++/* Link against Newlib libraries, because the ELF backend assumes Newlib. ++ Handle the circular dependence between libc and libgloss. */ ++#undef LIB_SPEC ++#define LIB_SPEC "--start-group -lc %{!specs=nosys.specs:-lgloss} --end-group" ++ ++#undef LINK_SPEC ++#define LINK_SPEC GNU_USER_TARGET_LINK_SPEC ++ ++#undef STARTFILE_SPEC ++#define STARTFILE_SPEC "crt0%O%s crtbegin%O%s" ++ ++#undef ENDFILE_SPEC ++#define ENDFILE_SPEC "crtend%O%s" ++ ++#undef SUBTARGET_CC1_SPEC ++#define SUBTARGET_CC1_SPEC "%{profile:-p}" +diff --git a/libgcc/config.host b/libgcc/config.host +index 8c56fcae5..dc12d646c 100644 +--- a/libgcc/config.host ++++ b/libgcc/config.host +@@ -138,7 +138,7 @@ hppa*-*-*) + lm32*-*-*) + cpu_type=lm32 + ;; +-loongarch*-*-*) ++loongarch*-*) + cpu_type=loongarch + tmake_file="loongarch/t-loongarch" + if test "${libgcc_cv_loongarch_hard_float}" = yes; then +@@ -942,7 +942,7 @@ lm32-*-uclinux*) + extra_parts="$extra_parts crtbegin.o crtendS.o crtbeginT.o" + tmake_file="lm32/t-lm32 lm32/t-uclinux t-libgcc-pic t-softfp-sfdf t-softfp" + ;; +-loongarch*-*-linux*) ++loongarch*-linux*) + extra_parts="$extra_parts crtfastmath.o" + tmake_file="${tmake_file} t-crtfm loongarch/t-crtstuff" + case ${host} in +@@ -952,6 +952,11 @@ loongarch*-*-linux*) + esac + md_unwind_header=loongarch/linux-unwind.h + ;; ++loongarch*-elf*) ++ extra_parts="$extra_parts crtfastmath.o" ++ tmake_file="${tmake_file} t-crtfm loongarch/t-crtstuff" ++ tmake_file="${tmake_file} t-slibgcc-libgcc" ++ ;; + m32r-*-elf*) + tmake_file="$tmake_file m32r/t-m32r t-fdpbit" + extra_parts="$extra_parts crtinit.o crtfini.o" +-- +2.33.0 +
View file
_service:tar_scm:LoongArch-testsuite-Disable-stack-protector-for-some.patch
Added
@@ -0,0 +1,65 @@ +From 3bbaedb0f20b52bc276f40b6016becd2c4e66276 Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao <xry111@xry111.site> +Date: Fri, 3 Mar 2023 16:32:41 +0800 +Subject: PATCH 038/124 LoongArch: testsuite: Disable stack protector for + some tests + +Stack protector will affect stack layout and break the expectation of +these tests, causing test failures if GCC is configured with +--enable-default-ssp. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/prolog-opt.c (dg-options): Add + -fno-stack-protector. + * gcc.target/loongarch/stack-check-cfa-1.c (dg-options): + Likewise. + * gcc.target/loongarch/stack-check-cfa-2.c (dg-options): + Likewise. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/testsuite/gcc.target/loongarch/prolog-opt.c | 2 +- + gcc/testsuite/gcc.target/loongarch/stack-check-cfa-1.c | 2 +- + gcc/testsuite/gcc.target/loongarch/stack-check-cfa-2.c | 2 +- + 3 files changed, 3 insertions(+), 3 deletions(-) + +diff --git a/gcc/testsuite/gcc.target/loongarch/prolog-opt.c b/gcc/testsuite/gcc.target/loongarch/prolog-opt.c +index 0470a1f1e..e6a642633 100644 +--- a/gcc/testsuite/gcc.target/loongarch/prolog-opt.c ++++ b/gcc/testsuite/gcc.target/loongarch/prolog-opt.c +@@ -1,7 +1,7 @@ + /* Test that LoongArch backend stack drop operation optimized. */ + + /* { dg-do compile } */ +-/* { dg-options "-O2 -mabi=lp64d" } */ ++/* { dg-options "-O2 -mabi=lp64d -fno-stack-protector" } */ + /* { dg-final { scan-assembler "addi.d\t\\\$r3,\\\$r3,-16" } } */ + + extern int printf (char *, ...); +diff --git a/gcc/testsuite/gcc.target/loongarch/stack-check-cfa-1.c b/gcc/testsuite/gcc.target/loongarch/stack-check-cfa-1.c +index f0c6877fc..3533fe7b6 100644 +--- a/gcc/testsuite/gcc.target/loongarch/stack-check-cfa-1.c ++++ b/gcc/testsuite/gcc.target/loongarch/stack-check-cfa-1.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* { dg-options "-O2 -fstack-clash-protection --param stack-clash-protection-guard-size=16 -funwind-tables" } */ ++/* { dg-options "-O2 -fstack-clash-protection --param stack-clash-protection-guard-size=16 -funwind-tables -fno-stack-protector" } */ + /* { dg-require-effective-target supports_stack_clash_protection } */ + /* { dg-skip-if "" { *-*-* } { "-fstack-check" } { "" } } */ + +diff --git a/gcc/testsuite/gcc.target/loongarch/stack-check-cfa-2.c b/gcc/testsuite/gcc.target/loongarch/stack-check-cfa-2.c +index c6e07bc56..e5e711105 100644 +--- a/gcc/testsuite/gcc.target/loongarch/stack-check-cfa-2.c ++++ b/gcc/testsuite/gcc.target/loongarch/stack-check-cfa-2.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* { dg-options "-O2 -fstack-clash-protection --param stack-clash-protection-guard-size=16 -funwind-tables" } */ ++/* { dg-options "-O2 -fstack-clash-protection --param stack-clash-protection-guard-size=16 -funwind-tables -fno-stack-protector" } */ + /* { dg-require-effective-target supports_stack_clash_protection } */ + /* { dg-skip-if "" { *-*-* } { "-fstack-check" } { "" } } */ + +-- +2.33.0 +
View file
_service:tar_scm:LoongArch-testsuite-refine-__tls_get_addr-tests-with.patch
Added
@@ -0,0 +1,159 @@ +From e34afad69acd5b0bd19aef9f6225ca38aa294193 Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao <xry111@xry111.site> +Date: Wed, 24 Aug 2022 19:34:47 +0800 +Subject: PATCH 015/124 LoongArch: testsuite: refine __tls_get_addr tests + with tls_native + +If GCC is not built with a working linker for the target (developers +occansionally build such a "minimal" GCC for testing and debugging), +TLS will be emulated and __tls_get_addr won't be used. Refine those +tests depending on __tls_get_addr with tls_native to avoid test +failures. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/func-call-medium-1.c: Refine test + depending on __tls_get_addr with { target tls_native }. + * gcc.target/loongarch/func-call-medium-2.c: Likewise. + * gcc.target/loongarch/func-call-medium-3.c: Likewise. + * gcc.target/loongarch/func-call-medium-4.c: Likewise. + * gcc.target/loongarch/func-call-medium-5.c: Likewise. + * gcc.target/loongarch/func-call-medium-6.c: Likewise. + * gcc.target/loongarch/func-call-medium-7.c: Likewise. + * gcc.target/loongarch/func-call-medium-8.c: Likewise. + * gcc.target/loongarch/tls-gd-noplt.c: Likewise. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/testsuite/gcc.target/loongarch/func-call-medium-1.c | 2 +- + gcc/testsuite/gcc.target/loongarch/func-call-medium-2.c | 2 +- + gcc/testsuite/gcc.target/loongarch/func-call-medium-3.c | 2 +- + gcc/testsuite/gcc.target/loongarch/func-call-medium-4.c | 2 +- + gcc/testsuite/gcc.target/loongarch/func-call-medium-5.c | 2 +- + gcc/testsuite/gcc.target/loongarch/func-call-medium-6.c | 2 +- + gcc/testsuite/gcc.target/loongarch/func-call-medium-7.c | 2 +- + gcc/testsuite/gcc.target/loongarch/func-call-medium-8.c | 3 ++- + gcc/testsuite/gcc.target/loongarch/tls-gd-noplt.c | 2 +- + 9 files changed, 10 insertions(+), 9 deletions(-) + +diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-medium-1.c b/gcc/testsuite/gcc.target/loongarch/func-call-medium-1.c +index 276d73e5e..6339e832f 100644 +--- a/gcc/testsuite/gcc.target/loongarch/func-call-medium-1.c ++++ b/gcc/testsuite/gcc.target/loongarch/func-call-medium-1.c +@@ -3,7 +3,7 @@ + /* { dg-final { scan-assembler "test:.*la\.global\t.*g\n\tjirl" } } */ + /* { dg-final { scan-assembler "test1:.*la\.global\t.*f\n\tjirl" } } */ + /* { dg-final { scan-assembler "test2:.*la\.local\t.*l\n\tjirl" } } */ +-/* { dg-final { scan-assembler "test3:.*la\.global\t.*\_\_tls\_get\_addr" } } */ ++/* { dg-final { scan-assembler "test3:.*la\.global\t.*\_\_tls\_get\_addr" { target tls_native } } } */ + + extern void g (void); + void +diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-medium-2.c b/gcc/testsuite/gcc.target/loongarch/func-call-medium-2.c +index 237821c06..a53e75e0b 100644 +--- a/gcc/testsuite/gcc.target/loongarch/func-call-medium-2.c ++++ b/gcc/testsuite/gcc.target/loongarch/func-call-medium-2.c +@@ -3,7 +3,7 @@ + /* { dg-final { scan-assembler "test:.*la\.global\t.*g\n\tjirl" } } */ + /* { dg-final { scan-assembler "test1:.*la\.local\t.*f\n\tjirl" } } */ + /* { dg-final { scan-assembler "test2:.*la\.local\t.*l\n\tjirl" } } */ +-/* { dg-final { scan-assembler "test3:.*la\.global\t.*\_\_tls\_get\_addr" } } */ ++/* { dg-final { scan-assembler "test3:.*la\.global\t.*\_\_tls\_get\_addr" { target tls_native } } } */ + + extern void g (void); + void +diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-medium-3.c b/gcc/testsuite/gcc.target/loongarch/func-call-medium-3.c +index 9a6e16103..0da7bf98e 100644 +--- a/gcc/testsuite/gcc.target/loongarch/func-call-medium-3.c ++++ b/gcc/testsuite/gcc.target/loongarch/func-call-medium-3.c +@@ -3,7 +3,7 @@ + /* { dg-final { scan-assembler "test:.*la\.global\t.*g\n\tjirl" } } */ + /* { dg-final { scan-assembler "test1:.*la\.global\t.*f\n\tjirl" } } */ + /* { dg-final { scan-assembler "test2:.*la\.local\t.*l\n\tjirl" } } */ +-/* { dg-final { scan-assembler "test3:.*la\.global\t.*\_\_tls\_get\_addr" } } */ ++/* { dg-final { scan-assembler "test3:.*la\.global\t.*\_\_tls\_get\_addr" { target tls_native } } } */ + + extern void g (void); + void +diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-medium-4.c b/gcc/testsuite/gcc.target/loongarch/func-call-medium-4.c +index 2577e3452..0219688ae 100644 +--- a/gcc/testsuite/gcc.target/loongarch/func-call-medium-4.c ++++ b/gcc/testsuite/gcc.target/loongarch/func-call-medium-4.c +@@ -3,7 +3,7 @@ + /* { dg-final { scan-assembler "test:.*la\.global\t.*g\n\tjirl" } } */ + /* { dg-final { scan-assembler "test1:.*la\.local\t.*f\n\tjirl" } } */ + /* { dg-final { scan-assembler "test2:.*la\.local\t.*l\n\tjirl" } } */ +-/* { dg-final { scan-assembler "test3:.*la\.global\t.*\_\_tls\_get\_addr" } } */ ++/* { dg-final { scan-assembler "test3:.*la\.global\t.*\_\_tls\_get\_addr" { target tls_native } } } */ + + extern void g (void); + void +diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-medium-5.c b/gcc/testsuite/gcc.target/loongarch/func-call-medium-5.c +index d70b6ea46..8a47b5afc 100644 +--- a/gcc/testsuite/gcc.target/loongarch/func-call-medium-5.c ++++ b/gcc/testsuite/gcc.target/loongarch/func-call-medium-5.c +@@ -3,7 +3,7 @@ + /* { dg-final { scan-assembler "test:.*pcalau12i.*%pc_hi20\\(g\\)\n\tjirl.*pc_lo12\\(g\\)" } } */ + /* { dg-final { scan-assembler "test1:.*pcalau12i.*%pc_hi20\\(f\\)\n\tjirl.*%pc_lo12\\(f\\)" } } */ + /* { dg-final { scan-assembler "test2:.*pcalau12i.*%pc_hi20\\(l\\)\n\tjirl.*%pc_lo12\\(l\\)" } } */ +-/* { dg-final { scan-assembler "test3:.*pcalau12i.*%pc_hi20\\(__tls_get_addr\\)\n\t.*\n\tjirl.*%pc_lo12\\(__tls_get_addr\\)" } } */ ++/* { dg-final { scan-assembler "test3:.*pcalau12i.*%pc_hi20\\(__tls_get_addr\\)\n\t.*\n\tjirl.*%pc_lo12\\(__tls_get_addr\\)" { target tls_native } } } */ + + extern void g (void); + +diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-medium-6.c b/gcc/testsuite/gcc.target/loongarch/func-call-medium-6.c +index f963a9944..1e75e60e0 100644 +--- a/gcc/testsuite/gcc.target/loongarch/func-call-medium-6.c ++++ b/gcc/testsuite/gcc.target/loongarch/func-call-medium-6.c +@@ -3,7 +3,7 @@ + /* { dg-final { scan-assembler "test:.*pcalau12i.*%pc_hi20\\(g\\)\n\tjirl.*pc_lo12\\(g\\)" } } */ + /* { dg-final { scan-assembler "test1:.*pcalau12i.*%pc_hi20\\(f\\)\n\tjirl.*%pc_lo12\\(f\\)" } } */ + /* { dg-final { scan-assembler "test2:.*pcalau12i.*%pc_hi20\\(l\\)\n\tjirl.*%pc_lo12\\(l\\)" } } */ +-/* { dg-final { scan-assembler "test3:.*pcalau12i.*%pc_hi20\\(__tls_get_addr\\)\n\t.*\n\tjirl.*%pc_lo12\\(__tls_get_addr\\)" } } */ ++/* { dg-final { scan-assembler "test3:.*pcalau12i.*%pc_hi20\\(__tls_get_addr\\)\n\t.*\n\tjirl.*%pc_lo12\\(__tls_get_addr\\)" { target tls_native } } } */ + + extern void g (void); + +diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-medium-7.c b/gcc/testsuite/gcc.target/loongarch/func-call-medium-7.c +index f2818b2da..9e89085ca 100644 +--- a/gcc/testsuite/gcc.target/loongarch/func-call-medium-7.c ++++ b/gcc/testsuite/gcc.target/loongarch/func-call-medium-7.c +@@ -3,7 +3,7 @@ + /* { dg-final { scan-assembler "test:.*pcalau12i\t.*%got_pc_hi20\\(g\\)\n\tld\.d\t.*%got_pc_lo12\\(g\\)\n\tjirl" } } */ + /* { dg-final { scan-assembler "test1:.*pcalau12i\t.*%got_pc_hi20\\(f\\)\n\tld\.d\t.*%got_pc_lo12\\(f\\)\n\tjirl" } } */ + /* { dg-final { scan-assembler "test2:.*pcalau12i\t.*%pc_hi20\\(l\\)\n\tjirl.*%pc_lo12\\(l\\)" } } */ +-/* { dg-final { scan-assembler "test3:.*pcalau12i.*%got_pc_hi20\\(__tls_get_addr\\)\n\tld\.d.*%got_pc_lo12\\(__tls_get_addr\\)" } } */ ++/* { dg-final { scan-assembler "test3:.*pcalau12i.*%got_pc_hi20\\(__tls_get_addr\\)\n\tld\.d.*%got_pc_lo12\\(__tls_get_addr\\)" { target tls_native } } } */ + + + extern void g (void); +diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-medium-8.c b/gcc/testsuite/gcc.target/loongarch/func-call-medium-8.c +index 7fa873d84..fde9c6e0e 100644 +--- a/gcc/testsuite/gcc.target/loongarch/func-call-medium-8.c ++++ b/gcc/testsuite/gcc.target/loongarch/func-call-medium-8.c +@@ -3,7 +3,8 @@ + /* { dg-final { scan-assembler "test:.*pcalau12i\t.*%got_pc_hi20\\(g\\)\n\tld\.d\t.*%got_pc_lo12\\(g\\)\n\tjirl" } } */ + /* { dg-final { scan-assembler "test1:.*pcalau12i\t.*%pc_hi20\\(f\\)\n\tjirl.*%pc_lo12\\(f\\)" } } */ + /* { dg-final { scan-assembler "test2:.*pcalau12i\t.*%pc_hi20\\(l\\)\n\tjirl.*%pc_lo12\\(l\\)" } } */ +-/* { dg-final { scan-assembler "test3:.*pcalau12i.*%got_pc_hi20\\(__tls_get_addr\\)\n\tld\.d.*%got_pc_lo12\\(__tls_get_addr\\)" } } */ ++/* { dg-final { scan-assembler "test3:.*pcalau12i.*%got_pc_hi20\\(__tls_get_addr\\)\n\tld\.d.*%got_pc_lo12\\(__tls_get_addr\\)" { target tls_native } } } */ ++/* { dg-final { scan-assembler "test3:.*pcalau12i.*%got_pc_hi20\\(__tls_get_addr\\)\n\tld\.d.*%got_pc_lo12\\(__tls_get_addr\\)" { target tls_native } } } */ + + extern void g (void); + +diff --git a/gcc/testsuite/gcc.target/loongarch/tls-gd-noplt.c b/gcc/testsuite/gcc.target/loongarch/tls-gd-noplt.c +index 375663286..9432c477e 100644 +--- a/gcc/testsuite/gcc.target/loongarch/tls-gd-noplt.c ++++ b/gcc/testsuite/gcc.target/loongarch/tls-gd-noplt.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* { dg-options "-O0 -fno-plt -mcmodel=normal -mexplicit-relocs" } */ +-/* { dg-final { scan-assembler "pcalau12i\t.*%got_pc_hi20\\(__tls_get_addr\\)\n\tld\.d.*%got_pc_lo12\\(__tls_get_addr\\)" } } */ ++/* { dg-final { scan-assembler "pcalau12i\t.*%got_pc_hi20\\(__tls_get_addr\\)\n\tld\.d.*%got_pc_lo12\\(__tls_get_addr\\)" { target tls_native } } } */ + + __attribute__ ((tls_model ("global-dynamic"))) __thread int a; + +-- +2.33.0 +
View file
_service:tar_scm:Loongarch-Fix-plugin-header-missing-install.patch
Added
@@ -0,0 +1,36 @@ +From ad4371f43e86f7cfe6b543926b2f587a30a8e32f Mon Sep 17 00:00:00 2001 +From: Guo Jie <guojie@loongson.cn> +Date: Wed, 16 Aug 2023 09:48:22 +0800 +Subject: PATCH 049/124 Loongarch: Fix plugin header missing install. + +gcc/ChangeLog: + + * config/loongarch/t-loongarch: Add loongarch-driver.h into + TM_H. Add loongarch-def.h and loongarch-tune.h into + OPTIONS_H_EXTRA. + +Co-authored-by: Lulu Cheng <chenglulu@loongson.cn> +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/t-loongarch | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/gcc/config/loongarch/t-loongarch b/gcc/config/loongarch/t-loongarch +index 6d6e3435d..e73f4f437 100644 +--- a/gcc/config/loongarch/t-loongarch ++++ b/gcc/config/loongarch/t-loongarch +@@ -16,6 +16,10 @@ + # along with GCC; see the file COPYING3. If not see + # <http://www.gnu.org/licenses/>. + ++TM_H += $(srcdir)/config/loongarch/loongarch-driver.h ++OPTIONS_H_EXTRA += $(srcdir)/config/loongarch/loongarch-def.h \ ++ $(srcdir)/config/loongarch/loongarch-tune.h ++ + # Canonical target triplet from config.gcc + LA_MULTIARCH_TRIPLET = $(patsubst LA_MULTIARCH_TRIPLET=%,%,$\ + $(filter LA_MULTIARCH_TRIPLET=%,$(tm_defines))) +-- +2.33.0 +
View file
_service:tar_scm:libffi-Backport-of-LoongArch-support-for-libffi.patch
Added
@@ -0,0 +1,1214 @@ +From aa12adeff7027bff4d03c61f982eb8bbb34f6937 Mon Sep 17 00:00:00 2001 +From: Lulu Cheng <chenglulu@loongson.cn> +Date: Tue, 22 Aug 2023 19:56:21 +0800 +Subject: PATCH 050/124 libffi: Backport of LoongArch support for libffi. + +This is a backport of <https://github.com/libffi/libffi/commit/f259a6f6de>, +and contains modifications to commit 5a4774cd4d, as well as the LoongArch +schema portion of commit ee22ecbd11. This is needed for libgo. + +libffi/ChangeLog: + + PR libffi/108682 + * configure.host: Add LoongArch support. + * Makefile.am: Likewise. + * Makefile.in: Regenerate. + * src/loongarch64/ffi.c: New file. + * src/loongarch64/ffitarget.h: New file. + * src/loongarch64/sysv.S: New file. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + libffi/Makefile.am | 4 +- + libffi/Makefile.in | 25 +- + libffi/configure.host | 5 + + libffi/src/loongarch64/ffi.c | 621 +++++++++++++++++++++++++++++ + libffi/src/loongarch64/ffitarget.h | 82 ++++ + libffi/src/loongarch64/sysv.S | 327 +++++++++++++++ + 6 files changed, 1058 insertions(+), 6 deletions(-) + create mode 100644 libffi/src/loongarch64/ffi.c + create mode 100644 libffi/src/loongarch64/ffitarget.h + create mode 100644 libffi/src/loongarch64/sysv.S + +diff --git a/libffi/Makefile.am b/libffi/Makefile.am +index c6d6f849c..2259ddb75 100644 +--- a/libffi/Makefile.am ++++ b/libffi/Makefile.am +@@ -139,7 +139,7 @@ noinst_HEADERS = src/aarch64/ffitarget.h src/aarch64/internal.h \ + src/sparc/internal.h src/tile/ffitarget.h src/vax/ffitarget.h \ + src/x86/ffitarget.h src/x86/internal.h src/x86/internal64.h \ + src/x86/asmnames.h src/xtensa/ffitarget.h src/dlmalloc.c \ +- src/kvx/ffitarget.h ++ src/kvx/ffitarget.h src/loongarch64/ffitarget.h + + EXTRA_libffi_la_SOURCES = src/aarch64/ffi.c src/aarch64/sysv.S \ + src/aarch64/win64_armasm.S src/alpha/ffi.c src/alpha/osf.S \ +@@ -169,7 +169,7 @@ EXTRA_libffi_la_SOURCES = src/aarch64/ffi.c src/aarch64/sysv.S \ + src/x86/ffiw64.c src/x86/win64.S src/x86/ffi64.c \ + src/x86/unix64.S src/x86/sysv_intel.S src/x86/win64_intel.S \ + src/xtensa/ffi.c src/xtensa/sysv.S src/kvx/ffi.c \ +- src/kvx/sysv.S ++ src/kvx/sysv.S src/loongarch64/ffi.c src/loongarch64/sysv.S + + TARGET_OBJ = @TARGET_OBJ@ + libffi_la_LIBADD = $(TARGET_OBJ) +diff --git a/libffi/Makefile.in b/libffi/Makefile.in +index 5524a6a57..1d936b5c8 100644 +--- a/libffi/Makefile.in ++++ b/libffi/Makefile.in +@@ -550,7 +550,7 @@ noinst_HEADERS = src/aarch64/ffitarget.h src/aarch64/internal.h \ + src/sparc/internal.h src/tile/ffitarget.h src/vax/ffitarget.h \ + src/x86/ffitarget.h src/x86/internal.h src/x86/internal64.h \ + src/x86/asmnames.h src/xtensa/ffitarget.h src/dlmalloc.c \ +- src/kvx/ffitarget.h ++ src/kvx/ffitarget.h src/loongarch64/ffitarget.h + + EXTRA_libffi_la_SOURCES = src/aarch64/ffi.c src/aarch64/sysv.S \ + src/aarch64/win64_armasm.S src/alpha/ffi.c src/alpha/osf.S \ +@@ -580,7 +580,7 @@ EXTRA_libffi_la_SOURCES = src/aarch64/ffi.c src/aarch64/sysv.S \ + src/x86/ffiw64.c src/x86/win64.S src/x86/ffi64.c \ + src/x86/unix64.S src/x86/sysv_intel.S src/x86/win64_intel.S \ + src/xtensa/ffi.c src/xtensa/sysv.S src/kvx/ffi.c \ +- src/kvx/sysv.S ++ src/kvx/sysv.S src/loongarch64/ffi.c src/loongarch64/sysv.S + + libffi_la_LIBADD = $(TARGET_OBJ) + libffi_convenience_la_SOURCES = $(libffi_la_SOURCES) +@@ -1074,6 +1074,16 @@ src/kvx/ffi.lo: src/kvx/$(am__dirstamp) \ + src/kvx/$(DEPDIR)/$(am__dirstamp) + src/kvx/sysv.lo: src/kvx/$(am__dirstamp) \ + src/kvx/$(DEPDIR)/$(am__dirstamp) ++src/loongarch64/$(am__dirstamp): ++ @$(MKDIR_P) src/loongarch64 ++ @: > src/loongarch64/$(am__dirstamp) ++src/loongarch64/$(DEPDIR)/$(am__dirstamp): ++ @$(MKDIR_P) src/loongarch64/$(DEPDIR) ++ @: > src/loongarch64/$(DEPDIR)/$(am__dirstamp) ++src/loongarch64/ffi.lo: src/loongarch64/$(am__dirstamp) \ ++ src/loongarch64/$(DEPDIR)/$(am__dirstamp) ++src/loongarch64/sysv.lo: src/loongarch64/$(am__dirstamp) \ ++ src/loongarch64/$(DEPDIR)/$(am__dirstamp) + + libffi.la: $(libffi_la_OBJECTS) $(libffi_la_DEPENDENCIES) $(EXTRA_libffi_la_DEPENDENCIES) + $(AM_V_CCLD)$(libffi_la_LINK) -rpath $(toolexeclibdir) $(libffi_la_OBJECTS) $(libffi_la_LIBADD) $(LIBS) +@@ -1107,6 +1117,8 @@ mostlyclean-compile: + -rm -f src/ia64/*.lo + -rm -f src/kvx/*.$(OBJEXT) + -rm -f src/kvx/*.lo ++ -rm -f src/loongarch64/*.$(OBJEXT) ++ -rm -f src/loongarch64/*.lo + -rm -f src/m32r/*.$(OBJEXT) + -rm -f src/m32r/*.lo + -rm -f src/m68k/*.$(OBJEXT) +@@ -1182,6 +1194,8 @@ distclean-compile: + @AMDEP_TRUE@@am__include@ @am__quote@src/ia64/$(DEPDIR)/unix.Plo@am__quote@ + @AMDEP_TRUE@@am__include@ @am__quote@src/kvx/$(DEPDIR)/ffi.Plo@am__quote@ + @AMDEP_TRUE@@am__include@ @am__quote@src/kvx/$(DEPDIR)/sysv.Plo@am__quote@ ++@AMDEP_TRUE@@am__include@ @am__quote@src/loongarch64/$(DEPDIR)/ffi.Plo@am__quote@ ++@AMDEP_TRUE@@am__include@ @am__quote@src/loongarch64/$(DEPDIR)/sysv.Plo@am__quote@ + @AMDEP_TRUE@@am__include@ @am__quote@src/m32r/$(DEPDIR)/ffi.Plo@am__quote@ + @AMDEP_TRUE@@am__include@ @am__quote@src/m32r/$(DEPDIR)/sysv.Plo@am__quote@ + @AMDEP_TRUE@@am__include@ @am__quote@src/m68k/$(DEPDIR)/ffi.Plo@am__quote@ +@@ -1308,6 +1322,7 @@ clean-libtool: + -rm -rf src/frv/.libs src/frv/_libs + -rm -rf src/ia64/.libs src/ia64/_libs + -rm -rf src/kvx/.libs src/kvx/_libs ++ -rm -rf src/loongarch64/.libs src/loongarch64/_libs + -rm -rf src/m32r/.libs src/m32r/_libs + -rm -rf src/m68k/.libs src/m68k/_libs + -rm -rf src/m88k/.libs src/m88k/_libs +@@ -1658,6 +1673,8 @@ distclean-generic: + -rm -f src/ia64/$(am__dirstamp) + -rm -f src/kvx/$(DEPDIR)/$(am__dirstamp) + -rm -f src/kvx/$(am__dirstamp) ++ -rm -f src/loongarch64/$(DEPDIR)/$(am__dirstamp) ++ -rm -f src/loongarch64/$(am__dirstamp) + -rm -f src/m32r/$(DEPDIR)/$(am__dirstamp) + -rm -f src/m32r/$(am__dirstamp) + -rm -f src/m68k/$(DEPDIR)/$(am__dirstamp) +@@ -1712,7 +1729,7 @@ clean-am: clean-aminfo clean-generic clean-libtool clean-local \ + + distclean: distclean-recursive + -rm -f $(am__CONFIG_DISTCLEAN_FILES) +- -rm -rf src/$(DEPDIR) src/aarch64/$(DEPDIR) src/alpha/$(DEPDIR) src/arc/$(DEPDIR) src/arm/$(DEPDIR) src/avr32/$(DEPDIR) src/bfin/$(DEPDIR) src/cris/$(DEPDIR) src/csky/$(DEPDIR) src/frv/$(DEPDIR) src/ia64/$(DEPDIR) src/kvx/$(DEPDIR) src/m32r/$(DEPDIR) src/m68k/$(DEPDIR) src/m88k/$(DEPDIR) src/metag/$(DEPDIR) src/microblaze/$(DEPDIR) src/mips/$(DEPDIR) src/moxie/$(DEPDIR) src/nios2/$(DEPDIR) src/or1k/$(DEPDIR) src/pa/$(DEPDIR) src/powerpc/$(DEPDIR) src/riscv/$(DEPDIR) src/s390/$(DEPDIR) src/sh/$(DEPDIR) src/sh64/$(DEPDIR) src/sparc/$(DEPDIR) src/tile/$(DEPDIR) src/vax/$(DEPDIR) src/x86/$(DEPDIR) src/xtensa/$(DEPDIR) ++ -rm -rf src/$(DEPDIR) src/aarch64/$(DEPDIR) src/alpha/$(DEPDIR) src/arc/$(DEPDIR) src/arm/$(DEPDIR) src/avr32/$(DEPDIR) src/bfin/$(DEPDIR) src/cris/$(DEPDIR) src/csky/$(DEPDIR) src/frv/$(DEPDIR) src/ia64/$(DEPDIR) src/kvx/$(DEPDIR) src/loongarch64/$(DEPDIR) src/m32r/$(DEPDIR) src/m68k/$(DEPDIR) src/m88k/$(DEPDIR) src/metag/$(DEPDIR) src/microblaze/$(DEPDIR) src/mips/$(DEPDIR) src/moxie/$(DEPDIR) src/nios2/$(DEPDIR) src/or1k/$(DEPDIR) src/pa/$(DEPDIR) src/powerpc/$(DEPDIR) src/riscv/$(DEPDIR) src/s390/$(DEPDIR) src/sh/$(DEPDIR) src/sh64/$(DEPDIR) src/sparc/$(DEPDIR) src/tile/$(DEPDIR) src/vax/$(DEPDIR) src/x86/$(DEPDIR) src/xtensa/$(DEPDIR) + -rm -f Makefile + distclean-am: clean-am distclean-compile distclean-generic \ + distclean-hdr distclean-libtool distclean-local distclean-tags +@@ -1851,7 +1868,7 @@ installcheck-am: + maintainer-clean: maintainer-clean-recursive + -rm -f $(am__CONFIG_DISTCLEAN_FILES) + -rm -rf $(top_srcdir)/autom4te.cache +- -rm -rf src/$(DEPDIR) src/aarch64/$(DEPDIR) src/alpha/$(DEPDIR) src/arc/$(DEPDIR) src/arm/$(DEPDIR) src/avr32/$(DEPDIR) src/bfin/$(DEPDIR) src/cris/$(DEPDIR) src/csky/$(DEPDIR) src/frv/$(DEPDIR) src/ia64/$(DEPDIR) src/kvx/$(DEPDIR) src/m32r/$(DEPDIR) src/m68k/$(DEPDIR) src/m88k/$(DEPDIR) src/metag/$(DEPDIR) src/microblaze/$(DEPDIR) src/mips/$(DEPDIR) src/moxie/$(DEPDIR) src/nios2/$(DEPDIR) src/or1k/$(DEPDIR) src/pa/$(DEPDIR) src/powerpc/$(DEPDIR) src/riscv/$(DEPDIR) src/s390/$(DEPDIR) src/sh/$(DEPDIR) src/sh64/$(DEPDIR) src/sparc/$(DEPDIR) src/tile/$(DEPDIR) src/vax/$(DEPDIR) src/x86/$(DEPDIR) src/xtensa/$(DEPDIR) ++ -rm -rf src/$(DEPDIR) src/aarch64/$(DEPDIR) src/alpha/$(DEPDIR) src/arc/$(DEPDIR) src/arm/$(DEPDIR) src/avr32/$(DEPDIR) src/bfin/$(DEPDIR) src/cris/$(DEPDIR) src/csky/$(DEPDIR) src/frv/$(DEPDIR) src/ia64/$(DEPDIR) src/kvx/$(DEPDIR) src/loongarch64/$(DEPDIR) src/m32r/$(DEPDIR) src/m68k/$(DEPDIR) src/m88k/$(DEPDIR) src/metag/$(DEPDIR) src/microblaze/$(DEPDIR) src/mips/$(DEPDIR) src/moxie/$(DEPDIR) src/nios2/$(DEPDIR) src/or1k/$(DEPDIR) src/pa/$(DEPDIR) src/powerpc/$(DEPDIR) src/riscv/$(DEPDIR) src/s390/$(DEPDIR) src/sh/$(DEPDIR) src/sh64/$(DEPDIR) src/sparc/$(DEPDIR) src/tile/$(DEPDIR) src/vax/$(DEPDIR) src/x86/$(DEPDIR) src/xtensa/$(DEPDIR) + -rm -f Makefile + maintainer-clean-am: distclean-am maintainer-clean-aminfo \ + maintainer-clean-generic maintainer-clean-local \ +diff --git a/libffi/configure.host b/libffi/configure.host +index 268267183..9d73f18ee 100644 +--- a/libffi/configure.host ++++ b/libffi/configure.host +@@ -140,6 +140,11 @@ case "${host}" in + SOURCES="ffi.c sysv.S" + ;; + ++ loongarch64-*-*) ++ TARGET=LOONGARCH64; TARGETDIR=loongarch64 ++ SOURCES="ffi.c sysv.S" ++ ;; ++ + m32r*-*-*) + TARGET=M32R; TARGETDIR=m32r + SOURCES="ffi.c sysv.S" +diff --git a/libffi/src/loongarch64/ffi.c b/libffi/src/loongarch64/ffi.c +new file mode 100644 +index 000000000..140be3bc3 +--- /dev/null ++++ b/libffi/src/loongarch64/ffi.c +@@ -0,0 +1,621 @@ ++/* ----------------------------------------------------------------------- ++ ffi.c - Copyright (c) 2022 Xu Chenghua <xuchenghua@loongson.cn> ++ 2022 Cheng Lulu <chenglulu@loongson.cn> ++ Based on RISC-V port ++ ++ LoongArch Foreign Function Interface ++ ++ Permission is hereby granted, free of charge, to any person obtaining ++ a copy of this software and associated documentation files (the ++ ``Software''), to deal in the Software without restriction, including ++ without limitation the rights to use, copy, modify, merge, publish, ++ distribute, sublicense, and/or sell copies of the Software, and to ++ permit persons to whom the Software is furnished to do so, subject to ++ the following conditions: ++ ++ The above copyright notice and this permission notice shall be included ++ in all copies or substantial portions of the Software. ++ ++ THE SOFTWARE IS PROVIDED ``AS IS'', WITHOUT WARRANTY OF ANY KIND, ++ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER ++ DEALINGS IN THE SOFTWARE. ++ ----------------------------------------------------------------------- */ ++ ++#include <ffi.h> ++#include <ffi_common.h>
View file
_service:tar_scm:libjccjit-do-not-link-objects-contained-same-element.patch
Added
@@ -0,0 +1,44 @@ +From 579464905cd757f219344d657f8929ecfa33c0e2 Mon Sep 17 00:00:00 2001 +From: Peng Fan <fanpeng@loongson.cn> +Date: Fri, 28 Jul 2023 09:58:05 +0800 +Subject: PATCH 2/3 libjccjit: do not link objects contained same element + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/jit/Make-lang.in | 9 +++++++-- + 1 file changed, 7 insertions(+), 2 deletions(-) + +diff --git a/gcc/jit/Make-lang.in b/gcc/jit/Make-lang.in +index 6e10abfd0..7f53304d9 100644 +--- a/gcc/jit/Make-lang.in ++++ b/gcc/jit/Make-lang.in +@@ -157,18 +157,23 @@ LIBGCCJIT_EXTRA_OPTS = $(LIBGCCJIT_VERSION_SCRIPT_OPTION) \ + endif + endif + ++# Only link objects from $(EXTRA_GCC_OBJS) that's not already ++# included in libbackend.a ($(EXTRA_OBJS)). ++EXTRA_GCC_OBJS_EXCLUSIVE = $(foreach _obj1, $(EXTRA_GCC_OBJS), \ ++ $(if $(filter $(_obj1), $(EXTRA_OBJS)),, $(_obj1))) ++ + # We avoid using $(BACKEND) from Makefile.in in order to avoid pulling + # in main.o + $(LIBGCCJIT_FILENAME): $(jit_OBJS) \ + libbackend.a libcommon-target.a libcommon.a \ + $(CPPLIB) $(LIBDECNUMBER) \ + $(LIBDEPS) $(srcdir)/jit/libgccjit.map \ +- $(EXTRA_GCC_OBJS) $(jit.prev) ++ $(EXTRA_GCC_OBJS_EXCLUSIVE) $(jit.prev) + @$(call LINK_PROGRESS,$(INDEX.jit),start) + +$(LLINKER) $(ALL_LINKERFLAGS) $(LDFLAGS) -o $@ -shared \ + $(jit_OBJS) libbackend.a libcommon-target.a libcommon.a \ + $(CPPLIB) $(LIBDECNUMBER) $(EXTRA_GCC_LIBS) $(LIBS) $(BACKENDLIBS) \ +- $(EXTRA_GCC_OBJS) \ ++ $(EXTRA_GCC_OBJS_EXCLUSIVE) \ + $(LIBGCCJIT_EXTRA_OPTS) + @$(call LINK_PROGRESS,$(INDEX.jit),end) + +-- +2.33.0 +
View file
_service:tar_scm:libsanitizer-add-LoongArch-support.patch
Added
@@ -0,0 +1,1372 @@ +From e9ff5810cfbc76b24adefcfd024d69c19789119c Mon Sep 17 00:00:00 2001 +From: ticat_fp <fanpeng@loongson.cn> +Date: Wed, 28 Feb 2024 15:13:42 +0800 +Subject: PATCH 124/124 libsanitizer: add LoongArch support + +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + libsanitizer/asan/asan_interceptors.h | 2 +- + libsanitizer/asan/asan_interceptors_vfork.S | 1 + + libsanitizer/asan/asan_mapping.h | 3 + + libsanitizer/configure.tgt | 7 + + libsanitizer/lsan/lsan_allocator.h | 3 +- + libsanitizer/lsan/lsan_common.cpp | 4 + + .../sanitizer_common/sanitizer_common.h | 3 + + ...ommon_interceptors_vfork_loongarch64.inc.S | 57 +++++ + .../sanitizer_common_syscalls.inc | 4 +- + .../sanitizer_common/sanitizer_linux.cpp | 111 +++++++++- + .../sanitizer_common/sanitizer_linux.h | 2 +- + .../sanitizer_linux_libcdep.cpp | 19 +- + .../sanitizer_common/sanitizer_platform.h | 10 +- + .../sanitizer_platform_limits_linux.cpp | 3 +- + .../sanitizer_platform_limits_posix.cpp | 13 +- + .../sanitizer_platform_limits_posix.h | 7 +- + .../sanitizer_common/sanitizer_stacktrace.cpp | 4 +- + .../sanitizer_stoptheworld_linux_libcdep.cpp | 11 +- + .../sanitizer_symbolizer_libcdep.cpp | 2 + + .../sanitizer_syscall_linux_loongarch64.inc | 171 +++++++++++++++ + ...ommon_interceptors_vfork_loongarch64.inc.S | 57 +++++ + libsanitizer/tsan/Makefile.am | 2 +- + libsanitizer/tsan/Makefile.in | 3 +- + libsanitizer/tsan/tsan_interceptors_posix.cpp | 2 + + libsanitizer/tsan/tsan_platform.h | 55 +++++ + libsanitizer/tsan/tsan_platform_linux.cpp | 21 +- + libsanitizer/tsan/tsan_rtl.h | 3 +- + libsanitizer/tsan/tsan_rtl_loongarch64.S | 196 ++++++++++++++++++ + 28 files changed, 749 insertions(+), 27 deletions(-) + create mode 100644 libsanitizer/sanitizer_common/sanitizer_common_interceptors_vfork_loongarch64.inc.S + create mode 100644 libsanitizer/sanitizer_common/sanitizer_syscall_linux_loongarch64.inc + create mode 100644 libsanitizer/sanitizer_common_interceptors_vfork_loongarch64.inc.S + create mode 100644 libsanitizer/tsan/tsan_rtl_loongarch64.S + +diff --git a/libsanitizer/asan/asan_interceptors.h b/libsanitizer/asan/asan_interceptors.h +index 105c672cc..c5534d7f6 100644 +--- a/libsanitizer/asan/asan_interceptors.h ++++ b/libsanitizer/asan/asan_interceptors.h +@@ -119,7 +119,7 @@ void InitializePlatformInterceptors(); + + #if SANITIZER_LINUX && \ + (defined(__arm__) || defined(__aarch64__) || defined(__i386__) || \ +- defined(__x86_64__) || SANITIZER_RISCV64) ++ defined(__x86_64__) || SANITIZER_RISCV64 || SANITIZER_LOONGARCH64) + # define ASAN_INTERCEPT_VFORK 1 + #else + # define ASAN_INTERCEPT_VFORK 0 +diff --git a/libsanitizer/asan/asan_interceptors_vfork.S b/libsanitizer/asan/asan_interceptors_vfork.S +index 3ae5503e8..ec29adc7b 100644 +--- a/libsanitizer/asan/asan_interceptors_vfork.S ++++ b/libsanitizer/asan/asan_interceptors_vfork.S +@@ -6,6 +6,7 @@ + #include "sanitizer_common/sanitizer_common_interceptors_vfork_aarch64.inc.S" + #include "sanitizer_common/sanitizer_common_interceptors_vfork_arm.inc.S" + #include "sanitizer_common/sanitizer_common_interceptors_vfork_i386.inc.S" ++#include "sanitizer_common/sanitizer_common_interceptors_vfork_loongarch64.inc.S" + #include "sanitizer_common/sanitizer_common_interceptors_vfork_riscv64.inc.S" + #include "sanitizer_common/sanitizer_common_interceptors_vfork_x86_64.inc.S" + #endif +diff --git a/libsanitizer/asan/asan_mapping.h b/libsanitizer/asan/asan_mapping.h +index 4b0037fce..6d89a9352 100644 +--- a/libsanitizer/asan/asan_mapping.h ++++ b/libsanitizer/asan/asan_mapping.h +@@ -173,6 +173,7 @@ static const u64 kFreeBSD_ShadowOffset64 = 1ULL << 46; // 0x400000000000 + static const u64 kNetBSD_ShadowOffset32 = 1ULL << 30; // 0x40000000 + static const u64 kNetBSD_ShadowOffset64 = 1ULL << 46; // 0x400000000000 + static const u64 kWindowsShadowOffset32 = 3ULL << 28; // 0x30000000 ++static const u64 kLoongArch64_ShadowOffset64 = 0x0000400000000000; + + #define SHADOW_SCALE kDefaultShadowScale + +@@ -217,6 +218,8 @@ static const u64 kWindowsShadowOffset32 = 3ULL << 28; // 0x30000000 + # define SHADOW_OFFSET kMIPS64_ShadowOffset64 + #elif defined(__sparc__) + #define SHADOW_OFFSET kSPARC64_ShadowOffset64 ++#elif defined(__loongarch__) ++# define SHADOW_OFFSET kLoongArch64_ShadowOffset64 + # elif SANITIZER_WINDOWS64 + # define SHADOW_OFFSET __asan_shadow_memory_dynamic_address + # else +diff --git a/libsanitizer/configure.tgt b/libsanitizer/configure.tgt +index fb89df493..9d42662d3 100644 +--- a/libsanitizer/configure.tgt ++++ b/libsanitizer/configure.tgt +@@ -72,6 +72,13 @@ case "${target}" in + ;; + riscv64-*-linux*) + ;; ++ loongarch64-*-linux*) ++ if test x$ac_cv_sizeof_void_p = x8; then ++ TSAN_SUPPORTED=yes ++ LSAN_SUPPORTED=yes ++ TSAN_TARGET_DEPENDENT_OBJECTS=tsan_rtl_loongarch64.lo ++ fi ++ ;; + *) + UNSUPPORTED=1 + ;; +diff --git a/libsanitizer/lsan/lsan_allocator.h b/libsanitizer/lsan/lsan_allocator.h +index 45c6ac406..dc9a02b19 100644 +--- a/libsanitizer/lsan/lsan_allocator.h ++++ b/libsanitizer/lsan/lsan_allocator.h +@@ -50,7 +50,8 @@ struct ChunkMetadata { + }; + + #if defined(__mips64) || defined(__aarch64__) || defined(__i386__) || \ +- defined(__arm__) || SANITIZER_RISCV64 || defined(__hexagon__) ++ defined(__arm__) || SANITIZER_RISCV64 || defined(__hexagon__) || \ ++ defined(__loongarch__) + template <typename AddressSpaceViewTy> + struct AP32 { + static const uptr kSpaceBeg = 0; +diff --git a/libsanitizer/lsan/lsan_common.cpp b/libsanitizer/lsan/lsan_common.cpp +index 308dbb3e4..9a78ed92c 100644 +--- a/libsanitizer/lsan/lsan_common.cpp ++++ b/libsanitizer/lsan/lsan_common.cpp +@@ -167,6 +167,10 @@ static inline bool CanBeAHeapPointer(uptr p) { + unsigned runtimeVMA = + (MostSignificantSetBitIndex(GET_CURRENT_FRAME()) + 1); + return ((p >> runtimeVMA) == 0); ++#elif defined(__loongarch_lp64) ++ // Allow 47-bit user-space VMA at current. ++ return ((p >> 47) == 0); ++ + #else + return true; + #endif +diff --git a/libsanitizer/sanitizer_common/sanitizer_common.h b/libsanitizer/sanitizer_common/sanitizer_common.h +index 065154496..5f68e4994 100644 +--- a/libsanitizer/sanitizer_common/sanitizer_common.h ++++ b/libsanitizer/sanitizer_common/sanitizer_common.h +@@ -696,6 +696,7 @@ enum ModuleArch { + kModuleArchARMV7S, + kModuleArchARMV7K, + kModuleArchARM64, ++ kModuleArchLoongArch64, + kModuleArchRISCV64, + kModuleArchHexagon + }; +@@ -765,6 +766,8 @@ inline const char *ModuleArchToString(ModuleArch arch) { + return "armv7k"; + case kModuleArchARM64: + return "arm64"; ++ case kModuleArchLoongArch64: ++ return "loongarch64"; + case kModuleArchRISCV64: + return "riscv64"; + case kModuleArchHexagon: +diff --git a/libsanitizer/sanitizer_common/sanitizer_common_interceptors_vfork_loongarch64.inc.S b/libsanitizer/sanitizer_common/sanitizer_common_interceptors_vfork_loongarch64.inc.S +new file mode 100644 +index 000000000..dae72b5ac +--- /dev/null ++++ b/libsanitizer/sanitizer_common/sanitizer_common_interceptors_vfork_loongarch64.inc.S +@@ -0,0 +1,57 @@ ++#if defined(__loongarch64) && defined(__linux__) ++ ++#include "sanitizer_common/sanitizer_asm.h" ++ ++ASM_HIDDEN(COMMON_INTERCEPTOR_SPILL_AREA) ++ASM_HIDDEN(_ZN14__interception10real_vforkE) ++ ++.text ++.globl ASM_WRAPPER_NAME(vfork) ++ASM_TYPE_FUNCTION(ASM_WRAPPER_NAME(vfork)) ++ASM_WRAPPER_NAME(vfork): ++ // Save ra in the off-stack spill area. ++ // allocate space on stack ++ addi.d $sp, $sp, -16 ++ // store $ra value ++ st.d $ra, $sp, 8 ++ bl COMMON_INTERCEPTOR_SPILL_AREA ++ // restore previous values from stack ++ ld.d $ra, $sp, 8 ++ // adjust stack ++ addi.d $sp, $sp, 16 ++ // store $ra by $a0 ++ st.d $ra, $a0, 0 ++ ++ // Call real vfork. This may return twice. User code that runs between the first and the second return ++ // may clobber the stack frame of the interceptor; that's why it does not have a frame. ++ la.local $a0, _ZN14__interception10real_vforkE ++ ld.d $a0, $a0, 0 ++ jirl $ra, $a0, 0 ++ ++ // adjust stack ++ addi.d $sp, $sp, -16 ++ // store $a0 by adjusted stack ++ st.d $a0, $sp, 8 ++ // jump to exit label if $a0 is 0 ++ beqz $a0, .L_exit ++ ++ // $a0 != 0 => parent process. Clear stack shadow.
View file
_service:tar_scm:loongarch-add-alternatives-for-idiv-insns-to-improve.patch
Added
@@ -0,0 +1,184 @@ +From 03a6da5290c60437a0fc97347bb84c120c26cc58 Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao <xry111@xry111.site> +Date: Wed, 6 Jul 2022 13:45:55 +0800 +Subject: PATCH 001/124 loongarch: add alternatives for idiv insns to improve + code generation + +Currently in the description of LoongArch integer division instructions, +the output is marked as earlyclobbered ('&'). It's necessary when +loongarch_check_zero_div_p() because clobbering operand 2 (divisor) will +make the checking for zero divisor impossible. + +But, for -mno-check-zero-division (the default of GCC >= 12.2 for +optimized code), the output is not earlyclobbered at all. And, the +read of operand 1 only occurs before clobbering the output. So we make +three alternatives for an idiv instruction: + +* (=r,r,r): For -mno-check-zero-division. +* (=&r,r,r): For -mcheck-zero-division. +* (=&r,0,r): For -mcheck-zero-division, to explicitly allow patterns + like "div.d $a0, $a0, $a1". + +gcc/ChangeLog: + + * config/loongarch/loongarch.cc (loongarch_check_zero_div_p): + Remove static, for use in the machine description file. + * config/loongarch/loongarch-protos.h: + (loongarch_check_zero_div_p): Add prototype. + * config/loongarch/loongarch.md (enabled): New attr. + (*<optab><mode>3): Add (=r,r,r) and (=&r,0,r) alternatives for + idiv. Conditionally enable the alternatives using + loongarch_check_zero_div_p. + (<optab>di3_fake): Likewise. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/div-1.c: New test. + * gcc.target/loongarch/div-2.c: New test. + * gcc.target/loongarch/div-3.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/loongarch-protos.h | 1 + + gcc/config/loongarch/loongarch.cc | 2 +- + gcc/config/loongarch/loongarch.md | 28 +++++++++++++++------- + gcc/testsuite/gcc.target/loongarch/div-1.c | 9 +++++++ + gcc/testsuite/gcc.target/loongarch/div-2.c | 9 +++++++ + gcc/testsuite/gcc.target/loongarch/div-3.c | 9 +++++++ + 6 files changed, 49 insertions(+), 9 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/loongarch/div-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/div-2.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/div-3.c + +diff --git a/gcc/config/loongarch/loongarch-protos.h b/gcc/config/loongarch/loongarch-protos.h +index 2144c2421..2287fd376 100644 +--- a/gcc/config/loongarch/loongarch-protos.h ++++ b/gcc/config/loongarch/loongarch-protos.h +@@ -130,6 +130,7 @@ extern bool loongarch_symbol_binds_local_p (const_rtx); + extern const char *current_section_name (void); + extern unsigned int current_section_flags (void); + extern bool loongarch_use_ins_ext_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT); ++extern bool loongarch_check_zero_div_p (void); + + union loongarch_gen_fn_ptrs + { +diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc +index 22901cb61..750d53bbe 100644 +--- a/gcc/config/loongarch/loongarch.cc ++++ b/gcc/config/loongarch/loongarch.cc +@@ -2110,7 +2110,7 @@ loongarch_load_store_insns (rtx mem, rtx_insn *insn) + + /* Return true if we need to trap on division by zero. */ + +-static bool ++bool + loongarch_check_zero_div_p (void) + { + /* if -mno-check-zero-division is given explicitly. */ +diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md +index 8f8412fba..6bca2ed39 100644 +--- a/gcc/config/loongarch/loongarch.md ++++ b/gcc/config/loongarch/loongarch.md +@@ -110,6 +110,8 @@ + ;; + ;; .................... + ++(define_attr "enabled" "no,yes" (const_string "yes")) ++ + (define_attr "got" "unset,load" + (const_string "unset")) + +@@ -763,26 +765,36 @@ + }) + + (define_insn "*<optab><mode>3" +- (set (match_operand:GPR 0 "register_operand" "=&r") +- (any_div:GPR (match_operand:GPR 1 "register_operand" "r") +- (match_operand:GPR 2 "register_operand" "r"))) ++ (set (match_operand:GPR 0 "register_operand" "=r,&r,&r") ++ (any_div:GPR (match_operand:GPR 1 "register_operand" "r,r,0") ++ (match_operand:GPR 2 "register_operand" "r,r,r"))) + "" + { + return loongarch_output_division ("<insn>.<d><u>\t%0,%1,%2", operands); + } + (set_attr "type" "idiv") +- (set_attr "mode" "<MODE>")) ++ (set_attr "mode" "<MODE>") ++ (set (attr "enabled") ++ (if_then_else ++ (match_test "!!which_alternative == loongarch_check_zero_div_p()") ++ (const_string "yes") ++ (const_string "no")))) + + (define_insn "<optab>di3_fake" +- (set (match_operand:SI 0 "register_operand" "=&r") +- (any_div:SI (match_operand:DI 1 "register_operand" "r") +- (match_operand:DI 2 "register_operand" "r"))) ++ (set (match_operand:SI 0 "register_operand" "=r,&r,&r") ++ (any_div:SI (match_operand:DI 1 "register_operand" "r,r,0") ++ (match_operand:DI 2 "register_operand" "r,r,r"))) + "" + { + return loongarch_output_division ("<insn>.w<u>\t%0,%1,%2", operands); + } + (set_attr "type" "idiv") +- (set_attr "mode" "SI")) ++ (set_attr "mode" "SI") ++ (set (attr "enabled") ++ (if_then_else ++ (match_test "!!which_alternative == loongarch_check_zero_div_p()") ++ (const_string "yes") ++ (const_string "no")))) + + ;; Floating point multiply accumulate instructions. + +diff --git a/gcc/testsuite/gcc.target/loongarch/div-1.c b/gcc/testsuite/gcc.target/loongarch/div-1.c +new file mode 100644 +index 000000000..b1683f853 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/div-1.c +@@ -0,0 +1,9 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -mcheck-zero-division" } */ ++/* { dg-final { scan-assembler "div.\wd\\t\\\$r4,\\\$r4,\\\$r5" } } */ ++ ++long ++div(long a, long b) ++{ ++ return a / b; ++} +diff --git a/gcc/testsuite/gcc.target/loongarch/div-2.c b/gcc/testsuite/gcc.target/loongarch/div-2.c +new file mode 100644 +index 000000000..4c2beb5b9 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/div-2.c +@@ -0,0 +1,9 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -mno-check-zero-division" } */ ++/* { dg-final { scan-assembler "div.\wd\\t\\\$r4,\\\$r5,\\\$r4" } } */ ++ ++long ++div(long a, long b) ++{ ++ return b / a; ++} +diff --git a/gcc/testsuite/gcc.target/loongarch/div-3.c b/gcc/testsuite/gcc.target/loongarch/div-3.c +new file mode 100644 +index 000000000..d25969263 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/div-3.c +@@ -0,0 +1,9 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -mcheck-zero-division" } */ ++/* { dg-final { scan-assembler-not "div.\wd\\t\\\$r4,\\\$r5,\\\$r4" } } */ ++ ++long ++div(long a, long b) ++{ ++ return b / a; ++} +-- +2.33.0 +
View file
_service:tar_scm:loongarch-avoid-unnecessary-sign-extend-after-32-bit.patch
Added
@@ -0,0 +1,102 @@ +From f69237e2e7d129e680fc0bd6a79c53aa193f2ef0 Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao <xry111@xry111.site> +Date: Wed, 6 Jul 2022 23:22:29 +0800 +Subject: PATCH 002/124 loongarch: avoid unnecessary sign-extend after 32-bit + division + +Like add.w/sub.w/mul.w, div.w/mod.w/div.wu/mod.wu also sign-extend the +output on LA64. But, LoongArch v1.00 mandates that the inputs of 32-bit +division to be sign-extended so we have to expand 32-bit division into +RTL sequences. + +We defined div.w/mod.w/div.wu/mod.wu as a (DI, DI) -> SI instruction. +This definition does not indicate the fact that these instructions will +store the result as sign-extended value in a 64-bit GR. Then the +compiler would emit unnecessary sign-extend operations. For example: + + int div(int a, int b) { return a / b; } + +was compiled to: + + div.w $r4, $r4, $r5 + slli.w $r4, $r4, 0 # this is unnecessary + jr $r1 + +To remove this unnecessary operation, we change the division +instructions to (DI, DI) -> DI and describe the sign-extend behavior +explicitly in the RTL template. In the expander for 32-bit division we +then use simplify_gen_subreg to extract the lower 32 bits. + +gcc/ChangeLog: + + * config/loongarch/loongarch.md (<any_div>di3_fake): Describe + the sign-extend of result in the RTL template. + (<any_div><mode>3): Adjust for <any_div>di3_fake change. + +gcc/testsuite/ChangeLog: + + * gcc.target/loongarch/div-4.c: New test. + +Signed-off-by: Peng Fan <fanpeng@loongson.cn> +Signed-off-by: ticat_fp <fanpeng@loongson.cn> +--- + gcc/config/loongarch/loongarch.md | 12 ++++++++---- + gcc/testsuite/gcc.target/loongarch/div-4.c | 9 +++++++++ + 2 files changed, 17 insertions(+), 4 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/loongarch/div-4.c + +diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md +index 6bca2ed39..5c0445dd8 100644 +--- a/gcc/config/loongarch/loongarch.md ++++ b/gcc/config/loongarch/loongarch.md +@@ -752,6 +752,7 @@ + { + rtx reg1 = gen_reg_rtx (DImode); + rtx reg2 = gen_reg_rtx (DImode); ++ rtx rd = gen_reg_rtx (DImode); + + operands1 = gen_rtx_SIGN_EXTEND (word_mode, operands1); + operands2 = gen_rtx_SIGN_EXTEND (word_mode, operands2); +@@ -759,7 +760,9 @@ + emit_insn (gen_rtx_SET (reg1, operands1)); + emit_insn (gen_rtx_SET (reg2, operands2)); + +- emit_insn (gen_<optab>di3_fake (operands0, reg1, reg2)); ++ emit_insn (gen_<optab>di3_fake (rd, reg1, reg2)); ++ emit_insn (gen_rtx_SET (operands0, ++ simplify_gen_subreg (SImode, rd, DImode, 0))); + DONE; + } + }) +@@ -781,9 +784,10 @@ + (const_string "no")))) + + (define_insn "<optab>di3_fake" +- (set (match_operand:SI 0 "register_operand" "=r,&r,&r") +- (any_div:SI (match_operand:DI 1 "register_operand" "r,r,0") +- (match_operand:DI 2 "register_operand" "r,r,r"))) ++ (set (match_operand:DI 0 "register_operand" "=r,&r,&r") ++ (sign_extend:DI ++ (any_div:SI (match_operand:DI 1 "register_operand" "r,r,0") ++ (match_operand:DI 2 "register_operand" "r,r,r")))) + "" + { + return loongarch_output_division ("<insn>.w<u>\t%0,%1,%2", operands); +diff --git a/gcc/testsuite/gcc.target/loongarch/div-4.c b/gcc/testsuite/gcc.target/loongarch/div-4.c +new file mode 100644 +index 000000000..a52f87d6c +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/div-4.c +@@ -0,0 +1,9 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2" } */ ++/* { dg-final { scan-assembler-not "slli" } } */ ++ ++int ++div(int a, int b) ++{ ++ return a / b; ++} +-- +2.33.0 +
View file
_service
Changed
@@ -1,6 +1,6 @@ <services> <service name="tar_scm"> - <param name="url">git@gitee.com:src-openeuler/gcc.git</param> + <param name="url">git@gitee.com:luofeng14/gcc.git</param> <param name="scm">git</param> <param name="revision">master</param> <param name="exclude">*</param>
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