开源软件构建与测试

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Changes of Revision 3

_service:tar_scm:dav1d.spec Added

@@ -0,0 +1,72 @@
+Name:           dav1d
+Version:        1.5.0
+Release:        1
+Summary:        AV1 cross-platform Decoder
+
+License:        BSD
+URL:            https://code.videolan.org/videolan/dav1d
+Source0:        %{url}/-/archive/%{version}/%{name}-%{version}.tar.bz2
+
+BuildRequires:  gcc nasm doxygen
+BuildRequires:  meson >= 0.49.0
+
+%description
+dav1d is a new AV1 cross-platform Decoder, open-source, and focused on speed
+and correctness.
+
+%package -n libdav1d
+Summary:        Library files for dav1d
+
+%description -n libdav1d
+Library files for dav1d, the AV1 cross-platform Decoder.
+
+%package -n libdav1d-devel
+Summary:        Development files for dav1d
+Requires:       libdav1d%{?_isa} = %{version}-%{release}
+
+%description -n libdav1d-devel
+Development files for dav1d, the AV1 cross-platform Decoder.
+
+%prep
+%autosetup -p1 -n %{name}-%{version}
+
+%build
+%meson --buildtype=release
+
+%meson_build
+%ninja_build -C %{_vpath_builddir} doc/html
+
+%install
+%meson_install
+
+%check
+%meson_test
+
+%files
+%license COPYING doc/PATENTS
+%doc CONTRIBUTING.md NEWS README.md
+%{_bindir}/dav1d
+
+%files -n libdav1d
+%license COPYING doc/PATENTS
+%{_libdir}/libdav1d.so.3*
+
+%files -n libdav1d-devel
+%doc %{_host_alias}/doc/html
+%{_includedir}/%{name}
+%{_libdir}/libdav1d.so
+%{_libdir}/pkgconfig/%{name}.pc
+
+%changelog
+* Tue Nov 5 2024 shafeipaozi <sunbo.oerv@isrc.iscas.ac.cn> - 1.5.0-1
+- update
+
+* Mon Jun 20 2022 zhangfan <zhangfan4@kylinos.cn> - 0.5.2-3
+- Update Source0
+
+* Sat Jun 26 2021 caodongxia <caodongxia@huawei.com> - 0.5.2-2
+- Fix doc/html build method.
+
+* Fri May 07 2021 weidong <weidong@uniontech.com> - 0.5.2-1
+- Initial package.
+

_service:tar_scm:llvm.spec Deleted

@@ -1,515 +0,0 @@
-%bcond_without sys_llvm
-%bcond_without check
-%bcond_with classic_flang
-%bcond_with toolchain_clang
-%bcond_without bisheng_autotuner
-
-%if %{with toolchain_clang}
-%global toolchain clang
-%endif
-
-%global maj_ver 17
-%global min_ver 0
-%global patch_ver 6
-
-%if %{with sys_llvm}
-%global pkg_name llvm
-%global install_prefix %{_prefix}
-%global install_datadir %{_datadir}
-%else
-%global pkg_name llvm%{maj_ver}
-%global install_prefix %{_libdir}/%{name}
-%global install_datadir %{install_prefix}/share
-%endif
-
-%global install_bindir %{install_prefix}/bin
-%global install_includedir %{install_prefix}/include
-%if 0%{?__isa_bits} == 64
-%global install_libdir %{install_prefix}/lib64
-%else
-%global install_libdir %{install_prefix}/lib
-%endif
-%global install_srcdir %{install_prefix}/src
-%global install_docdir %{install_prefix}/share/doc
-
-%global max_link_jobs %{_smp_build_ncpus}
-%global targets_to_build "all"
-%global experimental_targets_to_build ""
-
-%global build_install_prefix %{buildroot}%{install_prefix}
-%global llvm_triple %{_host}
-
-# Disable LTO as this causes crash if gcc lto enabled.
-%define _lto_cflags %{nil}
-
-Name:		%{pkg_name}
-Version:	%{maj_ver}.%{min_ver}.%{patch_ver}
-Release:	13
-Summary:	The Low Level Virtual Machine
-
-License:	NCSA
-URL:		http://llvm.org
-Source0:	https://github.com/llvm/llvm-project/releases/download/llvmorg-%{version}/llvm-%{version}.src.tar.xz
-Source1:	https://github.com/llvm/llvm-project/releases/download/llvmorg-%{version}/cmake-%{version}.src.tar.xz
-Source2:	https://github.com/llvm/llvm-project/releases/download/llvmorg-%{version}/third-party-%{version}.src.tar.xz
-
-# Patch{1-10} for supporting `relax` feture on LoongArch, which is consistent with !47 in openEuler repos
-Patch1: 	0001-Backport-LoongArch-Add-relax-feature-and-keep-relocations.patch
-Patch2: 	0002-Backport-LoongArch-Allow-delayed-decision-for-ADD-SUB-relocations.patch
-Patch3: 	0003-Backport-LoongArch-Emit-R_LARCH_RELAX-when-expanding-some-LoadAddress.patch
-Patch4: 	0004-Backport-MC-LoongArch-Add-AlignFragment-size-if-layout-is-available-and-not-need-insert-nops.patch
-Patch5: 	0005-Backport-LoongArch-RISCV-Support-R_LARCH_-ADD-SUB-_ULEB128-R_RISCV_-SET-SUB-_ULEB128-for-uleb128-directives.patch
-Patch6: 	0006-Backport-LoongArch-Add-relaxDwarfLineAddr-and-relaxDwarfCFA-to-handle-the-mutable-label-diff-in-dwarfinfo.patch
-Patch7: 	0007-Backport-LoongArch-Insert-nops-and-emit-align-reloc-when-handle-alignment-directive.patch
-Patch8: 	0008-Backport-test-Update-dwarf-loongarch-relocs.ll.patch
-Patch9: 	0009-Backport-MC-test-Change-ELF-uleb-ehtable.s-Mach-O-to-use-private-symbols-in-.uleb128-for-label-differences.patch
-Patch10: 	0010-Backport-Mips-MC-AttemptToFoldSymbolOffsetDifference-revert-isMicroMips-special-case.patch
-
-Patch11: 	0011-Backport-LoongArch-Add-the-support-for-vector-in-llvm17.patch
-Patch12: 	0012-Backport-LoongArch-improve-the-support-for-compiler-rt-and-bugfix.patch
-Patch13: 	0013-Backport-Bitcode-Add-some-missing-GetTypeByID-failure-checks.patch
-Patch14: 	0014-Backport-X86-Inline-Skip-inline-asm-in-inlining-targ.patch
-Patch15: 	0015-Backport-ARM-Check-all-terms-in-emitPopInst-when-clearing-Res.patch
-Patch16: 	0016-Backport-ARM-Update-IsRestored-for-LR-based-on-all-returns-82.patch
-Patch17:	0017-Add-the-support-for-classic-flang.patch
-Patch18:	0018-Fix-declaration-definition-mismatch-for-classic-flang.patch
-Patch19: 	0019-Backport-LoongArch-Improve-the-support-for-atomic-and-clear_cache.patch
-Patch20: 	0020-Update-llvm-lit-config-to-support-build_for_openeule.patch
-
-Patch21:	0021-Add-BiSheng-Autotuner-support-for-LLVM-compiler.patch
-
-BuildRequires:	binutils-devel
-BuildRequires:	cmake
-BuildRequires:	gcc
-BuildRequires:	gcc-c++
-BuildRequires:	libedit-devel
-BuildRequires:	libffi-devel
-BuildRequires:	multilib-rpm-config
-BuildRequires:	ncurses-devel
-BuildRequires:	ninja-build
-BuildRequires:	python3-devel
-BuildRequires:	python3-psutil
-BuildRequires:	python3-recommonmark
-BuildRequires:	python3-sphinx
-BuildRequires:	python3-setuptools
-BuildRequires:	zlib-devel
-%if %{with toolchain_clang}
-BuildRequires:	clang
-%endif
-
-Requires:	%{name}-libs%{?_isa} = %{version}-%{release}
-
-Provides:	llvm(major) = %{maj_ver}
-
-%description
-LLVM is a compiler infrastructure designed for compile-time, link-time,
-runtime, and idle-time optimization of programs from arbitrary programming
-languages. The compiler infrastructure includes mirror sets of programming
-tools as well as libraries with equivalent functionality.
-
-%package devel
-Summary:	Libraries and header files for LLVM
-Requires:	%{name}%{?_isa} = %{version}-%{release}
-Requires:	%{name}-libs%{?_isa} = %{version}-%{release}
-Requires:	libedit-devel
-Requires:	%{name}-static%{?_isa} = %{version}-%{release}
-
-%if %{with sys_llvm}
-Requires:	%{name}-test%{?_isa} = %{version}-%{release}
-Requires:	%{name}-googletest%{?_isa} = %{version}-%{release}
-%endif
-
-Requires(post):	%{_sbindir}/alternatives
-Requires(postun):	%{_sbindir}/alternatives
-
-Provides:	llvm-devel(major) = %{maj_ver}
-
-%description devel
-This package contains library and header files needed to develop new native
-programs that use the LLVM infrastructure.
-
-%package doc
-Summary:	Documentation for LLVM
-BuildArch:	noarch
-Requires:	%{name} = %{version}-%{release}
-
-%description doc
-Documentation for the LLVM compiler infrastructure.
-
-%package libs
-Summary:	LLVM shared libraries
-
-%description libs
-Shared libraries for the LLVM compiler infrastructure.
-
-%package static
-Summary:	LLVM static libraries
-Conflicts:	%{name}-devel < 8
-
-Provides:	llvm-static(major) = %{maj_ver}
-
-%description static
-Static libraries for the LLVM compiler infrastructure.
-
-%package cmake-utils
-Summary: CMake shared utilities
-
-%description cmake-utils
-CMake moudules shared between LLVM projects at buid time.
-This is for internal use by LLVM packages only.
-
-%package test
-Summary:	LLVM regression tests
-Requires:	%{name}%{?_isa} = %{version}-%{release}
-Requires:	%{name}-libs%{?_isa} = %{version}-%{release}
- 
-Provides:	llvm-test(major) = %{maj_ver}
-
-%description test
-LLVM regression tests.
- 
-%package googletest
-Summary: LLVM's modified googletest sources
- 
-%description googletest
-LLVM's modified googletest sources.
-
-%prep
-%setup -T -q -b 1 -n cmake-%{version}.src
-cd ..
-mv cmake-%{version}.src cmake
-%setup -T -q -b 2 -n third-party-%{version}.src
-cd ..
-mv third-party-%{version}.src third-party
-%setup -T -q -b 0 -n llvm-%{version}.src
-%autopatch -p2
-
-pathfix.py -i %{__python3} -pn \
-	test/BugPoint/compile-custom.ll.py \
-	tools/opt-viewer/*.py \
-	utils/update_cc_test_checks.py
-
-%build
-mkdir -p _build
-cd _build
-
-%cmake	.. -G Ninja \
-	-DBUILD_SHARED_LIBS:BOOL=OFF \
-	-DLLVM_PARALLEL_LINK_JOBS=%{max_link_jobs} \
-	-DCMAKE_BUILD_TYPE=RelWithDebInfo \

_service:tar_scm:0001-Backport-LoongArch-Add-relax-feature-and-keep-relocations.patch Deleted

@@ -1,178 +0,0 @@
-From 6f135b13769c64a6942b4b232a350b6a6207f2b2 Mon Sep 17 00:00:00 2001
-From: Jinyang He <hejinyang@loongson.cn>
-Date: Thu, 16 Nov 2023 11:01:26 +0800
-Subject: PATCH 02/14 LoongArch Add relax feature and keep relocations
- (#72191)
-
-Add relax feature. To support linker relocation, we should make
-relocation with a symbol rather than section plus offset, and keep all
-relocations with non-abs symbol.
-
-(cherry picked from commit f5bfc833fcbf17a5876911783d1adaca7028d20c)
-Change-Id: Ief38b480016175f2cc9939b74a84d9444559ffd6
----
- llvm/lib/Target/LoongArch/LoongArch.td        |  4 +++
- .../lib/Target/LoongArch/LoongArchSubtarget.h |  2 ++
- .../MCTargetDesc/LoongArchAsmBackend.cpp      |  5 +--
- .../MCTargetDesc/LoongArchELFObjectWriter.cpp | 18 ++++++++---
- .../MCTargetDesc/LoongArchMCTargetDesc.h      |  2 +-
- .../MC/LoongArch/Relocations/relax-attr.s     | 32 +++++++++++++++++++
- 6 files changed, 55 insertions(+), 8 deletions(-)
- create mode 100644 llvm/test/MC/LoongArch/Relocations/relax-attr.s
-
-diff --git a/llvm/lib/Target/LoongArch/LoongArch.td b/llvm/lib/Target/LoongArch/LoongArch.td
-index 0675caa3b601..75b65fe69f26 100644
---- a/llvm/lib/Target/LoongArch/LoongArch.td
-+++ b/llvm/lib/Target/LoongArch/LoongArch.td
-@@ -102,6 +102,10 @@ def FeatureUAL
-     : SubtargetFeature<"ual", "HasUAL", "true",
-                        "Allow memory accesses to be unaligned">;
- 
-+def FeatureRelax
-+    : SubtargetFeature<"relax", "HasLinkerRelax", "true",
-+                       "Enable Linker relaxation">;
-+
- //===----------------------------------------------------------------------===//
- // Registers, instruction descriptions ...
- //===----------------------------------------------------------------------===//
-diff --git a/llvm/lib/Target/LoongArch/LoongArchSubtarget.h b/llvm/lib/Target/LoongArch/LoongArchSubtarget.h
-index 0fbe23f2f62d..5c173675cca4 100644
---- a/llvm/lib/Target/LoongArch/LoongArchSubtarget.h
-+++ b/llvm/lib/Target/LoongArch/LoongArchSubtarget.h
-@@ -43,6 +43,7 @@ class LoongArchSubtarget : public LoongArchGenSubtargetInfo {
-   bool HasLaGlobalWithAbs = false;
-   bool HasLaLocalWithAbs = false;
-   bool HasUAL = false;
-+  bool HasLinkerRelax = false;
-   unsigned GRLen = 32;
-   MVT GRLenVT = MVT::i32;
-   LoongArchABI::ABI TargetABI = LoongArchABI::ABI_Unknown;
-@@ -100,6 +101,7 @@ public:
-   bool hasLaGlobalWithAbs() const { return HasLaGlobalWithAbs; }
-   bool hasLaLocalWithAbs() const { return HasLaLocalWithAbs; }
-   bool hasUAL() const { return HasUAL; }
-+  bool hasLinkerRelax() const { return HasLinkerRelax; }
-   MVT getGRLenVT() const { return GRLenVT; }
-   unsigned getGRLen() const { return GRLen; }
-   LoongArchABI::ABI getTargetABI() const { return TargetABI; }
-diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
-index ecb68ff401e9..aae3e544d326 100644
---- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
-+++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
-@@ -168,7 +168,7 @@ bool LoongArchAsmBackend::shouldForceRelocation(const MCAssembler &Asm,
-     return true;
-   switch (Fixup.getTargetKind()) {
-   default:
--    return false;
-+    return STI.hasFeature(LoongArch::FeatureRelax);
-   case FK_Data_1:
-   case FK_Data_2:
-   case FK_Data_4:
-@@ -193,7 +193,8 @@ bool LoongArchAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
- 
- std::unique_ptr<MCObjectTargetWriter>
- LoongArchAsmBackend::createObjectTargetWriter() const {
--  return createLoongArchELFObjectWriter(OSABI, Is64Bit);
-+  return createLoongArchELFObjectWriter(
-+      OSABI, Is64Bit, STI.hasFeature(LoongArch::FeatureRelax));
- }
- 
- MCAsmBackend *llvm::createLoongArchAsmBackend(const Target &T,
-diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchELFObjectWriter.cpp b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchELFObjectWriter.cpp
-index a6b9c0652639..e60b9c2cfd97 100644
---- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchELFObjectWriter.cpp
-+++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchELFObjectWriter.cpp
-@@ -20,19 +20,27 @@ using namespace llvm;
- namespace {
- class LoongArchELFObjectWriter : public MCELFObjectTargetWriter {
- public:
--  LoongArchELFObjectWriter(uint8_t OSABI, bool Is64Bit);
-+  LoongArchELFObjectWriter(uint8_t OSABI, bool Is64Bit, bool EnableRelax);
- 
-   ~LoongArchELFObjectWriter() override;
- 
-+  bool needsRelocateWithSymbol(const MCSymbol &Sym,
-+                               unsigned Type) const override {
-+    return EnableRelax;
-+  }
-+
- protected:
-   unsigned getRelocType(MCContext &Ctx, const MCValue &Target,
-                         const MCFixup &Fixup, bool IsPCRel) const override;
-+  bool EnableRelax;
- };
- } // end namespace
- 
--LoongArchELFObjectWriter::LoongArchELFObjectWriter(uint8_t OSABI, bool Is64Bit)
-+LoongArchELFObjectWriter::LoongArchELFObjectWriter(uint8_t OSABI, bool Is64Bit,
-+                                                   bool EnableRelax)
-     : MCELFObjectTargetWriter(Is64Bit, OSABI, ELF::EM_LOONGARCH,
--                              /*HasRelocationAddend*/ true) {}
-+                              /*HasRelocationAddend=*/true),
-+      EnableRelax(EnableRelax) {}
- 
- LoongArchELFObjectWriter::~LoongArchELFObjectWriter() {}
- 
-@@ -87,6 +95,6 @@ unsigned LoongArchELFObjectWriter::getRelocType(MCContext &Ctx,
- }
- 
- std::unique_ptr<MCObjectTargetWriter>
--llvm::createLoongArchELFObjectWriter(uint8_t OSABI, bool Is64Bit) {
--  return std::make_unique<LoongArchELFObjectWriter>(OSABI, Is64Bit);
-+llvm::createLoongArchELFObjectWriter(uint8_t OSABI, bool Is64Bit, bool Relax) {
-+  return std::make_unique<LoongArchELFObjectWriter>(OSABI, Is64Bit, Relax);
- }
-diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.h b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.h
-index ab35a0096c8a..bb05baa9b717 100644
---- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.h
-+++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.h
-@@ -36,7 +36,7 @@ MCAsmBackend *createLoongArchAsmBackend(const Target &T,
-                                         const MCTargetOptions &Options);
- 
- std::unique_ptr<MCObjectTargetWriter>
--createLoongArchELFObjectWriter(uint8_t OSABI, bool Is64Bit);
-+createLoongArchELFObjectWriter(uint8_t OSABI, bool Is64Bit, bool Relax);
- 
- } // end namespace llvm
- 
-diff --git a/llvm/test/MC/LoongArch/Relocations/relax-attr.s b/llvm/test/MC/LoongArch/Relocations/relax-attr.s
-new file mode 100644
-index 000000000000..b1e648d850bb
---- /dev/null
-+++ b/llvm/test/MC/LoongArch/Relocations/relax-attr.s
-@@ -0,0 +1,32 @@
-+# RUN: llvm-mc --filetype=obj --triple=loongarch64 %s -o %t
-+# RUN: llvm-readobj -r %t | FileCheck %s
-+# RUN: llvm-mc --filetype=obj --triple=loongarch64 -mattr=+relax %s -o %t
-+# RUN: llvm-readobj -r %t | FileCheck %s --check-prefix=CHECKR
-+
-+# CHECK:      Relocations 
-+# CHECK-NEXT:   Section ({{.*}}) .rela.data {
-+# CHECK-NEXT:     0x0 R_LARCH_64 .text 0x4
-+# CHECK-NEXT:   }
-+# CHECK-NEXT: 
-+
-+# CHECKR:      Relocations 
-+# CHECKR-NEXT:   Section ({{.*}}) .rela.text {
-+# CHECKR-NEXT:     0x8 R_LARCH_B21 .L1 0x0
-+# CHECKR-NEXT:     0xC R_LARCH_B16 .L1 0x0
-+# CHECKR-NEXT:     0x10 R_LARCH_B26 .L1 0x0
-+# CHECKR-NEXT:   }
-+# CHECKR-NEXT:   Section ({{.*}}) .rela.data {
-+# CHECKR-NEXT:     0x0 R_LARCH_64 .L1 0x0
-+# CHECKR-NEXT:   }
-+# CHECKR-NEXT: 
-+
-+.text
-+  nop
-+.L1:
-+  nop
-+  beqz $a0, .L1
-+  blt  $a0, $a1, .L1
-+  b    .L1
-+
-+.data
-+.dword .L1
--- 
-2.20.1
-

_service:tar_scm:0002-Backport-LoongArch-Allow-delayed-decision-for-ADD-SUB-relocations.patch Deleted

@@ -1,299 +0,0 @@
-From 77d74b8fa071fa2695c9782e2e63e7b930895b1b Mon Sep 17 00:00:00 2001
-From: Jinyang He <hejinyang@loongson.cn>
-Date: Wed, 20 Dec 2023 10:54:51 +0800
-Subject: PATCH 03/14 LoongArch Allow delayed decision for ADD/SUB
- relocations (#72960)
-
-Refer to RISCV 1, LoongArch also need delayed decision for ADD/SUB
-relocations. In handleAddSubRelocations, just return directly if SecA !=
-SecB, handleFixup usually will finish the the rest of creating PCRel
-relocations works. Otherwise we emit relocs depends on whether
-relaxation is enabled. If not, we return true and avoid record ADD/SUB
-relocations.
-Now the two symbols separated by alignment directive will return without
-folding symbol offset in AttemptToFoldSymbolOffsetDifference, which has
-the same effect when relaxation is enabled.
-
-1 https://reviews.llvm.org/D155357
-
-(cherry picked from commit a8081ed8ff0fd11fb8d5f4c83df49da909e49612)
-Change-Id: Ic4c6a3eb11b576cb0c6ed0eba02150ad67c33cf2
----
- llvm/lib/MC/MCExpr.cpp                        |  3 +-
- .../MCTargetDesc/LoongArchAsmBackend.cpp      | 78 +++++++++++++++++++
- .../MCTargetDesc/LoongArchAsmBackend.h        |  9 ++-
- .../MCTargetDesc/LoongArchFixupKinds.h        |  4 +-
- llvm/test/MC/LoongArch/Misc/subsection.s      | 38 +++++++++
- .../MC/LoongArch/Relocations/relax-addsub.s   | 68 ++++++++++++++++
- 6 files changed, 196 insertions(+), 4 deletions(-)
- create mode 100644 llvm/test/MC/LoongArch/Misc/subsection.s
- create mode 100644 llvm/test/MC/LoongArch/Relocations/relax-addsub.s
-
-diff --git a/llvm/lib/MC/MCExpr.cpp b/llvm/lib/MC/MCExpr.cpp
-index a7b980553af0..5a6596f93824 100644
---- a/llvm/lib/MC/MCExpr.cpp
-+++ b/llvm/lib/MC/MCExpr.cpp
-@@ -635,7 +635,8 @@ static void AttemptToFoldSymbolOffsetDifference(
-   // instructions and InSet is false (not expressions in directive like
-   // .size/.fill), disable the fast path.
-   if (Layout && (InSet || !SecA.hasInstructions() ||
--                 !Asm->getContext().getTargetTriple().isRISCV())) {
-+                 !(Asm->getContext().getTargetTriple().isRISCV() ||
-+                   Asm->getContext().getTargetTriple().isLoongArch()))) {
-     // If both symbols are in the same fragment, return the difference of their
-     // offsets. canGetFragmentOffset(FA) may be false.
-     if (FA == FB && !SA.isVariable() && !SB.isVariable()) {
-diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
-index aae3e544d326..1ed047a8e632 100644
---- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
-+++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
-@@ -177,6 +177,34 @@ bool LoongArchAsmBackend::shouldForceRelocation(const MCAssembler &Asm,
-   }
- }
- 
-+static inline std::pair<MCFixupKind, MCFixupKind>
-+getRelocPairForSize(unsigned Size) {
-+  switch (Size) {
-+  default:
-+    llvm_unreachable("unsupported fixup size");
-+  case 6:
-+    return std::make_pair(
-+        MCFixupKind(FirstLiteralRelocationKind + ELF::R_LARCH_ADD6),
-+        MCFixupKind(FirstLiteralRelocationKind + ELF::R_LARCH_SUB6));
-+  case 8:
-+    return std::make_pair(
-+        MCFixupKind(FirstLiteralRelocationKind + ELF::R_LARCH_ADD8),
-+        MCFixupKind(FirstLiteralRelocationKind + ELF::R_LARCH_SUB8));
-+  case 16:
-+    return std::make_pair(
-+        MCFixupKind(FirstLiteralRelocationKind + ELF::R_LARCH_ADD16),
-+        MCFixupKind(FirstLiteralRelocationKind + ELF::R_LARCH_SUB16));
-+  case 32:
-+    return std::make_pair(
-+        MCFixupKind(FirstLiteralRelocationKind + ELF::R_LARCH_ADD32),
-+        MCFixupKind(FirstLiteralRelocationKind + ELF::R_LARCH_SUB32));
-+  case 64:
-+    return std::make_pair(
-+        MCFixupKind(FirstLiteralRelocationKind + ELF::R_LARCH_ADD64),
-+        MCFixupKind(FirstLiteralRelocationKind + ELF::R_LARCH_SUB64));
-+  }
-+}
-+
- bool LoongArchAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
-                                        const MCSubtargetInfo *STI) const {
-   // We mostly follow binutils' convention here: align to 4-byte boundary with a
-@@ -191,6 +219,56 @@ bool LoongArchAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
-   return true;
- }
- 
-+bool LoongArchAsmBackend::handleAddSubRelocations(const MCAsmLayout &Layout,
-+                                                  const MCFragment &F,
-+                                                  const MCFixup &Fixup,
-+                                                  const MCValue &Target,
-+                                                  uint64_t &FixedValue) const {
-+  std::pair<MCFixupKind, MCFixupKind> FK;
-+  uint64_t FixedValueA, FixedValueB;
-+  const MCSection &SecA = Target.getSymA()->getSymbol().getSection();
-+  const MCSection &SecB = Target.getSymB()->getSymbol().getSection();
-+
-+  // We need record relocation if SecA != SecB. Usually SecB is same as the
-+  // section of Fixup, which will be record the relocation as PCRel. If SecB
-+  // is not same as the section of Fixup, it will report error. Just return
-+  // false and then this work can be finished by handleFixup.
-+  if (&SecA != &SecB)
-+    return false;
-+
-+  // In SecA == SecB case. If the linker relaxation is enabled, we need record
-+  // the ADD, SUB relocations. Otherwise the FixedValue has already been
-+  // calculated out in evaluateFixup, return true and avoid record relocations.
-+  if (!STI.hasFeature(LoongArch::FeatureRelax))
-+    return true;
-+
-+  switch (Fixup.getKind()) {
-+  case llvm::FK_Data_1:
-+    FK = getRelocPairForSize(8);
-+    break;
-+  case llvm::FK_Data_2:
-+    FK = getRelocPairForSize(16);
-+    break;
-+  case llvm::FK_Data_4:
-+    FK = getRelocPairForSize(32);
-+    break;
-+  case llvm::FK_Data_8:
-+    FK = getRelocPairForSize(64);
-+    break;
-+  default:
-+    llvm_unreachable("unsupported fixup size");
-+  }
-+  MCValue A = MCValue::get(Target.getSymA(), nullptr, Target.getConstant());
-+  MCValue B = MCValue::get(Target.getSymB());
-+  auto FA = MCFixup::create(Fixup.getOffset(), nullptr, std::get<0>(FK));
-+  auto FB = MCFixup::create(Fixup.getOffset(), nullptr, std::get<1>(FK));
-+  auto &Asm = Layout.getAssembler();
-+  Asm.getWriter().recordRelocation(Asm, Layout, &F, FA, A, FixedValueA);
-+  Asm.getWriter().recordRelocation(Asm, Layout, &F, FB, B, FixedValueB);
-+  FixedValue = FixedValueA - FixedValueB;
-+  return true;
-+}
-+
- std::unique_ptr<MCObjectTargetWriter>
- LoongArchAsmBackend::createObjectTargetWriter() const {
-   return createLoongArchELFObjectWriter(
-diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h
-index ae9bb8af0419..20f25b5cf53b 100644
---- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h
-+++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h
-@@ -31,10 +31,15 @@ class LoongArchAsmBackend : public MCAsmBackend {
- public:
-   LoongArchAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit,
-                       const MCTargetOptions &Options)
--      : MCAsmBackend(support::little), STI(STI), OSABI(OSABI), Is64Bit(Is64Bit),
--        TargetOptions(Options) {}
-+      : MCAsmBackend(support::little,
-+                     LoongArch::fixup_loongarch_relax),
-+        STI(STI), OSABI(OSABI), Is64Bit(Is64Bit), TargetOptions(Options) {}
-   ~LoongArchAsmBackend() override {}
- 
-+  bool handleAddSubRelocations(const MCAsmLayout &Layout, const MCFragment &F,
-+                               const MCFixup &Fixup, const MCValue &Target,
-+                               uint64_t &FixedValue) const override;
-+
-   void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
-                   const MCValue &Target, MutableArrayRef<char> Data,
-                   uint64_t Value, bool IsResolved,
-diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchFixupKinds.h b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchFixupKinds.h
-index ba2d6718cdf9..178fa6e5262b 100644
---- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchFixupKinds.h
-+++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchFixupKinds.h
-@@ -106,7 +106,9 @@ enum Fixups {
-   // 20-bit fixup corresponding to %gd_pc_hi20(foo) for instruction pcalau12i.
-   fixup_loongarch_tls_gd_pc_hi20,
-   // 20-bit fixup corresponding to %gd_hi20(foo) for instruction lu12i.w.
--  fixup_loongarch_tls_gd_hi20
-+  fixup_loongarch_tls_gd_hi20,
-+  // Generate an R_LARCH_RELAX which indicates the linker may relax here.
-+  fixup_loongarch_relax = FirstLiteralRelocationKind + ELF::R_LARCH_RELAX
- };
- } // end namespace LoongArch
- } // end namespace llvm
-diff --git a/llvm/test/MC/LoongArch/Misc/subsection.s b/llvm/test/MC/LoongArch/Misc/subsection.s
-new file mode 100644
-index 000000000000..0bd22b474536
---- /dev/null
-+++ b/llvm/test/MC/LoongArch/Misc/subsection.s
-@@ -0,0 +1,38 @@
-+# RUN: not llvm-mc --filetype=obj --triple=loongarch64 --mattr=-relax %s -o /dev/null 2>&1 | FileCheck %s --check-prefixes=ERR,NORELAX --implicit-check-not=error:
-+## TODO: not llvm-mc --filetype=obj --triple=loongarch64 --mattr=+relax %s -o /dev/null 2>&1 | FileCheck %s --check-prefixes=ERR,RELAX --implicit-check-not=error:
-+
-+a:
-+  nop
-+b:
-+  la.pcrel $t0, a
-+c:
-+  nop
-+d:
-+
-+.data
-+## Positive subsection numbers
-+## With relaxation, report an error as c-b is not an assemble-time constant.
-+# RELAX: :#@LINE+1:14: error: cannot evaluate subsection number

_service:tar_scm:0003-Backport-LoongArch-Emit-R_LARCH_RELAX-when-expanding-some-LoadAddress.patch Deleted

@@ -1,364 +0,0 @@
-From f2495d7efb79fdc82af6147f7201d9cf3c91beba Mon Sep 17 00:00:00 2001
-From: Jinyang He <hejinyang@loongson.cn>
-Date: Wed, 27 Dec 2023 08:51:48 +0800
-Subject: PATCH 04/14 LoongArch Emit R_LARCH_RELAX when expanding some
- LoadAddress (#72961)
-
-Emit relax relocs when expand non-large la.pcrel and non-large la.got on
-llvm-mc stage, which like what does on GAS.
-1, la.pcrel -> PCALA_HI20 + RELAX + PCALA_LO12 + RELAX
-2, la.got -> GOT_PC_HI20 + RELAX + GOT_PC_LO12 + RELAX
-
-(cherry picked from commit b3ef8dce9811b2725639b0d4fac3f85c7e112817)
-Change-Id: I222daf60b36ee70e23c76b753e1d2a3b8148f44b
----
- .../AsmParser/LoongArchAsmParser.cpp          | 12 +--
- .../MCTargetDesc/LoongArchMCCodeEmitter.cpp   | 13 +++
- .../MCTargetDesc/LoongArchMCExpr.cpp          |  7 +-
- .../LoongArch/MCTargetDesc/LoongArchMCExpr.h  |  8 +-
- llvm/test/MC/LoongArch/Macros/macros-la.s     | 84 ++++++++++++++++---
- llvm/test/MC/LoongArch/Misc/subsection.s      |  2 +-
- .../MC/LoongArch/Relocations/relax-addsub.s   | 16 +++-
- 7 files changed, 115 insertions(+), 27 deletions(-)
-
-diff --git a/llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp b/llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
-index 94d530306536..a132e645c864 100644
---- a/llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
-+++ b/llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
-@@ -86,7 +86,7 @@ class LoongArchAsmParser : public MCTargetAsmParser {
-   // "emitLoadAddress*" functions.
-   void emitLAInstSeq(MCRegister DestReg, MCRegister TmpReg,
-                      const MCExpr *Symbol, SmallVectorImpl<Inst> &Insts,
--                     SMLoc IDLoc, MCStreamer &Out);
-+                     SMLoc IDLoc, MCStreamer &Out, bool RelaxHint = false);
- 
-   // Helper to emit pseudo instruction "la.abs $rd, sym".
-   void emitLoadAddressAbs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
-@@ -749,12 +749,14 @@ bool LoongArchAsmParser::ParseInstruction(ParseInstructionInfo &Info,
- void LoongArchAsmParser::emitLAInstSeq(MCRegister DestReg, MCRegister TmpReg,
-                                        const MCExpr *Symbol,
-                                        SmallVectorImpl<Inst> &Insts,
--                                       SMLoc IDLoc, MCStreamer &Out) {
-+                                       SMLoc IDLoc, MCStreamer &Out,
-+                                       bool RelaxHint) {
-   MCContext &Ctx = getContext();
-   for (LoongArchAsmParser::Inst &Inst : Insts) {
-     unsigned Opc = Inst.Opc;
-     LoongArchMCExpr::VariantKind VK = Inst.VK;
--    const LoongArchMCExpr *LE = LoongArchMCExpr::create(Symbol, VK, Ctx);
-+    const LoongArchMCExpr *LE =
-+        LoongArchMCExpr::create(Symbol, VK, Ctx, RelaxHint);
-     switch (Opc) {
-     default:
-       llvm_unreachable("unexpected opcode");
-@@ -855,7 +857,7 @@ void LoongArchAsmParser::emitLoadAddressPcrel(MCInst &Inst, SMLoc IDLoc,
-   Insts.push_back(
-       LoongArchAsmParser::Inst(ADDI, LoongArchMCExpr::VK_LoongArch_PCALA_LO12));
- 
--  emitLAInstSeq(DestReg, DestReg, Symbol, Insts, IDLoc, Out);
-+  emitLAInstSeq(DestReg, DestReg, Symbol, Insts, IDLoc, Out, true);
- }
- 
- void LoongArchAsmParser::emitLoadAddressPcrelLarge(MCInst &Inst, SMLoc IDLoc,
-@@ -901,7 +903,7 @@ void LoongArchAsmParser::emitLoadAddressGot(MCInst &Inst, SMLoc IDLoc,
-   Insts.push_back(
-       LoongArchAsmParser::Inst(LD, LoongArchMCExpr::VK_LoongArch_GOT_PC_LO12));
- 
--  emitLAInstSeq(DestReg, DestReg, Symbol, Insts, IDLoc, Out);
-+  emitLAInstSeq(DestReg, DestReg, Symbol, Insts, IDLoc, Out, true);
- }
- 
- void LoongArchAsmParser::emitLoadAddressGotLarge(MCInst &Inst, SMLoc IDLoc,
-diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp
-index 03fb9e008ae9..08c0820cb862 100644
---- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp
-+++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp
-@@ -19,6 +19,7 @@
- #include "llvm/MC/MCInstBuilder.h"
- #include "llvm/MC/MCInstrInfo.h"
- #include "llvm/MC/MCRegisterInfo.h"
-+#include "llvm/MC/MCSubtargetInfo.h"
- #include "llvm/Support/Casting.h"
- #include "llvm/Support/EndianStream.h"
- 
-@@ -120,12 +121,15 @@ LoongArchMCCodeEmitter::getExprOpValue(const MCInst &MI, const MCOperand &MO,
-                                        SmallVectorImpl<MCFixup> &Fixups,
-                                        const MCSubtargetInfo &STI) const {
-   assert(MO.isExpr() && "getExprOpValue expects only expressions");
-+  bool RelaxCandidate = false;
-+  bool EnableRelax = STI.hasFeature(LoongArch::FeatureRelax);
-   const MCExpr *Expr = MO.getExpr();
-   MCExpr::ExprKind Kind = Expr->getKind();
-   LoongArch::Fixups FixupKind = LoongArch::fixup_loongarch_invalid;
-   if (Kind == MCExpr::Target) {
-     const LoongArchMCExpr *LAExpr = cast<LoongArchMCExpr>(Expr);
- 
-+    RelaxCandidate = LAExpr->getRelaxHint();
-     switch (LAExpr->getKind()) {
-     case LoongArchMCExpr::VK_LoongArch_None:
-     case LoongArchMCExpr::VK_LoongArch_Invalid:
-@@ -269,6 +273,15 @@ LoongArchMCCodeEmitter::getExprOpValue(const MCInst &MI, const MCOperand &MO,
- 
-   Fixups.push_back(
-       MCFixup::create(0, Expr, MCFixupKind(FixupKind), MI.getLoc()));
-+
-+  // Emit an R_LARCH_RELAX if linker relaxation is enabled and LAExpr has relax
-+  // hint.
-+  if (EnableRelax && RelaxCandidate) {
-+    const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx);
-+    Fixups.push_back(MCFixup::create(
-+        0, Dummy, MCFixupKind(LoongArch::fixup_loongarch_relax), MI.getLoc()));
-+  }
-+
-   return 0;
- }
- 
-diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCExpr.cpp b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCExpr.cpp
-index 993111552a31..82c992b1cc8c 100644
---- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCExpr.cpp
-+++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCExpr.cpp
-@@ -25,9 +25,10 @@ using namespace llvm;
- 
- #define DEBUG_TYPE "loongarch-mcexpr"
- 
--const LoongArchMCExpr *
--LoongArchMCExpr::create(const MCExpr *Expr, VariantKind Kind, MCContext &Ctx) {
--  return new (Ctx) LoongArchMCExpr(Expr, Kind);
-+const LoongArchMCExpr *LoongArchMCExpr::create(const MCExpr *Expr,
-+                                               VariantKind Kind, MCContext &Ctx,
-+                                               bool Hint) {
-+  return new (Ctx) LoongArchMCExpr(Expr, Kind, Hint);
- }
- 
- void LoongArchMCExpr::printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const {
-diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCExpr.h b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCExpr.h
-index 0945cf82db86..93251f824103 100644
---- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCExpr.h
-+++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCExpr.h
-@@ -67,16 +67,18 @@ public:
- private:
-   const MCExpr *Expr;
-   const VariantKind Kind;
-+  const bool RelaxHint;
- 
--  explicit LoongArchMCExpr(const MCExpr *Expr, VariantKind Kind)
--      : Expr(Expr), Kind(Kind) {}
-+  explicit LoongArchMCExpr(const MCExpr *Expr, VariantKind Kind, bool Hint)
-+      : Expr(Expr), Kind(Kind), RelaxHint(Hint) {}
- 
- public:
-   static const LoongArchMCExpr *create(const MCExpr *Expr, VariantKind Kind,
--                                       MCContext &Ctx);
-+                                       MCContext &Ctx, bool Hint = false);
- 
-   VariantKind getKind() const { return Kind; }
-   const MCExpr *getSubExpr() const { return Expr; }
-+  bool getRelaxHint() const { return RelaxHint; }
- 
-   void printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const override;
-   bool evaluateAsRelocatableImpl(MCValue &Res, const MCAsmLayout *Layout,
-diff --git a/llvm/test/MC/LoongArch/Macros/macros-la.s b/llvm/test/MC/LoongArch/Macros/macros-la.s
-index 924e4326b8e5..1a1d12d7d7df 100644
---- a/llvm/test/MC/LoongArch/Macros/macros-la.s
-+++ b/llvm/test/MC/LoongArch/Macros/macros-la.s
-@@ -1,66 +1,128 @@
- # RUN: llvm-mc --triple=loongarch64 %s | FileCheck %s
-+# RUN: llvm-mc --filetype=obj --triple=loongarch64 --mattr=-relax %s -o %t
-+# RUN: llvm-readobj -r %t | FileCheck %s --check-prefix=RELOC
-+# RUN: llvm-mc --filetype=obj --triple=loongarch64 --mattr=+relax %s -o %t.relax
-+# RUN: llvm-readobj -r %t.relax | FileCheck %s --check-prefixes=RELOC,RELAX
-+
-+# RELOC:      Relocations 
-+# RELOC-NEXT:   Section ({{.*}}) .rela.text {
- 
- la.abs $a0, sym_abs
- # CHECK:      lu12i.w $a0, %abs_hi20(sym_abs)
- # CHECK-NEXT: ori $a0, $a0, %abs_lo12(sym_abs)
- # CHECK-NEXT: lu32i.d $a0, %abs64_lo20(sym_abs)
- # CHECK-NEXT: lu52i.d $a0, $a0, %abs64_hi12(sym_abs)
-+# CHECK-EMPTY:
-+# RELOC-NEXT: R_LARCH_ABS_HI20 sym_abs 0x0
-+# RELOC-NEXT: R_LARCH_ABS_LO12 sym_abs 0x0
-+# RELOC-NEXT: R_LARCH_ABS64_LO20 sym_abs 0x0
-+# RELOC-NEXT: R_LARCH_ABS64_HI12 sym_abs 0x0
- 
- la.pcrel $a0, sym_pcrel
--# CHECK:      pcalau12i $a0, %pc_hi20(sym_pcrel)
-+# CHECK-NEXT: pcalau12i $a0, %pc_hi20(sym_pcrel)
- # CHECK-NEXT: addi.d $a0, $a0, %pc_lo12(sym_pcrel)
-+# CHECK-EMPTY:
-+# RELOC-NEXT: R_LARCH_PCALA_HI20 sym_pcrel 0x0
-+# RELAX-NEXT: R_LARCH_RELAX - 0x0
-+# RELOC-NEXT: R_LARCH_PCALA_LO12 sym_pcrel 0x0
-+# RELAX-NEXT: R_LARCH_RELAX - 0x0
- 
- la.pcrel $a0, $a1, sym_pcrel_large
--# CHECK:      pcalau12i $a0, %pc_hi20(sym_pcrel_large)
-+# CHECK-NEXT: pcalau12i $a0, %pc_hi20(sym_pcrel_large)
- # CHECK-NEXT: addi.d $a1, $zero, %pc_lo12(sym_pcrel_large)
- # CHECK-NEXT: lu32i.d $a1, %pc64_lo20(sym_pcrel_large)

_service:tar_scm:0004-Backport-MC-LoongArch-Add-AlignFragment-size-if-layout-is-available-and-not-need-insert-nops.patch Deleted

@@ -1,123 +0,0 @@
-From be6e5c566f49bee5efe3d710bdd321e15d8d95ea Mon Sep 17 00:00:00 2001
-From: Jinyang He <hejinyang@loongson.cn>
-Date: Thu, 14 Mar 2024 12:10:50 +0800
-Subject: PATCH 05/14 MCLoongArch Add AlignFragment size if layout is
- available and not need insert nops (#76552)
-
-Due to delayed decision for ADD/SUB relocations, RISCV and LoongArch may
-go slow fragment walk path with available layout. When RISCV (or
-LoongArch in the future) don't need insert nops, that means relax is
-disabled. With available layout and not needing insert nops, the size of
-AlignFragment should be a constant. So we can add it to Displacement for
-folding A-B.
-
-(cherry picked from commit 0731567a31e4ade97c27801045156a88c4589704)
-Change-Id: I554d6766bd7f688204e956e4a6431574b4c511c9
----
- llvm/lib/MC/MCExpr.cpp                        |  6 +++++
- llvm/test/MC/LoongArch/Misc/cfi-advance.s     | 27 +++++++++++++++++++
- .../MC/LoongArch/Relocations/relax-addsub.s   | 17 +++---------
- 3 files changed, 37 insertions(+), 13 deletions(-)
- create mode 100644 llvm/test/MC/LoongArch/Misc/cfi-advance.s
-
-diff --git a/llvm/lib/MC/MCExpr.cpp b/llvm/lib/MC/MCExpr.cpp
-index 5a6596f93824..a561fed11179 100644
---- a/llvm/lib/MC/MCExpr.cpp
-+++ b/llvm/lib/MC/MCExpr.cpp
-@@ -707,8 +707,14 @@ static void AttemptToFoldSymbolOffsetDifference(
-       }
- 
-       int64_t Num;
-+      unsigned Count;
-       if (DF) {
-         Displacement += DF->getContents().size();
-+      } else if (auto *AF = dyn_cast<MCAlignFragment>(FI);
-+                 AF && Layout &&
-+                 !Asm->getBackend().shouldInsertExtraNopBytesForCodeAlign(
-+                     *AF, Count)) {
-+        Displacement += Asm->computeFragmentSize(*Layout, *AF);
-       } else if (auto *FF = dyn_cast<MCFillFragment>(FI);
-                  FF && FF->getNumValues().evaluateAsAbsolute(Num)) {
-         Displacement += Num * FF->getValueSize();
-diff --git a/llvm/test/MC/LoongArch/Misc/cfi-advance.s b/llvm/test/MC/LoongArch/Misc/cfi-advance.s
-new file mode 100644
-index 000000000000..662c43e6bcea
---- /dev/null
-+++ b/llvm/test/MC/LoongArch/Misc/cfi-advance.s
-@@ -0,0 +1,27 @@
-+# RUN: llvm-mc --filetype=obj --triple=loongarch64 -mattr=-relax %s -o %t.o
-+# RUN: llvm-readobj -r %t.o | FileCheck --check-prefix=RELOC %s
-+# RUN: llvm-dwarfdump --debug-frame %t.o | FileCheck --check-prefix=DWARFDUMP %s
-+
-+# RELOC:       Relocations 
-+# RELOC-NEXT:    .rela.eh_frame {
-+# RELOC-NEXT:       0x1C R_LARCH_32_PCREL .text 0x0
-+# RELOC-NEXT:    }
-+# RELOC-NEXT:  
-+# DWARFDUMP:       DW_CFA_advance_loc: 4
-+# DWARFDUMP-NEXT:  DW_CFA_def_cfa_offset: +8
-+# DWARFDUMP-NEXT:  DW_CFA_advance_loc: 8
-+# DWARFDUMP-NEXT:  DW_CFA_def_cfa_offset: +8
-+
-+        .text
-+        .globl test
-+        .p2align 2
-+        .type   test,@function
-+test:
-+        .cfi_startproc
-+        nop
-+        .cfi_def_cfa_offset 8
-+        .p2align 3
-+        nop
-+        .cfi_def_cfa_offset 8
-+        nop
-+        .cfi_endproc
-diff --git a/llvm/test/MC/LoongArch/Relocations/relax-addsub.s b/llvm/test/MC/LoongArch/Relocations/relax-addsub.s
-index c4454f5bb98d..14922657ae89 100644
---- a/llvm/test/MC/LoongArch/Relocations/relax-addsub.s
-+++ b/llvm/test/MC/LoongArch/Relocations/relax-addsub.s
-@@ -23,14 +23,6 @@
- # RELAX-NEXT:      0x14 R_LARCH_RELAX - 0x0
- # RELAX-NEXT:    }
- # RELAX-NEXT:    Section ({{.*}}) .rela.data {
--# RELAX-NEXT:      0xF R_LARCH_ADD8 .L3 0x0
--# RELAX-NEXT:      0xF R_LARCH_SUB8 .L2 0x0
--# RELAX-NEXT:      0x10 R_LARCH_ADD16 .L3 0x0
--# RELAX-NEXT:      0x10 R_LARCH_SUB16 .L2 0x0
--# RELAX-NEXT:      0x12 R_LARCH_ADD32 .L3 0x0
--# RELAX-NEXT:      0x12 R_LARCH_SUB32 .L2 0x0
--# RELAX-NEXT:      0x16 R_LARCH_ADD64 .L3 0x0
--# RELAX-NEXT:      0x16 R_LARCH_SUB64 .L2 0x0
- # RELAX-NEXT:      0x1E R_LARCH_ADD8 .L4 0x0
- # RELAX-NEXT:      0x1E R_LARCH_SUB8 .L3 0x0
- # RELAX-NEXT:      0x1F R_LARCH_ADD16 .L4 0x0
-@@ -43,8 +35,8 @@
- # RELAX-NEXT:  
- 
- # RELAX:      Hex dump of section '.data':
--# RELAX-NEXT: 0x00000000 04040004 00000004 00000000 00000000
--# RELAX-NEXT: 0x00000010 00000000 00000000 00000000 00000000
-+# RELAX-NEXT: 0x00000000 04040004 00000004 00000000 0000000c
-+# RELAX-NEXT: 0x00000010 0c000c00 00000c00 00000000 00000000
- # RELAX-NEXT: 0x00000020 00000000 00000000 00000000 00
- 
- .text
-@@ -63,13 +55,12 @@
- .short .L2 - .L1
- .word  .L2 - .L1
- .dword .L2 - .L1
--## With relaxation, emit relocs because of the .align making the diff variable.
--## TODO Handle alignment directive. Why they emit relocs now? They returns
--## without folding symbols offset in AttemptToFoldSymbolOffsetDifference().
-+## TODO Handle alignment directive.
- .byte  .L3 - .L2
- .short .L3 - .L2
- .word  .L3 - .L2
- .dword .L3 - .L2
-+## With relaxation, emit relocs because the la.pcrel makes the diff variable.
- .byte  .L4 - .L3
- .short .L4 - .L3
- .word  .L4 - .L3
--- 
-2.20.1
-

_service:tar_scm:0005-Backport-LoongArch-RISCV-Support-R_LARCH_-ADD-SUB-_ULEB128-R_RISCV_-SET-SUB-_ULEB128-for-uleb128-directives.patch Deleted

@@ -1,633 +0,0 @@
-From 8d7b71890179d32474b3a1a1c627481bd5a2327d Mon Sep 17 00:00:00 2001
-From: zhanglimin <zhanglimin@loongson.cn>
-Date: Fri, 15 Mar 2024 14:39:48 +0800
-Subject: PATCH 06/14 LoongArchRISCV Support
- R_LARCH_{ADD,SUB}_ULEB128/R_RISCV_{SET,SUB}_ULEB128 for .uleb128 directives
-
-This patch is originally from three upstream commits:
-1, R_LARCH_{ADD,SUB}_ULEB128 are originally landed from b57159cb(#76433).
-2, R_RISCV_{SET,SUB}_ULEB128 are originally supported from 1df5ea29. Among it, we change
-the default behaviour of `-riscv-uleb128-reloc` to not produce uleb128 reloc, in order
-to avoid any other side-effects due to the updated implementation of `MCAssembler::relaxLEB()`
-function. And at the same time, we ensure that this patch can't introduce new default traits
-(such as the generation for uleb128 reloc) on RISCV in this version.
-3, Fix invalid-sleb.s in original commit d7398a35.
-
-Change-Id: Ie687b7d8483c76cf647141162641db1a9d819a04
----
- .../llvm/BinaryFormat/ELFRelocs/RISCV.def     |  2 +
- llvm/include/llvm/MC/MCAsmBackend.h           |  8 +++
- llvm/include/llvm/MC/MCFixup.h                |  1 +
- llvm/include/llvm/MC/MCFragment.h             |  9 ++-
- llvm/lib/MC/MCAsmBackend.cpp                  |  1 +
- llvm/lib/MC/MCAssembler.cpp                   | 39 ++++++++--
- .../MCTargetDesc/LoongArchAsmBackend.cpp      | 69 ++++++++++++++----
- .../MCTargetDesc/LoongArchAsmBackend.h        |  3 +
- .../RISCV/MCTargetDesc/RISCVAsmBackend.cpp    | 27 +++++++
- .../RISCV/MCTargetDesc/RISCVAsmBackend.h      |  2 +
- llvm/test/MC/ELF/RISCV/gen-dwarf.s            |  5 +-
- llvm/test/MC/LoongArch/Relocations/leb128.s   | 72 +++++++++++++++++++
- .../MC/LoongArch/Relocations/relax-addsub.s   | 57 +++++++++++----
- llvm/test/MC/X86/invalid-sleb.s               |  5 --
- 14 files changed, 252 insertions(+), 48 deletions(-)
- create mode 100644 llvm/test/MC/LoongArch/Relocations/leb128.s
- delete mode 100644 llvm/test/MC/X86/invalid-sleb.s
-
-diff --git a/llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV.def b/llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV.def
-index 9a126df01531..c7fd6490041c 100644
---- a/llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV.def
-+++ b/llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV.def
-@@ -55,3 +55,5 @@ ELF_RELOC(R_RISCV_SET32,             56)
- ELF_RELOC(R_RISCV_32_PCREL,          57)
- ELF_RELOC(R_RISCV_IRELATIVE,         58)
- ELF_RELOC(R_RISCV_PLT32,             59)
-+ELF_RELOC(R_RISCV_SET_ULEB128,       60)
-+ELF_RELOC(R_RISCV_SUB_ULEB128,       61)
-diff --git a/llvm/include/llvm/MC/MCAsmBackend.h b/llvm/include/llvm/MC/MCAsmBackend.h
-index 5e08fb41679b..968a767b17f8 100644
---- a/llvm/include/llvm/MC/MCAsmBackend.h
-+++ b/llvm/include/llvm/MC/MCAsmBackend.h
-@@ -21,6 +21,7 @@ class MCAlignFragment;
- class MCDwarfCallFrameFragment;
- class MCDwarfLineAddrFragment;
- class MCFragment;
-+class MCLEBFragment;
- class MCRelaxableFragment;
- class MCSymbol;
- class MCAsmLayout;
-@@ -194,6 +195,13 @@ public:
-     return false;
-   }
- 
-+  // Defined by linker relaxation targets to possibly emit LEB128 relocations
-+  // and set Value at the relocated location.
-+  virtual std::pair<bool, bool>
-+  relaxLEB128(MCLEBFragment &LF, MCAsmLayout &Layout, int64_t &Value) const {
-+    return std::make_pair(false, false);
-+  }
-+
-   /// @}
- 
-   /// Returns the minimum size of a nop in bytes on this target. The assembler
-diff --git a/llvm/include/llvm/MC/MCFixup.h b/llvm/include/llvm/MC/MCFixup.h
-index 069ca058310f..7f48a90cb1ec 100644
---- a/llvm/include/llvm/MC/MCFixup.h
-+++ b/llvm/include/llvm/MC/MCFixup.h
-@@ -25,6 +25,7 @@ enum MCFixupKind {
-   FK_Data_4,      ///< A four-byte fixup.
-   FK_Data_8,      ///< A eight-byte fixup.
-   FK_Data_6b,     ///< A six-bits fixup.
-+  FK_Data_leb128, ///< A leb128 fixup.
-   FK_PCRel_1,     ///< A one-byte pc relative fixup.
-   FK_PCRel_2,     ///< A two-byte pc relative fixup.
-   FK_PCRel_4,     ///< A four-byte pc relative fixup.
-diff --git a/llvm/include/llvm/MC/MCFragment.h b/llvm/include/llvm/MC/MCFragment.h
-index 7be4792a4521..e965732010fe 100644
---- a/llvm/include/llvm/MC/MCFragment.h
-+++ b/llvm/include/llvm/MC/MCFragment.h
-@@ -428,7 +428,7 @@ public:
-   }
- };
- 
--class MCLEBFragment : public MCFragment {
-+class MCLEBFragment final : public MCEncodedFragmentWithFixups<10, 1> {
-   /// True if this is a sleb128, false if uleb128.
-   bool IsSigned;
- 
-@@ -439,17 +439,16 @@ class MCLEBFragment : public MCFragment {
- 
- public:
-   MCLEBFragment(const MCExpr &Value_, bool IsSigned_, MCSection *Sec = nullptr)
--      : MCFragment(FT_LEB, false, Sec), IsSigned(IsSigned_), Value(&Value_) {
-+      : MCEncodedFragmentWithFixups<10, 1>(FT_LEB, false, Sec),
-+        IsSigned(IsSigned_), Value(&Value_) {
-     Contents.push_back(0);
-   }
- 
-   const MCExpr &getValue() const { return *Value; }
-+  void setValue(const MCExpr *Expr) { Value = Expr; }
- 
-   bool isSigned() const { return IsSigned; }
- 
--  SmallString<8> &getContents() { return Contents; }
--  const SmallString<8> &getContents() const { return Contents; }
--
-   /// @}
- 
-   static bool classof(const MCFragment *F) {
-diff --git a/llvm/lib/MC/MCAsmBackend.cpp b/llvm/lib/MC/MCAsmBackend.cpp
-index 64bbc63719c7..2eef7d363fe7 100644
---- a/llvm/lib/MC/MCAsmBackend.cpp
-+++ b/llvm/lib/MC/MCAsmBackend.cpp
-@@ -89,6 +89,7 @@ const MCFixupKindInfo &MCAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
-       {"FK_Data_4", 0, 32, 0},
-       {"FK_Data_8", 0, 64, 0},
-       {"FK_Data_6b", 0, 6, 0},
-+      {"FK_Data_leb128", 0, 0, 0},
-       {"FK_PCRel_1", 0, 8, MCFixupKindInfo::FKF_IsPCRel},
-       {"FK_PCRel_2", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
-       {"FK_PCRel_4", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
-diff --git a/llvm/lib/MC/MCAssembler.cpp b/llvm/lib/MC/MCAssembler.cpp
-index 55ed1a285cd7..86c798ec9e27 100644
---- a/llvm/lib/MC/MCAssembler.cpp
-+++ b/llvm/lib/MC/MCAssembler.cpp
-@@ -918,6 +918,12 @@ void MCAssembler::layout(MCAsmLayout &Layout) {
-         Contents = DF.getContents();
-         break;
-       }
-+      case MCFragment::FT_LEB: {
-+        auto &LF = cast<MCLEBFragment>(Frag);
-+        Fixups = LF.getFixups();
-+        Contents = LF.getContents();
-+        break;
-+      }
-       case MCFragment::FT_PseudoProbe: {
-         MCPseudoProbeAddrFragment &PF = cast<MCPseudoProbeAddrFragment>(Frag);
-         Fixups = PF.getFixups();
-@@ -1006,12 +1012,31 @@ bool MCAssembler::relaxInstruction(MCAsmLayout &Layout,
- }
- 
- bool MCAssembler::relaxLEB(MCAsmLayout &Layout, MCLEBFragment &LF) {
--  uint64_t OldSize = LF.getContents().size();
-+  const unsigned OldSize = static_cast<unsigned>(LF.getContents().size());
-+  unsigned PadTo = OldSize;
-   int64_t Value;
--  bool Abs = LF.getValue().evaluateKnownAbsolute(Value, Layout);
--  if (!Abs)
--    report_fatal_error("sleb128 and uleb128 expressions must be absolute");
--  SmallString<8> &Data = LF.getContents();
-+  SmallVectorImpl<char> &Data = LF.getContents();
-+  LF.getFixups().clear();
-+  // Use evaluateKnownAbsolute for Mach-O as a hack: .subsections_via_symbols
-+  // requires that .uleb128 A-B is foldable where A and B reside in different
-+  // fragments. This is used by __gcc_except_table.
-+  bool Abs = getSubsectionsViaSymbols()
-+                 ? LF.getValue().evaluateKnownAbsolute(Value, Layout)
-+                 : LF.getValue().evaluateAsAbsolute(Value, Layout);
-+  if (!Abs) {
-+    bool Relaxed, UseZeroPad;
-+    std::tie(Relaxed, UseZeroPad) = getBackend().relaxLEB128(LF, Layout, Value);
-+    if (!Relaxed) {
-+      getContext().reportError(LF.getValue().getLoc(),
-+                               Twine(LF.isSigned() ? ".s" : ".u") +
-+                                   "leb128 expression is not absolute");
-+      LF.setValue(MCConstantExpr::create(0, Context));
-+    }
-+    uint8_t Tmp10; // maximum size: ceil(64/7)
-+    PadTo = std::max(PadTo, encodeULEB128(uint64_t(Value), Tmp));
-+    if (UseZeroPad)
-+      Value = 0;
-+  }
-   Data.clear();
-   raw_svector_ostream OSE(Data);
-   // The compiler can generate EH table assembly that is impossible to assemble
-@@ -1019,9 +1044,9 @@ bool MCAssembler::relaxLEB(MCAsmLayout &Layout, MCLEBFragment &LF) {
-   // to a later alignment fragment. To accommodate such tables, relaxation can
-   // only increase an LEB fragment size here, not decrease it. See PR35809.
-   if (LF.isSigned())
--    encodeSLEB128(Value, OSE, OldSize);
-+    encodeSLEB128(Value, OSE, PadTo);
-   else
--    encodeULEB128(Value, OSE, OldSize);
-+    encodeULEB128(Value, OSE, PadTo);
-   return OldSize != LF.getContents().size();
- }
- 
-diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
-index 1ed047a8e632..9227d4d6afed 100644
---- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
-+++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp

_service:tar_scm:0006-Backport-LoongArch-Add-relaxDwarfLineAddr-and-relaxDwarfCFA-to-handle-the-mutable-label-diff-in-dwarfinfo.patch Deleted

@@ -1,376 +0,0 @@
-From 286c92a8e78c4b67368c2f47a8e73036fdacbae2 Mon Sep 17 00:00:00 2001
-From: Jinyang He <hejinyang@loongson.cn>
-Date: Tue, 16 Jan 2024 13:20:13 +0800
-Subject: PATCH 07/14 LoongArch Add relaxDwarfLineAddr and relaxDwarfCFA to
- handle the mutable label diff in dwarfinfo (#77728)
-
-When linker-relaxation is enabled, part of the label diff in dwarfinfo
-cannot be computed before static link. Refer to RISCV, we add the
-relaxDwarfLineAddr and relaxDwarfCFA to add relocations for these label
-diffs. Calculate whether the label diff is mutable. For immutable label
-diff, return false and do the other works by its parent function.
-
-(cherry picked from commit ed7f4edc19ada006789318a0929b57d1b5a761bd)
-Change-Id: Iae5bad958c6d1a71dac1672f5f03991eaeea6d22
----
- llvm/lib/Object/RelocationResolver.cpp        |  12 +-
- .../MCTargetDesc/LoongArchAsmBackend.cpp      | 129 ++++++++++++++++++
- .../MCTargetDesc/LoongArchAsmBackend.h        |   5 +
- .../LoongArch/dwarf-loongarch-relocs.ll       | 128 +++++++++++++++++
- llvm/test/DebugInfo/LoongArch/lit.local.cfg   |   2 +
- 5 files changed, 274 insertions(+), 2 deletions(-)
- create mode 100644 llvm/test/DebugInfo/LoongArch/dwarf-loongarch-relocs.ll
- create mode 100644 llvm/test/DebugInfo/LoongArch/lit.local.cfg
-
-diff --git a/llvm/lib/Object/RelocationResolver.cpp b/llvm/lib/Object/RelocationResolver.cpp
-index 03ac59289528..0e5036d7dfcc 100644
---- a/llvm/lib/Object/RelocationResolver.cpp
-+++ b/llvm/lib/Object/RelocationResolver.cpp
-@@ -539,6 +539,8 @@ static bool supportsLoongArch(uint64_t Type) {
-   case ELF::R_LARCH_32:
-   case ELF::R_LARCH_32_PCREL:
-   case ELF::R_LARCH_64:
-+  case ELF::R_LARCH_ADD6:
-+  case ELF::R_LARCH_SUB6:
-   case ELF::R_LARCH_ADD8:
-   case ELF::R_LARCH_SUB8:
-   case ELF::R_LARCH_ADD16:
-@@ -564,6 +566,10 @@ static uint64_t resolveLoongArch(uint64_t Type, uint64_t Offset, uint64_t S,
-     return (S + Addend - Offset) & 0xFFFFFFFF;
-   case ELF::R_LARCH_64:
-     return S + Addend;
-+  case ELF::R_LARCH_ADD6:
-+    return (LocData & 0xC0) | ((LocData + S + Addend) & 0x3F);
-+  case ELF::R_LARCH_SUB6:
-+    return (LocData & 0xC0) | ((LocData - (S + Addend)) & 0x3F);
-   case ELF::R_LARCH_ADD8:
-     return (LocData + (S + Addend)) & 0xFF;
-   case ELF::R_LARCH_SUB8:
-@@ -880,8 +886,10 @@ uint64_t resolveRelocation(RelocationResolver Resolver, const RelocationRef &R,
- 
-       if (GetRelSectionType() == ELF::SHT_RELA) {
-         Addend = getELFAddend(R);
--        // RISCV relocations use both LocData and Addend.
--        if (Obj->getArch() != Triple::riscv32 &&
-+        // LoongArch and RISCV relocations use both LocData and Addend.
-+        if (Obj->getArch() != Triple::loongarch32 &&
-+            Obj->getArch() != Triple::loongarch64 &&
-+            Obj->getArch() != Triple::riscv32 &&
-             Obj->getArch() != Triple::riscv64)
-           LocData = 0;
-       }
-diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
-index 9227d4d6afed..8d82327b2e2b 100644
---- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
-+++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
-@@ -12,6 +12,7 @@
- 
- #include "LoongArchAsmBackend.h"
- #include "LoongArchFixupKinds.h"
-+#include "llvm/MC/MCAsmInfo.h"
- #include "llvm/MC/MCAsmLayout.h"
- #include "llvm/MC/MCAssembler.h"
- #include "llvm/MC/MCContext.h"
-@@ -19,6 +20,7 @@
- #include "llvm/MC/MCValue.h"
- #include "llvm/Support/Endian.h"
- #include "llvm/Support/EndianStream.h"
-+#include "llvm/Support/LEB128.h"
- 
- #define DEBUG_TYPE "loongarch-asmbackend"
- 
-@@ -235,6 +237,133 @@ std::pair<bool, bool> LoongArchAsmBackend::relaxLEB128(MCLEBFragment &LF,
-   return std::make_pair(true, true);
- }
- 
-+bool LoongArchAsmBackend::relaxDwarfLineAddr(MCDwarfLineAddrFragment &DF,
-+                                             MCAsmLayout &Layout,
-+                                             bool &WasRelaxed) const {
-+  MCContext &C = Layout.getAssembler().getContext();
-+
-+  int64_t LineDelta = DF.getLineDelta();
-+  const MCExpr &AddrDelta = DF.getAddrDelta();
-+  SmallVectorImpl<char> &Data = DF.getContents();
-+  SmallVectorImpl<MCFixup> &Fixups = DF.getFixups();
-+  size_t OldSize = Data.size();
-+
-+  int64_t Value;
-+  if (AddrDelta.evaluateAsAbsolute(Value, Layout))
-+    return false;
-+  bool IsAbsolute = AddrDelta.evaluateKnownAbsolute(Value, Layout);
-+  assert(IsAbsolute && "CFA with invalid expression");
-+  (void)IsAbsolute;
-+
-+  Data.clear();
-+  Fixups.clear();
-+  raw_svector_ostream OS(Data);
-+
-+  // INT64_MAX is a signal that this is actually a DW_LNE_end_sequence.
-+  if (LineDelta != INT64_MAX) {
-+    OS << uint8_t(dwarf::DW_LNS_advance_line);
-+    encodeSLEB128(LineDelta, OS);
-+  }
-+
-+  unsigned Offset;
-+  std::pair<MCFixupKind, MCFixupKind> FK;
-+
-+  // According to the DWARF specification, the `DW_LNS_fixed_advance_pc` opcode
-+  // takes a single unsigned half (unencoded) operand. The maximum encodable
-+  // value is therefore 65535.  Set a conservative upper bound for relaxation.
-+  if (Value > 60000) {
-+    unsigned PtrSize = C.getAsmInfo()->getCodePointerSize();
-+
-+    OS << uint8_t(dwarf::DW_LNS_extended_op);
-+    encodeULEB128(PtrSize + 1, OS);
-+
-+    OS << uint8_t(dwarf::DW_LNE_set_address);
-+    Offset = OS.tell();
-+    assert((PtrSize == 4 || PtrSize == 8) && "Unexpected pointer size");
-+    FK = getRelocPairForSize(PtrSize == 4 ? 32 : 64);
-+    OS.write_zeros(PtrSize);
-+  } else {
-+    OS << uint8_t(dwarf::DW_LNS_fixed_advance_pc);
-+    Offset = OS.tell();
-+    FK = getRelocPairForSize(16);
-+    support::endian::write<uint16_t>(OS, 0, support::little);
-+  }
-+
-+  const MCBinaryExpr &MBE = cast<MCBinaryExpr>(AddrDelta);
-+  Fixups.push_back(MCFixup::create(Offset, MBE.getLHS(), std::get<0>(FK)));
-+  Fixups.push_back(MCFixup::create(Offset, MBE.getRHS(), std::get<1>(FK)));
-+
-+  if (LineDelta == INT64_MAX) {
-+    OS << uint8_t(dwarf::DW_LNS_extended_op);
-+    OS << uint8_t(1);
-+    OS << uint8_t(dwarf::DW_LNE_end_sequence);
-+  } else {
-+    OS << uint8_t(dwarf::DW_LNS_copy);
-+  }
-+
-+  WasRelaxed = OldSize != Data.size();
-+  return true;
-+}
-+
-+bool LoongArchAsmBackend::relaxDwarfCFA(MCDwarfCallFrameFragment &DF,
-+                                        MCAsmLayout &Layout,
-+                                        bool &WasRelaxed) const {
-+  const MCExpr &AddrDelta = DF.getAddrDelta();
-+  SmallVectorImpl<char> &Data = DF.getContents();
-+  SmallVectorImpl<MCFixup> &Fixups = DF.getFixups();
-+  size_t OldSize = Data.size();
-+
-+  int64_t Value;
-+  if (AddrDelta.evaluateAsAbsolute(Value, Layout))
-+    return false;
-+  bool IsAbsolute = AddrDelta.evaluateKnownAbsolute(Value, Layout);
-+  assert(IsAbsolute && "CFA with invalid expression");
-+  (void)IsAbsolute;
-+
-+  Data.clear();
-+  Fixups.clear();
-+  raw_svector_ostream OS(Data);
-+
-+  assert(
-+      Layout.getAssembler().getContext().getAsmInfo()->getMinInstAlignment() ==
-+          1 &&
-+      "expected 1-byte alignment");
-+  if (Value == 0) {
-+    WasRelaxed = OldSize != Data.size();
-+    return true;
-+  }
-+
-+  auto AddFixups = &Fixups,
-+                    &AddrDelta(unsigned Offset,
-+                                std::pair<MCFixupKind, MCFixupKind> FK) {
-+    const MCBinaryExpr &MBE = cast<MCBinaryExpr>(AddrDelta);
-+    Fixups.push_back(MCFixup::create(Offset, MBE.getLHS(), std::get<0>(FK)));
-+    Fixups.push_back(MCFixup::create(Offset, MBE.getRHS(), std::get<1>(FK)));
-+  };
-+
-+  if (isUIntN(6, Value)) {
-+    OS << uint8_t(dwarf::DW_CFA_advance_loc);
-+    AddFixups(0, getRelocPairForSize(6));
-+  } else if (isUInt<8>(Value)) {
-+    OS << uint8_t(dwarf::DW_CFA_advance_loc1);
-+    support::endian::write<uint8_t>(OS, 0, support::little);
-+    AddFixups(1, getRelocPairForSize(8));
-+  } else if (isUInt<16>(Value)) {
-+    OS << uint8_t(dwarf::DW_CFA_advance_loc2);
-+    support::endian::write<uint16_t>(OS, 0, support::little);

_service:tar_scm:0007-Backport-LoongArch-Insert-nops-and-emit-align-reloc-when-handle-alignment-directive.patch Deleted

@@ -1,362 +0,0 @@
-From 87f6adc2acf635a0a4c294217fb54c55eee3a06c Mon Sep 17 00:00:00 2001
-From: Jinyang He <hejinyang@loongson.cn>
-Date: Wed, 24 Jan 2024 09:17:49 +0800
-Subject: PATCH 08/14 LoongArch Insert nops and emit align reloc when
- handle alignment directive (#72962)
-
-Refer to RISCV, we will fix up the alignment if linker relaxation
-changes code size and breaks alignment. Insert enough Nops and emit
-R_LARCH_ALIGN relocation type so that linker could satisfy the alignment
-by removing Nops.
-It does so only in sections with the SHF_EXECINSTR flag.
-
-In LoongArch psABI v2.30, R_LARCH_ALIGN requires symbol index. The
-lowest 8 bits of addend represent alignment and the other bits of addend
-represent the maximum number of bytes to emit.
-
-(cherry picked from commit c51ab483e6c2d991a01179584705b83fbea1940d)
-Change-Id: Iba30702c9dda378acfae0b1f1134926fa838a368
----
- llvm/lib/MC/MCExpr.cpp                        |  2 +-
- .../MCTargetDesc/LoongArchAsmBackend.cpp      | 67 ++++++++++++++++
- .../MCTargetDesc/LoongArchAsmBackend.h        | 15 ++++
- .../MCTargetDesc/LoongArchFixupKinds.h        |  4 +-
- .../Relocations/align-non-executable.s        | 27 +++++++
- .../MC/LoongArch/Relocations/relax-addsub.s   | 15 +++-
- .../MC/LoongArch/Relocations/relax-align.s    | 79 +++++++++++++++++++
- 7 files changed, 205 insertions(+), 4 deletions(-)
- create mode 100644 llvm/test/MC/LoongArch/Relocations/align-non-executable.s
- create mode 100644 llvm/test/MC/LoongArch/Relocations/relax-align.s
-
-diff --git a/llvm/lib/MC/MCExpr.cpp b/llvm/lib/MC/MCExpr.cpp
-index a561fed11179..79808a58d81c 100644
---- a/llvm/lib/MC/MCExpr.cpp
-+++ b/llvm/lib/MC/MCExpr.cpp
-@@ -711,7 +711,7 @@ static void AttemptToFoldSymbolOffsetDifference(
-       if (DF) {
-         Displacement += DF->getContents().size();
-       } else if (auto *AF = dyn_cast<MCAlignFragment>(FI);
--                 AF && Layout &&
-+                 AF && Layout && AF->hasEmitNops() &&
-                  !Asm->getBackend().shouldInsertExtraNopBytesForCodeAlign(
-                      *AF, Count)) {
-         Displacement += Asm->computeFragmentSize(*Layout, *AF);
-diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
-index 8d82327b2e2b..8c482356402f 100644
---- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
-+++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
-@@ -17,10 +17,13 @@
- #include "llvm/MC/MCAssembler.h"
- #include "llvm/MC/MCContext.h"
- #include "llvm/MC/MCELFObjectWriter.h"
-+#include "llvm/MC/MCExpr.h"
-+#include "llvm/MC/MCSection.h"
- #include "llvm/MC/MCValue.h"
- #include "llvm/Support/Endian.h"
- #include "llvm/Support/EndianStream.h"
- #include "llvm/Support/LEB128.h"
-+#include "llvm/Support/MathExtras.h"
- 
- #define DEBUG_TYPE "loongarch-asmbackend"
- 
-@@ -177,6 +180,70 @@ void LoongArchAsmBackend::applyFixup(const MCAssembler &Asm,
-   }
- }
- 
-+// Linker relaxation may change code size. We have to insert Nops
-+// for .align directive when linker relaxation enabled. So then Linker
-+// could satisfy alignment by removing Nops.
-+// The function returns the total Nops Size we need to insert.
-+bool LoongArchAsmBackend::shouldInsertExtraNopBytesForCodeAlign(
-+    const MCAlignFragment &AF, unsigned &Size) {
-+  // Calculate Nops Size only when linker relaxation enabled.
-+  if (!AF.getSubtargetInfo()->hasFeature(LoongArch::FeatureRelax))
-+    return false;
-+
-+  // Ignore alignment if MaxBytesToEmit is less than the minimum Nop size.
-+  const unsigned MinNopLen = 4;
-+  if (AF.getMaxBytesToEmit() < MinNopLen)
-+    return false;
-+  Size = AF.getAlignment().value() - MinNopLen;
-+  return AF.getAlignment() > MinNopLen;
-+}
-+
-+// We need to insert R_LARCH_ALIGN relocation type to indicate the
-+// position of Nops and the total bytes of the Nops have been inserted
-+// when linker relaxation enabled.
-+// The function inserts fixup_loongarch_align fixup which eventually will
-+// transfer to R_LARCH_ALIGN relocation type.
-+// The improved R_LARCH_ALIGN requires symbol index. The lowest 8 bits of
-+// addend represent alignment and the other bits of addend represent the
-+// maximum number of bytes to emit. The maximum number of bytes is zero
-+// means ignore the emit limit.
-+bool LoongArchAsmBackend::shouldInsertFixupForCodeAlign(
-+    MCAssembler &Asm, const MCAsmLayout &Layout, MCAlignFragment &AF) {
-+  // Insert the fixup only when linker relaxation enabled.
-+  if (!AF.getSubtargetInfo()->hasFeature(LoongArch::FeatureRelax))
-+    return false;
-+
-+  // Calculate total Nops we need to insert. If there are none to insert
-+  // then simply return.
-+  unsigned Count;
-+  if (!shouldInsertExtraNopBytesForCodeAlign(AF, Count))
-+    return false;
-+
-+  MCSection *Sec = AF.getParent();
-+  MCContext &Ctx = Asm.getContext();
-+  const MCExpr *Dummy = MCConstantExpr::create(0, Ctx);
-+  // Create fixup_loongarch_align fixup.
-+  MCFixup Fixup =
-+      MCFixup::create(0, Dummy, MCFixupKind(LoongArch::fixup_loongarch_align));
-+  const MCSymbolRefExpr *MCSym = getSecToAlignSym()Sec;
-+  if (MCSym == nullptr) {
-+    // Create a symbol and make the value of symbol is zero.
-+    MCSymbol *Sym = Ctx.createNamedTempSymbol("la-relax-align");
-+    Sym->setFragment(&*Sec->getBeginSymbol()->getFragment());
-+    Asm.registerSymbol(*Sym);
-+    MCSym = MCSymbolRefExpr::create(Sym, Ctx);
-+    getSecToAlignSym()Sec = MCSym;
-+  }
-+
-+  uint64_t FixedValue = 0;
-+  unsigned Lo = Log2_64(Count) + 1;
-+  unsigned Hi = AF.getMaxBytesToEmit() >= Count ? 0 : AF.getMaxBytesToEmit();
-+  MCValue Value = MCValue::get(MCSym, nullptr, Hi << 8 | Lo);
-+  Asm.getWriter().recordRelocation(Asm, Layout, &AF, Fixup, Value, FixedValue);
-+
-+  return true;
-+}
-+
- bool LoongArchAsmBackend::shouldForceRelocation(const MCAssembler &Asm,
-                                                 const MCFixup &Fixup,
-                                                 const MCValue &Target) {
-diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h
-index 657f5ca5e731..71bbd003888a 100644
---- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h
-+++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h
-@@ -17,7 +17,9 @@
- #include "MCTargetDesc/LoongArchFixupKinds.h"
- #include "MCTargetDesc/LoongArchMCTargetDesc.h"
- #include "llvm/MC/MCAsmBackend.h"
-+#include "llvm/MC/MCExpr.h"
- #include "llvm/MC/MCFixupKindInfo.h"
-+#include "llvm/MC/MCSection.h"
- #include "llvm/MC/MCSubtargetInfo.h"
- 
- namespace llvm {
-@@ -27,6 +29,7 @@ class LoongArchAsmBackend : public MCAsmBackend {
-   uint8_t OSABI;
-   bool Is64Bit;
-   const MCTargetOptions &TargetOptions;
-+  DenseMap<MCSection *, const MCSymbolRefExpr *> SecToAlignSym;
- 
- public:
-   LoongArchAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit,
-@@ -45,6 +48,15 @@ public:
-                   uint64_t Value, bool IsResolved,
-                   const MCSubtargetInfo *STI) const override;
- 
-+  // Return Size with extra Nop Bytes for alignment directive in code section.
-+  bool shouldInsertExtraNopBytesForCodeAlign(const MCAlignFragment &AF,
-+                                             unsigned &Size) override;
-+
-+  // Insert target specific fixup type for alignment directive in code section.
-+  bool shouldInsertFixupForCodeAlign(MCAssembler &Asm,
-+                                     const MCAsmLayout &Layout,
-+                                     MCAlignFragment &AF) override;
-+
-   bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
-                              const MCValue &Target) override;
- 
-@@ -79,6 +91,9 @@ public:
-   std::unique_ptr<MCObjectTargetWriter>
-   createObjectTargetWriter() const override;
-   const MCTargetOptions &getTargetOptions() const { return TargetOptions; }
-+  DenseMap<MCSection *, const MCSymbolRefExpr *> &getSecToAlignSym() {
-+    return SecToAlignSym;
-+  }
- };
- } // end namespace llvm
- 
-diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchFixupKinds.h b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchFixupKinds.h
-index 178fa6e5262b..78414408f21f 100644
---- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchFixupKinds.h
-+++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchFixupKinds.h
-@@ -108,7 +108,9 @@ enum Fixups {
-   // 20-bit fixup corresponding to %gd_hi20(foo) for instruction lu12i.w.
-   fixup_loongarch_tls_gd_hi20,
-   // Generate an R_LARCH_RELAX which indicates the linker may relax here.
--  fixup_loongarch_relax = FirstLiteralRelocationKind + ELF::R_LARCH_RELAX
-+  fixup_loongarch_relax = FirstLiteralRelocationKind + ELF::R_LARCH_RELAX,
-+  // Generate an R_LARCH_ALIGN which indicates the linker may fixup align here.
-+  fixup_loongarch_align = FirstLiteralRelocationKind + ELF::R_LARCH_ALIGN,
- };
- } // end namespace LoongArch
- } // end namespace llvm
-diff --git a/llvm/test/MC/LoongArch/Relocations/align-non-executable.s b/llvm/test/MC/LoongArch/Relocations/align-non-executable.s
-new file mode 100644
-index 000000000000..47834acd9521
---- /dev/null

_service:tar_scm:0008-Backport-test-Update-dwarf-loongarch-relocs.ll.patch Deleted

@@ -1,86 +0,0 @@
-From f51ee6c3468eacc82d3b3f09fcca381178bdc9e7 Mon Sep 17 00:00:00 2001
-From: Weining Lu <luweining@loongson.cn>
-Date: Wed, 24 Jan 2024 11:03:14 +0800
-Subject: PATCH 11/14 test Update dwarf-loongarch-relocs.ll
-
-Address buildbot faiures:
-http://45.33.8.238/macm1/77360/step_11.txt
-http://45.33.8.238/linux/128902/step_12.txt
-
-(cherry picked from commit baba7e4175b6ca21e83b1cf8229f29dbba02e979)
-(cherry picked from commit c9e73cdd9a17f15ede120ea57657553f9e105eab)
-Change-Id: I00aa1414f556f0ba5ff6bf6a879a6fc1fcfa49e0
----
- .../LoongArch/dwarf-loongarch-relocs.ll       | 37 ++++++++++++-------
- 1 file changed, 23 insertions(+), 14 deletions(-)
-
-diff --git a/llvm/test/DebugInfo/LoongArch/dwarf-loongarch-relocs.ll b/llvm/test/DebugInfo/LoongArch/dwarf-loongarch-relocs.ll
-index e03b4c1d34de..07443a62b933 100644
---- a/llvm/test/DebugInfo/LoongArch/dwarf-loongarch-relocs.ll
-+++ b/llvm/test/DebugInfo/LoongArch/dwarf-loongarch-relocs.ll
-@@ -1,19 +1,22 @@
- ; RUN: llc --filetype=obj --mtriple=loongarch64 --mattr=-relax %s -o %t.o
- ; RUN: llvm-readobj -r %t.o | FileCheck --check-prefixes=RELOCS-BOTH,RELOCS-NORL %s
--; RUN: llvm-objdump --source %t.o | FileCheck --check-prefix=SOURCE %s
--; RUN: llvm-dwarfdump --debug-info --debug-line %t.o | FileCheck --check-prefix=DWARF %s
-+; RUN: llvm-objdump --source %t.o | FileCheck --check-prefixes=SOURCE,SOURCE-NORL %s
-+; RUN: llvm-dwarfdump --debug-info --debug-line %t.o | FileCheck --check-prefixes=DWARF,DWARF-NORL %s
- 
- ; RUN: llc --filetype=obj --mtriple=loongarch64 --mattr=+relax %s -o %t.r.o
- ; RUN: llvm-readobj -r %t.r.o | FileCheck --check-prefixes=RELOCS-BOTH,RELOCS-ENRL %s
--; RUN: llvm-objdump --source %t.r.o | FileCheck --check-prefix=SOURCE %s
--; RUN: llvm-dwarfdump --debug-info --debug-line %t.r.o | FileCheck --check-prefix=DWARF %s
-+; RUN: llvm-objdump --source %t.r.o | FileCheck --check-prefixes=SOURCE,SOURCE-ENRL %s
-+; RUN: llvm-dwarfdump --debug-info --debug-line %t.r.o | FileCheck --check-prefixes=DWARF,DWARF-ENRL %s
- 
- ; RELOCS-BOTH:       Relocations 
- ; RELOCS-BOTH-NEXT:    Section ({{.*}}) .rela.text {
--; RELOCS-BOTH-NEXT:      0x14 R_LARCH_PCALA_HI20 sym 0x0
--; RELOCS-ENRL-NEXT:      0x14 R_LARCH_RELAX - 0x0
--; RELOCS-BOTH-NEXT:      0x18 R_LARCH_PCALA_LO12 sym 0x0
--; RELOCS-ENRL-NEXT:      0x18 R_LARCH_RELAX - 0x0
-+; RELOCS-NORL-NEXT:      0x14 R_LARCH_PCALA_HI20 sym 0x0
-+; RELOCS-NORL-NEXT:      0x18 R_LARCH_PCALA_LO12 sym 0x0
-+; RELOCS-ENRL-NEXT:      0x0 R_LARCH_ALIGN .Lla-relax-align0 0x5
-+; RELOCS-ENRL-NEXT:      0x30 R_LARCH_PCALA_HI20 sym 0x0
-+; RELOCS-ENRL-NEXT:      0x30 R_LARCH_RELAX - 0x0
-+; RELOCS-ENRL-NEXT:      0x34 R_LARCH_PCALA_LO12 sym 0x0
-+; RELOCS-ENRL-NEXT:      0x34 R_LARCH_RELAX - 0x0
- ; RELOCS-BOTH-NEXT:    }
- ; RELOCS-BOTH:         Section ({{.*}}) .rela.debug_frame {
- ; RELOCS-NORL-NEXT:      0x1C R_LARCH_32 .debug_frame 0x0
-@@ -36,7 +39,8 @@
- ; RELOCS-BOTH-NEXT:    }
- ; RELOCS-BOTH-NEXT:  
- 
--; SOURCE:  0000000000000000 <foo>:
-+; SOURCE-NORL:  0000000000000000 <foo>:
-+; SOURCE-ENRL:  000000000000001c <foo>:
- ; SOURCE:  ; {
- ; SOURCE:  ;   asm volatile(
- ; SOURCE:  ;   return 0;
-@@ -87,11 +91,16 @@
- ; DWARF-EMPTY:
- ; DWARF-NEXT:  Address            Line   Column File   ISA Discriminator OpIndex Flags
- ; DWARF-NEXT:  ------------------ ------ ------ ------ --- ------------- ------- -------------
--; DWARF-NEXT:  0x0000000000000000      2      0      0   0             0       0  is_stmt
--; DWARF-NEXT:  0x0000000000000010      3      3      0   0             0       0  is_stmt prologue_end
--; DWARF-NEXT:  0x0000000000000020     10      3      0   0             0       0  is_stmt
--; DWARF-NEXT:  0x000000000000002c     10      3      0   0             0       0  epilogue_begin
--; DWARF-NEXT:  0x0000000000000034     10      3      0   0             0       0  end_sequence
-+; DWARF-NORL-NEXT:  0x0000000000000000      2      0      0   0             0       0  is_stmt
-+; DWARF-NORL-NEXT:  0x0000000000000010      3      3      0   0             0       0  is_stmt prologue_end
-+; DWARF-NORL-NEXT:  0x0000000000000020     10      3      0   0             0       0  is_stmt
-+; DWARF-NORL-NEXT:  0x000000000000002c     10      3      0   0             0       0  epilogue_begin
-+; DWARF-NORL-NEXT:  0x0000000000000034     10      3      0   0             0       0  end_sequence
-+; DWARF-ENRL-NEXT:  0x000000000000001c      2      0      0   0             0       0  is_stmt
-+; DWARF-ENRL-NEXT:  0x000000000000002c      3      3      0   0             0       0  is_stmt prologue_end
-+; DWARF-ENRL-NEXT:  0x000000000000003c     10      3      0   0             0       0  is_stmt
-+; DWARF-ENRL-NEXT:  0x0000000000000048     10      3      0   0             0       0  epilogue_begin
-+; DWARF-ENRL-NEXT:  0x0000000000000050     10      3      0   0             0       0  end_sequence
- 
- ; ModuleID = 'dwarf-loongarch-relocs.c'
- source_filename = "dwarf-loongarch-relocs.c"
--- 
-2.20.1
-

_service:tar_scm:0009-Backport-MC-test-Change-ELF-uleb-ehtable.s-Mach-O-to-use-private-symbols-in-.uleb128-for-label-differences.patch Deleted

@@ -1,53 +0,0 @@
-From 442b5109ccbabed1110c122c1ca92d4194ba632b Mon Sep 17 00:00:00 2001
-From: Fangrui Song <i@maskray.me>
-Date: Wed, 9 Aug 2023 21:42:18 -0700
-Subject: PATCH 13/14 MCtest Change ELF/uleb-ehtable.s Mach-O to use
- private symbols in .uleb128 for label differences
-
-On Mach-O, `.uleb128 A-B` where A and B are separated by a non-private symbol is invalid
-(see D153167).
-
-(cherry picked from commit 0a89bda4a8b756a00985e0965f7686b5ceb43295)
-Change-Id: I92ed11d6913b8c781e29be6e8c642cf0a371910d
----
- llvm/test/MC/ELF/uleb-ehtable.s | 13 +++++++++++--
- 1 file changed, 11 insertions(+), 2 deletions(-)
-
-diff --git a/llvm/test/MC/ELF/uleb-ehtable.s b/llvm/test/MC/ELF/uleb-ehtable.s
-index ca3f9e97bffc..6407223f36e7 100644
---- a/llvm/test/MC/ELF/uleb-ehtable.s
-+++ b/llvm/test/MC/ELF/uleb-ehtable.s
-@@ -1,7 +1,7 @@
- // RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu    %s -o - | llvm-readobj -S --sd - | FileCheck %s -check-prefix=CHECK -check-prefix=ELF
- // RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu  %s -o - | llvm-readobj -S --sd - | FileCheck %s -check-prefix=CHECK -check-prefix=ELF
--// RUN: llvm-mc -filetype=obj -triple i386-apple-darwin9   %s -o - | llvm-readobj -S --sd - | FileCheck %s -check-prefix=CHECK -check-prefix=MACHO
--// RUN: llvm-mc -filetype=obj -triple x86_64-apple-darwin9 %s -o - | llvm-readobj -S --sd - | FileCheck %s -check-prefix=CHECK -check-prefix=MACHO
-+// RUN: llvm-mc -filetype=obj -triple i386-apple-darwin9 --defsym MACHO=1 %s -o - | llvm-readobj -S --sd - | FileCheck %s -check-prefix=CHECK -check-prefix=MACHO
-+// RUN: llvm-mc -filetype=obj -triple x86_64-apple-darwin9 --defsym MACHO=1 %s -o - | llvm-readobj -S --sd - | FileCheck %s -check-prefix=CHECK -check-prefix=MACHO
- 
- // Test that we can assemble a GCC-like EH table that has 16381-16383 bytes of
- // non-padding data between .ttbaseref and .ttbase. The assembler must insert
-@@ -13,11 +13,20 @@
- foo:
-         .byte 0xff  // LPStart omitted
-         .byte 0x1   // TType encoding (uleb128)
-+.ifdef MACHO
-+        .uleb128 Lttbase-Lttbaseref
-+Lttbaseref:
-+.else
-         .uleb128 .ttbase-.ttbaseref
- .ttbaseref:
-+.endif
-         .fill 128*128-1, 1, 0xcd    // call site and actions tables
-         .balign 4
-+.ifdef MACHO
-+Lttbase:
-+.else
- .ttbase:
-+.endif
-         .byte 1, 2, 3, 4
- 
- // ELF:   Name: .data
--- 
-2.20.1
-

_service:tar_scm:0010-Backport-Mips-MC-AttemptToFoldSymbolOffsetDifference-revert-isMicroMips-special-case.patch Deleted

@@ -1,135 +0,0 @@
-From 3b777f98a3997f338919af7ff1ef8a6fd07f76a0 Mon Sep 17 00:00:00 2001
-From: Fangrui Song <i@maskray.me>
-Date: Wed, 16 Aug 2023 23:11:59 -0700
-Subject: PATCH 14/14 MipsMC AttemptToFoldSymbolOffsetDifference: revert
- isMicroMips special case
-
-D52985/D57677 added a .gcc_except_table workaround, but the new behavior
-doesn't match GNU assembler.
-```
-void foo();
-int bar() {
-  foo();
-  try { throw 1; }
-  catch (int) { return 1; }
-  return 0;
-}
-
-clang --target=mipsel-linux-gnu -mmicromips -S a.cc
-mipsel-linux-gnu-gcc -mmicromips -c a.s -o gnu.o
-
-.uleb128 ($cst_end0)-($cst_begin0)     // bit 0 is not forced to 1
-.uleb128 ($func_begin0)-($func_begin0) // bit 0 is not forced to 1
-```
-
-I have inspected `.gcc_except_table` output by `mipsel-linux-gnu-gcc -mmicromips -c a.cc`.
-The `.uleb128` values are not forced to set the least significant bit.
-
-In addition, D57677's adjustment (even->odd) to CodeGen/Mips/micromips-b-range.ll is wrong.
-PC-relative `.long func - .` values will differ from GNU assembler as well.
-
-The original intention of D52985 seems unclear to me. I think whatever
-goal it wants to achieve should be moved to an upper layer.
-
-This isMicroMips special case has caused problems to fix MCAssembler::relaxLEB to use evaluateAsAbsolute instead of evaluateKnownAbsolute,
-which is needed to proper support R_RISCV_SET_ULEB128/R_RISCV_SUB_ULEB128.
-
-Differential Revision: https://reviews.llvm.org/D157655
-
-(cherry picked from commit 4c89277095ee7cda3d20e0f5f18b384212069778)
-Change-Id: Iedd73e0c61856c30fde442309fc16d4327829f1a
----
- llvm/lib/MC/MCExpr.cpp                               | 5 -----
- llvm/test/CodeGen/Mips/micromips-b-range.ll          | 8 ++++----
- llvm/test/CodeGen/Mips/micromips-gcc-except-table.ll | 2 +-
- llvm/test/DebugInfo/Mips/eh_frame.ll                 | 4 ++--
- 4 files changed, 7 insertions(+), 12 deletions(-)
-
-diff --git a/llvm/lib/MC/MCExpr.cpp b/llvm/lib/MC/MCExpr.cpp
-index 79808a58d81c..c9ff1865cf91 100644
---- a/llvm/lib/MC/MCExpr.cpp
-+++ b/llvm/lib/MC/MCExpr.cpp
-@@ -611,11 +611,6 @@ static void AttemptToFoldSymbolOffsetDifference(
-     if (Asm->isThumbFunc(&SA))
-       Addend |= 1;
- 
--    // If symbol is labeled as micromips, we set low-bit to ensure
--    // correct offset in .gcc_except_table
--    if (Asm->getBackend().isMicroMips(&SA))
--      Addend |= 1;
--
-     // Clear the symbol expr pointers to indicate we have folded these
-     // operands.
-     A = B = nullptr;
-diff --git a/llvm/test/CodeGen/Mips/micromips-b-range.ll b/llvm/test/CodeGen/Mips/micromips-b-range.ll
-index 064afff3da0e..81d1c04208cc 100644
---- a/llvm/test/CodeGen/Mips/micromips-b-range.ll
-+++ b/llvm/test/CodeGen/Mips/micromips-b-range.ll
-@@ -13,7 +13,7 @@
- ; CHECK-NEXT:    1e:	fb fd 00 00 	sw	$ra, 0($sp)
- ; CHECK-NEXT:    22:	41 a1 00 01 	lui	$1, 1
- ; CHECK-NEXT:    26:	40 60 00 02 	bal	0x2e <foo+0x2e>
--; CHECK-NEXT:    2a:	30 21 04 69 	addiu	$1, $1, 1129
-+; CHECK-NEXT:    2a:	30 21 04 68 	addiu	$1, $1, 1128
- ; CHECK-NEXT:    2e:	00 3f 09 50 	addu	$1, $ra, $1
- ; CHECK-NEXT:    32:	ff fd 00 00 	lw	$ra, 0($sp)
- ; CHECK-NEXT:    36:	00 01 0f 3c 	jr	$1
-@@ -27,7 +27,7 @@
- ; CHECK-NEXT:    56:	fb fd 00 00 	sw	$ra, 0($sp)
- ; CHECK-NEXT:    5a:	41 a1 00 01 	lui	$1, 1
- ; CHECK-NEXT:    5e:	40 60 00 02 	bal	0x66 <foo+0x66>
--; CHECK-NEXT:    62:	30 21 04 5d 	addiu	$1, $1, 1117
-+; CHECK-NEXT:    62:	30 21 04 5c 	addiu	$1, $1, 1116
- ; CHECK-NEXT:    66:	00 3f 09 50 	addu	$1, $ra, $1
- ; CHECK-NEXT:    6a:	ff fd 00 00 	lw	$ra, 0($sp)
- ; CHECK-NEXT:    6e:	00 01 0f 3c 	jr	$1
-@@ -39,7 +39,7 @@
- ; CHECK-NEXT:    86:	fb fd 00 00 	sw	$ra, 0($sp)
- ; CHECK-NEXT:    8a:	41 a1 00 01 	lui	$1, 1
- ; CHECK-NEXT:    8e:	40 60 00 02 	bal	0x96 <foo+0x96>
--; CHECK-NEXT:    92:	30 21 04 2d 	addiu	$1, $1, 1069
-+; CHECK-NEXT:    92:	30 21 04 2c 	addiu	$1, $1, 1068
- ; CHECK-NEXT:    96:	00 3f 09 50 	addu	$1, $ra, $1
- ; CHECK-NEXT:    9a:	ff fd 00 00 	lw	$ra, 0($sp)
- ; CHECK-NEXT:    9e:	00 01 0f 3c 	jr	$1
-@@ -51,7 +51,7 @@
- ; CHECK-NEXT: 10476:	fb fd 00 00 	sw	$ra, 0($sp)
- ; CHECK-NEXT: 1047a:	41 a1 00 01 	lui	$1, 1
- ; CHECK-NEXT: 1047e:	40 60 00 02 	bal	0x10486 <foo+0x10486>
--; CHECK-NEXT: 10482:	30 21 04 01 	addiu	$1, $1, 1025
-+; CHECK-NEXT: 10482:	30 21 04 00 	addiu	$1, $1, 1024
- ; CHECK-NEXT: 10486:	00 3f 09 50 	addu	$1, $ra, $1
- ; CHECK-NEXT: 1048a:	ff fd 00 00 	lw	$ra, 0($sp)
- ; CHECK-NEXT: 1048e:	00 01 0f 3c 	jr	$1
-diff --git a/llvm/test/CodeGen/Mips/micromips-gcc-except-table.ll b/llvm/test/CodeGen/Mips/micromips-gcc-except-table.ll
-index 2b63aff01574..20d64fc216b7 100644
---- a/llvm/test/CodeGen/Mips/micromips-gcc-except-table.ll
-+++ b/llvm/test/CodeGen/Mips/micromips-gcc-except-table.ll
-@@ -1,7 +1,7 @@
- ; RUN: llc -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+micromips -O3 -filetype=obj < %s | llvm-objdump -s -j .gcc_except_table - | FileCheck %s
- 
- ; CHECK: Contents of section .gcc_except_table:
--; CHECK-NEXT: 0000 ff9b1501 0c011100 00110e1f 011f1800
-+; CHECK-NEXT: 0000 ff9b1501 0c001000 00100e1e 011e1800
- ; CHECK-NEXT: 0010 00010000 00000000
- 
- @_ZTIi = external constant ptr
-diff --git a/llvm/test/DebugInfo/Mips/eh_frame.ll b/llvm/test/DebugInfo/Mips/eh_frame.ll
-index 506e5b87892b..60d4dc76777e 100644
---- a/llvm/test/DebugInfo/Mips/eh_frame.ll
-+++ b/llvm/test/DebugInfo/Mips/eh_frame.ll
-@@ -26,9 +26,9 @@
- ; CHECK-READELF-PIC-NEXT: R_MIPS_PC32
- ; CHECK-READELF-NEXT: .gcc_except_table
- 
--; EXCEPT-TABLE-STATIC: 0000 ff9b1501 0c011500 00150e23 01231e00  ...........#.#..
-+; EXCEPT-TABLE-STATIC: 0000 ff9b1501 0c001400 00140e22 01221e00 ..........."."..
- ; EXCEPT-TABLE-STATIC: 0010 00010000 00000000
--; EXCEPT-TABLE-PIC:    0000 ff9b1501 0c012d00 002d133f 013f2a00 ......-..-.?.?*.
-+; EXCEPT-TABLE-PIC:    0000 ff9b1501 0c002c00 002c123e 013e2a00 ......,..,.>.>*.
- ; EXCEPT-TABLE-PIC:    0010 00010000 00000000                    ........
- 
- @_ZTIi = external constant ptr
--- 
-2.20.1
-

_service:tar_scm:0011-Backport-LoongArch-Add-the-support-for-vector-in-llvm17.patch Deleted

@@ -1,56520 +0,0 @@
-From 6ff32ae0ca7a400249535b19d9ca489b44deae19 Mon Sep 17 00:00:00 2001
-From: wanglei <wanglei@loongson.cn>
-Date: Wed, 9 Aug 2023 16:01:37 +0800
-Subject: PATCH 01/35 ClangLoongArch Use the ClangBuiltin class to
- automatically generate support for CBE and CFE
-
-Fixed the type modifier (L->W), removed redundant feature checking code
-since the feature has already been checked in `EmitBuiltinExpr`. And
-Cleaned up unused diagnostic information.
-
-Reviewed By: SixWeining
-
-Differential Revision: https://reviews.llvm.org/D156866
-
-(cherry picked from commit ea8d3b1f9f2d7385d97fcd34d14db0eb2cb2795c)
----
- llvm/include/llvm/IR/IntrinsicsLoongArch.td | 141 ++++++++++----------
- llvm/lib/IR/Function.cpp                    |   1 +
- 2 files changed, 72 insertions(+), 70 deletions(-)
-
-diff --git a/llvm/include/llvm/IR/IntrinsicsLoongArch.td b/llvm/include/llvm/IR/IntrinsicsLoongArch.td
-index 5edce3c529e1..4219b2f55346 100644
---- a/llvm/include/llvm/IR/IntrinsicsLoongArch.td
-+++ b/llvm/include/llvm/IR/IntrinsicsLoongArch.td
-@@ -51,74 +51,75 @@ defm int_loongarch_masked_cmpxchg : MaskedAtomicRMWFiveOpIntrinsics;
- //===----------------------------------------------------------------------===//
- // LoongArch BASE
- 
--def int_loongarch_break : Intrinsic<, llvm_i32_ty, ImmArg<ArgIndex<0>>>;
--def int_loongarch_cacop_d : Intrinsic<, llvm_i64_ty, llvm_i64_ty, llvm_i64_ty,
--    ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>>;
--def int_loongarch_cacop_w : Intrinsic<, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
--    ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>>;
--def int_loongarch_dbar : Intrinsic<, llvm_i32_ty, ImmArg<ArgIndex<0>>>;
--def int_loongarch_ibar : Intrinsic<, llvm_i32_ty, ImmArg<ArgIndex<0>>>;
--def int_loongarch_movfcsr2gr : Intrinsic<llvm_i32_ty, llvm_i32_ty,
--                               ImmArg<ArgIndex<0>>>;
--def int_loongarch_movgr2fcsr : Intrinsic<, llvm_i32_ty, llvm_i32_ty,
--                               ImmArg<ArgIndex<0>>>;
--def int_loongarch_syscall : Intrinsic<, llvm_i32_ty, ImmArg<ArgIndex<0>>>;
--
--def int_loongarch_crc_w_b_w : Intrinsic<llvm_i32_ty,
--                                        llvm_i32_ty, llvm_i32_ty>;
--def int_loongarch_crc_w_h_w : Intrinsic<llvm_i32_ty,
--                                        llvm_i32_ty, llvm_i32_ty>;
--def int_loongarch_crc_w_w_w : Intrinsic<llvm_i32_ty,
--                                        llvm_i32_ty, llvm_i32_ty>;
--def int_loongarch_crc_w_d_w : Intrinsic<llvm_i32_ty,
--                                        llvm_i64_ty, llvm_i32_ty>;
--
--def int_loongarch_crcc_w_b_w : Intrinsic<llvm_i32_ty,
--                                         llvm_i32_ty, llvm_i32_ty>;
--def int_loongarch_crcc_w_h_w : Intrinsic<llvm_i32_ty,
--                                         llvm_i32_ty, llvm_i32_ty>;
--def int_loongarch_crcc_w_w_w : Intrinsic<llvm_i32_ty,
--                                         llvm_i32_ty, llvm_i32_ty>;
--def int_loongarch_crcc_w_d_w : Intrinsic<llvm_i32_ty,
--                                         llvm_i64_ty, llvm_i32_ty>;
--
--def int_loongarch_csrrd_w : Intrinsic<llvm_i32_ty, llvm_i32_ty,
--                                      ImmArg<ArgIndex<0>>>;
--def int_loongarch_csrrd_d : Intrinsic<llvm_i64_ty, llvm_i32_ty,
--                                      ImmArg<ArgIndex<0>>>;
--def int_loongarch_csrwr_w : Intrinsic<llvm_i32_ty,
--                                      llvm_i32_ty, llvm_i32_ty,
--                                      ImmArg<ArgIndex<1>>>;
--def int_loongarch_csrwr_d : Intrinsic<llvm_i64_ty,
--                                      llvm_i64_ty, llvm_i32_ty,
--                                      ImmArg<ArgIndex<1>>>;
--def int_loongarch_csrxchg_w : Intrinsic<llvm_i32_ty,
--                                        llvm_i32_ty, llvm_i32_ty,
--                                         llvm_i32_ty,
--                                        ImmArg<ArgIndex<2>>>;
--def int_loongarch_csrxchg_d : Intrinsic<llvm_i64_ty,
--                                        llvm_i64_ty, llvm_i64_ty,
--                                         llvm_i32_ty,
--                                        ImmArg<ArgIndex<2>>>;
--
--def int_loongarch_iocsrrd_b : Intrinsic<llvm_i32_ty, llvm_i32_ty>;
--def int_loongarch_iocsrrd_h : Intrinsic<llvm_i32_ty, llvm_i32_ty>;
--def int_loongarch_iocsrrd_w : Intrinsic<llvm_i32_ty, llvm_i32_ty>;
--def int_loongarch_iocsrrd_d : Intrinsic<llvm_i64_ty, llvm_i32_ty>;
--
--def int_loongarch_iocsrwr_b : Intrinsic<, llvm_i32_ty, llvm_i32_ty>;
--def int_loongarch_iocsrwr_h : Intrinsic<, llvm_i32_ty, llvm_i32_ty>;
--def int_loongarch_iocsrwr_w : Intrinsic<, llvm_i32_ty, llvm_i32_ty>;
--def int_loongarch_iocsrwr_d : Intrinsic<, llvm_i64_ty, llvm_i32_ty>;
--
--def int_loongarch_cpucfg : Intrinsic<llvm_i32_ty, llvm_i32_ty>;
--
--def int_loongarch_asrtle_d : Intrinsic<, llvm_i64_ty, llvm_i64_ty>;
--def int_loongarch_asrtgt_d : Intrinsic<, llvm_i64_ty, llvm_i64_ty>;
--
--def int_loongarch_lddir_d : Intrinsic<llvm_i64_ty,
--                                      llvm_i64_ty, llvm_i64_ty,
--                                      ImmArg<ArgIndex<1>>>;
--def int_loongarch_ldpte_d : Intrinsic<, llvm_i64_ty, llvm_i64_ty,
--                                          ImmArg<ArgIndex<1>>>;
-+class BaseInt<list<LLVMType> ret_types, list<LLVMType> param_types,
-+              list<IntrinsicProperty> intr_properties = >
-+    : Intrinsic<ret_types, param_types, intr_properties>,
-+      ClangBuiltin<!subst("int_loongarch", "__builtin_loongarch", NAME)>;
-+
-+def int_loongarch_break : BaseInt<, llvm_i32_ty, ImmArg<ArgIndex<0>>>;
-+def int_loongarch_cacop_d : BaseInt<, llvm_i64_ty, llvm_i64_ty, llvm_i64_ty,
-+                                    ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>>;
-+def int_loongarch_cacop_w : BaseInt<, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
-+                                    ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>>;
-+def int_loongarch_dbar : BaseInt<, llvm_i32_ty, ImmArg<ArgIndex<0>>>;
-+
-+def int_loongarch_ibar : BaseInt<, llvm_i32_ty, ImmArg<ArgIndex<0>>>;
-+def int_loongarch_movfcsr2gr : BaseInt<llvm_i32_ty, llvm_i32_ty,
-+                                       ImmArg<ArgIndex<0>>>;
-+def int_loongarch_movgr2fcsr : BaseInt<, llvm_i32_ty, llvm_i32_ty,
-+                                       ImmArg<ArgIndex<0>>>;
-+def int_loongarch_syscall : BaseInt<, llvm_i32_ty, ImmArg<ArgIndex<0>>>;
-+
-+def int_loongarch_crc_w_b_w : BaseInt<llvm_i32_ty,
-+                                      llvm_i32_ty, llvm_i32_ty>;
-+def int_loongarch_crc_w_h_w : BaseInt<llvm_i32_ty,
-+                                      llvm_i32_ty, llvm_i32_ty>;
-+def int_loongarch_crc_w_w_w : BaseInt<llvm_i32_ty,
-+                                      llvm_i32_ty, llvm_i32_ty>;
-+def int_loongarch_crc_w_d_w : BaseInt<llvm_i32_ty,
-+                                      llvm_i64_ty, llvm_i32_ty>;
-+
-+def int_loongarch_crcc_w_b_w : BaseInt<llvm_i32_ty,
-+                                       llvm_i32_ty, llvm_i32_ty>;
-+def int_loongarch_crcc_w_h_w : BaseInt<llvm_i32_ty,
-+                                       llvm_i32_ty, llvm_i32_ty>;
-+def int_loongarch_crcc_w_w_w : BaseInt<llvm_i32_ty,
-+                                       llvm_i32_ty, llvm_i32_ty>;
-+def int_loongarch_crcc_w_d_w : BaseInt<llvm_i32_ty,
-+                                       llvm_i64_ty, llvm_i32_ty>;
-+
-+def int_loongarch_csrrd_w : BaseInt<llvm_i32_ty, llvm_i32_ty,
-+                                    ImmArg<ArgIndex<0>>>;
-+def int_loongarch_csrrd_d : BaseInt<llvm_i64_ty, llvm_i32_ty,
-+                                    ImmArg<ArgIndex<0>>>;
-+def int_loongarch_csrwr_w : BaseInt<llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
-+                                    ImmArg<ArgIndex<1>>>;
-+def int_loongarch_csrwr_d : BaseInt<llvm_i64_ty, llvm_i64_ty, llvm_i32_ty,
-+                                    ImmArg<ArgIndex<1>>>;
-+def int_loongarch_csrxchg_w : BaseInt<llvm_i32_ty,
-+                                      llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
-+                                      ImmArg<ArgIndex<2>>>;
-+def int_loongarch_csrxchg_d : BaseInt<llvm_i64_ty,
-+                                      llvm_i64_ty, llvm_i64_ty, llvm_i32_ty,
-+                                      ImmArg<ArgIndex<2>>>;
-+
-+def int_loongarch_iocsrrd_b : BaseInt<llvm_i32_ty, llvm_i32_ty>;
-+def int_loongarch_iocsrrd_h : BaseInt<llvm_i32_ty, llvm_i32_ty>;
-+def int_loongarch_iocsrrd_w : BaseInt<llvm_i32_ty, llvm_i32_ty>;
-+def int_loongarch_iocsrrd_d : BaseInt<llvm_i64_ty, llvm_i32_ty>;
-+
-+def int_loongarch_iocsrwr_b : BaseInt<, llvm_i32_ty, llvm_i32_ty>;
-+def int_loongarch_iocsrwr_h : BaseInt<, llvm_i32_ty, llvm_i32_ty>;
-+def int_loongarch_iocsrwr_w : BaseInt<, llvm_i32_ty, llvm_i32_ty>;
-+def int_loongarch_iocsrwr_d : BaseInt<, llvm_i64_ty, llvm_i32_ty>;
-+
-+def int_loongarch_cpucfg : BaseInt<llvm_i32_ty, llvm_i32_ty>;
-+
-+def int_loongarch_asrtle_d : BaseInt<, llvm_i64_ty, llvm_i64_ty>;
-+def int_loongarch_asrtgt_d : BaseInt<, llvm_i64_ty, llvm_i64_ty>;
-+
-+def int_loongarch_lddir_d : BaseInt<llvm_i64_ty, llvm_i64_ty, llvm_i64_ty,
-+                                    ImmArg<ArgIndex<1>>>;
-+def int_loongarch_ldpte_d : BaseInt<, llvm_i64_ty, llvm_i64_ty,
-+                                    ImmArg<ArgIndex<1>>>;
- } // TargetPrefix = "loongarch"
-diff --git a/llvm/lib/IR/Function.cpp b/llvm/lib/IR/Function.cpp
-index 27219e89dc5f..435800d9e5f9 100644
---- a/llvm/lib/IR/Function.cpp
-+++ b/llvm/lib/IR/Function.cpp
-@@ -37,6 +37,7 @@
- #include "llvm/IR/IntrinsicsBPF.h"
- #include "llvm/IR/IntrinsicsDirectX.h"
- #include "llvm/IR/IntrinsicsHexagon.h"
-+#include "llvm/IR/IntrinsicsLoongArch.h"
- #include "llvm/IR/IntrinsicsMips.h"
- #include "llvm/IR/IntrinsicsNVPTX.h"
- #include "llvm/IR/IntrinsicsPowerPC.h"
--- 
-2.20.1
-
-
-From fca9d0a876fb72d3b483044a7616d27a47121512 Mon Sep 17 00:00:00 2001
-From: wanglei <wanglei@loongson.cn>
-Date: Sat, 19 Aug 2023 15:58:38 +0800
-Subject: PATCH 02/35 LoongArch Add LSX intrinsic support
-
-For handling intrinsics, our approach is not simply to match them
-one-to-one with instructions. Instead, we lower some intrinsics
-to common nodes and then perform matching. The advantage of this
-approach is that it allows us to fully utilize the passes available
-at the common layer for optimizing purposes.
-
-We perform error checks on the immediate operand of all intrinsics,
-rather than waiting until the end to throw exceptions.

_service:tar_scm:0012-Backport-LoongArch-improve-the-support-for-compiler-rt-and-bugfix.patch Deleted

@@ -1,2474 +0,0 @@
-From 0bce68310dc0ff6a09ec2cf5c3ae32400c631324 Mon Sep 17 00:00:00 2001
-From: zhanglimin <zhanglimin@loongson.cn>
-Date: Tue, 12 Sep 2023 09:51:16 +0800
-Subject: PATCH 01/14 sanitizermsan VarArgHelper for loongarch64
-
-This patch adds support for variadic argument for loongarch64,
-which is based on MIPS64. And `check-msan` all pass.
-
-Reviewed By: vitalybuka
-
-Differential Revision: https://reviews.llvm.org/D158587
-
-(cherry picked from commit ec42c78cc43ac1e8364e5a0941aa5fc91b813dd3)
----
- .../Instrumentation/MemorySanitizer.cpp       |  7 ++
- .../LoongArch/vararg-loongarch64.ll           | 78 +++++++++++++++++++
- 2 files changed, 85 insertions(+)
- create mode 100644 llvm/test/Instrumentation/MemorySanitizer/LoongArch/vararg-loongarch64.ll
-
-diff --git a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
-index 83d90049abc3..362fd6e4151f 100644
---- a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
-+++ b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
-@@ -4945,6 +4945,7 @@ struct VarArgAMD64Helper : public VarArgHelper {
- };
- 
- /// MIPS64-specific implementation of VarArgHelper.
-+/// NOTE: This is also used for LoongArch64.
- struct VarArgMIPS64Helper : public VarArgHelper {
-   Function &F;
-   MemorySanitizer &MS;
-@@ -5836,6 +5837,10 @@ struct VarArgSystemZHelper : public VarArgHelper {
-   }
- };
- 
-+// Loongarch64 is not a MIPS, but the current vargs calling convention matches
-+// the MIPS.
-+using VarArgLoongArch64Helper = VarArgMIPS64Helper;
-+
- /// A no-op implementation of VarArgHelper.
- struct VarArgNoOpHelper : public VarArgHelper {
-   VarArgNoOpHelper(Function &F, MemorySanitizer &MS,
-@@ -5868,6 +5873,8 @@ static VarArgHelper *CreateVarArgHelper(Function &Func, MemorySanitizer &Msan,
-     return new VarArgPowerPC64Helper(Func, Msan, Visitor);
-   else if (TargetTriple.getArch() == Triple::systemz)
-     return new VarArgSystemZHelper(Func, Msan, Visitor);
-+  else if (TargetTriple.isLoongArch64())
-+    return new VarArgLoongArch64Helper(Func, Msan, Visitor);
-   else
-     return new VarArgNoOpHelper(Func, Msan, Visitor);
- }
-diff --git a/llvm/test/Instrumentation/MemorySanitizer/LoongArch/vararg-loongarch64.ll b/llvm/test/Instrumentation/MemorySanitizer/LoongArch/vararg-loongarch64.ll
-new file mode 100644
-index 000000000000..8a4ab59588ad
---- /dev/null
-+++ b/llvm/test/Instrumentation/MemorySanitizer/LoongArch/vararg-loongarch64.ll
-@@ -0,0 +1,78 @@
-+; RUN: opt < %s -S -passes=msan 2>&1 | FileCheck %s
-+
-+target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
-+target triple = "loongarch64-unknown-linux-gnu"
-+
-+;; First, check allocation of the save area.
-+declare void @llvm.lifetime.start.p0(i64, ptr nocapture) #1
-+declare void @llvm.va_start(ptr) #2
-+declare void @llvm.va_end(ptr) #2
-+declare void @llvm.lifetime.end.p0(i64, ptr nocapture) #1
-+define i32 @foo(i32 %guard, ...) {
-+; CHECK-LABEL: @foo
-+; CHECK:    TMP1:%.* = load {{.*}} @__msan_va_arg_overflow_size_tls
-+; CHECK:    TMP2:%.* = add i64 0, TMP1
-+; CHECK:    TMP3:%.* = alloca {{.*}} TMP2
-+; CHECK:    call void @llvm.memset.p0.i64(ptr align 8 TMP3, i8 0, i64 TMP2, i1 false)
-+; CHECK:    TMP4:%.* = call i64 @llvm.umin.i64(i64 TMP2, i64 800)
-+; CHECK:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 TMP3, ptr align 8 @__msan_va_arg_tls, i64 TMP4, i1 false)
-+;
-+  %vl = alloca ptr, align 8
-+  call void @llvm.lifetime.start.p0(i64 32, ptr %vl)
-+  call void @llvm.va_start(ptr %vl)
-+  call void @llvm.va_end(ptr %vl)
-+  call void @llvm.lifetime.end.p0(i64 32, ptr %vl)
-+  ret i32 0
-+}
-+
-+;; Save the incoming shadow value from the arguments in the __msan_va_arg_tls
-+;; array.
-+define i32 @bar() {
-+; CHECK-LABEL: @bar
-+; CHECK:    store i32 0, ptr @__msan_va_arg_tls, align 8
-+; CHECK:    store i64 0, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_va_arg_tls to i64), i64 8) to ptr), align 8
-+; CHECK:    store i64 0, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_va_arg_tls to i64), i64 16) to ptr), align 8
-+; CHECK:    store {{.*}} 24, {{.*}} @__msan_va_arg_overflow_size_tls
-+;
-+  %1 = call i32 (i32, ...) @foo(i32 0, i32 1, i64 2, double 3.000000e+00)
-+  ret i32 %1
-+}
-+
-+;; Check multiple fixed arguments.
-+declare i32 @foo2(i32 %g1, i32 %g2, ...)
-+define i32 @bar2() {
-+; CHECK-LABEL: @bar2
-+; CHECK:    store i64 0, ptr @__msan_va_arg_tls, align 8
-+; CHECK:    store i64 0, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_va_arg_tls to i64), i64 8) to ptr), align 8
-+; CHECK:    store {{.*}} 16, {{.*}} @__msan_va_arg_overflow_size_tls
-+;
-+  %1 = call i32 (i32, i32, ...) @foo2(i32 0, i32 1, i64 2, double 3.000000e+00)
-+  ret i32 %1
-+}
-+
-+;; Test that MSan doesn't generate code overflowing __msan_va_arg_tls when too many arguments are
-+;; passed to a variadic function.
-+declare i64 @sum(i64 %n, ...)
-+define dso_local i64 @many_args() {
-+;; If the size of __msan_va_arg_tls changes the second argument of `add` must also be changed.
-+; CHECK-LABEL: @many_args
-+; CHECK:    i64 add (i64 ptrtoint (ptr @__msan_va_arg_tls to i64), i64 792)
-+; CHECK-NOT: i64 add (i64 ptrtoint (ptr @__msan_va_arg_tls to i64), i64 800)
-+;
-+entry:
-+  %ret = call i64 (i64, ...) @sum(i64 120,
-+  i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1,
-+  i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1,
-+  i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1,
-+  i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1,
-+  i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1,
-+  i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1,
-+  i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1,
-+  i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1,
-+  i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1,
-+  i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1,
-+  i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1,
-+  i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1
-+  )
-+  ret i64 %ret
-+}
--- 
-2.20.1
-
-
-From f1265a12fa947b79967552ab520f904486c76353 Mon Sep 17 00:00:00 2001
-From: Ami-zhang <96056515+Ami-zhang@users.noreply.github.com>
-Date: Thu, 28 Sep 2023 15:26:18 +0800
-Subject: PATCH 02/14 LowerTypeTests Add loongarch64 to CFI jumptables
- (#67312)
-
-This patch implements jump tables for loongarch64.
-
-(cherry picked from commit 0e8a8c85f8765c086c573f36e60c895920381e18)
----
- llvm/lib/Transforms/IPO/LowerTypeTests.cpp           | 9 ++++++++-
- llvm/test/Transforms/LowerTypeTests/function-weak.ll | 2 ++
- llvm/test/Transforms/LowerTypeTests/function.ll      | 9 +++++++++
- 3 files changed, 19 insertions(+), 1 deletion(-)
-
-diff --git a/llvm/lib/Transforms/IPO/LowerTypeTests.cpp b/llvm/lib/Transforms/IPO/LowerTypeTests.cpp
-index 9b4b3efd7283..a89d57d12615 100644
---- a/llvm/lib/Transforms/IPO/LowerTypeTests.cpp
-+++ b/llvm/lib/Transforms/IPO/LowerTypeTests.cpp
-@@ -1196,6 +1196,7 @@ static const unsigned kARMJumpTableEntrySize = 4;
- static const unsigned kARMBTIJumpTableEntrySize = 8;
- static const unsigned kARMv6MJumpTableEntrySize = 16;
- static const unsigned kRISCVJumpTableEntrySize = 8;
-+static const unsigned kLOONGARCH64JumpTableEntrySize = 8;
- 
- unsigned LowerTypeTestsModule::getJumpTableEntrySize() {
-   switch (JumpTableArch) {
-@@ -1222,6 +1223,8 @@ unsigned LowerTypeTestsModule::getJumpTableEntrySize() {
-   case Triple::riscv32:
-   case Triple::riscv64:
-     return kRISCVJumpTableEntrySize;
-+  case Triple::loongarch64:
-+    return kLOONGARCH64JumpTableEntrySize;
-   default:
-     report_fatal_error("Unsupported architecture for jump tables");
-   }
-@@ -1286,6 +1289,9 @@ void LowerTypeTestsModule::createJumpTableEntry(
-   } else if (JumpTableArch == Triple::riscv32 ||
-              JumpTableArch == Triple::riscv64) {
-     AsmOS << "tail $" << ArgIndex << "@plt\n";
-+  } else if (JumpTableArch == Triple::loongarch64) {
-+    AsmOS << "pcalau12i $$t0, %pc_hi20($" << ArgIndex << ")\n"
-+          << "jirl $$r0, $$t0, %pc_lo12($" << ArgIndex << ")\n";
-   } else {
-     report_fatal_error("Unsupported architecture for jump tables");
-   }
-@@ -1304,7 +1310,8 @@ void LowerTypeTestsModule::buildBitSetsFromFunctions(
-     ArrayRef<Metadata *> TypeIds, ArrayRef<GlobalTypeMember *> Functions) {
-   if (Arch == Triple::x86 || Arch == Triple::x86_64 || Arch == Triple::arm ||
-       Arch == Triple::thumb || Arch == Triple::aarch64 ||
--      Arch == Triple::riscv32 || Arch == Triple::riscv64)
-+      Arch == Triple::riscv32 || Arch == Triple::riscv64 ||
-+      Arch == Triple::loongarch64)
-     buildBitSetsFromFunctionsNative(TypeIds, Functions);
-   else if (Arch == Triple::wasm32 || Arch == Triple::wasm64)
-     buildBitSetsFromFunctionsWASM(TypeIds, Functions);
-diff --git a/llvm/test/Transforms/LowerTypeTests/function-weak.ll b/llvm/test/Transforms/LowerTypeTests/function-weak.ll
-index ff69abacc8e9..c765937f1991 100644
---- a/llvm/test/Transforms/LowerTypeTests/function-weak.ll
-+++ b/llvm/test/Transforms/LowerTypeTests/function-weak.ll

_service:tar_scm:0013-Backport-Bitcode-Add-some-missing-GetTypeByID-failure-checks.patch Deleted

@@ -1,37 +0,0 @@
-From 58f4b115f97435efa1df1baa3247791a13444c00 Mon Sep 17 00:00:00 2001
-From: Nikita Popov <npopov@redhat.com>
-Date: Tue, 26 Sep 2023 16:51:40 +0200
-Subject: PATCH 1/3 Bitcode Add some missing GetTypeByID failure checks
-
-Print an error instead of crashing.
-
-Fixes https://github.com/llvm/llvm-project/issues/67388.
----
- llvm/lib/Bitcode/Reader/MetadataLoader.cpp | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/llvm/lib/Bitcode/Reader/MetadataLoader.cpp b/llvm/lib/Bitcode/Reader/MetadataLoader.cpp
-index 0a9a80688a41..2f024899b451 100644
---- a/llvm/lib/Bitcode/Reader/MetadataLoader.cpp
-+++ b/llvm/lib/Bitcode/Reader/MetadataLoader.cpp
-@@ -1315,7 +1315,7 @@ Error MetadataLoader::MetadataLoaderImpl::parseOneMetadata(
- 
-     unsigned TyID = Record0;
-     Type *Ty = Callbacks.GetTypeByID(TyID);
--    if (Ty->isMetadataTy() || Ty->isVoidTy()) {
-+    if (!Ty || Ty->isMetadataTy() || Ty->isVoidTy()) {
-       dropRecord();
-       break;
-     }
-@@ -1366,7 +1366,7 @@ Error MetadataLoader::MetadataLoaderImpl::parseOneMetadata(
- 
-     unsigned TyID = Record0;
-     Type *Ty = Callbacks.GetTypeByID(TyID);
--    if (Ty->isMetadataTy() || Ty->isVoidTy())
-+    if (!Ty || Ty->isMetadataTy() || Ty->isVoidTy())
-       return error("Invalid record");
- 
-     Value *V = ValueList.getValueFwdRef(Record1, Ty, TyID,
--- 
-2.33.0
-

_service:tar_scm:0014-Backport-X86-Inline-Skip-inline-asm-in-inlining-targ.patch Deleted

@@ -1,74 +0,0 @@
-From 678cf3a36644847cac4b0be2d919aba77416088a Mon Sep 17 00:00:00 2001
-From: Nikita Popov <npopov@redhat.com>
-Date: Mon, 04 Mar 2024 07:00:37 +0800
-Subject: PATCH BackportX86Inline Skip inline asm in inlining target
- feature check
-
-When inlining across functions with different target features, we
-perform roughly two checks:
-1. The caller features must be a superset of the callee features.
-2. Calls in the callee cannot use types where the target features would
-change the call ABI (e.g. by changing whether something is passed in a
-zmm or two ymm registers). The latter check is very crude right now.
-
-The latter check currently also catches inline asm "calls". I believe
-that inline asm should be excluded from this check, as it is independent
-from the usual call ABI, and instead governed by the inline asm
-constraint string.
----
- .../lib/Target/X86/X86TargetTransformInfo.cpp |  4 +++
- .../Inline/X86/call-abi-compatibility.ll      | 26 +++++++++++++++++++
- 2 files changed, 30 insertions(+)
-
-diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
-index 129a2646d..9c7954230 100644
---- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
-+++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
-@@ -6046,6 +6046,10 @@ bool X86TTIImpl::areInlineCompatible(const Function *Caller,
- 
-   for (const Instruction &I : instructions(Callee)) {
-     if (const auto *CB = dyn_cast<CallBase>(&I)) {
-+      // Having more target features is fine for inline ASM.
-+      if (CB->isInlineAsm())
-+        continue;
-+
-       SmallVector<Type *, 8> Types;
-       for (Value *Arg : CB->args())
-         Types.push_back(Arg->getType());
-diff --git a/llvm/test/Transforms/Inline/X86/call-abi-compatibility.ll b/llvm/test/Transforms/Inline/X86/call-abi-compatibility.ll
-index 3a30980fe..6f582cab2 100644
---- a/llvm/test/Transforms/Inline/X86/call-abi-compatibility.ll
-+++ b/llvm/test/Transforms/Inline/X86/call-abi-compatibility.ll
-@@ -93,3 +93,29 @@ define internal void @caller_not_avx4() {
- }
- 
- declare i64 @caller_unknown_simple(i64)
-+
-+; This call should get inlined, because the callee only contains
-+; inline ASM, not real calls.
-+define <8 x i64> @caller_inline_asm(ptr %p0, i64 %k, ptr %p1, ptr %p2) #0 {
-+; CHECK-LABEL: define {{^@+}}@caller_inline_asm
-+; CHECK-SAME: (ptr P0:%.*, i64 K:%.*, ptr P1:%.*, ptr P2:%.*) #ATTR2:0-9+ {
-+; CHECK-NEXT:    SRC_I:%.* = load <8 x i64>, ptr P0, align 64
-+; CHECK-NEXT:    A_I:%.* = load <8 x i64>, ptr P1, align 64
-+; CHECK-NEXT:    B_I:%.* = load <8 x i64>, ptr P2, align 64
-+; CHECK-NEXT:    TMP1:%.* = call <8 x i64> asm "vpaddb\09$($3, $2, $0 {$1}", "=v,^Yk,v,v,0,~{dirflag},~{fpsr},~{flags}"(i64 K, <8 x i64> A_I, <8 x i64> B_I, <8 x i64> SRC_I)
-+; CHECK-NEXT:    ret <8 x i64> TMP1
-+;
-+  %call = call <8 x i64> @callee_inline_asm(ptr %p0, i64 %k, ptr %p1, ptr %p2)
-+  ret <8 x i64> %call
-+}
-+
-+define internal <8 x i64> @callee_inline_asm(ptr %p0, i64 %k, ptr %p1, ptr %p2) #1 {
-+  %src = load <8 x i64>, ptr %p0, align 64
-+  %a = load <8 x i64>, ptr %p1, align 64
-+  %b = load <8 x i64>, ptr %p2, align 64
-+  %1 = tail call <8 x i64> asm "vpaddb\09$($3, $2, $0 {$1}", "=v,^Yk,v,v,0,~{dirflag},~{fpsr},~{flags}"(i64 %k, <8 x i64> %a, <8 x i64> %b, <8 x i64> %src) #2
-+  ret <8 x i64> %1
-+}
-+
-+attributes #0 = { "min-legal-vector-width"="512" "target-features"="+avx,+avx2,+avx512bw,+avx512dq,+avx512f,+cmov,+crc32,+cx8,+evex512,+f16c,+fma,+fxsr,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave" "tune-cpu"="generic" }
-+attributes #1 = { "min-legal-vector-width"="512" "target-features"="+avx,+avx2,+avx512bw,+avx512f,+cmov,+crc32,+cx8,+evex512,+f16c,+fma,+fxsr,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave" "tune-cpu"="generic" }
--- 
-2.33.0
-

_service:tar_scm:0015-Backport-ARM-Check-all-terms-in-emitPopInst-when-clearing-Res.patch Deleted

@@ -1,87 +0,0 @@
-From 4aec2da60ce3f639e31d81406c09d5c88b3b8f53 Mon Sep 17 00:00:00 2001
-From: Florian Hahn <flo@fhahn.com>
-Date: Wed, 20 Dec 2023 16:56:15 +0100
-Subject: PATCH 2/3 ARM Check all terms in emitPopInst when clearing
- Restored for LR. (#75527)
-
-emitPopInst checks a single function exit MBB. If other paths also exit
-the function and any of there terminators uses LR implicitly, it is not
-save to clear the Restored bit.
-
-Check all terminators for the function before clearing Restored.
-
-This fixes a mis-compile in outlined-fn-may-clobber-lr-in-caller.ll
-where the machine-outliner previously introduced BLs that clobbered LR
-which in turn is used by the tail call return.
-
-Alternative to #73553
----
- llvm/lib/Target/ARM/ARMFrameLowering.cpp | 30 +++++++++++++++++++++---
- llvm/lib/Target/ARM/ARMFrameLowering.h   |  3 +++
- 2 files changed, 30 insertions(+), 3 deletions(-)
-
-diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
-index 4496d4928ebe..650f4650eef0 100644
---- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp
-+++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
-@@ -1645,9 +1645,6 @@ void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB,
-         // Fold the return instruction into the LDM.
-         DeleteRet = true;
-         LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_RET : ARM::LDMIA_RET;
--        // We 'restore' LR into PC so it is not live out of the return block:
--        // Clear Restored bit.
--        Info.setRestored(false);
-       }
- 
-       // If NoGap is true, pop consecutive registers and then leave the rest
-@@ -2769,6 +2766,33 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF,
-   AFI->setLRIsSpilled(SavedRegs.test(ARM::LR));
- }
- 
-+void ARMFrameLowering::processFunctionBeforeFrameFinalized(
-+    MachineFunction &MF, RegScavenger *RS) const {
-+  TargetFrameLowering::processFunctionBeforeFrameFinalized(MF, RS);
-+
-+  MachineFrameInfo &MFI = MF.getFrameInfo();
-+  if (!MFI.isCalleeSavedInfoValid())
-+    return;
-+
-+  // Check if all terminators do not implicitly use LR. Then we can 'restore' LR
-+  // into PC so it is not live out of the return block: Clear the Restored bit
-+  // in that case.
-+  for (CalleeSavedInfo &Info : MFI.getCalleeSavedInfo()) {
-+    if (Info.getReg() != ARM::LR)
-+      continue;
-+    if (all_of(MF, (const MachineBasicBlock &MBB) {
-+          return all_of(MBB.terminators(), (const MachineInstr &Term) {
-+            return !Term.isReturn() || Term.getOpcode() == ARM::LDMIA_RET ||
-+                   Term.getOpcode() == ARM::t2LDMIA_RET ||
-+                   Term.getOpcode() == ARM::tPOP_RET;
-+          });
-+        })) {
-+      Info.setRestored(false);
-+      break;
-+    }
-+  }
-+}
-+
- void ARMFrameLowering::getCalleeSaves(const MachineFunction &MF,
-                                       BitVector &SavedRegs) const {
-   TargetFrameLowering::getCalleeSaves(MF, SavedRegs);
-diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.h b/llvm/lib/Target/ARM/ARMFrameLowering.h
-index 16f2ce6bea6f..8d2b8beb9a58 100644
---- a/llvm/lib/Target/ARM/ARMFrameLowering.h
-+++ b/llvm/lib/Target/ARM/ARMFrameLowering.h
-@@ -59,6 +59,9 @@ public:
-   void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
-                             RegScavenger *RS) const override;
- 
-+  void processFunctionBeforeFrameFinalized(
-+      MachineFunction &MF, RegScavenger *RS = nullptr) const override;
-+
-   void adjustForSegmentedStacks(MachineFunction &MF,
-                                 MachineBasicBlock &MBB) const override;
- 
--- 
-2.33.0
-

_service:tar_scm:0016-Backport-ARM-Update-IsRestored-for-LR-based-on-all-returns-82.patch Deleted

@@ -1,116 +0,0 @@
-From 369bfc8ea8c0a9da51b4bd964f0045cb389c3c2f Mon Sep 17 00:00:00 2001
-From: ostannard <oliver.stannard@arm.com>
-Date: Mon, 26 Feb 2024 12:23:25 +0000
-Subject: PATCH 3/3 ARM Update IsRestored for LR based on all returns
- (#82745)
-
-PR #75527 fixed ARMFrameLowering to set the IsRestored flag for LR based
-on all of the return instructions in the function, not just one.
-However, there is also code in ARMLoadStoreOptimizer which changes
-return instructions, but it set IsRestored based on the one instruction
-it changed, not the whole function.
-
-The fix is to factor out the code added in #75527, and also call it from
-ARMLoadStoreOptimizer if it made a change to return instructions.
-
-Fixes #80287.
----
- llvm/lib/Target/ARM/ARMFrameLowering.cpp      | 11 +++++----
- llvm/lib/Target/ARM/ARMFrameLowering.h        |  4 ++++
- llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 23 ++++++++-----------
- 3 files changed, 21 insertions(+), 17 deletions(-)
-
-diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
-index 650f4650eef0..008ba4e5924b 100644
---- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp
-+++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
-@@ -2766,10 +2766,7 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF,
-   AFI->setLRIsSpilled(SavedRegs.test(ARM::LR));
- }
- 
--void ARMFrameLowering::processFunctionBeforeFrameFinalized(
--    MachineFunction &MF, RegScavenger *RS) const {
--  TargetFrameLowering::processFunctionBeforeFrameFinalized(MF, RS);
--
-+void ARMFrameLowering::updateLRRestored(MachineFunction &MF) {
-   MachineFrameInfo &MFI = MF.getFrameInfo();
-   if (!MFI.isCalleeSavedInfoValid())
-     return;
-@@ -2793,6 +2790,12 @@ void ARMFrameLowering::processFunctionBeforeFrameFinalized(
-   }
- }
- 
-+void ARMFrameLowering::processFunctionBeforeFrameFinalized(
-+    MachineFunction &MF, RegScavenger *RS) const {
-+  TargetFrameLowering::processFunctionBeforeFrameFinalized(MF, RS);
-+  updateLRRestored(MF);
-+}
-+
- void ARMFrameLowering::getCalleeSaves(const MachineFunction &MF,
-                                       BitVector &SavedRegs) const {
-   TargetFrameLowering::getCalleeSaves(MF, SavedRegs);
-diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.h b/llvm/lib/Target/ARM/ARMFrameLowering.h
-index 8d2b8beb9a58..3c7358d8cd53 100644
---- a/llvm/lib/Target/ARM/ARMFrameLowering.h
-+++ b/llvm/lib/Target/ARM/ARMFrameLowering.h
-@@ -59,6 +59,10 @@ public:
-   void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
-                             RegScavenger *RS) const override;
- 
-+  /// Update the IsRestored flag on LR if it is spilled, based on the return
-+  /// instructions.
-+  static void updateLRRestored(MachineFunction &MF);
-+
-   void processFunctionBeforeFrameFinalized(
-       MachineFunction &MF, RegScavenger *RS = nullptr) const override;
- 
-diff --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
-index 93db983b92c0..37d9e1addd1e 100644
---- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
-+++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
-@@ -2062,17 +2062,6 @@ bool ARMLoadStoreOpt::MergeReturnIntoLDM(MachineBasicBlock &MBB) {
-       MO.setReg(ARM::PC);
-       PrevMI.copyImplicitOps(*MBB.getParent(), *MBBI);
-       MBB.erase(MBBI);
--      // We now restore LR into PC so it is not live-out of the return block
--      // anymore: Clear the CSI Restored bit.
--      MachineFrameInfo &MFI = MBB.getParent()->getFrameInfo();
--      // CSI should be fixed after PrologEpilog Insertion
--      assert(MFI.isCalleeSavedInfoValid() && "CSI should be valid");
--      for (CalleeSavedInfo &Info : MFI.getCalleeSavedInfo()) {
--        if (Info.getReg() == ARM::LR) {
--          Info.setRestored(false);
--          break;
--        }
--      }
-       return true;
-     }
-   }
-@@ -2120,14 +2109,22 @@ bool ARMLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
-   isThumb2 = AFI->isThumb2Function();
-   isThumb1 = AFI->isThumbFunction() && !isThumb2;
- 
--  bool Modified = false;
-+  bool Modified = false, ModifiedLDMReturn = false;
-   for (MachineBasicBlock &MBB : Fn) {
-     Modified |= LoadStoreMultipleOpti(MBB);
-     if (STI->hasV5TOps() && !AFI->shouldSignReturnAddress())
--      Modified |= MergeReturnIntoLDM(MBB);
-+      ModifiedLDMReturn |= MergeReturnIntoLDM(MBB);
-     if (isThumb1)
-       Modified |= CombineMovBx(MBB);
-   }
-+  Modified |= ModifiedLDMReturn;
-+
-+  // If we merged a BX instruction into an LDM, we need to re-calculate whether
-+  // LR is restored. This check needs to consider the whole function, not just
-+  // the instruction(s) we changed, because there may be other BX returns which
-+  // still need LR to be restored.
-+  if (ModifiedLDMReturn)
-+    ARMFrameLowering::updateLRRestored(Fn);
- 
-   Allocator.DestroyAll();
-   return Modified;
--- 
-2.33.0
-

_service:tar_scm:0017-Add-the-support-for-classic-flang.patch Deleted

@@ -1,1776 +0,0 @@
-From b297f30783da0dfb3098fe6d39b209caacd45691 Mon Sep 17 00:00:00 2001
-From: luofeng14 <luofeng13@huawei.com>
-Date: Fri, 1 Mar 2024 18:39:52 +0800
-Subject: PATCH sync classic flang patch
-
----
- llvm/cmake/modules/HandleLLVMOptions.cmake    |   8 +
- llvm/include/llvm-c/DebugInfo.h               |   5 +-
- .../include/llvm/Analysis/TargetLibraryInfo.h |   6 +-
- llvm/include/llvm/Analysis/VecFuncs.def       | 592 ++++++++++++++++++
- llvm/include/llvm/IR/DIBuilder.h              |  28 +-
- llvm/include/llvm/IR/DebugInfoMetadata.h      |  32 +-
- llvm/lib/Analysis/TargetLibraryInfo.cpp       |  38 +-
- llvm/lib/AsmParser/LLParser.cpp               |  22 +-
- llvm/lib/Bitcode/Reader/MetadataLoader.cpp    |  42 +-
- llvm/lib/Bitcode/Writer/BitcodeWriter.cpp     |   3 +-
- llvm/lib/CodeGen/AsmPrinter/DebugLocEntry.h   |  54 ++
- .../lib/CodeGen/AsmPrinter/DebugLocStream.cpp |   5 +
- llvm/lib/CodeGen/AsmPrinter/DebugLocStream.h  |   6 +
- .../CodeGen/AsmPrinter/DwarfCompileUnit.cpp   |   3 +
- llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h      |   4 +
- llvm/lib/IR/AsmWriter.cpp                     |   1 +
- llvm/lib/IR/DIBuilder.cpp                     |  12 +-
- llvm/lib/IR/DebugInfo.cpp                     |  10 +-
- llvm/lib/IR/DebugInfoMetadata.cpp             |  12 +-
- llvm/lib/IR/LLVMContextImpl.h                 |  11 +-
- .../Instrumentation/InstrProfiling.cpp        |   4 +-
- .../invalid-diglobalvariable-empty-name.ll    |   1 +
- .../Generic/fortran-subprogram-at.ll          |  24 +
- .../DebugInfo/Generic/more-subprogram-attr.ll |  38 ++
- llvm/test/DebugInfo/X86/DICommonBlock.ll      |  36 ++
- llvm/test/lit.cfg.py                          |   3 +
- llvm/test/lit.site.cfg.py.in                  |   1 +
- llvm/tools/llvm-c-test/debuginfo.c            |   4 +-
- llvm/unittests/IR/MetadataTest.cpp            |  47 +-
- llvm/utils/lit/lit/TestingConfig.py           |   1 +
- llvm/utils/lit/lit/llvm/config.py             |  10 +
- 31 files changed, 983 insertions(+), 80 deletions(-)
- create mode 100644 llvm/test/DebugInfo/Generic/fortran-subprogram-at.ll
- create mode 100644 llvm/test/DebugInfo/Generic/more-subprogram-attr.ll
- create mode 100644 llvm/test/DebugInfo/X86/DICommonBlock.ll
-
-diff --git a/llvm/cmake/modules/HandleLLVMOptions.cmake b/llvm/cmake/modules/HandleLLVMOptions.cmake
-index 76723be696e5..492ea25b179b 100644
---- a/llvm/cmake/modules/HandleLLVMOptions.cmake
-+++ b/llvm/cmake/modules/HandleLLVMOptions.cmake
-@@ -89,6 +89,14 @@ if( LLVM_ENABLE_ASSERTIONS )
-   add_compile_definitions(_LIBCPP_ENABLE_HARDENED_MODE)
- endif()
- 
-+option(LLVM_ENABLE_CLASSIC_FLANG "Build support for classic Flang instead of the new built-in Flang" OFF)
-+if(LLVM_ENABLE_CLASSIC_FLANG)
-+  set(LLVM_ENABLE_CLASSIC_FLANG 1)
-+  add_definitions( -DENABLE_CLASSIC_FLANG )
-+else()
-+  set(LLVM_ENABLE_CLASSIC_FLANG 0)
-+endif()
-+
- if(LLVM_ENABLE_EXPENSIVE_CHECKS)
-   add_compile_definitions(EXPENSIVE_CHECKS)
- 
-diff --git a/llvm/include/llvm-c/DebugInfo.h b/llvm/include/llvm-c/DebugInfo.h
-index 5924294708cc..09d584c24711 100644
---- a/llvm/include/llvm-c/DebugInfo.h
-+++ b/llvm/include/llvm-c/DebugInfo.h
-@@ -1148,7 +1148,8 @@ LLVMMetadataRef LLVMDIBuilderCreateGlobalVariableExpression(
-     LLVMDIBuilderRef Builder, LLVMMetadataRef Scope, const char *Name,
-     size_t NameLen, const char *Linkage, size_t LinkLen, LLVMMetadataRef File,
-     unsigned LineNo, LLVMMetadataRef Ty, LLVMBool LocalToUnit,
--    LLVMMetadataRef Expr, LLVMMetadataRef Decl, uint32_t AlignInBits);
-+    LLVMMetadataRef Expr, LLVMMetadataRef Decl, LLVMDIFlags Flags,
-+    uint32_t AlignInBits);
- 
- 
- /**
-@@ -1246,7 +1247,7 @@ LLVMMetadataRef LLVMDIBuilderCreateTempGlobalVariableFwdDecl(
-     LLVMDIBuilderRef Builder, LLVMMetadataRef Scope, const char *Name,
-     size_t NameLen, const char *Linkage, size_t LnkLen, LLVMMetadataRef File,
-     unsigned LineNo, LLVMMetadataRef Ty, LLVMBool LocalToUnit,
--    LLVMMetadataRef Decl, uint32_t AlignInBits);
-+    LLVMMetadataRef Decl, LLVMDIFlags Flags, uint32_t AlignInBits);
- 
- /**
-  * Insert a new llvm.dbg.declare intrinsic call before the given instruction.
-diff --git a/llvm/include/llvm/Analysis/TargetLibraryInfo.h b/llvm/include/llvm/Analysis/TargetLibraryInfo.h
-index 5d62e837c1f3..490252cd018a 100644
---- a/llvm/include/llvm/Analysis/TargetLibraryInfo.h
-+++ b/llvm/include/llvm/Analysis/TargetLibraryInfo.h
-@@ -22,7 +22,6 @@ namespace llvm {
- template <typename T> class ArrayRef;
- class Function;
- class Module;
--class Triple;
- 
- /// Describes a possible vectorization of a function.
- /// Function 'VectorFnName' is equivalent to 'ScalarFnName' vectorized
-@@ -81,6 +80,8 @@ class TargetLibraryInfoImpl {
-   bool isValidProtoForLibFunc(const FunctionType &FTy, LibFunc F,
-                               const Module &M) const;
- 
-+  Triple T;
-+
- public:
-   /// List of known vector-functions libraries.
-   ///
-@@ -95,6 +96,9 @@ public:
-     DarwinLibSystemM, // Use Darwin's libsystem_m.
-     LIBMVEC_X86,      // GLIBC Vector Math library.
-     MASSV,            // IBM MASS vector library.
-+#ifdef ENABLE_CLASSIC_FLANG
-+    PGMATH,           // PGI math library.
-+#endif
-     SVML,             // Intel short vector math library.
-     SLEEFGNUABI, // SLEEF - SIMD Library for Evaluating Elementary Functions.
-     ArmPL        // Arm Performance Libraries.
-diff --git a/llvm/include/llvm/Analysis/VecFuncs.def b/llvm/include/llvm/Analysis/VecFuncs.def
-index b884c1e3911e..d1712d158423 100644
---- a/llvm/include/llvm/Analysis/VecFuncs.def
-+++ b/llvm/include/llvm/Analysis/VecFuncs.def
-@@ -909,6 +909,596 @@ TLI_DEFINE_VECFUNC("tgammaf", "armpl_vtgammaq_f32", FIXED(4), NOMASK)
- TLI_DEFINE_VECFUNC("tgamma", "armpl_svtgamma_f64_x",  SCALABLE(2), MASKED)
- TLI_DEFINE_VECFUNC("tgammaf", "armpl_svtgamma_f32_x", SCALABLE(4), MASKED)
- 
-+#elif defined(TLI_DEFINE_PGMATH_AARCH64_VECFUNCS)
-+// Classic flang libpgmath library's Vector Functions for AArch64
-+
-+TLI_DEFINE_VECFUNC("__fd_sin_1", "__fd_sin_2", FIXED(2))
-+TLI_DEFINE_VECFUNC("__fs_sin_1", "__fs_sin_4", FIXED(4))
-+
-+TLI_DEFINE_VECFUNC("__pd_sin_1", "__pd_sin_2", FIXED(2))
-+TLI_DEFINE_VECFUNC("__ps_sin_1", "__ps_sin_4", FIXED(4))
-+
-+TLI_DEFINE_VECFUNC("__rd_sin_1", "__rd_sin_2", FIXED(2))
-+TLI_DEFINE_VECFUNC("__rs_sin_1", "__rs_sin_4", FIXED(4))
-+
-+TLI_DEFINE_VECFUNC("__fd_cos_1", "__fd_cos_2", FIXED(2))
-+TLI_DEFINE_VECFUNC("__fs_cos_1", "__fs_cos_4", FIXED(4))
-+
-+TLI_DEFINE_VECFUNC("__pd_cos_1", "__pd_cos_2", FIXED(2))
-+TLI_DEFINE_VECFUNC("__ps_cos_1", "__ps_cos_4", FIXED(4))
-+
-+TLI_DEFINE_VECFUNC("__rd_cos_1", "__rd_cos_2", FIXED(2))
-+TLI_DEFINE_VECFUNC("__rs_cos_1", "__rs_cos_4", FIXED(4))
-+
-+TLI_DEFINE_VECFUNC("__fd_sincos_1", "__fd_sincos_2", FIXED(2))
-+TLI_DEFINE_VECFUNC("__fs_sincos_1", "__fs_sincos_4", FIXED(4))
-+
-+TLI_DEFINE_VECFUNC("__pd_sincos_1", "__pd_sincos_2", FIXED(2))
-+TLI_DEFINE_VECFUNC("__ps_sincos_1", "__ps_sincos_4", FIXED(4))
-+
-+TLI_DEFINE_VECFUNC("__rd_sincos_1", "__rd_sincos_2", FIXED(2))
-+TLI_DEFINE_VECFUNC("__rs_sincos_1", "__rs_sincos_4", FIXED(4))
-+
-+TLI_DEFINE_VECFUNC("__fd_tan_1", "__fd_tan_2", FIXED(2))
-+TLI_DEFINE_VECFUNC("__fs_tan_1", "__fs_tan_4", FIXED(4))
-+
-+TLI_DEFINE_VECFUNC("__pd_tan_1", "__pd_tan_2", FIXED(2))
-+TLI_DEFINE_VECFUNC("__ps_tan_1", "__ps_tan_4", FIXED(4))
-+
-+TLI_DEFINE_VECFUNC("__rd_tan_1", "__rd_tan_2", FIXED(2))
-+TLI_DEFINE_VECFUNC("__rs_tan_1", "__rs_tan_4", FIXED(4))
-+
-+TLI_DEFINE_VECFUNC("__fd_sinh_1", "__fd_sinh_2", FIXED(2))
-+TLI_DEFINE_VECFUNC("__fs_sinh_1", "__fs_sinh_4", FIXED(4))
-+
-+TLI_DEFINE_VECFUNC("__pd_sinh_1", "__pd_sinh_2", FIXED(2))
-+TLI_DEFINE_VECFUNC("__ps_sinh_1", "__ps_sinh_4", FIXED(4))
-+
-+TLI_DEFINE_VECFUNC("__rd_sinh_1", "__rd_sinh_2", FIXED(2))
-+TLI_DEFINE_VECFUNC("__rs_sinh_1", "__rs_sinh_4", FIXED(4))
-+
-+TLI_DEFINE_VECFUNC("__fd_cosh_1", "__fd_cosh_2", FIXED(2))
-+TLI_DEFINE_VECFUNC("__fs_cosh_1", "__fs_cosh_4", FIXED(4))
-+
-+TLI_DEFINE_VECFUNC("__pd_cosh_1", "__pd_cosh_2", FIXED(2))
-+TLI_DEFINE_VECFUNC("__ps_cosh_1", "__ps_cosh_4", FIXED(4))
-+
-+TLI_DEFINE_VECFUNC("__rd_cosh_1", "__rd_cosh_2", FIXED(2))
-+TLI_DEFINE_VECFUNC("__rs_cosh_1", "__rs_cosh_4", FIXED(4))
-+
-+TLI_DEFINE_VECFUNC("__fd_tanh_1", "__fd_tanh_2", FIXED(2))
-+TLI_DEFINE_VECFUNC("__fs_tanh_1", "__fs_tanh_4", FIXED(4))
-+
-+TLI_DEFINE_VECFUNC("__pd_tanh_1", "__pd_tanh_2", FIXED(2))
-+TLI_DEFINE_VECFUNC("__ps_tanh_1", "__ps_tanh_4", FIXED(4))
-+
-+TLI_DEFINE_VECFUNC("__rd_tanh_1", "__rd_tanh_2", FIXED(2))
-+TLI_DEFINE_VECFUNC("__rs_tanh_1", "__rs_tanh_4", FIXED(4))
-+
-+TLI_DEFINE_VECFUNC("__fd_asin_1", "__fd_asin_2", FIXED(2))
-+TLI_DEFINE_VECFUNC("__fs_asin_1", "__fs_asin_4", FIXED(4))
-+
-+TLI_DEFINE_VECFUNC("__pd_asin_1", "__pd_asin_2", FIXED(2))
-+TLI_DEFINE_VECFUNC("__ps_asin_1", "__ps_asin_4", FIXED(4))
-+
-+TLI_DEFINE_VECFUNC("__rd_asin_1", "__rd_asin_2", FIXED(2))
-+TLI_DEFINE_VECFUNC("__rs_asin_1", "__rs_asin_4", FIXED(4))
-+
-+TLI_DEFINE_VECFUNC("__fd_acos_1", "__fd_acos_2", FIXED(2))

_service:tar_scm:0018-Fix-declaration-definition-mismatch-for-classic-flang.patch Deleted

@@ -1,1041 +0,0 @@
-From d6d17d8f0362ac47100be32f0d9cb31fd66a1060 Mon Sep 17 00:00:00 2001
-From: luofeng14 <luofeng13@huawei.com>
-Date: Wed, 17 Apr 2024 14:26:07 +0800
-Subject: PATCH Fix declaration definition mismatch for classic flang
-
----
- llvm/cmake/modules/TableGen.cmake             |  4 +
- llvm/include/llvm-c/DebugInfo.h               | 11 ++-
- .../include/llvm/Analysis/TargetLibraryInfo.h |  5 +
- llvm/include/llvm/Analysis/VecFuncs.def       |  8 ++
- llvm/include/llvm/IR/DebugInfoMetadata.h      | 65 ++++++++++---
- llvm/lib/Analysis/TargetLibraryInfo.cpp       | 24 +++++
- llvm/lib/AsmParser/LLParser.cpp               |  6 +-
- llvm/lib/Bitcode/Reader/MetadataLoader.cpp    | 44 ++++++---
- llvm/lib/Bitcode/Writer/BitcodeWriter.cpp     |  6 ++
- llvm/lib/CodeGen/AsmPrinter/DebugLocEntry.h   |  4 +
- .../CodeGen/AsmPrinter/DwarfCompileUnit.cpp   |  4 +-
- llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h      |  8 +-
- llvm/lib/IR/AsmWriter.cpp                     |  2 +
- llvm/lib/IR/DIBuilder.cpp                     | 21 +++-
- llvm/lib/IR/DebugInfo.cpp                     | 22 ++++-
- llvm/lib/IR/DebugInfoMetadata.cpp             | 19 +++-
- llvm/lib/IR/LLVMContextImpl.h                 | 22 ++++-
- .../Instrumentation/InstrProfiling.cpp        |  5 +-
- llvm/tools/llvm-c-test/debuginfo.c            | 12 ++-
- llvm/unittests/IR/MetadataTest.cpp            | 97 +++++++++++++++----
- llvm/utils/lit/lit/llvm/config.py             | 17 ++--
- 21 files changed, 321 insertions(+), 85 deletions(-)
-
-diff --git a/llvm/cmake/modules/TableGen.cmake b/llvm/cmake/modules/TableGen.cmake
-index 7fd6628ef55d..d4d2c06c051b 100644
---- a/llvm/cmake/modules/TableGen.cmake
-+++ b/llvm/cmake/modules/TableGen.cmake
-@@ -76,6 +76,10 @@ function(tablegen project ofn)
-     set(tblgen_change_flag "--write-if-changed")
-   endif()
- 
-+  if (LLVM_ENABLE_CLASSIC_FLANG)
-+    list(APPEND tblgen_change_flag "-DENABLE_CLASSIC_FLANG")
-+  endif()
-+
-   if (NOT LLVM_ENABLE_WARNINGS)
-     list(APPEND LLVM_TABLEGEN_FLAGS "-no-warn-on-unused-template-args")
-   endif()
-diff --git a/llvm/include/llvm-c/DebugInfo.h b/llvm/include/llvm-c/DebugInfo.h
-index 09d584c24711..0201bac4349d 100644
---- a/llvm/include/llvm-c/DebugInfo.h
-+++ b/llvm/include/llvm-c/DebugInfo.h
-@@ -1148,7 +1148,10 @@ LLVMMetadataRef LLVMDIBuilderCreateGlobalVariableExpression(
-     LLVMDIBuilderRef Builder, LLVMMetadataRef Scope, const char *Name,
-     size_t NameLen, const char *Linkage, size_t LinkLen, LLVMMetadataRef File,
-     unsigned LineNo, LLVMMetadataRef Ty, LLVMBool LocalToUnit,
--    LLVMMetadataRef Expr, LLVMMetadataRef Decl, LLVMDIFlags Flags,
-+    LLVMMetadataRef Expr, LLVMMetadataRef Decl,
-+#ifdef ENABLE_CLASSIC_FLANG
-+    LLVMDIFlags Flags,
-+#endif
-     uint32_t AlignInBits);
- 
- 
-@@ -1247,7 +1250,11 @@ LLVMMetadataRef LLVMDIBuilderCreateTempGlobalVariableFwdDecl(
-     LLVMDIBuilderRef Builder, LLVMMetadataRef Scope, const char *Name,
-     size_t NameLen, const char *Linkage, size_t LnkLen, LLVMMetadataRef File,
-     unsigned LineNo, LLVMMetadataRef Ty, LLVMBool LocalToUnit,
--    LLVMMetadataRef Decl, LLVMDIFlags Flags, uint32_t AlignInBits);
-+    LLVMMetadataRef Decl,
-+#ifdef ENABLE_CLASSIC_FLANG
-+    LLVMDIFlags Flags,
-+#endif
-+    uint32_t AlignInBits);
- 
- /**
-  * Insert a new llvm.dbg.declare intrinsic call before the given instruction.
-diff --git a/llvm/include/llvm/Analysis/TargetLibraryInfo.h b/llvm/include/llvm/Analysis/TargetLibraryInfo.h
-index 490252cd018a..6805c6535189 100644
---- a/llvm/include/llvm/Analysis/TargetLibraryInfo.h
-+++ b/llvm/include/llvm/Analysis/TargetLibraryInfo.h
-@@ -22,6 +22,9 @@ namespace llvm {
- template <typename T> class ArrayRef;
- class Function;
- class Module;
-+#ifndef ENABLE_CLASSIC_FLANG
-+class Triple;
-+#endif
- 
- /// Describes a possible vectorization of a function.
- /// Function 'VectorFnName' is equivalent to 'ScalarFnName' vectorized
-@@ -80,7 +83,9 @@ class TargetLibraryInfoImpl {
-   bool isValidProtoForLibFunc(const FunctionType &FTy, LibFunc F,
-                               const Module &M) const;
- 
-+#ifdef ENABLE_CLASSIC_FLANG
-   Triple T;
-+#endif
- 
- public:
-   /// List of known vector-functions libraries.
-diff --git a/llvm/include/llvm/Analysis/VecFuncs.def b/llvm/include/llvm/Analysis/VecFuncs.def
-index d1712d158423..679e28057d6e 100644
---- a/llvm/include/llvm/Analysis/VecFuncs.def
-+++ b/llvm/include/llvm/Analysis/VecFuncs.def
-@@ -910,6 +910,8 @@ TLI_DEFINE_VECFUNC("tgamma", "armpl_svtgamma_f64_x",  SCALABLE(2), MASKED)
- TLI_DEFINE_VECFUNC("tgammaf", "armpl_svtgamma_f32_x", SCALABLE(4), MASKED)
- 
- #elif defined(TLI_DEFINE_PGMATH_AARCH64_VECFUNCS)
-+
-+#ifdef ENABLE_CLASSIC_FLANG
- // Classic flang libpgmath library's Vector Functions for AArch64
- 
- TLI_DEFINE_VECFUNC("__fd_sin_1", "__fd_sin_2", FIXED(2))
-@@ -1079,8 +1081,11 @@ TLI_DEFINE_VECFUNC("__ps_exp_1", "__ps_exp_4", FIXED(4))
- 
- TLI_DEFINE_VECFUNC("__rd_exp_1", "__rd_exp_2", FIXED(2))
- TLI_DEFINE_VECFUNC("__rs_exp_1", "__rs_exp_4", FIXED(4))
-+#endif
- 
- #elif defined(TLI_DEFINE_PGMATH_X86_VECFUNCS)
-+
-+#ifdef ENABLE_CLASSIC_FLANG
- // Classic flang libpgmath library's Vector Functions for X86
- 
- TLI_DEFINE_VECFUNC("__fd_sin_1", "__fd_sin_2", FIXED(2))
-@@ -1498,6 +1503,7 @@ TLI_DEFINE_VECFUNC("__rd_exp_1", "__rd_exp_8", FIXED(8))
- TLI_DEFINE_VECFUNC("__rs_exp_1", "__rs_exp_4", FIXED(4))
- TLI_DEFINE_VECFUNC("__rs_exp_1", "__rs_exp_8", FIXED(8))
- TLI_DEFINE_VECFUNC("__rs_exp_1", "__rs_exp_16", FIXED(16))
-+#endif
- 
- #else
- #error "Must choose which vector library functions are to be defined."
-@@ -1519,5 +1525,7 @@ TLI_DEFINE_VECFUNC("__rs_exp_1", "__rs_exp_16", FIXED(16))
- #undef TLI_DEFINE_SLEEFGNUABI_SCALABLE_VECFUNCS
- #undef TLI_DEFINE_MASSV_VECFUNCS_NAMES
- #undef TLI_DEFINE_ARMPL_VECFUNCS
-+#ifdef ENABLE_CLASSIC_FLANG
- #undef TLI_DEFINE_PGMATH_AARCH64_VECFUNCS
- #undef TLI_DEFINE_PGMATH_X86_VECFUNCS
-+#endif
-diff --git a/llvm/include/llvm/IR/DebugInfoMetadata.h b/llvm/include/llvm/IR/DebugInfoMetadata.h
-index 9bd86172a4c0..277c2ddd4dd9 100644
---- a/llvm/include/llvm/IR/DebugInfoMetadata.h
-+++ b/llvm/include/llvm/IR/DebugInfoMetadata.h
-@@ -3062,14 +3062,23 @@ class DIGlobalVariable : public DIVariable {
- 
-   bool IsLocalToUnit;
-   bool IsDefinition;
-+#ifdef ENABLE_CLASSIC_FLANG
-   DIFlags Flags;
-+#endif
- 
-   DIGlobalVariable(LLVMContext &C, StorageType Storage, unsigned Line,
--                   bool IsLocalToUnit, bool IsDefinition, DIFlags Flags,
-+                   bool IsLocalToUnit, bool IsDefinition,
-+#ifdef ENABLE_CLASSIC_FLANG
-+                   DIFlags Flags,
-+#endif
-                    uint32_t AlignInBits, ArrayRef<Metadata *> Ops)
-       : DIVariable(C, DIGlobalVariableKind, Storage, Line, Ops, AlignInBits),
--        IsLocalToUnit(IsLocalToUnit), IsDefinition(IsDefinition),
--        Flags(Flags) {}
-+#ifdef ENABLE_CLASSIC_FLANG
-+        IsLocalToUnit(IsLocalToUnit), IsDefinition(IsDefinition), Flags(Flags) {}
-+#else
-+        IsLocalToUnit(IsLocalToUnit), IsDefinition(IsDefinition) {}
-+#endif
-+
-   ~DIGlobalVariable() = default;
- 
-   static DIGlobalVariable *
-@@ -3077,28 +3086,40 @@ class DIGlobalVariable : public DIVariable {
-           StringRef LinkageName, DIFile *File, unsigned Line, DIType *Type,
-           bool IsLocalToUnit, bool IsDefinition,
-           DIDerivedType *StaticDataMemberDeclaration, MDTuple *TemplateParams,
--          DIFlags Flags, uint32_t AlignInBits, DINodeArray Annotations,
-+#ifdef ENABLE_CLASSIC_FLANG
-+          DIFlags Flags,
-+#endif
-+          uint32_t AlignInBits, DINodeArray Annotations,
-           StorageType Storage, bool ShouldCreate = true) {
-     return getImpl(Context, Scope, getCanonicalMDString(Context, Name),
-                    getCanonicalMDString(Context, LinkageName), File, Line, Type,
-                    IsLocalToUnit, IsDefinition, StaticDataMemberDeclaration,
--                   cast_or_null<Metadata>(TemplateParams), Flags, AlignInBits,
--                   Annotations.get(), Storage, ShouldCreate);
-+                   cast_or_null<Metadata>(TemplateParams),
-+#ifdef ENABLE_CLASSIC_FLANG
-+                   Flags,
-+#endif
-+                   AlignInBits, Annotations.get(), Storage, ShouldCreate);
-   }
-   static DIGlobalVariable *
-   getImpl(LLVMContext &Context, Metadata *Scope, MDString *Name,
-           MDString *LinkageName, Metadata *File, unsigned Line, Metadata *Type,
-           bool IsLocalToUnit, bool IsDefinition,
-           Metadata *StaticDataMemberDeclaration, Metadata *TemplateParams,
--          DIFlags Flags, uint32_t AlignInBits, Metadata *Annotations,
-+#ifdef ENABLE_CLASSIC_FLANG
-+          DIFlags Flags,
-+#endif

_service:tar_scm:0019-Backport-LoongArch-Improve-the-support-for-atomic-and-clear_cache.patch Deleted

@@ -1,12426 +0,0 @@
-From ad367d826e5959792ce7384be62ba1ccffbf0d9a Mon Sep 17 00:00:00 2001
-From: hev <wangrui@loongson.cn>
-Date: Wed, 11 Oct 2023 10:24:18 +0800
-Subject: PATCH 1/7 LoongArch Improve codegen for atomic ops (#67391)
-
-This PR improves memory barriers generated by atomic operations.
-
-Memory barrier semantics of LL/SC:
-```
-LL: <memory-barrier> + <load-exclusive>
-SC: <store-conditional> + <memory-barrier>
-```
-
-Changes:
-* Remove unnecessary memory barriers before LL and between LL/SC.
-* Fix acquire semantics. (If the SC instruction is not executed, then
-the guarantee of acquiring semantics cannot be ensured. Therefore, an
-acquire barrier needs to be generated when memory ordering includes an
-acquire operation.)
-
-(cherry picked from commit 203ba238e33c570dba6cbcf247f1668bb2a13c26)
----
- .../LoongArchExpandAtomicPseudoInsts.cpp      |  50 +--
- .../Target/LoongArch/LoongArchInstrInfo.td    |  24 +-
- .../LoongArch/atomicrmw-uinc-udec-wrap.ll     |  24 +-
- .../ir-instruction/atomic-cmpxchg.ll          | 376 ++++++++++++++++--
- .../LoongArch/ir-instruction/atomicrmw-fp.ll  |  24 +-
- .../ir-instruction/atomicrmw-minmax.ll        |  24 --
- .../LoongArch/ir-instruction/atomicrmw.ll     |  31 --
- llvm/unittests/Target/LoongArch/InstSizes.cpp |   2 +-
- 8 files changed, 407 insertions(+), 148 deletions(-)
-
-diff --git a/llvm/lib/Target/LoongArch/LoongArchExpandAtomicPseudoInsts.cpp b/llvm/lib/Target/LoongArch/LoongArchExpandAtomicPseudoInsts.cpp
-index 51df0463e235..eb78ef065b21 100644
---- a/llvm/lib/Target/LoongArch/LoongArchExpandAtomicPseudoInsts.cpp
-+++ b/llvm/lib/Target/LoongArch/LoongArchExpandAtomicPseudoInsts.cpp
-@@ -153,18 +153,12 @@ static void doAtomicBinOpExpansion(const LoongArchInstrInfo *TII,
-   Register ScratchReg = MI.getOperand(1).getReg();
-   Register AddrReg = MI.getOperand(2).getReg();
-   Register IncrReg = MI.getOperand(3).getReg();
--  AtomicOrdering Ordering =
--      static_cast<AtomicOrdering>(MI.getOperand(4).getImm());
- 
-   // .loop:
--  //   if(Ordering != AtomicOrdering::Monotonic)
--  //     dbar 0
-   //   ll.w|d dest, (addr)
-   //   binop scratch, dest, val
-   //   sc.w|d scratch, scratch, (addr)
-   //   beqz scratch, loop
--  if (Ordering != AtomicOrdering::Monotonic)
--    BuildMI(LoopMBB, DL, TII->get(LoongArch::DBAR)).addImm(0);
-   BuildMI(LoopMBB, DL,
-           TII->get(Width == 32 ? LoongArch::LL_W : LoongArch::LL_D), DestReg)
-       .addReg(AddrReg)
-@@ -251,12 +245,8 @@ static void doMaskedAtomicBinOpExpansion(
-   Register AddrReg = MI.getOperand(2).getReg();
-   Register IncrReg = MI.getOperand(3).getReg();
-   Register MaskReg = MI.getOperand(4).getReg();
--  AtomicOrdering Ordering =
--      static_cast<AtomicOrdering>(MI.getOperand(5).getImm());
- 
-   // .loop:
--  //   if(Ordering != AtomicOrdering::Monotonic)
--  //     dbar 0
-   //   ll.w destreg, (alignedaddr)
-   //   binop scratch, destreg, incr
-   //   xor scratch, destreg, scratch
-@@ -264,8 +254,6 @@ static void doMaskedAtomicBinOpExpansion(
-   //   xor scratch, destreg, scratch
-   //   sc.w scratch, scratch, (alignedaddr)
-   //   beqz scratch, loop
--  if (Ordering != AtomicOrdering::Monotonic)
--    BuildMI(LoopMBB, DL, TII->get(LoongArch::DBAR)).addImm(0);
-   BuildMI(LoopMBB, DL, TII->get(LoongArch::LL_W), DestReg)
-       .addReg(AddrReg)
-       .addImm(0);
-@@ -372,23 +360,20 @@ bool LoongArchExpandAtomicPseudo::expandAtomicMinMaxOp(
-   auto LoopHeadMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
-   auto LoopIfBodyMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
-   auto LoopTailMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
--  auto TailMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
-   auto DoneMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
- 
-   // Insert new MBBs.
-   MF->insert(++MBB.getIterator(), LoopHeadMBB);
-   MF->insert(++LoopHeadMBB->getIterator(), LoopIfBodyMBB);
-   MF->insert(++LoopIfBodyMBB->getIterator(), LoopTailMBB);
--  MF->insert(++LoopTailMBB->getIterator(), TailMBB);
--  MF->insert(++TailMBB->getIterator(), DoneMBB);
-+  MF->insert(++LoopTailMBB->getIterator(), DoneMBB);
- 
-   // Set up successors and transfer remaining instructions to DoneMBB.
-   LoopHeadMBB->addSuccessor(LoopIfBodyMBB);
-   LoopHeadMBB->addSuccessor(LoopTailMBB);
-   LoopIfBodyMBB->addSuccessor(LoopTailMBB);
-   LoopTailMBB->addSuccessor(LoopHeadMBB);
--  LoopTailMBB->addSuccessor(TailMBB);
--  TailMBB->addSuccessor(DoneMBB);
-+  LoopTailMBB->addSuccessor(DoneMBB);
-   DoneMBB->splice(DoneMBB->end(), &MBB, MI, MBB.end());
-   DoneMBB->transferSuccessors(&MBB);
-   MBB.addSuccessor(LoopHeadMBB);
-@@ -402,11 +387,9 @@ bool LoongArchExpandAtomicPseudo::expandAtomicMinMaxOp(
- 
-   //
-   // .loophead:
--  //   dbar 0
-   //   ll.w destreg, (alignedaddr)
-   //   and scratch2, destreg, mask
-   //   move scratch1, destreg
--  BuildMI(LoopHeadMBB, DL, TII->get(LoongArch::DBAR)).addImm(0);
-   BuildMI(LoopHeadMBB, DL, TII->get(LoongArch::LL_W), DestReg)
-       .addReg(AddrReg)
-       .addImm(0);
-@@ -463,7 +446,6 @@ bool LoongArchExpandAtomicPseudo::expandAtomicMinMaxOp(
-   // .looptail:
-   //   sc.w scratch1, scratch1, (addr)
-   //   beqz scratch1, loop
--  //   dbar 0x700
-   BuildMI(LoopTailMBB, DL, TII->get(LoongArch::SC_W), Scratch1Reg)
-       .addReg(Scratch1Reg)
-       .addReg(AddrReg)
-@@ -472,10 +454,6 @@ bool LoongArchExpandAtomicPseudo::expandAtomicMinMaxOp(
-       .addReg(Scratch1Reg)
-       .addMBB(LoopHeadMBB);
- 
--  // .tail:
--  //   dbar 0x700
--  BuildMI(TailMBB, DL, TII->get(LoongArch::DBAR)).addImm(0x700);
--
-   NextMBBI = MBB.end();
-   MI.eraseFromParent();
- 
-@@ -483,7 +461,6 @@ bool LoongArchExpandAtomicPseudo::expandAtomicMinMaxOp(
-   computeAndAddLiveIns(LiveRegs, *LoopHeadMBB);
-   computeAndAddLiveIns(LiveRegs, *LoopIfBodyMBB);
-   computeAndAddLiveIns(LiveRegs, *LoopTailMBB);
--  computeAndAddLiveIns(LiveRegs, *TailMBB);
-   computeAndAddLiveIns(LiveRegs, *DoneMBB);
- 
-   return true;
-@@ -535,12 +512,10 @@ bool LoongArchExpandAtomicPseudo::expandAtomicCmpXchg(
-         .addReg(CmpValReg)
-         .addMBB(TailMBB);
-     // .looptail:
--    //   dbar 0
-     //   move scratch, newval
-     //   sc.w|d scratch, scratch, (addr)
-     //   beqz scratch, loophead
-     //   b done
--    BuildMI(LoopTailMBB, DL, TII->get(LoongArch::DBAR)).addImm(0);
-     BuildMI(LoopTailMBB, DL, TII->get(LoongArch::OR), ScratchReg)
-         .addReg(NewValReg)
-         .addReg(LoongArch::R0);
-@@ -573,13 +548,11 @@ bool LoongArchExpandAtomicPseudo::expandAtomicCmpXchg(
-         .addMBB(TailMBB);
- 
-     // .looptail:
--    //   dbar 0
-     //   andn scratch, dest, mask
-     //   or scratch, scratch, newval
-     //   sc.w|d scratch, scratch, (addr)
-     //   beqz scratch, loophead
-     //   b done
--    BuildMI(LoopTailMBB, DL, TII->get(LoongArch::DBAR)).addImm(0);
-     BuildMI(LoopTailMBB, DL, TII->get(LoongArch::ANDN), ScratchReg)
-         .addReg(DestReg)
-         .addReg(MaskReg);
-@@ -598,9 +571,24 @@ bool LoongArchExpandAtomicPseudo::expandAtomicCmpXchg(
-     BuildMI(LoopTailMBB, DL, TII->get(LoongArch::B)).addMBB(DoneMBB);
-   }
- 
-+  AtomicOrdering Ordering =
-+      static_cast<AtomicOrdering>(MI.getOperand(IsMasked ? 6 : 5).getImm());
-+  int hint;
-+
-+  switch (Ordering) {
-+  case AtomicOrdering::Acquire:
-+  case AtomicOrdering::AcquireRelease:
-+  case AtomicOrdering::SequentiallyConsistent:
-+    // TODO: acquire
-+    hint = 0;
-+    break;
-+  default:
-+    hint = 0x700;
-+  }
-+
-   // .tail:
--  //   dbar 0x700
--  BuildMI(TailMBB, DL, TII->get(LoongArch::DBAR)).addImm(0x700);
-+  //   dbar 0x700 | acquire
-+  BuildMI(TailMBB, DL, TII->get(LoongArch::DBAR)).addImm(hint);
- 
-   NextMBBI = MBB.end();
-   MI.eraseFromParent();
-diff --git a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
-index 05ae36a9781d..a9b0db30c2f6 100644
---- a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td

_service:tar_scm:0020-Update-llvm-lit-config-to-support-build_for_openeule.patch Deleted

_service:tar_scm:0021-Add-BiSheng-Autotuner-support-for-LLVM-compiler.patch Deleted

@@ -1,9915 +0,0 @@
-From a9863e2b6e6783aa9be0b9d1d187084fd4b32a3a Mon Sep 17 00:00:00 2001
-From: Muhammad Asif Manzoor <muhammad.asif.manzoor1@huawei.com>
-Date: Thu, 21 Mar 2024 12:50:38 -0400
-Subject: Add BiSheng Autotuner support for LLVM compiler
-
-Automatic tuning is an automatic iterative process that optimizes a given
-program by manipulating compilation options for optimal performance.
-BiSheng Autotuner provides a resumable interface for tuning process. BiSheng
-Autotuner can tune 1) individual code segments/blocks (fine grain turning) like
-loops, callsites, instructions, etc. and 2) entire modules/programs (coarse
-grain tuning) for compiler flags, pass ordering, etc.
-This patch enables LLVM compiler to extract tuneable code regions and then apply
-suggested configuration (by Autotuner) to find out the optimal configurations.
----
- llvm/cmake/modules/CrossCompile.cmake         |   1 +
- llvm/cmake/modules/HandleLLVMOptions.cmake    |   8 +
- llvm/include/llvm/Analysis/AutotuningDump.h   |  75 ++
- llvm/include/llvm/Analysis/LoopInfo.h         |  13 +
- llvm/include/llvm/Analysis/Passes.h           |  10 +
- llvm/include/llvm/AutoTuner/AutoTuning.h      | 486 ++++++++++++
- .../llvm/AutoTuner/AutoTuningRemarkManager.h  |  43 ++
- .../llvm/AutoTuner/AutoTuningRemarkStreamer.h |  47 ++
- llvm/include/llvm/CodeGen/MachineBasicBlock.h |  13 +
- llvm/include/llvm/IR/Function.h               |  37 +
- llvm/include/llvm/IR/InstrTypes.h             |  24 +
- llvm/include/llvm/IR/Instructions.h           |  24 +
- llvm/include/llvm/IR/Module.h                 |   3 +
- llvm/include/llvm/IR/StructuralHash.h         |  14 +
- llvm/include/llvm/InitializePasses.h          |   5 +
- llvm/include/llvm/LinkAllPasses.h             |   8 +
- llvm/include/llvm/Remarks/Remark.h            |  32 +
- llvm/include/llvm/Support/CommandLine.h       |  17 +
- llvm/include/llvm/Transforms/Scalar.h         |  17 +
- .../Transforms/Scalar/AutoTuningCompile.h     | 170 +++++
- .../llvm/Transforms/Utils/UnrollLoop.h        |   4 +
- llvm/lib/Analysis/AutotuningDump.cpp          | 265 +++++++
- llvm/lib/Analysis/CMakeLists.txt              |   2 +
- llvm/lib/Analysis/InlineAdvisor.cpp           |  18 +
- llvm/lib/Analysis/InlineCost.cpp              |  29 +
- llvm/lib/Analysis/LoopInfo.cpp                |  52 ++
- llvm/lib/AutoTuner/AutoTuning.cpp             | 705 ++++++++++++++++++
- .../lib/AutoTuner/AutoTuningRemarkManager.cpp | 299 ++++++++
- .../AutoTuner/AutoTuningRemarkStreamer.cpp    |  55 ++
- llvm/lib/AutoTuner/CMakeLists.txt             |  11 +
- llvm/lib/CMakeLists.txt                       |   1 +
- llvm/lib/CodeGen/CMakeLists.txt               |   1 +
- llvm/lib/CodeGen/CalcSpillWeights.cpp         |  30 +
- llvm/lib/CodeGen/MachineBasicBlock.cpp        |  36 +
- llvm/lib/CodeGen/MachineScheduler.cpp         |  44 ++
- llvm/lib/CodeGen/SwitchLoweringUtils.cpp      |  19 +
- llvm/lib/IR/AsmWriter.cpp                     | 151 ++++
- llvm/lib/IR/CMakeLists.txt                    |   1 +
- llvm/lib/IR/Function.cpp                      |  34 +
- llvm/lib/IR/Instructions.cpp                  |  86 +++
- llvm/lib/IR/StructuralHash.cpp                | 114 +++
- llvm/lib/Passes/PassBuilder.cpp               |   5 +
- llvm/lib/Passes/PassBuilderPipelines.cpp      |  46 ++
- llvm/lib/Passes/PassRegistry.def              |  13 +
- llvm/lib/Passes/StandardInstrumentations.cpp  |  23 +
- .../lib/Remarks/BitstreamRemarkSerializer.cpp |   8 +
- llvm/lib/Remarks/RemarkStreamer.cpp           |   4 +
- llvm/lib/Remarks/YAMLRemarkParser.cpp         | 122 +++
- llvm/lib/Remarks/YAMLRemarkParser.h           |   6 +
- llvm/lib/Remarks/YAMLRemarkSerializer.cpp     |  84 +++
- llvm/lib/Support/CommandLine.cpp              |  41 +
- llvm/lib/Transforms/IPO/CMakeLists.txt        |   1 +
- llvm/lib/Transforms/IPO/Inliner.cpp           |  36 +
- llvm/lib/Transforms/IPO/SampleProfile.cpp     |  14 +
- .../Transforms/Instrumentation/CMakeLists.txt |   1 +
- .../Instrumentation/PGOInstrumentation.cpp    |   8 +
- .../Transforms/Scalar/AutoTuningCompile.cpp   | 334 +++++++++
- llvm/lib/Transforms/Scalar/CMakeLists.txt     |   2 +
- llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp | 187 +++++
- llvm/lib/Transforms/Scalar/Scalar.cpp         |   4 +
- llvm/lib/Transforms/Scalar/Sink.cpp           |   5 +
- llvm/lib/Transforms/Utils/CMakeLists.txt      |   1 +
- llvm/lib/Transforms/Utils/LCSSA.cpp           |   5 +
- llvm/lib/Transforms/Utils/LoopSimplify.cpp    |   8 +
- llvm/lib/Transforms/Utils/LoopUnroll.cpp      |   3 +
- llvm/lib/Transforms/Vectorize/CMakeLists.txt  |   1 +
- .../Vectorize/LoopVectorizationLegality.cpp   |  12 +
- .../Transforms/Vectorize/LoopVectorize.cpp    |  34 +
- .../Inputs/unroll_template.yaml               |   8 +
- .../AutotuningDump/create-data-dir.ll         |  65 ++
- llvm/test/AutoTuning/AutotuningDump/unroll.ll |  35 +
- .../autotune_datadir/baseline_config.yaml     |   9 +
- .../autotune_datadir/random_config.yaml       |   9 +
- .../AutoTuning/BaselineConfig/Inputs/test.ll  | 117 +++
- .../BaselineConfig/apply_baseline_config.ll   |  11 +
- llvm/test/AutoTuning/BaselineConfig/opp.ll    |  67 ++
- .../CodeRegionFilter/function-filtering.ll    |  62 ++
- .../Error/Inputs/invalid-format.yaml          |   3 +
- .../AutoTuning/Error/Inputs/template.yaml     |  10 +
- .../AutoTuning/Error/file-not-found-error.ll  |  29 +
- .../AutoTuning/Error/invalid-yaml-error.ll    |  27 +
- .../AutoTuning/Error/malformed-input-error.ll | 136 ++++
- llvm/test/AutoTuning/Error/output-error.ll    |  28 +
- llvm/test/AutoTuning/Error/valid-input.ll     |  27 +
- .../Inputs/template.yaml                      |   9 +
- .../inc-compile-parse-input.ll                | 103 +++
- .../AutoTuning/Inline/Inputs/template.yaml    |   9 +
- .../Inline/Inputs/template_no_metadata.yaml   |   7 +
- .../test/AutoTuning/Inline/duplicate-calls.ll |  96 +++
- llvm/test/AutoTuning/Inline/force-inline.ll   |  84 +++
- .../AutoTuning/Inline/inline-attribute.ll     |  85 +++
- llvm/test/AutoTuning/Inline/opp.ll            |  64 ++
- .../LoopUnroll/Inputs/debug_loc_template.yaml |  10 +
- .../LoopUnroll/Inputs/loop_nest.yaml          |  10 +
- .../LoopUnroll/Inputs/loop_peel.yaml          |   9 +
- .../Inputs/unroll_raw_template.yaml           |  10 +
- .../LoopUnroll/Inputs/unroll_template.yaml    |  10 +
- .../Inputs/unroll_template_no_metadata.yaml   |   8 +
- llvm/test/AutoTuning/LoopUnroll/debug_loc.ll  | 161 ++++
- .../AutoTuning/LoopUnroll/dynamic_config.ll   |  56 ++
- llvm/test/AutoTuning/LoopUnroll/loop_nest.ll  | 136 ++++
- llvm/test/AutoTuning/LoopUnroll/loop_peel.ll  |  53 ++
- .../AutoTuning/LoopUnroll/unroll-pragma.ll    | 129 ++++
- llvm/test/AutoTuning/LoopUnroll/unroll.ll     | 101 +++
- llvm/test/AutoTuning/LoopUnroll/unroll_raw.ll | 113 +++
- .../Inputs/vectorize_template.yaml            |   9 +
- .../vectorize_template_no_metadata.yaml       |   7 +
- .../LoopVectorize/force-vector-interleave.ll  |  88 +++
- .../Inputs/misched_x86_template.yaml          |  10 +
- .../misched_x86_bidirectional.ll              |  73 ++
- .../MachineScheduler/misched_x86_bottomup.ll  |  72 ++
- .../MachineScheduler/misched_x86_topdown.ll   |  72 ++
- .../AutoTuning/MetaData/structural_hash.ll    | 234 ++++++
- .../AutoTuning/MetaData/write_no_metadata.ll  | 191 +++++
- .../MetaData/write_with_metadata.ll           | 204 +++++
- .../AutoTuning/PGO/Inputs/pgo-instr.proftext  |  17 +
- .../PGO/Inputs/pgo-sample-cold.prof           |   7 +
- .../AutoTuning/PGO/Inputs/pgo-sample-hot.prof |   7 +
- llvm/test/AutoTuning/PGO/pgo-instr-filters.ll |  61 ++
- .../test/AutoTuning/PGO/pgo-sample-filters.ll | 138 ++++
- .../Inputs/pass_invocation.yaml               |  10 +
- .../PassInvocation/pass_invocation_read.ll    |  64 ++
- .../PassInvocation/pass_invocation_write.ll   |  67 ++
- .../PhaseOrdering/Inputs/template.yaml        |   8 +
- .../AutoTuning/PhaseOrdering/pass-order.ll    |  65 ++
- .../AutoTuning/SwitchLowering/switch-opp.ll   |  47 ++
- llvm/test/AutoTuning/lit.local.cfg            |   2 +
- llvm/test/AutoTuning/opt-opp.ll               | 315 ++++++++
- llvm/test/lit.site.cfg.py.in                  |   1 +
- llvm/tools/llc/llc.cpp                        |  19 +
- llvm/tools/opt/NewPMDriver.cpp                |  42 ++
- llvm/tools/opt/opt.cpp                        |  53 ++
- 132 files changed, 7801 insertions(+)
- create mode 100644 llvm/include/llvm/Analysis/AutotuningDump.h
- create mode 100644 llvm/include/llvm/AutoTuner/AutoTuning.h
- create mode 100644 llvm/include/llvm/AutoTuner/AutoTuningRemarkManager.h
- create mode 100644 llvm/include/llvm/AutoTuner/AutoTuningRemarkStreamer.h
- create mode 100644 llvm/include/llvm/Transforms/Scalar/AutoTuningCompile.h
- create mode 100644 llvm/lib/Analysis/AutotuningDump.cpp
- create mode 100644 llvm/lib/AutoTuner/AutoTuning.cpp
- create mode 100644 llvm/lib/AutoTuner/AutoTuningRemarkManager.cpp
- create mode 100644 llvm/lib/AutoTuner/AutoTuningRemarkStreamer.cpp
- create mode 100644 llvm/lib/AutoTuner/CMakeLists.txt
- create mode 100644 llvm/lib/Transforms/Scalar/AutoTuningCompile.cpp
- create mode 100644 llvm/test/AutoTuning/AutotuningDump/Inputs/unroll_template.yaml
- create mode 100644 llvm/test/AutoTuning/AutotuningDump/create-data-dir.ll
- create mode 100644 llvm/test/AutoTuning/AutotuningDump/unroll.ll
- create mode 100644 llvm/test/AutoTuning/BaselineConfig/Inputs/autotune_datadir/baseline_config.yaml
- create mode 100644 llvm/test/AutoTuning/BaselineConfig/Inputs/autotune_datadir/random_config.yaml
- create mode 100644 llvm/test/AutoTuning/BaselineConfig/Inputs/test.ll
- create mode 100644 llvm/test/AutoTuning/BaselineConfig/apply_baseline_config.ll
- create mode 100644 llvm/test/AutoTuning/BaselineConfig/opp.ll
- create mode 100644 llvm/test/AutoTuning/CodeRegionFilter/function-filtering.ll
- create mode 100644 llvm/test/AutoTuning/Error/Inputs/invalid-format.yaml
- create mode 100644 llvm/test/AutoTuning/Error/Inputs/template.yaml
- create mode 100644 llvm/test/AutoTuning/Error/file-not-found-error.ll
- create mode 100644 llvm/test/AutoTuning/Error/invalid-yaml-error.ll
- create mode 100644 llvm/test/AutoTuning/Error/malformed-input-error.ll
- create mode 100644 llvm/test/AutoTuning/Error/output-error.ll
- create mode 100644 llvm/test/AutoTuning/Error/valid-input.ll
- create mode 100644 llvm/test/AutoTuning/IncrementalCompilation/Inputs/template.yaml
- create mode 100644 llvm/test/AutoTuning/IncrementalCompilation/inc-compile-parse-input.ll
- create mode 100644 llvm/test/AutoTuning/Inline/Inputs/template.yaml
- create mode 100644 llvm/test/AutoTuning/Inline/Inputs/template_no_metadata.yaml
- create mode 100644 llvm/test/AutoTuning/Inline/duplicate-calls.ll
- create mode 100644 llvm/test/AutoTuning/Inline/force-inline.ll
- create mode 100644 llvm/test/AutoTuning/Inline/inline-attribute.ll
- create mode 100644 llvm/test/AutoTuning/Inline/opp.ll
- create mode 100644 llvm/test/AutoTuning/LoopUnroll/Inputs/debug_loc_template.yaml
- create mode 100644 llvm/test/AutoTuning/LoopUnroll/Inputs/loop_nest.yaml
- create mode 100644 llvm/test/AutoTuning/LoopUnroll/Inputs/loop_peel.yaml
- create mode 100644 llvm/test/AutoTuning/LoopUnroll/Inputs/unroll_raw_template.yaml
- create mode 100644 llvm/test/AutoTuning/LoopUnroll/Inputs/unroll_template.yaml
- create mode 100644 llvm/test/AutoTuning/LoopUnroll/Inputs/unroll_template_no_metadata.yaml
- create mode 100644 llvm/test/AutoTuning/LoopUnroll/debug_loc.ll
- create mode 100644 llvm/test/AutoTuning/LoopUnroll/dynamic_config.ll
- create mode 100644 llvm/test/AutoTuning/LoopUnroll/loop_nest.ll
- create mode 100644 llvm/test/AutoTuning/LoopUnroll/loop_peel.ll
- create mode 100644 llvm/test/AutoTuning/LoopUnroll/unroll-pragma.ll
- create mode 100644 llvm/test/AutoTuning/LoopUnroll/unroll.ll
- create mode 100644 llvm/test/AutoTuning/LoopUnroll/unroll_raw.ll
- create mode 100644 llvm/test/AutoTuning/LoopVectorize/Inputs/vectorize_template.yaml
- create mode 100644 llvm/test/AutoTuning/LoopVectorize/Inputs/vectorize_template_no_metadata.yaml
- create mode 100644 llvm/test/AutoTuning/LoopVectorize/force-vector-interleave.ll
- create mode 100644 llvm/test/AutoTuning/MachineScheduler/Inputs/misched_x86_template.yaml

_service Changed

_service:tar_scm:README.en.md Changed

_service:tar_scm:README.md Changed

_service:tar_scm:cmake-17.0.6.src.tar.xz Deleted

_service:tar_scm:dav1d-1.5.0.tar.bz2 Added

_service:tar_scm:dav1d.yaml Added

_service:tar_scm:llvm-17.0.6.src.tar.xz Deleted

_service:tar_scm:llvm.yaml Deleted

_service:tar_scm:third-party-17.0.6.src.tar.xz Deleted