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Changes of Revision 12
View file
_service:tar_scm:llvm.spec
Changed
@@ -37,7 +37,7 @@ Name: %{pkg_name} Version: %{maj_ver}.%{min_ver}.%{patch_ver} -Release: 5 +Release: 7 Summary: The Low Level Virtual Machine License: NCSA @@ -61,6 +61,9 @@ Patch11: 0011-Backport-LoongArch-Add-the-support-for-vector-in-llvm17.patch Patch12: 0012-Backport-LoongArch-improve-the-support-for-compiler-rt-and-bugfix.patch Patch13: 0013-Backport-Bitcode-Add-some-missing-GetTypeByID-failure-checks.patch +Patch14: 0001-Backport-X86-Inline-Skip-inline-asm-in-inlining-targ.patch +Patch15: 0015-Backport-ARM-Check-all-terms-in-emitPopInst-when-clearing-Res.patch +Patch16: 0016-Backport-ARM-Update-IsRestored-for-LR-based-on-all-returns-82.patch BuildRequires: binutils-devel BuildRequires: cmake @@ -343,6 +346,12 @@ %{install_includedir}/llvm-gmock %changelog +* Fri Apr 12 2024 liyunfei <liyunfei33@huawei.com> - 17.0.6-6 +- Backport patch to fix CVE-2024-31852 + +* Thu Apr 11 2024 wangqiang <wangqiang1@kylinos.cn> - 17.0.6-6 +- Skip inline asm in inlining target feature check on X86 + * Tue Apr 09 2024 liyunfei <liyunfei33@huawei.com> - 17.0.6-5 - Backport patch to fix CVE-2023-46049
View file
_service:tar_scm:0001-Backport-X86-Inline-Skip-inline-asm-in-inlining-targ.patch
Added
@@ -0,0 +1,74 @@ +From 678cf3a36644847cac4b0be2d919aba77416088a Mon Sep 17 00:00:00 2001 +From: Nikita Popov <npopov@redhat.com> +Date: Mon, 04 Mar 2024 07:00:37 +0800 +Subject: PATCH BackportX86Inline Skip inline asm in inlining target + feature check + +When inlining across functions with different target features, we +perform roughly two checks: +1. The caller features must be a superset of the callee features. +2. Calls in the callee cannot use types where the target features would +change the call ABI (e.g. by changing whether something is passed in a +zmm or two ymm registers). The latter check is very crude right now. + +The latter check currently also catches inline asm "calls". I believe +that inline asm should be excluded from this check, as it is independent +from the usual call ABI, and instead governed by the inline asm +constraint string. +--- + .../lib/Target/X86/X86TargetTransformInfo.cpp | 4 +++ + .../Inline/X86/call-abi-compatibility.ll | 26 +++++++++++++++++++ + 2 files changed, 30 insertions(+) + +diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp +index 129a2646d..9c7954230 100644 +--- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp ++++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp +@@ -6046,6 +6046,10 @@ bool X86TTIImpl::areInlineCompatible(const Function *Caller, + + for (const Instruction &I : instructions(Callee)) { + if (const auto *CB = dyn_cast<CallBase>(&I)) { ++ // Having more target features is fine for inline ASM. ++ if (CB->isInlineAsm()) ++ continue; ++ + SmallVector<Type *, 8> Types; + for (Value *Arg : CB->args()) + Types.push_back(Arg->getType()); +diff --git a/llvm/test/Transforms/Inline/X86/call-abi-compatibility.ll b/llvm/test/Transforms/Inline/X86/call-abi-compatibility.ll +index 3a30980fe..6f582cab2 100644 +--- a/llvm/test/Transforms/Inline/X86/call-abi-compatibility.ll ++++ b/llvm/test/Transforms/Inline/X86/call-abi-compatibility.ll +@@ -93,3 +93,29 @@ define internal void @caller_not_avx4() { + } + + declare i64 @caller_unknown_simple(i64) ++ ++; This call should get inlined, because the callee only contains ++; inline ASM, not real calls. ++define <8 x i64> @caller_inline_asm(ptr %p0, i64 %k, ptr %p1, ptr %p2) #0 { ++; CHECK-LABEL: define {{^@+}}@caller_inline_asm ++; CHECK-SAME: (ptr P0:%.*, i64 K:%.*, ptr P1:%.*, ptr P2:%.*) #ATTR2:0-9+ { ++; CHECK-NEXT: SRC_I:%.* = load <8 x i64>, ptr P0, align 64 ++; CHECK-NEXT: A_I:%.* = load <8 x i64>, ptr P1, align 64 ++; CHECK-NEXT: B_I:%.* = load <8 x i64>, ptr P2, align 64 ++; CHECK-NEXT: TMP1:%.* = call <8 x i64> asm "vpaddb\09$($3, $2, $0 {$1}", "=v,^Yk,v,v,0,~{dirflag},~{fpsr},~{flags}"(i64 K, <8 x i64> A_I, <8 x i64> B_I, <8 x i64> SRC_I) ++; CHECK-NEXT: ret <8 x i64> TMP1 ++; ++ %call = call <8 x i64> @callee_inline_asm(ptr %p0, i64 %k, ptr %p1, ptr %p2) ++ ret <8 x i64> %call ++} ++ ++define internal <8 x i64> @callee_inline_asm(ptr %p0, i64 %k, ptr %p1, ptr %p2) #1 { ++ %src = load <8 x i64>, ptr %p0, align 64 ++ %a = load <8 x i64>, ptr %p1, align 64 ++ %b = load <8 x i64>, ptr %p2, align 64 ++ %1 = tail call <8 x i64> asm "vpaddb\09$($3, $2, $0 {$1}", "=v,^Yk,v,v,0,~{dirflag},~{fpsr},~{flags}"(i64 %k, <8 x i64> %a, <8 x i64> %b, <8 x i64> %src) #2 ++ ret <8 x i64> %1 ++} ++ ++attributes #0 = { "min-legal-vector-width"="512" "target-features"="+avx,+avx2,+avx512bw,+avx512dq,+avx512f,+cmov,+crc32,+cx8,+evex512,+f16c,+fma,+fxsr,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave" "tune-cpu"="generic" } ++attributes #1 = { "min-legal-vector-width"="512" "target-features"="+avx,+avx2,+avx512bw,+avx512f,+cmov,+crc32,+cx8,+evex512,+f16c,+fma,+fxsr,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave" "tune-cpu"="generic" } +-- +2.33.0 +
View file
_service:tar_scm:0015-Backport-ARM-Check-all-terms-in-emitPopInst-when-clearing-Res.patch
Added
@@ -0,0 +1,87 @@ +From 4aec2da60ce3f639e31d81406c09d5c88b3b8f53 Mon Sep 17 00:00:00 2001 +From: Florian Hahn <flo@fhahn.com> +Date: Wed, 20 Dec 2023 16:56:15 +0100 +Subject: PATCH 2/3 ARM Check all terms in emitPopInst when clearing + Restored for LR. (#75527) + +emitPopInst checks a single function exit MBB. If other paths also exit +the function and any of there terminators uses LR implicitly, it is not +save to clear the Restored bit. + +Check all terminators for the function before clearing Restored. + +This fixes a mis-compile in outlined-fn-may-clobber-lr-in-caller.ll +where the machine-outliner previously introduced BLs that clobbered LR +which in turn is used by the tail call return. + +Alternative to #73553 +--- + llvm/lib/Target/ARM/ARMFrameLowering.cpp | 30 +++++++++++++++++++++--- + llvm/lib/Target/ARM/ARMFrameLowering.h | 3 +++ + 2 files changed, 30 insertions(+), 3 deletions(-) + +diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp +index 4496d4928ebe..650f4650eef0 100644 +--- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp ++++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp +@@ -1645,9 +1645,6 @@ void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB, + // Fold the return instruction into the LDM. + DeleteRet = true; + LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_RET : ARM::LDMIA_RET; +- // We 'restore' LR into PC so it is not live out of the return block: +- // Clear Restored bit. +- Info.setRestored(false); + } + + // If NoGap is true, pop consecutive registers and then leave the rest +@@ -2769,6 +2766,33 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF, + AFI->setLRIsSpilled(SavedRegs.test(ARM::LR)); + } + ++void ARMFrameLowering::processFunctionBeforeFrameFinalized( ++ MachineFunction &MF, RegScavenger *RS) const { ++ TargetFrameLowering::processFunctionBeforeFrameFinalized(MF, RS); ++ ++ MachineFrameInfo &MFI = MF.getFrameInfo(); ++ if (!MFI.isCalleeSavedInfoValid()) ++ return; ++ ++ // Check if all terminators do not implicitly use LR. Then we can 'restore' LR ++ // into PC so it is not live out of the return block: Clear the Restored bit ++ // in that case. ++ for (CalleeSavedInfo &Info : MFI.getCalleeSavedInfo()) { ++ if (Info.getReg() != ARM::LR) ++ continue; ++ if (all_of(MF, (const MachineBasicBlock &MBB) { ++ return all_of(MBB.terminators(), (const MachineInstr &Term) { ++ return !Term.isReturn() || Term.getOpcode() == ARM::LDMIA_RET || ++ Term.getOpcode() == ARM::t2LDMIA_RET || ++ Term.getOpcode() == ARM::tPOP_RET; ++ }); ++ })) { ++ Info.setRestored(false); ++ break; ++ } ++ } ++} ++ + void ARMFrameLowering::getCalleeSaves(const MachineFunction &MF, + BitVector &SavedRegs) const { + TargetFrameLowering::getCalleeSaves(MF, SavedRegs); +diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.h b/llvm/lib/Target/ARM/ARMFrameLowering.h +index 16f2ce6bea6f..8d2b8beb9a58 100644 +--- a/llvm/lib/Target/ARM/ARMFrameLowering.h ++++ b/llvm/lib/Target/ARM/ARMFrameLowering.h +@@ -59,6 +59,9 @@ public: + void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, + RegScavenger *RS) const override; + ++ void processFunctionBeforeFrameFinalized( ++ MachineFunction &MF, RegScavenger *RS = nullptr) const override; ++ + void adjustForSegmentedStacks(MachineFunction &MF, + MachineBasicBlock &MBB) const override; + +-- +2.33.0 +
View file
_service:tar_scm:0016-Backport-ARM-Update-IsRestored-for-LR-based-on-all-returns-82.patch
Added
@@ -0,0 +1,116 @@ +From 369bfc8ea8c0a9da51b4bd964f0045cb389c3c2f Mon Sep 17 00:00:00 2001 +From: ostannard <oliver.stannard@arm.com> +Date: Mon, 26 Feb 2024 12:23:25 +0000 +Subject: PATCH 3/3 ARM Update IsRestored for LR based on all returns + (#82745) + +PR #75527 fixed ARMFrameLowering to set the IsRestored flag for LR based +on all of the return instructions in the function, not just one. +However, there is also code in ARMLoadStoreOptimizer which changes +return instructions, but it set IsRestored based on the one instruction +it changed, not the whole function. + +The fix is to factor out the code added in #75527, and also call it from +ARMLoadStoreOptimizer if it made a change to return instructions. + +Fixes #80287. +--- + llvm/lib/Target/ARM/ARMFrameLowering.cpp | 11 +++++---- + llvm/lib/Target/ARM/ARMFrameLowering.h | 4 ++++ + llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 23 ++++++++----------- + 3 files changed, 21 insertions(+), 17 deletions(-) + +diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp +index 650f4650eef0..008ba4e5924b 100644 +--- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp ++++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp +@@ -2766,10 +2766,7 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF, + AFI->setLRIsSpilled(SavedRegs.test(ARM::LR)); + } + +-void ARMFrameLowering::processFunctionBeforeFrameFinalized( +- MachineFunction &MF, RegScavenger *RS) const { +- TargetFrameLowering::processFunctionBeforeFrameFinalized(MF, RS); +- ++void ARMFrameLowering::updateLRRestored(MachineFunction &MF) { + MachineFrameInfo &MFI = MF.getFrameInfo(); + if (!MFI.isCalleeSavedInfoValid()) + return; +@@ -2793,6 +2790,12 @@ void ARMFrameLowering::processFunctionBeforeFrameFinalized( + } + } + ++void ARMFrameLowering::processFunctionBeforeFrameFinalized( ++ MachineFunction &MF, RegScavenger *RS) const { ++ TargetFrameLowering::processFunctionBeforeFrameFinalized(MF, RS); ++ updateLRRestored(MF); ++} ++ + void ARMFrameLowering::getCalleeSaves(const MachineFunction &MF, + BitVector &SavedRegs) const { + TargetFrameLowering::getCalleeSaves(MF, SavedRegs); +diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.h b/llvm/lib/Target/ARM/ARMFrameLowering.h +index 8d2b8beb9a58..3c7358d8cd53 100644 +--- a/llvm/lib/Target/ARM/ARMFrameLowering.h ++++ b/llvm/lib/Target/ARM/ARMFrameLowering.h +@@ -59,6 +59,10 @@ public: + void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, + RegScavenger *RS) const override; + ++ /// Update the IsRestored flag on LR if it is spilled, based on the return ++ /// instructions. ++ static void updateLRRestored(MachineFunction &MF); ++ + void processFunctionBeforeFrameFinalized( + MachineFunction &MF, RegScavenger *RS = nullptr) const override; + +diff --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +index 93db983b92c0..37d9e1addd1e 100644 +--- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp ++++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +@@ -2062,17 +2062,6 @@ bool ARMLoadStoreOpt::MergeReturnIntoLDM(MachineBasicBlock &MBB) { + MO.setReg(ARM::PC); + PrevMI.copyImplicitOps(*MBB.getParent(), *MBBI); + MBB.erase(MBBI); +- // We now restore LR into PC so it is not live-out of the return block +- // anymore: Clear the CSI Restored bit. +- MachineFrameInfo &MFI = MBB.getParent()->getFrameInfo(); +- // CSI should be fixed after PrologEpilog Insertion +- assert(MFI.isCalleeSavedInfoValid() && "CSI should be valid"); +- for (CalleeSavedInfo &Info : MFI.getCalleeSavedInfo()) { +- if (Info.getReg() == ARM::LR) { +- Info.setRestored(false); +- break; +- } +- } + return true; + } + } +@@ -2120,14 +2109,22 @@ bool ARMLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) { + isThumb2 = AFI->isThumb2Function(); + isThumb1 = AFI->isThumbFunction() && !isThumb2; + +- bool Modified = false; ++ bool Modified = false, ModifiedLDMReturn = false; + for (MachineBasicBlock &MBB : Fn) { + Modified |= LoadStoreMultipleOpti(MBB); + if (STI->hasV5TOps() && !AFI->shouldSignReturnAddress()) +- Modified |= MergeReturnIntoLDM(MBB); ++ ModifiedLDMReturn |= MergeReturnIntoLDM(MBB); + if (isThumb1) + Modified |= CombineMovBx(MBB); + } ++ Modified |= ModifiedLDMReturn; ++ ++ // If we merged a BX instruction into an LDM, we need to re-calculate whether ++ // LR is restored. This check needs to consider the whole function, not just ++ // the instruction(s) we changed, because there may be other BX returns which ++ // still need LR to be restored. ++ if (ModifiedLDMReturn) ++ ARMFrameLowering::updateLRRestored(Fn); + + Allocator.DestroyAll(); + return Modified; +-- +2.33.0 +
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