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Changes of Revision 14
View file
_service:tar_scm:binutils.spec
Changed
@@ -2,7 +2,7 @@ Summary: A GNU collection of binary utilities Name: binutils%{?_with_debug:-debug} Version: 2.41 -Release: 10 +Release: 11 License: GPL-3.0-or-later AND (GPL-3.0-or-later WITH Bison-exception-2.2) AND (LGPL-2.0-or-later WITH GCC-exception-2.0) AND BSD-3-Clause AND GFDL-1.3-or-later AND GPL-2.0-or-later AND LGPL-2.1-or-later AND LGPL-2.0-or-later URL: https://sourceware.org/binutils @@ -176,6 +176,128 @@ Patch3009: as-Add-new-estimated-reciprocal-instructions-in-Loon.patch Patch3010: LoongArch-Modify-inconsistent-behavior-of-ld-with-un.patch Patch3011: backport-ld-Remove-JANSSON_LIBS-from-ld_new_DEPENDENCIES.patch +Patch3012: LoongArch-Fix-immediate-overflow-check-bug.patch +Patch3013: LoongArch-ld-Simplify-inserting-IRELATIVE-relocation.patch +Patch3014: Libvtv-Add-loongarch-support.patch +Patch3015: LoongArch-implement-count_-leading-trailing-_zeros.patch +Patch3016: LoongArch-gas-Fix-make-check-gas-crash.patch +Patch3017: Use-32-64_PCREL-to-replace-a-pair-of-ADD32-64-and-SU.patch +Patch3018: Add-testcase-for-generation-of-32-64_PCREL.patch +Patch3019: Make-sure-DW_CFA_advance_loc4-is-in-the-same-frag.patch +Patch3020: LoongArch-Enable-gas-sort-relocs.patch +Patch3021: Add-support-for-pcaddi-rd-symbol.patch +Patch3022: as-add-option-for-generate-R_LARCH_32-64_PCREL.patch +Patch3023: Add-testsuits-for-new-assembler-option-of-mthin-add-.patch +Patch3024: LoongArch-GAS-Add-support-for-branch-relaxation.patch +Patch3025: LoongArch-readelf-d-RELASZ-excludes-.rela.plt-size.patch +Patch3026: LoongArch-Correct-comments.patch +Patch3027: as-fixed-internal-error-when-immediate-value-of-relo.patch +Patch3028: Add-support-for-ilp32-register-alias.patch +Patch3029: MIPS-GAS-Add-march-loongson2f-to-loongson-2f-3-test.patch +Patch3030: LoongArch-Add-support-for-b-.L1-and-beq-t0-t1-.L1.patch +Patch3031: LoongArch-Add-new-relocation-R_LARCH_CALL36.patch +Patch3032: LoongArch-Add-call36-and-tail36-pseudo-instructions-.patch +Patch3033: LoongArch-Allow-la.got-la.pcrel-relaxation-for-share.patch +Patch3034: LoongArch-Add-support-for-the-third-expression-of-.a.patch +Patch3035: Re-LoongArch-Add-support-for-b-.L1-and-beq-t0-t1-.L1.patch +Patch3036: LoongArch-Add-new-relocs-and-macro-for-TLSDESC.patch +Patch3037: LoongArch-Add-support-for-TLSDESC-in-ld.patch +Patch3038: LoongArch-Add-tls-transition-support.patch +Patch3039: LoongArch-Add-support-for-TLS-LD-GD-DESC-relaxation.patch +Patch3040: LoongArch-Add-testsuit-for-DESC-and-tls-transition-a.patch +Patch3041: asan-buffer-overflow-in-loongarch_elf_rtype_to_howto.patch +Patch3042: LoongArch-bfd-Add-support-for-tls-le-relax.patch +Patch3043: LoongArch-include-Add-support-for-tls-le-relax.patch +Patch3044: LoongArch-opcodes-Add-support-for-tls-le-relax.patch +Patch3045: LoongArch-gas-Add-support-for-tls-le-relax.patch +Patch3046: LoongArch-ld-Add-support-for-tls-le-relax.patch +Patch3047: LoongArch-Commas-inside-double-quotes.patch +Patch3048: LoongArch-Fix-some-macro-that-cannot-be-expanded-pro.patch +Patch3049: LoongArch-Fix-loongarch-elf-target-ld-testsuite-fail.patch +Patch3050: LoongArch-Fix-linker-generate-PLT-entry-for-data-sym.patch +Patch3051: loongarch-index-shadows-global.patch +Patch3052: LoongArch-Discard-extra-spaces-in-objdump-output.patch +Patch3053: LoongArch-ld-Adjusted-some-code-order-in-relax.exp.patch +Patch3054: LoongArch-Fix-relaxation-overflow-caused-by-section-.patch +Patch3055: LoongArch-Adapt-R_LARCH_-PCALA-GOT-TLS_IE-TLS_DESC-6.patch +Patch3056: LoongArch-Do-not-emit-R_LARCH_RELAX-for-two-register.patch +Patch3057: LoongArch-Use-tab-to-indent-assembly-in-TLSDESC-test.patch +Patch3058: LoongArch-Do-not-add-DF_STATIC_TLS-for-TLS-LE.patch +Patch3059: LoongArch-Fix-some-test-failures-about-TLS-desc-and-.patch +Patch3060: PATCH-v2-gas-NEWS-ld-NEWS-Announce-LoongArch-changes.patch +Patch3061: LoongArch-gas-Don-t-define-LoongArch-.align.patch +Patch3062: LoongArch-gas-Start-a-new-frag-after-instructions-th.patch +Patch3063: LoongArch-ld-Add-support-for-TLS-LE-symbol-with-adde.patch +Patch3064: LoongArch-gas-Add-support-for-s9-register.patch +Patch3065: LoongArch-Fix-a-bug-of-getting-relocation-type.patch +Patch3066: LoongArch-gas-Fix-the-types-of-symbols-referred-with.patch +Patch3067: LoongArch-gas-Try-to-avoid-R_LARCH_ALIGN-associate-w.patch +Patch3068: LoongArch-bfd-Correct-the-name-of-R_LARCH_SOP_POP_32.patch +Patch3069: LoongArch-bfd-Fix-some-bugs-of-howto-table.patch +Patch3070: LoongArch-ld-Fix-other-pop-relocs-overflow-check-and.patch +Patch3071: Avoid-unused-space-in-.rela.dyn-if-sec-was-discarded.patch +Patch3072: LoongArch-Run-overflow-testcases-only-on-LoongArch-t.patch +Patch3073: LoongArch-Add-gas-testsuit-for-alias-instructions.patch +Patch3074: LoongArch-Add-gas-testsuit-for-lbt-lvz-instructions.patch +Patch3075: LoongArch-Add-gas-testsuit-for-lsx-lasx-instructions.patch +Patch3076: LoongArch-Add-gas-testsuit-for-LA64-int-float-instru.patch +Patch3077: LoongArch-Add-gas-testsuit-for-LA32-int-float-instru.patch +Patch3078: LoongArch-Add-gas-testsuit-for-LA64-relocations.patch +Patch3079: LoongArch-Add-gas-testsuit-for-LA32-relocations.patch +Patch3080: LoongArch-Delete-extra-instructions-when-TLS-type-tr.patch +Patch3081: LoongArch-Add-dtpoff-calculation-function.patch +Patch3082: LoongArch-Fix-some-test-cases-for-TLS-transition-and.patch +Patch3083: LoongArch-Fix-gas-and-ld-test-cases.patch +Patch3084: LoongArch-Scan-all-illegal-operand-instructions-with.patch +Patch3085: LoongArch-Add-relaxation-for-R_LARCH_CALL36.patch +Patch3086: BFD-Fix-the-bug-of-R_LARCH_AGLIN-caused-by-discard-s.patch +Patch3087: LoongArch-gas-Ignore-.align-if-it-is-at-the-start-of.patch +Patch3088: LoongArch-Fix-the-issue-of-excessive-relocation-gene.patch +Patch3089: LoongArch-ld-Move-.got-.got.plt-before-.data-and-pro.patch +Patch3090: LoongArch-ld-Report-an-error-when-seeing-an-unrecogn.patch +Patch3091: LoongArch-Add-mignore-start-align-option.patch +Patch3092: LoongArch-The-symbol-got-type-can-only-be-obtained-a.patch +Patch3093: LoongArch-Add-bad-static-relocation-check-and-output.patch +Patch3094: LoongArch-gas-Simplify-relocations-in-sections-witho.patch +Patch3095: Fix-building-Loongarch-BFD-with-a-32-bit-compiler.patch +Patch3096: LoongArch-Fix-ld-test-failures-caused-by-using-instr.patch +Patch3097: LoongArch-gas-Adjust-DWARF-CIE-alignment-factors.patch +Patch3098: Re-LoongArch-gas-Adjust-DWARF-CIE-alignment-factors.patch +Patch3099: LoongArch-Fix-relaxation-overflow-caused-by-ld-z-sep.patch +Patch3100: LoongArch-Make-align-symbol-be-in-same-section-with-.patch +Patch3101: LoongArch-Disable-linker-relaxation-if-set-the-addre.patch +Patch3102: LoongArch-add-.option-directive.patch +Patch3103: LoongArch-TLS-IE-needs-only-one-dynamic-reloc.patch +Patch3104: LoongArch-Do-not-check-R_LARCH_SOP_PUSH_ABSOLUTE-to-.patch +Patch3105: LoongArch-Remove-unused-code-in-ld-test-suite.patch +Patch3106: LoongArch-Reject-R_LARCH_32-from-becoming-a-runtime-.patch +Patch3107: LoongArch-Fix-bad-reloc-with-mixed-visibility-ifunc-.patch +Patch3108: LoongArch-Make-protected-function-symbols-local-for-.patch +Patch3109: LoongArch-Add-DT_RELR-support.patch +Patch3110: LoongArch-Add-DT_RELR-tests.patch +Patch3111: LoongArch-Not-alloc-dynamic-relocs-if-symbol-is-abso.patch +Patch3112: LoongArch-Fix-dwarf3-test-cases-from-XPASS-to-PASS.patch +Patch3113: gas-NEWS-ld-NEWS-Announce-LoongArch-changes-in-2.43.patch +Patch3114: LoongArch-Fix-ld-FAIL-test-cases.patch +Patch3115: LoongArch-Add-support-for-OUTPUT_FORMAT-binary.patch +Patch3116: loongarch-ld-testsuite-xpasses.patch +Patch3117: LoongArch-Fix-assertion-failure-with-DT_RELR.patch +Patch3118: LoongArch-Fix-DT_RELR-and-relaxation-interaction.patch +Patch3119: LoongArch-Fix-wrong-relocation-handling-of-symbols-d.patch +Patch3120: LoongArch-LoongArch64-allows-relocations-to-use-64-b.patch +Patch3121: LoongArch-Fixed-ABI-v1.00-TLS-dynamic-relocation-gen.patch +Patch3122: Add-macros-to-get-opcode-of-instructions-approriatel.patch +Patch3123: Not-append-rela-for-absolute-symbol.patch +Patch3124: LoongArch-Add-elfNN_loongarch_mkobject-to-initialize.patch +Patch3125: LoongArch-Fixed-R_LARCH_-32-64-_PCREL-generation-bug.patch +Patch3126: LoongArch-Optimize-the-relaxation-process.patch +Patch3127: LoongArch-Add-more-relaxation-support-for-call36.patch +Patch3128: LoongArch-Force-relocation-for-every-reference-to-th.patch +Patch3129: LoongArch-Fixed-precedence-of-expression-operators-i.patch +Patch3130: Include-ldlex.h-when-compile-eelfxxloongarch.c.patch +Patch3131: Modify-test-because-of-readelf-not-update.patch +Patch3132: remove-file-produced-by-bison.patch +Patch3133: replace-space-with-tab.patch # Part 5000 - @@ -1247,6 +1369,9 @@ #---------------------------------------------------------------------------- %changelog +* Thu Oct 31 2024 wangxin <wangxin03@loongson.cn> - 2.41-11 +- LoongArch: sync patch from binutils upstream + * Thu Sep 26 2024 wangding <wangding16@huawei.com> - 2.41-10 - fix gold linker relocation offset
View file
_service:tar_scm:Add-macros-to-get-opcode-of-instructions-approriatel.patch
Added
@@ -0,0 +1,599 @@ +From 52fc0adff846e7fb01fd2995b5520e4194287489 Mon Sep 17 00:00:00 2001 +From: Xin Wang <yw987194828@gmail.com> +Date: Fri, 6 Sep 2024 08:54:07 +0800 +Subject: PATCH 112/123 Add macros to get opcode of instructions approriately + +LoongArch: Add macros to get opcode and register of instructions appropriately + +Currently, we get opcode of an instruction by manipulate the binary with +it's mask, it's a bit of a pain. Now a macro is defined to do this and a +macro to get the RD and RJ registers which is applicable to most instructions +of LoongArch are added. +--- + bfd/elfnn-loongarch.c | 62 +++--- + gas/config/tc-loongarch.c | 36 +-- + gas/testsuite/gas/loongarch/illegal-operand.l | 208 +++++++++--------- + include/opcode/loongarch.h | 70 +++++- + 4 files changed, 216 insertions(+), 160 deletions(-) + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index 30ac5555..770483cd 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -4064,7 +4064,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, + /* For 2G jump, generate pcalau12i, jirl. */ + /* If use jirl, turns to R_LARCH_B16. */ + uint32_t insn = bfd_get (32, input_bfd, contents + rel->r_offset); +- if ((insn & 0x4c000000) == 0x4c000000) ++ if (LARCH_INSN_JIRL(insn)) + { + relocation &= 0xfff; + /* Signed extend. */ +@@ -4704,7 +4704,7 @@ loongarch_tls_perform_trans (bfd *abfd, asection *sec, + pcalalau12i $a0,%desc_pc_hi20(var) => + lu12i.w $a0,%le_hi20(var) + */ +- bfd_put (32, abfd, LARCH_LU12I_W | LARCH_RD_A0, ++ bfd_put (32, abfd, LARCH_OP_LU12I_W | LARCH_RD_A0, + contents + rel->r_offset); + rel->r_info = ELFNN_R_INFO (r_symndx, R_LARCH_TLS_LE_HI20); + } +@@ -4725,8 +4725,8 @@ loongarch_tls_perform_trans (bfd *abfd, asection *sec, + addi.d $a0,$a0,%desc_pc_lo12(var) => + ori $a0,$a0,le_lo12(var) + */ +- insn = LARCH_ORI | LARCH_RD_RJ_A0; +- bfd_put (32, abfd, LARCH_ORI | LARCH_RD_RJ_A0, ++ insn = LARCH_OP_ORI | LARCH_RD_RJ_A0; ++ bfd_put (32, abfd, LARCH_OP_ORI | LARCH_RD_RJ_A0, + contents + rel->r_offset); + rel->r_info = ELFNN_R_INFO (r_symndx, R_LARCH_TLS_LE_LO12); + } +@@ -4736,7 +4736,7 @@ loongarch_tls_perform_trans (bfd *abfd, asection *sec, + addi.d $a0,$a0,%desc_pc_lo12(var) => + ld.d $a0,$a0,%ie_pc_lo12(var) + */ +- bfd_put (32, abfd, LARCH_LD_D | LARCH_RD_RJ_A0, ++ bfd_put (32, abfd, LARCH_OP_LD_D | LARCH_RD_RJ_A0, + contents + rel->r_offset); + rel->r_info = ELFNN_R_INFO (r_symndx, R_LARCH_TLS_IE_PC_LO12); + } +@@ -4763,7 +4763,7 @@ loongarch_tls_perform_trans (bfd *abfd, asection *sec, + lu12i.w $rd,%le_hi20(var) + */ + insn = bfd_getl32 (contents + rel->r_offset); +- bfd_put (32, abfd, LARCH_LU12I_W | (insn & 0x1f), ++ bfd_put (32, abfd, LARCH_OP_LU12I_W | LARCH_GET_RD(insn), + contents + rel->r_offset); + rel->r_info = ELFNN_R_INFO (r_symndx, R_LARCH_TLS_LE_HI20); + } +@@ -4777,7 +4777,7 @@ loongarch_tls_perform_trans (bfd *abfd, asection *sec, + ori $rd,$rj,le_lo12(var) + */ + insn = bfd_getl32 (contents + rel->r_offset); +- bfd_put (32, abfd, LARCH_ORI | (insn & 0x3ff), ++ bfd_put (32, abfd, LARCH_OP_ORI | (insn & 0x3ff), + contents + rel->r_offset); + rel->r_info = ELFNN_R_INFO (r_symndx, R_LARCH_TLS_LE_LO12); + } +@@ -4875,11 +4875,11 @@ loongarch_relax_tls_le (bfd *abfd, asection *sec, + /* Change rj to $tp. */ + insn_rj = 0x2 << 5; + /* Get rd register. */ +- insn_rd = insn & 0x1f; ++ insn_rd = LARCH_GET_RD(insn); + /* Write symbol offset. */ + symval <<= 10; + /* Writes the modified instruction. */ +- insn = insn & 0xffc00000; ++ insn = insn & LARCH_MK_ADDI_D; + insn = insn | symval | insn_rj | insn_rd; + bfd_put (32, abfd, insn, contents + rel->r_offset); + } +@@ -4894,7 +4894,7 @@ loongarch_relax_tls_le (bfd *abfd, asection *sec, + break; + + case R_LARCH_TLS_LE_LO12: +- bfd_put (32, abfd, LARCH_ORI | (insn & 0x1f), ++ bfd_put (32, abfd, LARCH_OP_ORI | LARCH_GET_RD(insn), + contents + rel->r_offset); + break; + +@@ -4940,7 +4940,7 @@ loongarch_relax_pcala_addi (bfd *abfd, asection *sec, asection *sym_sec, + Elf_Internal_Rela *rel_lo = rel_hi + 2; + uint32_t pca = bfd_get (32, abfd, contents + rel_hi->r_offset); + uint32_t add = bfd_get (32, abfd, contents + rel_lo->r_offset); +- uint32_t rd = pca & 0x1f; ++ uint32_t rd = LARCH_GET_RD(pca); + + /* This section's output_offset need to subtract the bytes of instructions + relaxed by the previous sections, so it needs to be updated beforehand. +@@ -4961,18 +4961,17 @@ loongarch_relax_pcala_addi (bfd *abfd, asection *sec, asection *sym_sec, + else if (symval < pc) + pc += (max_alignment > 4 ? max_alignment : 0); + +- const uint32_t addi_d = 0x02c00000; +- const uint32_t pcaddi = 0x18000000; ++ const uint32_t pcaddi = LARCH_OP_PCADDI; + + /* Is pcalau12i + addi.d insns? */ + if ((ELFNN_R_TYPE (rel_lo->r_info) != R_LARCH_PCALA_LO12) + || (ELFNN_R_TYPE ((rel_lo + 1)->r_info) != R_LARCH_RELAX) + || (ELFNN_R_TYPE ((rel_hi + 1)->r_info) != R_LARCH_RELAX) + || (rel_hi->r_offset + 4 != rel_lo->r_offset) +- || ((add & addi_d) != addi_d) ++ || !LARCH_INSN_ADDI_D(add) + /* Is pcalau12i $rd + addi.d $rd,$rd? */ +- || ((add & 0x1f) != rd) +- || (((add >> 5) & 0x1f) != rd) ++ || (LARCH_GET_RD(add) != rd) ++ || (LARCH_GET_RJ(add) != rd) + /* Can be relaxed to pcaddi? */ + || (symval & 0x3) /* 4 bytes align. */ + || ((bfd_signed_vma)(symval - pc) < (bfd_signed_vma)(int32_t)0xffe00000) +@@ -5005,7 +5004,7 @@ loongarch_relax_call36 (bfd *abfd, asection *sec, asection *sym_sec, + { + bfd_byte *contents = elf_section_data (sec)->this_hdr.contents; + uint32_t jirl = bfd_get (32, abfd, contents + rel->r_offset + 4); +- uint32_t rd = jirl & 0x1f; ++ uint32_t rd = LARCH_GET_RD(jirl); + + /* This section's output_offset need to subtract the bytes of instructions + relaxed by the previous sections, so it needs to be updated beforehand. +@@ -5026,11 +5025,10 @@ loongarch_relax_call36 (bfd *abfd, asection *sec, asection *sym_sec, + else if (symval < pc) + pc += (max_alignment > 4 ? max_alignment : 0); + +- const uint32_t jirl_opcode = 0x4c000000; + + /* Is pcalau12i + addi.d insns? */ + if ((ELFNN_R_TYPE ((rel + 1)->r_info) != R_LARCH_RELAX) +- || ((jirl & jirl_opcode) != jirl_opcode) ++ || !LARCH_INSN_JIRL(jirl) + || ((bfd_signed_vma)(symval - pc) < (bfd_signed_vma)(int32_t)0xf8000000) + || ((bfd_signed_vma)(symval - pc) > (bfd_signed_vma)(int32_t)0x7fffffc)) + return false; +@@ -5038,8 +5036,8 @@ loongarch_relax_call36 (bfd *abfd, asection *sec, asection *sym_sec, + /* Continue next relax trip. */ + *again = true; + +- const uint32_t bl = 0x54000000; +- const uint32_t b = 0x50000000; ++ const uint32_t bl = LARCH_OP_BL; ++ const uint32_t b = LARCH_OP_B; + + if (rd) + bfd_put (32, abfd, bl, contents + rel->r_offset); +@@ -5062,17 +5060,16 @@ loongarch_relax_pcala_ld (bfd *abfd, asection *sec, + Elf_Internal_Rela *rel_lo = rel_hi + 2; + uint32_t pca = bfd_get (32, abfd, contents + rel_hi->r_offset); + uint32_t ld = bfd_get (32, abfd, contents + rel_lo->r_offset); +- uint32_t rd = pca & 0x1f; +- const uint32_t ld_d = 0x28c00000; +- uint32_t addi_d = 0x02c00000; ++ uint32_t rd = LARCH_GET_RD(pca); ++ uint32_t addi_d = LARCH_OP_ADDI_D; + + if ((ELFNN_R_TYPE (rel_lo->r_info) != R_LARCH_GOT_PC_LO12) + || (ELFNN_R_TYPE ((rel_lo + 1)->r_info) != R_LARCH_RELAX) + || (ELFNN_R_TYPE ((rel_hi + 1)->r_info) != R_LARCH_RELAX) + || (rel_hi->r_offset + 4 != rel_lo->r_offset) +- || ((ld & 0x1f) != rd) +- || (((ld >> 5) & 0x1f) != rd) +- || ((ld & ld_d) != ld_d)) ++ || (LARCH_GET_RD(ld) != rd) ++ || (LARCH_GET_RJ(ld) != rd) ++ || !LARCH_INSN_LD_D(ld)) + return false; + + addi_d = addi_d | (rd << 5) | rd; +@@ -5165,7 +5162,7 @@ loongarch_relax_tls_ld_gd_desc (bfd *abfd, asection *sec, asection *sym_sec, + Elf_Internal_Rela *rel_lo = rel_hi + 2; + uint32_t pca = bfd_get (32, abfd, contents + rel_hi->r_offset); + uint32_t add = bfd_get (32, abfd, contents + rel_lo->r_offset); +- uint32_t rd = pca & 0x1f; ++ uint32_t rd = LARCH_GET_RD(pca); + + /* This section's output_offset need to subtract the bytes of instructions + relaxed by the previous sections, so it needs to be updated beforehand. +@@ -5186,8 +5183,7 @@ loongarch_relax_tls_ld_gd_desc (bfd *abfd, asection *sec, asection *sym_sec,
View file
_service:tar_scm:Add-support-for-ilp32-register-alias.patch
Added
@@ -0,0 +1,156 @@ +From 6a9c6951245b9b344ebb7ababd1e9f8192d8eccd Mon Sep 17 00:00:00 2001 +From: Lulu Cai <cailulu@loongson.cn> +Date: Mon, 30 Oct 2023 17:07:08 +0800 +Subject: PATCH 017/123 Add support for ilp32 register alias. + +--- + gas/config/tc-loongarch.c | 41 +++++++++++++++++--------------------- + include/opcode/loongarch.h | 8 ++++---- + opcodes/loongarch-dis.c | 4 ++-- + opcodes/loongarch-opc.c | 8 ++++---- + 4 files changed, 28 insertions(+), 33 deletions(-) + +diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c +index 49c70bf1..59232832 100644 +--- a/gas/config/tc-loongarch.c ++++ b/gas/config/tc-loongarch.c +@@ -303,6 +303,15 @@ loongarch_after_parse_args () + for (i = 0; i < ARRAY_SIZE (loongarch_r_normal_name); i++) + str_hash_insert (r_htab, loongarch_r_normal_namei, (void *) (i + 1), 0); + ++ /* Init ilp32/lp64 registers alias. */ ++ r_abi_names = loongarch_r_alias; ++ for (i = 0; i < ARRAY_SIZE (loongarch_r_alias); i++) ++ str_hash_insert (r_htab, loongarch_r_aliasi, (void *) (i + 1), ++ 0); ++ for (i = 0; i < ARRAY_SIZE (loongarch_r_alias_deprecated); i++) ++ str_hash_insert (r_deprecated_htab, loongarch_r_alias_deprecatedi, ++ (void *) (i + 1), 0); ++ + if (!cr_htab) + cr_htab = str_htab_create (), str_hash_insert (cr_htab, "", 0, 0); + +@@ -323,6 +332,15 @@ loongarch_after_parse_args () + str_hash_insert (f_htab, loongarch_f_normal_namei, (void *) (i + 1), + 0); + ++ /* Init float-ilp32/lp64 registers alias. */ ++ f_abi_names = loongarch_f_alias; ++ for (i = 0; i < ARRAY_SIZE (loongarch_f_alias); i++) ++ str_hash_insert (f_htab, loongarch_f_aliasi, ++ (void *) (i + 1), 0); ++ for (i = 0; i < ARRAY_SIZE (loongarch_f_alias_deprecated); i++) ++ str_hash_insert (f_deprecated_htab, loongarch_f_alias_deprecatedi, ++ (void *) (i + 1), 0); ++ + if (!fc_htab) + fc_htab = str_htab_create (), str_hash_insert (fc_htab, "", 0, 0); + +@@ -366,29 +384,6 @@ loongarch_after_parse_args () + 0); + } + +- /* Init lp64 registers alias. */ +- if (LARCH_opts.ase_lp64) +- { +- r_abi_names = loongarch_r_lp64_name; +- for (i = 0; i < ARRAY_SIZE (loongarch_r_lp64_name); i++) +- str_hash_insert (r_htab, loongarch_r_lp64_namei, (void *) (i + 1), +- 0); +- for (i = 0; i < ARRAY_SIZE (loongarch_r_lp64_name_deprecated); i++) +- str_hash_insert (r_deprecated_htab, loongarch_r_lp64_name_deprecatedi, +- (void *) (i + 1), 0); +- } +- +- /* Init float-lp64 registers alias */ +- if ((LARCH_opts.ase_sf || LARCH_opts.ase_df) && LARCH_opts.ase_lp64) +- { +- f_abi_names = loongarch_f_lp64_name; +- for (i = 0; i < ARRAY_SIZE (loongarch_f_lp64_name); i++) +- str_hash_insert (f_htab, loongarch_f_lp64_namei, +- (void *) (i + 1), 0); +- for (i = 0; i < ARRAY_SIZE (loongarch_f_lp64_name_deprecated); i++) +- str_hash_insert (f_deprecated_htab, loongarch_f_lp64_name_deprecatedi, +- (void *) (i + 1), 0); +- } + } + + const char * +diff --git a/include/opcode/loongarch.h b/include/opcode/loongarch.h +index f358ff42..da936f79 100644 +--- a/include/opcode/loongarch.h ++++ b/include/opcode/loongarch.h +@@ -189,11 +189,11 @@ dec2 : 1-90-9? + extern void loongarch_eliminate_adjacent_repeat_char (char *dest, char c); + + extern const char *const loongarch_r_normal_name32; +- extern const char *const loongarch_r_lp64_name32; +- extern const char *const loongarch_r_lp64_name_deprecated32; ++ extern const char *const loongarch_r_alias32; ++ extern const char *const loongarch_r_alias_deprecated32; + extern const char *const loongarch_f_normal_name32; +- extern const char *const loongarch_f_lp64_name32; +- extern const char *const loongarch_f_lp64_name_deprecated32; ++ extern const char *const loongarch_f_alias32; ++ extern const char *const loongarch_f_alias_deprecated32; + extern const char *const loongarch_fc_normal_name4; + extern const char *const loongarch_fc_numeric_name4; + extern const char *const loongarch_c_normal_name8; +diff --git a/opcodes/loongarch-dis.c b/opcodes/loongarch-dis.c +index 1e711f27..969ea28f 100644 +--- a/opcodes/loongarch-dis.c ++++ b/opcodes/loongarch-dis.c +@@ -82,8 +82,8 @@ set_default_loongarch_dis_options (void) + LARCH_opts.ase_lvz = 1; + LARCH_opts.ase_lbt = 1; + +- loongarch_r_disname = loongarch_r_lp64_name; +- loongarch_f_disname = loongarch_f_lp64_name; ++ loongarch_r_disname = loongarch_r_alias; ++ loongarch_f_disname = loongarch_f_alias; + loongarch_fc_disname = loongarch_fc_normal_name; + loongarch_c_disname = loongarch_c_normal_name; + loongarch_cr_disname = loongarch_cr_normal_name; +diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c +index 5cd1411a..15c7da63 100644 +--- a/opcodes/loongarch-opc.c ++++ b/opcodes/loongarch-opc.c +@@ -41,7 +41,7 @@ const char *const loongarch_r_normal_name32 = + "$r24", "$r25", "$r26", "$r27", "$r28", "$r29", "$r30", "$r31", + }; + +-const char *const loongarch_r_lp64_name32 = ++const char *const loongarch_r_alias32 = + { + "$zero", "$ra", "$tp", "$sp", "$a0", "$a1", "$a2", "$a3", + "$a4", "$a5", "$a6", "$a7", "$t0", "$t1", "$t2", "$t3", +@@ -49,7 +49,7 @@ const char *const loongarch_r_lp64_name32 = + "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7", "$s8", + }; + +-const char *const loongarch_r_lp64_name_deprecated32 = ++const char *const loongarch_r_alias_deprecated32 = + { + "", "", "", "", "$v0", "$v1", "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "$x", "", "", "", "", "", "", "", "", "", "", +@@ -63,7 +63,7 @@ const char *const loongarch_f_normal_name32 = + "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", + }; + +-const char *const loongarch_f_lp64_name32 = ++const char *const loongarch_f_alias32 = + { + "$fa0", "$fa1", "$fa2", "$fa3", "$fa4", "$fa5", "$fa6", "$fa7", + "$ft0", "$ft1", "$ft2", "$ft3", "$ft4", "$ft5", "$ft6", "$ft7", +@@ -71,7 +71,7 @@ const char *const loongarch_f_lp64_name32 = + "$fs0", "$fs1", "$fs2", "$fs3", "$fs4", "$fs5", "$fs6", "$fs7", + }; + +-const char *const loongarch_f_lp64_name_deprecated32 = ++const char *const loongarch_f_alias_deprecated32 = + { + "$fv0", "$fv1", "", "", "", "", "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", +-- +2.33.0 +
View file
_service:tar_scm:Add-support-for-pcaddi-rd-symbol.patch
Added
@@ -0,0 +1,446 @@ +From 91fcca79e66c426791c9055156644e96024e6599 Mon Sep 17 00:00:00 2001 +From: mengqinggang <mengqinggang@loongson.cn> +Date: Mon, 18 Sep 2023 18:00:21 +0800 +Subject: PATCH 010/123 Add support for "pcaddi rd, symbol" + +Add a macro pcaddi instruction to support "pcaddi rd, symbol". + +pcaddi has a 20-bit signed immediate, it can address a +/- 2MB pc relative +address, and the address should be 4-byte aligned. +--- + bfd/elfxx-loongarch.c | 4 +- + gas/testsuite/gas/loongarch/imm_ins.d | 137 ++++++++++++----------- + gas/testsuite/gas/loongarch/imm_ins_32.d | 91 +++++++-------- + gas/testsuite/gas/loongarch/imm_op.d | 82 +++++++------- + gas/testsuite/gas/loongarch/imm_op.s | 2 +- + gas/testsuite/gas/loongarch/pcaddi.d | 13 +++ + gas/testsuite/gas/loongarch/pcaddi.s | 4 + + opcodes/loongarch-opc.c | 2 +- + 8 files changed, 177 insertions(+), 158 deletions(-) + create mode 100644 gas/testsuite/gas/loongarch/pcaddi.d + create mode 100644 gas/testsuite/gas/loongarch/pcaddi.s + +diff --git a/bfd/elfxx-loongarch.c b/bfd/elfxx-loongarch.c +index 16a2b2fc..fd9507ce 100644 +--- a/bfd/elfxx-loongarch.c ++++ b/bfd/elfxx-loongarch.c +@@ -1415,7 +1415,7 @@ static loongarch_reloc_howto_type loongarch_howto_table = + NULL, /* adjust_reloc_bits. */ + NULL), /* larch_reloc_type_name. */ + +- /* pcala_hi20 + pcala_lo12 relaxed to pcrel20_s2. */ ++ /* For pcaddi and pcala_hi20 + pcala_lo12 can relax to pcrel_20. */ + LOONGARCH_HOWTO (R_LARCH_PCREL20_S2, /* type (103). */ + 2, /* rightshift. */ + 4, /* size. */ +@@ -1431,7 +1431,7 @@ static loongarch_reloc_howto_type loongarch_howto_table = + false, /* pcrel_offset. */ + BFD_RELOC_LARCH_PCREL20_S2, /* bfd_reloc_code_real_type. */ + reloc_sign_bits, /* adjust_reloc_bits. */ +- NULL), /* larch_reloc_type_name. */ ++ "pcrel_20"), /* larch_reloc_type_name. */ + + /* Canonical Frame Address. */ + LOONGARCH_HOWTO (R_LARCH_CFA, /* type (104). */ +diff --git a/gas/testsuite/gas/loongarch/imm_ins.d b/gas/testsuite/gas/loongarch/imm_ins.d +index f00110cd..b54df873 100644 +--- a/gas/testsuite/gas/loongarch/imm_ins.d ++++ b/gas/testsuite/gas/loongarch/imm_ins.d +@@ -7,74 +7,75 @@ + + Disassembly of section .text: + +-00000000.* <.text>: +- +0: +03848c0c +li.w +\$t0, +0x123 +- +4: +15ffe00d +lu12i.w +\$t1, +-256 +- +8: +16001fed +lu32i.d +\$t1, +255 +- +c: +02bffc0e +li.w +\$t2, +-1 +- +10: +1601ffee +lu32i.d +\$t2, +4095 +- +14: +0004b58b +alsl.w +\$a7, +\$t0, +\$t1, +0x2 +- +18: +0006b58b +alsl.wu +\$a7, +\$t0, +\$t1, +0x2 +- +1c: +0009358b +bytepick.w +\$a7, +\$t0, +\$t1, +0x2 +- +20: +000d358b +bytepick.d +\$a7, +\$t0, +\$t1, +0x2 ++ *0000000000000000 <.text>: ++ +0: +03848c0c +li.w +\$t0, 0x123 ++ +4: +15ffe00d +lu12i.w +\$t1, -256 ++ +8: +16001fed +lu32i.d +\$t1, 255 ++ +c: +02bffc0e +li.w +\$t2, -1 ++ +10: +1601ffee +lu32i.d +\$t2, 4095 ++ +14: +0004b58b +alsl.w +\$a7, \$t0, \$t1, 0x2 ++ +18: +0006b58b +alsl.wu +\$a7, \$t0, \$t1, 0x2 ++ +1c: +0009358b +bytepick.w +\$a7, \$t0, \$t1, 0x2 ++ +20: +000d358b +bytepick.d +\$a7, \$t0, \$t1, 0x2 + +24: +002a0002 +break +0x2 + +28: +002a8002 +dbcl +0x2 + +2c: +002b0002 +syscall +0x2 +- +30: +002cb58b +alsl.d +\$a7, +\$t0, +\$t1, +0x2 +- +34: +0040898b +slli.w +\$a7, +\$t0, +0x2 +- +38: +0041098b +slli.d +\$a7, +\$t0, +0x2 +- +3c: +0044898b +srli.w +\$a7, +\$t0, +0x2 +- +40: +004509ac +srli.d +\$t0, +\$t1, +0x2 +- +44: +004889ac +srai.w +\$t0, +\$t1, +0x2 +- +48: +004909ac +srai.d +\$t0, +\$t1, +0x2 +- +4c: +006209ac +bstrins.w +\$t0, +\$t1, +0x2, +0x2 +- +50: +008209ac +bstrins.d +\$t0, +\$t1, +0x2, +0x2 +- +54: +00c209ac +bstrpick.d +\$t0, +\$t1, +0x2, +0x2 +- +58: +00c209ac +bstrpick.d +\$t0, +\$t1, +0x2, +0x2 +- +5c: +02048dac +slti +\$t0, +\$t1, +291 +- +60: +02448dac +sltui +\$t0, +\$t1, +291 +- +64: +02848dac +addi.w +\$t0, +\$t1, +291 +- +68: +02c48dac +addi.d +\$t0, +\$t1, +291 +- +6c: +03048dac +lu52i.d +\$t0, +\$t1, +291 +- +70: +034009ac +andi +\$t0, +\$t1, +0x2 +- +74: +038009ac +ori +\$t0, +\$t1, +0x2 +- +78: +03c009ac +xori +\$t0, +\$t1, +0x2 +- +7c: +100009ac +addu16i.d +\$t0, +\$t1, +2 +- +80: +1400246c +lu12i.w +\$t0, +291 +- +84: +1600246c +lu32i.d +\$t0, +291 +- +88: +1800246c +pcaddi +\$t0, +291 +- +8c: +1a00246c +pcalau12i +\$t0, +291 +- +90: +1c00246c +pcaddu12i +\$t0, +291 +- +94: +1e00246c +pcaddu18i +\$t0, +291 +- +98: +04048c0c +csrrd +\$t0, +0x123 +- +9c: +04048c2c +csrwr +\$t0, +0x123 +- +a0: +040009ac +csrxchg +\$t0, +\$t1, +0x2 +- +a4: +060009a2 +cacop +0x2, +\$t1, +2 +- +a8: +064009ac +lddir +\$t0, +\$t1, +0x2 +- +ac: +06440980 +ldpte +\$t0, +0x2 +- +b0: +0649b9a2 +invtlb +0x2, +\$t1, +\$t2 +- +b4: +200101ac +ll.w +\$t0, +\$t1, +256 +- +b8: +210101ac +sc.w +\$t0, +\$t1, +256 +- +bc: +220101ac +ll.d +\$t0, +\$t1, +256 +- +c0: +230101ac +sc.d +\$t0, +\$t1, +256 +- +c4: +240101ac +ldptr.w +\$t0, +\$t1, +256 +- +c8: +250101ac +stptr.w +\$t0, +\$t1, +256 +- +cc: +260101ac +ldptr.d +\$t0, +\$t1, +256 +- +d0: +270101ac +stptr.d +\$t0, +\$t1, +256 +- +d4: +280401ac +ld.b +\$t0, +\$t1, +256 +- +d8: +284401ac +ld.h +\$t0, +\$t1, +256 +- +dc: +288401ac +ld.w +\$t0, +\$t1, +256 +- +e0: +28c401ac +ld.d +\$t0, +\$t1, +256 +- +e4: +290401ac +st.b +\$t0, +\$t1, +256 +- +e8: +294401ac +st.h +\$t0, +\$t1, +256 +- +ec: +298401ac +st.w +\$t0, +\$t1, +256 +- +f0: +29c401ac +st.d +\$t0, +\$t1, +256 +- +f4: +2a0401ac +ld.bu +\$t0, +\$t1, +256 +- +f8: +2a4401ac +ld.hu +\$t0, +\$t1, +256 +- +fc: +2a8401ac +ld.wu +\$t0, +\$t1, +256 +- +100: +2ac401a2 +preld +0x2, +\$t1, +256 +- +104: +382c39a2 +preldx +0x2, +\$t1, +\$t2 +- +108: +2b048d8a +fld.s +\$ft2, +\$t0, +291 +- +10c: +2b448d8a +fst.s +\$ft2, +\$t0, +291 +- +110: +2b848d8a +fld.d +\$ft2, +\$t0, +291 +- +114: +2bc48d8a +fst.d +\$ft2, +\$t0, +291 ++ +30: +002cb58b +alsl.d +\$a7, \$t0, \$t1, 0x2 ++ +34: +0040898b +slli.w +\$a7, \$t0, 0x2 ++ +38: +0041098b +slli.d +\$a7, \$t0, 0x2 ++ +3c: +0044898b +srli.w +\$a7, \$t0, 0x2 ++ +40: +004509ac +srli.d +\$t0, \$t1, 0x2 ++ +44: +004889ac +srai.w +\$t0, \$t1, 0x2 ++ +48: +004909ac +srai.d +\$t0, \$t1, 0x2 ++ +4c: +006209ac +bstrins.w +\$t0, \$t1, 0x2, 0x2 ++ +50: +008209ac +bstrins.d +\$t0, \$t1, 0x2, 0x2 ++ +54: +00c209ac +bstrpick.d +\$t0, \$t1, 0x2, 0x2 ++ +58: +00c209ac +bstrpick.d +\$t0, \$t1, 0x2, 0x2 ++ +5c: +02048dac +slti +\$t0, \$t1, 291 ++ +60: +02448dac +sltui +\$t0, \$t1, 291 ++ +64: +02848dac +addi.w +\$t0, \$t1, 291 ++ +68: +02c48dac +addi.d +\$t0, \$t1, 291 ++ +6c: +03048dac +lu52i.d +\$t0, \$t1, 291 ++ +70: +034009ac +andi +\$t0, \$t1, 0x2 ++ +74: +038009ac +ori +\$t0, \$t1, 0x2 ++ +78: +03c009ac +xori +\$t0, \$t1, 0x2 ++ +7c: +100009ac +addu16i.d +\$t0, \$t1, 2 ++ +80: +1400246c +lu12i.w +\$t0, 291 ++ +84: +1600246c +lu32i.d +\$t0, 291 ++ +88: +1800000c +pcaddi +\$t0, 0 ++ +88: R_LARCH_PCREL20_S2 +\*ABS\*\+0x123 ++ +8c: +1a00246c +pcalau12i +\$t0, 291 ++ +90: +1c00246c +pcaddu12i +\$t0, 291 ++ +94: +1e00246c +pcaddu18i +\$t0, 291 ++ +98: +04048c0c +csrrd +\$t0, 0x123 ++ +9c: +04048c2c +csrwr +\$t0, 0x123 ++ +a0: +040009ac +csrxchg +\$t0, \$t1, 0x2 ++ +a4: +060009a2 +cacop +0x2, \$t1, 2 ++ +a8: +064009ac +lddir +\$t0, \$t1, 0x2 ++ +ac: +06440980 +ldpte +\$t0, 0x2 ++ +b0: +0649b9a2 +invtlb +0x2, \$t1, \$t2 ++ +b4: +200101ac +ll.w +\$t0, \$t1, 256 ++ +b8: +210101ac +sc.w +\$t0, \$t1, 256 ++ +bc: +220101ac +ll.d +\$t0, \$t1, 256 ++ +c0: +230101ac +sc.d +\$t0, \$t1, 256 ++ +c4: +240101ac +ldptr.w +\$t0, \$t1, 256 ++ +c8: +250101ac +stptr.w +\$t0, \$t1, 256 ++ +cc: +260101ac +ldptr.d +\$t0, \$t1, 256 ++ +d0: +270101ac +stptr.d +\$t0, \$t1, 256 ++ +d4: +280401ac +ld.b +\$t0, \$t1, 256 ++ +d8: +284401ac +ld.h +\$t0, \$t1, 256 ++ +dc: +288401ac +ld.w +\$t0, \$t1, 256 ++ +e0: +28c401ac +ld.d +\$t0, \$t1, 256 ++ +e4: +290401ac +st.b +\$t0, \$t1, 256 ++ +e8: +294401ac +st.h +\$t0, \$t1, 256 ++ +ec: +298401ac +st.w +\$t0, \$t1, 256 ++ +f0: +29c401ac +st.d +\$t0, \$t1, 256 ++ +f4: +2a0401ac +ld.bu +\$t0, \$t1, 256 ++ +f8: +2a4401ac +ld.hu +\$t0, \$t1, 256 ++ +fc: +2a8401ac +ld.wu +\$t0, \$t1, 256 ++ +100: +2ac401a2 +preld +0x2, \$t1, 256 ++ +104: +382c39a2 +preldx +0x2, \$t1, \$t2 ++ +108: +2b048d8a +fld.s +\$ft2, \$t0, 291 ++ +10c: +2b448d8a +fst.s +\$ft2, \$t0, 291 ++ +110: +2b848d8a +fld.d +\$ft2, \$t0, 291 ++ +114: +2bc48d8a +fst.d +\$ft2, \$t0, 291 +diff --git a/gas/testsuite/gas/loongarch/imm_ins_32.d b/gas/testsuite/gas/loongarch/imm_ins_32.d +index dc2eeb9e..3662fdda 100644 +--- a/gas/testsuite/gas/loongarch/imm_ins_32.d ++++ b/gas/testsuite/gas/loongarch/imm_ins_32.d +@@ -7,51 +7,52 @@ + + Disassembly of section .text:
View file
_service:tar_scm:Add-testcase-for-generation-of-32-64_PCREL.patch
Added
@@ -0,0 +1,247 @@ +From aa0064d1240e10856f352516f6097f3e75c5e463 Mon Sep 17 00:00:00 2001 +From: cailulu <cailulu@loongson.cn> +Date: Fri, 1 Sep 2023 11:09:01 +0800 +Subject: PATCH 007/123 Add testcase for generation of 32/64_PCREL. + +--- + gas/testsuite/gas/loongarch/pcrel_norelax.d | 56 +++++++++++++++++++ + gas/testsuite/gas/loongarch/pcrel_norelax.s | 42 +++++++++++++++ + gas/testsuite/gas/loongarch/pcrel_relax.d | 60 +++++++++++++++++++++ + gas/testsuite/gas/loongarch/pcrel_relax.s | 46 ++++++++++++++++ + 4 files changed, 204 insertions(+) + create mode 100644 gas/testsuite/gas/loongarch/pcrel_norelax.d + create mode 100644 gas/testsuite/gas/loongarch/pcrel_norelax.s + create mode 100644 gas/testsuite/gas/loongarch/pcrel_relax.d + create mode 100644 gas/testsuite/gas/loongarch/pcrel_relax.s + +diff --git a/gas/testsuite/gas/loongarch/pcrel_norelax.d b/gas/testsuite/gas/loongarch/pcrel_norelax.d +new file mode 100644 +index 00000000..842c8d48 +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/pcrel_norelax.d +@@ -0,0 +1,56 @@ ++#as: -mno-relax ++#objdump: -Dr ++ ++.*: +file format .* ++ ++ ++Disassembly of section .text: ++ ++00000000.* <.L1>: ++ +... ++ +0: +R_LARCH_32_PCREL +.L3 ++ +4: +R_LARCH_32_PCREL +.L3\+0x4 ++ ++0*00000008 +<.L2>: ++ +... ++ +8: +R_LARCH_64_PCREL +.L3 ++ +10: +R_LARCH_64_PCREL +.L3\+0x8 ++ ++Disassembly +of +section +sx: ++ ++0*00000000 +<.L3>: ++ +0: +fffffff4 +.word +0xfffffff4 ++ +4: +fffffff4 +.word +0xfffffff4 ++ +8: +ffffffff +.word +0xffffffff ++ ++0*0000000c +<.L4>: ++ +... ++ +c: +R_LARCH_ADD32 +.L4 ++ +c: +R_LARCH_SUB32 +.L5 ++ +10: +R_LARCH_ADD64 +.L4 ++ +10: +R_LARCH_SUB64 +.L5 ++ ++Disassembly +of +section +sy: ++ ++0*00000000 +<.L5>: ++ +... ++ +0: +R_LARCH_32_PCREL +.L1 ++ +4: +R_LARCH_32_PCREL +.L2\+0x4 ++ +8: +R_LARCH_64_PCREL +.L1\+0x8 ++ +10: +R_LARCH_64_PCREL +.L2\+0x10 ++ ++Disassembly +of +section +sz: ++ ++0*00000000 +<sz>: ++ +0: +fffffff8 +.word +0xfffffff8 ++ +4: +fffffff4 +.word +0xfffffff4 ++ +8: +00000000 +.word +0x00000000 ++ +8: +R_LARCH_ADD32 +.L2 ++ +8: +R_LARCH_SUB32 +.L3 ++ +c: +fffffff8 +.word +0xfffffff8 ++ +10: +ffffffff +.word +0xffffffff ++ +14: +fffffff4 +.word +0xfffffff4 ++ +18: +ffffffff +.word +0xffffffff ++ +... ++ +1c: +R_LARCH_ADD64 +.L2 ++ +1c: +R_LARCH_SUB64 +.L3 +diff --git a/gas/testsuite/gas/loongarch/pcrel_norelax.s b/gas/testsuite/gas/loongarch/pcrel_norelax.s +new file mode 100644 +index 00000000..09527f14 +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/pcrel_norelax.s +@@ -0,0 +1,42 @@ ++ .section .text ++.L1: ++ # 32_pcrel ++ .4byte .L3-.L1 ++ .4byte .L3-.L1 ++.L2: ++ # 64_pcrel ++ .8byte .L3-.L2 ++ .8byte .L3-.L2 ++ ++ .section sx ++.L3: ++ # no relocation ++ .4byte .L3-.L4 ++ .8byte .L3-.L4 ++.L4: ++ # add32+sub32 ++ .4byte .L4-.L5 ++ # add64+sub64 ++ .8byte .L4-.L5 ++ ++ .section sy ++.L5: ++ # 32_pcrel ++ .4byte .L1-.L5 ++ .4byte .L2-.L5 ++ # 64_pcrel ++ .8byte .L1-.L5 ++ .8byte .L2-.L5 ++ ++ .section sz ++ # no relocation ++ .4byte .L1-.L2 ++ .4byte .L3-.L4 ++ # add32+sub32 ++ .4byte .L2-.L3 ++ ++ # no relocation ++ .8byte .L1-.L2 ++ .8byte .L3-.L4 ++ # add64+sub64 ++ .8byte .L2-.L3 +diff --git a/gas/testsuite/gas/loongarch/pcrel_relax.d b/gas/testsuite/gas/loongarch/pcrel_relax.d +new file mode 100644 +index 00000000..d6f87525 +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/pcrel_relax.d +@@ -0,0 +1,60 @@ ++#as: ++#objdump: -Dr ++ ++.*: +file format .* ++ ++ ++Disassembly of section .text: ++ ++00000000.* <.L1>: ++ +... ++ +0: +R_LARCH_32_PCREL +.L3 ++ +4: +R_LARCH_ADD32 +.L3 ++ +4: +R_LARCH_SUB32 +.L1 ++ ++0*00000008 +<.L2>: ++ +... ++ +8: +R_LARCH_64_PCREL +.L3 ++ +10: +R_LARCH_ADD64 +.L3 ++ +10: +R_LARCH_SUB64 +.L2 ++ ++Disassembly +of +section +sx: ++ ++0*00000000 +<.L3>: ++ +0: +fffffff4 +.word +0xfffffff4 ++ +4: +fffffff4 +.word +0xfffffff4 ++ +8: +ffffffff +.word +0xffffffff ++ ++0*0000000c +<.L4>: ++ +... ++ +c: +R_LARCH_ADD32 +.L4 ++ +c: +R_LARCH_SUB32 +.L5 ++ +10: +R_LARCH_ADD64 +.L4 ++ +10: +R_LARCH_SUB64 +.L5 ++ ++Disassembly +of +section +sy: ++ ++0*00000000 +<.L5>: ++ +... ++ +0: +R_LARCH_32_PCREL +.L1 ++ +4: +R_LARCH_32_PCREL +.L3\+0x4 ++ +8: +R_LARCH_64_PCREL +.L1\+0x8 ++ +10: +R_LARCH_64_PCREL +.L3\+0x10 ++ ++Disassembly +of +section +sz: ++ ++0*00000000 +<sz>: ++ +0: +00000000 +.word +0x00000000 ++ +0: +R_LARCH_ADD32 +.L1 ++ +0: +R_LARCH_SUB32 +.L2 ++ +4: +fffffff4 +.word +0xfffffff4 ++ +... ++ +8: +R_LARCH_ADD32 +.L3 ++ +8: +R_LARCH_SUB32 +.L5 ++ +c: +R_LARCH_ADD64 +.L1 ++ +c: +R_LARCH_SUB64 +.L2 ++ +14: +fffffff4 +.word +0xfffffff4 ++ +18: +ffffffff +.word +0xffffffff ++ +... ++ +1c: +R_LARCH_ADD64 +.L3 ++ +1c: +R_LARCH_SUB64 +.L5 +diff --git a/gas/testsuite/gas/loongarch/pcrel_relax.s b/gas/testsuite/gas/loongarch/pcrel_relax.s +new file mode 100644 +index 00000000..ded275fa +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/pcrel_relax.s +@@ -0,0 +1,46 @@ ++ .section .text
View file
_service:tar_scm:Add-testsuits-for-new-assembler-option-of-mthin-add-.patch
Added
@@ -0,0 +1,307 @@ +From 7904eb84e70187141d105971ff38de06215102cb Mon Sep 17 00:00:00 2001 +From: cailulu <cailulu@loongson.cn> +Date: Thu, 28 Sep 2023 16:01:53 +0800 +Subject: PATCH 012/123 Add testsuits for new assembler option of + mthin-add-sub. + +--- + gas/testsuite/gas/loongarch/no_thin_add_sub.d | 66 +++++++++++++++++++ + gas/testsuite/gas/loongarch/no_thin_add_sub.s | 44 +++++++++++++ + ...pcrel_norelax.d => thin_add_sub_norelax.d} | 25 ++++--- + ...pcrel_norelax.s => thin_add_sub_norelax.s} | 8 +-- + .../{pcrel_relax.d => thin_add_sub_relax.d} | 12 ++-- + .../{pcrel_relax.s => thin_add_sub_relax.s} | 0 + 6 files changed, 131 insertions(+), 24 deletions(-) + create mode 100644 gas/testsuite/gas/loongarch/no_thin_add_sub.d + create mode 100644 gas/testsuite/gas/loongarch/no_thin_add_sub.s + rename gas/testsuite/gas/loongarch/{pcrel_norelax.d => thin_add_sub_norelax.d} (75%) + rename gas/testsuite/gas/loongarch/{pcrel_norelax.s => thin_add_sub_norelax.s} (87%) + rename gas/testsuite/gas/loongarch/{pcrel_relax.d => thin_add_sub_relax.d} (91%) + rename gas/testsuite/gas/loongarch/{pcrel_relax.s => thin_add_sub_relax.s} (100%) + +diff --git a/gas/testsuite/gas/loongarch/no_thin_add_sub.d b/gas/testsuite/gas/loongarch/no_thin_add_sub.d +new file mode 100644 +index 00000000..614aca71 +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/no_thin_add_sub.d +@@ -0,0 +1,66 @@ ++#as: ++#objdump: -Dr ++ ++.*: +file format .* ++ ++ ++Disassembly of section .text: ++ ++00000000.* <.L1>: ++ +... ++ +0: +R_LARCH_ADD32 +.L3 ++ +0: +R_LARCH_SUB32 +.L1 ++ +4: +R_LARCH_ADD32 +.L3 ++ +4: +R_LARCH_SUB32 +.L1 ++ ++0*00000008 +<.L2>: ++ +... ++ +8: +R_LARCH_ADD64 +.L3 ++ +8: +R_LARCH_SUB64 +.L2 ++ +10: +R_LARCH_ADD64 +.L3 ++ +10: +R_LARCH_SUB64 +.L2 ++ ++Disassembly +of +section +sx: ++ ++0*00000000 +<.L3>: ++ +0: +fffffff4 +.word +0xfffffff4 ++ +4: +fffffff4 +.word +0xfffffff4 ++ +8: +ffffffff +.word +0xffffffff ++ ++0*0000000c +<.L4>: ++ +... ++ +c: +R_LARCH_ADD32 +.L4 ++ +c: +R_LARCH_SUB32 +.L5 ++ +10: +R_LARCH_ADD64 +.L4 ++ +10: +R_LARCH_SUB64 +.L5 ++ ++Disassembly +of +section +sy: ++ ++0*00000000 +<.L5>: ++ +... ++ +0: +R_LARCH_ADD32 +.L1 ++ +0: +R_LARCH_SUB32 +.L5 ++ +4: +R_LARCH_ADD32 +.L3 ++ +4: +R_LARCH_SUB32 +.L5 ++ +8: +R_LARCH_ADD64 +.L1 ++ +8: +R_LARCH_SUB64 +.L5 ++ +10: +R_LARCH_ADD64 +.L3 ++ +10: +R_LARCH_SUB64 +.L5 ++ ++Disassembly +of +section +sz: ++ ++0*00000000 +<sz>: ++ +0: +00000000 +.word +0x00000000 ++ +0: +R_LARCH_ADD32 +.L1 ++ +0: +R_LARCH_SUB32 +.L2 ++ +4: +fffffff4 +.word +0xfffffff4 ++ +... ++ +8: +R_LARCH_ADD32 +.L3 ++ +8: +R_LARCH_SUB32 +.L5 ++ +c: +R_LARCH_ADD64 +.L1 ++ +c: +R_LARCH_SUB64 +.L2 ++ +14: +fffffff4 +.word +0xfffffff4 ++ +18: +ffffffff +.word +0xffffffff ++ +... ++ +1c: +R_LARCH_ADD64 +.L3 ++ +1c: +R_LARCH_SUB64 +.L5 +diff --git a/gas/testsuite/gas/loongarch/no_thin_add_sub.s b/gas/testsuite/gas/loongarch/no_thin_add_sub.s +new file mode 100644 +index 00000000..c6801689 +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/no_thin_add_sub.s +@@ -0,0 +1,44 @@ ++ .section .text ++.L1: ++ # add32+sub32 ++ .4byte .L3-.L1 ++ .4byte .L3-.L1 ++.L2: ++ # add64+sub64 ++ .8byte .L3-.L2 ++ .8byte .L3-.L2 ++ ++ .section sx ++.L3: ++ # no relocation ++ .4byte .L3-.L4 ++ .8byte .L3-.L4 ++.L4: ++ # add32+sub32 ++ .4byte .L4-.L5 ++ # add64+sub64 ++ .8byte .L4-.L5 ++ ++ .section sy ++.L5: ++ # add32+sub32 ++ .4byte .L1-.L5 ++ .4byte .L3-.L5 ++ # add64+sub64 ++ .8byte .L1-.L5 ++ .8byte .L3-.L5 ++ ++ .section sz ++ # add32+sub32 ++ .4byte .L1-.L2 ++ # no relocation ++ .4byte .L3-.L4 ++ # add32+sub32 ++ .4byte .L3-.L5 ++ ++ # add64+sub64 ++ .8byte .L1-.L2 ++ # no relocation ++ .8byte .L3-.L4 ++ # add64+sub64 ++ .8byte .L3-.L5 +diff --git a/gas/testsuite/gas/loongarch/pcrel_norelax.d b/gas/testsuite/gas/loongarch/thin_add_sub_norelax.d +similarity index 75% +rename from gas/testsuite/gas/loongarch/pcrel_norelax.d +rename to gas/testsuite/gas/loongarch/thin_add_sub_norelax.d +index 842c8d48..702093b6 100644 +--- a/gas/testsuite/gas/loongarch/pcrel_norelax.d ++++ b/gas/testsuite/gas/loongarch/thin_add_sub_norelax.d +@@ -1,4 +1,4 @@ +-#as: -mno-relax ++#as: -mthin-add-sub -mno-relax + #objdump: -Dr + + .*: +file format .* +@@ -10,20 +10,17 @@ Disassembly of section .text: + +... + +0: +R_LARCH_32_PCREL +.L3 + +4: +R_LARCH_32_PCREL +.L3\+0x4 +- +-0*00000008 +<.L2>: +- +... + +8: +R_LARCH_64_PCREL +.L3 + +10: +R_LARCH_64_PCREL +.L3\+0x8 + + Disassembly +of +section +sx: + +-0*00000000 +<.L3>: ++0*00000000 +<.L3>: + +0: +fffffff4 +.word +0xfffffff4 + +4: +fffffff4 +.word +0xfffffff4 + +8: +ffffffff +.word +0xffffffff + +-0*0000000c +<.L4>: ++0*0000000c +<.L4>: + +... + +c: +R_LARCH_ADD32 +.L4 + +c: +R_LARCH_SUB32 +.L5 +@@ -32,25 +29,25 @@ Disassembly +of +section +sx: + + Disassembly +of +section +sy: + +-0*00000000 +<.L5>: ++0*00000000 +<.L5>: + +... + +0: +R_LARCH_32_PCREL +.L1 +- +4: +R_LARCH_32_PCREL +.L2\+0x4 ++ +4: +R_LARCH_32_PCREL +.L3\+0x4 + +8: +R_LARCH_64_PCREL +.L1\+0x8 +- +10: +R_LARCH_64_PCREL +.L2\+0x10 ++ +10: +R_LARCH_64_PCREL +.L3\+0x10 + + Disassembly +of +section +sz: + +-0*00000000 +<sz>: ++0*00000000 +<sz>: + +0: +fffffff8 +.word +0xfffffff8 + +4: +fffffff4 +.word +0xfffffff4
View file
_service:tar_scm:Avoid-unused-space-in-.rela.dyn-if-sec-was-discarded.patch
Added
@@ -0,0 +1,102 @@ +From 79505ef8b8ccd844aee06cab4aec2404fb5e4475 Mon Sep 17 00:00:00 2001 +From: Jinyang He <hejinyang@loongson.cn> +Date: Fri, 15 Sep 2023 11:52:14 +0800 +Subject: PATCH 060/123 Avoid unused space in .rela.dyn if sec was discarded + +The relsec size is still increased although sec is discarded, which +cause a lot of unused space allocated. Avoid size increased if sec +was discarded. + +bfd/ChangeLog: + + * bfd/elfnn-loongarch.c: (allocate_dynrelocs): Do not increase + sreloc size when discarded_section. + +ld/ChangeLog: + + * ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp: Add test. + * ld/testsuite/ld-loongarch-elf/pie_discard.d: New test. + * ld/testsuite/ld-loongarch-elf/pie_discard.s: New test. + * ld/testsuite/ld-loongarch-elf/pie_discard.t: New test. +--- + bfd/elfnn-loongarch.c | 2 ++ + ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp | 1 + + ld/testsuite/ld-loongarch-elf/pie_discard.d | 10 ++++++++++ + ld/testsuite/ld-loongarch-elf/pie_discard.s | 9 +++++++++ + ld/testsuite/ld-loongarch-elf/pie_discard.t | 9 +++++++++ + 5 files changed, 31 insertions(+) + create mode 100644 ld/testsuite/ld-loongarch-elf/pie_discard.d + create mode 100644 ld/testsuite/ld-loongarch-elf/pie_discard.s + create mode 100644 ld/testsuite/ld-loongarch-elf/pie_discard.t + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index 2e72fe5c..1693ad7e 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -1368,6 +1368,8 @@ allocate_dynrelocs (struct elf_link_hash_entry *h, void *inf) + + for (p = h->dyn_relocs; p != NULL; p = p->next) + { ++ if (discarded_section (p->sec)) ++ continue; + asection *sreloc = elf_section_data (p->sec)->sreloc; + sreloc->size += p->count * sizeof (ElfNN_External_Rela); + } +diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp +index 7fc43d41..b3029e53 100644 +--- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp ++++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp +@@ -147,3 +147,4 @@ run_dump_test "underflow_b16" + run_dump_test "underflow_b21" + run_dump_test "underflow_b26" + run_dump_test "underflow_pcrel20" ++run_dump_test "pie_discard" +diff --git a/ld/testsuite/ld-loongarch-elf/pie_discard.d b/ld/testsuite/ld-loongarch-elf/pie_discard.d +new file mode 100644 +index 00000000..7b863091 +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/pie_discard.d +@@ -0,0 +1,10 @@ ++#source: pie_discard.s ++#ld: -pie -e 0 -T pie_discard.t ++#readelf: -rW ++ ++#... ++Relocation section '\.rela\.dyn' .* 1 .* ++#... ++.*R_LARCH_RELATIVE.* ++#pass ++ +diff --git a/ld/testsuite/ld-loongarch-elf/pie_discard.s b/ld/testsuite/ld-loongarch-elf/pie_discard.s +new file mode 100644 +index 00000000..82b88fc1 +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/pie_discard.s +@@ -0,0 +1,9 @@ ++ .text ++ .global sym ++sym: nop ++ ++ .section .data,"aw" ++ .dword sym ++ ++ .section .discard,"aw" ++ .dword sym +diff --git a/ld/testsuite/ld-loongarch-elf/pie_discard.t b/ld/testsuite/ld-loongarch-elf/pie_discard.t +new file mode 100644 +index 00000000..49e52cdb +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/pie_discard.t +@@ -0,0 +1,9 @@ ++SECTIONS ++{ ++ . = SEGMENT_START("text-segment", 0) + SIZEOF_HEADERS; ++ .rela.dyn : { *(.rela.*) } ++ .text : { *(.text) } ++ . = DATA_SEGMENT_ALIGN (CONSTANT (MAXPAGESIZE), CONSTANT (COMMONPAGESIZE)); ++ .data : { *(.data) } ++ /DISCARD/ : { *(.discard) } ++} +-- +2.33.0 +
View file
_service:tar_scm:BFD-Fix-the-bug-of-R_LARCH_AGLIN-caused-by-discard-s.patch
Added
@@ -0,0 +1,226 @@ +From aef05e9e774983b4d4a5a08ab7e172e1e678eff5 Mon Sep 17 00:00:00 2001 +From: mengqinggang <mengqinggang@loongson.cn> +Date: Wed, 24 Jan 2024 14:34:26 +0800 +Subject: PATCH 075/123 BFD: Fix the bug of R_LARCH_AGLIN caused by discard + section + +To represent the first and third expression of .align, R_LARCH_ALIGN need to +associate with a symbol. We define a local symbol for R_LARCH_AGLIN. +But if the section of the local symbol is discarded, it may result in +a undefined symbol error. + +Instead, we use the section name symbols, and this does not need to +add extra symbols. + +During partial linking (ld -r), if the symbol associated with a relocation is +STT_SECTION type, the addend of relocation needs to add the section output +offset. We prevent it for R_LARCH_ALIGN. + +The elf_backend_data.rela_normal only can set all relocations of a target to +rela_normal. Add a new function is_rela_normal to elf_backend_data, it can +set part of relocations to rela_normal. +--- + bfd/elf-bfd.h | 4 ++++ + bfd/elflink.c | 5 ++++- + bfd/elfnn-loongarch.c | 16 ++++++++++++++++ + bfd/elfxx-target.h | 5 +++++ + gas/config/tc-loongarch.c | 5 +---- + gas/testsuite/gas/loongarch/relax_align.d | 6 +++--- + .../ld-loongarch-elf/relax-align-discard.lds | 4 ++++ + .../ld-loongarch-elf/relax-align-discard.s | 17 +++++++++++++++++ + ld/testsuite/ld-loongarch-elf/relax.exp | 12 ++++++++++++ + 9 files changed, 66 insertions(+), 8 deletions(-) + create mode 100644 ld/testsuite/ld-loongarch-elf/relax-align-discard.lds + create mode 100644 ld/testsuite/ld-loongarch-elf/relax-align-discard.s + +diff --git a/bfd/elf-bfd.h b/bfd/elf-bfd.h +index ec856764..074120a5 100644 +--- a/bfd/elf-bfd.h ++++ b/bfd/elf-bfd.h +@@ -1703,6 +1703,10 @@ struct elf_backend_data + backend relocate_section routine for relocatable linking. */ + unsigned rela_normal : 1; + ++ /* Whether a relocation is rela_normal. Compared with rela_normal, ++ is_rela_normal can set part of relocations to rela_normal. */ ++ bool (*is_rela_normal) (Elf_Internal_Rela *); ++ + /* Set if DT_REL/DT_RELA/DT_RELSZ/DT_RELASZ should not include PLT + relocations. */ + unsigned dtrel_excludes_plt : 1; +diff --git a/bfd/elflink.c b/bfd/elflink.c +index 7217c2f0..cbf87d70 100644 +--- a/bfd/elflink.c ++++ b/bfd/elflink.c +@@ -11647,7 +11647,10 @@ elf_link_input_bfd (struct elf_final_link_info *flinfo, bfd *input_bfd) + { + rel_hash = PTR_ADD (esdo->rela.hashes, esdo->rela.count); + rela_hash_list = rel_hash; +- rela_normal = bed->rela_normal; ++ if (bed->is_rela_normal != NULL) ++ rela_normal = bed->is_rela_normal (irela); ++ else ++ rela_normal = bed->rela_normal; + } + + irela->r_offset = _bfd_elf_section_offset (output_bfd, +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index 1c3295f4..f6975957 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -5454,6 +5454,21 @@ elf_loongarch64_hash_symbol (struct elf_link_hash_entry *h) + return _bfd_elf_hash_symbol (h); + } + ++/* If a relocation is rela_normal and the symbol associated with the ++ relocation is STT_SECTION type, the addend of the relocation would add ++ sec->output_offset when partial linking (ld -r). ++ See elf_backend_data.rela_normal and elf_link_input_bfd(). ++ The addend of R_LARCH_ALIGN is used to represent the first and third ++ expression of .align, it should be a constant when linking. */ ++ ++static bool ++loongarch_elf_is_rela_normal (Elf_Internal_Rela *rel) ++{ ++ if (R_LARCH_ALIGN == ELFNN_R_TYPE (rel->r_info)) ++ return false; ++ return true; ++} ++ + #define TARGET_LITTLE_SYM loongarch_elfNN_vec + #define TARGET_LITTLE_NAME "elfNN-loongarch" + #define ELF_ARCH bfd_arch_loongarch +@@ -5489,6 +5504,7 @@ elf_loongarch64_hash_symbol (struct elf_link_hash_entry *h) + #define elf_backend_grok_psinfo loongarch_elf_grok_psinfo + #define elf_backend_hash_symbol elf_loongarch64_hash_symbol + #define bfd_elfNN_bfd_relax_section loongarch_elf_relax_section ++#define elf_backend_is_rela_normal loongarch_elf_is_rela_normal + + #define elf_backend_dtrel_excludes_plt 1 + +diff --git a/bfd/elfxx-target.h b/bfd/elfxx-target.h +index f8553006..385e40b7 100644 +--- a/bfd/elfxx-target.h ++++ b/bfd/elfxx-target.h +@@ -703,6 +703,10 @@ + #define elf_backend_rela_normal 0 + #endif + ++#ifndef elf_backend_is_rela_normal ++#define elf_backend_is_rela_normal NULL ++#endif ++ + #ifndef elf_backend_dtrel_excludes_plt + #define elf_backend_dtrel_excludes_plt 0 + #endif +@@ -948,6 +952,7 @@ static const struct elf_backend_data elfNN_bed = + elf_backend_default_use_rela_p, + elf_backend_rela_plts_and_copies_p, + elf_backend_rela_normal, ++ elf_backend_is_rela_normal, + elf_backend_dtrel_excludes_plt, + elf_backend_sign_extend_vma, + elf_backend_want_got_plt, +diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c +index 51575757..1e835f51 100644 +--- a/gas/config/tc-loongarch.c ++++ b/gas/config/tc-loongarch.c +@@ -1791,10 +1791,7 @@ loongarch_frag_align_code (int n, int max) + if (fragP->fr_subtype != 0 && offset > fragP->fr_subtype). */ + if (max > 0 && (bfd_vma) max < worst_case_bytes) + { +- s = symbol_find (".Lla-relax-align"); +- if (s == NULL) +- s = (symbolS *)local_symbol_make (".Lla-relax-align", now_seg, +- &zero_address_frag, 0); ++ s = symbol_find (now_seg->name); + ex.X_add_symbol = s; + ex.X_op = O_symbol; + ex.X_add_number = (max << 8) | n; +diff --git a/gas/testsuite/gas/loongarch/relax_align.d b/gas/testsuite/gas/loongarch/relax_align.d +index fc1fd032..acd215a4 100644 +--- a/gas/testsuite/gas/loongarch/relax_align.d ++++ b/gas/testsuite/gas/loongarch/relax_align.d +@@ -7,7 +7,7 @@ + + Disassembly of section .text: + +- *0000000000000000 <.Lla-relax-align>: ++ *0000000000000000 <.text>: + +0: +4c000020 +ret + +4: +03400000 +nop + +4: R_LARCH_ALIGN +\*ABS\*\+0xc +@@ -20,12 +20,12 @@ Disassembly of section .text: + +1c: +03400000 +nop + +20: +4c000020 +ret + +24: +03400000 +nop +- +24: R_LARCH_ALIGN +.Lla-relax-align\+0x104 ++ +24: R_LARCH_ALIGN +.text\+0x104 + +28: +03400000 +nop + +2c: +03400000 +nop + +30: +4c000020 +ret + +34: +03400000 +nop +- +34: R_LARCH_ALIGN +.Lla-relax-align\+0xb04 ++ +34: R_LARCH_ALIGN +.text\+0xb04 + +38: +03400000 +nop + +3c: +03400000 +nop + +40: +4c000020 +ret +diff --git a/ld/testsuite/ld-loongarch-elf/relax-align-discard.lds b/ld/testsuite/ld-loongarch-elf/relax-align-discard.lds +new file mode 100644 +index 00000000..4a81323d +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/relax-align-discard.lds +@@ -0,0 +1,4 @@ ++SECTIONS ++{ ++ /DISCARD/ : { *(.another.*) } ++} +diff --git a/ld/testsuite/ld-loongarch-elf/relax-align-discard.s b/ld/testsuite/ld-loongarch-elf/relax-align-discard.s +new file mode 100644 +index 00000000..b65d63f3 +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/relax-align-discard.s +@@ -0,0 +1,17 @@ ++# Use the section name symbol for R_LARCH_ALIGN to avoid discard section problem ++.section ".another.text", "ax" ++.cfi_startproc ++break 0 ++.cfi_def_cfa_offset 16 ++.p2align 5 ++break 1 ++.cfi_endproc ++ ++.text ++.cfi_startproc ++break 0 ++.cfi_def_cfa_offset 16 ++.p2align 5 ++break 1 ++.cfi_endproc
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_service:tar_scm:Fix-building-Loongarch-BFD-with-a-32-bit-compiler.patch
Added
@@ -0,0 +1,25 @@ +From 6a455ac82af2d8f5989f71df38f6e779ae202a48 Mon Sep 17 00:00:00 2001 +From: Nick Clifton <nickc@redhat.com> +Date: Mon, 29 Apr 2024 09:02:43 +0100 +Subject: PATCH 084/123 Fix building Loongarch BFD with a 32-bit compiler + +--- + bfd/elfnn-loongarch.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index ee708c7f..47fd08cd 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -782,7 +782,7 @@ bad_static_reloc (bfd *abfd, const Elf_Internal_Rela *rel, asection *sec, + (*_bfd_error_handler) + (_("%pB:(%pA+%#lx): relocation %s against `%s` can not be used when making " + "a shared object; recompile with -fPIC"), +- abfd, sec, rel->r_offset, r ? r->name : _("<unknown>"), name); ++ abfd, sec, (long) rel->r_offset, r ? r->name : _("<unknown>"), name); + bfd_set_error (bfd_error_bad_value); + return false; + } +-- +2.33.0 +
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_service:tar_scm:Include-ldlex.h-when-compile-eelfxxloongarch.c.patch
Added
@@ -0,0 +1,26 @@ +From 00f4bdc23c28986e4bdff1385ab7c6456fe74a6a Mon Sep 17 00:00:00 2001 +From: Xin Wang <wangxin03@loongson.cn> +Date: Thu, 24 Oct 2024 16:45:16 +0800 +Subject: PATCH 120/123 Include ldlex.h when compile eelfxxloongarch.c We did + not cherry-pick 8d10083c23b9415a6d645b44d136104fcf8ed176 of upstream:master + because that modified files which are not related to LoongArch + +--- + ld/emultempl/loongarchelf.em | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/ld/emultempl/loongarchelf.em b/ld/emultempl/loongarchelf.em +index 2e6b8080..e50d85d0 100644 +--- a/ld/emultempl/loongarchelf.em ++++ b/ld/emultempl/loongarchelf.em +@@ -24,6 +24,7 @@ fragment <<EOF + #include "ldctor.h" + #include "elf/loongarch.h" + #include "elfxx-loongarch.h" ++#include "ldlex.h" + + EOF + +-- +2.33.0 +
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_service:tar_scm:Libvtv-Add-loongarch-support.patch
Added
@@ -0,0 +1,36 @@ +From d1c8ef9a15ddaadd5848949b0958a803fc844674 Mon Sep 17 00:00:00 2001 +From: Lulu Cheng <chenglulu@loongson.cn> +Date: Mon, 7 Aug 2023 13:07:05 +0200 +Subject: PATCH 003/123 Libvtv: Add loongarch support. + +The loongarch64 specification permits page sizes of 4KiB, 16KiB and 64KiB, +but only 16KiB pages are supported for now. + +Co-Authored-By: qijingwen <qijingwen@loongson.cn> + +include/ + * vtv-change-permission.h (defined): Determines whether the macro + __loongarch_lp64 is defined + (VTV_PAGE_SIZE): Set VTV_PAGE_SIZE to 16KiB for loongarch64. +--- + include/vtv-change-permission.h | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/include/vtv-change-permission.h b/include/vtv-change-permission.h +index 5906e7d7..ffb53125 100644 +--- a/include/vtv-change-permission.h ++++ b/include/vtv-change-permission.h +@@ -48,6 +48,10 @@ extern void __VLTChangePermission (int); + #else + #if defined(__sun__) && defined(__svr4__) && defined(__sparc__) + #define VTV_PAGE_SIZE 8192 ++#elif defined(__loongarch_lp64) ++/* The page size is configurable by the kernel to be 4, 16 or 64 KiB. ++ For now, only the default page size of 16KiB is supported. */ ++#define VTV_PAGE_SIZE 16384 + #else + #define VTV_PAGE_SIZE 4096 + #endif +-- +2.33.0 +
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_service:tar_scm:LoongArch-Adapt-R_LARCH_-PCALA-GOT-TLS_IE-TLS_DESC-6.patch
Added
@@ -0,0 +1,155 @@ +From 2a9dd993a723726ccc6f5cfb4119ab6c8637c0d0 Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao <xry111@xry111.site> +Date: Tue, 16 Jan 2024 15:00:16 +0800 +Subject: PATCH 044/123 LoongArch: Adapt + R_LARCH_{PCALA,GOT,TLS_IE,TLS_DESC}64_* handling per psABI v2.30 + +In LoongArch psABI v2.30, an offset (-8 for LO20 and -12 for HI12) +should be applied on PC for these reloc types to avoid wrong relocation +when the instruction sequence crosses a page boundary. + +The lld linker has already adapted the change. Make it for the bfd +linker too. + +Link: https://github.com/loongson/la-abi-specs/releases/v2.30 +Link: https://github.com/loongson-community/discussions/issues/17 +Link: https://github.com/llvm/llvm-project/pull/73387 +Signed-off-by: Xi Ruoyao <xry111@xry111.site> +--- + bfd/elfnn-loongarch.c | 31 +++++++++++-------- + .../ld-loongarch-elf/ld-loongarch-elf.exp | 1 + + ld/testsuite/ld-loongarch-elf/pcala64.d | 15 +++++++++ + ld/testsuite/ld-loongarch-elf/pcala64.s | 8 +++++ + 4 files changed, 42 insertions(+), 13 deletions(-) + create mode 100644 ld/testsuite/ld-loongarch-elf/pcala64.d + create mode 100644 ld/testsuite/ld-loongarch-elf/pcala64.s + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index 8b71e836..b0ebe89e 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -2529,7 +2529,7 @@ loongarch_reloc_is_fatal (struct bfd_link_info *info, + ({ \ + bfd_vma __lo = (relocation & (bfd_vma)0xfff); \ + relocation = (relocation & ~(bfd_vma)0xfff) \ +- - (pc & ~(bfd_vma)0xfff); \ ++ - ((pc) & ~(bfd_vma)0xfff); \ + if (__lo > 0x7ff) \ + relocation += (0x1000 - 0x100000000); \ + if (relocation & 0x80000000) \ +@@ -3527,14 +3527,16 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, + } + break; + +- case R_LARCH_PCALA64_LO20: + case R_LARCH_PCALA64_HI12: ++ pc -= 4; ++ /* Fall through. */ ++ case R_LARCH_PCALA64_LO20: + if (h && h->plt.offset != MINUS_ONE) + relocation = sec_addr (plt) + h->plt.offset; + else + relocation += rel->r_addend; + +- RELOCATE_CALC_PC64_HI32 (relocation, pc); ++ RELOCATE_CALC_PC64_HI32 (relocation, pc - 8); + + break; + +@@ -3661,9 +3663,10 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, + relocation = got_off + sec_addr (got); + } + +- if (r_type == R_LARCH_GOT64_PC_HI12 +- || r_type == R_LARCH_GOT64_PC_LO20) +- RELOCATE_CALC_PC64_HI32 (relocation, pc); ++ if (r_type == R_LARCH_GOT64_PC_HI12) ++ RELOCATE_CALC_PC64_HI32 (relocation, pc - 12); ++ else if (r_type == R_LARCH_GOT64_PC_LO20) ++ RELOCATE_CALC_PC64_HI32 (relocation, pc - 8); + + break; + +@@ -3864,13 +3867,14 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, + /* Use both TLS_GD and TLS_DESC. */ + if ((tls_type & GOT_TLS_GD) && (tls_type & GOT_TLS_GDESC)) + relocation += 2 * GOT_ENTRY_SIZE; +- } + +- if (r_type == R_LARCH_TLS_DESC64_PC_LO20 +- || r_type == R_LARCH_TLS_DESC64_PC_HI12) +- RELOCATE_CALC_PC64_HI32 (relocation, pc); ++ if (r_type == R_LARCH_TLS_DESC64_PC_LO20) ++ RELOCATE_CALC_PC64_HI32 (relocation, pc - 8); ++ else if (r_type == R_LARCH_TLS_DESC64_PC_HI12) ++ RELOCATE_CALC_PC64_HI32 (relocation, pc - 12); + + break; ++ } + + case R_LARCH_TLS_DESC_LD: + case R_LARCH_TLS_DESC_CALL: +@@ -3899,9 +3903,10 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, + else if (GOT_TLS_GD_ANY_P (tls_type) && (tls_type & GOT_TLS_IE)) + relocation += 2 * GOT_ENTRY_SIZE; + +- if (r_type == R_LARCH_TLS_IE64_PC_LO20 +- || r_type == R_LARCH_TLS_IE64_PC_HI12) +- RELOCATE_CALC_PC64_HI32 (relocation, pc); ++ if (r_type == R_LARCH_TLS_IE64_PC_LO20) ++ RELOCATE_CALC_PC64_HI32 (relocation, pc - 8); ++ else if (r_type == R_LARCH_TLS_IE64_PC_HI12) ++ RELOCATE_CALC_PC64_HI32 (relocation, pc - 12); + + break; + +diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp +index 64e644d3..c81f20af 100644 +--- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp ++++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp +@@ -33,6 +33,7 @@ if istarget "loongarch64-*-*" { + run_dump_test "disas-jirl" + run_dump_test "local-ifunc-reloc" + run_dump_test "anno-sym" ++ run_dump_test "pcala64" + } + + if istarget "loongarch32-*-*" { +diff --git a/ld/testsuite/ld-loongarch-elf/pcala64.d b/ld/testsuite/ld-loongarch-elf/pcala64.d +new file mode 100644 +index 00000000..e0e9819d +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/pcala64.d +@@ -0,0 +1,15 @@ ++#ld: -Ttext=0x180000ff8 -Tdata=0x1000000000 ++#objdump: -d ++ ++.*: +file format .* ++ ++ ++Disassembly of section .text: ++ ++0000000180000ff8 <_start>: ++ +180000ff8: +1b000004 +pcalau12i +\$a0, +-524288 ++ +180000ffc: +02c0000c +li.d +\$t0, +0 ++ +180001000: +160001ec +lu32i.d +\$t0, +15 ++ +180001004: +0300018c +lu52i.d +\$t0, +\$t0, +0 ++ +180001008: +0010b084 +add.d +\$a0, +\$a0, +\$t0 ++ +18000100c: +4c000020 +ret +diff --git a/ld/testsuite/ld-loongarch-elf/pcala64.s b/ld/testsuite/ld-loongarch-elf/pcala64.s +new file mode 100644 +index 00000000..dfef0e2b +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/pcala64.s +@@ -0,0 +1,8 @@ ++.text ++.globl _start ++_start: ++ la.pcrel $a0, $t0, sym ++ jr $ra ++.data ++sym: ++ .dword 0 +-- +2.33.0 +
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_service:tar_scm:LoongArch-Add-DT_RELR-support.patch
Added
@@ -0,0 +1,641 @@ +From f0c66bc13d177150c3055cf7c321e48d0eb58b12 Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao <xry111@xry111.site> +Date: Wed, 30 Oct 2024 18:32:50 +0800 +Subject: PATCH 098/123 LoongArch: Add DT_RELR support + +The logic is same as a71d87680110 ("aarch64: Add DT_RELR support"). + +As LoongArch does not have -z dynamic-undefined-weak, we don't need to +consider UNDEFWEAK_NO_DYNAMIC_RELOC. + +The linker relaxation adds another layer of complexity. When we delete +bytes in a section during relaxation, we need to fix up the offset in +the to-be-packed relative relocations against this section. + +Signed-off-by: Xi Ruoyao <xry111@xry111.site> +--- + bfd/elfnn-loongarch.c | 488 ++++++++++++++++++++- + binutils/testsuite/lib/binutils-common.exp | 3 +- + ld/emulparams/elf64loongarch.sh | 1 + + 3 files changed, 487 insertions(+), 5 deletions(-) + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index 2bdd7be2..d11189b4 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -84,6 +84,12 @@ struct _bfd_loongarch_elf_obj_tdata + && elf_tdata (bfd) != NULL \ + && elf_object_id (bfd) == LARCH_ELF_DATA) + ++struct relr_entry ++{ ++ asection *sec; ++ bfd_vma off; ++}; ++ + struct loongarch_elf_link_hash_table + { + struct elf_link_hash_table elf; +@@ -104,8 +110,51 @@ struct loongarch_elf_link_hash_table + /* The data segment phase, don't relax the section + when it is exp_seg_relro_adjust. */ + int *data_segment_phase; ++ ++ /* Array of relative relocs to be emitted in DT_RELR format. */ ++ bfd_size_type relr_alloc; ++ bfd_size_type relr_count; ++ struct relr_entry *relr; ++ ++ /* Sorted output addresses of above relative relocs. */ ++ bfd_vma *relr_sorted; ++ ++ /* Layout recomputation count. */ ++ bfd_size_type relr_layout_iter; ++}; ++ ++struct loongarch_elf_section_data ++{ ++ struct bfd_elf_section_data elf; ++ ++ /* &htab->relri where i is the smallest number s.t. ++ elf_section_data (htab->relri.sec) == &elf. ++ NULL if there exists no such i. */ ++ struct relr_entry *relr; + }; + ++/* We need an additional field in elf_section_data to handle complex ++ interactions between DT_RELR and relaxation. */ ++static bool ++loongarch_elf_new_section_hook (bfd *abfd, asection *sec) ++{ ++ if (!sec->used_by_bfd) ++ { ++ struct loongarch_elf_section_data *sdata; ++ size_t amt = sizeof (*sdata); ++ ++ sdata = bfd_zalloc (abfd, amt); ++ if (!sdata) ++ return false; ++ sec->used_by_bfd = sdata; ++ } ++ ++ return _bfd_elf_new_section_hook (abfd, sec); ++} ++ ++#define loongarch_elf_section_data(x) \ ++ ((struct loongarch_elf_section_data *) elf_section_data (x)) ++ + /* Get the LoongArch ELF linker hash table from a link_info structure. */ + #define loongarch_elf_hash_table(p) \ + (elf_hash_table_id (elf_hash_table (p)) == LARCH_ELF_DATA \ +@@ -927,6 +976,20 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, + if (rel + 1 != relocs + sec->reloc_count + && ELFNN_R_TYPE (rel1.r_info) == R_LARCH_RELAX) + r_type = loongarch_tls_transition (abfd, info, h, r_symndx, r_type); ++ ++ /* I don't want to spend time supporting DT_RELR with old object ++ files doing stack-based relocs. */ ++ if (info->enable_dt_relr ++ && r_type >= R_LARCH_SOP_PUSH_PCREL ++ && r_type <= R_LARCH_SOP_POP_32_U) ++ { ++ /* xgettext:c-format */ ++ _bfd_error_handler (_("%pB: stack based reloc type (%u) is not " ++ "supported with -z pack-relative-relocs"), ++ abfd, r_type); ++ return false; ++ } ++ + switch (r_type) + { + case R_LARCH_GOT_PC_HI20: +@@ -1143,6 +1206,20 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, + return false; + break; + ++ case R_LARCH_ALIGN: ++ /* Check against irrational R_LARCH_ALIGN relocs which may cause ++ removing an odd number of bytes and disrupt DT_RELR. */ ++ if (rel->r_offset % 4 != 0) ++ { ++ /* xgettext:c-format */ ++ _bfd_error_handler ( ++ _("%pB: R_LARCH_ALIGN with offset %" PRId64 " not aligned " ++ "to instruction boundary"), ++ abfd, (uint64_t) rel->r_offset); ++ return false; ++ } ++ break; ++ + default: + break; + } +@@ -1857,6 +1934,343 @@ maybe_set_textrel (struct elf_link_hash_entry *h, void *info_p) + return true; + } + ++static bool ++record_relr (struct loongarch_elf_link_hash_table *htab, asection *sec, ++ bfd_vma off, asection *sreloc) ++{ ++ struct relr_entry **sec_relr = &loongarch_elf_section_data (sec)->relr; ++ ++ /* Undo the relocation section size accounting. */ ++ BFD_ASSERT (sreloc->size >= sizeof (ElfNN_External_Rela)); ++ sreloc->size -= sizeof (ElfNN_External_Rela); ++ ++ BFD_ASSERT (off % 2 == 0 && sec->alignment_power > 0); ++ if (htab->relr_count >= htab->relr_alloc) ++ { ++ if (htab->relr_alloc == 0) ++ htab->relr_alloc = 4096; ++ else ++ htab->relr_alloc *= 2; ++ ++ htab->relr = bfd_realloc (htab->relr, ++ htab->relr_alloc * sizeof (*htab->relr)); ++ if (!htab->relr) ++ return false; ++ } ++ htab->relrhtab->relr_count.sec = sec; ++ htab->relrhtab->relr_count.off = off; ++ if (*sec_relr == NULL) ++ *sec_relr = &htab->relrhtab->relr_count; ++ htab->relr_count++; ++ return true; ++} ++ ++static bool ++record_relr_local_got_relocs (bfd *input_bfd, struct bfd_link_info *info) ++{ ++ bfd_vma *local_got_offsets = elf_local_got_offsets (input_bfd); ++ char *local_tls_type = _bfd_loongarch_elf_local_got_tls_type (input_bfd); ++ Elf_Internal_Shdr *symtab_hdr = &elf_symtab_hdr (input_bfd); ++ struct loongarch_elf_link_hash_table *htab = ++ loongarch_elf_hash_table (info); ++ ++ if (!local_got_offsets || !local_tls_type || !bfd_link_pic (info)) ++ return true; ++ ++ for (unsigned i = 0; i < symtab_hdr->sh_info; i++) ++ { ++ bfd_vma off = local_got_offsetsi; ++ ++ /* FIXME: If the local symbol is in SHN_ABS then emitting ++ a relative relocation is not correct, but it seems to be wrong ++ in loongarch_elf_relocate_section too. */ ++ if (local_tls_typei == GOT_NORMAL ++ && !record_relr (htab, htab->elf.sgot, off, htab->elf.srelgot)) ++ return false; ++ } ++ ++ return true; ++} ++ ++static bool ++record_relr_dyn_got_relocs (struct elf_link_hash_entry *h, void *inf) ++{ ++ struct bfd_link_info *info = (struct bfd_link_info *) inf; ++ struct loongarch_elf_link_hash_table *htab =
View file
_service:tar_scm:LoongArch-Add-DT_RELR-tests.patch
Added
@@ -0,0 +1,663 @@ +From c3d71bd5b8f0f949729025ad3338e3f93e5e0d77 Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao <xry111@xry111.site> +Date: Sun, 30 Jun 2024 15:18:25 +0800 +Subject: PATCH 099/123 LoongArch: Add DT_RELR tests + +Most tests are ported from AArch64. + +The relr-addend test is added to make sure the addend (link-time address) +is correctly written into the relocated section. Doing so is not +strictly needed for RELA, but strictly needed for RELR). + +Signed-off-by: Xi Ruoyao <xry111@xry111.site> +--- + .../ld-loongarch-elf/ld-loongarch-elf.exp | 10 ++ + ld/testsuite/ld-loongarch-elf/relr-addend.d | 11 ++ + ld/testsuite/ld-loongarch-elf/relr-addend.s | 17 +++ + ld/testsuite/ld-loongarch-elf/relr-align.d | 22 ++++ + ld/testsuite/ld-loongarch-elf/relr-align.s | 106 ++++++++++++++++++ + ld/testsuite/ld-loongarch-elf/relr-data-pie.d | 18 +++ + .../ld-loongarch-elf/relr-data-shared.d | 18 +++ + ld/testsuite/ld-loongarch-elf/relr-data.s | 71 ++++++++++++ + .../ld-loongarch-elf/relr-discard-pie.d | 8 ++ + .../ld-loongarch-elf/relr-discard-shared.d | 11 ++ + ld/testsuite/ld-loongarch-elf/relr-discard.ld | 13 +++ + ld/testsuite/ld-loongarch-elf/relr-discard.s | 61 ++++++++++ + ld/testsuite/ld-loongarch-elf/relr-got-pie.d | 15 +++ + .../ld-loongarch-elf/relr-got-shared.d | 15 +++ + ld/testsuite/ld-loongarch-elf/relr-got.s | 27 +++++ + ld/testsuite/ld-loongarch-elf/relr-relocs.ld | 24 ++++ + ld/testsuite/ld-loongarch-elf/relr-text-pie.d | 14 +++ + .../ld-loongarch-elf/relr-text-shared.d | 14 +++ + ld/testsuite/ld-loongarch-elf/relr-text.s | 10 ++ + 19 files changed, 485 insertions(+) + create mode 100644 ld/testsuite/ld-loongarch-elf/relr-addend.d + create mode 100644 ld/testsuite/ld-loongarch-elf/relr-addend.s + create mode 100644 ld/testsuite/ld-loongarch-elf/relr-align.d + create mode 100644 ld/testsuite/ld-loongarch-elf/relr-align.s + create mode 100644 ld/testsuite/ld-loongarch-elf/relr-data-pie.d + create mode 100644 ld/testsuite/ld-loongarch-elf/relr-data-shared.d + create mode 100644 ld/testsuite/ld-loongarch-elf/relr-data.s + create mode 100644 ld/testsuite/ld-loongarch-elf/relr-discard-pie.d + create mode 100644 ld/testsuite/ld-loongarch-elf/relr-discard-shared.d + create mode 100644 ld/testsuite/ld-loongarch-elf/relr-discard.ld + create mode 100644 ld/testsuite/ld-loongarch-elf/relr-discard.s + create mode 100644 ld/testsuite/ld-loongarch-elf/relr-got-pie.d + create mode 100644 ld/testsuite/ld-loongarch-elf/relr-got-shared.d + create mode 100644 ld/testsuite/ld-loongarch-elf/relr-got.s + create mode 100644 ld/testsuite/ld-loongarch-elf/relr-relocs.ld + create mode 100644 ld/testsuite/ld-loongarch-elf/relr-text-pie.d + create mode 100644 ld/testsuite/ld-loongarch-elf/relr-text-shared.d + create mode 100644 ld/testsuite/ld-loongarch-elf/relr-text.s + +diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp +index 30d7bc03..2be67651 100644 +--- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp ++++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp +@@ -135,10 +135,20 @@ if istarget "loongarch64-*-*" { + run_dump_test "r_larch_32_elf64" + run_dump_test "ifunc-reloc" + run_dump_test "protected-func" ++ run_dump_test "relr-addend" ++ run_dump_test "relr-align" ++ run_dump_test "relr-data-shared" ++ run_dump_test "relr-discard-shared" ++ run_dump_test "relr-got-shared" ++ run_dump_test "relr-text-shared" + } + + if check_pie_support { + run_dump_test "pie_discard" ++ run_dump_test "relr-data-pie" ++ run_dump_test "relr-discard-pie" ++ run_dump_test "relr-got-pie" ++ run_dump_test "relr-text-pie" + } + + run_dump_test "max_imm_b16" +diff --git a/ld/testsuite/ld-loongarch-elf/relr-addend.d b/ld/testsuite/ld-loongarch-elf/relr-addend.d +new file mode 100644 +index 00000000..da13c2cf +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/relr-addend.d +@@ -0,0 +1,11 @@ ++#ld: -shared -z pack-relative-relocs -T relr-relocs.ld ++#objdump: -s -j.got -j.data ++ ++.*: file format elf64-loongarch ++ ++Contents of section \.got: ++ 20000 0-9a-f+ 0-9a-f+ 00003412 00000000 .* ++ 20010 08003412 00000000 .* ++Contents of section \.data: ++ 12340000 14451100 00000000 10989101 00000000 .* ++ 12340010 00003412 00000000 08003412 00000000 .* +diff --git a/ld/testsuite/ld-loongarch-elf/relr-addend.s b/ld/testsuite/ld-loongarch-elf/relr-addend.s +new file mode 100644 +index 00000000..3d08f6ca +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/relr-addend.s +@@ -0,0 +1,17 @@ ++.data ++.align 8 ++x: ++ .quad 0x114514 ++y: ++ .quad 0x1919810 ++px: ++ .quad x ++py: ++ .quad y ++ ++.text ++.align 2 ++_start: ++ la.got $a0, x ++ la.got $a1, y ++ ret +diff --git a/ld/testsuite/ld-loongarch-elf/relr-align.d b/ld/testsuite/ld-loongarch-elf/relr-align.d +new file mode 100644 +index 00000000..d534243b +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/relr-align.d +@@ -0,0 +1,22 @@ ++#source: relr-align.s ++#ld: -shared -z pack-relative-relocs -T relr-relocs.ld ++#readelf: -rW ++ ++Relocation section '\.rela.dyn' at offset 0x0-9a-f+ contains 3 entries: ++ Offset Info Type Symbol's Value Symbol's Name \+ Addend ++0000000012340011 0000000000000003 R_LARCH_RELATIVE 10000 ++0000000012340019 0000000000000003 R_LARCH_RELATIVE 10000 ++0000000012340041 0000000000000003 R_LARCH_RELATIVE 10000 ++ ++Relocation section '\.relr.dyn' at offset 0x0-9a-f+ contains 9 entries which relocate 10 locations: ++Index: Entry Address Symbolic Address ++0000: 0000000012340000 0000000012340000 double_0 ++0001: 0000000000000003 0000000012340008 double_0 \+ 0x8 ++0002: 0000000012340022 0000000012340022 double_2 ++0003: 0000000000000003 000000001234002a double_2 \+ 0x8 ++0004: 0000000012340038 0000000012340038 single_0 ++0005: 000000001234004a 000000001234004a single_2 ++0006: 0000000012340058 0000000012340058 big ++0007: 8000000100000001 0000000012340158 big \+ 0x100 ++ 0000000012340250 big \+ 0x1f8 ++0008: 0000000000000003 0000000012340258 big \+ 0x200 +diff --git a/ld/testsuite/ld-loongarch-elf/relr-align.s b/ld/testsuite/ld-loongarch-elf/relr-align.s +new file mode 100644 +index 00000000..ddd055ab +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/relr-align.s +@@ -0,0 +1,106 @@ ++# Test DT_RELR with differently aligned relative relocs. ++ ++.text ++.global _start ++_start: ++foo: ++ ++.data ++.p2align 3 ++double_0: ++.quad foo ++.quad foo ++.byte 0 ++double_1: ++.quad foo ++.quad foo ++.byte 0 ++double_2: ++.quad foo ++.quad foo ++.byte 0 ++.byte 0 ++.byte 0 ++.byte 0 ++.byte 0 ++.byte 0 ++single_0: ++.quad foo ++.byte 0 ++single_1: ++.quad foo ++.byte 0 ++single_2: ++.quad foo ++.byte 0 ++.byte 0 ++.byte 0 ++.byte 0 ++.byte 0 ++.byte 0 ++big: ++.quad foo ++.quad 1 ++.quad 2 ++.quad 3 ++.quad 4 ++.quad 5 ++.quad 6
View file
_service:tar_scm:LoongArch-Add-bad-static-relocation-check-and-output.patch
Added
@@ -0,0 +1,185 @@ +From 3aeea61a3efc9a5535a2dcb9e938782ba3a60aa6 Mon Sep 17 00:00:00 2001 +From: Lulu Cai <cailulu@loongson.cn> +Date: Tue, 19 Mar 2024 17:51:19 +0800 +Subject: PATCH 082/123 LoongArch: Add bad static relocation check and output + more information to user + +Absolute address symbols cannot be used with -shared. +We output more information to the user than just BFD_ASSETR. +--- + bfd/elfnn-loongarch.c | 33 +++++++++++++++++-- + .../ld-loongarch-elf/ld-loongarch-elf.exp | 3 ++ + .../ld-loongarch-elf/reloc_abs_with_shared.d | 6 ++++ + .../ld-loongarch-elf/reloc_abs_with_shared.s | 9 +++++ + .../ld-loongarch-elf/reloc_le_with_shared.d | 6 ++++ + .../ld-loongarch-elf/reloc_le_with_shared.s | 8 +++++ + .../ld-loongarch-elf/reloc_ler_with_shared.d | 4 +++ + .../ld-loongarch-elf/reloc_ler_with_shared.s | 9 +++++ + 8 files changed, 76 insertions(+), 2 deletions(-) + create mode 100644 ld/testsuite/ld-loongarch-elf/reloc_abs_with_shared.d + create mode 100644 ld/testsuite/ld-loongarch-elf/reloc_abs_with_shared.s + create mode 100644 ld/testsuite/ld-loongarch-elf/reloc_le_with_shared.d + create mode 100644 ld/testsuite/ld-loongarch-elf/reloc_le_with_shared.s + create mode 100644 ld/testsuite/ld-loongarch-elf/reloc_ler_with_shared.d + create mode 100644 ld/testsuite/ld-loongarch-elf/reloc_ler_with_shared.s + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index 0a7caa2a..ee708c7f 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -760,6 +760,33 @@ loongarch_tls_transition (bfd *input_bfd, + allocate space in the global offset table or procedure linkage + table. */ + ++static bool ++bad_static_reloc (bfd *abfd, const Elf_Internal_Rela *rel, asection *sec, ++ unsigned r_type, struct elf_link_hash_entry *h, ++ Elf_Internal_Sym *isym) ++{ ++ /* We propably can improve the information to tell users that they should ++ be recompile the code with -fPIC or -fPIE, just like what x86 does. */ ++ reloc_howto_type * r = loongarch_elf_rtype_to_howto (abfd, r_type); ++ const char *name = NULL; ++ ++ if (h) ++ name = h->root.root.string; ++ else if (isym) ++ name = bfd_elf_string_from_elf_section (abfd, ++ elf_symtab_hdr (abfd).sh_link, ++ isym->st_name); ++ if (name == NULL || *name == '\0') ++ name ="<nameless>"; ++ ++ (*_bfd_error_handler) ++ (_("%pB:(%pA+%#lx): relocation %s against `%s` can not be used when making " ++ "a shared object; recompile with -fPIC"), ++ abfd, sec, rel->r_offset, r ? r->name : _("<unknown>"), name); ++ bfd_set_error (bfd_error_bad_value); ++ return false; ++} ++ + static bool + loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, + asection *sec, const Elf_Internal_Rela *relocs) +@@ -904,7 +931,7 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, + case R_LARCH_TLS_LE_HI20_R: + case R_LARCH_SOP_PUSH_TLS_TPREL: + if (!bfd_link_executable (info)) +- return false; ++ return bad_static_reloc (abfd, rel, sec, r_type, h, isym); + + if (!loongarch_elf_record_tls_and_got_reference (abfd, info, h, + r_symndx, +@@ -922,6 +949,9 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, + + case R_LARCH_ABS_HI20: + case R_LARCH_SOP_PUSH_ABSOLUTE: ++ if (bfd_link_pic (info)) ++ return bad_static_reloc (abfd, rel, sec, r_type, h, isym); ++ + if (h != NULL) + /* If this reloc is in a read-only section, we might + need a copy reloc. We can't check reliably at this +@@ -3397,7 +3427,6 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, + case R_LARCH_ABS_LO12: + case R_LARCH_ABS64_LO20: + case R_LARCH_ABS64_HI12: +- BFD_ASSERT (!is_pic); + + if (is_undefweak) + { +diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp +index fc7b5bfe..3c8e9195 100644 +--- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp ++++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp +@@ -134,6 +134,9 @@ if istarget "loongarch64-*-*" { + run_dump_test "desc-norelax" + run_dump_test "desc-relax" + run_dump_test "data-got" ++ run_dump_test "reloc_le_with_shared" ++ run_dump_test "reloc_ler_with_shared" ++ run_dump_test "reloc_abs_with_shared" + } + + if check_pie_support { +diff --git a/ld/testsuite/ld-loongarch-elf/reloc_abs_with_shared.d b/ld/testsuite/ld-loongarch-elf/reloc_abs_with_shared.d +new file mode 100644 +index 00000000..532e84fb +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/reloc_abs_with_shared.d +@@ -0,0 +1,6 @@ ++#source: reloc_abs_with_shared.s ++#as: ++#ld: -shared ++#error: .*relocation R_LARCH_ABS_HI20 against `s` can not be used when making a shared object; recompile with -fPIC ++#... ++#pass +diff --git a/ld/testsuite/ld-loongarch-elf/reloc_abs_with_shared.s b/ld/testsuite/ld-loongarch-elf/reloc_abs_with_shared.s +new file mode 100644 +index 00000000..13341af2 +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/reloc_abs_with_shared.s +@@ -0,0 +1,9 @@ ++ .text ++ .globl s ++ .data ++ .type s, @object ++ s: ++ .word 123 ++ .text ++ lu12i.w $r4,%abs_hi20(s) ++ addi.d $r4,$r4,%abs_lo12(s) +diff --git a/ld/testsuite/ld-loongarch-elf/reloc_le_with_shared.d b/ld/testsuite/ld-loongarch-elf/reloc_le_with_shared.d +new file mode 100644 +index 00000000..562b079a +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/reloc_le_with_shared.d +@@ -0,0 +1,6 @@ ++#source: reloc_le_with_shared.s ++#as: ++#ld: -shared ++#error: .*relocation R_LARCH_TLS_LE_HI20 against `s` can not be used when making a shared object; recompile with -fPIC ++#... ++#pass +diff --git a/ld/testsuite/ld-loongarch-elf/reloc_le_with_shared.s b/ld/testsuite/ld-loongarch-elf/reloc_le_with_shared.s +new file mode 100644 +index 00000000..c7206650 +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/reloc_le_with_shared.s +@@ -0,0 +1,8 @@ ++ .text ++ .globl s ++ .section .tdata,"awT",@progbits ++ .type s, @object ++ s: ++ .word 123 ++ .text ++ la.tls.le $r4, s +diff --git a/ld/testsuite/ld-loongarch-elf/reloc_ler_with_shared.d b/ld/testsuite/ld-loongarch-elf/reloc_ler_with_shared.d +new file mode 100644 +index 00000000..7382d5b8 +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/reloc_ler_with_shared.d +@@ -0,0 +1,4 @@ ++#source: reloc_ler_with_shared.s ++#as: ++#ld: -shared ++#error: .*relocation R_LARCH_TLS_LE_HI20_R against `s` can not be used when making a shared object; recompile with -fPIC +diff --git a/ld/testsuite/ld-loongarch-elf/reloc_ler_with_shared.s b/ld/testsuite/ld-loongarch-elf/reloc_ler_with_shared.s +new file mode 100644 +index 00000000..a9e56967 +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/reloc_ler_with_shared.s +@@ -0,0 +1,9 @@ ++ .text ++ .globl s ++ .section .tdata,"awT",@progbits ++ .type s, @object ++ s: ++ .word 123 ++ .text ++ lu12i.w $r4,%le_hi20_r(s) ++ add.d $r4,$r4,$r2,%le_add_r(s) +-- +2.33.0 +
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_service:tar_scm:LoongArch-Add-call36-and-tail36-pseudo-instructions-.patch
Added
@@ -0,0 +1,101 @@ +From 205e07d68684bc331c16b7bcea44b8d5ca84f7e8 Mon Sep 17 00:00:00 2001 +From: mengqinggang <mengqinggang@loongson.cn> +Date: Thu, 23 Nov 2023 15:42:49 +0800 +Subject: PATCH 021/123 LoongArch: Add call36 and tail36 pseudo instructions + for medium code model + + For tail36, it is necessary to explicitly indicate the temporary register. + Therefore, the compiler and users will know that the tail will use a register. + + call36 func + pcalau18i $ra, %call36(func) + jirl $ra, $ra, 0; + + tail36 $t0, func + pcalau18i $t0, %call36(func) + jirl $zero, $t0, 0; +--- + gas/testsuite/gas/loongarch/medium-call.d | 10 ++++++++-- + gas/testsuite/gas/loongarch/medium-call.s | 2 ++ + ld/testsuite/ld-loongarch-elf/medium-call.s | 2 ++ + opcodes/loongarch-opc.c | 11 +++++++++++ + 4 files changed, 23 insertions(+), 2 deletions(-) + +diff --git a/gas/testsuite/gas/loongarch/medium-call.d b/gas/testsuite/gas/loongarch/medium-call.d +index 4183818c..3491760b 100644 +--- a/gas/testsuite/gas/loongarch/medium-call.d ++++ b/gas/testsuite/gas/loongarch/medium-call.d +@@ -10,6 +10,12 @@ Disassembly of section .text: + +0: +1e000001 +pcaddu18i +\$ra, 0 + +0: R_LARCH_CALL36 +a + +4: +4c000021 +jirl +\$ra, \$ra, 0 +- +8: +1e00000c +pcaddu18i +\$t0, 0 ++ +8: +1e000001 +pcaddu18i +\$ra, 0 + +8: R_LARCH_CALL36 +a +- +c: +4c000180 +jr +\$t0 ++ +c: +4c000021 +jirl +\$ra, \$ra, 0 ++ +10: +1e00000c +pcaddu18i +\$t0, 0 ++ +10: R_LARCH_CALL36 +a ++ +14: +4c000180 +jr +\$t0 ++ +18: +1e00000c +pcaddu18i +\$t0, 0 ++ +18: R_LARCH_CALL36 +a ++ +1c: +4c000180 +jr +\$t0 +diff --git a/gas/testsuite/gas/loongarch/medium-call.s b/gas/testsuite/gas/loongarch/medium-call.s +index f2977d1c..74d15076 100644 +--- a/gas/testsuite/gas/loongarch/medium-call.s ++++ b/gas/testsuite/gas/loongarch/medium-call.s +@@ -1,6 +1,8 @@ + # call .L1, r1(ra) temp register, r1(ra) return register. ++ call36 a + pcaddu18i $r1, %call36(a) + jirl $r1, $r1, 0 + # tail .L1, r12(t0) temp register, r0(zero) return register. ++ tail36 $r12, a + pcaddu18i $r12, %call36(a) + jirl $r0, $r12, 0 +diff --git a/ld/testsuite/ld-loongarch-elf/medium-call.s b/ld/testsuite/ld-loongarch-elf/medium-call.s +index 4d1888b7..50a6b8e7 100644 +--- a/ld/testsuite/ld-loongarch-elf/medium-call.s ++++ b/ld/testsuite/ld-loongarch-elf/medium-call.s +@@ -1,7 +1,9 @@ + .L1: + # call .L1, r1(ra) temp register, r1(ra) return register. ++ call36 .L1 + pcaddu18i $r1, %call36(.L1) + jirl $r1, $r1, 0 + # tail .L1, r12(t0) temp register, r0(zero) return register. ++ tail36 $r12, .L1 + pcaddu18i $r12, %call36(.L1) + jirl $r0, $r12, 0 +diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c +index 15c7da63..b47817f8 100644 +--- a/opcodes/loongarch-opc.c ++++ b/opcodes/loongarch-opc.c +@@ -293,6 +293,15 @@ const char *const loongarch_x_normal_name32 = + &LARCH_opts.ase_lp64, \ + &LARCH_opts.ase_gpcr + ++#define INSN_LA_CALL \ ++ "pcaddu18i $ra,%%call36(%1);" \ ++ "jirl $ra,$ra,0;", \ ++ 0, 0 ++ ++#define INSN_LA_TAIL \ ++ "pcaddu18i %1,%%call36(%2);" \ ++ "jirl $zero,%1,0;", \ ++ 0, 0 + + static struct loongarch_opcode loongarch_macro_opcodes = + { +@@ -340,6 +349,8 @@ static struct loongarch_opcode loongarch_macro_opcodes = + { 0, 0, "la.tls.gd", "r,l", INSN_LA_TLS_GD64, 0 }, + { 0, 0, "la.tls.gd", "r,l", INSN_LA_TLS_GD64_LARGE_ABS, 0 }, + { 0, 0, "la.tls.gd", "r,r,l", INSN_LA_TLS_GD64_LARGE_PCREL, 0 }, ++ { 0, 0, "call36", "la", INSN_LA_CALL, 0 }, ++ { 0, 0, "tail36", "r,la", INSN_LA_TAIL, 0 }, + { 0, 0, "pcaddi", "r,la", "pcaddi %1, %%pcrel_20(%2)", &LARCH_opts.ase_ilp32, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */ + }; +-- +2.33.0 +
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_service:tar_scm:LoongArch-Add-dtpoff-calculation-function.patch
Added
@@ -0,0 +1,44 @@ +From 43fdb57b36afb8fd1d76f3dc7a9833d60ef90422 Mon Sep 17 00:00:00 2001 +From: Lulu Cai <cailulu@loongson.cn> +Date: Fri, 23 Feb 2024 16:28:22 +0800 +Subject: PATCH 070/123 LoongArch: Add dtpoff calculation function + +When tls_sec is NULL, we should not access the virtual address +of tls_sec. +--- + bfd/elfnn-loongarch.c | 12 +++++++++++- + 1 file changed, 11 insertions(+), 1 deletion(-) + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index eea1839f..489ccbe0 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -2550,6 +2550,16 @@ loongarch_reloc_is_fatal (struct bfd_link_info *info, + }) + + ++static bfd_vma ++tls_dtpoff_base (struct bfd_link_info *info) ++{ ++ /* If tls_sec is NULL, we should have signalled an error already. */ ++ if (elf_hash_table (info)->tls_sec == NULL) ++ return 0; ++ return elf_hash_table (info)->tls_sec->vma; ++} ++ ++ + static int + loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, + bfd *input_bfd, asection *input_section, +@@ -3708,7 +3718,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, + rela.r_offset = sec_addr (got) + got_off + desc_off; + rela.r_addend = 0; + if (indx == 0) +- rela.r_addend = relocation - elf_hash_table (info)->tls_sec->vma; ++ rela.r_addend = relocation - tls_dtpoff_base (info); + + rela.r_info = ELFNN_R_INFO (indx, R_LARCH_TLS_DESCNN); + loongarch_elf_append_rela (output_bfd, relgot, &rela); +-- +2.33.0 +
View file
_service:tar_scm:LoongArch-Add-elfNN_loongarch_mkobject-to-initialize.patch
Added
@@ -0,0 +1,42 @@ +From 5ba625b50145a8234129ab6b4a58a18e530ae9d7 Mon Sep 17 00:00:00 2001 +From: Xin Wang <yw987194828@gmail.com> +Date: Fri, 6 Sep 2024 09:00:12 +0800 +Subject: PATCH 114/123 LoongArch: Add elfNN_loongarch_mkobject to initialize + LoongArch tdata + +LoongArch: Add elfNN_loongarch_mkobject to initialize LoongArch tdata. +--- + bfd/elfnn-loongarch.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index 09a9513b..b6d7d1e8 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -84,6 +84,14 @@ struct _bfd_loongarch_elf_obj_tdata + && elf_tdata (bfd) != NULL \ + && elf_object_id (bfd) == LARCH_ELF_DATA) + ++static bool ++elfNN_loongarch_object (bfd *abfd) ++{ ++ return bfd_elf_allocate_object (abfd, ++ sizeof (struct _bfd_loongarch_elf_obj_tdata), ++ LARCH_ELF_DATA); ++} ++ + struct relr_entry + { + asection *sec; +@@ -6158,6 +6166,8 @@ elf_loongarch64_hash_symbol (struct elf_link_hash_entry *h) + #define bfd_elfNN_bfd_reloc_name_lookup loongarch_reloc_name_lookup + #define elf_info_to_howto_rel NULL /* Fall through to elf_info_to_howto. */ + #define elf_info_to_howto loongarch_info_to_howto_rela ++#define bfd_elfNN_mkobject \ ++ elfNN_loongarch_object + #define bfd_elfNN_bfd_merge_private_bfd_data \ + elfNN_loongarch_merge_private_bfd_data + +-- +2.33.0 +
View file
_service:tar_scm:LoongArch-Add-gas-testsuit-for-LA32-int-float-instru.patch
Added
@@ -0,0 +1,654 @@ +From 1ced47506592c7724be57101d70254e826e833d1 Mon Sep 17 00:00:00 2001 +From: Lulu Cai <cailulu@loongson.cn> +Date: Wed, 10 Jan 2024 16:17:50 +0800 +Subject: PATCH 066/123 LoongArch: Add gas testsuit for LA32 int/float + instructions + +Test the int/float instructions of LA32. +--- + gas/testsuite/gas/loongarch/insn_float32.d | 157 +++++++++++++++++++++ + gas/testsuite/gas/loongarch/insn_float32.s | 149 +++++++++++++++++++ + gas/testsuite/gas/loongarch/insn_int32.d | 147 +++++++++++++++++++ + gas/testsuite/gas/loongarch/insn_int32.s | 156 ++++++++++++++++++++ + 4 files changed, 609 insertions(+) + create mode 100644 gas/testsuite/gas/loongarch/insn_float32.d + create mode 100644 gas/testsuite/gas/loongarch/insn_float32.s + create mode 100644 gas/testsuite/gas/loongarch/insn_int32.d + create mode 100644 gas/testsuite/gas/loongarch/insn_int32.s + +diff --git a/gas/testsuite/gas/loongarch/insn_float32.d b/gas/testsuite/gas/loongarch/insn_float32.d +new file mode 100644 +index 00000000..ee2408af +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/insn_float32.d +@@ -0,0 +1,157 @@ ++#as-new: ++#objdump: -d ++#skip: loongarch64-*-* ++ ++.*: file format .* ++ ++ ++Disassembly of section .text: ++ ++0+ <.*>: ++ 0: 01008820 fadd.s \$fa0, \$fa1, \$fa2 ++ 4: 01010820 fadd.d \$fa0, \$fa1, \$fa2 ++ 8: 01028820 fsub.s \$fa0, \$fa1, \$fa2 ++ c: 01030820 fsub.d \$fa0, \$fa1, \$fa2 ++ 10: 01048820 fmul.s \$fa0, \$fa1, \$fa2 ++ 14: 01050820 fmul.d \$fa0, \$fa1, \$fa2 ++ 18: 01068820 fdiv.s \$fa0, \$fa1, \$fa2 ++ 1c: 01070820 fdiv.d \$fa0, \$fa1, \$fa2 ++ 20: 01088820 fmax.s \$fa0, \$fa1, \$fa2 ++ 24: 01090820 fmax.d \$fa0, \$fa1, \$fa2 ++ 28: 010a8820 fmin.s \$fa0, \$fa1, \$fa2 ++ 2c: 010b0820 fmin.d \$fa0, \$fa1, \$fa2 ++ 30: 010c8820 fmaxa.s \$fa0, \$fa1, \$fa2 ++ 34: 010d0820 fmaxa.d \$fa0, \$fa1, \$fa2 ++ 38: 010e8820 fmina.s \$fa0, \$fa1, \$fa2 ++ 3c: 010f0820 fmina.d \$fa0, \$fa1, \$fa2 ++ 40: 01108820 fscaleb.s \$fa0, \$fa1, \$fa2 ++ 44: 01110820 fscaleb.d \$fa0, \$fa1, \$fa2 ++ 48: 01128820 fcopysign.s \$fa0, \$fa1, \$fa2 ++ 4c: 01130820 fcopysign.d \$fa0, \$fa1, \$fa2 ++ 50: 01140420 fabs.s \$fa0, \$fa1 ++ 54: 01140820 fabs.d \$fa0, \$fa1 ++ 58: 01141420 fneg.s \$fa0, \$fa1 ++ 5c: 01141820 fneg.d \$fa0, \$fa1 ++ 60: 01142420 flogb.s \$fa0, \$fa1 ++ 64: 01142820 flogb.d \$fa0, \$fa1 ++ 68: 01143420 fclass.s \$fa0, \$fa1 ++ 6c: 01143820 fclass.d \$fa0, \$fa1 ++ 70: 01144420 fsqrt.s \$fa0, \$fa1 ++ 74: 01144820 fsqrt.d \$fa0, \$fa1 ++ 78: 01145420 frecip.s \$fa0, \$fa1 ++ 7c: 01145820 frecip.d \$fa0, \$fa1 ++ 80: 01146420 frsqrt.s \$fa0, \$fa1 ++ 84: 01146820 frsqrt.d \$fa0, \$fa1 ++ 88: 01149420 fmov.s \$fa0, \$fa1 ++ 8c: 01149820 fmov.d \$fa0, \$fa1 ++ 90: 0114a4a0 movgr2fr.w \$fa0, \$a1 ++ 94: 0114a8a0 movgr2fr.d \$fa0, \$a1 ++ 98: 0114aca0 movgr2frh.w \$fa0, \$a1 ++ 9c: 0114b424 movfr2gr.s \$a0, \$fa1 ++ a0: 0114b824 movfr2gr.d \$a0, \$fa1 ++ a4: 0114bc24 movfrh2gr.s \$a0, \$fa1 ++ a8: 0114c0a0 movgr2fcsr \$fcsr0, \$a1 ++ ac: 0114c804 movfcsr2gr \$a0, \$fcsr0 ++ b0: 0114d020 movfr2cf \$fcc0, \$fa1 ++ b4: 0114d4a0 movcf2fr \$fa0, \$fcc5 ++ b8: 0114d8a0 movgr2cf \$fcc0, \$a1 ++ bc: 0114dca4 movcf2gr \$a0, \$fcc5 ++ c0: 01191820 fcvt.s.d \$fa0, \$fa1 ++ c4: 01192420 fcvt.d.s \$fa0, \$fa1 ++ c8: 011a0420 ftintrm.w.s \$fa0, \$fa1 ++ cc: 011a0820 ftintrm.w.d \$fa0, \$fa1 ++ d0: 011a2420 ftintrm.l.s \$fa0, \$fa1 ++ d4: 011a2820 ftintrm.l.d \$fa0, \$fa1 ++ d8: 011a4420 ftintrp.w.s \$fa0, \$fa1 ++ dc: 011a4820 ftintrp.w.d \$fa0, \$fa1 ++ e0: 011a6420 ftintrp.l.s \$fa0, \$fa1 ++ e4: 011a6820 ftintrp.l.d \$fa0, \$fa1 ++ e8: 011a8420 ftintrz.w.s \$fa0, \$fa1 ++ ec: 011a8820 ftintrz.w.d \$fa0, \$fa1 ++ f0: 011aa420 ftintrz.l.s \$fa0, \$fa1 ++ f4: 011aa820 ftintrz.l.d \$fa0, \$fa1 ++ f8: 011ac420 ftintrne.w.s \$fa0, \$fa1 ++ fc: 011ac820 ftintrne.w.d \$fa0, \$fa1 ++ 100: 011ae420 ftintrne.l.s \$fa0, \$fa1 ++ 104: 011ae820 ftintrne.l.d \$fa0, \$fa1 ++ 108: 011b0420 ftint.w.s \$fa0, \$fa1 ++ 10c: 011b0820 ftint.w.d \$fa0, \$fa1 ++ 110: 011b2420 ftint.l.s \$fa0, \$fa1 ++ 114: 011b2820 ftint.l.d \$fa0, \$fa1 ++ 118: 011d1020 ffint.s.w \$fa0, \$fa1 ++ 11c: 011d1820 ffint.s.l \$fa0, \$fa1 ++ 120: 011d2020 ffint.d.w \$fa0, \$fa1 ++ 124: 011d2820 ffint.d.l \$fa0, \$fa1 ++ 128: 011e4420 frint.s \$fa0, \$fa1 ++ 12c: 011e4820 frint.d \$fa0, \$fa1 ++ 130: 01147420 frecipe.s \$fa0, \$fa1 ++ 134: 01147820 frecipe.d \$fa0, \$fa1 ++ 138: 01148420 frsqrte.s \$fa0, \$fa1 ++ 13c: 01148820 frsqrte.d \$fa0, \$fa1 ++ 140: 08118820 fmadd.s \$fa0, \$fa1, \$fa2, \$fa3 ++ 144: 08218820 fmadd.d \$fa0, \$fa1, \$fa2, \$fa3 ++ 148: 08518820 fmsub.s \$fa0, \$fa1, \$fa2, \$fa3 ++ 14c: 08618820 fmsub.d \$fa0, \$fa1, \$fa2, \$fa3 ++ 150: 08918820 fnmadd.s \$fa0, \$fa1, \$fa2, \$fa3 ++ 154: 08a18820 fnmadd.d \$fa0, \$fa1, \$fa2, \$fa3 ++ 158: 08d18820 fnmsub.s \$fa0, \$fa1, \$fa2, \$fa3 ++ 15c: 08e18820 fnmsub.d \$fa0, \$fa1, \$fa2, \$fa3 ++ 160: 0c100820 fcmp.caf.s \$fcc0, \$fa1, \$fa2 ++ 164: 0c108820 fcmp.saf.s \$fcc0, \$fa1, \$fa2 ++ 168: 0c110820 fcmp.clt.s \$fcc0, \$fa1, \$fa2 ++ 16c: 0c118820 fcmp.slt.s \$fcc0, \$fa1, \$fa2 ++ 170: 0c118820 fcmp.slt.s \$fcc0, \$fa1, \$fa2 ++ 174: 0c120820 fcmp.ceq.s \$fcc0, \$fa1, \$fa2 ++ 178: 0c128820 fcmp.seq.s \$fcc0, \$fa1, \$fa2 ++ 17c: 0c130820 fcmp.cle.s \$fcc0, \$fa1, \$fa2 ++ 180: 0c138820 fcmp.sle.s \$fcc0, \$fa1, \$fa2 ++ 184: 0c138820 fcmp.sle.s \$fcc0, \$fa1, \$fa2 ++ 188: 0c140820 fcmp.cun.s \$fcc0, \$fa1, \$fa2 ++ 18c: 0c148820 fcmp.sun.s \$fcc0, \$fa1, \$fa2 ++ 190: 0c150820 fcmp.cult.s \$fcc0, \$fa1, \$fa2 ++ 194: 0c150820 fcmp.cult.s \$fcc0, \$fa1, \$fa2 ++ 198: 0c158820 fcmp.sult.s \$fcc0, \$fa1, \$fa2 ++ 19c: 0c160820 fcmp.cueq.s \$fcc0, \$fa1, \$fa2 ++ 1a0: 0c168820 fcmp.sueq.s \$fcc0, \$fa1, \$fa2 ++ 1a4: 0c170820 fcmp.cule.s \$fcc0, \$fa1, \$fa2 ++ 1a8: 0c170820 fcmp.cule.s \$fcc0, \$fa1, \$fa2 ++ 1ac: 0c178820 fcmp.sule.s \$fcc0, \$fa1, \$fa2 ++ 1b0: 0c180820 fcmp.cne.s \$fcc0, \$fa1, \$fa2 ++ 1b4: 0c188820 fcmp.sne.s \$fcc0, \$fa1, \$fa2 ++ 1b8: 0c1a0820 fcmp.cor.s \$fcc0, \$fa1, \$fa2 ++ 1bc: 0c1a8820 fcmp.sor.s \$fcc0, \$fa1, \$fa2 ++ 1c0: 0c1c0820 fcmp.cune.s \$fcc0, \$fa1, \$fa2 ++ 1c4: 0c1c8820 fcmp.sune.s \$fcc0, \$fa1, \$fa2 ++ 1c8: 0c200820 fcmp.caf.d \$fcc0, \$fa1, \$fa2 ++ 1cc: 0c208820 fcmp.saf.d \$fcc0, \$fa1, \$fa2 ++ 1d0: 0c210820 fcmp.clt.d \$fcc0, \$fa1, \$fa2 ++ 1d4: 0c218820 fcmp.slt.d \$fcc0, \$fa1, \$fa2 ++ 1d8: 0c218820 fcmp.slt.d \$fcc0, \$fa1, \$fa2 ++ 1dc: 0c220820 fcmp.ceq.d \$fcc0, \$fa1, \$fa2 ++ 1e0: 0c228820 fcmp.seq.d \$fcc0, \$fa1, \$fa2 ++ 1e4: 0c230820 fcmp.cle.d \$fcc0, \$fa1, \$fa2 ++ 1e8: 0c238820 fcmp.sle.d \$fcc0, \$fa1, \$fa2 ++ 1ec: 0c238820 fcmp.sle.d \$fcc0, \$fa1, \$fa2 ++ 1f0: 0c240820 fcmp.cun.d \$fcc0, \$fa1, \$fa2 ++ 1f4: 0c248820 fcmp.sun.d \$fcc0, \$fa1, \$fa2 ++ 1f8: 0c250820 fcmp.cult.d \$fcc0, \$fa1, \$fa2 ++ 1fc: 0c250820 fcmp.cult.d \$fcc0, \$fa1, \$fa2 ++ 200: 0c258820 fcmp.sult.d \$fcc0, \$fa1, \$fa2 ++ 204: 0c260820 fcmp.cueq.d \$fcc0, \$fa1, \$fa2 ++ 208: 0c268820 fcmp.sueq.d \$fcc0, \$fa1, \$fa2 ++ 20c: 0c270820 fcmp.cule.d \$fcc0, \$fa1, \$fa2 ++ 210: 0c270820 fcmp.cule.d \$fcc0, \$fa1, \$fa2 ++ 214: 0c278820 fcmp.sule.d \$fcc0, \$fa1, \$fa2 ++ 218: 0c280820 fcmp.cne.d \$fcc0, \$fa1, \$fa2 ++ 21c: 0c288820 fcmp.sne.d \$fcc0, \$fa1, \$fa2 ++ 220: 0c2a0820 fcmp.cor.d \$fcc0, \$fa1, \$fa2 ++ 224: 0c2a8820 fcmp.sor.d \$fcc0, \$fa1, \$fa2 ++ 228: 0c2c0820 fcmp.cune.d \$fcc0, \$fa1, \$fa2 ++ 22c: 0c2c8820 fcmp.sune.d \$fcc0, \$fa1, \$fa2 ++ 230: 0d000820 fsel \$fa0, \$fa1, \$fa2, \$fcc0 ++ 234: 2b00058a fld.s \$ft2, \$t0, 1 ++ 238: 2b40058a fst.s \$ft2, \$t0, 1 ++ 23c: 2b80058a fld.d \$ft2, \$t0, 1 ++ 240: 2bc0058a fst.d \$ft2, \$t0, 1 ++ 244: 48000000 bceqz \$fcc0, 0 # 0x244 ++ 248: 48000100 bcnez \$fcc0, 0 # 0x248 +diff --git a/gas/testsuite/gas/loongarch/insn_float32.s b/gas/testsuite/gas/loongarch/insn_float32.s +new file mode 100644 +index 00000000..8465633b +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/insn_float32.s +@@ -0,0 +1,149 @@ ++fadd.s $f0,$f1,$f2 ++fadd.d $f0,$f1,$f2 ++fsub.s $f0,$f1,$f2 ++fsub.d $f0,$f1,$f2 ++fmul.s $f0,$f1,$f2 ++fmul.d $f0,$f1,$f2 ++fdiv.s $f0,$f1,$f2 ++fdiv.d $f0,$f1,$f2 ++fmax.s $f0,$f1,$f2 ++fmax.d $f0,$f1,$f2 ++fmin.s $f0,$f1,$f2 ++fmin.d $f0,$f1,$f2
View file
_service:tar_scm:LoongArch-Add-gas-testsuit-for-LA32-relocations.patch
Added
@@ -0,0 +1,164 @@ +From bed92cdad966e2a7b9cfea8a5113187304255968 Mon Sep 17 00:00:00 2001 +From: Lulu Cai <cailulu@loongson.cn> +Date: Fri, 12 Jan 2024 11:15:10 +0800 +Subject: PATCH 068/123 LoongArch: Add gas testsuit for LA32 relocations + +Test the relocation of the LA32 instruction set. +--- + gas/testsuite/gas/loongarch/relocs_32.d | 75 +++++++++++++++++++++++++ + gas/testsuite/gas/loongarch/relocs_32.s | 61 ++++++++++++++++++++ + 2 files changed, 136 insertions(+) + create mode 100644 gas/testsuite/gas/loongarch/relocs_32.d + create mode 100644 gas/testsuite/gas/loongarch/relocs_32.s + +diff --git a/gas/testsuite/gas/loongarch/relocs_32.d b/gas/testsuite/gas/loongarch/relocs_32.d +new file mode 100644 +index 00000000..3e1bb62e +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/relocs_32.d +@@ -0,0 +1,75 @@ ++#as: -mthin-add-sub ++#objdump: -dr ++#skip: loongarch64-*-* ++ ++.*: +file format .* ++ ++ ++Disassembly of section .text: ++ ++0+ <.*>: ++ 0: 4c0050a4 jirl \$a0, \$a1, 80 ++ 0: R_LARCH_B16 .L1 ++ 4: 50004c00 b 76 # 50 <.L1> ++ 4: R_LARCH_B26 .L1 ++ 8: 14000004 lu12i.w \$a0, 0 ++ 8: R_LARCH_ABS_HI20 .L1 ++ c: 038000a4 ori \$a0, \$a1, 0x0 ++ c: R_LARCH_ABS_LO12 .L1 ++ 10: 1a000004 pcalau12i \$a0, 0 ++ 10: R_LARCH_PCALA_HI20 .L1 ++ 14: 02800085 addi.w \$a1, \$a0, 0 ++ 14: R_LARCH_PCALA_LO12 .L1 ++ 18: 1a000004 pcalau12i \$a0, 0 ++ 18: R_LARCH_GOT_PC_HI20 .L1 ++ 1c: 28800085 ld.w \$a1, \$a0, 0 ++ 1c: R_LARCH_GOT_PC_LO12 .L1 ++ 20: 14000004 lu12i.w \$a0, 0 ++ 20: R_LARCH_GOT_HI20 .L1 ++ 24: 03800084 ori \$a0, \$a0, 0x0 ++ 24: R_LARCH_GOT_LO12 .L1 ++ 28: 14000004 lu12i.w \$a0, 0 ++ 28: R_LARCH_TLS_LE_HI20 TLSL1 ++ 2c: 03800085 ori \$a1, \$a0, 0x0 ++ 2c: R_LARCH_TLS_LE_LO12 TLSL1 ++ 30: 1a000004 pcalau12i \$a0, 0 ++ 30: R_LARCH_TLS_IE_PC_HI20 TLSL1 ++ 34: 02c00005 li.d \$a1, 0 ++ 34: R_LARCH_TLS_IE_PC_LO12 TLSL1 ++ 38: 14000004 lu12i.w \$a0, 0 ++ 38: R_LARCH_TLS_IE_HI20 TLSL1 ++ 3c: 03800084 ori \$a0, \$a0, 0x0 ++ 3c: R_LARCH_TLS_IE_LO12 TLSL1 ++ 40: 1a000004 pcalau12i \$a0, 0 ++ 40: R_LARCH_TLS_LD_PC_HI20 TLSL1 ++ 44: 14000004 lu12i.w \$a0, 0 ++ 44: R_LARCH_TLS_LD_HI20 TLSL1 ++ 48: 1a000004 pcalau12i \$a0, 0 ++ 48: R_LARCH_TLS_GD_PC_HI20 TLSL1 ++ 4c: 14000004 lu12i.w \$a0, 0 ++ 4c: R_LARCH_TLS_GD_HI20 TLSL1 ++ ++0+50 <.L1>: ++ 50: 00000000 .word 0x00000000 ++ 50: R_LARCH_32_PCREL .L2 ++ ++0+54 <.L2>: ++ 54: 03400000 nop ++ 58: 03400000 nop ++ 58: R_LARCH_ALIGN .* ++ 5c: 03400000 nop ++ 60: 03400000 nop ++ 64: 1800000c pcaddi \$t0, 0 ++ 64: R_LARCH_PCREL20_S2 .L1 ++ 68: 1a000004 pcalau12i \$a0, 0 ++ 68: R_LARCH_TLS_DESC_PC_HI20 TLSL1 ++ 6c: 028000a5 addi.w \$a1, \$a1, 0 ++ 6c: R_LARCH_TLS_DESC_PC_LO12 TLSL1 ++ 70: 14000004 lu12i.w \$a0, 0 ++ 70: R_LARCH_TLS_DESC_HI20 TLSL1 ++ 74: 03800084 ori \$a0, \$a0, 0x0 ++ 74: R_LARCH_TLS_DESC_LO12 TLSL1 ++ 78: 28800081 ld.w \$ra, \$a0, 0 ++ 78: R_LARCH_TLS_DESC_LD TLSL1 ++ 7c: 4c000021 jirl \$ra, \$ra, 0 ++ 7c: R_LARCH_TLS_DESC_CALL TLSL1 +diff --git a/gas/testsuite/gas/loongarch/relocs_32.s b/gas/testsuite/gas/loongarch/relocs_32.s +new file mode 100644 +index 00000000..c5139a75 +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/relocs_32.s +@@ -0,0 +1,61 @@ ++/* b16. */ ++jirl $r4,$r5,%b16(.L1) ++ ++/* b26. */ ++b %b26(.L1) ++ ++/* lu12i.w. */ ++lu12i.w $r4,%abs_hi20(.L1) ++ ++/* ori */ ++ori $r4,$r5,%abs_lo12(.L1) ++ ++pcalau12i $r4,%pc_hi20(.L1) ++addi.w $r5,$r4,%pc_lo12(.L1) ++ ++pcalau12i $r4,%got_pc_hi20(.L1) ++ld.w $r5,$r4,%got_pc_lo12(.L1) ++ ++lu12i.w $r4,%got_hi20(.L1) ++ori $r4,$r4,%got_lo12(.L1) ++ ++/* TLS LE. */ ++lu12i.w $r4,%le_hi20(TLSL1) ++ori $r5,$r4,%le_lo12(TLSL1) ++ ++/* Part of IE relocs. */ ++pcalau12i $r4,%ie_pc_hi20(TLSL1) ++addi.d $r5,$r0,%ie_pc_lo12(TLSL1) ++ ++lu12i.w $r4,%ie_hi20(TLSL1) ++ori $r4,$r4,%ie_lo12(TLSL1) ++ ++/* Part of LD relocs. */ ++pcalau12i $r4,%ld_pc_hi20(TLSL1) ++lu12i.w $r4,%ld_hi20(TLSL1) ++ ++/* Part of GD relocs. */ ++pcalau12i $r4,%gd_pc_hi20(TLSL1) ++lu12i.w $r4,%gd_hi20(TLSL1) ++ ++/* Test insn relocs. */ ++.L1: ++/* 32-bit PC relative. */ ++.4byte .L2-.L1 ++.L2: ++nop ++ ++/* R_LARCH_ALIGN. */ ++.align 4 ++ ++/* R_LARCH_PCREL20_S2. */ ++pcaddi $r12,.L1 ++ ++/* Part of DESC relocs. */ ++pcalau12i $r4,%desc_pc_hi20(TLSL1) ++addi.w $r5,$r5,%desc_pc_lo12(TLSL1) ++ ++lu12i.w $r4,%desc_hi20(TLSL1) ++ori $r4,$r4,%desc_lo12(TLSL1) ++ld.w $r1,$r4,%desc_ld(TLSL1) ++jirl $r1,$r1,%desc_call(TLSL1) +-- +2.33.0 +
View file
_service:tar_scm:LoongArch-Add-gas-testsuit-for-LA64-int-float-instru.patch
Added
@@ -0,0 +1,1237 @@ +From 1d52dc328f178949b32251507572afb688e929d5 Mon Sep 17 00:00:00 2001 +From: Lulu Cai <cailulu@loongson.cn> +Date: Wed, 10 Jan 2024 14:44:48 +0800 +Subject: PATCH 065/123 LoongArch: Add gas testsuit for LA64 int/float + instructions + +Test the int/float instructions of LA64. +--- + gas/testsuite/gas/loongarch/insn_float64.d | 165 ++++++++ + gas/testsuite/gas/loongarch/insn_float64.s | 157 ++++++++ + gas/testsuite/gas/loongarch/insn_int64.d | 430 ++++++++++++++++++++ + gas/testsuite/gas/loongarch/insn_int64.s | 440 +++++++++++++++++++++ + 4 files changed, 1192 insertions(+) + create mode 100644 gas/testsuite/gas/loongarch/insn_float64.d + create mode 100644 gas/testsuite/gas/loongarch/insn_float64.s + create mode 100644 gas/testsuite/gas/loongarch/insn_int64.d + create mode 100644 gas/testsuite/gas/loongarch/insn_int64.s + +diff --git a/gas/testsuite/gas/loongarch/insn_float64.d b/gas/testsuite/gas/loongarch/insn_float64.d +new file mode 100644 +index 00000000..4ffbfa78 +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/insn_float64.d +@@ -0,0 +1,165 @@ ++#as-new: ++#objdump: -d ++#skip: loongarch32-*-* ++ ++.*: file format .* ++ ++ ++Disassembly of section .text: ++ ++0+ <.*>: ++ 0: 01008820 fadd.s \$fa0, \$fa1, \$fa2 ++ 4: 01010820 fadd.d \$fa0, \$fa1, \$fa2 ++ 8: 01028820 fsub.s \$fa0, \$fa1, \$fa2 ++ c: 01030820 fsub.d \$fa0, \$fa1, \$fa2 ++ 10: 01048820 fmul.s \$fa0, \$fa1, \$fa2 ++ 14: 01050820 fmul.d \$fa0, \$fa1, \$fa2 ++ 18: 01068820 fdiv.s \$fa0, \$fa1, \$fa2 ++ 1c: 01070820 fdiv.d \$fa0, \$fa1, \$fa2 ++ 20: 01088820 fmax.s \$fa0, \$fa1, \$fa2 ++ 24: 01090820 fmax.d \$fa0, \$fa1, \$fa2 ++ 28: 010a8820 fmin.s \$fa0, \$fa1, \$fa2 ++ 2c: 010b0820 fmin.d \$fa0, \$fa1, \$fa2 ++ 30: 010c8820 fmaxa.s \$fa0, \$fa1, \$fa2 ++ 34: 010d0820 fmaxa.d \$fa0, \$fa1, \$fa2 ++ 38: 010e8820 fmina.s \$fa0, \$fa1, \$fa2 ++ 3c: 010f0820 fmina.d \$fa0, \$fa1, \$fa2 ++ 40: 01108820 fscaleb.s \$fa0, \$fa1, \$fa2 ++ 44: 01110820 fscaleb.d \$fa0, \$fa1, \$fa2 ++ 48: 01128820 fcopysign.s \$fa0, \$fa1, \$fa2 ++ 4c: 01130820 fcopysign.d \$fa0, \$fa1, \$fa2 ++ 50: 01140420 fabs.s \$fa0, \$fa1 ++ 54: 01140820 fabs.d \$fa0, \$fa1 ++ 58: 01141420 fneg.s \$fa0, \$fa1 ++ 5c: 01141820 fneg.d \$fa0, \$fa1 ++ 60: 01142420 flogb.s \$fa0, \$fa1 ++ 64: 01142820 flogb.d \$fa0, \$fa1 ++ 68: 01143420 fclass.s \$fa0, \$fa1 ++ 6c: 01143820 fclass.d \$fa0, \$fa1 ++ 70: 01144420 fsqrt.s \$fa0, \$fa1 ++ 74: 01144820 fsqrt.d \$fa0, \$fa1 ++ 78: 01145420 frecip.s \$fa0, \$fa1 ++ 7c: 01145820 frecip.d \$fa0, \$fa1 ++ 80: 01146420 frsqrt.s \$fa0, \$fa1 ++ 84: 01146820 frsqrt.d \$fa0, \$fa1 ++ 88: 01149420 fmov.s \$fa0, \$fa1 ++ 8c: 01149820 fmov.d \$fa0, \$fa1 ++ 90: 0114a4a0 movgr2fr.w \$fa0, \$a1 ++ 94: 0114a8a0 movgr2fr.d \$fa0, \$a1 ++ 98: 0114aca0 movgr2frh.w \$fa0, \$a1 ++ 9c: 0114b424 movfr2gr.s \$a0, \$fa1 ++ a0: 0114b824 movfr2gr.d \$a0, \$fa1 ++ a4: 0114bc24 movfrh2gr.s \$a0, \$fa1 ++ a8: 0114c0a0 movgr2fcsr \$fcsr0, \$a1 ++ ac: 0114c804 movfcsr2gr \$a0, \$fcsr0 ++ b0: 0114d020 movfr2cf \$fcc0, \$fa1 ++ b4: 0114d4a0 movcf2fr \$fa0, \$fcc5 ++ b8: 0114d8a0 movgr2cf \$fcc0, \$a1 ++ bc: 0114dca4 movcf2gr \$a0, \$fcc5 ++ c0: 01191820 fcvt.s.d \$fa0, \$fa1 ++ c4: 01192420 fcvt.d.s \$fa0, \$fa1 ++ c8: 011a0420 ftintrm.w.s \$fa0, \$fa1 ++ cc: 011a0820 ftintrm.w.d \$fa0, \$fa1 ++ d0: 011a2420 ftintrm.l.s \$fa0, \$fa1 ++ d4: 011a2820 ftintrm.l.d \$fa0, \$fa1 ++ d8: 011a4420 ftintrp.w.s \$fa0, \$fa1 ++ dc: 011a4820 ftintrp.w.d \$fa0, \$fa1 ++ e0: 011a6420 ftintrp.l.s \$fa0, \$fa1 ++ e4: 011a6820 ftintrp.l.d \$fa0, \$fa1 ++ e8: 011a8420 ftintrz.w.s \$fa0, \$fa1 ++ ec: 011a8820 ftintrz.w.d \$fa0, \$fa1 ++ f0: 011aa420 ftintrz.l.s \$fa0, \$fa1 ++ f4: 011aa820 ftintrz.l.d \$fa0, \$fa1 ++ f8: 011ac420 ftintrne.w.s \$fa0, \$fa1 ++ fc: 011ac820 ftintrne.w.d \$fa0, \$fa1 ++ 100: 011ae420 ftintrne.l.s \$fa0, \$fa1 ++ 104: 011ae820 ftintrne.l.d \$fa0, \$fa1 ++ 108: 011b0420 ftint.w.s \$fa0, \$fa1 ++ 10c: 011b0820 ftint.w.d \$fa0, \$fa1 ++ 110: 011b2420 ftint.l.s \$fa0, \$fa1 ++ 114: 011b2820 ftint.l.d \$fa0, \$fa1 ++ 118: 011d1020 ffint.s.w \$fa0, \$fa1 ++ 11c: 011d1820 ffint.s.l \$fa0, \$fa1 ++ 120: 011d2020 ffint.d.w \$fa0, \$fa1 ++ 124: 011d2820 ffint.d.l \$fa0, \$fa1 ++ 128: 011e4420 frint.s \$fa0, \$fa1 ++ 12c: 011e4820 frint.d \$fa0, \$fa1 ++ 130: 01147420 frecipe.s \$fa0, \$fa1 ++ 134: 01147820 frecipe.d \$fa0, \$fa1 ++ 138: 01148420 frsqrte.s \$fa0, \$fa1 ++ 13c: 01148820 frsqrte.d \$fa0, \$fa1 ++ 140: 08118820 fmadd.s \$fa0, \$fa1, \$fa2, \$fa3 ++ 144: 08218820 fmadd.d \$fa0, \$fa1, \$fa2, \$fa3 ++ 148: 08518820 fmsub.s \$fa0, \$fa1, \$fa2, \$fa3 ++ 14c: 08618820 fmsub.d \$fa0, \$fa1, \$fa2, \$fa3 ++ 150: 08918820 fnmadd.s \$fa0, \$fa1, \$fa2, \$fa3 ++ 154: 08a18820 fnmadd.d \$fa0, \$fa1, \$fa2, \$fa3 ++ 158: 08d18820 fnmsub.s \$fa0, \$fa1, \$fa2, \$fa3 ++ 15c: 08e18820 fnmsub.d \$fa0, \$fa1, \$fa2, \$fa3 ++ 160: 0c100820 fcmp.caf.s \$fcc0, \$fa1, \$fa2 ++ 164: 0c108820 fcmp.saf.s \$fcc0, \$fa1, \$fa2 ++ 168: 0c110820 fcmp.clt.s \$fcc0, \$fa1, \$fa2 ++ 16c: 0c118820 fcmp.slt.s \$fcc0, \$fa1, \$fa2 ++ 170: 0c118820 fcmp.slt.s \$fcc0, \$fa1, \$fa2 ++ 174: 0c120820 fcmp.ceq.s \$fcc0, \$fa1, \$fa2 ++ 178: 0c128820 fcmp.seq.s \$fcc0, \$fa1, \$fa2 ++ 17c: 0c130820 fcmp.cle.s \$fcc0, \$fa1, \$fa2 ++ 180: 0c138820 fcmp.sle.s \$fcc0, \$fa1, \$fa2 ++ 184: 0c138820 fcmp.sle.s \$fcc0, \$fa1, \$fa2 ++ 188: 0c140820 fcmp.cun.s \$fcc0, \$fa1, \$fa2 ++ 18c: 0c148820 fcmp.sun.s \$fcc0, \$fa1, \$fa2 ++ 190: 0c150820 fcmp.cult.s \$fcc0, \$fa1, \$fa2 ++ 194: 0c150820 fcmp.cult.s \$fcc0, \$fa1, \$fa2 ++ 198: 0c158820 fcmp.sult.s \$fcc0, \$fa1, \$fa2 ++ 19c: 0c160820 fcmp.cueq.s \$fcc0, \$fa1, \$fa2 ++ 1a0: 0c168820 fcmp.sueq.s \$fcc0, \$fa1, \$fa2 ++ 1a4: 0c170820 fcmp.cule.s \$fcc0, \$fa1, \$fa2 ++ 1a8: 0c170820 fcmp.cule.s \$fcc0, \$fa1, \$fa2 ++ 1ac: 0c178820 fcmp.sule.s \$fcc0, \$fa1, \$fa2 ++ 1b0: 0c180820 fcmp.cne.s \$fcc0, \$fa1, \$fa2 ++ 1b4: 0c188820 fcmp.sne.s \$fcc0, \$fa1, \$fa2 ++ 1b8: 0c1a0820 fcmp.cor.s \$fcc0, \$fa1, \$fa2 ++ 1bc: 0c1a8820 fcmp.sor.s \$fcc0, \$fa1, \$fa2 ++ 1c0: 0c1c0820 fcmp.cune.s \$fcc0, \$fa1, \$fa2 ++ 1c4: 0c1c8820 fcmp.sune.s \$fcc0, \$fa1, \$fa2 ++ 1c8: 0c200820 fcmp.caf.d \$fcc0, \$fa1, \$fa2 ++ 1cc: 0c208820 fcmp.saf.d \$fcc0, \$fa1, \$fa2 ++ 1d0: 0c210820 fcmp.clt.d \$fcc0, \$fa1, \$fa2 ++ 1d4: 0c218820 fcmp.slt.d \$fcc0, \$fa1, \$fa2 ++ 1d8: 0c218820 fcmp.slt.d \$fcc0, \$fa1, \$fa2 ++ 1dc: 0c220820 fcmp.ceq.d \$fcc0, \$fa1, \$fa2 ++ 1e0: 0c228820 fcmp.seq.d \$fcc0, \$fa1, \$fa2 ++ 1e4: 0c230820 fcmp.cle.d \$fcc0, \$fa1, \$fa2 ++ 1e8: 0c238820 fcmp.sle.d \$fcc0, \$fa1, \$fa2 ++ 1ec: 0c238820 fcmp.sle.d \$fcc0, \$fa1, \$fa2 ++ 1f0: 0c240820 fcmp.cun.d \$fcc0, \$fa1, \$fa2 ++ 1f4: 0c248820 fcmp.sun.d \$fcc0, \$fa1, \$fa2 ++ 1f8: 0c250820 fcmp.cult.d \$fcc0, \$fa1, \$fa2 ++ 1fc: 0c250820 fcmp.cult.d \$fcc0, \$fa1, \$fa2 ++ 200: 0c258820 fcmp.sult.d \$fcc0, \$fa1, \$fa2 ++ 204: 0c260820 fcmp.cueq.d \$fcc0, \$fa1, \$fa2 ++ 208: 0c268820 fcmp.sueq.d \$fcc0, \$fa1, \$fa2 ++ 20c: 0c270820 fcmp.cule.d \$fcc0, \$fa1, \$fa2 ++ 210: 0c270820 fcmp.cule.d \$fcc0, \$fa1, \$fa2 ++ 214: 0c278820 fcmp.sule.d \$fcc0, \$fa1, \$fa2 ++ 218: 0c280820 fcmp.cne.d \$fcc0, \$fa1, \$fa2 ++ 21c: 0c288820 fcmp.sne.d \$fcc0, \$fa1, \$fa2 ++ 220: 0c2a0820 fcmp.cor.d \$fcc0, \$fa1, \$fa2 ++ 224: 0c2a8820 fcmp.sor.d \$fcc0, \$fa1, \$fa2 ++ 228: 0c2c0820 fcmp.cune.d \$fcc0, \$fa1, \$fa2 ++ 22c: 0c2c8820 fcmp.sune.d \$fcc0, \$fa1, \$fa2 ++ 230: 0d000820 fsel \$fa0, \$fa1, \$fa2, \$fcc0 ++ 234: 2b00058a fld.s \$ft2, \$t0, 1 ++ 238: 2b40058a fst.s \$ft2, \$t0, 1 ++ 23c: 2b80058a fld.d \$ft2, \$t0, 1 ++ 240: 2bc0058a fst.d \$ft2, \$t0, 1 ++ 244: 38741480 fldgt.s \$fa0, \$a0, \$a1 ++ 248: 38749480 fldgt.d \$fa0, \$a0, \$a1 ++ 24c: 38751480 fldle.s \$fa0, \$a0, \$a1 ++ 250: 38759480 fldle.d \$fa0, \$a0, \$a1 ++ 254: 38761480 fstgt.s \$fa0, \$a0, \$a1 ++ 258: 38769480 fstgt.d \$fa0, \$a0, \$a1 ++ 25c: 38771480 fstle.s \$fa0, \$a0, \$a1 ++ 260: 38779480 fstle.d \$fa0, \$a0, \$a1 ++ 264: 48000000 bceqz \$fcc0, 0 # 0x264 ++ 268: 48000100 bcnez \$fcc0, 0 # 0x268 +diff --git a/gas/testsuite/gas/loongarch/insn_float64.s b/gas/testsuite/gas/loongarch/insn_float64.s +new file mode 100644 +index 00000000..a7ce56ef +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/insn_float64.s +@@ -0,0 +1,157 @@ ++fadd.s $f0,$f1,$f2 ++fadd.d $f0,$f1,$f2 ++fsub.s $f0,$f1,$f2 ++fsub.d $f0,$f1,$f2
View file
_service:tar_scm:LoongArch-Add-gas-testsuit-for-LA64-relocations.patch
Added
@@ -0,0 +1,281 @@ +From 6dbcb5e8afae6d282e0955fdbbc7732b10338902 Mon Sep 17 00:00:00 2001 +From: Lulu Cai <cailulu@loongson.cn> +Date: Thu, 11 Jan 2024 09:45:57 +0800 +Subject: PATCH 067/123 LoongArch: Add gas testsuit for LA64 relocations + +Test the relocation of the LA64 instruction set. +--- + gas/testsuite/gas/loongarch/relocs_64.d | 144 ++++++++++++++++++++++++ + gas/testsuite/gas/loongarch/relocs_64.s | 109 ++++++++++++++++++ + 2 files changed, 253 insertions(+) + create mode 100644 gas/testsuite/gas/loongarch/relocs_64.d + create mode 100644 gas/testsuite/gas/loongarch/relocs_64.s + +diff --git a/gas/testsuite/gas/loongarch/relocs_64.d b/gas/testsuite/gas/loongarch/relocs_64.d +new file mode 100644 +index 00000000..631137eb +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/relocs_64.d +@@ -0,0 +1,144 @@ ++#as: -mthin-add-sub ++#objdump: -dr ++#skip: loongarch32-*-* ++ ++.*: file format .* ++ ++ ++Disassembly of section .text: ++ ++0+ <.*>: ++ 0: 4c008ca4 jirl \$a0, \$a1, 140 ++ 0: R_LARCH_B16 .L1 ++ 4: 40008880 beqz \$a0, 136 # 8c <.L1> ++ 4: R_LARCH_B21 .L1 ++ 8: 50008400 b 132 # 8c <.L1> ++ 8: R_LARCH_B26 .L1 ++ c: 14000004 lu12i.w \$a0, 0 ++ c: R_LARCH_ABS_HI20 .L1 ++ 10: 038000a4 ori \$a0, \$a1, 0x0 ++ 10: R_LARCH_ABS_LO12 .L1 ++ 14: 16000004 lu32i.d \$a0, 0 ++ 14: R_LARCH_ABS64_LO20 .L1 ++ 18: 03000085 lu52i.d \$a1, \$a0, 0 ++ 18: R_LARCH_ABS64_HI12 .L1 ++ 1c: 1a000004 pcalau12i \$a0, 0 ++ 1c: R_LARCH_PCALA_HI20 .L1 ++ 20: 02c00085 addi.d \$a1, \$a0, 0 ++ 20: R_LARCH_PCALA_LO12 .L1 ++ 24: 16000004 lu32i.d \$a0, 0 ++ 24: R_LARCH_PCALA64_LO20 .L1 ++ 28: 03000085 lu52i.d \$a1, \$a0, 0 ++ 28: R_LARCH_PCALA64_HI12 .L1 ++ 2c: 1a000004 pcalau12i \$a0, 0 ++ 2c: R_LARCH_GOT_PC_HI20 .L1 ++ 30: 28c00085 ld.d \$a1, \$a0, 0 ++ 30: R_LARCH_GOT_PC_LO12 .L1 ++ 34: 16000004 lu32i.d \$a0, 0 ++ 34: R_LARCH_GOT64_PC_LO20 .L1 ++ 38: 03000085 lu52i.d \$a1, \$a0, 0 ++ 38: R_LARCH_GOT64_PC_HI12 .L1 ++ 3c: 14000004 lu12i.w \$a0, 0 ++ 3c: R_LARCH_GOT_HI20 .L1 ++ 40: 03800084 ori \$a0, \$a0, 0x0 ++ 40: R_LARCH_GOT_LO12 .L1 ++ 44: 16000004 lu32i.d \$a0, 0 ++ 44: R_LARCH_GOT64_LO20 .L1 ++ 48: 03000085 lu52i.d \$a1, \$a0, 0 ++ 48: R_LARCH_GOT64_HI12 .L1 ++ 4c: 14000004 lu12i.w \$a0, 0 ++ 4c: R_LARCH_TLS_LE_HI20 TLSL1 ++ 50: 03800085 ori \$a1, \$a0, 0x0 ++ 50: R_LARCH_TLS_LE_LO12 TLSL1 ++ 54: 16000004 lu32i.d \$a0, 0 ++ 54: R_LARCH_TLS_LE64_LO20 TLSL1 ++ 58: 03000085 lu52i.d \$a1, \$a0, 0 ++ 58: R_LARCH_TLS_LE64_HI12 TLSL1 ++ 5c: 1a000004 pcalau12i \$a0, 0 ++ 5c: R_LARCH_TLS_IE_PC_HI20 TLSL1 ++ 60: 02c00005 li.d \$a1, 0 ++ 60: R_LARCH_TLS_IE_PC_LO12 TLSL1 ++ 64: 16000005 lu32i.d \$a1, 0 ++ 64: R_LARCH_TLS_IE64_PC_LO20 TLSL1 ++ 68: 030000a5 lu52i.d \$a1, \$a1, 0 ++ 68: R_LARCH_TLS_IE64_PC_HI12 TLSL1 ++ 6c: 14000004 lu12i.w \$a0, 0 ++ 6c: R_LARCH_TLS_IE_HI20 TLSL1 ++ 70: 03800084 ori \$a0, \$a0, 0x0 ++ 70: R_LARCH_TLS_IE_LO12 TLSL1 ++ 74: 16000004 lu32i.d \$a0, 0 ++ 74: R_LARCH_TLS_IE64_LO20 TLSL1 ++ 78: 03000084 lu52i.d \$a0, \$a0, 0 ++ 78: R_LARCH_TLS_IE64_HI12 TLSL1 ++ 7c: 1a000004 pcalau12i \$a0, 0 ++ 7c: R_LARCH_TLS_LD_PC_HI20 TLSL1 ++ 80: 14000004 lu12i.w \$a0, 0 ++ 80: R_LARCH_TLS_LD_HI20 TLSL1 ++ 84: 1a000004 pcalau12i \$a0, 0 ++ 84: R_LARCH_TLS_GD_PC_HI20 TLSL1 ++ 88: 14000004 lu12i.w \$a0, 0 ++ 88: R_LARCH_TLS_GD_HI20 TLSL1 ++ ++0+8c <.L1>: ++ 8c: 00000000 .word 0x00000000 ++ 8c: R_LARCH_32_PCREL .L2 ++ ++0+90 <.L2>: ++ ... ++ 90: R_LARCH_64_PCREL .L3 ++ ++0+98 <.L3>: ++ 98: 03400000 nop ++ 9c: 03400000 nop ++ 9c: R_LARCH_ALIGN .* ++ a0: 03400000 nop ++ a4: 03400000 nop ++ a8: 1800000c pcaddi \$t0, 0 ++ a8: R_LARCH_PCREL20_S2 .L1 ++ ac: 1e000001 pcaddu18i \$ra, 0 ++ ac: R_LARCH_CALL36 a ++ b0: 4c000021 jirl \$ra, \$ra, 0 ++ b4: 1a000004 pcalau12i \$a0, 0 ++ b4: R_LARCH_TLS_DESC_PC_HI20 TLSL1 ++ b8: 02c000a5 addi.d \$a1, \$a1, 0 ++ b8: R_LARCH_TLS_DESC_PC_LO12 TLSL1 ++ bc: 16000005 lu32i.d \$a1, 0 ++ bc: R_LARCH_TLS_DESC64_PC_LO20 TLSL1 ++ c0: 030000a5 lu52i.d \$a1, \$a1, 0 ++ c0: R_LARCH_TLS_DESC64_PC_HI12 TLSL1 ++ c4: 14000004 lu12i.w \$a0, 0 ++ c4: R_LARCH_TLS_DESC_HI20 TLSL1 ++ c8: 03800084 ori \$a0, \$a0, 0x0 ++ c8: R_LARCH_TLS_DESC_LO12 TLSL1 ++ cc: 16000004 lu32i.d \$a0, 0 ++ cc: R_LARCH_TLS_DESC64_LO20 TLSL1 ++ d0: 03000084 lu52i.d \$a0, \$a0, 0 ++ d0: R_LARCH_TLS_DESC64_HI12 TLSL1 ++ d4: 28c00081 ld.d \$ra, \$a0, 0 ++ d4: R_LARCH_TLS_DESC_LD TLSL1 ++ d8: 4c000021 jirl \$ra, \$ra, 0 ++ d8: R_LARCH_TLS_DESC_CALL TLSL1 ++ dc: 14000004 lu12i.w \$a0, 0 ++ dc: R_LARCH_TLS_LE_HI20_R TLSL1 ++ dc: R_LARCH_RELAX \*ABS\* ++ e0: 001090a5 add.d \$a1, \$a1, \$a0 ++ e0: R_LARCH_TLS_LE_ADD_R TLSL1 ++ e0: R_LARCH_RELAX \*ABS\* ++ e4: 29800085 st.w \$a1, \$a0, 0 ++ e4: R_LARCH_TLS_LE_LO12_R TLSL1 ++ e4: R_LARCH_RELAX \*ABS\* ++ e8: 14000004 lu12i.w \$a0, 0 ++ e8: R_LARCH_TLS_LE_HI20_R TLSL1 ++ e8: R_LARCH_RELAX \*ABS\* ++ ec: 001090a5 add.d \$a1, \$a1, \$a0 ++ ec: R_LARCH_TLS_LE_ADD_R TLSL1 ++ ec: R_LARCH_RELAX \*ABS\* ++ f0: 29800085 st.w \$a1, \$a0, 0 ++ f0: R_LARCH_TLS_LE_LO12_R TLSL1 ++ f0: R_LARCH_RELAX \*ABS\* ++ f4: 18000004 pcaddi \$a0, 0 ++ f4: R_LARCH_TLS_LD_PCREL20_S2 TLSL1 ++ f8: 18000004 pcaddi \$a0, 0 ++ f8: R_LARCH_TLS_GD_PCREL20_S2 TLSL1 ++ fc: 18000004 pcaddi \$a0, 0 ++ fc: R_LARCH_TLS_DESC_PCREL20_S2 TLSL1 +diff --git a/gas/testsuite/gas/loongarch/relocs_64.s b/gas/testsuite/gas/loongarch/relocs_64.s +new file mode 100644 +index 00000000..1d1548f5 +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/relocs_64.s +@@ -0,0 +1,109 @@ ++/* b16. */ ++jirl $r4,$r5,%b16(.L1) ++ ++/* b21. */ ++beqz $r4,%b21(.L1) ++ ++/* b26. */ ++b %b26(.L1) ++ ++/* lu12i.w. */ ++lu12i.w $r4,%abs_hi20(.L1) ++ ++/* ori */ ++ori $r4,$r5,%abs_lo12(.L1) ++ ++/* lu32i.d. */ ++lu32i.d $r4,%abs64_lo20(.L1) ++ ++/* lu52i.d. */ ++lu52i.d $r5,$r4,%abs64_hi12(.L1) ++ ++pcalau12i $r4,%pc_hi20(.L1) ++addi.d $r5,$r4,%pc_lo12(.L1) ++lu32i.d $r4,%pc64_lo20(.L1) ++lu52i.d $r5,$r4,%pc64_hi12(.L1) ++ ++pcalau12i $r4,%got_pc_hi20(.L1) ++ld.d $r5,$r4,%got_pc_lo12(.L1) ++lu32i.d $r4,%got64_pc_lo20(.L1) ++lu52i.d $r5,$r4,%got64_pc_hi12(.L1)
View file
_service:tar_scm:LoongArch-Add-gas-testsuit-for-alias-instructions.patch
Added
@@ -0,0 +1,104 @@ +From f2183b3edb1cee6d9fe0c3dbd26956501bcd6904 Mon Sep 17 00:00:00 2001 +From: Lulu Cai <cailulu@loongson.cn> +Date: Fri, 5 Jan 2024 11:41:27 +0800 +Subject: PATCH 062/123 LoongArch: Add gas testsuit for alias instructions + +Test the alias instructions. +--- + gas/testsuite/gas/loongarch/insn_alias_32.d | 19 +++++++++++++++++++ + gas/testsuite/gas/loongarch/insn_alias_32.s | 10 ++++++++++ + gas/testsuite/gas/loongarch/insn_alias_64.d | 20 ++++++++++++++++++++ + gas/testsuite/gas/loongarch/insn_alias_64.s | 11 +++++++++++ + 4 files changed, 60 insertions(+) + create mode 100644 gas/testsuite/gas/loongarch/insn_alias_32.d + create mode 100644 gas/testsuite/gas/loongarch/insn_alias_32.s + create mode 100644 gas/testsuite/gas/loongarch/insn_alias_64.d + create mode 100644 gas/testsuite/gas/loongarch/insn_alias_64.s + +diff --git a/gas/testsuite/gas/loongarch/insn_alias_32.d b/gas/testsuite/gas/loongarch/insn_alias_32.d +new file mode 100644 +index 00000000..753eae7a +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/insn_alias_32.d +@@ -0,0 +1,19 @@ ++#as: ++#objdump: -d -M no-aliases ++#skip: loongarch64-*-* ++ ++.* file format .* ++ ++ ++Disassembly of section .text: ++ ++0+ <L1>: ++ 0: 001500a4 or \$a0, \$a1, \$zero ++ 4: 02bffc04 addi.w \$a0, \$zero, -1 ++ 8: 03400000 andi \$zero, \$zero, 0x0 ++ c: 03800404 ori \$a0, \$zero, 0x1 ++ 10: 4c000020 jirl \$zero, \$ra, 0 ++ 14: 4c000020 jirl \$zero, \$ra, 0 ++ 18: 60000080 blt \$a0, \$zero, 0 # 18 <L1\+0x18> ++ 1c: 64000080 bge \$a0, \$zero, 0 # 1c <L1\+0x1c> ++ 20: 64000004 bge \$zero, \$a0, 0 # 20 <L1\+0x20> +diff --git a/gas/testsuite/gas/loongarch/insn_alias_32.s b/gas/testsuite/gas/loongarch/insn_alias_32.s +new file mode 100644 +index 00000000..8027e32a +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/insn_alias_32.s +@@ -0,0 +1,10 @@ ++L1: ++ move $a0,$a1 ++ li.w $a0,-1 ++ nop ++ li.w $a0,1 ++ ret ++ jr $ra ++ bltz $a0,.L1 ++ bgez $a0,.L1 ++ blez $a0,.L1 +diff --git a/gas/testsuite/gas/loongarch/insn_alias_64.d b/gas/testsuite/gas/loongarch/insn_alias_64.d +new file mode 100644 +index 00000000..8d3ed7bc +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/insn_alias_64.d +@@ -0,0 +1,20 @@ ++#as-new: ++#objdump: -d -M no-aliases ++#skip: loongarch32-*-* ++ ++.*: file format .* ++ ++ ++Disassembly of section .text: ++ ++0+ <L1>: ++ 0: 001500a4 or \$a0, \$a1, \$zero ++ 4: 02bffc04 addi.w \$a0, \$zero, -1 ++ 8: 02bffc04 addi.w \$a0, \$zero, -1 ++ c: 03400000 andi \$zero, \$zero, 0x0 ++ 10: 03800404 ori \$a0, \$zero, 0x1 ++ 14: 4c000020 jirl \$zero, \$ra, 0 ++ 18: 4c000020 jirl \$zero, \$ra, 0 ++ 1c: 60000080 blt \$a0, \$zero, 0 # 1c <L1\+0x1c> ++ 20: 64000080 bge \$a0, \$zero, 0 # 20 <L1\+0x20> ++ 24: 64000004 bge \$zero, \$a0, 0 # 24 <L1\+0x24> +diff --git a/gas/testsuite/gas/loongarch/insn_alias_64.s b/gas/testsuite/gas/loongarch/insn_alias_64.s +new file mode 100644 +index 00000000..e7e42638 +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/insn_alias_64.s +@@ -0,0 +1,11 @@ ++L1: ++ move $a0,$a1 ++ li.w $a0,-1 ++ li.d $a0,-1 ++ nop ++ li.w $a0,1 ++ ret ++ jr $ra ++ bltz $a0,.L1 ++ bgez $a0,.L1 ++ blez $a0,.L1 +-- +2.33.0 +
View file
_service:tar_scm:LoongArch-Add-gas-testsuit-for-lbt-lvz-instructions.patch
Added
@@ -0,0 +1,427 @@ +From 8b2478a4eab5b880516b32b5d478a1eab5be1f4c Mon Sep 17 00:00:00 2001 +From: Lulu Cai <cailulu@loongson.cn> +Date: Fri, 5 Jan 2024 11:58:34 +0800 +Subject: PATCH 063/123 LoongArch: Add gas testsuit for lbt/lvz instructions + +Test the LBT/LVZ instructions. Only LA64 supports +these instructions. +--- + gas/testsuite/gas/loongarch/insn_lbt.d | 186 +++++++++++++++++++++++++ + gas/testsuite/gas/loongarch/insn_lbt.s | 176 +++++++++++++++++++++++ + gas/testsuite/gas/loongarch/insn_lvz.d | 15 ++ + gas/testsuite/gas/loongarch/insn_lvz.s | 5 + + 4 files changed, 382 insertions(+) + create mode 100644 gas/testsuite/gas/loongarch/insn_lbt.d + create mode 100644 gas/testsuite/gas/loongarch/insn_lbt.s + create mode 100644 gas/testsuite/gas/loongarch/insn_lvz.d + create mode 100644 gas/testsuite/gas/loongarch/insn_lvz.s + +diff --git a/gas/testsuite/gas/loongarch/insn_lbt.d b/gas/testsuite/gas/loongarch/insn_lbt.d +new file mode 100644 +index 00000000..7d80fb89 +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/insn_lbt.d +@@ -0,0 +1,186 @@ ++#as: ++#objdump: -d ++#skip: loongarch32-*-* ++ ++.*: file format .* ++ ++ ++Disassembly of section .text: ++ ++0+ <.*>: ++ 0: 00000820 movgr2scr \$scr0, \$ra ++ 4: 00000c20 movscr2gr \$zero, \$scr1 ++ 8: 48006600 jiscr0 100 ++ c: 48006700 jiscr1 100 ++ 10: 00290420 addu12i.w \$zero, \$ra, 1 ++ 14: 00298420 addu12i.d \$zero, \$ra, 1 ++ 18: 00300820 adc.b \$zero, \$ra, \$tp ++ 1c: 00308820 adc.h \$zero, \$ra, \$tp ++ 20: 00310820 adc.w \$zero, \$ra, \$tp ++ 24: 00318820 adc.d \$zero, \$ra, \$tp ++ 28: 00320820 sbc.b \$zero, \$ra, \$tp ++ 2c: 00328820 sbc.h \$zero, \$ra, \$tp ++ 30: 00330820 sbc.w \$zero, \$ra, \$tp ++ 34: 00338820 sbc.d \$zero, \$ra, \$tp ++ 38: 001a0820 rotr.b \$zero, \$ra, \$tp ++ 3c: 001a8820 rotr.h \$zero, \$ra, \$tp ++ 40: 004c2420 rotri.b \$zero, \$ra, 0x1 ++ 44: 004c4420 rotri.h \$zero, \$ra, 0x1 ++ 48: 00340820 rcr.b \$zero, \$ra, \$tp ++ 4c: 00348820 rcr.h \$zero, \$ra, \$tp ++ 50: 00350820 rcr.w \$zero, \$ra, \$tp ++ 54: 00358820 rcr.d \$zero, \$ra, \$tp ++ 58: 00502420 rcri.b \$zero, \$ra, 0x1 ++ 5c: 00504420 rcri.h \$zero, \$ra, 0x1 ++ 60: 00508420 rcri.w \$zero, \$ra, 0x1 ++ 64: 00510420 rcri.d \$zero, \$ra, 0x1 ++ 68: 0114e420 fcvt.ud.d \$fa0, \$fa1 ++ 6c: 0114e020 fcvt.ld.d \$fa0, \$fa1 ++ 70: 01150820 fcvt.d.ld \$fa0, \$fa1, \$fa2 ++ 74: 2e800420 ldl.d \$zero, \$ra, 1 ++ 78: 2e000420 ldl.w \$zero, \$ra, 1 ++ 7c: 2e400420 ldr.w \$zero, \$ra, 1 ++ 80: 2ec00420 ldr.d \$zero, \$ra, 1 ++ 84: 2f000420 stl.w \$zero, \$ra, 1 ++ 88: 2f800420 stl.d \$zero, \$ra, 1 ++ 8c: 2f400420 str.w \$zero, \$ra, 1 ++ 90: 2fc00420 str.d \$zero, \$ra, 1 ++ 94: 003f040c x86adc.b \$zero, \$ra ++ 98: 003f040d x86adc.h \$zero, \$ra ++ 9c: 003f040e x86adc.w \$zero, \$ra ++ a0: 003f040f x86adc.d \$zero, \$ra ++ a4: 003f0404 x86add.b \$zero, \$ra ++ a8: 003f0405 x86add.h \$zero, \$ra ++ ac: 003f0406 x86add.w \$zero, \$ra ++ b0: 003f0407 x86add.d \$zero, \$ra ++ b4: 003f0400 x86add.wu \$zero, \$ra ++ b8: 003f0401 x86add.du \$zero, \$ra ++ bc: 00008000 x86inc.b \$zero ++ c0: 00008001 x86inc.h \$zero ++ c4: 00008002 x86inc.w \$zero ++ c8: 00008003 x86inc.d \$zero ++ cc: 003f0410 x86sbc.b \$zero, \$ra ++ d0: 003f0411 x86sbc.h \$zero, \$ra ++ d4: 003f0412 x86sbc.w \$zero, \$ra ++ d8: 003f0413 x86sbc.d \$zero, \$ra ++ dc: 003f0408 x86sub.b \$zero, \$ra ++ e0: 003f0409 x86sub.h \$zero, \$ra ++ e4: 003f040a x86sub.w \$zero, \$ra ++ e8: 003f040b x86sub.d \$zero, \$ra ++ ec: 003f0402 x86sub.wu \$zero, \$ra ++ f0: 003f0403 x86sub.du \$zero, \$ra ++ f4: 00008004 x86dec.b \$zero ++ f8: 00008005 x86dec.h \$zero ++ fc: 00008006 x86dec.w \$zero ++ 100: 00008007 x86dec.d \$zero ++ 104: 003f8410 x86and.b \$zero, \$ra ++ 108: 003f8411 x86and.h \$zero, \$ra ++ 10c: 003f8412 x86and.w \$zero, \$ra ++ 110: 003f8413 x86and.d \$zero, \$ra ++ 114: 003f8414 x86or.b \$zero, \$ra ++ 118: 003f8415 x86or.h \$zero, \$ra ++ 11c: 003f8416 x86or.w \$zero, \$ra ++ 120: 003f8417 x86or.d \$zero, \$ra ++ 124: 003f8418 x86xor.b \$zero, \$ra ++ 128: 003f8419 x86xor.h \$zero, \$ra ++ 12c: 003f841a x86xor.w \$zero, \$ra ++ 130: 003f841b x86xor.d \$zero, \$ra ++ 134: 003e8400 x86mul.b \$zero, \$ra ++ 138: 003e8401 x86mul.h \$zero, \$ra ++ 13c: 003e8402 x86mul.w \$zero, \$ra ++ 140: 003e8403 x86mul.d \$zero, \$ra ++ 144: 003e8404 x86mul.bu \$zero, \$ra ++ 148: 003e8405 x86mul.hu \$zero, \$ra ++ 14c: 003e8406 x86mul.wu \$zero, \$ra ++ 150: 003e8407 x86mul.du \$zero, \$ra ++ 154: 003f840c x86rcl.b \$zero, \$ra ++ 158: 003f840d x86rcl.h \$zero, \$ra ++ 15c: 003f840e x86rcl.w \$zero, \$ra ++ 160: 003f840f x86rcl.d \$zero, \$ra ++ 164: 00542418 x86rcli.b \$zero, 0x1 ++ 168: 00544419 x86rcli.h \$zero, 0x1 ++ 16c: 0054841a x86rcli.w \$zero, 0x1 ++ 170: 0055041b x86rcli.d \$zero, 0x1 ++ 174: 003f8408 x86rcr.b \$zero, \$ra ++ 178: 003f8409 x86rcr.h \$zero, \$ra ++ 17c: 003f840a x86rcr.w \$zero, \$ra ++ 180: 003f840b x86rcr.d \$zero, \$ra ++ 184: 00542410 x86rcri.b \$zero, 0x1 ++ 188: 00544411 x86rcri.h \$zero, 0x1 ++ 18c: 00548412 x86rcri.w \$zero, 0x1 ++ 190: 00550413 x86rcri.d \$zero, 0x1 ++ 194: 003f8404 x86rotl.b \$zero, \$ra ++ 198: 003f8405 x86rotl.h \$zero, \$ra ++ 19c: 003f8406 x86rotl.w \$zero, \$ra ++ 1a0: 003f8407 x86rotl.d \$zero, \$ra ++ 1a4: 00542414 x86rotli.b \$zero, 0x1 ++ 1a8: 00544415 x86rotli.h \$zero, 0x1 ++ 1ac: 00548416 x86rotli.w \$zero, 0x1 ++ 1b0: 00550417 x86rotli.d \$zero, 0x1 ++ 1b4: 003f8400 x86rotr.b \$zero, \$ra ++ 1b8: 003f8401 x86rotr.h \$zero, \$ra ++ 1bc: 003f8402 x86rotr.d \$zero, \$ra ++ 1c0: 003f8403 x86rotr.w \$zero, \$ra ++ 1c4: 0054240c x86rotri.b \$zero, 0x1 ++ 1c8: 0054440d x86rotri.h \$zero, 0x1 ++ 1cc: 0054840e x86rotri.w \$zero, 0x1 ++ 1d0: 0055040f x86rotri.d \$zero, 0x1 ++ 1d4: 003f0414 x86sll.b \$zero, \$ra ++ 1d8: 003f0415 x86sll.h \$zero, \$ra ++ 1dc: 003f0416 x86sll.w \$zero, \$ra ++ 1e0: 003f0417 x86sll.d \$zero, \$ra ++ 1e4: 00542400 x86slli.b \$zero, 0x1 ++ 1e8: 00544401 x86slli.h \$zero, 0x1 ++ 1ec: 00548402 x86slli.w \$zero, 0x1 ++ 1f0: 00550403 x86slli.d \$zero, 0x1 ++ 1f4: 003f0418 x86srl.b \$zero, \$ra ++ 1f8: 003f0419 x86srl.h \$zero, \$ra ++ 1fc: 003f041a x86srl.w \$zero, \$ra ++ 200: 003f041b x86srl.d \$zero, \$ra ++ 204: 00542404 x86srli.b \$zero, 0x1 ++ 208: 00544405 x86srli.h \$zero, 0x1 ++ 20c: 00548406 x86srli.w \$zero, 0x1 ++ 210: 00550407 x86srli.d \$zero, 0x1 ++ 214: 003f041c x86sra.b \$zero, \$ra ++ 218: 003f041d x86sra.h \$zero, \$ra ++ 21c: 003f041e x86sra.w \$zero, \$ra ++ 220: 003f041f x86sra.d \$zero, \$ra ++ 224: 00542408 x86srai.b \$zero, 0x1 ++ 228: 00544409 x86srai.h \$zero, 0x1 ++ 22c: 0054840a x86srai.w \$zero, 0x1 ++ 230: 0055040b x86srai.d \$zero, 0x1 ++ 234: 00368400 setx86j \$zero, 0x1 ++ 238: 00007820 setx86loope \$zero, \$ra ++ 23c: 00007c20 setx86loopne \$zero, \$ra ++ 240: 005c0400 x86mfflag \$zero, 0x1 ++ 244: 005c0420 x86mtflag \$zero, 0x1 ++ 248: 00007400 x86mftop \$zero ++ 24c: 00007020 x86mttop 0x1 ++ 250: 00008009 x86inctop ++ 254: 00008029 x86dectop ++ 258: 00008008 x86settm ++ 25c: 00008028 x86clrtm ++ 260: 00580420 x86settag \$zero, 0x1, 0x1 ++ 264: 00370411 armadd.w \$zero, \$ra, 0x1 ++ 268: 00378411 armsub.w \$zero, \$ra, 0x1 ++ 26c: 00380411 armadc.w \$zero, \$ra, 0x1 ++ 270: 00388411 armsbc.w \$zero, \$ra, 0x1 ++ 274: 00390411 armand.w \$zero, \$ra, 0x1 ++ 278: 00398411 armor.w \$zero, \$ra, 0x1 ++ 27c: 003a0411 armxor.w \$zero, \$ra, 0x1 ++ 280: 003fc41c armnot.w \$zero, 0x1 ++ 284: 003a8411 armsll.w \$zero, \$ra, 0x1 ++ 288: 003b0411 armsrl.w \$zero, \$ra, 0x1 ++ 28c: 003b8411 armsra.w \$zero, \$ra, 0x1 ++ 290: 003c0411 armrotr.w \$zero, \$ra, 0x1
View file
_service:tar_scm:LoongArch-Add-gas-testsuit-for-lsx-lasx-instructions.patch
Added
@@ -0,0 +1,2983 @@ +From a603a7896467eb497797ff323f3ad61105a1b416 Mon Sep 17 00:00:00 2001 +From: Lulu Cai <cailulu@loongson.cn> +Date: Fri, 5 Jan 2024 15:05:13 +0800 +Subject: PATCH 064/123 LoongArch: Add gas testsuit for lsx/lasx instructions + +Test the LSX/LASX instructions. Only LA64 supports +these instructions. +--- + gas/testsuite/gas/loongarch/insn_lasx.d | 737 +++++++++++++++++++++++ + gas/testsuite/gas/loongarch/insn_lasx.s | 727 +++++++++++++++++++++++ + gas/testsuite/gas/loongarch/insn_lsx.d | 742 ++++++++++++++++++++++++ + gas/testsuite/gas/loongarch/insn_lsx.s | 732 +++++++++++++++++++++++ + 4 files changed, 2938 insertions(+) + create mode 100644 gas/testsuite/gas/loongarch/insn_lasx.d + create mode 100644 gas/testsuite/gas/loongarch/insn_lasx.s + create mode 100644 gas/testsuite/gas/loongarch/insn_lsx.d + create mode 100644 gas/testsuite/gas/loongarch/insn_lsx.s + +diff --git a/gas/testsuite/gas/loongarch/insn_lasx.d b/gas/testsuite/gas/loongarch/insn_lasx.d +new file mode 100644 +index 00000000..74742b5f +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/insn_lasx.d +@@ -0,0 +1,737 @@ ++#as: ++#objdump: -d ++#skip: loongarch32-*-* ++ ++.*: file format .* ++ ++ ++Disassembly of section .text: ++ ++0+ <.*>: ++ 0: 0a118820 xvfmadd.s \$xr0, \$xr1, \$xr2, \$xr3 ++ 4: 0a518820 xvfmsub.s \$xr0, \$xr1, \$xr2, \$xr3 ++ 8: 0a918820 xvfnmadd.s \$xr0, \$xr1, \$xr2, \$xr3 ++ c: 0ad18820 xvfnmsub.s \$xr0, \$xr1, \$xr2, \$xr3 ++ 10: 0c900820 xvfcmp.caf.s \$xr0, \$xr1, \$xr2 ++ 14: 0c908820 xvfcmp.saf.s \$xr0, \$xr1, \$xr2 ++ 18: 0c910820 xvfcmp.clt.s \$xr0, \$xr1, \$xr2 ++ 1c: 0c918820 xvfcmp.slt.s \$xr0, \$xr1, \$xr2 ++ 20: 0c920820 xvfcmp.ceq.s \$xr0, \$xr1, \$xr2 ++ 24: 0c928820 xvfcmp.seq.s \$xr0, \$xr1, \$xr2 ++ 28: 0c930820 xvfcmp.cle.s \$xr0, \$xr1, \$xr2 ++ 2c: 0c938820 xvfcmp.sle.s \$xr0, \$xr1, \$xr2 ++ 30: 0c940820 xvfcmp.cun.s \$xr0, \$xr1, \$xr2 ++ 34: 0c948820 xvfcmp.sun.s \$xr0, \$xr1, \$xr2 ++ 38: 0c950820 xvfcmp.cult.s \$xr0, \$xr1, \$xr2 ++ 3c: 0c958820 xvfcmp.sult.s \$xr0, \$xr1, \$xr2 ++ 40: 0c960820 xvfcmp.cueq.s \$xr0, \$xr1, \$xr2 ++ 44: 0c968820 xvfcmp.sueq.s \$xr0, \$xr1, \$xr2 ++ 48: 0c970820 xvfcmp.cule.s \$xr0, \$xr1, \$xr2 ++ 4c: 0c978820 xvfcmp.sule.s \$xr0, \$xr1, \$xr2 ++ 50: 0c980820 xvfcmp.cne.s \$xr0, \$xr1, \$xr2 ++ 54: 0c988820 xvfcmp.sne.s \$xr0, \$xr1, \$xr2 ++ 58: 0c9a0820 xvfcmp.cor.s \$xr0, \$xr1, \$xr2 ++ 5c: 0c9a8820 xvfcmp.sor.s \$xr0, \$xr1, \$xr2 ++ 60: 0c9c0820 xvfcmp.cune.s \$xr0, \$xr1, \$xr2 ++ 64: 0c9c8820 xvfcmp.sune.s \$xr0, \$xr1, \$xr2 ++ 68: 0d218820 xvbitsel.v \$xr0, \$xr1, \$xr2, \$xr3 ++ 6c: 0d618820 xvshuf.b \$xr0, \$xr1, \$xr2, \$xr3 ++ 70: 0a218820 xvfmadd.d \$xr0, \$xr1, \$xr2, \$xr3 ++ 74: 0a618820 xvfmsub.d \$xr0, \$xr1, \$xr2, \$xr3 ++ 78: 0aa18820 xvfnmadd.d \$xr0, \$xr1, \$xr2, \$xr3 ++ 7c: 0ae18820 xvfnmsub.d \$xr0, \$xr1, \$xr2, \$xr3 ++ 80: 0ca00820 xvfcmp.caf.d \$xr0, \$xr1, \$xr2 ++ 84: 0ca08820 xvfcmp.saf.d \$xr0, \$xr1, \$xr2 ++ 88: 0ca10820 xvfcmp.clt.d \$xr0, \$xr1, \$xr2 ++ 8c: 0ca18820 xvfcmp.slt.d \$xr0, \$xr1, \$xr2 ++ 90: 0ca20820 xvfcmp.ceq.d \$xr0, \$xr1, \$xr2 ++ 94: 0ca28820 xvfcmp.seq.d \$xr0, \$xr1, \$xr2 ++ 98: 0ca30820 xvfcmp.cle.d \$xr0, \$xr1, \$xr2 ++ 9c: 0ca38820 xvfcmp.sle.d \$xr0, \$xr1, \$xr2 ++ a0: 0ca40820 xvfcmp.cun.d \$xr0, \$xr1, \$xr2 ++ a4: 0ca48820 xvfcmp.sun.d \$xr0, \$xr1, \$xr2 ++ a8: 0ca50820 xvfcmp.cult.d \$xr0, \$xr1, \$xr2 ++ ac: 0ca58820 xvfcmp.sult.d \$xr0, \$xr1, \$xr2 ++ b0: 0ca60820 xvfcmp.cueq.d \$xr0, \$xr1, \$xr2 ++ b4: 0ca68820 xvfcmp.sueq.d \$xr0, \$xr1, \$xr2 ++ b8: 0ca70820 xvfcmp.cule.d \$xr0, \$xr1, \$xr2 ++ bc: 0ca78820 xvfcmp.sule.d \$xr0, \$xr1, \$xr2 ++ c0: 0ca80820 xvfcmp.cne.d \$xr0, \$xr1, \$xr2 ++ c4: 0ca88820 xvfcmp.sne.d \$xr0, \$xr1, \$xr2 ++ c8: 0caa0820 xvfcmp.cor.d \$xr0, \$xr1, \$xr2 ++ cc: 0caa8820 xvfcmp.sor.d \$xr0, \$xr1, \$xr2 ++ d0: 0cac0820 xvfcmp.cune.d \$xr0, \$xr1, \$xr2 ++ d4: 0cac8820 xvfcmp.sune.d \$xr0, \$xr1, \$xr2 ++ d8: 2c800420 xvld \$xr0, \$ra, 1 ++ dc: 2cc00420 xvst \$xr0, \$ra, 1 ++ e0: 38480820 xvldx \$xr0, \$ra, \$tp ++ e4: 384c0820 xvstx \$xr0, \$ra, \$tp ++ e8: 3211f420 xvldrepl.d \$xr0, \$ra, 1000 ++ ec: 32206420 xvldrepl.w \$xr0, \$ra, 100 ++ f0: 32401420 xvldrepl.h \$xr0, \$ra, 10 ++ f4: 32800420 xvldrepl.b \$xr0, \$ra, 1 ++ f8: 3315f420 xvstelm.d \$xr0, \$ra, 1000, 0x1 ++ fc: 33246420 xvstelm.w \$xr0, \$ra, 100, 0x1 ++ 100: 33441420 xvstelm.h \$xr0, \$ra, 10, 0x1 ++ 104: 33840420 xvstelm.b \$xr0, \$ra, 1, 0x1 ++ 108: 74000820 xvseq.b \$xr0, \$xr1, \$xr2 ++ 10c: 74008820 xvseq.h \$xr0, \$xr1, \$xr2 ++ 110: 74010820 xvseq.w \$xr0, \$xr1, \$xr2 ++ 114: 74018820 xvseq.d \$xr0, \$xr1, \$xr2 ++ 118: 74020820 xvsle.b \$xr0, \$xr1, \$xr2 ++ 11c: 74028820 xvsle.h \$xr0, \$xr1, \$xr2 ++ 120: 74030820 xvsle.w \$xr0, \$xr1, \$xr2 ++ 124: 74038820 xvsle.d \$xr0, \$xr1, \$xr2 ++ 128: 74040820 xvsle.bu \$xr0, \$xr1, \$xr2 ++ 12c: 74048820 xvsle.hu \$xr0, \$xr1, \$xr2 ++ 130: 74050820 xvsle.wu \$xr0, \$xr1, \$xr2 ++ 134: 74058820 xvsle.du \$xr0, \$xr1, \$xr2 ++ 138: 74060820 xvslt.b \$xr0, \$xr1, \$xr2 ++ 13c: 74068820 xvslt.h \$xr0, \$xr1, \$xr2 ++ 140: 74070820 xvslt.w \$xr0, \$xr1, \$xr2 ++ 144: 74078820 xvslt.d \$xr0, \$xr1, \$xr2 ++ 148: 74080820 xvslt.bu \$xr0, \$xr1, \$xr2 ++ 14c: 74088820 xvslt.hu \$xr0, \$xr1, \$xr2 ++ 150: 74090820 xvslt.wu \$xr0, \$xr1, \$xr2 ++ 154: 74098820 xvslt.du \$xr0, \$xr1, \$xr2 ++ 158: 740a0820 xvadd.b \$xr0, \$xr1, \$xr2 ++ 15c: 740a8820 xvadd.h \$xr0, \$xr1, \$xr2 ++ 160: 740b0820 xvadd.w \$xr0, \$xr1, \$xr2 ++ 164: 740b8820 xvadd.d \$xr0, \$xr1, \$xr2 ++ 168: 740c0820 xvsub.b \$xr0, \$xr1, \$xr2 ++ 16c: 740c8820 xvsub.h \$xr0, \$xr1, \$xr2 ++ 170: 740d0820 xvsub.w \$xr0, \$xr1, \$xr2 ++ 174: 740d8820 xvsub.d \$xr0, \$xr1, \$xr2 ++ 178: 74460820 xvsadd.b \$xr0, \$xr1, \$xr2 ++ 17c: 74468820 xvsadd.h \$xr0, \$xr1, \$xr2 ++ 180: 74470820 xvsadd.w \$xr0, \$xr1, \$xr2 ++ 184: 74478820 xvsadd.d \$xr0, \$xr1, \$xr2 ++ 188: 74480820 xvssub.b \$xr0, \$xr1, \$xr2 ++ 18c: 74488820 xvssub.h \$xr0, \$xr1, \$xr2 ++ 190: 74490820 xvssub.w \$xr0, \$xr1, \$xr2 ++ 194: 74498820 xvssub.d \$xr0, \$xr1, \$xr2 ++ 198: 744a0820 xvsadd.bu \$xr0, \$xr1, \$xr2 ++ 19c: 744a8820 xvsadd.hu \$xr0, \$xr1, \$xr2 ++ 1a0: 744b0820 xvsadd.wu \$xr0, \$xr1, \$xr2 ++ 1a4: 744b8820 xvsadd.du \$xr0, \$xr1, \$xr2 ++ 1a8: 744c0820 xvssub.bu \$xr0, \$xr1, \$xr2 ++ 1ac: 744c8820 xvssub.hu \$xr0, \$xr1, \$xr2 ++ 1b0: 744d0820 xvssub.wu \$xr0, \$xr1, \$xr2 ++ 1b4: 744d8820 xvssub.du \$xr0, \$xr1, \$xr2 ++ 1b8: 74540820 xvhaddw.h.b \$xr0, \$xr1, \$xr2 ++ 1bc: 74548820 xvhaddw.w.h \$xr0, \$xr1, \$xr2 ++ 1c0: 74550820 xvhaddw.d.w \$xr0, \$xr1, \$xr2 ++ 1c4: 74558820 xvhaddw.q.d \$xr0, \$xr1, \$xr2 ++ 1c8: 74560820 xvhsubw.h.b \$xr0, \$xr1, \$xr2 ++ 1cc: 74568820 xvhsubw.w.h \$xr0, \$xr1, \$xr2 ++ 1d0: 74570820 xvhsubw.d.w \$xr0, \$xr1, \$xr2 ++ 1d4: 74578820 xvhsubw.q.d \$xr0, \$xr1, \$xr2 ++ 1d8: 74580820 xvhaddw.hu.bu \$xr0, \$xr1, \$xr2 ++ 1dc: 74588820 xvhaddw.wu.hu \$xr0, \$xr1, \$xr2 ++ 1e0: 74590820 xvhaddw.du.wu \$xr0, \$xr1, \$xr2 ++ 1e4: 74598820 xvhaddw.qu.du \$xr0, \$xr1, \$xr2 ++ 1e8: 745a0820 xvhsubw.hu.bu \$xr0, \$xr1, \$xr2 ++ 1ec: 745a8820 xvhsubw.wu.hu \$xr0, \$xr1, \$xr2 ++ 1f0: 745b0820 xvhsubw.du.wu \$xr0, \$xr1, \$xr2 ++ 1f4: 745b8820 xvhsubw.qu.du \$xr0, \$xr1, \$xr2 ++ 1f8: 741e0820 xvaddwev.h.b \$xr0, \$xr1, \$xr2 ++ 1fc: 741e8820 xvaddwev.w.h \$xr0, \$xr1, \$xr2 ++ 200: 741f0820 xvaddwev.d.w \$xr0, \$xr1, \$xr2 ++ 204: 741f8820 xvaddwev.q.d \$xr0, \$xr1, \$xr2 ++ 208: 742e0820 xvaddwev.h.bu \$xr0, \$xr1, \$xr2 ++ 20c: 742e8820 xvaddwev.w.hu \$xr0, \$xr1, \$xr2 ++ 210: 742f0820 xvaddwev.d.wu \$xr0, \$xr1, \$xr2 ++ 214: 742f8820 xvaddwev.q.du \$xr0, \$xr1, \$xr2 ++ 218: 743e0820 xvaddwev.h.bu.b \$xr0, \$xr1, \$xr2 ++ 21c: 743e8820 xvaddwev.w.hu.h \$xr0, \$xr1, \$xr2 ++ 220: 743f0820 xvaddwev.d.wu.w \$xr0, \$xr1, \$xr2 ++ 224: 743f8820 xvaddwev.q.du.d \$xr0, \$xr1, \$xr2 ++ 228: 74220820 xvaddwod.h.b \$xr0, \$xr1, \$xr2 ++ 22c: 74228820 xvaddwod.w.h \$xr0, \$xr1, \$xr2 ++ 230: 74230820 xvaddwod.d.w \$xr0, \$xr1, \$xr2 ++ 234: 74238820 xvaddwod.q.d \$xr0, \$xr1, \$xr2 ++ 238: 74320820 xvaddwod.h.bu \$xr0, \$xr1, \$xr2 ++ 23c: 74328820 xvaddwod.w.hu \$xr0, \$xr1, \$xr2 ++ 240: 74330820 xvaddwod.d.wu \$xr0, \$xr1, \$xr2 ++ 244: 74338820 xvaddwod.q.du \$xr0, \$xr1, \$xr2 ++ 248: 74400820 xvaddwod.h.bu.b \$xr0, \$xr1, \$xr2 ++ 24c: 74408820 xvaddwod.w.hu.h \$xr0, \$xr1, \$xr2 ++ 250: 74410820 xvaddwod.d.wu.w \$xr0, \$xr1, \$xr2 ++ 254: 74418820 xvaddwod.q.du.d \$xr0, \$xr1, \$xr2 ++ 258: 74ac0820 xvmaddwev.h.b \$xr0, \$xr1, \$xr2 ++ 25c: 74ac8820 xvmaddwev.w.h \$xr0, \$xr1, \$xr2 ++ 260: 74ad0820 xvmaddwev.d.w \$xr0, \$xr1, \$xr2 ++ 264: 74ad8820 xvmaddwev.q.d \$xr0, \$xr1, \$xr2 ++ 268: 74bc0820 xvmaddwev.h.bu.b \$xr0, \$xr1, \$xr2 ++ 26c: 74bc8820 xvmaddwev.w.hu.h \$xr0, \$xr1, \$xr2 ++ 270: 74bd0820 xvmaddwev.d.wu.w \$xr0, \$xr1, \$xr2 ++ 274: 74bd8820 xvmaddwev.q.du.d \$xr0, \$xr1, \$xr2 ++ 278: 74b40820 xvmaddwev.h.bu \$xr0, \$xr1, \$xr2 ++ 27c: 74b48820 xvmaddwev.w.hu \$xr0, \$xr1, \$xr2 ++ 280: 74b50820 xvmaddwev.d.wu \$xr0, \$xr1, \$xr2 ++ 284: 74b58820 xvmaddwev.q.du \$xr0, \$xr1, \$xr2 ++ 288: 74ae0820 xvmaddwod.h.b \$xr0, \$xr1, \$xr2 ++ 28c: 74ae8820 xvmaddwod.w.h \$xr0, \$xr1, \$xr2 ++ 290: 74af0820 xvmaddwod.d.w \$xr0, \$xr1, \$xr2
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_service:tar_scm:LoongArch-Add-mignore-start-align-option.patch
Added
@@ -0,0 +1,316 @@ +From 5b5553b3a8d81b48b5b6829165173fe158c3fe8f Mon Sep 17 00:00:00 2001 +From: mengqinggang <mengqinggang@loongson.cn> +Date: Sun, 7 Apr 2024 16:34:42 +0800 +Subject: PATCH 080/123 LoongArch: Add -mignore-start-align option + +Ignore .align at the start of a section may result in misalignment when +partial linking. Manually add -mignore-start-align option without partial +linking. + +Gcc -falign-functions add .align 5 to the start of a section, it causes some +error message mismatch. Set these testcases to xfail on LoongArch target. +--- + gas/config/tc-loongarch.c | 70 +++++++++++++------ + ...ign-first.d => relax-align-ignore-start.d} | 2 +- + ...ign-first.s => relax-align-ignore-start.s} | 0 + include/opcode/loongarch.h | 1 + + ld/testsuite/ld-elf/dwarf.exp | 5 ++ + .../ld-loongarch-elf/partial-link-align-a.s | 2 + + .../ld-loongarch-elf/partial-link-align-b.s | 3 + + ...ign-first.d => relax-align-ignore-start.d} | 1 + + ...ign-first.s => relax-align-ignore-start.s} | 0 + ld/testsuite/ld-loongarch-elf/relax.exp | 32 ++++++++- + ld/testsuite/ld-undefined/undefined.exp | 2 + + 11 files changed, 95 insertions(+), 23 deletions(-) + rename gas/testsuite/gas/loongarch/{relax-align-first.d => relax-align-ignore-start.d} (87%) + rename gas/testsuite/gas/loongarch/{relax-align-first.s => relax-align-ignore-start.s} (100%) + create mode 100644 ld/testsuite/ld-loongarch-elf/partial-link-align-a.s + create mode 100644 ld/testsuite/ld-loongarch-elf/partial-link-align-b.s + rename ld/testsuite/ld-loongarch-elf/{relax-align-first.d => relax-align-ignore-start.d} (92%) + rename ld/testsuite/ld-loongarch-elf/{relax-align-first.s => relax-align-ignore-start.s} (100%) + +diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c +index 110b92e4..f030fd07 100644 +--- a/gas/config/tc-loongarch.c ++++ b/gas/config/tc-loongarch.c +@@ -139,15 +139,17 @@ enum options + + OPTION_ABI, + OPTION_FLOAT_ABI, +- + OPTION_FLOAT_ISA, + + OPTION_LA_LOCAL_WITH_ABS, + OPTION_LA_GLOBAL_WITH_PCREL, + OPTION_LA_GLOBAL_WITH_ABS, ++ + OPTION_RELAX, + OPTION_NO_RELAX, ++ + OPTION_THIN_ADD_SUB, ++ OPTION_IGNORE_START_ALIGN, + + OPTION_END_OF_ENUM, + }; +@@ -165,6 +167,7 @@ struct option md_longopts = + { "mrelax", no_argument, NULL, OPTION_RELAX }, + { "mno-relax", no_argument, NULL, OPTION_NO_RELAX }, + { "mthin-add-sub", no_argument, NULL, OPTION_THIN_ADD_SUB}, ++ { "mignore-start-align", no_argument, NULL, OPTION_IGNORE_START_ALIGN}, + + { NULL, no_argument, NULL, 0 } + }; +@@ -247,6 +250,10 @@ md_parse_option (int c, const char *arg) + LARCH_opts.thin_add_sub = 1; + break; + ++ case OPTION_IGNORE_START_ALIGN: ++ LARCH_opts.ignore_start_align = 1; ++ break; ++ + case OPTION_IGNORE: + break; + +@@ -1772,7 +1779,9 @@ md_show_usage (FILE *stream) + -mthin-add-sub Convert a pair of R_LARCH_ADD32/64 and R_LARCH_SUB32/64 to\n\ + R_LARCH_32/64_PCREL as much as possible\n\ + The option does not affect the generation of R_LARCH_32_PCREL\n\ +- relocations in .eh_frame\n")); ++ relocations in .eh_frame\n\ ++ -mignore-start-align Ignore .align if it is at the start of a section. This option\n\ ++ can't be used when partial linking (ld -r).\n")); + } + + static void +@@ -1794,39 +1803,60 @@ bool + loongarch_frag_align_code (int n, int max) + { + char *nops; ++ expressionS ex; + symbolS *s = NULL; + +- bfd_vma insn_alignment = 4; +- bfd_vma bytes = (bfd_vma) 1 << n; +- bfd_vma worst_case_bytes = bytes - insn_alignment; ++ /* When not relaxing, loongarch_handle_align handles code alignment. */ ++ if (!LARCH_opts.relax) ++ return false; ++ ++ bfd_vma align_bytes = (bfd_vma) 1 << n; ++ bfd_vma worst_case_bytes = align_bytes - 4; ++ bfd_vma addend = worst_case_bytes; ++ bool align_max = max > 0 && (bfd_vma) max < worst_case_bytes; + + /* If we are moving to a smaller alignment than the instruction size, then no + alignment is required. */ +- if (bytes <= insn_alignment) ++ if (align_bytes <= 4) + return true; + +- /* When not relaxing, loongarch_handle_align handles code alignment. */ +- if (!LARCH_opts.relax) +- return false; +- + /* If max <= 0, ignore max. + If max >= worst_case_bytes, max has no effect. + Similar to gas/write.c relax_segment function rs_align_code case: + if (fragP->fr_subtype != 0 && offset > fragP->fr_subtype). */ +- if (max > 0 && (bfd_vma) max < worst_case_bytes) ++ if (align_max) + { + s = symbol_find (now_seg->name); +- worst_case_bytes = ALIGN_MAX_ADDEND (n, max); ++ addend = ALIGN_MAX_ADDEND (n, max); ++ } ++ ++ if (LARCH_opts.ignore_start_align) ++ { ++ frag_grow (worst_case_bytes); ++ /* Use relaxable frag for .align. ++ If .align at the start of section, do nothing. Section alignment can ++ ensure correct alignment. ++ If .align is not at the start of a section, reserve NOP instructions ++ and R_LARCH_ALIGN relocation. */ ++ nops = frag_var (rs_machine_dependent, worst_case_bytes, worst_case_bytes, ++ rs_align_code, s, addend, NULL); + } ++ else ++ { ++ nops = frag_more (worst_case_bytes); ++ if (align_max) ++ { ++ ex.X_add_symbol = s; ++ ex.X_op = O_symbol; ++ } ++ else ++ ex.X_op = O_constant; ++ ++ ex.X_add_number = addend; + +- frag_grow (worst_case_bytes); +- /* Use relaxable frag for .align. +- If .align at the start of section, do nothing. Section alignment can +- ensure correct alignment. +- If .align is not at the start of a section, reserve NOP instructions +- and R_LARCH_ALIGN relocation. */ +- nops = frag_var (rs_machine_dependent, worst_case_bytes, worst_case_bytes, +- rs_align_code, s, worst_case_bytes, NULL); ++ fix_new_exp (frag_now, nops - frag_now->fr_literal, 0, ++ &ex, false, BFD_RELOC_LARCH_ALIGN); ++ } + + /* Default write NOP for aligned bytes. */ + loongarch_make_nops (nops, worst_case_bytes); +diff --git a/gas/testsuite/gas/loongarch/relax-align-first.d b/gas/testsuite/gas/loongarch/relax-align-ignore-start.d +similarity index 87% +rename from gas/testsuite/gas/loongarch/relax-align-first.d +rename to gas/testsuite/gas/loongarch/relax-align-ignore-start.d +index ec0698b6..0a67392d 100644 +--- a/gas/testsuite/gas/loongarch/relax-align-first.d ++++ b/gas/testsuite/gas/loongarch/relax-align-ignore-start.d +@@ -1,4 +1,4 @@ +-#as: ++#as: -mignore-start-align + #objdump: -dr + + .*: +file format .* +diff --git a/gas/testsuite/gas/loongarch/relax-align-first.s b/gas/testsuite/gas/loongarch/relax-align-ignore-start.s +similarity index 100% +rename from gas/testsuite/gas/loongarch/relax-align-first.s +rename to gas/testsuite/gas/loongarch/relax-align-ignore-start.s +diff --git a/include/opcode/loongarch.h b/include/opcode/loongarch.h +index 5fc6e190..024ba99c 100644 +--- a/include/opcode/loongarch.h ++++ b/include/opcode/loongarch.h +@@ -256,6 +256,7 @@ dec2 : 1-90-9? + + int relax; + int thin_add_sub; ++ int ignore_start_align; + } LARCH_opts; + + extern size_t loongarch_insn_length (insn_t insn); +diff --git a/ld/testsuite/ld-elf/dwarf.exp b/ld/testsuite/ld-elf/dwarf.exp +index 3d1b99ac..5cb2aab9 100644 +--- a/ld/testsuite/ld-elf/dwarf.exp ++++ b/ld/testsuite/ld-elf/dwarf.exp +@@ -52,6 +52,9 @@ set build_tests { + {"DWARF parse during linker error" + "" "-fno-toplevel-reorder"
View file
_service:tar_scm:LoongArch-Add-more-relaxation-support-for-call36.patch
Added
@@ -0,0 +1,266 @@ +From 0638980f66ece88b89b96746aba82c1f5cd6d6eb Mon Sep 17 00:00:00 2001 +From: mengqinggang <mengqinggang@loongson.cn> +Date: Thu, 10 Oct 2024 16:23:30 +0800 +Subject: PATCH 117/123 LoongArch: Add more relaxation support for call36 + +Add relaxation support for call36 that jump to PLT entry. + +Add relaxation support for call36 with IFUNC symbol. + +Add relaxation support for call36 that jump to undefweak symbol. +For undefweak symbol, it can always be relaxed if it have no PLT entry. +Because we set the address of undefweak symbol without PLT entry to PC +like relocate_section. +--- + bfd/elfnn-loongarch.c | 21 +++- + .../ld-loongarch-elf/relax-call36-exe.s | 32 ++++++ + .../ld-loongarch-elf/relax-call36-so.s | 35 ++++++ + ld/testsuite/ld-loongarch-elf/relax.exp | 105 ++++++++++++++++++ + 4 files changed, 190 insertions(+), 3 deletions(-) + create mode 100644 ld/testsuite/ld-loongarch-elf/relax-call36-exe.s + create mode 100644 ld/testsuite/ld-loongarch-elf/relax-call36-so.s + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index 70522fae..890233d1 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -5434,7 +5434,8 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, + Elf_Internal_Sym *sym = (Elf_Internal_Sym *)symtab_hdr->contents + + r_symndx; + +- if (ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC) ++ if (ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC ++ && r_type != R_LARCH_CALL36) + continue; + + /* Only TLS instruction sequences that are accompanied by +@@ -5467,8 +5468,8 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, + } + else + { +- /* Disable the relaxation for ifunc. */ +- if (h != NULL && h->type == STT_GNU_IFUNC) ++ if (h != NULL && h->type == STT_GNU_IFUNC ++ && r_type != R_LARCH_CALL36) + continue; + + /* The GOT entry of tls symbols must in current execute file or +@@ -5485,6 +5486,20 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, + && GOT_TLS_GD_BOTH_P (tls_type)) + symval += 2 * GOT_ENTRY_SIZE; + } ++ else if (h->plt.offset != MINUS_ONE) ++ { ++ sym_sec = htab->elf.splt ? htab->elf.splt : htab->elf.iplt; ++ symval = h->plt.offset; ++ } ++ /* Like loongarch_elf_relocate_section, set relocation(offset) to 0. ++ Undefweak for other relocations handing in the future. */ ++ else if (h->root.type == bfd_link_hash_undefweak ++ && !h->root.linker_def ++ && r_type == R_LARCH_CALL36) ++ { ++ sym_sec = sec; ++ symval = rel->r_offset; ++ } + else if ((h->root.type == bfd_link_hash_defined + || h->root.type == bfd_link_hash_defweak) + && h->root.u.def.section != NULL +diff --git a/ld/testsuite/ld-loongarch-elf/relax-call36-exe.s b/ld/testsuite/ld-loongarch-elf/relax-call36-exe.s +new file mode 100644 +index 00000000..26cff4df +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/relax-call36-exe.s +@@ -0,0 +1,32 @@ ++ldd: # local define default ++call36 ldd # ldd ++ ++ldh: # local define hidden ++.hidden ldh ++call36 ldh # ldh ++ ++gdd: ++.global gdd # global define default ++call36 gdd # gdd@plt ++ ++gdh: ++.global gdh # global define hidden ++.hidden gdh ++call36 gdh # gdh ++ ++wdd: ++.weak wdd # weak define default ++call36 wdd # wdd@plt ++ ++.weak wud # weak undefine default ++call36 wud # wud@plt ++ ++wdh: ++.weak wdh # weak define hidden ++.hidden wdh ++call36 wdh # wdh ++ ++.weak wuh # weak undefine hidden ++.hidden wuh ++call36 wuh # wuh ++ +diff --git a/ld/testsuite/ld-loongarch-elf/relax-call36-so.s b/ld/testsuite/ld-loongarch-elf/relax-call36-so.s +new file mode 100644 +index 00000000..050273b0 +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/relax-call36-so.s +@@ -0,0 +1,35 @@ ++ldd: # local define default ++call36 ldd # ldd ++ ++ldh: # local define hidden ++.hidden ldh ++call36 ldh # ldh ++ ++gdd: ++.global gdd # global define default ++call36 gdd # gdd@plt ++ ++.global gud # global undefine default ++call36 gud # gud@plt ++ ++gdh: ++.global gdh # global define hidden ++.hidden gdh ++call36 gdh # gdh ++ ++wdd: ++.weak wdd # weak define default ++call36 wdd # wdd@plt ++ ++.weak wud # weak undefine default ++call36 wud # wud@plt ++ ++wdh: ++.weak wdh # weak define hidden ++.hidden wdh ++call36 wdh # wdh ++ ++.weak wuh # weak undefine hidden ++.hidden wuh ++call36 wuh # wuh ++ +diff --git a/ld/testsuite/ld-loongarch-elf/relax.exp b/ld/testsuite/ld-loongarch-elf/relax.exp +index 05b268f4..57ea3877 100644 +--- a/ld/testsuite/ld-loongarch-elf/relax.exp ++++ b/ld/testsuite/ld-loongarch-elf/relax.exp +@@ -51,6 +51,111 @@ if istarget loongarch64-*-* { + run_dump_test "relax-align-ignore-start" + run_partial_linking_align_test + ++ run_ld_link_tests \ ++ list \ ++ list \ ++ "loongarch relax call36 .so build" \ ++ "-shared" "" \ ++ "" \ ++ {relax-call36-so.s} \ ++ {} \ ++ "relax-call36.so" \ ++ \ ++ ++ ++ if file exist "tmpdir/relax-call36.so" { ++ set objdump_output run_host_cmd "objdump" "-d tmpdir/relax-call36.so" ++ if { regexp "pcaddu18i" $objdump_output } { ++ fail "loongarch relax call36 so" ++ } { ++ pass "loongarch relax call36 so" ++ } ++ } ++ ++ run_ld_link_tests \ ++ list \ ++ list \ ++ "loongarch relax call36 dyn exe build" \ ++ "-pie -e 0" "" \ ++ "" \ ++ {relax-call36-exe.s} \ ++ {} \ ++ "relax-call36-d.exe" \ ++ \ ++ ++ ++ if file exist "tmpdir/relax-call36-d.exe" { ++ set objdump_output run_host_cmd "objdump" "-d tmpdir/relax-call36-d.exe" ++ if { regexp "pcaddu18i" $objdump_output } { ++ fail "loongarch relax call36 dyn exe" ++ } { ++ pass "loongarch relax call36 dyn exe" ++ } ++ } ++ ++ run_ld_link_tests \ ++ list \
View file
_service:tar_scm:LoongArch-Add-new-relocation-R_LARCH_CALL36.patch
Added
@@ -0,0 +1,278 @@ +From 27daffe58e9d1494a1e3c66813526ec4e8e8480b Mon Sep 17 00:00:00 2001 +From: mengqinggang <mengqinggang@loongson.cn> +Date: Thu, 28 Sep 2023 16:41:15 +0800 +Subject: PATCH 020/123 LoongArch: Add new relocation R_LARCH_CALL36 + +R_LARCH_CALL36 is used for medium code model function call pcaddu18i+jirl, and +these two instructions must adjacent. + +The LoongArch ABI v2.20 at here: https://github.com/loongson/la-abi-specs. +--- + bfd/bfd-in2.h | 4 +++- + bfd/elfnn-loongarch.c | 19 ++++++++++----- + bfd/elfxx-loongarch.c | 24 +++++++++++++++++++ + bfd/libbfd.h | 1 + + bfd/reloc.c | 3 +++ + gas/config/tc-loongarch.c | 6 ++++- + gas/testsuite/gas/loongarch/medium-call.d | 15 ++++++++++++ + gas/testsuite/gas/loongarch/medium-call.s | 6 +++++ + include/elf/loongarch.h | 2 ++ + .../ld-loongarch-elf/ld-loongarch-elf.exp | 12 ++++++++++ + ld/testsuite/ld-loongarch-elf/medium-call.s | 7 ++++++ + 11 files changed, 91 insertions(+), 8 deletions(-) + create mode 100644 gas/testsuite/gas/loongarch/medium-call.d + create mode 100644 gas/testsuite/gas/loongarch/medium-call.s + create mode 100644 ld/testsuite/ld-loongarch-elf/medium-call.s + +diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h +index 933b8ec2..86e7139f 100644 +--- a/bfd/bfd-in2.h ++++ b/bfd/bfd-in2.h +@@ -7343,7 +7343,9 @@ assembler and not (currently) written to any object files. */ + BFD_RELOC_LARCH_ADD_ULEB128, + BFD_RELOC_LARCH_SUB_ULEB128, + BFD_RELOC_LARCH_64_PCREL, +- BFD_RELOC_UNUSED }; ++ BFD_RELOC_LARCH_CALL36, ++ BFD_RELOC_UNUSED ++}; + typedef enum bfd_reloc_code_real bfd_reloc_code_real_type; + + reloc_howto_type *bfd_reloc_type_lookup +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index 09c98713..20dd0640 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -780,6 +780,7 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, + case R_LARCH_B16: + case R_LARCH_B21: + case R_LARCH_B26: ++ case R_LARCH_CALL36: + if (h != NULL) + { + h->needs_plt = 1; +@@ -1884,20 +1885,24 @@ loongarch_check_offset (const Elf_Internal_Rela *rel, + ret; \ + }) + ++/* Write immediate to instructions. */ ++ + static bfd_reloc_status_type + loongarch_reloc_rewrite_imm_insn (const Elf_Internal_Rela *rel, + const asection *input_section ATTRIBUTE_UNUSED, + reloc_howto_type *howto, bfd *input_bfd, + bfd_byte *contents, bfd_vma reloc_val) + { +- int bits = bfd_get_reloc_size (howto) * 8; +- uint32_t insn = bfd_get (bits, input_bfd, contents + rel->r_offset); +- ++ /* Adjust the immediate based on alignment and ++ its position in the instruction. */ + if (!loongarch_adjust_reloc_bitsfield (input_bfd, howto, &reloc_val)) + return bfd_reloc_overflow; + +- insn = (insn & (uint32_t)howto->src_mask) +- | ((insn & (~(uint32_t)howto->dst_mask)) | reloc_val); ++ int bits = bfd_get_reloc_size (howto) * 8; ++ uint64_t insn = bfd_get (bits, input_bfd, contents + rel->r_offset); ++ ++ /* Write immediate to instruction. */ ++ insn = (insn & ~howto->dst_mask) | (reloc_val & howto->dst_mask); + + bfd_put (bits, input_bfd, insn, contents + rel->r_offset); + +@@ -2120,6 +2125,7 @@ perform_relocation (const Elf_Internal_Rela *rel, asection *input_section, + case R_LARCH_TLS_GD_PC_HI20: + case R_LARCH_TLS_GD_HI20: + case R_LARCH_PCREL20_S2: ++ case R_LARCH_CALL36: + r = loongarch_check_offset (rel, input_section); + if (r != bfd_reloc_ok) + break; +@@ -3120,9 +3126,10 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, + break; + + /* New reloc types. */ ++ case R_LARCH_B16: + case R_LARCH_B21: + case R_LARCH_B26: +- case R_LARCH_B16: ++ case R_LARCH_CALL36: + unresolved_reloc = false; + if (is_undefweak) + { +diff --git a/bfd/elfxx-loongarch.c b/bfd/elfxx-loongarch.c +index 7f298c08..d93b7904 100644 +--- a/bfd/elfxx-loongarch.c ++++ b/bfd/elfxx-loongarch.c +@@ -1547,6 +1547,24 @@ static loongarch_reloc_howto_type loongarch_howto_table = + NULL, /* adjust_reloc_bits */ + NULL), /* larch_reloc_type_name */ + ++ /* Used for medium code model function call pcaddu18i+jirl, ++ these two instructions must adjacent. */ ++ LOONGARCH_HOWTO (R_LARCH_CALL36, /* type (110). */ ++ 2, /* rightshift. */ ++ 8, /* size. */ ++ 36, /* bitsize. */ ++ true, /* pc_relative. */ ++ 0, /* bitpos. */ ++ complain_overflow_signed, /* complain_on_overflow. */ ++ bfd_elf_generic_reloc, /* special_function. */ ++ "R_LARCH_CALL36", /* name. */ ++ false, /* partial_inplace. */ ++ 0, /* src_mask. */ ++ 0x03fffc0001ffffe0, /* dst_mask. */ ++ false, /* pcrel_offset. */ ++ BFD_RELOC_LARCH_CALL36, /* bfd_reloc_code_real_type. */ ++ reloc_sign_bits, /* adjust_reloc_bits. */ ++ "call36"), /* larch_reloc_type_name. */ + }; + + reloc_howto_type * +@@ -1726,6 +1744,12 @@ reloc_sign_bits (bfd *abfd, reloc_howto_type *howto, bfd_vma *fix_val) + /* Perform insn bits field. 15:0<<10, 20:16>>16. */ + val = ((val & 0xffff) << 10) | ((val >> 16) & 0x1f); + break; ++ case R_LARCH_CALL36: ++ /* 0x8000: If low 16-bit immediate greater than 0x7fff, ++ it become to a negative number due to sign-extended, ++ so the high part need to add 0x8000. */ ++ val = (((val + 0x8000) >> 16) << 5) | (((val & 0xffff) << 10) << 32); ++ break; + default: + val <<= howto->bitpos; + break; +diff --git a/bfd/libbfd.h b/bfd/libbfd.h +index d4fb3107..297f3048 100644 +--- a/bfd/libbfd.h ++++ b/bfd/libbfd.h +@@ -3525,6 +3525,7 @@ static const char *const bfd_reloc_code_real_names = { "@@uninitialized@@", + "BFD_RELOC_LARCH_ADD_ULEB128", + "BFD_RELOC_LARCH_SUB_ULEB128", + "BFD_RELOC_LARCH_64_PCREL", ++ "BFD_RELOC_LARCH_CALL36", + "@@overflow: BFD_RELOC_UNUSED@@", + }; + #endif +diff --git a/bfd/reloc.c b/bfd/reloc.c +index fbc67ac7..70004f04 100644 +--- a/bfd/reloc.c ++++ b/bfd/reloc.c +@@ -8156,6 +8156,9 @@ ENUMX + ENUMX + BFD_RELOC_LARCH_64_PCREL + ++ENUMX ++ BFD_RELOC_LARCH_CALL36 ++ + ENUMDOC + LARCH relocations. + +diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c +index 59232832..367a0b6c 100644 +--- a/gas/config/tc-loongarch.c ++++ b/gas/config/tc-loongarch.c +@@ -682,7 +682,7 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2, + esc_ch1, esc_ch2, bit_field, arg); + + if (ip->reloc_info0.type >= BFD_RELOC_LARCH_B16 +- && ip->reloc_info0.type < BFD_RELOC_LARCH_64_PCREL) ++ && ip->reloc_info0.type < BFD_RELOC_UNUSED) + { + /* As we compact stack-relocs, it is no need for pop operation. + But break out until here in order to check the imm field. +@@ -956,6 +956,10 @@ move_insn (struct loongarch_cl_insn *insn, fragS *frag, long where) + static void + append_fixed_insn (struct loongarch_cl_insn *insn) + { ++ /* Ensure the jirl is emitted to the same frag as the pcaddu18i. */ ++ if (BFD_RELOC_LARCH_CALL36 == insn->reloc_info0.type) ++ frag_grow (8); ++ + char *f = frag_more (insn->insn_length); + move_insn (insn, frag_now, f - frag_now->fr_literal); + } +diff --git a/gas/testsuite/gas/loongarch/medium-call.d b/gas/testsuite/gas/loongarch/medium-call.d +new file mode 100644 +index 00000000..4183818c +--- /dev/null
View file
_service:tar_scm:LoongArch-Add-new-relocs-and-macro-for-TLSDESC.patch
Added
@@ -0,0 +1,510 @@ +From a7cc512b2871a9ba63967eaa9f7b91f41baed858 Mon Sep 17 00:00:00 2001 +From: Lulu Cai <cailulu@loongson.cn> +Date: Tue, 31 Oct 2023 16:11:29 +0800 +Subject: PATCH 025/123 LoongArch: Add new relocs and macro for TLSDESC. + +The normal DESC instruction sequence is: + pcalau12i $a0,%desc_pc_hi20(var) #R_LARCH_TLS_DESC_PC_HI20 + addi.d $a0,$a0,%desc_pc_lo12(var) #R_LARCH_TLS_DESC_PC_LO12 + ld.d $ra,$a0,%desc_ld(var) #R_LARCH_TLS_DESC_LD + jirl $ra,$ra,%desc_call(var) #R_LARCH_TLS_DESC_CALL + add.d $a0,$a0,$tp +--- + bfd/bfd-in2.h | 12 +++ + bfd/elfxx-loongarch.c | 210 +++++++++++++++++++++++++++++++++++++- + bfd/libbfd.h | 12 +++ + bfd/reloc.c | 29 ++++++ + gas/config/tc-loongarch.c | 14 ++- + include/elf/loongarch.h | 22 +++- + opcodes/loongarch-opc.c | 54 ++++++++++ + 7 files changed, 349 insertions(+), 4 deletions(-) + +diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h +index 86e7139f..d210e71b 100644 +--- a/bfd/bfd-in2.h ++++ b/bfd/bfd-in2.h +@@ -7260,6 +7260,8 @@ assembler and not (currently) written to any object files. */ + BFD_RELOC_LARCH_TLS_DTPREL64, + BFD_RELOC_LARCH_TLS_TPREL32, + BFD_RELOC_LARCH_TLS_TPREL64, ++ BFD_RELOC_LARCH_TLS_DESC32, ++ BFD_RELOC_LARCH_TLS_DESC64, + BFD_RELOC_LARCH_MARK_LA, + BFD_RELOC_LARCH_MARK_PCREL, + BFD_RELOC_LARCH_SOP_PUSH_PCREL, +@@ -7344,6 +7346,16 @@ assembler and not (currently) written to any object files. */ + BFD_RELOC_LARCH_SUB_ULEB128, + BFD_RELOC_LARCH_64_PCREL, + BFD_RELOC_LARCH_CALL36, ++ BFD_RELOC_LARCH_TLS_DESC_PC_HI20, ++ BFD_RELOC_LARCH_TLS_DESC_PC_LO12, ++ BFD_RELOC_LARCH_TLS_DESC64_PC_LO20, ++ BFD_RELOC_LARCH_TLS_DESC64_PC_HI12, ++ BFD_RELOC_LARCH_TLS_DESC_HI20, ++ BFD_RELOC_LARCH_TLS_DESC_LO12, ++ BFD_RELOC_LARCH_TLS_DESC64_LO20, ++ BFD_RELOC_LARCH_TLS_DESC64_HI12, ++ BFD_RELOC_LARCH_TLS_DESC_LD, ++ BFD_RELOC_LARCH_TLS_DESC_CALL, + BFD_RELOC_UNUSED + }; + typedef enum bfd_reloc_code_real bfd_reloc_code_real_type; +diff --git a/bfd/elfxx-loongarch.c b/bfd/elfxx-loongarch.c +index 679b79f3..30a941a8 100644 +--- a/bfd/elfxx-loongarch.c ++++ b/bfd/elfxx-loongarch.c +@@ -293,8 +293,40 @@ static loongarch_reloc_howto_type loongarch_howto_table = + NULL, /* adjust_reloc_bits */ + NULL), /* larch_reloc_type_name */ + +- LOONGARCH_EMPTY_HOWTO (13), +- LOONGARCH_EMPTY_HOWTO (14), ++ LOONGARCH_HOWTO (R_LARCH_TLS_DESC32, /* type (13). */ ++ 0, /* rightshift. */ ++ 4, /* size. */ ++ 32, /* bitsize. */ ++ false, /* pc_relative. */ ++ 0, /* bitpos. */ ++ complain_overflow_dont, /* complain_on_overflow. */ ++ bfd_elf_generic_reloc, /* special_function. */ ++ "R_LARCH_TLS_DESC32", /* name. */ ++ false, /* partial_inplace. */ ++ 0, /* src_mask. */ ++ ALL_ONES, /* dst_mask. */ ++ false, /* pcrel_offset. */ ++ BFD_RELOC_LARCH_TLS_DESC32, /* bfd_reloc_code_real_type. */ ++ NULL, /* adjust_reloc_bits. */ ++ NULL), /* larch_reloc_type_name. */ ++ ++ LOONGARCH_HOWTO (R_LARCH_TLS_DESC64, /* type (14). */ ++ 0, /* rightshift. */ ++ 4, /* size. */ ++ 64, /* bitsize. */ ++ false, /* pc_relative. */ ++ 0, /* bitpos. */ ++ complain_overflow_dont, /* complain_on_overflow. */ ++ bfd_elf_generic_reloc, /* special_function. */ ++ "R_LARCH_TLS_DESC64", /* name. */ ++ false, /* partial_inplace. */ ++ 0, /* src_mask. */ ++ ALL_ONES, /* dst_mask. */ ++ false, /* pcrel_offset. */ ++ BFD_RELOC_LARCH_TLS_DESC64, /* bfd_reloc_code_real_type. */ ++ NULL, /* adjust_reloc_bits. */ ++ NULL), /* larch_reloc_type_name. */ ++ + LOONGARCH_EMPTY_HOWTO (15), + LOONGARCH_EMPTY_HOWTO (16), + LOONGARCH_EMPTY_HOWTO (17), +@@ -1569,6 +1601,180 @@ static loongarch_reloc_howto_type loongarch_howto_table = + BFD_RELOC_LARCH_CALL36, /* bfd_reloc_code_real_type. */ + reloc_sign_bits, /* adjust_reloc_bits. */ + "call36"), /* larch_reloc_type_name. */ ++ ++ /* TLS_DESC PCREL. */ ++ LOONGARCH_HOWTO (R_LARCH_TLS_DESC_PC_HI20, /* type (111). */ ++ 12, /* rightshift. */ ++ 4, /* size. */ ++ 20, /* bitsize. */ ++ true, /* pc_relative. */ ++ 5, /* bitpos. */ ++ complain_overflow_signed, /* complain_on_overflow. */ ++ bfd_elf_generic_reloc, /* special_function. */ ++ "R_LARCH_TLS_DESC_PC_HI20", /* name. */ ++ false, /* partial_inplace. */ ++ 0, /* src_mask. */ ++ 0x1ffffe0, /* dst_mask. */ ++ false, /* pcrel_offset. */ ++ BFD_RELOC_LARCH_TLS_DESC_PC_HI20, /* bfd_reloc_code_real_type. */ ++ reloc_bits, /* adjust_reloc_bits. */ ++ "desc_pc_hi20"), /* larch_reloc_type_name. */ ++ ++ LOONGARCH_HOWTO (R_LARCH_TLS_DESC_PC_LO12, /* type (112). */ ++ 0, /* rightshift. */ ++ 4, /* size. */ ++ 12, /* bitsize. */ ++ true, /* pc_relative. */ ++ 10, /* bitpos. */ ++ complain_overflow_signed, /* complain_on_overflow. */ ++ bfd_elf_generic_reloc, /* special_function. */ ++ "R_LARCH_TLS_DESC_PC_LO12", /* name. */ ++ false, /* partial_inplace. */ ++ 0, /* src_mask. */ ++ 0x3ffc00, /* dst_mask. */ ++ false, /* pcrel_offset. */ ++ BFD_RELOC_LARCH_TLS_DESC_PC_LO12, /* bfd_reloc_code_real_type. */ ++ reloc_bits, /* adjust_reloc_bits. */ ++ "desc_pc_lo12"), /* larch_reloc_type_name. */ ++ ++ /* TLS_DESC64 LARGE PCREL. */ ++ LOONGARCH_HOWTO (R_LARCH_TLS_DESC64_PC_LO20, /* type (113). */ ++ 32, /* rightshift. */ ++ 8, /* size. */ ++ 20, /* bitsize. */ ++ true, /* pc_relative. */ ++ 5, /* bitpos. */ ++ complain_overflow_signed, /* complain_on_overflow. */ ++ bfd_elf_generic_reloc, /* special_function. */ ++ "R_LARCH_TLS_DESC64_PC_LO20", /* name. */ ++ false, /* partial_inplace. */ ++ 0, /* src_mask. */ ++ 0x1ffffe0, /* dst_mask. */ ++ false, /* pcrel_offset. */ ++ BFD_RELOC_LARCH_TLS_DESC64_PC_LO20, /* bfd_reloc_code_real_type. */ ++ reloc_bits, /* adjust_reloc_bits. */ ++ "desc64_pc_lo20"), /* larch_reloc_type_name. */ ++ ++ LOONGARCH_HOWTO (R_LARCH_TLS_DESC64_PC_HI12, /* type (114). */ ++ 52, /* rightshift. */ ++ 8, /* size. */ ++ 12, /* bitsize. */ ++ true, /* pc_relative. */ ++ 10, /* bitpos. */ ++ complain_overflow_signed, /* complain_on_overflow. */ ++ bfd_elf_generic_reloc, /* special_function. */ ++ "R_LARCH_TLS_DESC64_PC_HI12", /* name. */ ++ false, /* partial_inplace. */ ++ 0, /* src_mask. */ ++ 0x3ffc00, /* dst_mask. */ ++ false, /* pcrel_offset. */ ++ BFD_RELOC_LARCH_TLS_DESC64_PC_HI12, /* bfd_reloc_code_real_type. */ ++ reloc_bits, /* adjust_reloc_bits. */ ++ "desc64_pc_hi12"), /* larch_reloc_type_name. */ ++ ++ /* TLS_DESC ABS. */ ++ LOONGARCH_HOWTO (R_LARCH_TLS_DESC_HI20, /* type (115). */ ++ 12, /* rightshift. */ ++ 4, /* size. */ ++ 20, /* bitsize. */ ++ false, /* pc_relative. */ ++ 5, /* bitpos. */ ++ complain_overflow_signed, /* complain_on_overflow. */ ++ bfd_elf_generic_reloc, /* special_function. */ ++ "R_LARCH_TLS_DESC_HI20", /* name. */ ++ false, /* partial_inplace. */ ++ 0, /* src_mask. */ ++ 0x1ffffe0, /* dst_mask. */ ++ false, /* pcrel_offset. */ ++ BFD_RELOC_LARCH_TLS_DESC_HI20, /* bfd_reloc_code_real_type. */ ++ reloc_bits, /* adjust_reloc_bits. */ ++ "desc_hi20"), /* larch_reloc_type_name. */ ++ ++ LOONGARCH_HOWTO (R_LARCH_TLS_DESC_LO12, /* type (116). */ ++ 0, /* rightshift. */ ++ 4, /* size. */ ++ 12, /* bitsize. */ ++ false, /* pc_relative. */ ++ 10, /* bitpos. */ ++ complain_overflow_signed, /* complain_on_overflow. */ ++ bfd_elf_generic_reloc, /* special_function. */
View file
_service:tar_scm:LoongArch-Add-relaxation-for-R_LARCH_CALL36.patch
Added
@@ -0,0 +1,684 @@ +From 1ac9f2fb1378c35c8d75b54b82a34a5e560b6ad3 Mon Sep 17 00:00:00 2001 +From: mengqinggang <mengqinggang@loongson.cn> +Date: Wed, 28 Feb 2024 17:42:36 +0800 +Subject: PATCH 074/123 LoongArch: Add relaxation for R_LARCH_CALL36 + +This relaxation is effective for both macro instructions (call36, tail36) +and explicit relocation instructions (pcaddu18i + jirl). + +call36 f -> bl f + R_LARCH_CALL36 -> R_LARCH_B26 + +tail36 $t0, f -> b f + R_LARCH_CALL36 -> R_LARCH_B26 +--- + bfd/elfnn-loongarch.c | 59 ++++ + gas/config/tc-loongarch.c | 19 +- + gas/testsuite/gas/loongarch/medium-call.d | 7 +- + .../relax-cfi-fde-DW_CFA_advance_loc.d | 10 +- + .../relax-cfi-fde-DW_CFA_advance_loc.s | 4 + + gas/testsuite/gas/loongarch/relocs_64.d | 282 +++++++++--------- + .../ld-loongarch-elf/ld-loongarch-elf.exp | 2 + + .../ld-loongarch-elf/relax-medium-call-1.d | 21 ++ + .../ld-loongarch-elf/relax-medium-call-1.s | 43 +++ + .../ld-loongarch-elf/relax-medium-call.d | 21 ++ + .../ld-loongarch-elf/relax-medium-call.s | 35 +++ + 11 files changed, 356 insertions(+), 147 deletions(-) + create mode 100644 ld/testsuite/ld-loongarch-elf/relax-medium-call-1.d + create mode 100644 ld/testsuite/ld-loongarch-elf/relax-medium-call-1.s + create mode 100644 ld/testsuite/ld-loongarch-elf/relax-medium-call.d + create mode 100644 ld/testsuite/ld-loongarch-elf/relax-medium-call.s + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index 489ccbe0..1c3295f4 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -4334,6 +4334,60 @@ loongarch_relax_pcala_addi (bfd *abfd, asection *sec, asection *sym_sec, + return true; + } + ++/* call36 f -> bl f ++ tail36 $t0, f -> b f. */ ++static bool ++loongarch_relax_call36 (bfd *abfd, asection *sec, ++ Elf_Internal_Rela *rel, bfd_vma symval, ++ struct bfd_link_info *info, bool *again, ++ bfd_vma max_alignment) ++{ ++ bfd_byte *contents = elf_section_data (sec)->this_hdr.contents; ++ uint32_t jirl = bfd_get (32, abfd, contents + rel->r_offset + 4); ++ uint32_t rd = jirl & 0x1f; ++ ++ /* This section's output_offset need to subtract the bytes of instructions ++ relaxed by the previous sections, so it needs to be updated beforehand. ++ size_input_section already took care of updating it after relaxation, ++ so we additionally update once here. */ ++ sec->output_offset = sec->output_section->size; ++ bfd_vma pc = sec_addr (sec) + rel->r_offset; ++ ++ /* If pc and symbol not in the same segment, add/sub segment alignment. ++ FIXME: if there are multiple readonly segments? How to determine if ++ two sections are in the same segment. */ ++ if (symval > pc) ++ pc -= (max_alignment > 4 ? max_alignment : 0); ++ else if (symval < pc) ++ pc += (max_alignment > 4 ? max_alignment : 0); ++ ++ const uint32_t jirl_opcode = 0x4c000000; ++ ++ /* Is pcalau12i + addi.d insns? */ ++ if ((ELFNN_R_TYPE ((rel + 1)->r_info) != R_LARCH_RELAX) ++ || ((jirl & jirl_opcode) != jirl_opcode) ++ || ((bfd_signed_vma)(symval - pc) < (bfd_signed_vma)(int32_t)0xf8000000) ++ || ((bfd_signed_vma)(symval - pc) > (bfd_signed_vma)(int32_t)0x7fffffc)) ++ return false; ++ ++ /* Continue next relax trip. */ ++ *again = true; ++ ++ const uint32_t bl = 0x54000000; ++ const uint32_t b = 0x50000000; ++ ++ if (rd) ++ bfd_put (32, abfd, bl, contents + rel->r_offset); ++ else ++ bfd_put (32, abfd, b, contents + rel->r_offset); ++ ++ /* Adjust relocations. */ ++ rel->r_info = ELFNN_R_INFO (ELFNN_R_SYM (rel->r_info), R_LARCH_B26); ++ /* Delete jirl instruction. */ ++ loongarch_relax_delete_bytes (abfd, sec, rel->r_offset + 4, 4, info); ++ return true; ++} ++ + /* Relax pcalau12i,ld.d => pcalau12i,addi.d. */ + static bool + loongarch_relax_pcala_ld (bfd *abfd, asection *sec, +@@ -4752,6 +4806,11 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, + rel->r_info = ELFNN_R_INFO (0, R_LARCH_NONE); + } + break; ++ case R_LARCH_CALL36: ++ if (0 == info->relax_pass && (i + 2) <= sec->reloc_count) ++ loongarch_relax_call36 (abfd, sec, rel, symval, info, again, ++ max_alignment); ++ break; + + case R_LARCH_TLS_LE_HI20_R: + case R_LARCH_TLS_LE_LO12_R: +diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c +index ff126d56..51575757 100644 +--- a/gas/config/tc-loongarch.c ++++ b/gas/config/tc-loongarch.c +@@ -116,6 +116,8 @@ const char *md_shortopts = "O::g::G:"; + + static const char default_arch = DEFAULT_ARCH; + ++static bool call36 = 0; ++ + /* The lowest 4-bit is the bytes of instructions. */ + #define RELAX_BRANCH_16 0xc0000014 + #define RELAX_BRANCH_21 0xc0000024 +@@ -720,7 +722,8 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2, + || BFD_RELOC_LARCH_TLS_LE_HI20 == reloc_type + || BFD_RELOC_LARCH_TLS_LE_LO12 == reloc_type + || BFD_RELOC_LARCH_TLS_LE64_LO20 == reloc_type +- || BFD_RELOC_LARCH_TLS_LE64_HI12 == reloc_type)) ++ || BFD_RELOC_LARCH_TLS_LE64_HI12 == reloc_type ++ || BFD_RELOC_LARCH_CALL36 == reloc_type)) + { + ip->reloc_infoip->reloc_num.type = BFD_RELOC_LARCH_RELAX; + ip->reloc_infoip->reloc_num.value = const_0; +@@ -1016,6 +1019,20 @@ append_fixed_insn (struct loongarch_cl_insn *insn) + + char *f = frag_more (insn->insn_length); + move_insn (insn, frag_now, f - frag_now->fr_literal); ++ ++ if (call36) ++ { ++ if (strcmp (insn->name, "jirl") == 0) ++ { ++ /* See comment at end of append_fixp_and_insn. */ ++ frag_wane (frag_now); ++ frag_new (0); ++ } ++ call36 = 0; ++ } ++ ++ if (BFD_RELOC_LARCH_CALL36 == insn->reloc_info0.type) ++ call36 = 1; + } + + /* Add instructions based on the worst-case scenario firstly. */ +diff --git a/gas/testsuite/gas/loongarch/medium-call.d b/gas/testsuite/gas/loongarch/medium-call.d +index 3491760b..79d74ba3 100644 +--- a/gas/testsuite/gas/loongarch/medium-call.d ++++ b/gas/testsuite/gas/loongarch/medium-call.d +@@ -1,21 +1,26 @@ + #as: + #objdump: -dr ++#skip: loongarch32-*-* + + .*: +file format .* + + + Disassembly of section .text: + +-.* <.text>: ++ *0000000000000000 <.text>: + +0: +1e000001 +pcaddu18i +\$ra, 0 + +0: R_LARCH_CALL36 +a ++ +0: R_LARCH_RELAX +\*ABS\* + +4: +4c000021 +jirl +\$ra, \$ra, 0 + +8: +1e000001 +pcaddu18i +\$ra, 0 + +8: R_LARCH_CALL36 +a ++ +8: R_LARCH_RELAX +\*ABS\* + +c: +4c000021 +jirl +\$ra, \$ra, 0 + +10: +1e00000c +pcaddu18i +\$t0, 0 + +10: R_LARCH_CALL36 +a ++ +10: R_LARCH_RELAX +\*ABS\* + +14: +4c000180 +jr +\$t0 + +18: +1e00000c +pcaddu18i +\$t0, 0 + +18: R_LARCH_CALL36 +a ++ +18: R_LARCH_RELAX +\*ABS\* + +1c: +4c000180 +jr +\$t0 +diff --git a/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.d b/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.d +index 6b164cfb..d685bd86 100644 +--- a/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.d ++++ b/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.d +@@ -26,7 +26,7 @@ Disassembly of section .eh_frame: + +2c: +d6400016 +.word + +0xd6400016 + +2e: R_LARCH_ADD6 +L0\^A + +2e: R_LARCH_SUB6 +L0\^A +- +30: +4000160c +beqz +\$t4, 3145748 +# 300044 <L0\^A\+0x2ffffc> ++ +30: +4000160c +beqz +\$t4, 3145748 +# 300044 <L0\^A\+0x2ffff4> + +33: R_LARCH_ADD6 +L0\^A + +33: R_LARCH_SUB6 +L0\^A + +34: +00160cd6 +orn +\$fp, \$a2, \$sp +@@ -39,14 +39,16 @@ Disassembly of section .eh_frame: + +40: +d6400016 +.word + +0xd6400016
View file
_service:tar_scm:LoongArch-Add-support-for-OUTPUT_FORMAT-binary.patch
Added
@@ -0,0 +1,124 @@ +From 2d1db1c7427598dbabc93b7d47b01a1aa5e2cec0 Mon Sep 17 00:00:00 2001 +From: mengqinggang <mengqinggang@loongson.cn> +Date: Fri, 28 Jun 2024 14:24:19 +0800 +Subject: PATCH 105/123 LoongArch: Add support for OUTPUT_FORMAT("binary") + +In binary output format, loongarch_elf_hash_table return NULL and result +in segment fault. + +When ld output binary file, it seems that elf related functions should +not be called. But loongarch_elf_relax_section be called and +loongarch_elf_hash_table cause segment fault. + +Just redefined loongarch_elf_hash_table and always return +link_info->hash. + +The tests of binutils, glibc and gcc is ok. + +0 loongarch_elf_relax_section () +1 0x000055555557ab28 in lang_size_sections_1 () +2 0x000055555557a16c in lang_size_sections_1 () +3 0x000055555557b0a8 in one_lang_size_sections_pass () +4 0x000055555557b478 in lang_size_sections () +5 0x000055555557e65c in lang_relax_sections () +6 0x000055555559f9c8 in ldelf_map_segments () +7 0x000055555559783c in gldelf64loongarch_after_allocation () +8 0x000055555558dac0 in ldemul_after_allocation () +9 0x000055555557f6c0 in lang_process () +10 0x0000555555585314 in main () +--- + bfd/elfnn-loongarch.c | 4 +--- + ld/emultempl/loongarchelf.em | 16 ---------------- + ld/testsuite/ld-loongarch-elf/binary.ld | 1 + + ld/testsuite/ld-loongarch-elf/binary.s | 4 ++++ + .../ld-loongarch-elf/ld-loongarch-elf.exp | 12 ++++++++++++ + 5 files changed, 18 insertions(+), 19 deletions(-) + create mode 100644 ld/testsuite/ld-loongarch-elf/binary.ld + create mode 100644 ld/testsuite/ld-loongarch-elf/binary.s + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index af4d8baa..c2468443 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -157,9 +157,7 @@ loongarch_elf_new_section_hook (bfd *abfd, asection *sec) + + /* Get the LoongArch ELF linker hash table from a link_info structure. */ + #define loongarch_elf_hash_table(p) \ +- (elf_hash_table_id (elf_hash_table (p)) == LARCH_ELF_DATA \ +- ? ((struct loongarch_elf_link_hash_table *) ((p)->hash)) \ +- : NULL) ++ ((struct loongarch_elf_link_hash_table *) ((p)->hash)) \ + + #define MINUS_ONE ((bfd_vma) 0 - 1) + +diff --git a/ld/emultempl/loongarchelf.em b/ld/emultempl/loongarchelf.em +index 13f8dacb..2e6b8080 100644 +--- a/ld/emultempl/loongarchelf.em ++++ b/ld/emultempl/loongarchelf.em +@@ -102,23 +102,7 @@ gld${EMULATION_NAME}_after_allocation (void) + ldelf_map_segments (need_layout); + } + +-/* This is a convenient point to tell BFD about target specific flags. +- After the output has been created, but before inputs are read. */ +- +-static void +-larch_create_output_section_statements (void) +-{ +- /* See PR 22920 for an example of why this is necessary. */ +- if (strstr (bfd_get_target (link_info.output_bfd), "loong") == NULL) +- { +- einfo (_("%F%P: error: cannot change output format" +- " whilst linking %s binaries\n"), "LoongArch"); +- return; +- } +-} +- + EOF + + LDEMUL_BEFORE_ALLOCATION=larch_elf_before_allocation + LDEMUL_AFTER_ALLOCATION=gld${EMULATION_NAME}_after_allocation +-LDEMUL_CREATE_OUTPUT_SECTION_STATEMENTS=larch_create_output_section_statements +diff --git a/ld/testsuite/ld-loongarch-elf/binary.ld b/ld/testsuite/ld-loongarch-elf/binary.ld +new file mode 100644 +index 00000000..73cd4f2c +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/binary.ld +@@ -0,0 +1 @@ ++OUTPUT_FORMAT(binary); +diff --git a/ld/testsuite/ld-loongarch-elf/binary.s b/ld/testsuite/ld-loongarch-elf/binary.s +new file mode 100644 +index 00000000..b0aeb62a +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/binary.s +@@ -0,0 +1,4 @@ ++.text ++ ret ++.data ++ .4byte 0x12345678 +diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp +index 032b9bad..232e7c20 100644 +--- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp ++++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp +@@ -118,6 +118,18 @@ if istarget "loongarch64-*-*" { + "abi1_max_imm" \ + \ + ++ ++ run_ld_link_tests \ ++ list \ ++ list \ ++ "binary output format" \ ++ "-T binary.ld" "" \ ++ "" \ ++ {binary.s} \ ++ {} \ ++ "a.binary" \ ++ \ ++ + } + + if istarget "loongarch64-*-*" { +-- +2.33.0 +
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_service:tar_scm:LoongArch-Add-support-for-TLS-LD-GD-DESC-relaxation.patch
Added
@@ -0,0 +1,1611 @@ +From b71b59b2ff4e169cbed791a1738ba7ac40e1ed49 Mon Sep 17 00:00:00 2001 +From: mengqinggang <mengqinggang@loongson.cn> +Date: Mon, 11 Dec 2023 16:08:20 +0800 +Subject: PATCH 028/123 LoongArch: Add support for TLS LD/GD/DESC relaxation + +The pcalau12i + addi.d of TLS LD/GD/DESC relax to pcaddi. +Relaxation is only performed when the TLS model transition is not possible. +--- + bfd/bfd-in2.h | 3 + + bfd/elfnn-loongarch.c | 174 +++++++- + bfd/elfxx-loongarch.c | 60 +++ + bfd/libbfd.h | 3 + + bfd/reloc.c | 7 + + gas/config/tc-loongarch.c | 8 +- + gas/testsuite/gas/loongarch/macro_op.d | 128 +++--- + gas/testsuite/gas/loongarch/macro_op_32.d | 120 +++--- + .../gas/loongarch/macro_op_large_abs.d | 160 +++---- + .../gas/loongarch/macro_op_large_pc.d | 160 +++---- + include/elf/loongarch.h | 4 + + ld/testsuite/ld-loongarch-elf/macro_op.d | 391 +++++++++--------- + ld/testsuite/ld-loongarch-elf/macro_op_32.d | 120 +++--- + 13 files changed, 795 insertions(+), 543 deletions(-) + +diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h +index d210e71b..d7b762d4 100644 +--- a/bfd/bfd-in2.h ++++ b/bfd/bfd-in2.h +@@ -7356,6 +7356,9 @@ assembler and not (currently) written to any object files. */ + BFD_RELOC_LARCH_TLS_DESC64_HI12, + BFD_RELOC_LARCH_TLS_DESC_LD, + BFD_RELOC_LARCH_TLS_DESC_CALL, ++ BFD_RELOC_LARCH_TLS_LD_PCREL20_S2, ++ BFD_RELOC_LARCH_TLS_GD_PCREL20_S2, ++ BFD_RELOC_LARCH_TLS_DESC_PCREL20_S2, + BFD_RELOC_UNUSED + }; + typedef enum bfd_reloc_code_real bfd_reloc_code_real_type; +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index 13fddd63..d46bcd77 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -2285,7 +2285,9 @@ perform_relocation (const Elf_Internal_Rela *rel, asection *input_section, + case R_LARCH_TLS_DESC_LO12: + case R_LARCH_TLS_DESC64_LO20: + case R_LARCH_TLS_DESC64_HI12: +- ++ case R_LARCH_TLS_LD_PCREL20_S2: ++ case R_LARCH_TLS_GD_PCREL20_S2: ++ case R_LARCH_TLS_DESC_PCREL20_S2: + r = loongarch_check_offset (rel, input_section); + if (r != bfd_reloc_ok) + break; +@@ -3667,6 +3669,9 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, + case R_LARCH_TLS_GD_HI20: + case R_LARCH_TLS_DESC_PC_HI20: + case R_LARCH_TLS_DESC_HI20: ++ case R_LARCH_TLS_LD_PCREL20_S2: ++ case R_LARCH_TLS_GD_PCREL20_S2: ++ case R_LARCH_TLS_DESC_PCREL20_S2: + BFD_ASSERT (rel->r_addend == 0); + unresolved_reloc = false; + +@@ -3675,7 +3680,8 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, + is_ie = true; + + if (r_type == R_LARCH_TLS_DESC_PC_HI20 +- || r_type == R_LARCH_TLS_DESC_HI20) ++ || r_type == R_LARCH_TLS_DESC_HI20 ++ || r_type == R_LARCH_TLS_DESC_PCREL20_S2) + is_desc = true; + + bfd_vma got_off = 0; +@@ -3806,7 +3812,11 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, + || r_type == R_LARCH_TLS_IE_PC_HI20 + || r_type == R_LARCH_TLS_DESC_PC_HI20) + RELOCATE_CALC_PC32_HI20 (relocation, pc); +- ++ else if (r_type == R_LARCH_TLS_LD_PCREL20_S2 ++ || r_type == R_LARCH_TLS_GD_PCREL20_S2 ++ || r_type == R_LARCH_TLS_DESC_PCREL20_S2) ++ relocation -= pc; ++ /* else {} ABS relocations. */ + break; + + case R_LARCH_TLS_DESC_PC_LO12: +@@ -4237,6 +4247,85 @@ loongarch_relax_align (bfd *abfd, asection *sec, + addend - need_nop_bytes, link_info); + } + ++/* Relax pcalau12i + addi.d of TLS LD/GD/DESC to pcaddi. */ ++static bool ++loongarch_relax_tls_ld_gd_desc (bfd *abfd, asection *sec, asection *sym_sec, ++ Elf_Internal_Rela *rel_hi, bfd_vma symval, ++ struct bfd_link_info *info, bool *again) ++{ ++ bfd_byte *contents = elf_section_data (sec)->this_hdr.contents; ++ Elf_Internal_Rela *rel_lo = rel_hi + 2; ++ uint32_t pca = bfd_get (32, abfd, contents + rel_hi->r_offset); ++ uint32_t add = bfd_get (32, abfd, contents + rel_lo->r_offset); ++ uint32_t rd = pca & 0x1f; ++ ++ /* This section's output_offset need to subtract the bytes of instructions ++ relaxed by the previous sections, so it needs to be updated beforehand. ++ size_input_section already took care of updating it after relaxation, ++ so we additionally update once here. */ ++ sec->output_offset = sec->output_section->size; ++ bfd_vma pc = sec_addr (sec) + rel_hi->r_offset; ++ ++ /* If pc and symbol not in the same segment, add/sub segment alignment. ++ FIXME: if there are multiple readonly segments? */ ++ if (!(sym_sec->flags & SEC_READONLY)) ++ { ++ if (symval > pc) ++ pc -= info->maxpagesize; ++ else if (symval < pc) ++ pc += info->maxpagesize; ++ } ++ ++ const uint32_t addi_d = 0x02c00000; ++ const uint32_t pcaddi = 0x18000000; ++ ++ /* Is pcalau12i + addi.d insns? */ ++ if ((ELFNN_R_TYPE (rel_lo->r_info) != R_LARCH_GOT_PC_LO12 ++ && ELFNN_R_TYPE (rel_lo->r_info) != R_LARCH_TLS_DESC_PC_LO12) ++ || (ELFNN_R_TYPE ((rel_lo + 1)->r_info) != R_LARCH_RELAX) ++ || (ELFNN_R_TYPE ((rel_hi + 1)->r_info) != R_LARCH_RELAX) ++ || (rel_hi->r_offset + 4 != rel_lo->r_offset) ++ || ((add & addi_d) != addi_d) ++ /* Is pcalau12i $rd + addi.d $rd,$rd? */ ++ || ((add & 0x1f) != rd) ++ || (((add >> 5) & 0x1f) != rd) ++ /* Can be relaxed to pcaddi? */ ++ || (symval & 0x3) /* 4 bytes align. */ ++ || ((bfd_signed_vma)(symval - pc) < (bfd_signed_vma)(int32_t)0xffe00000) ++ || ((bfd_signed_vma)(symval - pc) > (bfd_signed_vma)(int32_t)0x1ffffc)) ++ return false; ++ ++ /* Continue next relax trip. */ ++ *again = true; ++ ++ pca = pcaddi | rd; ++ bfd_put (32, abfd, pca, contents + rel_hi->r_offset); ++ ++ /* Adjust relocations. */ ++ switch (ELFNN_R_TYPE (rel_hi->r_info)) ++ { ++ case R_LARCH_TLS_LD_PC_HI20: ++ rel_hi->r_info = ELFNN_R_INFO (ELFNN_R_SYM (rel_hi->r_info), ++ R_LARCH_TLS_LD_PCREL20_S2); ++ break; ++ case R_LARCH_TLS_GD_PC_HI20: ++ rel_hi->r_info = ELFNN_R_INFO (ELFNN_R_SYM (rel_hi->r_info), ++ R_LARCH_TLS_GD_PCREL20_S2); ++ break; ++ case R_LARCH_TLS_DESC_PC_HI20: ++ rel_hi->r_info = ELFNN_R_INFO (ELFNN_R_SYM (rel_hi->r_info), ++ R_LARCH_TLS_DESC_PCREL20_S2); ++ break; ++ default: ++ break; ++ } ++ rel_lo->r_info = ELFNN_R_INFO (0, R_LARCH_NONE); ++ ++ loongarch_relax_delete_bytes (abfd, sec, rel_lo->r_offset, 4, info); ++ ++ return true; ++} ++ + static bool + loongarch_elf_relax_section (bfd *abfd, asection *sec, + struct bfd_link_info *info, +@@ -4281,15 +4370,23 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, + + for (unsigned int i = 0; i < sec->reloc_count; i++) + { +- Elf_Internal_Rela *rel = relocs + i; +- asection *sym_sec; ++ char symtype; + bfd_vma symval; +- unsigned long r_symndx = ELFNN_R_SYM (rel->r_info); +- unsigned long r_type = ELFNN_R_TYPE (rel->r_info); ++ asection *sym_sec; + bool local_got = false; +- char symtype; ++ Elf_Internal_Rela *rel = relocs + i; + struct elf_link_hash_entry *h = NULL; ++ unsigned long r_type = ELFNN_R_TYPE (rel->r_info); ++ unsigned long r_symndx = ELFNN_R_SYM (rel->r_info); + ++ /* Four kind of relocations: ++ Normal: symval is the symbol address. ++ R_LARCH_ALIGN: symval is the address of the last NOP instruction ++ added by this relocation, and then adds 4 more. ++ R_LARCH_CALL36: symval is the symbol address for local symbols, ++ or the PLT entry address of the symbol. (Todo) ++ R_LARCHL_TLS_LD/GD/DESC_PC_HI20: symval is the GOT entry address ++ of the symbol. */ + if (r_symndx < symtab_hdr->sh_info) + {
View file
_service:tar_scm:LoongArch-Add-support-for-TLSDESC-in-ld.patch
Added
@@ -0,0 +1,331 @@ +From b6d513ce677d288d470740a2a150a68a961e07cd Mon Sep 17 00:00:00 2001 +From: Lulu Cai <cailulu@loongson.cn> +Date: Tue, 31 Oct 2023 16:11:56 +0800 +Subject: PATCH 026/123 LoongArch: Add support for TLSDESC in ld. + +1.The linker for each DESC generates a R_LARCH_TLS_DESC64 dynamic + relocation, which relocation is placed at .rela.dyn. + TLSDESC always allocates two GOT slots and one dynamic relocation + space to TLSDESC. +2. When using multiple ways to access the same TLS variable, a + maximum of 5 GOT slots are used. For example, using GD, TLSDESC, + and IE to access the same TLS variable, GD always uses the first + two of the five GOT, TLSDESC uses the third and fourth, and IE + uses the last. +--- + bfd/elfnn-loongarch.c | 168 ++++++++++++++++++++++++++++++++++++------ + 1 file changed, 146 insertions(+), 22 deletions(-) + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index 8e61d8d2..31dde892 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -48,6 +48,12 @@ struct loongarch_elf_link_hash_entry + #define GOT_TLS_GD 2 + #define GOT_TLS_IE 4 + #define GOT_TLS_LE 8 ++#define GOT_TLS_GDESC 16 ++ ++#define GOT_TLS_GD_BOTH_P(tls_type) \ ++ ((tls_type & GOT_TLS_GD) && (tls_type & GOT_TLS_GDESC)) ++#define GOT_TLS_GD_ANY_P(tls_type) \ ++ ((tls_type & GOT_TLS_GD) || (tls_type & GOT_TLS_GDESC)) + char tls_type; + }; + +@@ -563,6 +569,7 @@ loongarch_elf_record_tls_and_got_reference (bfd *abfd, + case GOT_NORMAL: + case GOT_TLS_GD: + case GOT_TLS_IE: ++ case GOT_TLS_GDESC: + /* Need GOT. */ + if (htab->elf.sgot == NULL + && !loongarch_elf_create_got_section (htab->elf.dynobj, info)) +@@ -750,6 +757,14 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, + return false; + break; + ++ case R_LARCH_TLS_DESC_PC_HI20: ++ case R_LARCH_TLS_DESC_HI20: ++ if (!loongarch_elf_record_tls_and_got_reference (abfd, info, h, ++ r_symndx, ++ GOT_TLS_GDESC)) ++ return false; ++ break; ++ + case R_LARCH_ABS_HI20: + case R_LARCH_SOP_PUSH_ABSOLUTE: + if (h != NULL) +@@ -1130,7 +1145,7 @@ allocate_dynrelocs (struct elf_link_hash_entry *h, void *inf) + + s = htab->elf.sgot; + h->got.offset = s->size; +- if (tls_type & (GOT_TLS_GD | GOT_TLS_IE)) ++ if (tls_type & (GOT_TLS_GD | GOT_TLS_IE | GOT_TLS_GDESC)) + { + /* TLS_GD needs two dynamic relocs and two GOT slots. */ + if (tls_type & GOT_TLS_GD) +@@ -1167,7 +1182,15 @@ allocate_dynrelocs (struct elf_link_hash_entry *h, void *inf) + htab->elf.srelgot->size += sizeof (ElfNN_External_Rela); + } + } ++ ++ /* TLS_DESC needs one dynamic reloc and two GOT slot. */ ++ if (tls_type & GOT_TLS_GDESC) ++ { ++ s->size += GOT_ENTRY_SIZE * 2; ++ htab->elf.srelgot->size += sizeof (ElfNN_External_Rela); ++ } + } ++ + else + { + s->size += GOT_ENTRY_SIZE; +@@ -1670,19 +1693,34 @@ loongarch_elf_size_dynamic_sections (bfd *output_bfd, + if (0 < *local_got) + { + *local_got = s->size; ++ if (*local_tls_type & (GOT_TLS_GD | GOT_TLS_IE | GOT_TLS_GDESC)) ++ { ++ /* TLS gd use two got. */ ++ if (*local_tls_type & GOT_TLS_GD) ++ { ++ s->size += 2 * GOT_ENTRY_SIZE; ++ if (!bfd_link_executable (info)) ++ srel->size += sizeof (ElfNN_External_Rela); ++ } + +- /* TLS gd use two got. */ +- if (*local_tls_type & GOT_TLS_GD) +- s->size += GOT_ENTRY_SIZE * 2; +- else +- /* Normal got, tls ie/ld use one got. */ +- s->size += GOT_ENTRY_SIZE; ++ /* TLS_DESC use two got. */ ++ if (*local_tls_type & GOT_TLS_GDESC) ++ { ++ s->size += 2 * GOT_ENTRY_SIZE; ++ srel->size += sizeof (ElfNN_External_Rela); ++ } + +- if (bfd_link_executable (info) +- && (*local_tls_type & (GOT_TLS_GD| GOT_TLS_IE))) +- ;/* Do nothing. */ ++ /* TLS ie and use one got. */ ++ if (*local_tls_type & GOT_TLS_IE) ++ { ++ s->size += GOT_ENTRY_SIZE; ++ if (!bfd_link_executable (info)) ++ srel->size += sizeof (ElfNN_External_Rela); ++ } ++ } + else + { ++ s->size += GOT_ENTRY_SIZE; + srel->size += sizeof (ElfNN_External_Rela); + } + } +@@ -2126,6 +2164,15 @@ perform_relocation (const Elf_Internal_Rela *rel, asection *input_section, + case R_LARCH_TLS_GD_HI20: + case R_LARCH_PCREL20_S2: + case R_LARCH_CALL36: ++ case R_LARCH_TLS_DESC_PC_HI20: ++ case R_LARCH_TLS_DESC_PC_LO12: ++ case R_LARCH_TLS_DESC64_PC_LO20: ++ case R_LARCH_TLS_DESC64_PC_HI12: ++ case R_LARCH_TLS_DESC_HI20: ++ case R_LARCH_TLS_DESC_LO12: ++ case R_LARCH_TLS_DESC64_LO20: ++ case R_LARCH_TLS_DESC64_HI12: ++ + r = loongarch_check_offset (rel, input_section); + if (r != bfd_reloc_ok) + break; +@@ -2135,6 +2182,11 @@ perform_relocation (const Elf_Internal_Rela *rel, asection *input_section, + contents, value); + break; + ++ case R_LARCH_TLS_DESC_LD: ++ case R_LARCH_TLS_DESC_CALL: ++ r = bfd_reloc_ok; ++ break; ++ + case R_LARCH_RELAX: + break; + +@@ -2383,10 +2435,10 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, + struct elf_link_hash_entry *h = NULL; + const char *name; + bfd_reloc_status_type r = bfd_reloc_ok; +- bool is_ie, is_undefweak, unresolved_reloc, defined_local; ++ bool is_ie, is_desc, is_undefweak, unresolved_reloc, defined_local; + bool resolved_local, resolved_dynly, resolved_to_const; + char tls_type; +- bfd_vma relocation, off, ie_off; ++ bfd_vma relocation, off, ie_off, desc_off; + int i, j; + + howto = loongarch_elf_rtype_to_howto (input_bfd, r_type); +@@ -2515,6 +2567,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, + + BFD_ASSERT (!resolved_local || defined_local); + ++ is_desc = false; + is_ie = false; + switch (r_type) + { +@@ -3398,6 +3451,8 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, + case R_LARCH_TLS_LD_HI20: + case R_LARCH_TLS_GD_PC_HI20: + case R_LARCH_TLS_GD_HI20: ++ case R_LARCH_TLS_DESC_PC_HI20: ++ case R_LARCH_TLS_DESC_HI20: + BFD_ASSERT (rel->r_addend == 0); + unresolved_reloc = false; + +@@ -3405,6 +3460,10 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, + || r_type == R_LARCH_TLS_IE_HI20) + is_ie = true; + ++ if (r_type == R_LARCH_TLS_DESC_PC_HI20 ++ || r_type == R_LARCH_TLS_DESC_HI20) ++ is_desc = true; ++ + bfd_vma got_off = 0; + if (h != NULL) + { +@@ -3419,9 +3478,19 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, + + BFD_ASSERT (got_off != MINUS_ONE);
View file
_service:tar_scm:LoongArch-Add-support-for-b-.L1-and-beq-t0-t1-.L1.patch
Added
@@ -0,0 +1,63 @@ +From 114ab354c7fd16678578031340437b60e7b36e53 Mon Sep 17 00:00:00 2001 +From: mengqinggang <mengqinggang@loongson.cn> +Date: Sun, 10 Dec 2023 17:41:32 +0800 +Subject: PATCH 019/123 LoongArch: Add support for <b ".L1"> and <beq, $t0, + $t1, ".L1"> + +Support symbol names enclosed in double quotation marks. +--- + .../gas/loongarch/double_quotation_marks.d | 13 +++++++++++++ + .../gas/loongarch/double_quotation_marks.s | 2 ++ + opcodes/loongarch-coder.c | 7 +++++++ + 3 files changed, 22 insertions(+) + create mode 100644 gas/testsuite/gas/loongarch/double_quotation_marks.d + create mode 100644 gas/testsuite/gas/loongarch/double_quotation_marks.s + +diff --git a/gas/testsuite/gas/loongarch/double_quotation_marks.d b/gas/testsuite/gas/loongarch/double_quotation_marks.d +new file mode 100644 +index 00000000..a42534b9 +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/double_quotation_marks.d +@@ -0,0 +1,13 @@ ++#as: ++#objdump: -dr ++ ++.*: +file format .* ++ ++ ++Disassembly of section .text: ++ ++.* <.text>: ++ +0: +50000000 +b +0 +# 0x0 ++ +0: R_LARCH_B26 +.L1 ++ +4: +5800018d +beq +\$t0, \$t1, 0 +# 0x4 ++ +4: R_LARCH_B16 +.L1 +diff --git a/gas/testsuite/gas/loongarch/double_quotation_marks.s b/gas/testsuite/gas/loongarch/double_quotation_marks.s +new file mode 100644 +index 00000000..f8b63074 +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/double_quotation_marks.s +@@ -0,0 +1,2 @@ ++b ".L1" ++beq $r12, $r13, ".L1" +diff --git a/opcodes/loongarch-coder.c b/opcodes/loongarch-coder.c +index a68ae1c3..672a468b 100644 +--- a/opcodes/loongarch-coder.c ++++ b/opcodes/loongarch-coder.c +@@ -264,6 +264,13 @@ loongarch_split_args_by_comma (char *args, const char *arg_strs) + else + *args = '\0', arg_strsnum++ = args + 1; + } ++ ++ if (*(args-1) == '"') ++ { ++ *(args-1) = '\0'; ++ arg_strsnum-1 = arg_strsnum-1 + 1; ++ } ++ + arg_strsnum = NULL; + return num; + } +-- +2.33.0 +
View file
_service:tar_scm:LoongArch-Add-support-for-the-third-expression-of-.a.patch
Added
@@ -0,0 +1,445 @@ +From 3df3fec5862a2d6adec7dc469e7c53596e0ca464 Mon Sep 17 00:00:00 2001 +From: mengqinggang <mengqinggang@loongson.cn> +Date: Fri, 8 Dec 2023 15:15:50 +0800 +Subject: PATCH 023/123 LoongArch: Add support for the third expression of + .align for R_LARCH_ALIGN + +If the symbol index is not zero, the addend is used to represent +the first and the third expressions of the .align. + +The lowest 8 bits are used to represent the first expression. +Other bits are used to represent the third expression. + +The addend of R_LARCH_ALIGN for ".align 5, ,4" is 0x405. +The addend of R_LARCH_ALIGN for ".balign 32, ,4" is 0x405. +--- + bfd/elfnn-loongarch.c | 71 ++++++++++++------- + bfd/elfxx-loongarch.c | 10 ++- + gas/config/tc-loongarch.c | 20 ++++-- + gas/config/tc-loongarch.h | 4 +- + gas/testsuite/gas/loongarch/relax_align.d | 46 +++++++----- + gas/testsuite/gas/loongarch/relax_align.s | 4 +- + ld/testsuite/ld-elf/anno-sym.d | 2 + + ld/testsuite/ld-loongarch-elf/anno-sym.d | 7 ++ + ld/testsuite/ld-loongarch-elf/anno-sym.l | 4 ++ + ld/testsuite/ld-loongarch-elf/anno-sym.s | 13 ++++ + .../ld-loongarch-elf/ld-loongarch-elf.exp | 1 + + ld/testsuite/ld-loongarch-elf/relax-align.dd | 5 +- + ld/testsuite/ld-loongarch-elf/relax-align.s | 5 +- + ld/testsuite/ld-loongarch-elf/relax.exp | 2 +- + 14 files changed, 134 insertions(+), 60 deletions(-) + create mode 100644 ld/testsuite/ld-loongarch-elf/anno-sym.d + create mode 100644 ld/testsuite/ld-loongarch-elf/anno-sym.l + create mode 100644 ld/testsuite/ld-loongarch-elf/anno-sym.s + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index 6fd6a04d..8e61d8d2 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -3851,44 +3851,53 @@ loongarch_relax_align (bfd *abfd, asection *sec, + Elf_Internal_Rela *rel, + bfd_vma symval) + { +- bfd_byte *contents = elf_section_data (sec)->this_hdr.contents; +- bfd_vma alignment = 1, pos; +- while (alignment <= rel->r_addend) +- alignment *= 2; ++ bfd_vma addend, max = 0, alignment = 1; + +- symval -= rel->r_addend; +- bfd_vma aligned_addr = ((symval - 1) & ~(alignment - 1)) + alignment; +- bfd_vma nop_bytes = aligned_addr - symval; ++ int index = ELFNN_R_SYM (rel->r_info); ++ if (index > 0) ++ { ++ alignment = 1 << (rel->r_addend & 0xff); ++ max = rel->r_addend >> 8; ++ } ++ else ++ alignment = rel->r_addend + 4; + +- /* Once we've handled an R_LARCH_ALIGN, we can't relax anything else. */ +- sec->sec_flg0 = true; ++ addend = alignment - 4; /* The bytes of NOPs added by R_LARCH_ALIGN. */ ++ symval -= addend; /* The address of first NOP added by R_LARCH_ALIGN. */ ++ bfd_vma aligned_addr = ((symval - 1) & ~(alignment - 1)) + alignment; ++ bfd_vma need_nop_bytes = aligned_addr - symval; /* */ + + /* Make sure there are enough NOPs to actually achieve the alignment. */ +- if (rel->r_addend < nop_bytes) ++ if (addend < need_nop_bytes) + { + _bfd_error_handler + (_("%pB(%pA+%#" PRIx64 "): %" PRId64 " bytes required for alignment " + "to %" PRId64 "-byte boundary, but only %" PRId64 " present"), + abfd, sym_sec, (uint64_t) rel->r_offset, +- (int64_t) nop_bytes, (int64_t) alignment, (int64_t) rel->r_addend); ++ (int64_t) need_nop_bytes, (int64_t) alignment, (int64_t) addend); + bfd_set_error (bfd_error_bad_value); + return false; + } + +- /* Delete the reloc. */ ++ /* Once we've handled an R_LARCH_ALIGN in a section, ++ we can't relax anything else in this section. */ ++ sec->sec_flg0 = true; + rel->r_info = ELFNN_R_INFO (0, R_LARCH_NONE); + ++ /* If skipping more bytes than the specified maximum, ++ then the alignment is not done at all and delete all NOPs. */ ++ if (max > 0 && need_nop_bytes > max) ++ return loongarch_relax_delete_bytes (abfd, sec, rel->r_offset, ++ addend, link_info); ++ + /* If the number of NOPs is already correct, there's nothing to do. */ +- if (nop_bytes == rel->r_addend) ++ if (need_nop_bytes == addend) + return true; + +- /* Write as many LOONGARCH NOPs as we need. */ +- for (pos = 0; pos < (nop_bytes & -4); pos += 4) +- bfd_putl32 (LARCH_NOP, contents + rel->r_offset + pos); +- + /* Delete the excess NOPs. */ +- return loongarch_relax_delete_bytes (abfd, sec, rel->r_offset + nop_bytes, +- rel->r_addend - nop_bytes, link_info); ++ return loongarch_relax_delete_bytes (abfd, sec, ++ rel->r_offset + need_nop_bytes, ++ addend - need_nop_bytes, link_info); + } + + static bool +@@ -3897,8 +3906,8 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, + bool *again) + { + struct loongarch_elf_link_hash_table *htab = loongarch_elf_hash_table (info); +- Elf_Internal_Shdr *symtab_hdr = &elf_symtab_hdr (abfd); + struct bfd_elf_section_data *data = elf_section_data (sec); ++ Elf_Internal_Shdr *symtab_hdr = &elf_symtab_hdr (abfd); + Elf_Internal_Rela *relocs; + *again = false; + +@@ -3931,7 +3940,7 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, + 0, NULL, NULL, NULL))) + return true; + +- data->relocs = relocs; ++ data->relocs = relocs; + + for (unsigned int i = 0; i < sec->reloc_count; i++) + { +@@ -3939,6 +3948,7 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, + asection *sym_sec; + bfd_vma symval; + unsigned long r_symndx = ELFNN_R_SYM (rel->r_info); ++ unsigned long r_type = ELFNN_R_TYPE (rel->r_info); + bool local_got = false; + char symtype; + struct elf_link_hash_entry *h = NULL; +@@ -3950,7 +3960,7 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, + if (ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC) + continue; + +- if (sym->st_shndx == SHN_UNDEF) ++ if (sym->st_shndx == SHN_UNDEF || R_LARCH_ALIGN == r_type) + { + sym_sec = sec; + symval = rel->r_offset; +@@ -3976,9 +3986,9 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, + continue; + + if ((h->root.type == bfd_link_hash_defined +- || h->root.type == bfd_link_hash_defweak) +- && h->root.u.def.section != NULL +- && h->root.u.def.section->output_section != NULL) ++ || h->root.type == bfd_link_hash_defweak) ++ && h->root.u.def.section != NULL ++ && h->root.u.def.section->output_section != NULL) + { + symval = h->root.u.def.value; + sym_sec = h->root.u.def.section; +@@ -4004,12 +4014,21 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, + if (symtype != STT_SECTION) + symval += rel->r_addend; + } ++ /* For R_LARCH_ALIGN, symval is sec_addr (sym_sec) + rel->r_offset ++ + (alingmeng - 4). ++ If r_symndx is 0, alignmeng-4 is r_addend. ++ If r_symndx > 0, alignment-4 is 2^(r_addend & 0xff)-4. */ ++ else if (R_LARCH_ALIGN == r_type) ++ if (r_symndx > 0) ++ symval += ((1 << (rel->r_addend & 0xff)) - 4); ++ else ++ symval += rel->r_addend; + else + symval += rel->r_addend; + + symval += sec_addr (sym_sec); + +- switch (ELFNN_R_TYPE (rel->r_info)) ++ switch (r_type) + { + case R_LARCH_ALIGN: + if (1 == info->relax_pass) +diff --git a/bfd/elfxx-loongarch.c b/bfd/elfxx-loongarch.c +index d93b7904..679b79f3 100644 +--- a/bfd/elfxx-loongarch.c ++++ b/bfd/elfxx-loongarch.c +@@ -1395,9 +1395,13 @@ static loongarch_reloc_howto_type loongarch_howto_table = + NULL, /* adjust_reloc_bits. */ + NULL), /* larch_reloc_type_name. */ + +- /* Indicates an alignment statement. The addend field encodes how many +- bytes of NOPs follow the statement. The desired alignment is the +- addend rounded up to the next power of two. */ ++ /* Indicates an alignment statement. f the symbol index is 0, ++ the addend indicates the number of bytes occupied by nop instructions ++ at the relocation offset. The alignment boundary is specified by the ++ addend rounded up to the next power of two. ++ If the symbol index is not 0, the addend indicates the first and third
View file
_service:tar_scm:LoongArch-Add-testsuit-for-DESC-and-tls-transition-a.patch
Added
@@ -0,0 +1,669 @@ +From aaab3bca7ff42e982134fd638ad1ae8324260a8f Mon Sep 17 00:00:00 2001 +From: Lulu Cai <cailulu@loongson.cn> +Date: Wed, 13 Dec 2023 11:34:56 +0800 +Subject: PATCH 029/123 LoongArch: Add testsuit for DESC and tls transition + and tls relaxation. + +--- + gas/testsuite/gas/loongarch/tlsdesc_32.d | 27 ++++++++ + gas/testsuite/gas/loongarch/tlsdesc_32.s | 12 ++++ + gas/testsuite/gas/loongarch/tlsdesc_32_abs.d | 26 ++++++++ + gas/testsuite/gas/loongarch/tlsdesc_32_abs.s | 8 +++ + gas/testsuite/gas/loongarch/tlsdesc_64.d | 28 ++++++++ + gas/testsuite/gas/loongarch/tlsdesc_64.s | 12 ++++ + .../gas/loongarch/tlsdesc_large_abs.d | 34 ++++++++++ + .../gas/loongarch/tlsdesc_large_abs.s | 12 ++++ + .../gas/loongarch/tlsdesc_large_pc.d | 38 +++++++++++ + .../gas/loongarch/tlsdesc_large_pc.s | 17 +++++ + ld/testsuite/ld-loongarch-elf/desc-ie.d | 16 +++++ + ld/testsuite/ld-loongarch-elf/desc-ie.s | 18 +++++ + ld/testsuite/ld-loongarch-elf/desc-le.d | 15 +++++ + ld/testsuite/ld-loongarch-elf/desc-le.s | 14 ++++ + ld/testsuite/ld-loongarch-elf/desc-norelax.d | 16 +++++ + ld/testsuite/ld-loongarch-elf/desc-norelax.s | 5 ++ + ld/testsuite/ld-loongarch-elf/desc-relax.d | 15 +++++ + ld/testsuite/ld-loongarch-elf/desc-relax.s | 5 ++ + ld/testsuite/ld-loongarch-elf/ie-le.d | 13 ++++ + ld/testsuite/ld-loongarch-elf/ie-le.s | 11 ++++ + .../ld-loongarch-elf/ld-loongarch-elf.exp | 9 +++ + ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d | 56 ++++++++++++++++ + ld/testsuite/ld-loongarch-elf/tlsdesc-dso.s | 65 +++++++++++++++++++ + 23 files changed, 472 insertions(+) + create mode 100644 gas/testsuite/gas/loongarch/tlsdesc_32.d + create mode 100644 gas/testsuite/gas/loongarch/tlsdesc_32.s + create mode 100644 gas/testsuite/gas/loongarch/tlsdesc_32_abs.d + create mode 100644 gas/testsuite/gas/loongarch/tlsdesc_32_abs.s + create mode 100644 gas/testsuite/gas/loongarch/tlsdesc_64.d + create mode 100644 gas/testsuite/gas/loongarch/tlsdesc_64.s + create mode 100644 gas/testsuite/gas/loongarch/tlsdesc_large_abs.d + create mode 100644 gas/testsuite/gas/loongarch/tlsdesc_large_abs.s + create mode 100644 gas/testsuite/gas/loongarch/tlsdesc_large_pc.d + create mode 100644 gas/testsuite/gas/loongarch/tlsdesc_large_pc.s + create mode 100644 ld/testsuite/ld-loongarch-elf/desc-ie.d + create mode 100644 ld/testsuite/ld-loongarch-elf/desc-ie.s + create mode 100644 ld/testsuite/ld-loongarch-elf/desc-le.d + create mode 100644 ld/testsuite/ld-loongarch-elf/desc-le.s + create mode 100644 ld/testsuite/ld-loongarch-elf/desc-norelax.d + create mode 100644 ld/testsuite/ld-loongarch-elf/desc-norelax.s + create mode 100644 ld/testsuite/ld-loongarch-elf/desc-relax.d + create mode 100644 ld/testsuite/ld-loongarch-elf/desc-relax.s + create mode 100644 ld/testsuite/ld-loongarch-elf/ie-le.d + create mode 100644 ld/testsuite/ld-loongarch-elf/ie-le.s + create mode 100644 ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d + create mode 100644 ld/testsuite/ld-loongarch-elf/tlsdesc-dso.s + +diff --git a/gas/testsuite/gas/loongarch/tlsdesc_32.d b/gas/testsuite/gas/loongarch/tlsdesc_32.d +new file mode 100644 +index 00000000..eddcc5ed +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/tlsdesc_32.d +@@ -0,0 +1,27 @@ ++#as: ++#objdump: -dr ++#skip: loongarch64-*-* ++ ++.*: +file format .* ++ ++Disassembly of section .text: ++ ++0+ <.*>: ++ 0: 1a000004 pcalau12i \$a0, 0 ++ 0: R_LARCH_TLS_DESC_PC_HI20 var ++ 4: 02800084 addi.w \$a0, \$a0, 0 ++ 4: R_LARCH_TLS_DESC_PC_LO12 var ++ 8: 28800081 ld.w \$ra, \$a0, 0 ++ 8: R_LARCH_TLS_DESC_LD var ++ c: 4c000021 jirl \$ra, \$ra, 0 ++ c: R_LARCH_TLS_DESC_CALL var ++ 10: 1a000004 pcalau12i \$a0, 0 ++ 10: R_LARCH_TLS_DESC_PC_HI20 var ++ 10: R_LARCH_RELAX \*ABS\* ++ 14: 02800084 addi.w \$a0, \$a0, 0 ++ 14: R_LARCH_TLS_DESC_PC_LO12 var ++ 14: R_LARCH_RELAX \*ABS\* ++ 18: 28800081 ld.w \$ra, \$a0, 0 ++ 18: R_LARCH_TLS_DESC_LD var ++ 1c: 4c000021 jirl \$ra, \$ra, 0 ++ 1c: R_LARCH_TLS_DESC_CALL var +diff --git a/gas/testsuite/gas/loongarch/tlsdesc_32.s b/gas/testsuite/gas/loongarch/tlsdesc_32.s +new file mode 100644 +index 00000000..ef6aee94 +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/tlsdesc_32.s +@@ -0,0 +1,12 @@ ++.L1: ++ # R_LARCH_TLS_DESC_PC_HI20 var ++ pcalau12i $a0,%desc_pc_hi20(var) ++ # R_LARCH_TLS_DESC_PC_LO12 var ++ addi.w $a0,$a0,%desc_pc_lo12(var) ++ # R_LARCH_TLS_DESC_LD var ++ ld.w $ra,$a0,%desc_ld(var) ++ # R_LARCH_TLS_DESC_CALL var ++ jirl $ra,$ra,%desc_call(var) ++ ++ # test macro, pcalau12i + addi.w => pcaddi ++ la.tls.desc $a0,var +diff --git a/gas/testsuite/gas/loongarch/tlsdesc_32_abs.d b/gas/testsuite/gas/loongarch/tlsdesc_32_abs.d +new file mode 100644 +index 00000000..e787e409 +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/tlsdesc_32_abs.d +@@ -0,0 +1,26 @@ ++#as: -mla-global-with-abs ++#objdump: -dr ++#skip: loongarch64-*-* ++ ++.*: file format .* ++ ++ ++Disassembly of section .text: ++ ++0+ <.*>: ++ 0: 14000004 lu12i.w \$a0, 0 ++ 0: R_LARCH_TLS_DESC_HI20 var ++ 4: 03800084 ori \$a0, \$a0, 0x0 ++ 4: R_LARCH_TLS_DESC_LO12 var ++ 8: 28800081 ld.w \$ra, \$a0, 0 ++ 8: R_LARCH_TLS_DESC_LD var ++ c: 4c000021 jirl \$ra, \$ra, 0 ++ c: R_LARCH_TLS_DESC_CALL var ++ 10: 14000004 lu12i.w \$a0, 0 ++ 10: R_LARCH_TLS_DESC_HI20 var ++ 14: 03800084 ori \$a0, \$a0, 0x0 ++ 14: R_LARCH_TLS_DESC_LO12 var ++ 18: 28800081 ld.w \$ra, \$a0, 0 ++ 18: R_LARCH_TLS_DESC_LD var ++ 1c: 4c000021 jirl \$ra, \$ra, 0 ++ 1c: R_LARCH_TLS_DESC_CALL var +diff --git a/gas/testsuite/gas/loongarch/tlsdesc_32_abs.s b/gas/testsuite/gas/loongarch/tlsdesc_32_abs.s +new file mode 100644 +index 00000000..65d096ea +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/tlsdesc_32_abs.s +@@ -0,0 +1,8 @@ ++.L1: ++ lu12i.w $a0,%desc_hi20(var) ++ ori $a0,$a0,%desc_lo12(var) ++ ld.w $ra,$a0,%desc_ld(var) ++ jirl $ra,$ra,%desc_call(var) ++ ++ # Test macro expansion ++ la.tls.desc $a0,var +diff --git a/gas/testsuite/gas/loongarch/tlsdesc_64.d b/gas/testsuite/gas/loongarch/tlsdesc_64.d +new file mode 100644 +index 00000000..2a2829c9 +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/tlsdesc_64.d +@@ -0,0 +1,28 @@ ++#as: ++#objdump: -dr ++#skip: loongarch32-*-* ++ ++.*: file format .* ++ ++ ++Disassembly of section .text: ++ ++0+ <.*>: ++ 0: 1a000004 pcalau12i \$a0, 0 ++ 0: R_LARCH_TLS_DESC_PC_HI20 var ++ 4: 02c00084 addi.d \$a0, \$a0, 0 ++ 4: R_LARCH_TLS_DESC_PC_LO12 var ++ 8: 28c00081 ld.d \$ra, \$a0, 0 ++ 8: R_LARCH_TLS_DESC_LD var ++ c: 4c000021 jirl \$ra, \$ra, 0 ++ c: R_LARCH_TLS_DESC_CALL var ++ 10: 1a000004 pcalau12i \$a0, 0 ++ 10: R_LARCH_TLS_DESC_PC_HI20 var ++ 10: R_LARCH_RELAX \*ABS\* ++ 14: 02c00084 addi.d \$a0, \$a0, 0 ++ 14: R_LARCH_TLS_DESC_PC_LO12 var ++ 14: R_LARCH_RELAX \*ABS\* ++ 18: 28c00081 ld.d \$ra, \$a0, 0 ++ 18: R_LARCH_TLS_DESC_LD var ++ 1c: 4c000021 jirl \$ra, \$ra, 0 ++ 1c: R_LARCH_TLS_DESC_CALL var +diff --git a/gas/testsuite/gas/loongarch/tlsdesc_64.s b/gas/testsuite/gas/loongarch/tlsdesc_64.s +new file mode 100644 +index 00000000..9d0ccb17 +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/tlsdesc_64.s +@@ -0,0 +1,12 @@ ++.L1: ++ # R_LARCH_TLS_DESC_PC_HI20 var ++ pcalau12i $a0,%desc_pc_hi20(var) ++ # R_LARCH_TLS_DESC_PC_LO12 var ++ addi.d $a0,$a0,%desc_pc_lo12(var) ++ # R_LARCH_TLS_DESC_LD var ++ ld.d $ra,$a0,%desc_ld(var) ++ # R_LARCH_TLS_DESC_CALL var
View file
_service:tar_scm:LoongArch-Add-tls-transition-support.patch
Added
@@ -0,0 +1,325 @@ +From c5c96dc807dbb67b601ff90fb9976dc123d5b7af Mon Sep 17 00:00:00 2001 +From: Lulu Cai <cailulu@loongson.cn> +Date: Sun, 26 Nov 2023 14:25:26 +0800 +Subject: PATCH 027/123 LoongArch: Add tls transition support. + +Transitions between DESC->IE/LE and IE->LE are supported now. +1. For DESC -> LE: + pcalau12i $a0,%desc_pc_hi20(var) => lu12i.w $a0,%le_hi20(var) + addi.d $a0,$a0,%desc_pc_lo12(var) => ori $a0,$a0,%le_lo12(var) + ld.d $a1,$a0,%desc_ld(var) => NOP + jirl $ra,$a1,%desc_call(var) => NOP + add.d $a0,$a0,$tp +2. For DESC -> IE: + pcalau12i $a0,%desc_pc_hi20(var) => pcalau12i $a0,%ie_pc_hi20(var) + addi.d $a0,$a0,%desc_pc_lo12(var) => ld.d $a0,$a0,%ie_pc_lo12(var) + ld.d $a1,$a0,%desc_ld(var) => NOP + jirl $ra,$a1,%desc_call(var) => NOP + add.d $a0,$a0,$tp +3. For IE -> LE: + pcalau12i $a0,%ie_pc_hi20(var) => lu12i.w $a0,%le_hi20(var) + ld.d $a0,$a0,%ie_pc_lo12(var) => ori $a0,$a0,%le_lo12(var) + add.d $a0,$a0,$tp +4. When a tls variable is accessed using both DESC and IE, DESC transitions + to IE and uses the same GOT entry as IE. +--- + bfd/elfnn-loongarch.c | 216 ++++++++++++++++++++++++++++++++++++- + include/opcode/loongarch.h | 6 ++ + 2 files changed, 221 insertions(+), 1 deletion(-) + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index 31dde892..13fddd63 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -145,6 +145,16 @@ struct loongarch_elf_link_hash_table + #define elf_backend_rela_normal 1 + #define elf_backend_default_execstack 0 + ++#define IS_LOONGARCH_TLS_DESC_RELOC(R_TYPE) \ ++ ((R_TYPE) == R_LARCH_TLS_DESC_PC_HI20 \ ++ || (R_TYPE) == R_LARCH_TLS_DESC_PC_LO12 \ ++ || (R_TYPE) == R_LARCH_TLS_DESC_LD \ ++ || (R_TYPE) == R_LARCH_TLS_DESC_CALL) ++ ++#define IS_LOONGARCH_TLS_IE_RELOC(R_TYPE) \ ++ ((R_TYPE) == R_LARCH_TLS_IE_PC_HI20 \ ++ || (R_TYPE) == R_LARCH_TLS_IE_PC_LO12) ++ + /* Generate a PLT header. */ + + static bool +@@ -593,6 +603,10 @@ loongarch_elf_record_tls_and_got_reference (bfd *abfd, + + char *new_tls_type = &_bfd_loongarch_elf_tls_type (abfd, h, symndx); + *new_tls_type |= tls_type; ++ ++ /* If a symbol is accessed by both IE and DESC, relax DESC to IE. */ ++ if ((*new_tls_type & GOT_TLS_IE) && (*new_tls_type & GOT_TLS_GDESC)) ++ *new_tls_type &= ~ (GOT_TLS_GDESC); + if ((*new_tls_type & GOT_NORMAL) && (*new_tls_type & ~GOT_NORMAL)) + { + _bfd_error_handler (_("%pB: `%s' accessed both as normal and " +@@ -605,6 +619,104 @@ loongarch_elf_record_tls_and_got_reference (bfd *abfd, + return true; + } + ++static unsigned int ++loongarch_reloc_got_type (unsigned int r_type) ++{ ++ switch (r_type) ++ { ++ case R_LARCH_TLS_DESC_PC_HI20: ++ case R_LARCH_TLS_DESC_PC_LO12: ++ case R_LARCH_TLS_DESC_LD: ++ case R_LARCH_TLS_DESC_CALL: ++ return GOT_TLS_GDESC; ++ ++ case R_LARCH_TLS_IE_PC_HI20: ++ case R_LARCH_TLS_IE_PC_LO12: ++ return GOT_TLS_IE; ++ ++ default: ++ break; ++ } ++ return GOT_UNKNOWN; ++} ++ ++/* Return true if tls type transition can be performed. */ ++static bool ++loongarch_can_relax_tls (struct bfd_link_info *info, unsigned int r_type, ++ struct elf_link_hash_entry *h, bfd *input_bfd, ++ unsigned long r_symndx) ++{ ++ char symbol_tls_type; ++ unsigned int reloc_got_type; ++ ++ if (! (IS_LOONGARCH_TLS_DESC_RELOC (r_type) ++ || IS_LOONGARCH_TLS_IE_RELOC (r_type))) ++ return false; ++ ++ symbol_tls_type = _bfd_loongarch_elf_tls_type (input_bfd, h, r_symndx); ++ reloc_got_type = loongarch_reloc_got_type (r_type); ++ ++ if (symbol_tls_type == GOT_TLS_IE && GOT_TLS_GD_ANY_P (reloc_got_type)) ++ return true; ++ ++ if (! bfd_link_executable (info)) ++ return false; ++ ++ if (h && h->root.type == bfd_link_hash_undefweak) ++ return false; ++ ++ return true; ++} ++ ++/* The type of relocation that can be transitioned. */ ++static unsigned int ++loongarch_tls_transition_without_check (struct bfd_link_info *info, ++ unsigned int r_type, ++ struct elf_link_hash_entry *h) ++{ ++ bool local_exec = bfd_link_executable (info) ++ && SYMBOL_REFERENCES_LOCAL (info, h); ++ ++ switch (r_type) ++ { ++ case R_LARCH_TLS_DESC_PC_HI20: ++ return (local_exec ++ ? R_LARCH_TLS_LE_HI20 ++ : R_LARCH_TLS_IE_PC_HI20); ++ ++ case R_LARCH_TLS_DESC_PC_LO12: ++ return (local_exec ++ ? R_LARCH_TLS_LE_LO12 ++ : R_LARCH_TLS_IE_PC_LO12); ++ ++ case R_LARCH_TLS_DESC_LD: ++ case R_LARCH_TLS_DESC_CALL: ++ return R_LARCH_NONE; ++ ++ case R_LARCH_TLS_IE_PC_HI20: ++ return local_exec ? R_LARCH_TLS_LE_HI20 : r_type; ++ ++ case R_LARCH_TLS_IE_PC_LO12: ++ return local_exec ? R_LARCH_TLS_LE_LO12 : r_type; ++ ++ default: ++ break; ++ } ++ ++ return r_type; ++} ++ ++static unsigned int ++loongarch_tls_transition (struct bfd_link_info *info, unsigned int r_type, ++ struct elf_link_hash_entry *h, bfd *input_bfd, ++ unsigned long r_symndx) ++{ ++ if (! loongarch_can_relax_tls (info, r_type, h, input_bfd,r_symndx)) ++ return r_type; ++ ++ return loongarch_tls_transition_without_check (info, r_type, h); ++} ++ + /* Look through the relocs for a section during the first phase, and + allocate space in the global offset table or procedure linkage + table. */ +@@ -706,6 +818,7 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, + int need_dynreloc = 0; + int only_need_pcrel = 0; + ++ r_type = loongarch_tls_transition (info, r_type, h, abfd, r_symndx); + switch (r_type) + { + case R_LARCH_GOT_PC_HI20: +@@ -2403,6 +2516,96 @@ loongarch_reloc_is_fatal (struct bfd_link_info *info, + relocation += 0x100000000; \ + }) + ++/* Transition instruction sequence to relax instruction sequence. */ ++static bool ++loongarch_tls_relax (bfd *abfd, asection *sec, Elf_Internal_Rela *rel, ++ int r_type, struct elf_link_hash_entry *h, ++ struct bfd_link_info *info) ++{ ++ bool local_exec = bfd_link_executable (info) ++ && SYMBOL_REFERENCES_LOCAL (info, h); ++ bfd_byte *contents = elf_section_data (sec)->this_hdr.contents; ++ unsigned long insn; ++ ++ switch (r_type) ++ { ++ case R_LARCH_TLS_DESC_PC_HI20: ++ if (local_exec) ++ /* DESC -> LE relaxation: ++ pcalalau12i $a0,%desc_pc_hi20(var) => ++ lu12i.w $a0,%le_hi20(var) ++ */ ++ bfd_put (32, abfd, LARCH_LU12I_W | LARCH_RD_A0, ++ contents + rel->r_offset);
View file
_service:tar_scm:LoongArch-Allow-la.got-la.pcrel-relaxation-for-share.patch
Added
@@ -0,0 +1,68 @@ +From f1cef8611e241100dc6da362d27382b7fd543143 Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao <xry111@xry111.site> +Date: Wed, 6 Dec 2023 03:05:47 +0800 +Subject: PATCH 022/123 LoongArch: Allow la.got -> la.pcrel relaxation for + shared object + +Even in shared objects, la.got -> la.pcrel relaxation can still be +performed for symbols with hidden visibility. For example, if a.c is: + + extern int x; + int f() { return x++; } + +and b.c is: + + int x = 114514; + +If compiling and linking with: + + gcc -shared -fPIC -O2 -fvisibility=hidden a.c b.c + +Then the la.got in a.o should be relaxed to la.pcrel, and the resulted f +should be like: + + pcaddi $t0, x + ldptr.w $a0, $t0, 0 + addi.w $t1, $a0, 1 + stptr.w $t1, $t0, 0 + ret + +Remove bfd_link_executable from the condition of la.got -> la.pcrel +relaxation so this will really happen. The SYMBOL_REFERENCES_LOCAL +check is enough not to wrongly relax preemptable symbols (for e.g. +when -fvisibility=hidden is not used). + +Note that on x86_64 this is also relaxed and the produced code is like: + + lea x(%rip), %rdx + mov (%rdx), %rax + lea 1(%rax), %ecx + mov %ecx, (%rdx) + ret + +Tested by running ld test suite, bootstrapping and regtesting GCC with +the patched ld, and building and testing Glibc with the patched ld. No +regression is observed. + +Signed-off-by: Xi Ruoyao <xry111@xry111.site> +--- + bfd/elfnn-loongarch.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index 20dd0640..6fd6a04d 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -3986,8 +3986,7 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, + else + continue; + +- if (h && bfd_link_executable (info) +- && SYMBOL_REFERENCES_LOCAL (info, h)) ++ if (h && SYMBOL_REFERENCES_LOCAL (info, h)) + local_got = true; + symtype = h->type; + } +-- +2.33.0 +
View file
_service:tar_scm:LoongArch-Commas-inside-double-quotes.patch
Added
@@ -0,0 +1,43 @@ +From 0f5ce25e8a67bb55de5de18e02c8c9afe2a31ec7 Mon Sep 17 00:00:00 2001 +From: Alan Modra <amodra@gmail.com> +Date: Thu, 28 Dec 2023 22:12:17 +1030 +Subject: PATCH 036/123 LoongArch: Commas inside double quotes + +This adds an extra feature: Commas inside double quotes are not an +arg delimiter, and thus can be part of the arg. + + * loongarch-coder.c (loongarch_split_args_by_comma): Commas + inside quotes are not arg delimiters. +--- + opcodes/loongarch-coder.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +diff --git a/opcodes/loongarch-coder.c b/opcodes/loongarch-coder.c +index b6835276..c5b09509 100644 +--- a/opcodes/loongarch-coder.c ++++ b/opcodes/loongarch-coder.c +@@ -18,6 +18,7 @@ + along with this program; see the file COPYING3. If not, + see <http://www.gnu.org/licenses/>. */ + #include "sysdep.h" ++#include <stdbool.h> + #include "opcode/loongarch.h" + + int +@@ -256,9 +257,12 @@ loongarch_split_args_by_comma (char *args, const char *arg_strs) + + if (*args) + { ++ bool inquote = false; + arg_strsnum++ = args; + for (; *args; args++) +- if (*args == ',') ++ if (*args == '"') ++ inquote = !inquote; ++ else if (*args == ',' && !inquote) + { + if (MAX_ARG_NUM_PLUS_2 - 1 == num) + goto out; +-- +2.33.0 +
View file
_service:tar_scm:LoongArch-Correct-comments.patch
Added
@@ -0,0 +1,25 @@ +From 4744da32d9f3c4fb37f4ddf4019a514bbbbd5220 Mon Sep 17 00:00:00 2001 +From: caiyinyu <caiyinyu@loongson.cn> +Date: Tue, 17 Oct 2023 20:58:40 +0800 +Subject: PATCH 015/123 LoongArch: Correct comments. + +--- + bfd/elfnn-loongarch.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index 7dbe31eb..09c98713 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -2325,7 +2325,7 @@ loongarch_reloc_is_fatal (struct bfd_link_info *info, + addi.d $t0, $zero, lo12 (0x812) + $t0 = 0xfffffffffffff812 (if lo12 > 0x7ff, because sign-extend, + lo20 need to sub 0x1) +- lu32i.d $t0, lo12 (0x71234) ++ lu32i.d $t0, lo20 (0x71234) + $t0 = {0x71234, 0xfffff812} + = 0x71234fffff812 + lu52i.d $t0, hi12 (0x0) +-- +2.33.0 +
View file
_service:tar_scm:LoongArch-Delete-extra-instructions-when-TLS-type-tr.patch
Added
@@ -0,0 +1,652 @@ +From 2bd49b44dfe938623456d4abfef7f0c5f5b3b81f Mon Sep 17 00:00:00 2001 +From: Lulu Cai <cailulu@loongson.cn> +Date: Wed, 24 Jan 2024 17:43:20 +0800 +Subject: PATCH 069/123 LoongArch: Delete extra instructions when TLS type + transition + +This modification mainly changes the timing of type transition, +adds relaxation to the old LE instruction sequence, and fixes +bugs in extreme code models. + +We strictly distinguish between type transition and relaxation. +Type transition is from one type to another, while relaxation +is the removal of instructions under the same TLS type. Detailed +instructions are as follows: + +1. For type transition, only the normal code model of DESC/IE +does type transition, and each relocation is accompanied by a +RELAX relocation. Neither abs nor extreme will do type transition, +and no RELAX relocation will be generated. +The extra instructions when DESC transitions to other TLS types +will be deleted during the type transition. + +2. Implemented relaxation for the old LE instruction sequence. +The first two instructions of LE's 32-bit and 64-bit models +use the same relocations and cannot be distinguished based on +relocations. Therefore, for LE's instruction sequence, any code +model will try to relax. + +3. Some function names have been adjusted to facilitate understanding, +parameters have been adjusted, and unused macros have been deleted. +--- + bfd/elfnn-loongarch.c | 420 +++++++++++++++++++++++--------------- + gas/config/tc-loongarch.c | 31 ++- + 2 files changed, 279 insertions(+), 172 deletions(-) + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index 1693ad7e..eea1839f 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -145,16 +145,20 @@ struct loongarch_elf_link_hash_table + #define elf_backend_rela_normal 1 + #define elf_backend_default_execstack 0 + +-#define IS_LOONGARCH_TLS_DESC_RELOC(R_TYPE) \ +- ((R_TYPE) == R_LARCH_TLS_DESC_PC_HI20 \ +- || (R_TYPE) == R_LARCH_TLS_DESC_PC_LO12 \ +- || (R_TYPE) == R_LARCH_TLS_DESC_LD \ +- || (R_TYPE) == R_LARCH_TLS_DESC_CALL) +- +-#define IS_LOONGARCH_TLS_IE_RELOC(R_TYPE) \ +- ((R_TYPE) == R_LARCH_TLS_IE_PC_HI20 \ ++#define IS_LOONGARCH_TLS_TRANS_RELOC(R_TYPE) \ ++ ((R_TYPE) == R_LARCH_TLS_DESC_PC_HI20 \ ++ || (R_TYPE) == R_LARCH_TLS_DESC_PC_LO12 \ ++ || (R_TYPE) == R_LARCH_TLS_DESC_LD \ ++ || (R_TYPE) == R_LARCH_TLS_DESC_CALL \ ++ || (R_TYPE) == R_LARCH_TLS_IE_PC_HI20 \ + || (R_TYPE) == R_LARCH_TLS_IE_PC_LO12) + ++#define IS_OUTDATED_TLS_LE_RELOC(R_TYPE) \ ++ ((R_TYPE) == R_LARCH_TLS_LE_HI20 \ ++ || (R_TYPE) == R_LARCH_TLS_LE_LO12 \ ++ || (R_TYPE) == R_LARCH_TLS_LE64_LO20 \ ++ || (R_TYPE) == R_LARCH_TLS_LE64_HI12) ++ + /* Generate a PLT header. */ + + static bool +@@ -642,15 +646,18 @@ loongarch_reloc_got_type (unsigned int r_type) + + /* Return true if tls type transition can be performed. */ + static bool +-loongarch_can_relax_tls (struct bfd_link_info *info, unsigned int r_type, +- struct elf_link_hash_entry *h, bfd *input_bfd, +- unsigned long r_symndx) ++loongarch_can_trans_tls (bfd *input_bfd, ++ struct bfd_link_info *info, ++ struct elf_link_hash_entry *h, ++ unsigned int r_symndx, ++ unsigned int r_type) + { + char symbol_tls_type; + unsigned int reloc_got_type; + +- if (! (IS_LOONGARCH_TLS_DESC_RELOC (r_type) +- || IS_LOONGARCH_TLS_IE_RELOC (r_type))) ++ /* Only TLS DESC/IE in normal code mode will perform type ++ transition. */ ++ if (! IS_LOONGARCH_TLS_TRANS_RELOC (r_type)) + return false; + + symbol_tls_type = _bfd_loongarch_elf_tls_type (input_bfd, h, r_symndx); +@@ -707,11 +714,13 @@ loongarch_tls_transition_without_check (struct bfd_link_info *info, + } + + static unsigned int +-loongarch_tls_transition (struct bfd_link_info *info, unsigned int r_type, +- struct elf_link_hash_entry *h, bfd *input_bfd, +- unsigned long r_symndx) ++loongarch_tls_transition (bfd *input_bfd, ++ struct bfd_link_info *info, ++ struct elf_link_hash_entry *h, ++ unsigned int r_symndx, ++ unsigned int r_type) + { +- if (! loongarch_can_relax_tls (info, r_type, h, input_bfd,r_symndx)) ++ if (! loongarch_can_trans_tls (input_bfd, info, h, r_symndx, r_type)) + return r_type; + + return loongarch_tls_transition_without_check (info, r_type, h); +@@ -818,7 +827,11 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, + int need_dynreloc = 0; + int only_need_pcrel = 0; + +- r_type = loongarch_tls_transition (info, r_type, h, abfd, r_symndx); ++ /* Type transitions are only possible with relocations accompanied ++ by R_LARCH_RELAX. */ ++ if (rel + 1 != relocs + sec->reloc_count ++ && ELFNN_R_TYPE (rel1.r_info) == R_LARCH_RELAX) ++ r_type = loongarch_tls_transition (abfd, info, h, r_symndx, r_type); + switch (r_type) + { + case R_LARCH_GOT_PC_HI20: +@@ -2536,95 +2549,6 @@ loongarch_reloc_is_fatal (struct bfd_link_info *info, + relocation += 0x100000000; \ + }) + +-/* Transition instruction sequence to relax instruction sequence. */ +-static bool +-loongarch_tls_relax (bfd *abfd, asection *sec, Elf_Internal_Rela *rel, +- int r_type, struct elf_link_hash_entry *h, +- struct bfd_link_info *info) +-{ +- bool local_exec = bfd_link_executable (info) +- && SYMBOL_REFERENCES_LOCAL (info, h); +- bfd_byte *contents = elf_section_data (sec)->this_hdr.contents; +- unsigned long insn; +- +- switch (r_type) +- { +- case R_LARCH_TLS_DESC_PC_HI20: +- if (local_exec) +- /* DESC -> LE relaxation: +- pcalalau12i $a0,%desc_pc_hi20(var) => +- lu12i.w $a0,%le_hi20(var) +- */ +- bfd_put (32, abfd, LARCH_LU12I_W | LARCH_RD_A0, +- contents + rel->r_offset); +- +- /* DESC -> IE relaxation: +- pcalalau12i $a0,%desc_pc_hi20(var) => +- pcalalau12i $a0,%ie_pc_hi20(var) +- */ +- return true; +- +- case R_LARCH_TLS_DESC_PC_LO12: +- if (local_exec) +- { +- /* DESC -> LE relaxation: +- addi.d $a0,$a0,%desc_pc_lo12(var) => +- ori $a0,$a0,le_lo12(var) +- */ +- insn = LARCH_ORI | LARCH_RD_RJ_A0; +- bfd_put (32, abfd, LARCH_ORI | LARCH_RD_RJ_A0, +- contents + rel->r_offset); +- } +- else +- { +- /* DESC -> IE relaxation: +- addi.d $a0,$a0,%desc_pc_lo12(var) => +- ld.d $a0,$a0,%%ie_pc_lo12 +- */ +- bfd_put (32, abfd, LARCH_LD_D | LARCH_RD_RJ_A0, +- contents + rel->r_offset); +- } +- return true; +- +- case R_LARCH_TLS_DESC_LD: +- case R_LARCH_TLS_DESC_CALL: +- /* DESC -> LE/IE relaxation: +- ld.d $ra,$a0,%desc_ld(var) => NOP +- jirl $ra,$ra,%desc_call(var) => NOP +- */ +- bfd_put (32, abfd, LARCH_NOP, contents + rel->r_offset); +- return true; +- +- case R_LARCH_TLS_IE_PC_HI20: +- if (local_exec) +- { +- /* IE -> LE relaxation: +- pcalalau12i $rd,%ie_pc_hi20(var) => +- lu12i.w $rd,%le_hi20(var) +- */ +- insn = bfd_getl32 (contents + rel->r_offset); +- bfd_put (32, abfd, LARCH_LU12I_W | (insn & 0x1f), +- contents + rel->r_offset); +- } +- return true; +-
View file
_service:tar_scm:LoongArch-Disable-linker-relaxation-if-set-the-addre.patch
Added
@@ -0,0 +1,87 @@ +From 9bdf2be420d4477838bfb11d9cd4c2d6ad257119 Mon Sep 17 00:00:00 2001 +From: mengqinggang <mengqinggang@loongson.cn> +Date: Thu, 30 May 2024 19:52:34 +0800 +Subject: PATCH 090/123 LoongArch: Disable linker relaxation if set the + address of section or segment + +If set the address of section or segment, the offset from pc to symbol +may become bigger and cause overflow. +--- + ld/emultempl/loongarchelf.em | 16 ++++++++++++++++ + ld/testsuite/ld-loongarch-elf/relax-ttext.s | 13 +++++++++++++ + ld/testsuite/ld-loongarch-elf/relax.exp | 12 ++++++++++++ + 3 files changed, 41 insertions(+) + create mode 100644 ld/testsuite/ld-loongarch-elf/relax-ttext.s + +diff --git a/ld/emultempl/loongarchelf.em b/ld/emultempl/loongarchelf.em +index 99749894..13f8dacb 100644 +--- a/ld/emultempl/loongarchelf.em ++++ b/ld/emultempl/loongarchelf.em +@@ -25,6 +25,22 @@ fragment <<EOF + #include "elf/loongarch.h" + #include "elfxx-loongarch.h" + ++EOF ++ ++# Disable linker relaxation if set address of section or segment. ++PARSE_AND_LIST_ARGS_CASES=${PARSE_AND_LIST_ARGS_CASES}' ++ case OPTION_SECTION_START: ++ case OPTION_TTEXT: ++ case OPTION_TBSS: ++ case OPTION_TDATA: ++ case OPTION_TTEXT_SEGMENT: ++ case OPTION_TRODATA_SEGMENT: ++ case OPTION_TLDATA_SEGMENT: ++ link_info.disable_target_specific_optimizations = 2; ++ return false; ++' ++ ++fragment <<EOF + static void + larch_elf_before_allocation (void) + { +diff --git a/ld/testsuite/ld-loongarch-elf/relax-ttext.s b/ld/testsuite/ld-loongarch-elf/relax-ttext.s +new file mode 100644 +index 00000000..1bbd85a0 +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/relax-ttext.s +@@ -0,0 +1,13 @@ ++# At relax pass 0, offset is 0x120204000-0x12000bff8=0x1f8008 < 0x200000 ++# At relax pass 1, delete 0x7ff8 bytes NOP, ++# offset is 0x120204000-0x120004000=0x200000 >= 0x200000, overflow ++.text ++.align 14 # delete at relax pass 1 ++.fill 0x4000 ++.align 14 # delete at relax pass 1 ++la.local $t2, a # relax to pcaddi at relax pass 0 ++ ++.section ".text1", "ax" ++ .fill 0x4000 ++a: # 0x120204000 ++ ret +diff --git a/ld/testsuite/ld-loongarch-elf/relax.exp b/ld/testsuite/ld-loongarch-elf/relax.exp +index 05c4ed0a..05b268f4 100644 +--- a/ld/testsuite/ld-loongarch-elf/relax.exp ++++ b/ld/testsuite/ld-loongarch-elf/relax.exp +@@ -51,6 +51,18 @@ if istarget loongarch64-*-* { + run_dump_test "relax-align-ignore-start" + run_partial_linking_align_test + ++ run_ld_link_tests \ ++ list \ ++ list \ ++ "loongarch relax ttext" \ ++ "" "" \ ++ "" \ ++ {relax-ttext.s} \ ++ {} \ ++ "relax-ttext" \ ++ \ ++ ++ + set testname "loongarch relax .exe build" + set pre_builds list \ + list \ +-- +2.33.0 +
View file
_service:tar_scm:LoongArch-Discard-extra-spaces-in-objdump-output.patch
Added
@@ -0,0 +1,131 @@ +From c65840dfbeb0e2b292439b3627a0a29436649845 Mon Sep 17 00:00:00 2001 +From: Lulu Cai <cailulu@loongson.cn> +Date: Wed, 3 Jan 2024 19:57:10 +0800 +Subject: PATCH 041/123 LoongArch: Discard extra spaces in objdump output + +Due to the formatted output of objdump, some instructions +that do not require output operands (such as nop/ret) will +have extra spaces added after them. + +Determine whether to output operands through the format +of opcodes. When opc->format is an empty string, no extra +spaces are output. +--- + gas/testsuite/gas/loongarch/64_pcrel.d | 2 +- + .../gas/loongarch/deprecated_reg_aliases.d | 2 +- + gas/testsuite/gas/loongarch/jmp_op.d | 4 ++-- + gas/testsuite/gas/loongarch/nop.d | 2 +- + gas/testsuite/gas/loongarch/privilege_op.d | 14 +++++++------- + gas/testsuite/gas/loongarch/reloc.d | 2 +- + opcodes/loongarch-dis.c | 7 ++++++- + 7 files changed, 19 insertions(+), 14 deletions(-) + +diff --git a/gas/testsuite/gas/loongarch/64_pcrel.d b/gas/testsuite/gas/loongarch/64_pcrel.d +index 66b80a39..642e3079 100644 +--- a/gas/testsuite/gas/loongarch/64_pcrel.d ++++ b/gas/testsuite/gas/loongarch/64_pcrel.d +@@ -7,5 +7,5 @@ + Disassembly of section .text: + + 00000000.* <.text>: +- +0: +03400000 +nop + ++ +0: +03400000 +nop + +0: +R_LARCH_64_PCREL +\*ABS\* +diff --git a/gas/testsuite/gas/loongarch/deprecated_reg_aliases.d b/gas/testsuite/gas/loongarch/deprecated_reg_aliases.d +index 3ea08067..01e593fb 100644 +--- a/gas/testsuite/gas/loongarch/deprecated_reg_aliases.d ++++ b/gas/testsuite/gas/loongarch/deprecated_reg_aliases.d +@@ -15,4 +15,4 @@ Disassembly of section .text: + +8: +16024685 +lu32i\.d +\$a1, 4660 + +c: +08200420 +fmadd\.d +\$fa0, \$fa1, \$fa1, \$fa0 + +10: +380c16a4 +ldx\.d +\$a0, \$r21, \$a1 +- +14: +4c000020 +ret + ++ +14: +4c000020 +ret +diff --git a/gas/testsuite/gas/loongarch/jmp_op.d b/gas/testsuite/gas/loongarch/jmp_op.d +index cc544f11..21576072 100644 +--- a/gas/testsuite/gas/loongarch/jmp_op.d ++++ b/gas/testsuite/gas/loongarch/jmp_op.d +@@ -7,7 +7,7 @@ + Disassembly of section .text: + + 00000000.* <.L1>: +- +0: +03400000 +nop + ++ +0: +03400000 +nop + +4: +63fffc04 +bgtz +\$a0, +-4 +# +0 +<\.L1> + +4: +R_LARCH_B16 +\.L1 + +8: +67fff880 +bgez +\$a0, +-8 +# +0 +<\.L1> +@@ -47,4 +47,4 @@ Disassembly of section .text: + +4c: +R_LARCH_B16 +\.L1 + +50: +6fffb0a4 +bgeu +\$a1, +\$a0, +-80 +# +0 +<\.L1> + +50: +R_LARCH_B16 +\.L1 +- +54: +4c000020 +ret + ++ +54: +4c000020 +ret +diff --git a/gas/testsuite/gas/loongarch/nop.d b/gas/testsuite/gas/loongarch/nop.d +index 222456e8..ca8c5630 100644 +--- a/gas/testsuite/gas/loongarch/nop.d ++++ b/gas/testsuite/gas/loongarch/nop.d +@@ -7,4 +7,4 @@ + Disassembly of section .text: + + 0+000 <target>: +- +0: +03400000 +nop + ++ +0: +03400000 +nop +diff --git a/gas/testsuite/gas/loongarch/privilege_op.d b/gas/testsuite/gas/loongarch/privilege_op.d +index 73925f21..e9ca60b2 100644 +--- a/gas/testsuite/gas/loongarch/privilege_op.d ++++ b/gas/testsuite/gas/loongarch/privilege_op.d +@@ -31,13 +31,13 @@ Disassembly of section .text: + +54: +064814a4 +iocsrwr.h + +\$a0, \$a1 + +58: +064818a4 +iocsrwr.w + +\$a0, \$a1 + +5c: +06481ca4 +iocsrwr.d + +\$a0, \$a1 +- +60: +06482000 +tlbclr + +- +64: +06482400 +tlbflush + +- +68: +06482800 +tlbsrch + +- +6c: +06482c00 +tlbrd + +- +70: +06483000 +tlbwr + +- +74: +06483400 +tlbfill + +- +78: +06483800 +ertn + ++ +60: +06482000 +tlbclr ++ +64: +06482400 +tlbflush ++ +68: +06482800 +tlbsrch ++ +6c: +06482c00 +tlbrd ++ +70: +06483000 +tlbwr ++ +74: +06483400 +tlbfill ++ +78: +06483800 +ertn + +7c: +06488000 +idle + +0x0 + +80: +0648ffff +idle + +0x7fff + +84: +064998a0 +invtlb + +0x0, \$a1, \$a2 +diff --git a/gas/testsuite/gas/loongarch/reloc.d b/gas/testsuite/gas/loongarch/reloc.d +index 0458830f..fa249c58 100644 +--- a/gas/testsuite/gas/loongarch/reloc.d ++++ b/gas/testsuite/gas/loongarch/reloc.d +@@ -8,7 +8,7 @@ + Disassembly of section .text: + + 00000000.* <.text>: +- +0: +03400000 +nop + ++ +0: +03400000 +nop + +4: +58000085 +beq +\$a0, +\$a1, +0 +# +0x4 + +4: +R_LARCH_B16 +.L1 + +8: +5c000085 +bne +\$a0, +\$a1, +0 +# +0x8 +diff --git a/opcodes/loongarch-dis.c b/opcodes/loongarch-dis.c +index 969ea28f..941bf363 100644 +--- a/opcodes/loongarch-dis.c ++++ b/opcodes/loongarch-dis.c +@@ -267,7 +267,12 @@ disassemble_one (insn_t insn, struct disassemble_info *info) + } + + info->insn_type = dis_nonbranch; +- info->fprintf_styled_func (info->stream, dis_style_mnemonic, "%-12s", opc->name); ++ if (opc->format == NULL || opc->format0 == '\0') ++ info->fprintf_styled_func (info->stream, dis_style_mnemonic, ++ "%s", opc->name); ++ else ++ info->fprintf_styled_func (info->stream, dis_style_mnemonic, ++ "%-12s", opc->name); + + { + char *fake_args = xmalloc (strlen (opc->format) + 1); +-- +2.33.0 +
View file
_service:tar_scm:LoongArch-Do-not-add-DF_STATIC_TLS-for-TLS-LE.patch
Added
@@ -0,0 +1,27 @@ +From 85e65d5f829b23397ad39ad610589421e29c0e32 Mon Sep 17 00:00:00 2001 +From: Tatsuyuki Ishi <ishitatsuyuki@gmail.com> +Date: Thu, 28 Dec 2023 23:58:00 +0900 +Subject: PATCH 047/123 LoongArch: Do not add DF_STATIC_TLS for TLS LE + +TLS LE is exclusively for executables, while DF_STATIC_TLS is for DLLs. +DF_STATIC_TLS should only be set for TLS IE (and when it's DLL), not LE. +--- + bfd/elfnn-loongarch.c | 2 -- + 1 file changed, 2 deletions(-) + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index b0ebe89e..f57b6152 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -863,8 +863,6 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, + if (!bfd_link_executable (info)) + return false; + +- info->flags |= DF_STATIC_TLS; +- + if (!loongarch_elf_record_tls_and_got_reference (abfd, info, h, + r_symndx, + GOT_TLS_LE)) +-- +2.33.0 +
View file
_service:tar_scm:LoongArch-Do-not-check-R_LARCH_SOP_PUSH_ABSOLUTE-to-.patch
Added
@@ -0,0 +1,55 @@ +From 1f00570084528ffcc4764a7f31307e2b5d233301 Mon Sep 17 00:00:00 2001 +From: Lulu Cai <cailulu@loongson.cn> +Date: Wed, 19 Jun 2024 11:00:36 +0800 +Subject: PATCH 093/123 LoongArch: Do not check R_LARCH_SOP_PUSH_ABSOLUTE to + avoid broken links to old object files + +R_LARCH_SOP_PUSH_ABSOLUTE with -fPIC was heavily used in the era of gas-2.38. +We do not check this relocation to prevent broken links with old object +files. +--- + bfd/elfnn-loongarch.c | 11 ++++++----- + 1 file changed, 6 insertions(+), 5 deletions(-) + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index 51e3d311..840cdd35 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -756,10 +756,6 @@ loongarch_tls_transition (bfd *input_bfd, + return loongarch_tls_transition_without_check (info, r_type, h); + } + +-/* Look through the relocs for a section during the first phase, and +- allocate space in the global offset table or procedure linkage +- table. */ +- + static bool + bad_static_reloc (bfd *abfd, const Elf_Internal_Rela *rel, asection *sec, + unsigned r_type, struct elf_link_hash_entry *h, +@@ -787,6 +783,10 @@ bad_static_reloc (bfd *abfd, const Elf_Internal_Rela *rel, asection *sec, + return false; + } + ++/* Look through the relocs for a section during the first phase, and ++ allocate space in the global offset table or procedure linkage ++ table. */ ++ + static bool + loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, + asection *sec, const Elf_Internal_Rela *relocs) +@@ -948,10 +948,11 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, + break; + + case R_LARCH_ABS_HI20: +- case R_LARCH_SOP_PUSH_ABSOLUTE: + if (bfd_link_pic (info)) + return bad_static_reloc (abfd, rel, sec, r_type, h, isym); + ++ /* Fall through. */ ++ case R_LARCH_SOP_PUSH_ABSOLUTE: + if (h != NULL) + /* If this reloc is in a read-only section, we might + need a copy reloc. We can't check reliably at this +-- +2.33.0 +
View file
_service:tar_scm:LoongArch-Do-not-emit-R_LARCH_RELAX-for-two-register.patch
Added
@@ -0,0 +1,754 @@ +From ef4712b21aa2ab233282bc3aa38f21e6957a9db9 Mon Sep 17 00:00:00 2001 +From: mengqinggang <mengqinggang@loongson.cn> +Date: Wed, 10 Jan 2024 09:55:13 +0800 +Subject: PATCH 045/123 LoongArch: Do not emit R_LARCH_RELAX for two register + macros + +For two register macros (e.g. la.local $t0, $t1, symbol) used in extreme code +model, do not emit R_LARCH_RELAX relocations. +--- + gas/config/tc-loongarch.c | 45 ++- + .../gas/loongarch/macro_op_extreme_pc.d | 151 ++++--- + .../gas/loongarch/tlsdesc_large_pc.d | 58 ++- + ld/testsuite/ld-loongarch-elf/macro_op.d | 376 +++++++++--------- + 4 files changed, 311 insertions(+), 319 deletions(-) + +diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c +index fad18fcd..1ae57b45 100644 +--- a/gas/config/tc-loongarch.c ++++ b/gas/config/tc-loongarch.c +@@ -71,7 +71,17 @@ struct loongarch_cl_insn + long where; + /* The relocs associated with the instruction, if any. */ + fixS *fixpMAX_RELOC_NUMBER_A_INSN; +- long macro_id; ++ /* Represents macros or instructions expanded from macro. ++ For la.local -> la.pcrel or la.pcrel -> pcalau12i + addi.d, la.pcrel, ++ pcalau12i and addi.d are expanded from macro. ++ The first bit represents expanded from one register macro (e.g. ++ la.local $t0, symbol) and emit R_LARCH_RELAX relocations. ++ The second bit represents expanded from two registers macro (e.g. ++ la.local $t0, $t1, symbol) and not emit R_LARCH_RELAX relocations. ++ ++ The macros or instructions expanded from macros do not output register ++ deprecated warning. */ ++ unsigned int expand_from_macro; + }; + + #ifndef DEFAULT_ARCH +@@ -722,7 +732,10 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2, + ip->reloc_infoip->reloc_num.value = const_0; + ip->reloc_num++; + } +- if (LARCH_opts.relax && ip->macro_id ++ ++ /* Only one register macros (used in normal code model) ++ emit R_LARCH_RELAX. */ ++ if (LARCH_opts.relax && (ip->expand_from_macro & 1) + && (BFD_RELOC_LARCH_PCALA_HI20 == reloc_type + || BFD_RELOC_LARCH_PCALA_LO12 == reloc_type + || BFD_RELOC_LARCH_GOT_PC_HI20 == reloc_type +@@ -754,7 +767,9 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2, + imm = (intptr_t) str_hash_find (r_deprecated_htab, arg); + ip->match_now = 0 < imm; + ret = imm - 1; +- if (ip->match_now && !ip->macro_id) ++ /* !ip->expand_from_macro: avoiding duplicate output warnings, ++ only the first macro output warning. */ ++ if (ip->match_now && !ip->expand_from_macro) + as_warn (_("register alias %s is deprecated, use %s instead"), + arg, r_abi_namesret); + break; +@@ -773,7 +788,7 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2, + } + ip->match_now = 0 < imm; + ret = imm - 1; +- if (ip->match_now && !ip->macro_id) ++ if (ip->match_now && !ip->expand_from_macro) + break; + /* Handle potential usage of deprecated register aliases. */ + imm = (intptr_t) str_hash_find (f_deprecated_htab, arg); +@@ -1172,7 +1187,7 @@ assember_macro_helper (const char *const args, void *context_ptr) + * assuming 'not starting with space and not ending with space' or pass in + * empty c_str. */ + static void +-loongarch_assemble_INSNs (char *str, struct loongarch_cl_insn *ctx) ++loongarch_assemble_INSNs (char *str, unsigned int expand_from_macro) + { + char *rest; + size_t len_str = strlen(str); +@@ -1195,7 +1210,7 @@ loongarch_assemble_INSNs (char *str, struct loongarch_cl_insn *ctx) + + struct loongarch_cl_insn the_one = { 0 }; + the_one.name = str; +- the_one.macro_id = ctx->macro_id; ++ the_one.expand_from_macro = expand_from_macro; + + for (; *str && *str != ' '; str++) + ; +@@ -1217,29 +1232,37 @@ loongarch_assemble_INSNs (char *str, struct loongarch_cl_insn *ctx) + break; + + append_fixp_and_insn (&the_one); ++ ++ /* Expanding macro instructions. */ + if (the_one.insn_length == 0 && the_one.insn->macro) + { +- the_one.macro_id = 1; ++ unsigned int new_expand_from_macro = 0; ++ if (2 == the_one.arg_num) ++ new_expand_from_macro |= 1; ++ else if (3 == the_one.arg_num) ++ new_expand_from_macro |= 2; + + char *c_str = loongarch_expand_macro (the_one.insn->macro, + the_one.arg_strs, + assember_macro_helper, + &the_one, len_str); +- loongarch_assemble_INSNs (c_str, &the_one); ++ /* The first instruction expanded from macro. */ ++ loongarch_assemble_INSNs (c_str, new_expand_from_macro); + free (c_str); + } + } + while (0); + ++ /* The rest instructions expanded from macro, split by semicolon(;), ++ assembly one by one. */ + if (*rest != '\0') +- loongarch_assemble_INSNs (rest, ctx); ++ loongarch_assemble_INSNs (rest, expand_from_macro); + } + + void + md_assemble (char *str) + { +- struct loongarch_cl_insn the_one = { 0 }; +- loongarch_assemble_INSNs (str, &the_one); ++ loongarch_assemble_INSNs (str, 0); + } + + const char * +diff --git a/gas/testsuite/gas/loongarch/macro_op_extreme_pc.d b/gas/testsuite/gas/loongarch/macro_op_extreme_pc.d +index 8e4b6e6c..68fbb338 100644 +--- a/gas/testsuite/gas/loongarch/macro_op_extreme_pc.d ++++ b/gas/testsuite/gas/loongarch/macro_op_extreme_pc.d +@@ -2,87 +2,76 @@ + #objdump: -dr + #skip: loongarch32-*-* + +-.*: file format .* ++.*: +file format .* ++ + + Disassembly of section .text: + +-0+ <.L1>: +- 0: 1a000004 pcalau12i \$a0, 0 +- 0: R_LARCH_PCALA_HI20 .L1 +- 0: R_LARCH_RELAX \*ABS\* +- 4: 02c00005 li.d \$a1, 0 +- 4: R_LARCH_PCALA_LO12 .L1 +- 4: R_LARCH_RELAX \*ABS\* +- 8: 16000005 lu32i.d \$a1, 0 +- 8: R_LARCH_PCALA64_LO20 .L1 +- c: 030000a5 lu52i.d \$a1, \$a1, 0 +- c: R_LARCH_PCALA64_HI12 .L1 +- 10: 00109484 add.d \$a0, \$a0, \$a1 +- 14: 1a000004 pcalau12i \$a0, 0 +- 14: R_LARCH_PCALA_HI20 .L1 +- 14: R_LARCH_RELAX \*ABS\* +- 18: 02c00005 li.d \$a1, 0 +- 18: R_LARCH_PCALA_LO12 .L1 +- 18: R_LARCH_RELAX \*ABS\* +- 1c: 16000005 lu32i.d \$a1, 0 +- 1c: R_LARCH_PCALA64_LO20 .L1 +- 20: 030000a5 lu52i.d \$a1, \$a1, 0 +- 20: R_LARCH_PCALA64_HI12 .L1 +- 24: 00109484 add.d \$a0, \$a0, \$a1 +- 28: 1a000004 pcalau12i \$a0, 0 +- 28: R_LARCH_PCALA_HI20 .L1 +- 28: R_LARCH_RELAX \*ABS\* +- 2c: 02c00005 li.d \$a1, 0 +- 2c: R_LARCH_PCALA_LO12 .L1 +- 2c: R_LARCH_RELAX \*ABS\* +- 30: 16000005 lu32i.d \$a1, 0 +- 30: R_LARCH_PCALA64_LO20 .L1 +- 34: 030000a5 lu52i.d \$a1, \$a1, 0 +- 34: R_LARCH_PCALA64_HI12 .L1 +- 38: 00109484 add.d \$a0, \$a0, \$a1 +- 3c: 1a000004 pcalau12i \$a0, 0 +- 3c: R_LARCH_GOT_PC_HI20 .L1 +- 3c: R_LARCH_RELAX \*ABS\* +- 40: 02c00005 li.d \$a1, 0 +- 40: R_LARCH_GOT_PC_LO12 .L1 +- 40: R_LARCH_RELAX \*ABS\* +- 44: 16000005 lu32i.d \$a1, 0 +- 44: R_LARCH_GOT64_PC_LO20 .L1 +- 48: 030000a5 lu52i.d \$a1, \$a1, 0 +- 48: R_LARCH_GOT64_PC_HI12 .L1 +- 4c: 380c1484 ldx.d \$a0, \$a0, \$a1 +- 50: 14000004 lu12i.w \$a0, 0 +- 50: R_LARCH_TLS_LE_HI20 TLS1 +- 54: 03800084 ori \$a0, \$a0, 0x0 +- 54: R_LARCH_TLS_LE_LO12 TLS1 +- 58: 1a000004 pcalau12i \$a0, 0 +- 58: R_LARCH_TLS_IE_PC_HI20 TLS1 +- 5c: 02c00005 li.d \$a1, 0 +- 5c: R_LARCH_TLS_IE_PC_LO12 TLS1 +- 60: 16000005 lu32i.d \$a1, 0
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_service:tar_scm:LoongArch-Enable-gas-sort-relocs.patch
Added
@@ -0,0 +1,29 @@ +From c4da692895d01cf281c22efc2c30a6d4fdfb3d21 Mon Sep 17 00:00:00 2001 +From: Jinyang He <hejinyang@loongson.cn> +Date: Fri, 11 Aug 2023 16:10:40 +0800 +Subject: PATCH 009/123 LoongArch: Enable gas sort relocs + +The md_pre_output_hook creating fixup is asynchronous, causing relocs +may be out of order in .eh_frame. Define GAS_SORT_RELOCS so that reorder +relocs when write_relocs. + +Reported-by: Rui Ueyama <rui314@gmail.com> +--- + gas/config/tc-loongarch.h | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/gas/config/tc-loongarch.h b/gas/config/tc-loongarch.h +index d353f18d..fd094356 100644 +--- a/gas/config/tc-loongarch.h ++++ b/gas/config/tc-loongarch.h +@@ -123,6 +123,7 @@ extern void tc_loongarch_parse_to_dw2regnum (expressionS *); + + extern void loongarch_pre_output_hook (void); + #define md_pre_output_hook loongarch_pre_output_hook () ++#define GAS_SORT_RELOCS 1 + + #define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 0 + +-- +2.33.0 +
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_service:tar_scm:LoongArch-Fix-DT_RELR-and-relaxation-interaction.patch
Added
@@ -0,0 +1,74 @@ +From 9a78ebba126036f6ebdd15ffbe50ffbd8ccd84dd Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao <xry111@xry111.site> +Date: Mon, 12 Aug 2024 18:23:47 +0800 +Subject: PATCH 108/123 LoongArch: Fix DT_RELR and relaxation interaction + +Due to the way BFD implements DT_RELR as a part of relaxation, if in a +relax trip size_relative_relocs has changed the layout, when +relax_section runs only the vma of the section being relaxed is +guaranteed to be updated. Then bad thing can happen. For example, when +linking an auxilary program _freeze_module in the Python 3.12.4 building +system (with PGO + LTO), before sizing the .relr.dyn section, the vma of +.text is 30560 and the vma of .rodata is 2350944; in the final +executable the vma of .text is 36704 and the vma of .rodata is 2357024. +The vma increase is expected because .relr.dyn is squashed somewhere +before .text. But size_relative_relocs may see the state in which .text +is at 36704 but .rodata "is" still at 2350944. Thus the distance +between .text and .rodata can be under-estimated and overflowing +R_LARCH_PCREL20_S2 reloc can be created. + +To avoid this issue, if size_relative_relocs is updating the size of +.relr.dyn, just supress the normal relaxation in this relax trip. In +this situation size_relative_relocs should have been demending the next +relax trip, so the normal relaxation can happen in the next trip. + +I tried to make a reduced test case but failed. + +Signed-off-by: Xi Ruoyao <xry111@xry111.site> +--- + bfd/elfnn-loongarch.c | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index 73eea0f9..0c499c47 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -121,6 +121,12 @@ struct loongarch_elf_link_hash_table + + /* Layout recomputation count. */ + bfd_size_type relr_layout_iter; ++ ++ /* In BFD DT_RELR is implemented as a "relaxation." If in a relax trip ++ size_relative_relocs is updating the layout, relax_section may see ++ a partially updated state (some sections have vma updated but the ++ others do not), and it's unsafe to do the normal relaxation. */ ++ bool layout_mutating_for_relr; + }; + + struct loongarch_elf_section_data +@@ -2210,6 +2216,8 @@ loongarch_elf_size_relative_relocs (struct bfd_link_info *info, + *need_layout = false; + } + } ++ ++ htab->layout_mutating_for_relr = *need_layout; + return true; + } + +@@ -5256,6 +5264,13 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, + return true; + + struct loongarch_elf_link_hash_table *htab = loongarch_elf_hash_table (info); ++ ++ /* It may happen that some sections have updated vma but the others do ++ not. Go to the next relax trip (size_relative_relocs should have ++ been demending another relax trip anyway). */ ++ if (htab->layout_mutating_for_relr) ++ return true; ++ + if (bfd_link_relocatable (info) + || sec->sec_flg0 + || (sec->flags & SEC_RELOC) == 0 +-- +2.33.0 +
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_service:tar_scm:LoongArch-Fix-a-bug-of-getting-relocation-type.patch
Added
@@ -0,0 +1,27 @@ +From 8b0f08599a65c649ce88b53b8042a13d1b307371 Mon Sep 17 00:00:00 2001 +From: mengqinggang <mengqinggang@loongson.cn> +Date: Fri, 26 Jan 2024 11:16:49 +0800 +Subject: PATCH 054/123 LoongArch: Fix a bug of getting relocation type + +The old code works because R_LARCH_RELAX has no symbol index. It causes +'(rel + 1)->r_info == R_LARCH_RELAX' is 1 and ELFNN_R_TYPE (1) is 1. +--- + bfd/elfnn-loongarch.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index 858b95e1..2e72fe5c 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -4158,7 +4158,7 @@ loongarch_relax_tls_le (bfd *abfd, asection *sec, + static uint32_t insn_rj,insn_rd; + symval = symval - elf_hash_table (link_info)->tls_sec->vma; + /* Whether the symbol offset is in the interval (offset < 0x800). */ +- if (ELFNN_R_TYPE ((rel + 1)->r_info == R_LARCH_RELAX) && (symval < 0x800)) ++ if (ELFNN_R_TYPE ((rel + 1)->r_info) == R_LARCH_RELAX && (symval < 0x800)) + { + switch (ELFNN_R_TYPE (rel->r_info)) + { +-- +2.33.0 +
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_service:tar_scm:LoongArch-Fix-assertion-failure-with-DT_RELR.patch
Added
@@ -0,0 +1,87 @@ +From c49ea2f71e219ee85f2dd18ad18a928b135d45f9 Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao <xry111@xry111.site> +Date: Mon, 12 Aug 2024 18:23:46 +0800 +Subject: PATCH 107/123 LoongArch: Fix assertion failure with DT_RELR + +In the DT_RELR implementation I missed a code path emiting relative +reloc entries. Then the already packed relative reloc entries will be +(unnecessarily) pushed into .rela.dyn but we've not allocated the space +for them, triggering an assertion failure. + +Unfortunately I failed to notice the issue until profiled bootstrapping +GCC with LTO and -Wl,-z,pack-relative-relocs. The failure can be easily +triggered by linking a "hello world" program with -fprofile-generate and +LTO: + + $ PATH=$HOME/ld-test:$PATH gcc hw.c -fprofile-generate -Wl,-z,pack-relative-relocs -flto + /home/xry111/git-repos/binutils-build/TEST/ld: BFD (GNU Binutils) 2.43.50.20240802 assertion fail ../../binutils-gdb/bfd/elfnn-loongarch.c:2628 + /home/xry111/git-repos/binutils-build/TEST/ld: BFD (GNU Binutils) 2.43.50.20240802 assertion fail ../../binutils-gdb/bfd/elfnn-loongarch.c:2628 + collect2: error: ld returned 1 exit status + +And the reduced test case is just incredibly simple (included in the +patch) so it seems I'm just stupid enough to fail to detect it before. +Let's fix it now anyway. + +Signed-off-by: Xi Ruoyao <xry111@xry111.site> +--- + bfd/elfnn-loongarch.c | 3 ++- + ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp | 1 + + ld/testsuite/ld-loongarch-elf/relr-got-start.d | 7 +++++++ + ld/testsuite/ld-loongarch-elf/relr-got-start.s | 5 +++++ + 4 files changed, 15 insertions(+), 1 deletion(-) + create mode 100644 ld/testsuite/ld-loongarch-elf/relr-got-start.d + create mode 100644 ld/testsuite/ld-loongarch-elf/relr-got-start.s + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index adf16ddc..73eea0f9 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -4130,7 +4130,8 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, + bfd_link_pic (info), + h) + && bfd_link_pic (info) +- && LARCH_REF_LOCAL (info, h)) ++ && LARCH_REF_LOCAL (info, h) ++ && !info->enable_dt_relr) + { + Elf_Internal_Rela rela; + rela.r_offset = sec_addr (got) + got_off; +diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp +index 232e7c20..78726900 100644 +--- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp ++++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp +@@ -161,6 +161,7 @@ if istarget "loongarch64-*-*" { + run_dump_test "relr-data-pie" + run_dump_test "relr-discard-pie" + run_dump_test "relr-got-pie" ++ run_dump_test "relr-got-start" + run_dump_test "relr-text-pie" + run_dump_test "abssym_pie" + } +diff --git a/ld/testsuite/ld-loongarch-elf/relr-got-start.d b/ld/testsuite/ld-loongarch-elf/relr-got-start.d +new file mode 100644 +index 00000000..0b1a5b98 +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/relr-got-start.d +@@ -0,0 +1,7 @@ ++#source: relr-got-start.s ++#ld: -pie -z pack-relative-relocs -T relr-relocs.ld ++#readelf: -rW ++ ++Relocation section '\.relr\.dyn' at offset 0xa-z0-f+ contains 1 entry which relocates 1 location: ++Index: Entry Address Symbolic Address ++0000: 0000000000020008 0000000000020008 _GLOBAL_OFFSET_TABLE_ \+ 0x8 +diff --git a/ld/testsuite/ld-loongarch-elf/relr-got-start.s b/ld/testsuite/ld-loongarch-elf/relr-got-start.s +new file mode 100644 +index 00000000..c89fb425 +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/relr-got-start.s +@@ -0,0 +1,5 @@ ++.globl _start ++_start: ++ pcalau12i $r5,%got_pc_hi20(_start) ++ ld.d $r5,$r5,%got_pc_lo12(_start) ++ ret +-- +2.33.0 +
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_service:tar_scm:LoongArch-Fix-bad-reloc-with-mixed-visibility-ifunc-.patch
Added
@@ -0,0 +1,269 @@ +From 601d68c3a9866761ca19d1c27186f30de68a7af5 Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao <xry111@xry111.site> +Date: Sun, 30 Jun 2024 15:18:22 +0800 +Subject: PATCH 096/123 LoongArch: Fix bad reloc with mixed visibility ifunc + symbols in shared libraries + +With a simple test case: + + .globl ifunc + .globl ifunc_hidden + .hidden ifunc_hidden + .type ifunc, %gnu_indirect_function + .type ifunc_hidden, %gnu_indirect_function + + .text + .align 2 + ifunc: ret + ifunc_hidden: ret + + test: + bl ifunc + bl ifunc_hidden + +"ld -shared" produces a shared object with one R_LARCH_NONE (instead of +R_LARCH_JUMP_SLOT as we expect) to relocate the GOT entry of "ifunc". +It's because the indices in .plt and .rela.plt mismatches for +STV_DEFAULT STT_IFUNC symbols when another PLT entry exists for a +STV_HIDDEN STT_IFUNC symbol, and such a mismatch breaks the logic of +loongarch_elf_finish_dynamic_symbol. Fix the issue by reordering .plt +so the indices no longer mismatch. + +Signed-off-by: Xi Ruoyao <xry111@xry111.site> +--- + bfd/elfnn-loongarch.c | 77 ++++++++++++++++--- + ld/testsuite/ld-loongarch-elf/ifunc-reloc.d | 19 +++++ + ld/testsuite/ld-loongarch-elf/ifunc-reloc.s | 55 +++++++++++++ + .../ld-loongarch-elf/ld-loongarch-elf.exp | 1 + + 4 files changed, 140 insertions(+), 12 deletions(-) + create mode 100644 ld/testsuite/ld-loongarch-elf/ifunc-reloc.d + create mode 100644 ld/testsuite/ld-loongarch-elf/ifunc-reloc.s + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index fa0a5e38..6b1a4ecc 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -1716,9 +1716,10 @@ local_allocate_ifunc_dyn_relocs (struct bfd_link_info *info, + ifunc dynamic relocs. */ + + static bool +-elfNN_allocate_ifunc_dynrelocs (struct elf_link_hash_entry *h, void *inf) ++elfNN_allocate_ifunc_dynrelocs (struct elf_link_hash_entry *h, ++ struct bfd_link_info *info, ++ bool ref_local) + { +- struct bfd_link_info *info; + /* An example of a bfd_link_hash_indirect symbol is versioned + symbol. For example: __gxx_personality_v0(bfd_link_hash_indirect) + -> __gxx_personality_v0(bfd_link_hash_defined) +@@ -1734,20 +1735,18 @@ elfNN_allocate_ifunc_dynrelocs (struct elf_link_hash_entry *h, void *inf) + if (h->root.type == bfd_link_hash_warning) + h = (struct elf_link_hash_entry *) h->root.u.i.link; + +- info = (struct bfd_link_info *) inf; +- + /* Since STT_GNU_IFUNC symbol must go through PLT, we handle it + here if it is defined and referenced in a non-shared object. */ + if (h->type == STT_GNU_IFUNC && h->def_regular) + { +- if (SYMBOL_REFERENCES_LOCAL (info, h)) ++ if (ref_local && SYMBOL_REFERENCES_LOCAL (info, h)) + return local_allocate_ifunc_dyn_relocs (info, h, + &h->dyn_relocs, + PLT_ENTRY_SIZE, + PLT_HEADER_SIZE, + GOT_ENTRY_SIZE, + false); +- else ++ else if (!ref_local && !SYMBOL_REFERENCES_LOCAL (info, h)) + return _bfd_elf_allocate_ifunc_dyn_relocs (info, h, + &h->dyn_relocs, + PLT_ENTRY_SIZE, +@@ -1759,6 +1758,23 @@ elfNN_allocate_ifunc_dynrelocs (struct elf_link_hash_entry *h, void *inf) + return true; + } + ++static bool ++elfNN_allocate_ifunc_dynrelocs_ref_local (struct elf_link_hash_entry *h, ++ void *info) ++{ ++ return elfNN_allocate_ifunc_dynrelocs (h, (struct bfd_link_info *) info, ++ true); ++} ++ ++static bool ++elfNN_allocate_ifunc_dynrelocs_ref_global (struct elf_link_hash_entry *h, ++ void *info) ++{ ++ return elfNN_allocate_ifunc_dynrelocs (h, (struct bfd_link_info *) info, ++ false); ++} ++ ++ + /* Allocate space in .plt, .got and associated reloc sections for + ifunc dynamic relocs. */ + +@@ -1774,7 +1790,7 @@ elfNN_allocate_local_ifunc_dynrelocs (void **slot, void *inf) + || h->root.type != bfd_link_hash_defined) + abort (); + +- return elfNN_allocate_ifunc_dynrelocs (h, inf); ++ return elfNN_allocate_ifunc_dynrelocs_ref_local (h, inf); + } + + /* Set DF_TEXTREL if we find any dynamic relocs that apply to +@@ -1933,11 +1949,48 @@ loongarch_elf_size_dynamic_sections (bfd *output_bfd, + sym dynamic relocs. */ + elf_link_hash_traverse (&htab->elf, allocate_dynrelocs, info); + +- /* Allocate global ifunc sym .plt and .got entries, and space for global +- ifunc sym dynamic relocs. */ +- elf_link_hash_traverse (&htab->elf, elfNN_allocate_ifunc_dynrelocs, info); +- +- /* Allocate .plt and .got entries, and space for local ifunc symbols. */ ++ /* Allocate global ifunc sym .plt and .got entries, and space for ++ *preemptible* ifunc sym dynamic relocs. Note that we must do it ++ for *all* preemptible ifunc (including local ifuncs and STV_HIDDEN ++ ifuncs) before doing it for any non-preemptible ifunc symbol: ++ assuming we are not so careful, when we link a shared library the ++ correlation of .plt and .rela.plt might look like: ++ ++ idx in .plt idx in .rela.plt ++ ext_func1@plt 0 0 ++ ext_func2@plt 1 1 ++ ext_func3@plt 2 2 ++ hidden_ifunc1@plt 3 None: it's in .rela.got ++ hidden_ifunc2@plt 4 None: it's in .rela.got ++ normal_ifunc1@plt 5 != 3 ++ normal_ifunc2@plt 6 != 4 ++ local_ifunc@plt 7 None: it's in .rela.got ++ ++ Now oops the indices for normal_ifunc{1,2} in .rela.plt were different ++ from the indices in .plt :(. This would break finish_dynamic_symbol ++ which assumes the index in .rela.plt matches the index in .plt. ++ ++ So let's be careful and make it correct: ++ ++ idx in .plt idx in .rela.plt ++ ext_func1@plt 0 0 ++ ext_func2@plt 1 1 ++ ext_func3@plt 2 2 ++ normal_ifunc1@plt 3 3 ++ normal_ifunc2@plt 4 4 ++ hidden_ifunc1@plt 5 None: it's in .rela.got ++ hidden_ifunc2@plt 6 None: it's in .rela.got ++ local_ifunc@plt 7 None: it's in .rela.got ++ ++ Now normal_ifuncs first. */ ++ elf_link_hash_traverse (&htab->elf, ++ elfNN_allocate_ifunc_dynrelocs_ref_global, info); ++ ++ /* Next hidden_ifuncs follows. */ ++ elf_link_hash_traverse (&htab->elf, ++ elfNN_allocate_ifunc_dynrelocs_ref_local, info); ++ ++ /* Finally local_ifuncs. */ + htab_traverse (htab->loc_hash_table, + elfNN_allocate_local_ifunc_dynrelocs, info); + +diff --git a/ld/testsuite/ld-loongarch-elf/ifunc-reloc.d b/ld/testsuite/ld-loongarch-elf/ifunc-reloc.d +new file mode 100644 +index 00000000..cb592874 +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/ifunc-reloc.d +@@ -0,0 +1,19 @@ ++#ld: -shared ++#readelf: -Wr ++ ++#... ++.*'\.rela\.dyn'.* ++#... ++.* R_LARCH_RELATIVE .* ++.* R_LARCH_IRELATIVE .* ++.* R_LARCH_IRELATIVE .* ++.* R_LARCH_IRELATIVE .* ++#... ++.*'\.rela\.plt'.* ++#... ++.* R_LARCH_JUMP_SLOT .* ++.* R_LARCH_JUMP_SLOT .* ++.* R_LARCH_JUMP_SLOT .* ++.* R_LARCH_JUMP_SLOT .* ++.* R_LARCH_JUMP_SLOT .* ++.* R_LARCH_JUMP_SLOT .* +diff --git a/ld/testsuite/ld-loongarch-elf/ifunc-reloc.s b/ld/testsuite/ld-loongarch-elf/ifunc-reloc.s +new file mode 100644 +index 00000000..e59f2b20 +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/ifunc-reloc.s +@@ -0,0 +1,55 @@
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_service:tar_scm:LoongArch-Fix-dwarf3-test-cases-from-XPASS-to-PASS.patch
Added
@@ -0,0 +1,38 @@ +From 30f91452b13e20976c0d470f1e097c083571459b Mon Sep 17 00:00:00 2001 +From: Lulu Cai <cailulu@loongson.cn> +Date: Thu, 11 Jul 2024 19:00:43 +0800 +Subject: PATCH 102/123 LoongArch: Fix dwarf3 test cases from XPASS to PASS + +In the past, the .align directive generated a label that did not match +the regular expression, and we set it to XFAIL. +But now it matches fine so it becomes XPASS. We fix it with PASS. +--- + ld/testsuite/ld-elf/dwarf.exp | 5 ----- + 1 file changed, 5 deletions(-) + +diff --git a/ld/testsuite/ld-elf/dwarf.exp b/ld/testsuite/ld-elf/dwarf.exp +index 5cb2aab9..3d1b99ac 100644 +--- a/ld/testsuite/ld-elf/dwarf.exp ++++ b/ld/testsuite/ld-elf/dwarf.exp +@@ -52,9 +52,6 @@ set build_tests { + {"DWARF parse during linker error" + "" "-fno-toplevel-reorder" + {dwarf2a.c dwarf2b.c} {{error_output "dwarf2.err"}} "dwarf2.x"} +-} +- +-set build_tests_dwarf3 { + {"Handle no DWARF information" + "" "-g0" + {dwarf3.c} {{error_output "dwarf3.err"}} "dwarf3.x"} +@@ -75,8 +72,6 @@ set run_tests { + set old_CFLAGS "$CFLAGS_FOR_TARGET" + append CFLAGS_FOR_TARGET " $NOSANITIZE_CFLAGS" + run_cc_link_tests $build_tests +-setup_xfail loongarch*-*-* +-run_cc_link_tests $build_tests_dwarf3 + run_ld_link_exec_tests $run_tests + set CFLAGS_FOR_TARGET "$old_CFLAGS" + +-- +2.33.0 +
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_service:tar_scm:LoongArch-Fix-gas-and-ld-test-cases.patch
Added
@@ -0,0 +1,149 @@ +From e361b5c22683557c2214f8bb9032d80bb7c3d4e0 Mon Sep 17 00:00:00 2001 +From: Lulu Cai <cailulu@loongson.cn> +Date: Thu, 7 Mar 2024 11:09:14 +0800 +Subject: PATCH 072/123 LoongArch: Fix gas and ld test cases + +* After adding the old LE relax, all old LE relocations will have + an R_LARCH_RELAX relocation. Fix the gas test case failure caused + by the implementation of the old LE relax. + +* loongarch64-elf does not support pie and -z norelro options, + removed in test files. +--- + gas/testsuite/gas/loongarch/relocs_32.d | 2 ++ + gas/testsuite/gas/loongarch/relocs_64.d | 4 ++++ + ld/testsuite/ld-loongarch-elf/desc-le-norelax.d | 2 +- + ld/testsuite/ld-loongarch-elf/desc-le-relax.d | 2 +- + ld/testsuite/ld-loongarch-elf/ie-le-norelax.d | 2 +- + ld/testsuite/ld-loongarch-elf/ie-le-relax.d | 2 +- + ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp | 5 ++++- + ld/testsuite/ld-loongarch-elf/macro_op_32.d | 4 ++++ + 8 files changed, 18 insertions(+), 5 deletions(-) + +diff --git a/gas/testsuite/gas/loongarch/relocs_32.d b/gas/testsuite/gas/loongarch/relocs_32.d +index 3e1bb62e..96ef2800 100644 +--- a/gas/testsuite/gas/loongarch/relocs_32.d ++++ b/gas/testsuite/gas/loongarch/relocs_32.d +@@ -30,8 +30,10 @@ Disassembly of section .text: + 24: R_LARCH_GOT_LO12 .L1 + 28: 14000004 lu12i.w \$a0, 0 + 28: R_LARCH_TLS_LE_HI20 TLSL1 ++ 28: R_LARCH_RELAX \*ABS\* + 2c: 03800085 ori \$a1, \$a0, 0x0 + 2c: R_LARCH_TLS_LE_LO12 TLSL1 ++ 2c: R_LARCH_RELAX \*ABS\* + 30: 1a000004 pcalau12i \$a0, 0 + 30: R_LARCH_TLS_IE_PC_HI20 TLSL1 + 34: 02c00005 li.d \$a1, 0 +diff --git a/gas/testsuite/gas/loongarch/relocs_64.d b/gas/testsuite/gas/loongarch/relocs_64.d +index 631137eb..35dde02f 100644 +--- a/gas/testsuite/gas/loongarch/relocs_64.d ++++ b/gas/testsuite/gas/loongarch/relocs_64.d +@@ -48,12 +48,16 @@ Disassembly of section .text: + 48: R_LARCH_GOT64_HI12 .L1 + 4c: 14000004 lu12i.w \$a0, 0 + 4c: R_LARCH_TLS_LE_HI20 TLSL1 ++ 4c: R_LARCH_RELAX \*ABS\* + 50: 03800085 ori \$a1, \$a0, 0x0 + 50: R_LARCH_TLS_LE_LO12 TLSL1 ++ 50: R_LARCH_RELAX \*ABS\* + 54: 16000004 lu32i.d \$a0, 0 + 54: R_LARCH_TLS_LE64_LO20 TLSL1 ++ 54: R_LARCH_RELAX \*ABS\* + 58: 03000085 lu52i.d \$a1, \$a0, 0 + 58: R_LARCH_TLS_LE64_HI12 TLSL1 ++ 58: R_LARCH_RELAX \*ABS\* + 5c: 1a000004 pcalau12i \$a0, 0 + 5c: R_LARCH_TLS_IE_PC_HI20 TLSL1 + 60: 02c00005 li.d \$a1, 0 +diff --git a/ld/testsuite/ld-loongarch-elf/desc-le-norelax.d b/ld/testsuite/ld-loongarch-elf/desc-le-norelax.d +index 5a53245a..43749f1b 100644 +--- a/ld/testsuite/ld-loongarch-elf/desc-le-norelax.d ++++ b/ld/testsuite/ld-loongarch-elf/desc-le-norelax.d +@@ -1,5 +1,5 @@ + #as: +-#ld: -z norelro -e0 --no-relax ++#ld: -e0 --no-relax + #objdump: -dr + #skip: loongarch32-*-* + +diff --git a/ld/testsuite/ld-loongarch-elf/desc-le-relax.d b/ld/testsuite/ld-loongarch-elf/desc-le-relax.d +index 03b5535e..71a540fd 100644 +--- a/ld/testsuite/ld-loongarch-elf/desc-le-relax.d ++++ b/ld/testsuite/ld-loongarch-elf/desc-le-relax.d +@@ -1,5 +1,5 @@ + #as: +-#ld: -z norelro -e0 ++#ld: -e0 + #objdump: -dr -M no-aliases + #skip: loongarch32-*-* + +diff --git a/ld/testsuite/ld-loongarch-elf/ie-le-norelax.d b/ld/testsuite/ld-loongarch-elf/ie-le-norelax.d +index 81d78ca3..0221b495 100644 +--- a/ld/testsuite/ld-loongarch-elf/ie-le-norelax.d ++++ b/ld/testsuite/ld-loongarch-elf/ie-le-norelax.d +@@ -1,5 +1,5 @@ + #as: +-#ld: -z norelro -e0 --no-relax ++#ld: -e0 --no-relax + #objdump: -dr + #skip: loongarch32-*-* + +diff --git a/ld/testsuite/ld-loongarch-elf/ie-le-relax.d b/ld/testsuite/ld-loongarch-elf/ie-le-relax.d +index 03b5535e..71a540fd 100644 +--- a/ld/testsuite/ld-loongarch-elf/ie-le-relax.d ++++ b/ld/testsuite/ld-loongarch-elf/ie-le-relax.d +@@ -1,5 +1,5 @@ + #as: +-#ld: -z norelro -e0 ++#ld: -e0 + #objdump: -dr -M no-aliases + #skip: loongarch32-*-* + +diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp +index ca428f5b..c839f525 100644 +--- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp ++++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp +@@ -133,6 +133,10 @@ if istarget "loongarch64-*-*" { + run_dump_test "desc-relax" + } + ++ if check_pie_support { ++ run_dump_test "pie_discard" ++ } ++ + run_dump_test "max_imm_b16" + run_dump_test "max_imm_b21" + run_dump_test "max_imm_b26" +@@ -145,7 +149,6 @@ if istarget "loongarch64-*-*" { + run_dump_test "underflow_b21" + run_dump_test "underflow_b26" + run_dump_test "underflow_pcrel20" +- run_dump_test "pie_discard" + run_dump_test "desc-le-norelax" + run_dump_test "desc-le-relax" + run_dump_test "ie-le-norelax" +diff --git a/ld/testsuite/ld-loongarch-elf/macro_op_32.d b/ld/testsuite/ld-loongarch-elf/macro_op_32.d +index a7349aa8..8fd69922 100644 +--- a/ld/testsuite/ld-loongarch-elf/macro_op_32.d ++++ b/ld/testsuite/ld-loongarch-elf/macro_op_32.d +@@ -49,12 +49,16 @@ Disassembly of section .text: + 3c: R_LARCH_RELAX \*ABS\* + 40: 14000004 lu12i.w \$a0, 0 + 40: R_LARCH_TLS_LE_HI20 TLS1 ++ 40: R_LARCH_RELAX \*ABS\* + 44: 03800084 ori \$a0, \$a0, 0x0 + 44: R_LARCH_TLS_LE_LO12 TLS1 ++ 44: R_LARCH_RELAX \*ABS\* + 48: 1a000004 pcalau12i \$a0, 0 + 48: R_LARCH_TLS_IE_PC_HI20 TLS1 ++ 48: R_LARCH_RELAX \*ABS\* + 4c: 28800084 ld.w \$a0, \$a0, 0 + 4c: R_LARCH_TLS_IE_PC_LO12 TLS1 ++ 4c: R_LARCH_RELAX \*ABS\* + 50: 1a000004 pcalau12i \$a0, 0 + 50: R_LARCH_TLS_LD_PC_HI20 TLS1 + 50: R_LARCH_RELAX \*ABS\* +-- +2.33.0 +
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_service:tar_scm:LoongArch-Fix-immediate-overflow-check-bug.patch
Added
@@ -0,0 +1,42 @@ +From 1dfd5f57202ef519e7ae21219be9c16e7a163072 Mon Sep 17 00:00:00 2001 +From: mengqinggang <mengqinggang@loongson.cn> +Date: Sat, 15 Jul 2023 17:56:07 +0800 +Subject: PATCH 001/123 LoongArch: Fix immediate overflow check bug + +For B16/B21/B26/PCREL20_S2 relocations, if immediate overflow check after +rightshift, and the mask need to include sign bit. + +Now, the immediate overflow check before rightshift for easier understand. + +bfd/ChangeLog: + + * elfxx-loongarch.c (reloc_bits_pcrel20_s2): Delete. + (reloc_bits_b16): Delete. + (reloc_bits_b21): Delete. + (reloc_bits_b26): Delete. + (reloc_sign_bits): New. +--- + bfd/elfxx-loongarch.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/bfd/elfxx-loongarch.c b/bfd/elfxx-loongarch.c +index 35676ead..16a2b2fc 100644 +--- a/bfd/elfxx-loongarch.c ++++ b/bfd/elfxx-loongarch.c +@@ -1708,10 +1708,12 @@ reloc_sign_bits (bfd *abfd, reloc_howto_type *howto, bfd_vma *fix_val) + { + case R_LARCH_SOP_POP_32_S_0_10_10_16_S2: + case R_LARCH_B26: +- /* Perform insn bits field. 25:16>>16, 15:0<<10. */ ++ /* Perform insn bits field. 15:0<<10, 25:16>>16. */ + val = ((val & 0xffff) << 10) | ((val >> 16) & 0x3ff); + break; ++ case R_LARCH_SOP_POP_32_S_0_5_10_16_S2: + case R_LARCH_B21: ++ /* Perform insn bits field. 15:0<<10, 20:16>>16. */ + val = ((val & 0xffff) << 10) | ((val >> 16) & 0x1f); + break; + default: +-- +2.33.0 +
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_service:tar_scm:LoongArch-Fix-ld-FAIL-test-cases.patch
Added
@@ -0,0 +1,91 @@ +From 32434338ecb0d5547e2cb7986f98040bc726f43f Mon Sep 17 00:00:00 2001 +From: Lulu Cai <cailulu@loongson.cn> +Date: Wed, 17 Jul 2024 10:54:46 +0800 +Subject: PATCH 104/123 LoongArch: Fix ld FAIL test cases + +To avoid differences in C library paths on different systems +use gcc instead of ld to perform the test. + +Problems caused by adding options to different distributions +will not be fixed. +--- + ld/testsuite/ld-loongarch-elf/pic.exp | 41 ++++++++++++++++----------- + 1 file changed, 24 insertions(+), 17 deletions(-) + +diff --git a/ld/testsuite/ld-loongarch-elf/pic.exp b/ld/testsuite/ld-loongarch-elf/pic.exp +index 2ca5b3a0..241d198d 100644 +--- a/ld/testsuite/ld-loongarch-elf/pic.exp ++++ b/ld/testsuite/ld-loongarch-elf/pic.exp +@@ -92,17 +92,6 @@ set link_tests list \ + \ + "nopic-global" \ + \ +- list \ +- "$testname readelf -s/-r nopic-global-so" \ +- "-L./tmpdir -lnopic-global -L/usr/lib -lc" "" \ +- "" \ +- {nopic-global.s} \ +- list \ +- list readelf -s nopic-global-so.sd \ +- list readelf -r nopic-global-so.rd \ +- \ +- "nopic-global-so" \ +- \ + list \ + "$testname readelf -s/-x nopic-weak-global" \ + "-T pic.ld" "" \ +@@ -114,19 +103,35 @@ set link_tests list \ + \ + "nopic-weak-global" \ + \ ++ ++ ++# Since the c library path may be different in different ++# Distributions, the test program can link to the c library ++# using the gcc instead of ld to avoid system impact. ++run_ld_link_tests $link_tests ++ ++ ++ ++set link_tests_libc list \ ++ list \ ++ "$testname readelf -s/-r nopic-global-so" \ ++ "-L./tmpdir -lnopic-global -L/usr/lib -lc" "" \ ++ {nopic-global.s} \ ++ {{readelf {-s} nopic-global-so.sd} \ ++ {readelf {-r} nopic-global-so.rd}} \ ++ "nopic-global-so" \ ++ \ + list \ + "$testname readelf -s/-x nopic-weak-global-so" \ + "-L./tmpdir -lnopic-global -L/usr/lib -lc" "" \ +- "" \ + {nopic-weak-global.s} \ +- list \ +- list readelf -s nopic-weak-global-so.sd \ +- list readelf -r nopic-weak-global-so.rd \ +- \ ++ {{readelf {-s} nopic-weak-global-so.sd} \ ++ {readelf {-r} nopic-weak-global-so.rd}} \ + "nopic-weak-global-so" \ + \ + + ++ + # 0:name + # 1:ld/ar leading options, placed before object files + # 2:ld/ar trailing options, placed after object files +@@ -135,7 +140,9 @@ set link_tests list \ + # 5:list of actions, options and expected outputs. + # 6:name of output file + # 7:compiler flags (optional) +-run_ld_link_tests $link_tests ++run_cc_link_tests $link_tests_libc ++ ++ + + set testname "nopic link exec test" + +-- +2.33.0 +
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_service:tar_scm:LoongArch-Fix-ld-test-failures-caused-by-using-instr.patch
Added
@@ -0,0 +1,29 @@ +From 765057030817ea3083dd7a7ca607c89d21d4eed3 Mon Sep 17 00:00:00 2001 +From: Lulu Cai <cailulu@loongson.cn> +Date: Tue, 23 Apr 2024 15:49:09 +0800 +Subject: PATCH 085/123 LoongArch: Fix ld test failures caused by using + instruction aliases + +Different versions of objdump may take different forms of output +for instructions. Use -M no-aliases to avoid the failure of ld +test cases caused by objdump using aliases. +--- + ld/testsuite/ld-loongarch-elf/relax.exp | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/ld/testsuite/ld-loongarch-elf/relax.exp b/ld/testsuite/ld-loongarch-elf/relax.exp +index bfd6d1c0..c1da9c10 100644 +--- a/ld/testsuite/ld-loongarch-elf/relax.exp ++++ b/ld/testsuite/ld-loongarch-elf/relax.exp +@@ -37,7 +37,7 @@ proc run_partial_linking_align_test {} { + || !ld_link $ld tmpdir/$testname "tmpdir/$testname.os -e0 -Ttext 0x1000" } { + fail $testname + } else { +- set objdump_output run_host_cmd "objdump" "-d tmpdir/$testname" ++ set objdump_output run_host_cmd "objdump" "-d -M no-aliases tmpdir/$testname" + if { regexp ".*1010:\\s*4c000020\\s*jirl.*" $objdump_output } { + pass $testname + } else { +-- +2.33.0 +
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_service:tar_scm:LoongArch-Fix-linker-generate-PLT-entry-for-data-sym.patch
Added
@@ -0,0 +1,121 @@ +From 9836fa5ff54d6543ab05e552579810ef150d8a77 Mon Sep 17 00:00:00 2001 +From: mengqinggang <mengqinggang@loongson.cn> +Date: Thu, 1 Dec 2022 17:23:14 +0800 +Subject: PATCH 039/123 LoongArch: Fix linker generate PLT entry for data + symbol + +With old "medium" code model, we call a function with a pair of PCALAU12I +and JIRL instructions. The assembler produces something like: + + 8: 1a00000c pcalau12i $t0, 0 + 8: R_LARCH_PCALA_HI20 g + c: 4c000181 jirl $ra, $t0, 0 + c: R_LARCH_PCALA_LO12 g + +The linker generates a "PLT entry" for data without any diagnostic. +If "g" is a data symbol and ld with -shared option, it may load two +instructions in the PLT. + +Without -shared option, loongarch_elf_adjust_dynamic_symbol can delete PLT +entry. + +For R_LARCH_PCALA_HI20 relocation, linker only generate PLT entry for STT_FUNC +and STT_GNU_IFUNC symbols. +--- + bfd/elfnn-loongarch.c | 6 ++++- + ld/testsuite/ld-loongarch-elf/data-plt.s | 20 ++++++++++++++++ + .../ld-loongarch-elf/ld-loongarch-elf.exp | 24 +++++++++++++++++++ + ld/testsuite/ld-loongarch-elf/libjirl.s | 1 + + 4 files changed, 50 insertions(+), 1 deletion(-) + create mode 100644 ld/testsuite/ld-loongarch-elf/data-plt.s + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index f7eb66da..73e4b819 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -891,8 +891,12 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, + h->non_got_ref = 1; + break; + ++ /* For normal cmodel, pcalau12i + addi.d/w used to data. ++ For first version medium cmodel, pcalau12i + jirl are used to ++ function call, it need to creat PLT entry for STT_FUNC and ++ STT_GNU_IFUNC type symbol. */ + case R_LARCH_PCALA_HI20: +- if (h != NULL) ++ if (h != NULL && (STT_FUNC == h->type || STT_GNU_IFUNC == h->type)) + { + /* For pcalau12i + jirl. */ + h->needs_plt = 1; +diff --git a/ld/testsuite/ld-loongarch-elf/data-plt.s b/ld/testsuite/ld-loongarch-elf/data-plt.s +new file mode 100644 +index 00000000..faff052c +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/data-plt.s +@@ -0,0 +1,20 @@ ++# The first version medium codel model function call is: pcalau12i + jirl. ++# R_LARCH_PCALA_HI20 only need to generate PLT entry for function symbols. ++ .text ++ .globl a ++ ++ .data ++ .align 2 ++ .type a, @object ++ .size a, 4 ++a: ++ .word 1 ++ ++ .text ++ .align 2 ++ .globl test ++ .type test, @function ++test: ++ pcalau12i $r12,%pc_hi20(a) ++ ld.w $r12,$r12,%pc_lo12(a) ++ .size test, .-test +diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp +index 8dc04fea..64e644d3 100644 +--- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp ++++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp +@@ -59,6 +59,30 @@ if istarget "loongarch64-*-*" { + + } + ++ # loongarch*-elf target do not support -shared option ++ if check_shared_lib_support { ++ run_ld_link_tests \ ++ list \ ++ list \ ++ "data plt" \ ++ "-shared" "" \ ++ "" \ ++ {data-plt.s} \ ++ {} \ ++ "data-plt.so" \ ++ \ ++ ++ ++ if file exist "tmpdir/data-plt.so" { ++ set objdump_output run_host_cmd "objdump" "-d tmpdir/data-plt.so" ++ if { regexp "<a@plt>" $objdump_output } { ++ fail "data plt" ++ } { ++ pass "data plt" ++ } ++ } ++ } ++ + run_ld_link_tests \ + list \ + list \ +diff --git a/ld/testsuite/ld-loongarch-elf/libjirl.s b/ld/testsuite/ld-loongarch-elf/libjirl.s +index 4d963870..de028c5a 100644 +--- a/ld/testsuite/ld-loongarch-elf/libjirl.s ++++ b/ld/testsuite/ld-loongarch-elf/libjirl.s +@@ -1,2 +1,3 @@ ++.type func @function + pcalau12i $r12, %pc_hi20(func) + jirl $r1,$r12, %pc_lo12(func) +-- +2.33.0 +
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_service:tar_scm:LoongArch-Fix-loongarch-elf-target-ld-testsuite-fail.patch
Added
@@ -0,0 +1,206 @@ +From e86a0c83da7c0d80f02428d400538113f8294757 Mon Sep 17 00:00:00 2001 +From: Lulu Cai <cailulu@loongson.cn> +Date: Wed, 27 Dec 2023 17:10:41 +0800 +Subject: PATCH 038/123 LoongArch: Fix loongarch*-elf target ld testsuite + failure + +The loongarch*-elf target does not support SHARED and PIE, so this +target is skipped for some tests that require these options. +--- + .../ld-loongarch-elf/ld-loongarch-elf.exp | 30 +++--- + .../ld-loongarch-elf/local-ifunc-reloc.d | 1 + + ld/testsuite/ld-loongarch-elf/relax.exp | 99 ++++++++++--------- + 3 files changed, 71 insertions(+), 59 deletions(-) + +diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp +index 2a5709a5..8dc04fea 100644 +--- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp ++++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp +@@ -43,19 +43,21 @@ if istarget "loongarch32-*-*" { + } + + if istarget "loongarch64-*-*" { +- run_ld_link_tests \ +- list \ +- list \ +- "64_pcrel" \ +- "-e 0x0 -z relro" "" \ +- "" \ +- {64_pcrel.s} \ +- list \ +- list objdump -D 64_pcrel.d \ +- \ +- "64_pcrel" \ +- \ +- ++ if check_shared_lib_support { ++ run_ld_link_tests \ ++ list \ ++ list \ ++ "64_pcrel" \ ++ "-e 0x0 -z relro" "" \ ++ "" \ ++ {64_pcrel.s} \ ++ list \ ++ list objdump -D 64_pcrel.d \ ++ \ ++ "64_pcrel" \ ++ \ ++ ++ } + + run_ld_link_tests \ + list \ +@@ -71,10 +73,12 @@ if istarget "loongarch64-*-*" { + } + + if istarget "loongarch64-*-*" { ++ if check_shared_lib_support { + run_dump_test "desc-ie" + run_dump_test "desc-le" + run_dump_test "ie-le" + run_dump_test "tlsdesc-dso" + run_dump_test "desc-norelax" + run_dump_test "desc-relax" ++ } + } +diff --git a/ld/testsuite/ld-loongarch-elf/local-ifunc-reloc.d b/ld/testsuite/ld-loongarch-elf/local-ifunc-reloc.d +index bf73d9f2..8e1d3f0d 100644 +--- a/ld/testsuite/ld-loongarch-elf/local-ifunc-reloc.d ++++ b/ld/testsuite/ld-loongarch-elf/local-ifunc-reloc.d +@@ -1,6 +1,7 @@ + #as: + #ld: -shared -z combreloc + #objdump: -R ++#skip: loongarch*-elf + + .*: +file format .* + +diff --git a/ld/testsuite/ld-loongarch-elf/relax.exp b/ld/testsuite/ld-loongarch-elf/relax.exp +index b697d015..6c65318a 100644 +--- a/ld/testsuite/ld-loongarch-elf/relax.exp ++++ b/ld/testsuite/ld-loongarch-elf/relax.exp +@@ -150,17 +150,19 @@ if istarget loongarch64-*-* { + } + } + +- run_ld_link_tests \ +- list \ +- list \ +- "loongarch relax .so build" \ +- "-shared -e 0x0" "" \ +- "" \ +- {relax-so.s} \ +- {} \ +- "relax-so" \ +- \ +- ++ if check_shared_lib_support { ++ run_ld_link_tests \ ++ list \ ++ list \ ++ "loongarch relax .so build" \ ++ "-shared -e 0x0" "" \ ++ "" \ ++ {relax-so.s} \ ++ {} \ ++ "relax-so" \ ++ \ ++ ++ } + + if file exist "tmpdir/relax-so" { + set objdump_output run_host_cmd "objdump" "-d tmpdir/relax-so" +@@ -173,29 +175,31 @@ if istarget loongarch64-*-* { + + # If symbol in data segment, offset need to sub segment align to prevent + # overflow. +- run_ld_link_tests \ +- list \ +- list \ +- "loongarch relax segment alignment min" \ +- "-e0 -Ttext 0x120004000 -pie -z relro" "" \ +- "" \ +- {relax-segment-min.s} \ +- {} \ +- "relax-segment-min" \ +- \ +- ++ if check_pie_support { ++ run_ld_link_tests \ ++ list \ ++ list \ ++ "loongarch relax segment alignment min" \ ++ "-e0 -Ttext 0x120004000 -pie -z relro" "" \ ++ "" \ ++ {relax-segment-min.s} \ ++ {} \ ++ "relax-segment-min" \ ++ \ ++ + +- run_ld_link_tests \ +- list \ +- list \ +- "loongarch relax segment alignment max" \ +- "-e0 -Ttext 0x120004000 -pie -z relro" "" \ +- "" \ +- {relax-segment-max.s} \ +- {} \ +- "relax-segment-max" \ +- \ +- ++ run_ld_link_tests \ ++ list \ ++ list \ ++ "loongarch relax segment alignment max" \ ++ "-e0 -Ttext 0x120004000 -pie -z relro" "" \ ++ "" \ ++ {relax-segment-max.s} \ ++ {} \ ++ "relax-segment-max" \ ++ \ ++ ++ } + + if file exist "tmpdir/relax-tls-le" { + set objdump_output1 run_host_cmd "objdump" "-d tmpdir/relax-tls-le" +@@ -265,19 +269,22 @@ if istarget loongarch64-*-* { + } + + } +- run_ld_link_tests \ +- list \ +- list \ +- "loongarch relax-align" \ +- "-e 0x0 -z relro" "" \ +- "--no-warn" \ +- {relax-align.s} \ +- list \ +- list objdump -d relax-align.dd \ +- \ +- "relax-align" \ +- \ +- ++ ++ if check_shared_lib_support { ++ run_ld_link_tests \ ++ list \ ++ list \ ++ "loongarch relax-align" \ ++ "-e 0x0 -z relro" "" \ ++ "--no-warn" \ ++ {relax-align.s} \ ++ list \ ++ list objdump -d relax-align.dd \ ++ \ ++ "relax-align" \ ++ \ ++
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_service:tar_scm:LoongArch-Fix-relaxation-overflow-caused-by-ld-z-sep.patch
Added
@@ -0,0 +1,413 @@ +From a86ce43d41f2b4453d1137939f25c7b2c68215ee Mon Sep 17 00:00:00 2001 +From: mengqinggang <mengqinggang@loongson.cn> +Date: Wed, 22 May 2024 14:27:08 +0800 +Subject: PATCH 088/123 LoongArch: Fix relaxation overflow caused by ld -z + separate-code + +ld -z separate-code let .text and .rodata in two different but read only +segment. If the symbol and pc in two segment, the offset from pc to +symbol need to consider segment alignment. + +Add a function 'loongarch_two_sections_in_same_segment' to determine +whether two sections are in the same segment. +--- + bfd/elfnn-loongarch.c | 101 +++++++++++------- + .../ld-loongarch-elf/relax-medium-call-1.d | 51 ++++++--- + .../ld-loongarch-elf/relax-medium-call-1.s | 6 +- + .../ld-loongarch-elf/relax-medium-call.d | 51 ++++++--- + .../ld-loongarch-elf/relax-medium-call.s | 6 +- + .../relax-separate-code-overflow.s | 21 ++++ + ld/testsuite/ld-loongarch-elf/relax.exp | 15 +++ + 7 files changed, 176 insertions(+), 75 deletions(-) + create mode 100644 ld/testsuite/ld-loongarch-elf/relax-separate-code-overflow.s + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index 47fd08cd..eb572a77 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -3948,6 +3948,12 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, + info->callbacks->reloc_overflow + (info, h ? &h->root : NULL, name, howto->name, rel->r_addend, + input_bfd, input_section, rel->r_offset); ++ if (r_type == R_LARCH_PCREL20_S2 ++ || r_type == R_LARCH_TLS_LD_PCREL20_S2 ++ || r_type == R_LARCH_TLS_GD_PCREL20_S2 ++ || r_type == R_LARCH_TLS_DESC_PCREL20_S2) ++ _bfd_error_handler (_("recompile with 'gcc -mno-relax' or" ++ " 'as -mno-relax' or 'ld --no-relax'")); + break; + + case bfd_reloc_outofrange: +@@ -4312,6 +4318,30 @@ loongarch_relax_tls_le (bfd *abfd, asection *sec, + return true; + } + ++/* Whether two sections in the same segment. */ ++static bool ++loongarch_two_sections_in_same_segment (bfd *abfd, asection *a, asection *b) ++{ ++ struct elf_segment_map *m; ++ for (m = elf_seg_map (abfd); m != NULL; m = m->next) ++ { ++ int i; ++ int j = 0; ++ for (i = m->count - 1; i >= 0; i--) ++ { ++ if (m->sectionsi == a) ++ j++; ++ if (m->sectionsi == b) ++ j++; ++ } ++ if (1 == j) ++ return false; ++ if (2 == j) ++ return true; ++ } ++ return false; ++} ++ + /* Relax pcalau12i,addi.d => pcaddi. */ + static bool + loongarch_relax_pcala_addi (bfd *abfd, asection *sec, asection *sym_sec, +@@ -4332,23 +4362,17 @@ loongarch_relax_pcala_addi (bfd *abfd, asection *sec, asection *sym_sec, + sec->output_offset = sec->output_section->size; + bfd_vma pc = sec_addr (sec) + rel_hi->r_offset; + +- /* If pc and symbol not in the same segment, add/sub segment alignment. +- FIXME: if there are multiple readonly segments? How to determine if +- two sections are in the same segment. */ +- if (!(sym_sec->flags & SEC_READONLY)) +- { +- max_alignment = info->maxpagesize > max_alignment ? info->maxpagesize +- : max_alignment; +- if (symval > pc) +- pc -= max_alignment; +- else if (symval < pc) +- pc += max_alignment; +- } +- else +- if (symval > pc) +- pc -= max_alignment; +- else if (symval < pc) +- pc += max_alignment; ++ /* If pc and symbol not in the same segment, add/sub segment alignment. */ ++ if (!loongarch_two_sections_in_same_segment (info->output_bfd, ++ sec->output_section, ++ sym_sec->output_section)) ++ max_alignment = info->maxpagesize > max_alignment ? info->maxpagesize ++ : max_alignment; ++ ++ if (symval > pc) ++ pc -= (max_alignment > 4 ? max_alignment : 0); ++ else if (symval < pc) ++ pc += (max_alignment > 4 ? max_alignment : 0); + + const uint32_t addi_d = 0x02c00000; + const uint32_t pcaddi = 0x18000000; +@@ -4387,7 +4411,7 @@ loongarch_relax_pcala_addi (bfd *abfd, asection *sec, asection *sym_sec, + /* call36 f -> bl f + tail36 $t0, f -> b f. */ + static bool +-loongarch_relax_call36 (bfd *abfd, asection *sec, ++loongarch_relax_call36 (bfd *abfd, asection *sec, asection *sym_sec, + Elf_Internal_Rela *rel, bfd_vma symval, + struct bfd_link_info *info, bool *again, + bfd_vma max_alignment) +@@ -4403,9 +4427,13 @@ loongarch_relax_call36 (bfd *abfd, asection *sec, + sec->output_offset = sec->output_section->size; + bfd_vma pc = sec_addr (sec) + rel->r_offset; + +- /* If pc and symbol not in the same segment, add/sub segment alignment. +- FIXME: if there are multiple readonly segments? How to determine if +- two sections are in the same segment. */ ++ /* If pc and symbol not in the same segment, add/sub segment alignment. */ ++ if (!loongarch_two_sections_in_same_segment (info->output_bfd, ++ sec->output_section, ++ sym_sec->output_section)) ++ max_alignment = info->maxpagesize > max_alignment ? info->maxpagesize ++ : max_alignment; ++ + if (symval > pc) + pc -= (max_alignment > 4 ? max_alignment : 0); + else if (symval < pc) +@@ -4559,22 +4587,17 @@ loongarch_relax_tls_ld_gd_desc (bfd *abfd, asection *sec, asection *sym_sec, + sec->output_offset = sec->output_section->size; + bfd_vma pc = sec_addr (sec) + rel_hi->r_offset; + +- /* If pc and symbol not in the same segment, add/sub segment alignment. +- FIXME: if there are multiple readonly segments? */ +- if (!(sym_sec->flags & SEC_READONLY)) +- { +- max_alignment = info->maxpagesize > max_alignment ? info->maxpagesize +- : max_alignment; +- if (symval > pc) +- pc -= max_alignment; +- else if (symval < pc) +- pc += max_alignment; +- } +- else +- if (symval > pc) +- pc -= max_alignment; +- else if (symval < pc) +- pc += max_alignment; ++ /* If pc and symbol not in the same segment, add/sub segment alignment. */ ++ if (!loongarch_two_sections_in_same_segment (info->output_bfd, ++ sec->output_section, ++ sym_sec->output_section)) ++ max_alignment = info->maxpagesize > max_alignment ? info->maxpagesize ++ : max_alignment; ++ ++ if (symval > pc) ++ pc -= (max_alignment > 4 ? max_alignment : 0); ++ else if (symval < pc) ++ pc += (max_alignment > 4 ? max_alignment : 0); + + const uint32_t addi_d = 0x02c00000; + const uint32_t pcaddi = 0x18000000; +@@ -4858,8 +4881,8 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, + break; + case R_LARCH_CALL36: + if (0 == info->relax_pass && (i + 2) <= sec->reloc_count) +- loongarch_relax_call36 (abfd, sec, rel, symval, info, again, +- max_alignment); ++ loongarch_relax_call36 (abfd, sec, sym_sec, rel, symval, ++ info, again, max_alignment); + break; + + case R_LARCH_TLS_LE_HI20_R: +diff --git a/ld/testsuite/ld-loongarch-elf/relax-medium-call-1.d b/ld/testsuite/ld-loongarch-elf/relax-medium-call-1.d +index c8ee9333..96e7bb09 100644 +--- a/ld/testsuite/ld-loongarch-elf/relax-medium-call-1.d ++++ b/ld/testsuite/ld-loongarch-elf/relax-medium-call-1.d +@@ -1,21 +1,42 @@ +-#ld: -e0 -Ttext=0x120000000 --section-start=ta=0x118000000 --section-start=tb=0x127fffffc +-#objdump: -d -j .text ++#ld: -e0 ++#objdump: -d + + .*: +file format .* + + + Disassembly of section .text: + +- *0000000120000000 <__bss_start-0x4030>: +- +120000000: +54000200 +bl +-134217728 +# 118000000 <a> +- +120000004: +1fffc001 +pcaddu18i +\$ra, -512 +- +120000008: +4ffffc21 +jirl +\$ra, \$ra, -4 +- +12000000c: +50000200 +b +-134217728 +# 11800000c <b> +- +120000010: +1fffc00c +pcaddu18i +\$t0, -512 +- +120000014: +4ffffd80 +jirl +\$zero, \$t0, -4
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_service:tar_scm:LoongArch-Fix-relaxation-overflow-caused-by-section-.patch
Added
@@ -0,0 +1,273 @@ +From 9c12754717e9564ba5caa8220a87fa759f6e3f33 Mon Sep 17 00:00:00 2001 +From: mengqinggang <mengqinggang@loongson.cn> +Date: Wed, 27 Dec 2023 11:12:30 +0800 +Subject: PATCH 043/123 LoongArch: Fix relaxation overflow caused by section + alignment + +When deleting NOP instructions addend by .align at second pass, this may cause +the PC decrease but the symbol address to remain unchanged due to section +alignment. + +To solve this question, we subtract a maximux alignment of all sections like +RISC-V. +--- + bfd/elfnn-loongarch.c | 79 +++++++++++++------ + .../relax-section-align-overflow.s | 25 ++++++ + ld/testsuite/ld-loongarch-elf/relax.exp | 25 ++++-- + 3 files changed, 100 insertions(+), 29 deletions(-) + create mode 100644 ld/testsuite/ld-loongarch-elf/relax-section-align-overflow.s + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index 3d858169..8b71e836 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -4188,8 +4188,9 @@ loongarch_relax_tls_le (bfd *abfd, asection *sec, + /* Relax pcalau12i,addi.d => pcaddi. */ + static bool + loongarch_relax_pcala_addi (bfd *abfd, asection *sec, asection *sym_sec, +- Elf_Internal_Rela *rel_hi, bfd_vma symval, +- struct bfd_link_info *info, bool *again) ++ Elf_Internal_Rela *rel_hi, bfd_vma symval, ++ struct bfd_link_info *info, bool *again, ++ bfd_vma max_alignment) + { + bfd_byte *contents = elf_section_data (sec)->this_hdr.contents; + Elf_Internal_Rela *rel_lo = rel_hi + 2; +@@ -4205,14 +4206,22 @@ loongarch_relax_pcala_addi (bfd *abfd, asection *sec, asection *sym_sec, + bfd_vma pc = sec_addr (sec) + rel_hi->r_offset; + + /* If pc and symbol not in the same segment, add/sub segment alignment. +- FIXME: if there are multiple readonly segments? */ ++ FIXME: if there are multiple readonly segments? How to determine if ++ two sections are in the same segment. */ + if (!(sym_sec->flags & SEC_READONLY)) + { ++ max_alignment = info->maxpagesize > max_alignment ? info->maxpagesize ++ : max_alignment; + if (symval > pc) +- pc -= info->maxpagesize; ++ pc -= max_alignment; + else if (symval < pc) +- pc += info->maxpagesize; ++ pc += max_alignment; + } ++ else ++ if (symval > pc) ++ pc -= max_alignment; ++ else if (symval < pc) ++ pc += max_alignment; + + const uint32_t addi_d = 0x02c00000; + const uint32_t pcaddi = 0x18000000; +@@ -4352,8 +4361,9 @@ loongarch_relax_align (bfd *abfd, asection *sec, + /* Relax pcalau12i + addi.d of TLS LD/GD/DESC to pcaddi. */ + static bool + loongarch_relax_tls_ld_gd_desc (bfd *abfd, asection *sec, asection *sym_sec, +- Elf_Internal_Rela *rel_hi, bfd_vma symval, +- struct bfd_link_info *info, bool *again) ++ Elf_Internal_Rela *rel_hi, bfd_vma symval, ++ struct bfd_link_info *info, bool *again, ++ bfd_vma max_alignment) + { + bfd_byte *contents = elf_section_data (sec)->this_hdr.contents; + Elf_Internal_Rela *rel_lo = rel_hi + 2; +@@ -4372,11 +4382,18 @@ loongarch_relax_tls_ld_gd_desc (bfd *abfd, asection *sec, asection *sym_sec, + FIXME: if there are multiple readonly segments? */ + if (!(sym_sec->flags & SEC_READONLY)) + { ++ max_alignment = info->maxpagesize > max_alignment ? info->maxpagesize ++ : max_alignment; + if (symval > pc) +- pc -= info->maxpagesize; ++ pc -= max_alignment; + else if (symval < pc) +- pc += info->maxpagesize; ++ pc += max_alignment; + } ++ else ++ if (symval > pc) ++ pc -= max_alignment; ++ else if (symval < pc) ++ pc += max_alignment; + + const uint32_t addi_d = 0x02c00000; + const uint32_t pcaddi = 0x18000000; +@@ -4428,6 +4445,21 @@ loongarch_relax_tls_ld_gd_desc (bfd *abfd, asection *sec, asection *sym_sec, + return true; + } + ++/* Traverse all output sections and return the max alignment. */ ++ ++static bfd_vma ++loongarch_get_max_alignment (asection *sec) ++{ ++ asection *o; ++ unsigned int max_alignment_power = 0; ++ ++ for (o = sec->output_section->owner->sections; o != NULL; o = o->next) ++ if (o->alignment_power > max_alignment_power) ++ max_alignment_power = o->alignment_power; ++ ++ return (bfd_vma) 1 << max_alignment_power; ++} ++ + static bool + loongarch_elf_relax_section (bfd *abfd, asection *sec, + struct bfd_link_info *info, +@@ -4438,6 +4470,7 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, + Elf_Internal_Shdr *symtab_hdr = &elf_symtab_hdr (abfd); + Elf_Internal_Rela *relocs; + *again = false; ++ bfd_vma max_alignment = 0; + + if (bfd_link_relocatable (info) + || sec->sec_flg0 +@@ -4470,6 +4503,15 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, + + data->relocs = relocs; + ++ /* Estimate the maximum alignment for all output sections once time ++ should be enough. */ ++ max_alignment = htab->max_alignment; ++ if (max_alignment == (bfd_vma) -1) ++ { ++ max_alignment = loongarch_get_max_alignment (sec); ++ htab->max_alignment = max_alignment; ++ } ++ + for (unsigned int i = 0; i < sec->reloc_count; i++) + { + char symtype; +@@ -4606,6 +4648,7 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, + if (1 == info->relax_pass) + loongarch_relax_align (abfd, sec, sym_sec, info, rel, symval); + break; ++ + case R_LARCH_DELETE: + if (1 == info->relax_pass) + { +@@ -4613,6 +4656,7 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, + rel->r_info = ELFNN_R_INFO (0, R_LARCH_NONE); + } + break; ++ + case R_LARCH_TLS_LE_HI20_R: + case R_LARCH_TLS_LE_LO12_R: + case R_LARCH_TLS_LE_ADD_R: +@@ -4623,34 +4667,25 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, + case R_LARCH_PCALA_HI20: + if (0 == info->relax_pass && (i + 4) <= sec->reloc_count) + loongarch_relax_pcala_addi (abfd, sec, sym_sec, rel, symval, +- info, again); ++ info, again, max_alignment); + break; ++ + case R_LARCH_GOT_PC_HI20: + if (local_got && 0 == info->relax_pass + && (i + 4) <= sec->reloc_count) + { + if (loongarch_relax_pcala_ld (abfd, sec, rel)) + loongarch_relax_pcala_addi (abfd, sec, sym_sec, rel, symval, +- info, again); ++ info, again, max_alignment); + } + break; + + case R_LARCH_TLS_LD_PC_HI20: +- if (0 == info->relax_pass && (i + 4) <= sec->reloc_count) +- loongarch_relax_tls_ld_gd_desc (abfd, sec, sym_sec, rel, symval, +- info, again); +- break; +- + case R_LARCH_TLS_GD_PC_HI20: +- if (0 == info->relax_pass && (i + 4) <= sec->reloc_count) +- loongarch_relax_tls_ld_gd_desc (abfd, sec, sym_sec, rel, symval, +- info, again); +- break; +- + case R_LARCH_TLS_DESC_PC_HI20: + if (0 == info->relax_pass && (i + 4) <= sec->reloc_count) + loongarch_relax_tls_ld_gd_desc (abfd, sec, sym_sec, rel, symval, +- info, again); ++ info, again, max_alignment); + break; + + default: +diff --git a/ld/testsuite/ld-loongarch-elf/relax-section-align-overflow.s b/ld/testsuite/ld-loongarch-elf/relax-section-align-overflow.s +new file mode 100644 +index 00000000..c341a8bb +--- /dev/null
View file
_service:tar_scm:LoongArch-Fix-some-macro-that-cannot-be-expanded-pro.patch
Added
@@ -0,0 +1,390 @@ +From 6ddd9c5a47335388ce3031313325b259a9f28773 Mon Sep 17 00:00:00 2001 +From: Lulu Cai <cailulu@loongson.cn> +Date: Wed, 27 Dec 2023 19:42:01 +0800 +Subject: PATCH 037/123 LoongArch: Fix some macro that cannot be expanded + properly + +Suppose we want to use la.got to generate 32 pcrel and +32 abs instruction sequences respectively. According to +the existing conditions, to generate 32 pcrel sequences +use -mabi=ilp32*, and to generate 32 abs use -mabi=ilp32* +and -mla-global-with-abs. + +Due to the fact that the conditions for generating 32 abs +also satisfy 32 pcrel, using -mabi=ilp32* and -mla-global-with-abs +will result in only generating instruction sequences of 32 pcrel. + +By modifying the conditions for macro expansion and adjusting +the matching order of macro instructions, it is ensured that +the correct sequence of instructions can be generated. +--- + .../gas/loongarch/macro_op_extreme_abs.d | 72 +++++++++++++++ + .../gas/loongarch/macro_op_extreme_abs.s | 9 ++ + ...o_op_large_abs.d => macro_op_extreme_pc.d} | 13 ++- + .../gas/loongarch/macro_op_extreme_pc.s | 9 ++ + .../gas/loongarch/macro_op_large_abs.s | 9 -- + .../gas/loongarch/macro_op_large_pc.d | 89 ------------------- + .../gas/loongarch/macro_op_large_pc.s | 9 -- + opcodes/loongarch-opc.c | 24 ++--- + 8 files changed, 108 insertions(+), 126 deletions(-) + create mode 100644 gas/testsuite/gas/loongarch/macro_op_extreme_abs.d + create mode 100644 gas/testsuite/gas/loongarch/macro_op_extreme_abs.s + rename gas/testsuite/gas/loongarch/{macro_op_large_abs.d => macro_op_extreme_pc.d} (93%) + create mode 100644 gas/testsuite/gas/loongarch/macro_op_extreme_pc.s + delete mode 100644 gas/testsuite/gas/loongarch/macro_op_large_abs.s + delete mode 100644 gas/testsuite/gas/loongarch/macro_op_large_pc.d + delete mode 100644 gas/testsuite/gas/loongarch/macro_op_large_pc.s + +diff --git a/gas/testsuite/gas/loongarch/macro_op_extreme_abs.d b/gas/testsuite/gas/loongarch/macro_op_extreme_abs.d +new file mode 100644 +index 00000000..5c823ba0 +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/macro_op_extreme_abs.d +@@ -0,0 +1,72 @@ ++#as: -mla-global-with-abs -mla-local-with-abs ++#objdump: -dr ++#skip: loongarch32-*-* ++ ++.*: file format .* ++ ++ ++Disassembly of section .text: ++ ++0+ <.L1>: ++ 0: 14000004 lu12i.w \$a0, 0 ++ 0: R_LARCH_MARK_LA \*ABS\* ++ 0: R_LARCH_ABS_HI20 .L1 ++ 4: 03800084 ori \$a0, \$a0, 0x0 ++ 4: R_LARCH_ABS_LO12 .L1 ++ 8: 16000004 lu32i.d \$a0, 0 ++ 8: R_LARCH_ABS64_LO20 .L1 ++ c: 03000084 lu52i.d \$a0, \$a0, 0 ++ c: R_LARCH_ABS64_HI12 .L1 ++ 10: 14000004 lu12i.w \$a0, 0 ++ 10: R_LARCH_MARK_LA \*ABS\* ++ 10: R_LARCH_ABS_HI20 .L1 ++ 14: 03800084 ori \$a0, \$a0, 0x0 ++ 14: R_LARCH_ABS_LO12 .L1 ++ 18: 16000004 lu32i.d \$a0, 0 ++ 18: R_LARCH_ABS64_LO20 .L1 ++ 1c: 03000084 lu52i.d \$a0, \$a0, 0 ++ 1c: R_LARCH_ABS64_HI12 .L1 ++ 20: 1a000004 pcalau12i \$a0, 0 ++ 20: R_LARCH_PCALA_HI20 .L1 ++ 20: R_LARCH_RELAX \*ABS\* ++ 24: 02c00084 addi.d \$a0, \$a0, 0 ++ 24: R_LARCH_PCALA_LO12 .L1 ++ 24: R_LARCH_RELAX \*ABS\* ++ 28: 14000004 lu12i.w \$a0, 0 ++ 28: R_LARCH_GOT_HI20 .L1 ++ 2c: 03800084 ori \$a0, \$a0, 0x0 ++ 2c: R_LARCH_GOT_LO12 .L1 ++ 30: 16000004 lu32i.d \$a0, 0 ++ 30: R_LARCH_GOT64_LO20 .L1 ++ 34: 03000084 lu52i.d \$a0, \$a0, 0 ++ 34: R_LARCH_GOT64_HI12 .L1 ++ 38: 28c00084 ld.d \$a0, \$a0, 0 ++ 3c: 14000004 lu12i.w \$a0, 0 ++ 3c: R_LARCH_TLS_LE_HI20 TLS1 ++ 40: 03800084 ori \$a0, \$a0, 0x0 ++ 40: R_LARCH_TLS_LE_LO12 TLS1 ++ 44: 14000004 lu12i.w \$a0, 0 ++ 44: R_LARCH_TLS_IE_HI20 TLS1 ++ 48: 03800084 ori \$a0, \$a0, 0x0 ++ 48: R_LARCH_TLS_IE_LO12 TLS1 ++ 4c: 16000004 lu32i.d \$a0, 0 ++ 4c: R_LARCH_TLS_IE64_LO20 TLS1 ++ 50: 03000084 lu52i.d \$a0, \$a0, 0 ++ 50: R_LARCH_TLS_IE64_HI12 TLS1 ++ 54: 28c00084 ld.d \$a0, \$a0, 0 ++ 58: 14000004 lu12i.w \$a0, 0 ++ 58: R_LARCH_TLS_LD_HI20 TLS1 ++ 5c: 03800084 ori \$a0, \$a0, 0x0 ++ 5c: R_LARCH_GOT_LO12 TLS1 ++ 60: 16000004 lu32i.d \$a0, 0 ++ 60: R_LARCH_GOT64_LO20 TLS1 ++ 64: 03000084 lu52i.d \$a0, \$a0, 0 ++ 64: R_LARCH_GOT64_HI12 TLS1 ++ 68: 14000004 lu12i.w \$a0, 0 ++ 68: R_LARCH_TLS_GD_HI20 TLS1 ++ 6c: 03800084 ori \$a0, \$a0, 0x0 ++ 6c: R_LARCH_GOT_LO12 TLS1 ++ 70: 16000004 lu32i.d \$a0, 0 ++ 70: R_LARCH_GOT64_LO20 TLS1 ++ 74: 03000084 lu52i.d \$a0, \$a0, 0 ++ 74: R_LARCH_GOT64_HI12 TLS1 +diff --git a/gas/testsuite/gas/loongarch/macro_op_extreme_abs.s b/gas/testsuite/gas/loongarch/macro_op_extreme_abs.s +new file mode 100644 +index 00000000..eca07006 +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/macro_op_extreme_abs.s +@@ -0,0 +1,9 @@ ++.L1: ++la.local $r4, $r5, .L1 ++la.global $r4, $r5, .L1 ++la.pcrel $r4, .L1 ++la.got $r4,.L1 ++la.tls.le $r4, TLS1 ++la.tls.ie $r4, TLS1 ++la.tls.ld $r4, TLS1 ++la.tls.gd $r4, TLS1 +diff --git a/gas/testsuite/gas/loongarch/macro_op_large_abs.d b/gas/testsuite/gas/loongarch/macro_op_extreme_pc.d +similarity index 93% +rename from gas/testsuite/gas/loongarch/macro_op_large_abs.d +rename to gas/testsuite/gas/loongarch/macro_op_extreme_pc.d +index 729e878f..8e4b6e6c 100644 +--- a/gas/testsuite/gas/loongarch/macro_op_large_abs.d ++++ b/gas/testsuite/gas/loongarch/macro_op_extreme_pc.d +@@ -1,10 +1,9 @@ +-#as: ++#as: -mla-global-with-pcrel + #objdump: -dr + #skip: loongarch32-*-* + + .*: file format .* + +- + Disassembly of section .text: + + 0+ <.L1>: +@@ -20,16 +19,16 @@ Disassembly of section .text: + c: R_LARCH_PCALA64_HI12 .L1 + 10: 00109484 add.d \$a0, \$a0, \$a1 + 14: 1a000004 pcalau12i \$a0, 0 +- 14: R_LARCH_GOT_PC_HI20 .L1 ++ 14: R_LARCH_PCALA_HI20 .L1 + 14: R_LARCH_RELAX \*ABS\* + 18: 02c00005 li.d \$a1, 0 +- 18: R_LARCH_GOT_PC_LO12 .L1 ++ 18: R_LARCH_PCALA_LO12 .L1 + 18: R_LARCH_RELAX \*ABS\* + 1c: 16000005 lu32i.d \$a1, 0 +- 1c: R_LARCH_GOT64_PC_LO20 .L1 ++ 1c: R_LARCH_PCALA64_LO20 .L1 + 20: 030000a5 lu52i.d \$a1, \$a1, 0 +- 20: R_LARCH_GOT64_PC_HI12 .L1 +- 24: 380c1484 ldx.d \$a0, \$a0, \$a1 ++ 20: R_LARCH_PCALA64_HI12 .L1 ++ 24: 00109484 add.d \$a0, \$a0, \$a1 + 28: 1a000004 pcalau12i \$a0, 0 + 28: R_LARCH_PCALA_HI20 .L1 + 28: R_LARCH_RELAX \*ABS\* +diff --git a/gas/testsuite/gas/loongarch/macro_op_extreme_pc.s b/gas/testsuite/gas/loongarch/macro_op_extreme_pc.s +new file mode 100644 +index 00000000..4c685b5b +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/macro_op_extreme_pc.s +@@ -0,0 +1,9 @@ ++.L1: ++la.local $r4, $r5, .L1 ++la.global $r4, $r5, .L1 ++la.pcrel $r4, $r5, .L1 ++la.got $r4, $r5, .L1 ++la.tls.le $r4, TLS1 ++la.tls.ie $r4, $r5, TLS1 ++la.tls.ld $r4, $r5, TLS1 ++la.tls.gd $r4, $r5, TLS1 +diff --git a/gas/testsuite/gas/loongarch/macro_op_large_abs.s b/gas/testsuite/gas/loongarch/macro_op_large_abs.s +deleted file mode 100644 +index fd76391d..00000000 +--- a/gas/testsuite/gas/loongarch/macro_op_large_abs.s ++++ /dev/null +@@ -1,9 +0,0 @@ +-.L1: +-la.local $r4, $r5, .L1 +-la.global $r4, $r5, .L1 +-la.pcrel $r4, $r5, .L1 +-la.got $r4, $r5, .L1 +-la.tls.le $r4, TLS1 +-la.tls.ie $r4, $r5, TLS1
View file
_service:tar_scm:LoongArch-Fix-some-test-cases-for-TLS-transition-and.patch
Added
@@ -0,0 +1,997 @@ +From 67ca2a7a3bd324aaef2d033de24384e64778d0d9 Mon Sep 17 00:00:00 2001 +From: Lulu Cai <cailulu@loongson.cn> +Date: Thu, 25 Jan 2024 19:20:00 +0800 +Subject: PATCH 071/123 LoongArch: Fix some test cases for TLS transition and + relax + +--- + gas/testsuite/gas/loongarch/macro_op.d | 4 + + gas/testsuite/gas/loongarch/macro_op_32.d | 4 + + .../gas/loongarch/macro_op_extreme_abs.d | 4 +- + .../gas/loongarch/macro_op_extreme_pc.d | 2 + + .../relax-cfi-fde-DW_CFA_advance_loc.d | 16 ++-- + .../relax-cfi-fde-DW_CFA_advance_loc.s | 8 ++ + gas/testsuite/gas/loongarch/reloc.d | 8 ++ + gas/testsuite/gas/loongarch/tlsdesc_32.d | 27 ------ + gas/testsuite/gas/loongarch/tlsdesc_32.s | 12 --- + gas/testsuite/gas/loongarch/tlsdesc_64.d | 2 + + ld/testsuite/ld-loongarch-elf/desc-ie.d | 14 ++- + ld/testsuite/ld-loongarch-elf/desc-ie.s | 13 +-- + .../ld-loongarch-elf/desc-le-norelax.d | 15 ++++ + .../ld-loongarch-elf/desc-le-norelax.s | 11 +++ + ld/testsuite/ld-loongarch-elf/desc-le-relax.d | 13 +++ + ld/testsuite/ld-loongarch-elf/desc-le-relax.s | 14 +++ + ld/testsuite/ld-loongarch-elf/desc-le.d | 15 ---- + ld/testsuite/ld-loongarch-elf/desc-le.s | 14 --- + ld/testsuite/ld-loongarch-elf/ie-le-norelax.d | 13 +++ + .../{ie-le.s => ie-le-norelax.s} | 4 +- + ld/testsuite/ld-loongarch-elf/ie-le-relax.d | 13 +++ + ld/testsuite/ld-loongarch-elf/ie-le-relax.s | 13 +++ + ld/testsuite/ld-loongarch-elf/ie-le.d | 13 --- + .../ld-loongarch-elf/ld-loongarch-elf.exp | 11 ++- + ld/testsuite/ld-loongarch-elf/macro_op.d | 4 + + ld/testsuite/ld-loongarch-elf/relax.exp | 6 +- + .../ld-loongarch-elf/tls-le-norelax.d | 18 ++++ + .../{tls-le.s => tls-le-norelax.s} | 4 + + ld/testsuite/ld-loongarch-elf/tls-le-relax.d | 13 +++ + ld/testsuite/ld-loongarch-elf/tls-le-relax.s | 22 +++++ + ld/testsuite/ld-loongarch-elf/tls-le.d | 14 --- + ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d | 86 ++++++++++--------- + ld/testsuite/ld-loongarch-elf/tlsdesc-dso.s | 9 ++ + ld/testsuite/ld-loongarch-elf/tlsdesc_abs.d | 23 +++++ + ld/testsuite/ld-loongarch-elf/tlsdesc_abs.s | 7 ++ + .../ld-loongarch-elf/tlsdesc_extreme.d | 25 ++++++ + .../ld-loongarch-elf/tlsdesc_extreme.s | 7 ++ + 37 files changed, 333 insertions(+), 168 deletions(-) + delete mode 100644 gas/testsuite/gas/loongarch/tlsdesc_32.d + delete mode 100644 gas/testsuite/gas/loongarch/tlsdesc_32.s + create mode 100644 ld/testsuite/ld-loongarch-elf/desc-le-norelax.d + create mode 100644 ld/testsuite/ld-loongarch-elf/desc-le-norelax.s + create mode 100644 ld/testsuite/ld-loongarch-elf/desc-le-relax.d + create mode 100644 ld/testsuite/ld-loongarch-elf/desc-le-relax.s + delete mode 100644 ld/testsuite/ld-loongarch-elf/desc-le.d + delete mode 100644 ld/testsuite/ld-loongarch-elf/desc-le.s + create mode 100644 ld/testsuite/ld-loongarch-elf/ie-le-norelax.d + rename ld/testsuite/ld-loongarch-elf/{ie-le.s => ie-le-norelax.s} (63%) + create mode 100644 ld/testsuite/ld-loongarch-elf/ie-le-relax.d + create mode 100644 ld/testsuite/ld-loongarch-elf/ie-le-relax.s + delete mode 100644 ld/testsuite/ld-loongarch-elf/ie-le.d + create mode 100644 ld/testsuite/ld-loongarch-elf/tls-le-norelax.d + rename ld/testsuite/ld-loongarch-elf/{tls-le.s => tls-le-norelax.s} (70%) + create mode 100644 ld/testsuite/ld-loongarch-elf/tls-le-relax.d + create mode 100644 ld/testsuite/ld-loongarch-elf/tls-le-relax.s + delete mode 100644 ld/testsuite/ld-loongarch-elf/tls-le.d + create mode 100644 ld/testsuite/ld-loongarch-elf/tlsdesc_abs.d + create mode 100644 ld/testsuite/ld-loongarch-elf/tlsdesc_abs.s + create mode 100644 ld/testsuite/ld-loongarch-elf/tlsdesc_extreme.d + create mode 100644 ld/testsuite/ld-loongarch-elf/tlsdesc_extreme.s + +diff --git a/gas/testsuite/gas/loongarch/macro_op.d b/gas/testsuite/gas/loongarch/macro_op.d +index 47f8f45c..106f619e 100644 +--- a/gas/testsuite/gas/loongarch/macro_op.d ++++ b/gas/testsuite/gas/loongarch/macro_op.d +@@ -53,12 +53,16 @@ Disassembly of section .text: + 44: R_LARCH_RELAX \*ABS\* + 48: 14000004 lu12i.w \$a0, 0 + 48: R_LARCH_TLS_LE_HI20 TLS1 ++ 48: R_LARCH_RELAX \*ABS\* + 4c: 03800084 ori \$a0, \$a0, 0x0 + 4c: R_LARCH_TLS_LE_LO12 TLS1 ++ 4c: R_LARCH_RELAX \*ABS\* + 50: 1a000004 pcalau12i \$a0, 0 + 50: R_LARCH_TLS_IE_PC_HI20 TLS1 ++ 50: R_LARCH_RELAX \*ABS\* + 54: 28c00084 ld.d \$a0, \$a0, 0 + 54: R_LARCH_TLS_IE_PC_LO12 TLS1 ++ 54: R_LARCH_RELAX \*ABS\* + 58: 1a000004 pcalau12i \$a0, 0 + 58: R_LARCH_TLS_LD_PC_HI20 TLS1 + 58: R_LARCH_RELAX \*ABS\* +diff --git a/gas/testsuite/gas/loongarch/macro_op_32.d b/gas/testsuite/gas/loongarch/macro_op_32.d +index a7349aa8..8fd69922 100644 +--- a/gas/testsuite/gas/loongarch/macro_op_32.d ++++ b/gas/testsuite/gas/loongarch/macro_op_32.d +@@ -49,12 +49,16 @@ Disassembly of section .text: + 3c: R_LARCH_RELAX \*ABS\* + 40: 14000004 lu12i.w \$a0, 0 + 40: R_LARCH_TLS_LE_HI20 TLS1 ++ 40: R_LARCH_RELAX \*ABS\* + 44: 03800084 ori \$a0, \$a0, 0x0 + 44: R_LARCH_TLS_LE_LO12 TLS1 ++ 44: R_LARCH_RELAX \*ABS\* + 48: 1a000004 pcalau12i \$a0, 0 + 48: R_LARCH_TLS_IE_PC_HI20 TLS1 ++ 48: R_LARCH_RELAX \*ABS\* + 4c: 28800084 ld.w \$a0, \$a0, 0 + 4c: R_LARCH_TLS_IE_PC_LO12 TLS1 ++ 4c: R_LARCH_RELAX \*ABS\* + 50: 1a000004 pcalau12i \$a0, 0 + 50: R_LARCH_TLS_LD_PC_HI20 TLS1 + 50: R_LARCH_RELAX \*ABS\* +diff --git a/gas/testsuite/gas/loongarch/macro_op_extreme_abs.d b/gas/testsuite/gas/loongarch/macro_op_extreme_abs.d +index 5c823ba0..8e3a2aa9 100644 +--- a/gas/testsuite/gas/loongarch/macro_op_extreme_abs.d ++++ b/gas/testsuite/gas/loongarch/macro_op_extreme_abs.d +@@ -28,10 +28,8 @@ Disassembly of section .text: + 1c: R_LARCH_ABS64_HI12 .L1 + 20: 1a000004 pcalau12i \$a0, 0 + 20: R_LARCH_PCALA_HI20 .L1 +- 20: R_LARCH_RELAX \*ABS\* + 24: 02c00084 addi.d \$a0, \$a0, 0 + 24: R_LARCH_PCALA_LO12 .L1 +- 24: R_LARCH_RELAX \*ABS\* + 28: 14000004 lu12i.w \$a0, 0 + 28: R_LARCH_GOT_HI20 .L1 + 2c: 03800084 ori \$a0, \$a0, 0x0 +@@ -43,8 +41,10 @@ Disassembly of section .text: + 38: 28c00084 ld.d \$a0, \$a0, 0 + 3c: 14000004 lu12i.w \$a0, 0 + 3c: R_LARCH_TLS_LE_HI20 TLS1 ++ 3c: R_LARCH_RELAX \*ABS\* + 40: 03800084 ori \$a0, \$a0, 0x0 + 40: R_LARCH_TLS_LE_LO12 TLS1 ++ 40: R_LARCH_RELAX \*ABS\* + 44: 14000004 lu12i.w \$a0, 0 + 44: R_LARCH_TLS_IE_HI20 TLS1 + 48: 03800084 ori \$a0, \$a0, 0x0 +diff --git a/gas/testsuite/gas/loongarch/macro_op_extreme_pc.d b/gas/testsuite/gas/loongarch/macro_op_extreme_pc.d +index 68fbb338..21c5e5a0 100644 +--- a/gas/testsuite/gas/loongarch/macro_op_extreme_pc.d ++++ b/gas/testsuite/gas/loongarch/macro_op_extreme_pc.d +@@ -46,8 +46,10 @@ Disassembly of section .text: + +4c: +380c1484 +ldx.d +\$a0, \$a0, \$a1 + +50: +14000004 +lu12i.w +\$a0, 0 + +50: R_LARCH_TLS_LE_HI20 +TLS1 ++ +50: R_LARCH_RELAX +\*ABS\* + +54: +03800084 +ori +\$a0, \$a0, 0x0 + +54: R_LARCH_TLS_LE_LO12 +TLS1 ++ +54: R_LARCH_RELAX +\*ABS\* + +58: +1a000004 +pcalau12i +\$a0, 0 + +58: R_LARCH_TLS_IE_PC_HI20 +TLS1 + +5c: +02c00005 +li.d +\$a1, 0 +diff --git a/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.d b/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.d +index 367039e1..6b164cfb 100644 +--- a/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.d ++++ b/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.d +@@ -14,7 +14,7 @@ Disassembly of section .eh_frame: + +c: +01017c01 +fadd.d +\$fa1, \$fa0, \$fs7 + +10: +0c030d1b +.word + +0x0c030d1b + +14: +00000016 +.word + +0x00000016 +- +18: +00000034 +.word + +0x00000034 ++ +18: +0000003c +.word + +0x0000003c + +1c: +0000001c +.word + +0x0000001c + +... + +20: R_LARCH_32_PCREL +L0\^A +@@ -26,7 +26,7 @@ Disassembly of section .eh_frame: + +2c: +d6400016 +.word + +0xd6400016 + +2e: R_LARCH_ADD6 +L0\^A + +2e: R_LARCH_SUB6 +L0\^A +- +30: +4000160c +beqz +\$t4, 3145748 +# 300044 <L0\^A\+0x30000c> ++ +30: +4000160c +beqz +\$t4, 3145748 +# 300044 <L0\^A\+0x2ffffc> + +33: R_LARCH_ADD6 +L0\^A + +33: R_LARCH_SUB6 +L0\^A + +34: +00160cd6 +orn +\$fp, \$a2, \$sp +@@ -39,8 +39,14 @@ Disassembly of section .eh_frame: + +40: +d6400016 +.word + +0xd6400016 + +42: R_LARCH_ADD6 +L0\^A + +42: R_LARCH_SUB6 +L0\^A +- +44: +4000160c +beqz +\$t4, 3145748 +# 300058 <L0\^A\+0x300020> ++ +44: +4000160c +beqz +\$t4, 3145748 +# 300058 <L0\^A\+0x300010> + +47: R_LARCH_ADD6 +L0\^A + +47: R_LARCH_SUB6 +L0\^A +- +48: +000000d6 +.word + +0x000000d6 +- +4c: +00000000 +.word + +0x00000000 ++ +48: +00160cd6 +orn +\$fp, \$a2, \$sp ++ +4c: +160cd640 +lu32i.d +\$zero, 26290 ++ +4c: R_LARCH_ADD6 +L0\^A ++ +4c: R_LARCH_SUB6 +L0\^A ++ +50: +00d64000 +bstrpick.d +\$zero, \$zero, 0x16, 0x10 ++ +51: R_LARCH_ADD6 +L0\^A ++ +51: R_LARCH_SUB6 +L0\^A ++ +54: +00000000 +.word + +0x00000000 +diff --git a/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.s b/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.s +index 6e4c9b8b..2c67587b 100644 +--- a/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.s ++++ b/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.s +@@ -30,4 +30,12 @@ pcalau12i $t0, %le_hi20_r(a) + add.d $t0, $tp, $t0, %le_add_r(a) + .cfi_restore 22 +
View file
_service:tar_scm:LoongArch-Fix-some-test-failures-about-TLS-desc-and-.patch
Added
@@ -0,0 +1,146 @@ +From ced17161d4aac5b19c9aca8e6183607a83fc1774 Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao <xry111@xry111.site> +Date: Sat, 20 Jan 2024 00:38:24 +0800 +Subject: PATCH 048/123 LoongArch: Fix some test failures about TLS desc and + TLS relaxation + +There are two issues causing 11 test failures: + +1. The TLS desc tests are matching the entire disassemble of a linked + executable. But if ld is configured --enable-default-hash-style=gnu + (note that most modern distros use this option), the layout of the + linked executables will be different and the immediate operands in + the linked executables will also be different. So we add + "--hash-style=both" for these tests to cancel the effect of + --enable-default-hash-style=gnu, like x86_64 mark-plt tests. +2. By default objdump disassemble uses pseudo-instructions so "addi.w" + is outputed as "li.w", causing mismatches in TLS relaxation tests. + We can turn off the pseudo-instruction usage in objdump using "-M + no-aliases" to fix them. + +x86_64 mark-plt tests: 16666ccc91295d1568c5c2cb0e7600694840dfd9 +pseudo-instructions: 17f9439038257b1de0c130a416a9a7645c653cb0 + +Signed-off-by: Xi Ruoyao <xry111@xry111.site> +--- + ld/testsuite/ld-loongarch-elf/desc-ie.d | 2 +- + ld/testsuite/ld-loongarch-elf/desc-norelax.d | 2 +- + ld/testsuite/ld-loongarch-elf/desc-relax.d | 2 +- + ld/testsuite/ld-loongarch-elf/relax.exp | 14 +++++++------- + ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d | 2 +- + 5 files changed, 11 insertions(+), 11 deletions(-) + +diff --git a/ld/testsuite/ld-loongarch-elf/desc-ie.d b/ld/testsuite/ld-loongarch-elf/desc-ie.d +index d1acbfc6..32e35050 100644 +--- a/ld/testsuite/ld-loongarch-elf/desc-ie.d ++++ b/ld/testsuite/ld-loongarch-elf/desc-ie.d +@@ -1,5 +1,5 @@ + #as: +-#ld: -shared -z norelro -e 0x0 ++#ld: -shared -z norelro -e 0x0 --hash-style=both + #objdump: -dr + #skip: loongarch32-*-* + +diff --git a/ld/testsuite/ld-loongarch-elf/desc-norelax.d b/ld/testsuite/ld-loongarch-elf/desc-norelax.d +index 32ce3e5e..e4863dda 100644 +--- a/ld/testsuite/ld-loongarch-elf/desc-norelax.d ++++ b/ld/testsuite/ld-loongarch-elf/desc-norelax.d +@@ -1,5 +1,5 @@ + #as: +-#ld: -z norelro -shared --section-start=.got=0x1ff000 ++#ld: -z norelro -shared --section-start=.got=0x1ff000 --hash-style=both + #objdump: -dr + #skip: loongarch32-*-* + +diff --git a/ld/testsuite/ld-loongarch-elf/desc-relax.d b/ld/testsuite/ld-loongarch-elf/desc-relax.d +index ce53d317..c885953c 100644 +--- a/ld/testsuite/ld-loongarch-elf/desc-relax.d ++++ b/ld/testsuite/ld-loongarch-elf/desc-relax.d +@@ -1,5 +1,5 @@ + #as: +-#ld: -z norelro -shared ++#ld: -z norelro -shared --hash-style=both + #objdump: -dr + #skip: loongarch32-*-* + +diff --git a/ld/testsuite/ld-loongarch-elf/relax.exp b/ld/testsuite/ld-loongarch-elf/relax.exp +index 107e5a56..c537976a 100644 +--- a/ld/testsuite/ld-loongarch-elf/relax.exp ++++ b/ld/testsuite/ld-loongarch-elf/relax.exp +@@ -104,7 +104,7 @@ if istarget loongarch64-*-* { + + + if file exist "tmpdir/relax-tls-le" { +- set objdump_output1 run_host_cmd "objdump" "-d tmpdir/relax-tls-le" ++ set objdump_output1 run_host_cmd "objdump" "-d tmpdir/relax-tls-le -M no-aliases" + if { regexp ".addi.*st.*" $objdump_output1 } { + pass "loongarch relax success" + } { +@@ -125,7 +125,7 @@ if istarget loongarch64-*-* { + + + if file exist "tmpdir/no-relax-tls-le" { +- set objdump_output2 run_host_cmd "objdump" "-d tmpdir/no-relax-tls-le" ++ set objdump_output2 run_host_cmd "objdump" "-d tmpdir/no-relax-tls-le -M no-aliases" + if { regexp ".*lu12i.*add.*addi.*st.*" $objdump_output2 } { + pass "loongarch no-relax success" + } { +@@ -146,7 +146,7 @@ if istarget loongarch64-*-* { + + + if file exist "tmpdir/old-tls-le" { +- set objdump_output3 run_host_cmd "objdump" "-d tmpdir/old-tls-le" ++ set objdump_output3 run_host_cmd "objdump" "-d tmpdir/old-tls-le -M no-aliases" + if { regexp ".*lu12i.*ori.*add.*addi.*stptr.*" $objdump_output3 } { + pass "loongarch old tls le success" + } { +@@ -167,7 +167,7 @@ if istarget loongarch64-*-* { + + + if file exist "tmpdir/realx-compatible" { +- set objdump_output4 run_host_cmd "objdump" "-d tmpdir/realx-compatible" ++ set objdump_output4 run_host_cmd "objdump" "-d tmpdir/realx-compatible -M no-aliases" + if { regexp ".addi.*st.*" $objdump_output4 && \ + regexp ".*lu12i.*ori.*add.*addi.*stptr.*" $objdump_output4 } { + pass "loongarch tls le relax compatible check success" +@@ -188,7 +188,7 @@ if istarget loongarch64-*-* { + \ + + if file exist "tmpdir/no-realx-compatible" { +- set objdump_output4 run_host_cmd "objdump" "-d tmpdir/no-realx-compatible" ++ set objdump_output4 run_host_cmd "objdump" "-d tmpdir/no-realx-compatible -M no-aliases" + if { regexp ".*lu12i.*add.*addi.*st.*" $objdump_output4 && \ + regexp ".*lu12i.*ori.*add.*addi.*stptr.*" $objdump_output4 } { + pass "loongarch tls le no-relax compatible check success" +@@ -210,7 +210,7 @@ if istarget loongarch64-*-* { + + + if file exist "tmpdir/relax-bound-check-tls-le" { +- set objdump_output5 run_host_cmd "objdump" "-d tmpdir/relax-bound-check-tls-le" ++ set objdump_output5 run_host_cmd "objdump" "-d tmpdir/relax-bound-check-tls-le -M no-aliases" + if { regexp ".*lu12i.*add.*addi.*st.*" $objdump_output5 && \ + regexp ".addi.*st.*" $objdump_output5 } { + pass "loongarch no-relax success" +@@ -232,7 +232,7 @@ if istarget loongarch64-*-* { + + + if file exist "tmpdir/no-relax-bound-check-tls-le" { +- set objdump_output5 run_host_cmd "objdump" "-d tmpdir/no-relax-bound-check-tls-le" ++ set objdump_output5 run_host_cmd "objdump" "-d tmpdir/no-relax-bound-check-tls-le -M no-aliases" + if { regexp ".*addi.*st.*" $objdump_output5 } { + pass "loongarch no-relax success" + } { +diff --git a/ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d b/ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d +index 667ad746..453902d1 100644 +--- a/ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d ++++ b/ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d +@@ -1,5 +1,5 @@ + #as: +-#ld: -shared -z norelro ++#ld: -shared -z norelro --hash-style=both + #objdump: -dr + #skip: loongarch32-*-* + +-- +2.33.0 +
View file
_service:tar_scm:LoongArch-Fix-the-issue-of-excessive-relocation-gene.patch
Added
@@ -0,0 +1,437 @@ +From e43c6e4abc81d9bbf66fb210d86682d9f647031d Mon Sep 17 00:00:00 2001 +From: Lulu Cai <cailulu@loongson.cn> +Date: Thu, 21 Mar 2024 16:33:21 +0800 +Subject: PATCH 077/123 LoongArch: Fix the issue of excessive relocation + generated by GD and IE + +Currently, whether GD and IE generate dynamic relocation is +determined by SYMBOL_REFERENCES_LOCAL and bfd_link_executable. +This results in dynamic relocations still being generated in some +situations where dynamic relocations are not necessary (such as +the undefined weak symbol in static links). + +We use RLARCH_TLS_GD_IE_NEED_DYN_RELOC macros to determine whether +GD/IE needs dynamic relocation. If GD/IE requires dynamic relocation, +set need_reloc to true and indx to be a dynamic index. + +At the same time, some test cases were modified to use regular +expression matching instead of complete disassembly matching. +--- + bfd/elfnn-loongarch.c | 179 ++++++++++---------- + ld/testsuite/ld-loongarch-elf/desc-ie.d | 4 +- + ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d | 94 +++++----- + 3 files changed, 142 insertions(+), 135 deletions(-) + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index f6975957..7f98dce1 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -159,6 +159,27 @@ struct loongarch_elf_link_hash_table + || (R_TYPE) == R_LARCH_TLS_LE64_LO20 \ + || (R_TYPE) == R_LARCH_TLS_LE64_HI12) + ++/* If TLS GD/IE need dynamic relocations, INDX will be the dynamic indx, ++ and set NEED_RELOC to true used in allocate_dynrelocs and ++ loongarch_elf_relocate_section for TLS GD/IE. */ ++#define LARCH_TLS_GD_IE_NEED_DYN_RELOC(INFO, DYN, H, INDX, NEED_RELOC) \ ++ do \ ++ { \ ++ if ((H) != NULL \ ++ && (H)->dynindx != -1 \ ++ && WILL_CALL_FINISH_DYNAMIC_SYMBOL ((DYN), \ ++ bfd_link_pic (INFO), (H))) \ ++ (INDX) = (H)->dynindx; \ ++ if (((H) == NULL \ ++ || ELF_ST_VISIBILITY ((H)->other) == STV_DEFAULT \ ++ || (H)->root.type != bfd_link_hash_undefweak) \ ++ && (!bfd_link_executable (INFO) \ ++ || (INDX) != 0)) \ ++ (NEED_RELOC) = true; \ ++ } \ ++ while (0) ++ ++ + /* Generate a PLT header. */ + + static bool +@@ -1276,40 +1297,24 @@ allocate_dynrelocs (struct elf_link_hash_entry *h, void *inf) + h->got.offset = s->size; + if (tls_type & (GOT_TLS_GD | GOT_TLS_IE | GOT_TLS_GDESC)) + { ++ int indx = 0; ++ bool need_reloc = false; ++ LARCH_TLS_GD_IE_NEED_DYN_RELOC (info, dyn, h, indx, ++ need_reloc); + /* TLS_GD needs two dynamic relocs and two GOT slots. */ + if (tls_type & GOT_TLS_GD) + { + s->size += 2 * GOT_ENTRY_SIZE; +- if (bfd_link_executable (info)) +- { +- /* Link exe and not defined local. */ +- if (!SYMBOL_REFERENCES_LOCAL (info, h)) +- htab->elf.srelgot->size += 2 * sizeof (ElfNN_External_Rela); +- } +- else +- { +- if (SYMBOL_REFERENCES_LOCAL (info, h)) +- htab->elf.srelgot->size += sizeof (ElfNN_External_Rela); +- else +- htab->elf.srelgot->size += 2 * sizeof (ElfNN_External_Rela); +- } ++ if (need_reloc) ++ htab->elf.srelgot->size += 2 * sizeof (ElfNN_External_Rela); + } + + /* TLS_IE needs one dynamic reloc and one GOT slot. */ + if (tls_type & GOT_TLS_IE) + { + s->size += GOT_ENTRY_SIZE; +- +- if (bfd_link_executable (info)) +- { +- /* Link exe and not defined local. */ +- if (!SYMBOL_REFERENCES_LOCAL (info, h)) +- htab->elf.srelgot->size += sizeof (ElfNN_External_Rela); +- } +- else +- { +- htab->elf.srelgot->size += sizeof (ElfNN_External_Rela); +- } ++ if (need_reloc) ++ htab->elf.srelgot->size += 2 * sizeof (ElfNN_External_Rela); + } + + /* TLS_DESC needs one dynamic reloc and two GOT slot. */ +@@ -2550,13 +2555,18 @@ loongarch_reloc_is_fatal (struct bfd_link_info *info, + }) + + ++/* Compute the tp/dtp offset of a tls symbol. ++ It is dtp offset in dynamic tls model (gd/ld) and tp ++ offset in static tls model (ie/le). Both offsets are ++ calculated the same way on LoongArch, so the same ++ function is used. */ + static bfd_vma +-tls_dtpoff_base (struct bfd_link_info *info) ++tlsoff (struct bfd_link_info *info, bfd_vma addr) + { + /* If tls_sec is NULL, we should have signalled an error already. */ + if (elf_hash_table (info)->tls_sec == NULL) + return 0; +- return elf_hash_table (info)->tls_sec->vma; ++ return addr - elf_hash_table (info)->tls_sec->vma; + } + + +@@ -2890,7 +2900,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, + is_undefweak, name, "TLS section not be created"); + } + else +- relocation -= elf_hash_table (info)->tls_sec->vma; ++ relocation = tlsoff (info, relocation); + } + else + { +@@ -3416,7 +3426,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, + + case R_LARCH_TLS_LE_HI20_R: + relocation += rel->r_addend; +- relocation -= elf_hash_table (info)->tls_sec->vma; ++ relocation = tlsoff (info, relocation); + RELOCATE_TLS_TP32_HI20 (relocation); + break; + +@@ -3599,7 +3609,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, + BFD_ASSERT (resolved_local && elf_hash_table (info)->tls_sec); + + relocation += rel->r_addend; +- relocation -= elf_hash_table (info)->tls_sec->vma; ++ relocation = tlsoff (info, relocation); + break; + + /* TLS IE LD/GD process separately is troublesome. +@@ -3654,71 +3664,72 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, + /* If a tls variable is accessed in multiple ways, GD uses + the first two slots of GOT, desc follows with two slots, + and IE uses one slot at the end. */ +- desc_off = 0; +- if (GOT_TLS_GD_BOTH_P (tls_type)) +- desc_off = 2 * GOT_ENTRY_SIZE; +- +- ie_off = 0; +- if (GOT_TLS_GD_BOTH_P (tls_type) && (tls_type & GOT_TLS_IE)) +- ie_off = 4 * GOT_ENTRY_SIZE; +- else if (GOT_TLS_GD_ANY_P (tls_type) && (tls_type & GOT_TLS_IE)) +- ie_off = 2 * GOT_ENTRY_SIZE; ++ off = 0; ++ if (tls_type & GOT_TLS_GD) ++ off += 2 * GOT_ENTRY_SIZE; ++ desc_off = off; ++ if (tls_type & GOT_TLS_GDESC) ++ off += 2 * GOT_ENTRY_SIZE; ++ ie_off = off; + + if ((got_off & 1) == 0) + { + Elf_Internal_Rela rela; + asection *relgot = htab->elf.srelgot; +- bfd_vma tls_block_off = 0; + +- if (SYMBOL_REFERENCES_LOCAL (info, h)) +- { +- BFD_ASSERT (elf_hash_table (info)->tls_sec); +- tls_block_off = relocation +- - elf_hash_table (info)->tls_sec->vma; +- } ++ int indx = 0; ++ bool need_reloc = false; ++ LARCH_TLS_GD_IE_NEED_DYN_RELOC (info, is_dyn, h, indx, ++ need_reloc); + + if (tls_type & GOT_TLS_GD) + { +- rela.r_offset = sec_addr (got) + got_off; +- rela.r_addend = 0; +- if (SYMBOL_REFERENCES_LOCAL (info, h)) ++ if (need_reloc) + { +- /* Local sym, used in exec, set module id 1. */
View file
_service:tar_scm:LoongArch-Fix-wrong-relocation-handling-of-symbols-d.patch
Added
@@ -0,0 +1,126 @@ +From a5d5353514c361b3fbc5be1e5d1b51c7b3de591b Mon Sep 17 00:00:00 2001 +From: Lulu Cai <cailulu@loongson.cn> +Date: Fri, 9 Aug 2024 17:40:59 +0800 +Subject: PATCH 109/123 LoongArch: Fix wrong relocation handling of symbols + defined by PROVIDE + +If the symbol defined by PROVIDE in the link script is not in SECTION, +the symbol is placed in the ABS section. The linker considers that +symbols in the ABS section do not need to calculate PC relative offsets. + +Symbols in ABS sections should calculate PC relative offsets normally +based on relocations. +--- + bfd/elfnn-loongarch.c | 2 +- + ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp | 3 +++ + ld/testsuite/ld-loongarch-elf/provide_abs.d | 12 ++++++++++++ + ld/testsuite/ld-loongarch-elf/provide_abs.ld | 1 + + ld/testsuite/ld-loongarch-elf/provide_noabs.d | 13 +++++++++++++ + ld/testsuite/ld-loongarch-elf/provide_noabs.ld | 7 +++++++ + ld/testsuite/ld-loongarch-elf/provide_sym.s | 7 +++++++ + 7 files changed, 44 insertions(+), 1 deletion(-) + create mode 100644 ld/testsuite/ld-loongarch-elf/provide_abs.d + create mode 100644 ld/testsuite/ld-loongarch-elf/provide_abs.ld + create mode 100644 ld/testsuite/ld-loongarch-elf/provide_noabs.d + create mode 100644 ld/testsuite/ld-loongarch-elf/provide_noabs.ld + create mode 100644 ld/testsuite/ld-loongarch-elf/provide_sym.s + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index 0c499c47..14ecd944 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -3312,7 +3312,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, + /* The r_symndx will be STN_UNDEF (zero) only for relocs against symbols + from removed linkonce sections, or sections discarded by a linker + script. Also for R_*_SOP_PUSH_ABSOLUTE and PCREL to specify const. */ +- if (r_symndx == STN_UNDEF || bfd_is_abs_section (sec)) ++ if (r_symndx == STN_UNDEF) + { + defined_local = false; + resolved_local = false; +diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp +index 78726900..cb6d2296 100644 +--- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp ++++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp +@@ -184,5 +184,8 @@ if istarget "loongarch64-*-*" { + run_dump_test "ie-le-relax" + run_dump_test "tlsdesc_abs" + run_dump_test "tlsdesc_extreme" ++ run_dump_test "provide_abs" ++ run_dump_test "provide_noabs" ++ + } + +diff --git a/ld/testsuite/ld-loongarch-elf/provide_abs.d b/ld/testsuite/ld-loongarch-elf/provide_abs.d +new file mode 100644 +index 00000000..1514fb18 +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/provide_abs.d +@@ -0,0 +1,12 @@ ++#source: provide_sym.s ++#as: ++#ld: -T provide_abs.ld ++#objdump: -d ++ ++.*: +file format .* ++ ++#... ++ 0: 58001085 beq \$a0, \$a1, 16 # 10 <fun1> ++ 4: 40000c80 beqz \$a0, 12 # 10 <fun1> ++ 8: 54000800 bl 8 # 10 <fun1> ++#pass +diff --git a/ld/testsuite/ld-loongarch-elf/provide_abs.ld b/ld/testsuite/ld-loongarch-elf/provide_abs.ld +new file mode 100644 +index 00000000..473476cd +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/provide_abs.ld +@@ -0,0 +1 @@ ++PROVIDE(fun1 = 0x10); +diff --git a/ld/testsuite/ld-loongarch-elf/provide_noabs.d b/ld/testsuite/ld-loongarch-elf/provide_noabs.d +new file mode 100644 +index 00000000..7d6bc4d1 +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/provide_noabs.d +@@ -0,0 +1,13 @@ ++#source: provide_sym.s ++#as: ++#ld: -T provide_noabs.ld ++#objdump: -d ++ ++.*: +file format .* ++ ++ ++#... ++ 0: 58001085 beq \$a0, \$a1, 16 # 10 <fun1> ++ 4: 40000c80 beqz \$a0, 12 # 10 <fun1> ++ 8: 54000800 bl 8 # 10 <fun1> ++#pass +diff --git a/ld/testsuite/ld-loongarch-elf/provide_noabs.ld b/ld/testsuite/ld-loongarch-elf/provide_noabs.ld +new file mode 100644 +index 00000000..0154c6f3 +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/provide_noabs.ld +@@ -0,0 +1,7 @@ ++SECTIONS ++{ ++ .text : ++ { ++ PROVIDE(fun1 = 0x10); ++ } ++} +diff --git a/ld/testsuite/ld-loongarch-elf/provide_sym.s b/ld/testsuite/ld-loongarch-elf/provide_sym.s +new file mode 100644 +index 00000000..6610894e +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/provide_sym.s +@@ -0,0 +1,7 @@ ++ .text ++ .globl main ++ .type main, @function ++main: ++ beq $a0,$a1,%b16(fun1) ++ beqz $a0,%b21(fun1) ++ bl %b26(fun1) +-- +2.33.0 +
View file
_service:tar_scm:LoongArch-Fixed-ABI-v1.00-TLS-dynamic-relocation-gen.patch
Added
@@ -0,0 +1,152 @@ +From aa37c01e929ddd41416ecdd6d8b57799cff4b001 Mon Sep 17 00:00:00 2001 +From: Lulu Cai <cailulu@loongson.cn> +Date: Thu, 5 Sep 2024 10:20:49 +0800 +Subject: PATCH 111/123 LoongArch: Fixed ABI v1.00 TLS dynamic relocation + generation bug + +Commit "b67a17aa7c0c478a" modified the logic of allocating dynamic +relocation space for TLS GD/IE, but only modified the logic of +generation dynamic relocations for TLS GD/IE in ABI v2.00. When +linking an object file of ABI v1.00 with bfd ld of ABI v2.00, it +will cause an assertion failure. + +Modified the dynamic relocation generation logic of TLS GD/IE +in ABI v1.00 to be consistent with ABI v2.00. +--- + bfd/elfnn-loongarch.c | 92 +++++++++++++++++++++---------------------- + 1 file changed, 45 insertions(+), 47 deletions(-) + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index 14ecd944..30ac5555 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -3541,7 +3541,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, + bfd_reloc_notsupported, is_undefweak, name, + "TLS section not be created")); + else +- relocation -= elf_hash_table (info)->tls_sec->vma; ++ relocation = tlsoff (info, relocation); + } + else + fatal = (loongarch_reloc_is_fatal +@@ -3890,73 +3890,71 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, + { + Elf_Internal_Rela rela; + asection *srel = htab->elf.srelgot; +- bfd_vma tls_block_off = 0; + +- if (LARCH_REF_LOCAL (info, h)) +- { +- BFD_ASSERT (elf_hash_table (info)->tls_sec); +- tls_block_off = relocation +- - elf_hash_table (info)->tls_sec->vma; +- } ++ int indx = 0; ++ bool need_reloc = false; ++ LARCH_TLS_GD_IE_NEED_DYN_RELOC (info, is_dyn, h, indx, ++ need_reloc); + + if (tls_type & GOT_TLS_GD) + { +- rela.r_offset = sec_addr (got) + got_off; +- rela.r_addend = 0; +- if (LARCH_REF_LOCAL (info, h)) ++ if (need_reloc) + { +- /* Local sym, used in exec, set module id 1. */ +- if (bfd_link_executable (info)) +- bfd_put_NN (output_bfd, 1, got->contents + got_off); ++ /* Dynamic resolved Module ID. */ ++ rela.r_offset = sec_addr (got) + got_off; ++ rela.r_addend = 0; ++ rela.r_info = ELFNN_R_INFO (indx, R_LARCH_TLS_DTPMODNN); ++ bfd_put_NN (output_bfd, 0, got->contents + got_off); ++ loongarch_elf_append_rela (output_bfd, srel, &rela); ++ ++ if (indx == 0) ++ { ++ /* Local symbol, tp offset has been known. */ ++ BFD_ASSERT (! unresolved_reloc); ++ bfd_put_NN (output_bfd, ++ tlsoff (info, relocation), ++ (got->contents + got_off + GOT_ENTRY_SIZE)); ++ } + else + { +- rela.r_info = ELFNN_R_INFO (0, +- R_LARCH_TLS_DTPMODNN); ++ /* Dynamic resolved block offset. */ ++ bfd_put_NN (output_bfd, 0, ++ got->contents + got_off + GOT_ENTRY_SIZE); ++ rela.r_info = ELFNN_R_INFO (indx, ++ R_LARCH_TLS_DTPRELNN); ++ rela.r_offset += GOT_ENTRY_SIZE; + loongarch_elf_append_rela (output_bfd, srel, &rela); + } +- +- bfd_put_NN (output_bfd, tls_block_off, +- got->contents + got_off + GOT_ENTRY_SIZE); + } +- /* Dynamic resolved. */ + else + { +- /* Dynamic relocate module id. */ +- rela.r_info = ELFNN_R_INFO (h->dynindx, +- R_LARCH_TLS_DTPMODNN); +- loongarch_elf_append_rela (output_bfd, srel, &rela); +- +- /* Dynamic relocate offset of block. */ +- rela.r_offset += GOT_ENTRY_SIZE; +- rela.r_info = ELFNN_R_INFO (h->dynindx, +- R_LARCH_TLS_DTPRELNN); +- loongarch_elf_append_rela (output_bfd, srel, &rela); ++ /* In a static link or an executable link with the symbol ++ binding locally. Mark it as belonging to module 1. */ ++ bfd_put_NN (output_bfd, 1, got->contents + got_off); ++ bfd_put_NN (output_bfd, tlsoff (info, relocation), ++ got->contents + got_off + GOT_ENTRY_SIZE); + } + } + if (tls_type & GOT_TLS_IE) + { +- rela.r_offset = sec_addr (got) + got_off + ie_off; +- if (LARCH_REF_LOCAL (info, h)) ++ if (need_reloc) + { +- /* Local sym, used in exec, set module id 1. */ +- if (!bfd_link_executable (info)) +- { +- rela.r_info = ELFNN_R_INFO (0, R_LARCH_TLS_TPRELNN); +- rela.r_addend = tls_block_off; +- loongarch_elf_append_rela (output_bfd, srel, &rela); +- } ++ bfd_put_NN (output_bfd, 0, ++ got->contents + got_off + ie_off); ++ rela.r_offset = sec_addr (got) + got_off + ie_off; ++ rela.r_addend = 0; + +- bfd_put_NN (output_bfd, tls_block_off, +- got->contents + got_off + ie_off); ++ if (indx == 0) ++ rela.r_addend = tlsoff (info, relocation); ++ rela.r_info = ELFNN_R_INFO (indx, R_LARCH_TLS_TPRELNN); ++ loongarch_elf_append_rela (output_bfd, srel, &rela); + } +- /* Dynamic resolved. */ + else + { +- /* Dynamic relocate offset of block. */ +- rela.r_info = ELFNN_R_INFO (h->dynindx, +- R_LARCH_TLS_TPRELNN); +- rela.r_addend = 0; +- loongarch_elf_append_rela (output_bfd, srel, &rela); ++ /* In a static link or an executable link with the symbol ++ binding locally, compute offset directly. */ ++ bfd_put_NN (output_bfd, tlsoff (info, relocation), ++ got->contents + got_off + ie_off); + } + } + } +-- +2.33.0 +
View file
_service:tar_scm:LoongArch-Fixed-R_LARCH_-32-64-_PCREL-generation-bug.patch
Added
@@ -0,0 +1,81 @@ +From 75fa7292c935fc1306985b6959712d633edc9e36 Mon Sep 17 00:00:00 2001 +From: Lulu Cai <cailulu@loongson.cn> +Date: Sat, 21 Sep 2024 11:29:39 +0800 +Subject: PATCH 115/123 LoongArch: Fixed R_LARCH_32/64_PCREL generation bug + +The enum BFD_RELOC_32/64 was mistakenly used in the macro instead +of the relocation in fixp. This can cause the second relocation +of a pair to be deleted when -mthin-add-sub is enabled. Apply the +correct macro to fix this. + +Also sets the initial value of -mthin-add-sub. +--- + gas/config/tc-loongarch.h | 3 ++- + gas/testsuite/gas/loongarch/no_thin_add_sub_8_16.d | 12 ++++++++++++ + gas/testsuite/gas/loongarch/no_thin_add_sub_8_16.s | 6 ++++++ + opcodes/loongarch-opc.c | 3 ++- + 4 files changed, 22 insertions(+), 2 deletions(-) + create mode 100644 gas/testsuite/gas/loongarch/no_thin_add_sub_8_16.d + create mode 100644 gas/testsuite/gas/loongarch/no_thin_add_sub_8_16.s + +diff --git a/gas/config/tc-loongarch.h b/gas/config/tc-loongarch.h +index 05c0af45..2f081edf 100644 +--- a/gas/config/tc-loongarch.h ++++ b/gas/config/tc-loongarch.h +@@ -79,7 +79,8 @@ extern bool loongarch_frag_align_code (int, int); + SEC_CODE, we generate 32/64_PCREL. */ + #define TC_FORCE_RELOCATION_SUB_LOCAL(FIX, SEG) \ + (!(LARCH_opts.thin_add_sub \ +- && (BFD_RELOC_32 || BFD_RELOC_64) \ ++ && ((FIX)->fx_r_type == BFD_RELOC_32 \ ++ ||(FIX)->fx_r_type == BFD_RELOC_64) \ + && (!LARCH_opts.relax \ + || S_GET_VALUE (FIX->fx_subsy) \ + == FIX->fx_frag->fr_address + FIX->fx_where \ +diff --git a/gas/testsuite/gas/loongarch/no_thin_add_sub_8_16.d b/gas/testsuite/gas/loongarch/no_thin_add_sub_8_16.d +new file mode 100644 +index 00000000..334d1742 +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/no_thin_add_sub_8_16.d +@@ -0,0 +1,12 @@ ++#as: -mthin-add-sub ++#readelf: -rW ++#skip: loongarch32-*-* ++ ++Relocation section '.rela.text' at offset 0x108 contains 6 entries: ++.* ++0+0 000000060000002f R_LARCH_ADD8 0+0 global_a \+ 0 ++0+0 0000000400000034 R_LARCH_SUB8 0+0 L0\^A \+ 0 ++0+1 0000000600000030 R_LARCH_ADD16 0+0 global_a \+ 0 ++0+1 0000000500000035 R_LARCH_SUB16 0+1 L0\^A \+ 0 ++0+3 0000000600000063 R_LARCH_32_PCREL 0+0 global_a \+ 0 ++0+7 000000060000006d R_LARCH_64_PCREL 0+0 global_a \+ 0 +diff --git a/gas/testsuite/gas/loongarch/no_thin_add_sub_8_16.s b/gas/testsuite/gas/loongarch/no_thin_add_sub_8_16.s +new file mode 100644 +index 00000000..68f3655c +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/no_thin_add_sub_8_16.s +@@ -0,0 +1,6 @@ ++ .text ++.L1: ++ .byte global_a - . ++ .2byte global_a - . ++ .4byte global_a - . ++ .8byte global_a - . +diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c +index 6afc0e8a..f3794b6a 100644 +--- a/opcodes/loongarch-opc.c ++++ b/opcodes/loongarch-opc.c +@@ -24,7 +24,8 @@ + + struct loongarch_ASEs_option LARCH_opts = + { +- .relax = 1 ++ .relax = 1, ++ .thin_add_sub = 0 + }; + + size_t +-- +2.33.0 +
View file
_service:tar_scm:LoongArch-Fixed-precedence-of-expression-operators-i.patch
Added
@@ -0,0 +1,86 @@ +From 75fd1d4832ec228aa66be49e24ba686bfeb5507b Mon Sep 17 00:00:00 2001 +From: Lulu Cai <cailulu@loongson.cn> +Date: Mon, 2 Sep 2024 12:05:54 +0800 +Subject: PATCH 119/123 LoongArch: Fixed precedence of expression operators + in instructions + +The precedence of the operators "+" and "-" in the current loongarch +instruction expression is higher than "<<" and ">>", which is different +from the explanation in the user guide. + +We modified the precedence of "<<" and ">>" to be higher than "+" and "-". +--- + gas/config/loongarch-parse.y | 24 ++++++++++++------------ + gas/testsuite/gas/loongarch/insn_expr.d | 10 ++++++++++ + gas/testsuite/gas/loongarch/insn_expr.s | 1 + + 3 files changed, 23 insertions(+), 12 deletions(-) + create mode 100644 gas/testsuite/gas/loongarch/insn_expr.d + create mode 100644 gas/testsuite/gas/loongarch/insn_expr.s + +diff --git a/gas/config/loongarch-parse.y b/gas/config/loongarch-parse.y +index f786fdae..ec5a4166 100644 +--- a/gas/config/loongarch-parse.y ++++ b/gas/config/loongarch-parse.y +@@ -368,24 +368,24 @@ multiplicative_expression + | multiplicative_expression '%' unary_expression {emit_bin ('%');} + ; + +-additive_expression ++shift_expression + : multiplicative_expression +- | additive_expression '+' multiplicative_expression {emit_bin ('+');} +- | additive_expression '-' multiplicative_expression {emit_bin ('-');} ++ | shift_expression LEFT_OP multiplicative_expression {emit_bin (LEFT_OP);} ++ | shift_expression RIGHT_OP multiplicative_expression {emit_bin (RIGHT_OP);} + ; + +-shift_expression +- : additive_expression +- | shift_expression LEFT_OP additive_expression {emit_bin (LEFT_OP);} +- | shift_expression RIGHT_OP additive_expression {emit_bin (RIGHT_OP);} ++additive_expression ++ : shift_expression ++ | additive_expression '+' shift_expression {emit_bin ('+');} ++ | additive_expression '-' shift_expression {emit_bin ('-');} + ; + + relational_expression +- : shift_expression +- | relational_expression '<' shift_expression {emit_bin ('<');} +- | relational_expression '>' shift_expression {emit_bin ('>');} +- | relational_expression LE_OP shift_expression {emit_bin (LE_OP);} +- | relational_expression GE_OP shift_expression {emit_bin (GE_OP);} ++ : additive_expression ++ | relational_expression '<' additive_expression {emit_bin ('<');} ++ | relational_expression '>' additive_expression {emit_bin ('>');} ++ | relational_expression LE_OP additive_expression {emit_bin (LE_OP);} ++ | relational_expression GE_OP additive_expression {emit_bin (GE_OP);} + ; + + equality_expression +diff --git a/gas/testsuite/gas/loongarch/insn_expr.d b/gas/testsuite/gas/loongarch/insn_expr.d +new file mode 100644 +index 00000000..9abc711a +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/insn_expr.d +@@ -0,0 +1,10 @@ ++#as: ++#objdump: -d ++ ++.*: file format .* ++ ++ ++Disassembly of section \.text: ++ ++0+ <\.text>: ++ 0: 02c00ca4 addi.d \$a0, \$a1, 3 +diff --git a/gas/testsuite/gas/loongarch/insn_expr.s b/gas/testsuite/gas/loongarch/insn_expr.s +new file mode 100644 +index 00000000..3b9ef08a +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/insn_expr.s +@@ -0,0 +1 @@ ++addi.d $a0,$a1,(8 >> 2 + 1) +-- +2.33.0 +
View file
_service:tar_scm:LoongArch-Force-relocation-for-every-reference-to-th.patch
Added
@@ -0,0 +1,207 @@ +From 6be26e106b7a240afce3fa1d8f214ef90ee53bd1 Mon Sep 17 00:00:00 2001 +From: Lulu Cai <cailulu@loongson.cn> +Date: Thu, 17 Oct 2024 15:08:47 +0800 +Subject: PATCH 118/123 LoongArch: Force relocation for every reference to + the global offset table + +Local absolute symbols are resolved at assembly stage and the symbol +value is placed in the relocation addend. But non-zero addend will +cause an assertion failure during linking. + +Forces emission of relocations to defer resolution of local abs symbols +until link time. + +bfd/ + + * elfnn-loongarch.c (loongarch_elf_relax_section): Determine + absolute symbols in advance to avoid ld crash. + +gas/ + + * config/tc-loongarch.c (loongarch_force_relocation): New + function to force relocation. + * config/tc-loongarch.h (TC_FORCE_RELOCATION): New macros + to force relocation. + (loongarch_force_relocation): Function declaration. + * testsuite/gas/loongarch/localpic.d: New test. + * testsuite/gas/loongarch/localpic.s: New test. +--- + bfd/elfnn-loongarch.c | 16 ++++++++-------- + gas/config/tc-loongarch.c | 24 ++++++++++++++++++++++++ + gas/config/tc-loongarch.h | 3 +++ + gas/testsuite/gas/loongarch/localpic.d | 22 ++++++++++++++++++++++ + gas/testsuite/gas/loongarch/localpic.s | 26 ++++++++++++++++++++++++++ + 5 files changed, 83 insertions(+), 8 deletions(-) + create mode 100644 gas/testsuite/gas/loongarch/localpic.d + create mode 100644 gas/testsuite/gas/loongarch/localpic.s + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index 890233d1..8b9628f7 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -5328,7 +5328,6 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, + bfd_vma symval; + asection *sym_sec; + bool local_got = false; +- bool is_abs_symbol = false; + Elf_Internal_Rela *rel = relocs + i; + struct elf_link_hash_entry *h = NULL; + unsigned long r_type = ELFNN_R_TYPE (rel->r_info); +@@ -5434,8 +5433,9 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, + Elf_Internal_Sym *sym = (Elf_Internal_Sym *)symtab_hdr->contents + + r_symndx; + +- if (ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC +- && r_type != R_LARCH_CALL36) ++ if ((ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC ++ && r_type != R_LARCH_CALL36) ++ || sym->st_shndx == SHN_ABS) + continue; + + /* Only TLS instruction sequences that are accompanied by +@@ -5464,12 +5464,13 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, + symval = sym->st_value; + } + symtype = ELF_ST_TYPE (sym->st_info); +- is_abs_symbol = sym->st_shndx == SHN_ABS; + } + else + { +- if (h != NULL && h->type == STT_GNU_IFUNC +- && r_type != R_LARCH_CALL36) ++ if (h != NULL ++ && ((h->type == STT_GNU_IFUNC ++ && r_type != R_LARCH_CALL36) ++ || bfd_is_abs_section (h->root.u.def.section))) + continue; + + /* The GOT entry of tls symbols must in current execute file or +@@ -5511,7 +5512,6 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, + else + continue; + +- is_abs_symbol = bfd_is_abs_section (h->root.u.def.section); + if (h && LARCH_REF_LOCAL (info, h)) + local_got = true; + symtype = h->type; +@@ -5544,7 +5544,7 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, + + symval += sec_addr (sym_sec); + +- if (r_type == R_LARCH_GOT_PC_HI20 && (!local_got || is_abs_symbol)) ++ if (r_type == R_LARCH_GOT_PC_HI20 && !local_got) + continue; + + if (relax_func (abfd, sec, sym_sec, rel, symval, +diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c +index 046e198f..7fa7fa0f 100644 +--- a/gas/config/tc-loongarch.c ++++ b/gas/config/tc-loongarch.c +@@ -1456,6 +1456,30 @@ md_pcrel_from (fixS *fixP ATTRIBUTE_UNUSED) + return 0; + } + ++/* Return 1 if the relocation must be forced, and 0 if the relocation ++ should never be forced. */ ++int ++loongarch_force_relocation (struct fix *fixp) ++{ ++ /* Ensure we emit a relocation for every reference to the global ++ offset table. */ ++ switch (fixp->fx_r_type) ++ { ++ case BFD_RELOC_LARCH_GOT_PC_HI20: ++ case BFD_RELOC_LARCH_GOT_PC_LO12: ++ case BFD_RELOC_LARCH_GOT64_PC_LO20: ++ case BFD_RELOC_LARCH_GOT64_PC_HI12: ++ case BFD_RELOC_LARCH_GOT_HI20: ++ case BFD_RELOC_LARCH_GOT_LO12: ++ case BFD_RELOC_LARCH_GOT64_LO20: ++ case BFD_RELOC_LARCH_GOT64_HI12: ++ return 1; ++ default: ++ break; ++ } ++ return generic_force_reloc (fixp); ++} ++ + static void fix_reloc_insn (fixS *fixP, bfd_vma reloc_val, char *buf) + { + reloc_howto_type *howto; +diff --git a/gas/config/tc-loongarch.h b/gas/config/tc-loongarch.h +index 2f081edf..da8b0547 100644 +--- a/gas/config/tc-loongarch.h ++++ b/gas/config/tc-loongarch.h +@@ -74,6 +74,9 @@ extern bool loongarch_frag_align_code (int, int); + relaxation, so do not resolve such expressions in the assembler. */ + #define md_allow_local_subtract(l,r,s) 0 + ++#define TC_FORCE_RELOCATION(FIX) loongarch_force_relocation (FIX) ++extern int loongarch_force_relocation (struct fix *); ++ + /* If subsy of BFD_RELOC32/64 and PC in same segment, and without relax + or PC at start of subsy or with relax but sub_symbol_segment not in + SEC_CODE, we generate 32/64_PCREL. */ +diff --git a/gas/testsuite/gas/loongarch/localpic.d b/gas/testsuite/gas/loongarch/localpic.d +new file mode 100644 +index 00000000..bea19578 +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/localpic.d +@@ -0,0 +1,22 @@ ++#as: ++#readelf: -rWs ++#name: loongarch64 local PIC ++ ++Relocation section '.rela.text' at offset 0x0-9a-f+ contains 12 entries: ++ Offset Info Type Symbol's Value Symbol's Name \+ Addend ++0-9a-f+ 0-9a-f+ R_LARCH_GOT_PC_HI20 0-9a-f+ sym \+ 0 ++0-9a-f+ 0-9a-f+ R_LARCH_GOT_PC_LO12 0-9a-f+ sym \+ 0 ++0-9a-f+ 0-9a-f+ R_LARCH_GOT_PC_HI20 0-9a-f+ foo \+ 0 ++0-9a-f+ 0-9a-f+ R_LARCH_GOT_PC_LO12 0-9a-f+ foo \+ 0 ++0-9a-f+ 0-9a-f+ R_LARCH_GOT64_PC_LO20 0-9a-f+ foo \+ 0 ++0-9a-f+ 0-9a-f+ R_LARCH_GOT64_PC_HI12 0-9a-f+ foo \+ 0 ++0-9a-f+ 0-9a-f+ R_LARCH_GOT_HI20 0-9a-f+ foo \+ 0 ++0-9a-f+ 0-9a-f+ R_LARCH_GOT_LO12 0-9a-f+ foo \+ 0 ++0-9a-f+ 0-9a-f+ R_LARCH_GOT_HI20 0-9a-f+ sym \+ 0 ++0-9a-f+ 0-9a-f+ R_LARCH_GOT_LO12 0-9a-f+ sym \+ 0 ++0-9a-f+ 0-9a-f+ R_LARCH_GOT64_LO20 0-9a-f+ sym \+ 0 ++0-9a-f+ 0-9a-f+ R_LARCH_GOT64_HI12 0-9a-f+ sym \+ 0 ++#... ++ +0-9a-f+: +0-9a-f+ 0 NOTYPE LOCAL DEFAULT +0-9a-f+ foo ++ +0-9a-f+: 0+abba 0 NOTYPE LOCAL DEFAULT ABS sym ++#pass +diff --git a/gas/testsuite/gas/loongarch/localpic.s b/gas/testsuite/gas/loongarch/localpic.s +new file mode 100644 +index 00000000..55548e4b +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/localpic.s +@@ -0,0 +1,26 @@ ++.text ++foo: ++ .quad 0 ++ # 32-bit PC-relative ++ pcalau12i $a0,%got_pc_hi20(sym) ++ ld.d $a0,$a0,%got_pc_lo12(sym) ++ # 64-bit PC-relative ++ pcalau12i $a0,%got_pc_hi20(foo) ++ addi.d $a1,$zero,%got_pc_lo12(foo) ++ lu32i.d $a1,%got64_pc_lo20(foo) ++ lu52i.d $a1,$a1,%got64_pc_hi12(foo) ++ ldx.d $a0,$a0,$a1 ++ ++ # 32-bit absolute ++ lu12i.w $a0,%got_hi20(foo) ++ ori $a0,$a0,%got_lo12(foo) ++ ld.w $a0,$a0,0 ++ ++ #64-bit absolute ++ lu12i.w $a0,%got_hi20(sym) ++ ori $a0,$a0,%got_lo12(sym)
View file
_service:tar_scm:LoongArch-GAS-Add-support-for-branch-relaxation.patch
Added
@@ -0,0 +1,529 @@ +From f9249a44e8e12e90cf5a49729107f69661ed07ec Mon Sep 17 00:00:00 2001 +From: mengqinggang <mengqinggang@loongson.cn> +Date: Sun, 24 Sep 2023 14:53:28 +0800 +Subject: PATCH 013/123 LoongArch/GAS: Add support for branch relaxation + +For the instructions of R_LARCH_B16/B21, if the immediate overflow, +add a B instruction and R_LARCH_B26 relocation. + +For example: + +.L1 + ... + blt $t0, $t1, .L1 + R_LARCH_B16 + +change to: + +.L1 + ... + bge $t0, $t1, .L2 + b .L1 + R_LARCH_B26 +.L2 +--- + gas/config/tc-loongarch.c | 236 +++++++++++++++--- + .../gas/loongarch/la_branch_relax_1.d | 64 +++++ + .../gas/loongarch/la_branch_relax_1.s | 33 +++ + .../gas/loongarch/la_branch_relax_2.d | 40 +++ + .../gas/loongarch/la_branch_relax_2.s | 23 ++ + include/opcode/loongarch.h | 12 + + 6 files changed, 367 insertions(+), 41 deletions(-) + create mode 100644 gas/testsuite/gas/loongarch/la_branch_relax_1.d + create mode 100644 gas/testsuite/gas/loongarch/la_branch_relax_1.s + create mode 100644 gas/testsuite/gas/loongarch/la_branch_relax_2.d + create mode 100644 gas/testsuite/gas/loongarch/la_branch_relax_2.s + +diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c +index 4c48382c..059a1711 100644 +--- a/gas/config/tc-loongarch.c ++++ b/gas/config/tc-loongarch.c +@@ -106,6 +106,16 @@ const char *md_shortopts = "O::g::G:"; + + static const char default_arch = DEFAULT_ARCH; + ++/* The lowest 4-bit is the bytes of instructions. */ ++#define RELAX_BRANCH_16 0xc0000014 ++#define RELAX_BRANCH_21 0xc0000024 ++#define RELAX_BRANCH_26 0xc0000048 ++ ++#define RELAX_BRANCH(x) \ ++ (((x) & 0xf0000000) == 0xc0000000) ++#define RELAX_BRANCH_ENCODE(x) \ ++ (BFD_RELOC_LARCH_B16 == (x) ? RELAX_BRANCH_16 : RELAX_BRANCH_21) ++ + enum options + { + OPTION_IGNORE = OPTION_MD_BASE, +@@ -955,11 +965,22 @@ append_fixed_insn (struct loongarch_cl_insn *insn) + move_insn (insn, frag_now, f - frag_now->fr_literal); + } + ++/* Add instructions based on the worst-case scenario firstly. */ ++static void ++append_relaxed_branch_insn (struct loongarch_cl_insn *insn, int max_chars, ++ int var, relax_substateT subtype, symbolS *symbol, offsetT offset) ++{ ++ frag_grow (max_chars); ++ move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); ++ frag_var (rs_machine_dependent, max_chars, var, ++ subtype, symbol, offset, NULL); ++} ++ + static void + append_fixp_and_insn (struct loongarch_cl_insn *ip) + { + reloc_howto_type *howto; +- bfd_reloc_code_real_type reloc_type; ++ bfd_reloc_code_real_type r_type; + struct reloc_info *reloc_info = ip->reloc_info; + size_t i; + +@@ -967,14 +988,40 @@ append_fixp_and_insn (struct loongarch_cl_insn *ip) + + for (i = 0; i < ip->reloc_num; i++) + { +- reloc_type = reloc_infoi.type; +- howto = bfd_reloc_type_lookup (stdoutput, reloc_type); +- if (howto == NULL) +- as_fatal (_("no HOWTO loong relocation number %d"), reloc_type); +- +- ip->fixpi = +- fix_new_exp (ip->frag, ip->where, bfd_get_reloc_size (howto), +- &reloc_infoi.value, FALSE, reloc_type); ++ r_type = reloc_infoi.type; ++ ++ if (r_type != BFD_RELOC_UNUSED) ++ { ++ ++ gas_assert (&(reloc_infoi.value)); ++ if (BFD_RELOC_LARCH_B16 == r_type || BFD_RELOC_LARCH_B21 == r_type) ++ { ++ int min_bytes = 4; /* One branch instruction. */ ++ unsigned max_bytes = 8; /* Branch and jump instructions. */ ++ ++ if (now_seg == absolute_section) ++ { ++ as_bad (_("relaxable branches not supported in absolute section")); ++ return; ++ } ++ ++ append_relaxed_branch_insn (ip, max_bytes, min_bytes, ++ RELAX_BRANCH_ENCODE (r_type), ++ reloc_infoi.value.X_add_symbol, ++ reloc_infoi.value.X_add_number); ++ return; ++ } ++ else ++ { ++ howto = bfd_reloc_type_lookup (stdoutput, r_type); ++ if (howto == NULL) ++ as_fatal (_("no HOWTO loong relocation number %d"), r_type); ++ ++ ip->fixpi = fix_new_exp (ip->frag, ip->where, ++ bfd_get_reloc_size (howto), ++ &reloc_infoi.value, FALSE, r_type); ++ } ++ } + } + + if (ip->insn_length < ip->relax_max_length) +@@ -1489,14 +1536,6 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) + } + } + +-int +-loongarch_relax_frag (asection *sec ATTRIBUTE_UNUSED, +- fragS *fragp ATTRIBUTE_UNUSED, +- long stretch ATTRIBUTE_UNUSED) +-{ +- return 0; +-} +- + int + md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED, + asection *segtype ATTRIBUTE_UNUSED) +@@ -1528,30 +1567,6 @@ tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) + return reloc; + } + +-/* Convert a machine dependent frag. */ +-void +-md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec ATTRIBUTE_UNUSED, +- fragS *fragp) +-{ +- expressionS exp; +- exp.X_op = O_symbol; +- exp.X_add_symbol = fragp->fr_symbol; +- exp.X_add_number = fragp->fr_offset; +- bfd_byte *buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; +- +- fixS *fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, +- 4, &exp, false, fragp->fr_subtype); +- buf += 4; +- +- fixp->fx_file = fragp->fr_file; +- fixp->fx_line = fragp->fr_line; +- fragp->fr_fix += fragp->fr_var; +- +- gas_assert (fragp->fr_next == NULL +- || (fragp->fr_next->fr_address - fragp->fr_address +- == fragp->fr_fix)); +-} +- + /* Standard calling conventions leave the CFA at SP on entry. */ + void + loongarch_cfi_frame_initial_instructions (void) +@@ -1777,3 +1792,142 @@ loongarch_elf_final_processing (void) + { + elf_elfheader (stdoutput)->e_flags = LARCH_opts.ase_abi; + } ++ ++/* Compute the length of a branch sequence, and adjust the stored length ++ accordingly. If FRAGP is NULL, the worst-case length is returned. */ ++static unsigned ++loongarch_relaxed_branch_length (fragS *fragp, asection *sec, int update) ++{ ++ int length = 4; ++ ++ if (!fragp) ++ return 8; ++ ++ if (fragp->fr_symbol != NULL ++ && S_IS_DEFINED (fragp->fr_symbol) ++ && !S_IS_WEAK (fragp->fr_symbol) ++ && sec == S_GET_SEGMENT (fragp->fr_symbol)) ++ { ++ offsetT val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; ++ ++ val -= fragp->fr_address + fragp->fr_fix;
View file
_service:tar_scm:LoongArch-LoongArch64-allows-relocations-to-use-64-b.patch
Added
@@ -0,0 +1,65 @@ +From 87c63c08d6171b556f86c14fded00ab8b4aaa73b Mon Sep 17 00:00:00 2001 +From: Lulu Cai <cailulu@loongson.cn> +Date: Wed, 7 Aug 2024 18:04:26 +0800 +Subject: PATCH 110/123 LoongArch: LoongArch64 allows relocations to use + 64-bit addends + +Relocations using 64-bit addends allow larger constant offset address +calculations to be fused. +--- + gas/config/tc-loongarch.c | 3 +++ + gas/testsuite/gas/loongarch/large_addend.d | 12 ++++++++++++ + gas/testsuite/gas/loongarch/large_addend.s | 8 ++++++++ + 3 files changed, 23 insertions(+) + create mode 100644 gas/testsuite/gas/loongarch/large_addend.d + create mode 100644 gas/testsuite/gas/loongarch/large_addend.s + +diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c +index 72815233..16355cac 100644 +--- a/gas/config/tc-loongarch.c ++++ b/gas/config/tc-loongarch.c +@@ -1221,6 +1221,9 @@ append_fixp_and_insn (struct loongarch_cl_insn *ip) + bfd_get_reloc_size (howto), + &reloc_infoi.value, FALSE, r_type); + } ++ /* Allow LoongArch 64 to use 64-bit addends. */ ++ if (LARCH_opts.ase_lp64) ++ ip->fixpi->fx_no_overflow = 1; + } + } + +diff --git a/gas/testsuite/gas/loongarch/large_addend.d b/gas/testsuite/gas/loongarch/large_addend.d +new file mode 100644 +index 00000000..18eb33a3 +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/large_addend.d +@@ -0,0 +1,12 @@ ++#as: ++#objdump: -r ++#skip: loongarch32-*-* ++ ++.*: file format elf64-loongarch ++ ++RELOCATION RECORDS FOR \\.text\: ++OFFSET TYPE VALUE ++0000000000000000 R_LARCH_PCALA_HI20 _start\+0x7fffabcd12345678 ++0000000000000004 R_LARCH_PCALA_LO12 _start\+0x7fffabcd12345678 ++0000000000000008 R_LARCH_PCALA64_LO20 _start\+0x7fffabcd12345678 ++000000000000000c R_LARCH_PCALA64_HI12 _start\+0x7fffabcd12345678 +diff --git a/gas/testsuite/gas/loongarch/large_addend.s b/gas/testsuite/gas/loongarch/large_addend.s +new file mode 100644 +index 00000000..7db90525 +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/large_addend.s +@@ -0,0 +1,8 @@ ++ .text ++ .global _start ++_start: ++ pcalau12i $a0, %pc_hi20(_start+0x7fffabcd12345678) ++ addi.d $a1, $zero, %pc_lo12(_start+0x7fffabcd12345678) ++ lu32i.d $a1, %pc64_lo20(_start+0x7fffabcd12345678) ++ lu52i.d $a1, $a1, %pc64_hi12(_start+0x7fffabcd12345678) ++ add.d $a0, $a1, $a0 +-- +2.33.0 +
View file
_service:tar_scm:LoongArch-Make-align-symbol-be-in-same-section-with-.patch
Added
@@ -0,0 +1,303 @@ +From ea14dbe723a67501b377bf6d4f390ca4b6a58938 Mon Sep 17 00:00:00 2001 +From: mengqinggang <mengqinggang@loongson.cn> +Date: Wed, 29 May 2024 14:50:39 +0800 +Subject: PATCH 089/123 LoongArch: Make align symbol be in same section with + alignment directive + +R_LARCH_ALIGN (psABI v2.30) requires a symbol index. The symbol is only +created at the first time to handle alignment directive. This means that +all other sections may use this symbol. If the section of this symbol is +discarded, there may be problems. Search it in its own section. + +Remove elf_backend_data.is_rela_normal() function added at commit daeda14191c. + +Co-authored-by: Jinyang He <hejinyang@loongson.cn> +Reported-by: WANG Xuerui <git@xen0n.name> +Link: https://lore.kernel.org/loongarch/2abbb633-a10e-71cc-a5e1-4d9e39074066@loongson.cn/T/#t +--- + bfd/elf-bfd.h | 4 -- + bfd/elflink.c | 5 +- + bfd/elfnn-loongarch.c | 16 ------ + bfd/elfxx-target.h | 5 -- + gas/config/tc-loongarch.c | 63 +++++++++++++++++++++- + gas/config/tc-loongarch.h | 3 ++ + gas/testsuite/gas/loongarch/relax-align2.d | 24 +++++++++ + gas/testsuite/gas/loongarch/relax-align2.s | 11 ++++ + gas/testsuite/gas/loongarch/relax_align.d | 6 +-- + 9 files changed, 104 insertions(+), 33 deletions(-) + create mode 100644 gas/testsuite/gas/loongarch/relax-align2.d + create mode 100644 gas/testsuite/gas/loongarch/relax-align2.s + +diff --git a/bfd/elf-bfd.h b/bfd/elf-bfd.h +index 074120a5..ec856764 100644 +--- a/bfd/elf-bfd.h ++++ b/bfd/elf-bfd.h +@@ -1703,10 +1703,6 @@ struct elf_backend_data + backend relocate_section routine for relocatable linking. */ + unsigned rela_normal : 1; + +- /* Whether a relocation is rela_normal. Compared with rela_normal, +- is_rela_normal can set part of relocations to rela_normal. */ +- bool (*is_rela_normal) (Elf_Internal_Rela *); +- + /* Set if DT_REL/DT_RELA/DT_RELSZ/DT_RELASZ should not include PLT + relocations. */ + unsigned dtrel_excludes_plt : 1; +diff --git a/bfd/elflink.c b/bfd/elflink.c +index cbf87d70..7217c2f0 100644 +--- a/bfd/elflink.c ++++ b/bfd/elflink.c +@@ -11647,10 +11647,7 @@ elf_link_input_bfd (struct elf_final_link_info *flinfo, bfd *input_bfd) + { + rel_hash = PTR_ADD (esdo->rela.hashes, esdo->rela.count); + rela_hash_list = rel_hash; +- if (bed->is_rela_normal != NULL) +- rela_normal = bed->is_rela_normal (irela); +- else +- rela_normal = bed->rela_normal; ++ rela_normal = bed->rela_normal; + } + + irela->r_offset = _bfd_elf_section_offset (output_bfd, +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index eb572a77..9eaad7f4 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -5527,21 +5527,6 @@ elf_loongarch64_hash_symbol (struct elf_link_hash_entry *h) + return _bfd_elf_hash_symbol (h); + } + +-/* If a relocation is rela_normal and the symbol associated with the +- relocation is STT_SECTION type, the addend of the relocation would add +- sec->output_offset when partial linking (ld -r). +- See elf_backend_data.rela_normal and elf_link_input_bfd(). +- The addend of R_LARCH_ALIGN is used to represent the first and third +- expression of .align, it should be a constant when linking. */ +- +-static bool +-loongarch_elf_is_rela_normal (Elf_Internal_Rela *rel) +-{ +- if (R_LARCH_ALIGN == ELFNN_R_TYPE (rel->r_info)) +- return false; +- return true; +-} +- + #define TARGET_LITTLE_SYM loongarch_elfNN_vec + #define TARGET_LITTLE_NAME "elfNN-loongarch" + #define ELF_ARCH bfd_arch_loongarch +@@ -5577,7 +5562,6 @@ loongarch_elf_is_rela_normal (Elf_Internal_Rela *rel) + #define elf_backend_grok_psinfo loongarch_elf_grok_psinfo + #define elf_backend_hash_symbol elf_loongarch64_hash_symbol + #define bfd_elfNN_bfd_relax_section loongarch_elf_relax_section +-#define elf_backend_is_rela_normal loongarch_elf_is_rela_normal + + #define elf_backend_dtrel_excludes_plt 1 + +diff --git a/bfd/elfxx-target.h b/bfd/elfxx-target.h +index 385e40b7..f8553006 100644 +--- a/bfd/elfxx-target.h ++++ b/bfd/elfxx-target.h +@@ -703,10 +703,6 @@ + #define elf_backend_rela_normal 0 + #endif + +-#ifndef elf_backend_is_rela_normal +-#define elf_backend_is_rela_normal NULL +-#endif +- + #ifndef elf_backend_dtrel_excludes_plt + #define elf_backend_dtrel_excludes_plt 0 + #endif +@@ -952,7 +948,6 @@ static const struct elf_backend_data elfNN_bed = + elf_backend_default_use_rela_p, + elf_backend_rela_plts_and_copies_p, + elf_backend_rela_normal, +- elf_backend_is_rela_normal, + elf_backend_dtrel_excludes_plt, + elf_backend_sign_extend_vma, + elf_backend_want_got_plt, +diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c +index f030fd07..f039d027 100644 +--- a/gas/config/tc-loongarch.c ++++ b/gas/config/tc-loongarch.c +@@ -419,6 +419,55 @@ loongarch_target_format () + return LARCH_opts.ase_lp64 ? "elf64-loongarch" : "elf32-loongarch"; + } + ++typedef struct ++{ ++ unsigned int sec_id; ++ symbolS *s; ++} align_sec_sym; ++ ++static htab_t align_hash; ++ ++static hashval_t ++align_sec_sym_hash (const void *entry) ++{ ++ const align_sec_sym *e = entry; ++ return (hashval_t) (e->sec_id); ++} ++ ++static int ++align_sec_sym_eq (const void *entry1, const void *entry2) ++{ ++ const align_sec_sym *e1 = entry1, *e2 = entry2; ++ return e1->sec_id == e2->sec_id; ++} ++ ++/* Make align symbol be in same section with alignment directive. ++ If the symbol is only created at the first time to handle alignment ++ directive. This means that all other sections may use this symbol. ++ If the section of this symbol is discarded, there may be problems. */ ++ ++static symbolS *get_align_symbol (segT sec) ++{ ++ align_sec_sym search = { sec->id, NULL }; ++ align_sec_sym *pentry = htab_find (align_hash, &search); ++ if (pentry) ++ return pentry->s; ++ ++ /* If we not find the symbol in this section. Create and insert it. */ ++ symbolS *s = (symbolS *)local_symbol_make (".Lla-relax-align", sec, ++ &zero_address_frag, 0); ++ align_sec_sym entry = { sec->id, s }; ++ align_sec_sym **slot = (align_sec_sym **) htab_find_slot (align_hash, ++ &entry, INSERT); ++ if (slot == NULL) ++ return NULL; ++ *slot = (align_sec_sym *) xmalloc (sizeof (align_sec_sym)); ++ if (*slot == NULL) ++ return NULL; ++ **slot = entry; ++ return entry.s; ++} ++ + void + md_begin () + { +@@ -440,11 +489,21 @@ md_begin () + it->name, it->format, it->macro); + } + ++ align_hash = htab_create (10, align_sec_sym_hash, align_sec_sym_eq, free); ++ + /* FIXME: expressionS use 'offsetT' as constant, + * we want this is 64-bit type. */ + assert (8 <= sizeof (offsetT)); + } + ++/* Called just before the assembler exits. */ ++ ++void ++loongarch_md_end (void) ++{ ++ htab_delete (align_hash); ++} ++ + unsigned long + loongarch_mach (void)
View file
_service:tar_scm:LoongArch-Make-protected-function-symbols-local-for-.patch
Added
@@ -0,0 +1,311 @@ +From a95555b83c866216189dde969ab7b76ebd57c60c Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao <xry111@xry111.site> +Date: Sun, 30 Jun 2024 15:18:23 +0800 +Subject: PATCH 097/123 LoongArch: Make protected function symbols local for + -shared + +On LoongArch there is no reason to treat STV_PROTECTED STT_FUNC symbols +as preemptible. See the comment above LARCH_REF_LOCAL for detailed +explanation. + +Signed-off-by: Xi Ruoyao <xry111@xry111.site> +--- + bfd/elfnn-loongarch.c | 76 ++++++++++++++----- + ld/testsuite/ld-loongarch-elf/ifunc-reloc.d | 2 +- + .../ld-loongarch-elf/ld-loongarch-elf.exp | 1 + + .../ld-loongarch-elf/protected-func.d | 6 ++ + .../ld-loongarch-elf/protected-func.s | 17 +++++ + 5 files changed, 81 insertions(+), 21 deletions(-) + create mode 100644 ld/testsuite/ld-loongarch-elf/protected-func.d + create mode 100644 ld/testsuite/ld-loongarch-elf/protected-func.s + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index 6b1a4ecc..2bdd7be2 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -181,6 +181,44 @@ struct loongarch_elf_link_hash_table + } \ + while (0) + ++/* TL;DR always use it in this file instead when you want to type ++ SYMBOL_REFERENCES_LOCAL. ++ ++ It's like SYMBOL_REFERENCES_LOCAL, but it returns true for local ++ protected functions. It happens to be same as SYMBOL_CALLS_LOCAL but ++ let's not reuse SYMBOL_CALLS_LOCAL or "CALLS" may puzzle people. ++ ++ We do generate a PLT entry when someone attempts to la.pcrel an external ++ function. But we never really implemented "R_LARCH_COPY", thus we've ++ never supported la.pcrel an external symbol unless the loaded address is ++ only used for locating a function to be called. Thus the PLT entry is ++ a normal PLT entry, not intended to be a so-called "canonical PLT entry" ++ on the ports supporting copy relocation. So attempting to la.pcrel an ++ external function will just break pointer equality, even it's a ++ STV_DEFAULT function: ++ ++ $ cat t.c ++ #include <assert.h> ++ void check(void *p) {assert(p == check);} ++ $ cat main.c ++ extern void check(void *); ++ int main(void) { check(check); } ++ $ cc t.c -fPIC -shared -o t.so ++ $ cc main.c -mdirect-extern-access t.so -Wl,-rpath=. -fpie -pie ++ $ ./a.out ++ a.out: t.c:2: check: Assertion `p == check' failed. ++ Aborted ++ ++ Thus handling STV_PROTECTED function specially just fixes nothing: ++ adding -fvisibility=protected compiling t.c will not magically fix ++ the inequality. The only possible and correct fix is not to use ++ -mdirect-extern-access. ++ ++ So we should remove this special handling, because it's only an ++ unsuccessful workaround for invalid code and it's penalizing valid ++ code. */ ++#define LARCH_REF_LOCAL(info, h) \ ++ (_bfd_elf_symbol_refs_local_p ((h), (info), true)) + + /* Generate a PLT header. */ + +@@ -712,7 +750,7 @@ loongarch_tls_transition_without_check (struct bfd_link_info *info, + struct elf_link_hash_entry *h) + { + bool local_exec = bfd_link_executable (info) +- && SYMBOL_REFERENCES_LOCAL (info, h); ++ && LARCH_REF_LOCAL (info, h); + + switch (r_type) + { +@@ -1221,7 +1259,7 @@ loongarch_elf_adjust_dynamic_symbol (struct bfd_link_info *info, + { + if (h->plt.refcount <= 0 + || (h->type != STT_GNU_IFUNC +- && (SYMBOL_REFERENCES_LOCAL (info, h) ++ && (LARCH_REF_LOCAL (info, h) + || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT + && h->root.type == bfd_link_hash_undefweak)))) + { +@@ -1739,14 +1777,14 @@ elfNN_allocate_ifunc_dynrelocs (struct elf_link_hash_entry *h, + here if it is defined and referenced in a non-shared object. */ + if (h->type == STT_GNU_IFUNC && h->def_regular) + { +- if (ref_local && SYMBOL_REFERENCES_LOCAL (info, h)) ++ if (ref_local && LARCH_REF_LOCAL (info, h)) + return local_allocate_ifunc_dyn_relocs (info, h, + &h->dyn_relocs, + PLT_ENTRY_SIZE, + PLT_HEADER_SIZE, + GOT_ENTRY_SIZE, + false); +- else if (!ref_local && !SYMBOL_REFERENCES_LOCAL (info, h)) ++ else if (!ref_local && !LARCH_REF_LOCAL (info, h)) + return _bfd_elf_allocate_ifunc_dyn_relocs (info, h, + &h->dyn_relocs, + PLT_ENTRY_SIZE, +@@ -1774,7 +1812,6 @@ elfNN_allocate_ifunc_dynrelocs_ref_global (struct elf_link_hash_entry *h, + false); + } + +- + /* Allocate space in .plt, .got and associated reloc sections for + ifunc dynamic relocs. */ + +@@ -2686,7 +2723,6 @@ tlsoff (struct bfd_link_info *info, bfd_vma addr) + return addr - elf_hash_table (info)->tls_sec->vma; + } + +- + static int + loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, + bfd *input_bfd, asection *input_section, +@@ -2812,7 +2848,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, + { + defined_local = !unresolved_reloc && !ignored; + resolved_local = +- defined_local && SYMBOL_REFERENCES_LOCAL (info, h); ++ defined_local && LARCH_REF_LOCAL (info, h); + resolved_dynly = !resolved_local; + resolved_to_const = !resolved_local && !resolved_dynly; + } +@@ -2901,7 +2937,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, + outrel.r_addend = 0; + } + +- if (SYMBOL_REFERENCES_LOCAL (info, h)) ++ if (LARCH_REF_LOCAL (info, h)) + { + + if (htab->elf.splt != NULL) +@@ -3251,7 +3287,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, + if (!WILL_CALL_FINISH_DYNAMIC_SYMBOL (is_dyn, + bfd_link_pic (info), h) + && ((bfd_link_pic (info) +- && SYMBOL_REFERENCES_LOCAL (info, h)))) ++ && LARCH_REF_LOCAL (info, h)))) + { + /* This is actually a static link, or it is a + -Bsymbolic link and the symbol is defined +@@ -3396,7 +3432,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, + asection *srel = htab->elf.srelgot; + bfd_vma tls_block_off = 0; + +- if (SYMBOL_REFERENCES_LOCAL (info, h)) ++ if (LARCH_REF_LOCAL (info, h)) + { + BFD_ASSERT (elf_hash_table (info)->tls_sec); + tls_block_off = relocation +@@ -3407,7 +3443,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, + { + rela.r_offset = sec_addr (got) + got_off; + rela.r_addend = 0; +- if (SYMBOL_REFERENCES_LOCAL (info, h)) ++ if (LARCH_REF_LOCAL (info, h)) + { + /* Local sym, used in exec, set module id 1. */ + if (bfd_link_executable (info)) +@@ -3440,7 +3476,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, + if (tls_type & GOT_TLS_IE) + { + rela.r_offset = sec_addr (got) + got_off + ie_off; +- if (SYMBOL_REFERENCES_LOCAL (info, h)) ++ if (LARCH_REF_LOCAL (info, h)) + { + /* Local sym, used in exec, set module id 1. */ + if (!bfd_link_executable (info)) +@@ -3642,7 +3678,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, + bfd_link_pic (info), + h) + && bfd_link_pic (info) +- && SYMBOL_REFERENCES_LOCAL (info, h)) ++ && LARCH_REF_LOCAL (info, h)) + { + Elf_Internal_Rela rela; + rela.r_offset = sec_addr (got) + got_off; +@@ -4183,7 +4219,7 @@ loongarch_tls_perform_trans (bfd *abfd, asection *sec, + { + unsigned long insn; + bool local_exec = bfd_link_executable (info) +- && SYMBOL_REFERENCES_LOCAL (info, h); ++ && LARCH_REF_LOCAL (info, h); + bfd_byte *contents = elf_section_data (sec)->this_hdr.contents; + unsigned long r_type = ELFNN_R_TYPE (rel->r_info); + unsigned long r_symndx = ELFNN_R_SYM (rel->r_info); +@@ -4895,7 +4931,7 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, + else + continue; + +- if (h && SYMBOL_REFERENCES_LOCAL (info, h)) ++ if (h && LARCH_REF_LOCAL (info, h))
View file
_service:tar_scm:LoongArch-Not-alloc-dynamic-relocs-if-symbol-is-abso.patch
Added
@@ -0,0 +1,128 @@ +From d7c082ef88547077b24d3b27144daf4ce4e442f4 Mon Sep 17 00:00:00 2001 +From: Jinyang He <hejinyang@loongson.cn> +Date: Mon, 8 Jul 2024 11:27:52 +0800 +Subject: PATCH 101/123 LoongArch: Not alloc dynamic relocs if symbol is + absolute + +The absolute symbol should be resolved to const when link to dso or exe. +Alloc dynamic relocs will cause extra space and R_LARCH_NONE finally. +--- + bfd/elfnn-loongarch.c | 14 +++++++------- + ld/testsuite/ld-loongarch-elf/abssym.s | 3 +++ + ld/testsuite/ld-loongarch-elf/abssym_pie.d | 6 ++++++ + ld/testsuite/ld-loongarch-elf/abssym_shared.d | 6 ++++++ + ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp | 2 ++ + 5 files changed, 24 insertions(+), 7 deletions(-) + create mode 100644 ld/testsuite/ld-loongarch-elf/abssym.s + create mode 100644 ld/testsuite/ld-loongarch-elf/abssym_pie.d + create mode 100644 ld/testsuite/ld-loongarch-elf/abssym_shared.d + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index d11189b4..af4d8baa 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -899,6 +899,7 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, + unsigned int r_type; + unsigned int r_symndx; + struct elf_link_hash_entry *h; ++ bool is_abs_symbol = false; + Elf_Internal_Sym *isym = NULL; + + r_symndx = ELFNN_R_SYM (rel->r_info); +@@ -917,6 +918,7 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, + if (isym == NULL) + return false; + ++ is_abs_symbol = isym->st_shndx == SHN_ABS; + if (ELF_ST_TYPE (isym->st_info) == STT_GNU_IFUNC) + { + h = elfNN_loongarch_get_local_sym_hash (htab, abfd, rel, true); +@@ -935,6 +937,7 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, + while (h->root.type == bfd_link_hash_indirect + || h->root.type == bfd_link_hash_warning) + h = (struct elf_link_hash_entry *) h->root.u.i.link; ++ is_abs_symbol = bfd_is_abs_symbol (&h->root); + } + + /* It is referenced by a non-shared object. */ +@@ -1142,13 +1145,6 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, + && bfd_link_pic (info) + && (sec->flags & SEC_ALLOC) != 0) + { +- bool is_abs_symbol = false; +- +- if (r_symndx < symtab_hdr->sh_info) +- is_abs_symbol = isym->st_shndx == SHN_ABS; +- else +- is_abs_symbol = bfd_is_abs_symbol (&h->root); +- + if (!is_abs_symbol) + { + _bfd_error_handler +@@ -1165,6 +1161,10 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, + case R_LARCH_JUMP_SLOT: + case R_LARCH_64: + ++ /* Resolved to const. */ ++ if (is_abs_symbol) ++ break; ++ + need_dynreloc = 1; + + /* If resolved symbol is defined in this object, +diff --git a/ld/testsuite/ld-loongarch-elf/abssym.s b/ld/testsuite/ld-loongarch-elf/abssym.s +new file mode 100644 +index 00000000..3eacc766 +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/abssym.s +@@ -0,0 +1,3 @@ ++.section .data,"aw" ++.quad _size8 ++.word _size4 +diff --git a/ld/testsuite/ld-loongarch-elf/abssym_pie.d b/ld/testsuite/ld-loongarch-elf/abssym_pie.d +new file mode 100644 +index 00000000..dfc3e35b +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/abssym_pie.d +@@ -0,0 +1,6 @@ ++#source: abssym.s ++#ld: -pie -e 0 --defsym _size8=0 --defsym _size4=0 ++#readelf: -r ++#... ++There are no relocations in this file. ++#... +diff --git a/ld/testsuite/ld-loongarch-elf/abssym_shared.d b/ld/testsuite/ld-loongarch-elf/abssym_shared.d +new file mode 100644 +index 00000000..2db7e890 +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/abssym_shared.d +@@ -0,0 +1,6 @@ ++#source: abssym.s ++#ld: -shared --defsym _size8=0 --defsym _size4=0 ++#readelf: -r ++#... ++There are no relocations in this file. ++#... +diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp +index 2be67651..032b9bad 100644 +--- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp ++++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp +@@ -141,6 +141,7 @@ if istarget "loongarch64-*-*" { + run_dump_test "relr-discard-shared" + run_dump_test "relr-got-shared" + run_dump_test "relr-text-shared" ++ run_dump_test "abssym_shared" + } + + if check_pie_support { +@@ -149,6 +150,7 @@ if istarget "loongarch64-*-*" { + run_dump_test "relr-discard-pie" + run_dump_test "relr-got-pie" + run_dump_test "relr-text-pie" ++ run_dump_test "abssym_pie" + } + + run_dump_test "max_imm_b16" +-- +2.33.0 +
View file
_service:tar_scm:LoongArch-Optimize-the-relaxation-process.patch
Added
@@ -0,0 +1,482 @@ +From 4c19c0fd7815a9acabdca9954028f772da1d985e Mon Sep 17 00:00:00 2001 +From: mengqinggang <mengqinggang@loongson.cn> +Date: Thu, 10 Oct 2024 16:20:52 +0800 +Subject: PATCH 116/123 LoongArch: Optimize the relaxation process + +The symbol value is only calculated when the relocation can be relaxed. +--- + bfd/elfnn-loongarch.c | 281 +++++++++++++++++++++--------------------- + 1 file changed, 139 insertions(+), 142 deletions(-) + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index b6d7d1e8..70522fae 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -4072,7 +4072,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, + /* For 2G jump, generate pcalau12i, jirl. */ + /* If use jirl, turns to R_LARCH_B16. */ + uint32_t insn = bfd_get (32, input_bfd, contents + rel->r_offset); +- if (LARCH_INSN_JIRL(insn)) ++ if (LARCH_INSN_JIRL (insn)) + { + relocation &= 0xfff; + /* Signed extend. */ +@@ -4852,9 +4852,11 @@ loongarch_tls_perform_trans (bfd *abfd, asection *sec, + */ + static bool + loongarch_relax_tls_le (bfd *abfd, asection *sec, +- Elf_Internal_Rela *rel, ++ asection *sym_sec ATTRIBUTE_UNUSED, ++ Elf_Internal_Rela *rel, bfd_vma symval, + struct bfd_link_info *link_info, +- bfd_vma symval) ++ bool *agin ATTRIBUTE_UNUSED, ++ bfd_vma max_alignment ATTRIBUTE_UNUSED) + { + bfd_byte *contents = elf_section_data (sec)->this_hdr.contents; + uint32_t insn = bfd_get (32, abfd, contents + rel->r_offset); +@@ -4862,7 +4864,7 @@ loongarch_relax_tls_le (bfd *abfd, asection *sec, + symval = symval - elf_hash_table (link_info)->tls_sec->vma; + /* The old LE instruction sequence can be relaxed when the symbol offset + is smaller than the 12-bit range. */ +- if (ELFNN_R_TYPE ((rel + 1)->r_info) == R_LARCH_RELAX && (symval <= 0xfff)) ++ if (symval <= 0xfff) + { + switch (ELFNN_R_TYPE (rel->r_info)) + { +@@ -4975,9 +4977,6 @@ loongarch_relax_pcala_addi (bfd *abfd, asection *sec, asection *sym_sec, + + /* Is pcalau12i + addi.d insns? */ + if ((ELFNN_R_TYPE (rel_lo->r_info) != R_LARCH_PCALA_LO12) +- || (ELFNN_R_TYPE ((rel_lo + 1)->r_info) != R_LARCH_RELAX) +- || (ELFNN_R_TYPE ((rel_hi + 1)->r_info) != R_LARCH_RELAX) +- || (rel_hi->r_offset + 4 != rel_lo->r_offset) + || !LARCH_INSN_ADDI_D(add) + /* Is pcalau12i $rd + addi.d $rd,$rd? */ + || (LARCH_GET_RD(add) != rd) +@@ -5035,10 +5034,8 @@ loongarch_relax_call36 (bfd *abfd, asection *sec, asection *sym_sec, + else if (symval < pc) + pc += (max_alignment > 4 ? max_alignment : 0); + +- + /* Is pcalau12i + addi.d insns? */ +- if ((ELFNN_R_TYPE ((rel + 1)->r_info) != R_LARCH_RELAX) +- || !LARCH_INSN_JIRL(jirl) ++ if (!LARCH_INSN_JIRL (jirl) + || ((bfd_signed_vma)(symval - pc) < (bfd_signed_vma)(int32_t)0xf8000000) + || ((bfd_signed_vma)(symval - pc) > (bfd_signed_vma)(int32_t)0x7fffffc)) + return false; +@@ -5064,7 +5061,12 @@ loongarch_relax_call36 (bfd *abfd, asection *sec, asection *sym_sec, + /* Relax pcalau12i,ld.d => pcalau12i,addi.d. */ + static bool + loongarch_relax_pcala_ld (bfd *abfd, asection *sec, +- Elf_Internal_Rela *rel_hi) ++ asection *sym_sec ATTRIBUTE_UNUSED, ++ Elf_Internal_Rela *rel_hi, ++ bfd_vma symval ATTRIBUTE_UNUSED, ++ struct bfd_link_info *info ATTRIBUTE_UNUSED, ++ bool *again ATTRIBUTE_UNUSED, ++ bfd_vma max_alignment ATTRIBUTE_UNUSED) + { + bfd_byte *contents = elf_section_data (sec)->this_hdr.contents; + Elf_Internal_Rela *rel_lo = rel_hi + 2; +@@ -5074,9 +5076,6 @@ loongarch_relax_pcala_ld (bfd *abfd, asection *sec, + uint32_t addi_d = LARCH_OP_ADDI_D; + + if ((ELFNN_R_TYPE (rel_lo->r_info) != R_LARCH_GOT_PC_LO12) +- || (ELFNN_R_TYPE ((rel_lo + 1)->r_info) != R_LARCH_RELAX) +- || (ELFNN_R_TYPE ((rel_hi + 1)->r_info) != R_LARCH_RELAX) +- || (rel_hi->r_offset + 4 != rel_lo->r_offset) + || (LARCH_GET_RD(ld) != rd) + || (LARCH_GET_RJ(ld) != rd) + || !LARCH_INSN_LD_D(ld)) +@@ -5106,11 +5105,12 @@ bfd_elfNN_loongarch_set_data_segment_info (struct bfd_link_info *info, + /* Implement R_LARCH_ALIGN by deleting excess alignment NOPs. + Once we've handled an R_LARCH_ALIGN, we can't relax anything else. */ + static bool +-loongarch_relax_align (bfd *abfd, asection *sec, +- asection *sym_sec, +- struct bfd_link_info *link_info, ++loongarch_relax_align (bfd *abfd, asection *sec, asection *sym_sec, + Elf_Internal_Rela *rel, +- bfd_vma symval) ++ bfd_vma symval ATTRIBUTE_UNUSED, ++ struct bfd_link_info *link_info, ++ bool *again ATTRIBUTE_UNUSED, ++ bfd_vma max_alignment ATTRIBUTE_UNUSED) + { + bfd_vma addend, max = 0, alignment = 1; + +@@ -5198,9 +5198,6 @@ loongarch_relax_tls_ld_gd_desc (bfd *abfd, asection *sec, asection *sym_sec, + /* Is pcalau12i + addi.d insns? */ + if ((ELFNN_R_TYPE (rel_lo->r_info) != R_LARCH_GOT_PC_LO12 + && ELFNN_R_TYPE (rel_lo->r_info) != R_LARCH_TLS_DESC_PC_LO12) +- || (ELFNN_R_TYPE ((rel_lo + 1)->r_info) != R_LARCH_RELAX) +- || (ELFNN_R_TYPE ((rel_hi + 1)->r_info) != R_LARCH_RELAX) +- || (rel_hi->r_offset + 4 != rel_lo->r_offset) + || !LARCH_INSN_ADDI_D(add) + /* Is pcalau12i $rd + addi.d $rd,$rd? */ + || (LARCH_GET_RD(add) != rd) +@@ -5257,12 +5254,18 @@ loongarch_get_max_alignment (asection *sec) + return (bfd_vma) 1 << max_alignment_power; + } + ++typedef bool (*relax_func_t) (bfd *, asection *, asection *, ++ Elf_Internal_Rela *, bfd_vma, ++ struct bfd_link_info *, bool *, ++ bfd_vma); ++ + static bool + loongarch_elf_relax_section (bfd *abfd, asection *sec, + struct bfd_link_info *info, + bool *again) + { + *again = false; ++ + if (!is_elf_hash_table (info->hash) + || elf_hash_table_id (elf_hash_table (info)) != LARCH_ELF_DATA) + return true; +@@ -5277,13 +5280,13 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, + + if (bfd_link_relocatable (info) + || sec->sec_flg0 +- || (sec->flags & SEC_RELOC) == 0 + || sec->reloc_count == 0 ++ || (sec->flags & SEC_RELOC) == 0 ++ || (sec->flags & SEC_HAS_CONTENTS) == 0 ++ /* The exp_seg_relro_adjust is enum phase_enum (0x4). */ ++ || *(htab->data_segment_phase) == 4 + || (info->disable_target_specific_optimizations +- && info->relax_pass == 0) +- /* The exp_seg_relro_adjust is enum phase_enum (0x4), +- and defined in ld/ldexp.h. */ +- || *(htab->data_segment_phase) == 4) ++ && info->relax_pass == 0)) + return true; + + struct bfd_elf_section_data *data = elf_section_data (sec); +@@ -5293,11 +5296,14 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, + else if (!(relocs = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, + info->keep_memory))) + return true; ++ data->relocs = relocs; + ++ /* Read this BFD's contents if we haven't done so already. */ + if (!data->this_hdr.contents + && !bfd_malloc_and_get_section (abfd, sec, &data->this_hdr.contents)) + return true; + ++ /* Read this BFD's symbols if we haven't done so already. */ + Elf_Internal_Shdr *symtab_hdr = &elf_symtab_hdr (abfd); + if (symtab_hdr->sh_info != 0 + && !symtab_hdr->contents +@@ -5307,8 +5313,6 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, + 0, NULL, NULL, NULL))) + return true; + +- data->relocs = relocs; +- + /* Estimate the maximum alignment for all output sections once time + should be enough. */ + bfd_vma max_alignment = htab->max_alignment; +@@ -5330,6 +5334,93 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, + unsigned long r_type = ELFNN_R_TYPE (rel->r_info); + unsigned long r_symndx = ELFNN_R_SYM (rel->r_info); + ++ if (r_symndx >= symtab_hdr->sh_info) ++ { ++ h = elf_sym_hashes (abfd)r_symndx - symtab_hdr->sh_info; ++ while (h->root.type == bfd_link_hash_indirect ++ || h->root.type == bfd_link_hash_warning) ++ h = (struct elf_link_hash_entry *) h->root.u.i.link; ++ } ++ ++ /* If the conditions for tls type transition are met, type ++ transition is performed instead of relax. ++ During the transition from DESC->IE/LE, there are 2 situations ++ depending on the different configurations of the relax/norelax ++ option. ++ If the -relax option is used, the extra nops will be removed,
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_service:tar_scm:LoongArch-Reject-R_LARCH_32-from-becoming-a-runtime-.patch
Added
@@ -0,0 +1,132 @@ +From b1375201b1643fee97a240ba17523a529b286e12 Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao <xry111@xry111.site> +Date: Sun, 30 Jun 2024 15:18:21 +0800 +Subject: PATCH 095/123 LoongArch: Reject R_LARCH_32 from becoming a runtime + reloc in ELFCLASS64 + +We were converting R_LARCH_32 to R_LARCH_RELATIVE for ELFCLASS64: + + $ cat t.s + .data + x: + .4byte x + .4byte 0xdeadbeef + $ as/as-new t.s -o t.o + $ ld/ld-new -shared t.o + $ objdump -R + a.out: file format elf64-loongarch + + DYNAMIC RELOCATION RECORDS + OFFSET TYPE VALUE + 00000000000001a8 R_LARCH_RELATIVE *ABS*+0x00000000000001a8 + +But this is just wrong: at runtime the dynamic linker will run +*(uintptr *)&x += load_address, clobbering the next 4 bytes of data +("0xdeadbeef" in the example). + +If we keep the R_LARCH_32 reloc as-is in ELFCLASS64, it'll be rejected +by the Glibc dynamic linker anyway. And it does not make too much sense +to modify Glibc to support it. So we can just reject it like x86_64: + + relocation R_X86_64_32 against `.data' can not be used when making a + shared object; recompile with -fPIC + +or RISC-V: + + relocation R_RISCV_32 against non-absolute symbol `a local symbol' + can not be used in RV64 when making a shared object + +Signed-off-by: Xi Ruoyao <xry111@xry111.site> +--- + bfd/elfnn-loongarch.c | 30 +++++++++++++++++-- + .../ld-loongarch-elf/ld-loongarch-elf.exp | 1 + + .../ld-loongarch-elf/r_larch_32_elf64.d | 4 +++ + .../ld-loongarch-elf/r_larch_32_elf64.s | 3 ++ + 4 files changed, 36 insertions(+), 2 deletions(-) + create mode 100644 ld/testsuite/ld-loongarch-elf/r_larch_32_elf64.d + create mode 100644 ld/testsuite/ld-loongarch-elf/r_larch_32_elf64.s + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index 840cdd35..fa0a5e38 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -1036,8 +1036,32 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, + only_need_pcrel = 1; + break; + +- case R_LARCH_JUMP_SLOT: + case R_LARCH_32: ++ if (ARCH_SIZE > 32 ++ && bfd_link_pic (info) ++ && (sec->flags & SEC_ALLOC) != 0) ++ { ++ bool is_abs_symbol = false; ++ ++ if (r_symndx < symtab_hdr->sh_info) ++ is_abs_symbol = isym->st_shndx == SHN_ABS; ++ else ++ is_abs_symbol = bfd_is_abs_symbol (&h->root); ++ ++ if (!is_abs_symbol) ++ { ++ _bfd_error_handler ++ (_("%pB: relocation R_LARCH_32 against non-absolute " ++ "symbol `%s' cannot be used in ELFCLASS64 when " ++ "making a shared object or PIE"), ++ abfd, h ? h->root.root.string : "a local symbol"); ++ bfd_set_error (bfd_error_bad_value); ++ return false; ++ } ++ } ++ ++ /* Fall through. */ ++ case R_LARCH_JUMP_SLOT: + case R_LARCH_64: + + need_dynreloc = 1; +@@ -2858,8 +2882,10 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, + outrel.r_addend = relocation + rel->r_addend; + } + +- /* No alloc space of func allocate_dynrelocs. */ ++ /* No alloc space of func allocate_dynrelocs. ++ No alloc space of invalid R_LARCH_32 in ELFCLASS64. */ + if (unresolved_reloc ++ && (ARCH_SIZE == 32 || r_type != R_LARCH_32) + && !(h && (h->is_weakalias || !h->dyn_relocs))) + loongarch_elf_append_rela (output_bfd, sreloc, &outrel); + } +diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp +index 89552a11..7ffabe2c 100644 +--- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp ++++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp +@@ -132,6 +132,7 @@ if istarget "loongarch64-*-*" { + run_dump_test "reloc_le_with_shared" + run_dump_test "reloc_ler_with_shared" + run_dump_test "reloc_abs_with_shared" ++ run_dump_test "r_larch_32_elf64" + } + + if check_pie_support { +diff --git a/ld/testsuite/ld-loongarch-elf/r_larch_32_elf64.d b/ld/testsuite/ld-loongarch-elf/r_larch_32_elf64.d +new file mode 100644 +index 00000000..34313295 +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/r_larch_32_elf64.d +@@ -0,0 +1,4 @@ ++#name: R_LARCH_32 in ELFCLASS64 ++#source: r_larch_32_elf64.s ++#ld: -shared -melf64loongarch ++#error: R_LARCH_32 .* cannot be used in ELFCLASS64 +diff --git a/ld/testsuite/ld-loongarch-elf/r_larch_32_elf64.s b/ld/testsuite/ld-loongarch-elf/r_larch_32_elf64.s +new file mode 100644 +index 00000000..6649f2bc +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/r_larch_32_elf64.s +@@ -0,0 +1,3 @@ ++.data ++x: ++ .4byte x +-- +2.33.0 +
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_service:tar_scm:LoongArch-Remove-unused-code-in-ld-test-suite.patch
Added
@@ -0,0 +1,45 @@ +From a88594951ad3b0657d8e6139c3fde63e7a771b12 Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao <xry111@xry111.site> +Date: Sat, 22 Jun 2024 18:06:47 +0800 +Subject: PATCH 094/123 LoongArch: Remove unused code in ld test suite + +These seems some left over from MIPS code and they do not make any +sense for LoongArch. + +Signed-off-by: Xi Ruoyao <xry111@xry111.site> +--- + ld/testsuite/ld-loongarch-elf/anno-sym.d | 2 -- + ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp | 7 ------- + 2 files changed, 9 deletions(-) + +diff --git a/ld/testsuite/ld-loongarch-elf/anno-sym.d b/ld/testsuite/ld-loongarch-elf/anno-sym.d +index a58f4a6c..6d2149f0 100644 +--- a/ld/testsuite/ld-loongarch-elf/anno-sym.d ++++ b/ld/testsuite/ld-loongarch-elf/anno-sym.d +@@ -3,5 +3,3 @@ + #as: -mno-relax + #ld: -e _start + #error_output: anno-sym.l +-# The mips-irix6 target fails this test because it does not find any function symbols. Not sure why. +-#skip: *-*-irix* +diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp +index 5d109a4d..89552a11 100644 +--- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp ++++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp +@@ -19,13 +19,6 @@ + # MA 02110-1301, USA. + # + +-proc loongarch_choose_lp64_emul {} { +- if { istarget "loongarch64be-*" } { +- return "elf64bloongarch" +- } +- return "elf64lloongarch" +-} +- + if istarget "loongarch64-*-*" { + run_dump_test "jmp_op" + run_dump_test "macro_op" +-- +2.33.0 +
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_service:tar_scm:LoongArch-Run-overflow-testcases-only-on-LoongArch-t.patch
Added
@@ -0,0 +1,50 @@ +From 070b9a5e5d1a0864a8e9971cefd4b0e73637e783 Mon Sep 17 00:00:00 2001 +From: mengqinggang <mengqinggang@loongson.cn> +Date: Tue, 27 Feb 2024 15:12:14 +0800 +Subject: PATCH 061/123 LoongArch: Run overflow testcases only on LoongArch + target + +--- + .../ld-loongarch-elf/ld-loongarch-elf.exp | 27 ++++++++++--------- + 1 file changed, 14 insertions(+), 13 deletions(-) + +diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp +index b3029e53..7dca8218 100644 +--- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp ++++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp +@@ -133,18 +133,19 @@ if istarget "loongarch64-*-*" { + run_dump_test "desc-norelax" + run_dump_test "desc-relax" + } ++ ++ run_dump_test "max_imm_b16" ++ run_dump_test "max_imm_b21" ++ run_dump_test "max_imm_b26" ++ run_dump_test "max_imm_pcrel20" ++ run_dump_test "overflow_b16" ++ run_dump_test "overflow_b21" ++ run_dump_test "overflow_b26" ++ run_dump_test "overflow_pcrel20" ++ run_dump_test "underflow_b16" ++ run_dump_test "underflow_b21" ++ run_dump_test "underflow_b26" ++ run_dump_test "underflow_pcrel20" ++ run_dump_test "pie_discard" + } + +-run_dump_test "max_imm_b16" +-run_dump_test "max_imm_b21" +-run_dump_test "max_imm_b26" +-run_dump_test "max_imm_pcrel20" +-run_dump_test "overflow_b16" +-run_dump_test "overflow_b21" +-run_dump_test "overflow_b26" +-run_dump_test "overflow_pcrel20" +-run_dump_test "underflow_b16" +-run_dump_test "underflow_b21" +-run_dump_test "underflow_b26" +-run_dump_test "underflow_pcrel20" +-run_dump_test "pie_discard" +-- +2.33.0 +
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_service:tar_scm:LoongArch-Scan-all-illegal-operand-instructions-with.patch
Added
@@ -0,0 +1,381 @@ +From e3cee667f81d7f7982f4a9f75370415b00e9cff6 Mon Sep 17 00:00:00 2001 +From: Lulu Cai <cailulu@loongson.cn> +Date: Sat, 2 Mar 2024 10:47:42 +0800 +Subject: PATCH 073/123 LoongArch: Scan all illegal operand instructions + without interruption + +Currently, gas will exit immediately and report an error when +it sees illegal operands, and will not process the remaining +instructions. Replace as_fatal with as_bad to check for all +illegal operands. + +Add test cases for illegal operands of some instructions. +--- + gas/config/tc-loongarch.c | 11 +- + .../gas/loongarch/check_bstrins-pick.d | 18 +++ + .../gas/loongarch/check_bstrins-pick.s | 9 ++ + gas/testsuite/gas/loongarch/illegal-operand.l | 113 +++++++++++++++++ + gas/testsuite/gas/loongarch/illegal-operand.s | 117 ++++++++++++++++++ + gas/testsuite/gas/loongarch/loongarch.exp | 4 + + gas/testsuite/gas/loongarch/lvz-lbt.d | 2 +- + gas/testsuite/gas/loongarch/lvz-lbt.s | 2 +- + 8 files changed, 269 insertions(+), 7 deletions(-) + create mode 100644 gas/testsuite/gas/loongarch/check_bstrins-pick.d + create mode 100644 gas/testsuite/gas/loongarch/check_bstrins-pick.s + create mode 100644 gas/testsuite/gas/loongarch/illegal-operand.l + create mode 100644 gas/testsuite/gas/loongarch/illegal-operand.s + +diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c +index b510d228..ff126d56 100644 +--- a/gas/config/tc-loongarch.c ++++ b/gas/config/tc-loongarch.c +@@ -958,8 +958,8 @@ check_this_insn_before_appending (struct loongarch_cl_insn *ip) + /* For AMO insn amswap.wd, amadd.wd, etc. */ + if (ip->args0 != 0 + && (ip->args0 == ip->args1 || ip->args0 == ip->args2)) +- as_fatal (_("AMO insns require rd != base && rd != rt" +- " when rd isn't $r0")); ++ as_bad (_("automic memory operations insns require rd != rj" ++ " && rd != rk when rd isn't r0")); + } + else if ((ip->insn->mask == 0xffe08000 + /* bstrins.w rd, rj, msbw, lsbw */ +@@ -970,12 +970,13 @@ check_this_insn_before_appending (struct loongarch_cl_insn *ip) + { + /* For bstr(ins|pick).wd. */ + if (ip->args2 < ip->args3) +- as_fatal (_("bstr(ins|pick).wd require msbd >= lsbd")); ++ as_bad (_("bstr(ins|pick).wd require msbd >= lsbd")); + } + else if (ip->insn->mask != 0 && (ip->insn_bin & 0xfe0003c0) == 0x04000000 + /* csrxchg rd, rj, csr_num */ +- && (strcmp ("csrxchg", ip->name) == 0)) +- as_fatal (_("csrxchg require rj != $r0 && rj != $r1")); ++ && (strcmp ("csrxchg", ip->name) == 0 ++ || strcmp ("gcsrxchg", ip->name) == 0)) ++ as_bad (_("g?csrxchg require rj != r0 && rj != r1")); + + return ret; + } +diff --git a/gas/testsuite/gas/loongarch/check_bstrins-pick.d b/gas/testsuite/gas/loongarch/check_bstrins-pick.d +new file mode 100644 +index 00000000..7575be19 +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/check_bstrins-pick.d +@@ -0,0 +1,18 @@ ++#as: ++#objdump: -d ++#skip: loongarch32-*-* ++ ++.*: +file format .* ++ ++ ++Disassembly of section .text: ++ ++0+ <.*>: ++ 0: 00682041 bstrins\.w \$ra, \$tp, 0x8, 0x8 ++ 4: 00882041 bstrins\.d \$ra, \$tp, 0x8, 0x8 ++ 8: 0068a041 bstrpick\.w \$ra, \$tp, 0x8, 0x8 ++ c: 00c82041 bstrpick\.d \$ra, \$tp, 0x8, 0x8 ++ 10: 00680041 bstrins\.w \$ra, \$tp, 0x8, 0x0 ++ 14: 00880041 bstrins\.d \$ra, \$tp, 0x8, 0x0 ++ 18: 00688041 bstrpick\.w \$ra, \$tp, 0x8, 0x0 ++ 1c: 00c80041 bstrpick\.d \$ra, \$tp, 0x8, 0x0 +diff --git a/gas/testsuite/gas/loongarch/check_bstrins-pick.s b/gas/testsuite/gas/loongarch/check_bstrins-pick.s +new file mode 100644 +index 00000000..0decaf98 +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/check_bstrins-pick.s +@@ -0,0 +1,9 @@ ++bstrins.w $r1,$r2,8,8 ++bstrins.d $r1,$r2,8,8 ++bstrpick.w $r1,$r2,8,8 ++bstrpick.d $r1,$r2,8,8 ++ ++bstrins.w $r1,$r2,8,0 ++bstrins.d $r1,$r2,8,0 ++bstrpick.w $r1,$r2,8,0 ++bstrpick.d $r1,$r2,8,0 +diff --git a/gas/testsuite/gas/loongarch/illegal-operand.l b/gas/testsuite/gas/loongarch/illegal-operand.l +new file mode 100644 +index 00000000..dddc6d6f +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/illegal-operand.l +@@ -0,0 +1,113 @@ ++.*: Assembler messages: ++.*:2: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:3: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:4: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:5: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:6: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:7: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:8: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:9: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:10: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:11: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:12: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:13: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:14: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:15: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:16: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:17: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:18: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:19: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:20: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:21: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:22: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:23: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:24: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:25: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:26: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:27: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:28: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:29: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:30: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:31: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:32: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:33: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:34: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:35: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:36: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:37: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:38: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:39: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:40: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:41: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:42: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:43: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:44: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:45: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:46: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:47: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:48: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:49: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:50: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:51: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:52: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:53: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:54: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:55: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:56: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:57: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:58: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:59: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:60: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:61: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:62: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:63: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:64: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:65: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:66: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:67: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:68: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:69: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:70: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:71: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:72: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:73: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:74: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:75: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:76: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:77: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:78: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:79: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:80: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:81: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:82: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:83: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:84: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:85: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:86: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:87: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:88: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:89: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:90: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:91: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:92: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:93: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:94: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 ++.*:95: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0
View file
_service:tar_scm:LoongArch-TLS-IE-needs-only-one-dynamic-reloc.patch
Added
@@ -0,0 +1,201 @@ +From 35938863d51f469f5bc715b3a7aa6f2a0eb150a6 Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao <xry111@xry111.site> +Date: Wed, 19 Jun 2024 14:04:18 +0800 +Subject: PATCH 092/123 LoongArch: TLS IE needs only one dynamic reloc + +As the comment in the code says, TLS_IE needs only one dynamic reloc. +But commit b67a17aa7c0c ("LoongArch: Fix the issue of excessive +relocation generated by GD and IE") has incorrectly allocated the space +for two dynamic relocs, causing libc.so to contain 8 R_LARCH_NONE. + +Adjust tlsdesc-dso.d for the offset changes and add two tests to ensure +there are no R_LARCH_NONE with TLS. + +Signed-off-by: Xi Ruoyao <xry111@xry111.site> +--- + bfd/elfnn-loongarch.c | 2 +- + ld/testsuite/ld-loongarch-elf/desc-ie-reloc.d | 9 ++ + ld/testsuite/ld-loongarch-elf/desc-ie.d | 8 +- + .../ld-loongarch-elf/ld-loongarch-elf.exp | 2 + + .../ld-loongarch-elf/tlsdesc-dso-reloc.d | 9 ++ + ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d | 86 +++++++++---------- + 6 files changed, 68 insertions(+), 48 deletions(-) + create mode 100644 ld/testsuite/ld-loongarch-elf/desc-ie-reloc.d + create mode 100644 ld/testsuite/ld-loongarch-elf/tlsdesc-dso-reloc.d + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index 9eaad7f4..51e3d311 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -1353,7 +1353,7 @@ allocate_dynrelocs (struct elf_link_hash_entry *h, void *inf) + { + s->size += GOT_ENTRY_SIZE; + if (need_reloc) +- htab->elf.srelgot->size += 2 * sizeof (ElfNN_External_Rela); ++ htab->elf.srelgot->size += sizeof (ElfNN_External_Rela); + } + + /* TLS_DESC needs one dynamic reloc and two GOT slot. */ +diff --git a/ld/testsuite/ld-loongarch-elf/desc-ie-reloc.d b/ld/testsuite/ld-loongarch-elf/desc-ie-reloc.d +new file mode 100644 +index 00000000..c7a2f8ed +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/desc-ie-reloc.d +@@ -0,0 +1,9 @@ ++#source: desc-ie.s ++#as: ++#ld: -shared -z norelro --hash-style=both ++#readelf: -Wr ++ ++#failif ++#... ++.* +R_LARCH_NONE +.* ++#... +diff --git a/ld/testsuite/ld-loongarch-elf/desc-ie.d b/ld/testsuite/ld-loongarch-elf/desc-ie.d +index c833b233..0759404b 100644 +--- a/ld/testsuite/ld-loongarch-elf/desc-ie.d ++++ b/ld/testsuite/ld-loongarch-elf/desc-ie.d +@@ -8,7 +8,7 @@ + Disassembly of section .text: + + 0-9a-f+ <fn1>: +- +0-9a-f+: 1a000084 pcalau12i \$a0, .* +- +0-9a-f+: 28cd0084 ld.d \$a0, \$a0, .* +- +0-9a-f+: 1a000084 pcalau12i \$a0, .* +- +0-9a-f+: 28cd0084 ld.d \$a0, \$a0, .* ++ +0-9a-f+: 0-9a-f+ pcalau12i \$a0, .* ++ +0-9a-f+: 0-9a-f+ ld.d \$a0, \$a0, .* ++ +0-9a-f+: 0-9a-f+ pcalau12i \$a0, .* ++ +0-9a-f+: 0-9a-f+ ld.d \$a0, \$a0, .* +diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp +index 3c8e9195..5d109a4d 100644 +--- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp ++++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp +@@ -130,7 +130,9 @@ if istarget "loongarch64-*-*" { + if istarget "loongarch64-*-*" { + if check_shared_lib_support { + run_dump_test "desc-ie" ++ run_dump_test "desc-ie-reloc" + run_dump_test "tlsdesc-dso" ++ run_dump_test "tlsdesc-dso-reloc" + run_dump_test "desc-norelax" + run_dump_test "desc-relax" + run_dump_test "data-got" +diff --git a/ld/testsuite/ld-loongarch-elf/tlsdesc-dso-reloc.d b/ld/testsuite/ld-loongarch-elf/tlsdesc-dso-reloc.d +new file mode 100644 +index 00000000..d5afa7c3 +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/tlsdesc-dso-reloc.d +@@ -0,0 +1,9 @@ ++#source: tlsdesc-dso.s ++#as: ++#ld: -shared -z norelro --hash-style=both ++#readelf: -Wr ++ ++#failif ++#... ++.* +R_LARCH_NONE +.* ++#... +diff --git a/ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d b/ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d +index 8f66302f..d6997ec9 100644 +--- a/ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d ++++ b/ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d +@@ -9,52 +9,52 @@ + Disassembly of section .text: + + 0-9a-f+ <fun_gl1>: +- +0-9a-f+: 18021584 pcaddi \$a0, 4268 +- +0-9a-f+: 1a000084 pcalau12i \$a0, 4 +- +0-9a-f+: 28dd4084 ld.d \$a0, \$a0, 1872 +- +0-9a-f+: 18021364 pcaddi \$a0, 4251 +- +0-9a-f+: 180213c4 pcaddi \$a0, 4254 +- +0-9a-f+: 28c00081 ld.d \$ra, \$a0, 0 +- +0-9a-f+: 4c000021 jirl \$ra, \$ra, 0 +- +0-9a-f+: 1a000084 pcalau12i \$a0, 4 +- +0-9a-f+: 28dc0084 ld.d \$a0, \$a0, 1792 +- +0-9a-f+: 1a000084 pcalau12i \$a0, 4 +- +0-9a-f+: 28dc0084 ld.d \$a0, \$a0, 1792 +- +0-9a-f+: 18021364 pcaddi \$a0, 4251 +- +0-9a-f+: 180213c4 pcaddi \$a0, 4254 +- +0-9a-f+: 28c00081 ld.d \$ra, \$a0, 0 +- +0-9a-f+: 4c000021 jirl \$ra, \$ra, 0 +- +0-9a-f+: 1a000084 pcalau12i \$a0, 4 +- +0-9a-f+: 28dce084 ld.d \$a0, \$a0, 1848 ++ +0-9a-f+: 0-9a-f+ pcaddi \$a0, .* ++ +0-9a-f+: 0-9a-f+ pcalau12i \$a0, .* ++ +0-9a-f+: 0-9a-f+ ld.d \$a0, \$a0, .* ++ +0-9a-f+: 0-9a-f+ pcaddi \$a0, .* ++ +0-9a-f+: 0-9a-f+ pcaddi \$a0, .* ++ +0-9a-f+: 0-9a-f+ ld.d \$ra, \$a0, .* ++ +0-9a-f+: 0-9a-f+ jirl \$ra, \$ra, .* ++ +0-9a-f+: 0-9a-f+ pcalau12i \$a0, .* ++ +0-9a-f+: 0-9a-f+ ld.d \$a0, \$a0, .* ++ +0-9a-f+: 0-9a-f+ pcalau12i \$a0, .* ++ +0-9a-f+: 0-9a-f+ ld.d \$a0, \$a0, .* ++ +0-9a-f+: 0-9a-f+ pcaddi \$a0, .* ++ +0-9a-f+: 0-9a-f+ pcaddi \$a0, .* ++ +0-9a-f+: 0-9a-f+ ld.d \$ra, \$a0, .* ++ +0-9a-f+: 0-9a-f+ jirl \$ra, \$ra, .* ++ +0-9a-f+: 0-9a-f+ pcalau12i \$a0, .* ++ +0-9a-f+: 0-9a-f+ ld.d \$a0, \$a0, .* + + 0-9a-f+ <fun_lo>: +- +0-9a-f+: 1a000084 pcalau12i \$a0, 4 +- +0-9a-f+: 28daa084 ld.d \$a0, \$a0, 1704 +- +0-9a-f+: 18020de4 pcaddi \$a0, 4207 +- +0-9a-f+: 18020f04 pcaddi \$a0, 4216 +- +0-9a-f+: 28c00081 ld.d \$ra, \$a0, 0 +- +0-9a-f+: 4c000021 jirl \$ra, \$ra, 0 +- +0-9a-f+: 18020e24 pcaddi \$a0, 4209 +- +0-9a-f+: 1a000084 pcalau12i \$a0, 4 +- +0-9a-f+: 28db4084 ld.d \$a0, \$a0, 1744 +- +0-9a-f+: 1a000084 pcalau12i \$a0, 4 +- +0-9a-f+: 28db4084 ld.d \$a0, \$a0, 1744 +- +0-9a-f+: 18020f44 pcaddi \$a0, 4218 +- +0-9a-f+: 28c00081 ld.d \$ra, \$a0, 0 +- +0-9a-f+: 4c000021 jirl \$ra, \$ra, 0 +- +0-9a-f+: 18020e64 pcaddi \$a0, 4211 +- +0-9a-f+: 1a000084 pcalau12i \$a0, 4 +- +0-9a-f+: 28dba084 ld.d \$a0, \$a0, 1768 ++ +0-9a-f+: 0-9a-f+ pcalau12i \$a0, .* ++ +0-9a-f+: 0-9a-f+ ld.d \$a0, \$a0, .* ++ +0-9a-f+: 0-9a-f+ pcaddi \$a0, .* ++ +0-9a-f+: 0-9a-f+ pcaddi \$a0, .* ++ +0-9a-f+: 0-9a-f+ ld.d \$ra, \$a0, .* ++ +0-9a-f+: 0-9a-f+ jirl \$ra, \$ra, .* ++ +0-9a-f+: 0-9a-f+ pcaddi \$a0, .* ++ +0-9a-f+: 0-9a-f+ pcalau12i \$a0, .* ++ +0-9a-f+: 0-9a-f+ ld.d \$a0, \$a0, .* ++ +0-9a-f+: 0-9a-f+ pcalau12i \$a0, .* ++ +0-9a-f+: 0-9a-f+ ld.d \$a0, \$a0, .* ++ +0-9a-f+: 0-9a-f+ pcaddi \$a0, .* ++ +0-9a-f+: 0-9a-f+ ld.d \$ra, \$a0, .* ++ +0-9a-f+: 0-9a-f+ jirl \$ra, \$ra, .* ++ +0-9a-f+: 0-9a-f+ pcaddi \$a0, .* ++ +0-9a-f+: 0-9a-f+ pcalau12i \$a0, .* ++ +0-9a-f+: 0-9a-f+ ld.d \$a0, \$a0, .* + + 0-9a-f+ <fun_external>: +- +0-9a-f+: 18020ec4 pcaddi \$a0, 4214 +- +0-9a-f+: 28c00081 ld.d \$ra, \$a0, 0 +- +0-9a-f+: 4c000021 jirl \$ra, \$ra, 0 ++ +0-9a-f+: 0-9a-f+ pcaddi \$a0, .* ++ +0-9a-f+: 0-9a-f+ ld.d \$ra, \$a0, .* ++ +0-9a-f+: 0-9a-f+ jirl \$ra, \$ra, .* + + 0-9a-f+ <fun_hidden>: +- +0-9a-f+: 18021224 pcaddi \$a0, 4241 +- +0-9a-f+: 28c00081 ld.d \$ra, \$a0, 0 +- +0-9a-f+: 4c000021 jirl \$ra, \$ra, 0 +- +0-9a-f+: 18021144 pcaddi \$a0, 4234 +- +0-9a-f+: 28c00081 ld.d \$ra, \$a0, 0 +- +0-9a-f+: 4c000021 jirl \$ra, \$ra, 0 ++ +0-9a-f+: 0-9a-f+ pcaddi \$a0, .* ++ +0-9a-f+: 0-9a-f+ ld.d \$ra, \$a0, .* ++ +0-9a-f+: 0-9a-f+ jirl \$ra, \$ra, .* ++ +0-9a-f+: 0-9a-f+ pcaddi \$a0, .* ++ +0-9a-f+: 0-9a-f+ ld.d \$ra, \$a0, .* ++ +0-9a-f+: 0-9a-f+ jirl \$ra, \$ra, .* +--
View file
_service:tar_scm:LoongArch-The-symbol-got-type-can-only-be-obtained-a.patch
Added
@@ -0,0 +1,37 @@ +From 6f250e80b7445f58291c273adf8fa03c65939b43 Mon Sep 17 00:00:00 2001 +From: Lulu Cai <cailulu@loongson.cn> +Date: Fri, 19 Apr 2024 10:24:52 +0800 +Subject: PATCH 081/123 LoongArch: The symbol got type can only be obtained + after initialization + +When scanning relocations and determining whether TLS type transition is +possible, it will try to obtain the symbol got type. If the symbol got +type record has not yet been allocated space and initialized, it will +cause ld to crash. So when uninitialized, the symbol is set to GOT_UNKNOWN. +--- + bfd/elfnn-loongarch.c | 9 ++++++++- + 1 file changed, 8 insertions(+), 1 deletion(-) + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index 70ef28f3..0a7caa2a 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -683,7 +683,14 @@ loongarch_can_trans_tls (bfd *input_bfd, + if (! IS_LOONGARCH_TLS_TRANS_RELOC (r_type)) + return false; + +- symbol_tls_type = _bfd_loongarch_elf_tls_type (input_bfd, h, r_symndx); ++ /* Obtaining tls got type here may occur before ++ loongarch_elf_record_tls_and_got_reference, so it is necessary ++ to ensure that tls got type has been initialized, otherwise it ++ is set to GOT_UNKNOWN. */ ++ symbol_tls_type = GOT_UNKNOWN; ++ if (_bfd_loongarch_elf_local_got_tls_type (input_bfd) || h) ++ symbol_tls_type = _bfd_loongarch_elf_tls_type (input_bfd, h, r_symndx); ++ + reloc_got_type = loongarch_reloc_got_type (r_type); + + if (symbol_tls_type == GOT_TLS_IE && GOT_TLS_GD_ANY_P (reloc_got_type)) +-- +2.33.0 +
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_service:tar_scm:LoongArch-Use-tab-to-indent-assembly-in-TLSDESC-test.patch
Added
@@ -0,0 +1,43 @@ +From 6f1158c052786ad574d6fdb34db4e1e5ddf90309 Mon Sep 17 00:00:00 2001 +From: Tatsuyuki Ishi <ishitatsuyuki@gmail.com> +Date: Thu, 28 Dec 2023 23:58:01 +0900 +Subject: PATCH 046/123 LoongArch: Use tab to indent assembly in TLSDESC test + suite + +The usual convention is to use tabs. Not all test are following this, +but at least when using tabs, let's use it consistently throughout the +file. +--- + gas/testsuite/gas/loongarch/tlsdesc_32.s | 2 +- + gas/testsuite/gas/loongarch/tlsdesc_64.s | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/gas/testsuite/gas/loongarch/tlsdesc_32.s b/gas/testsuite/gas/loongarch/tlsdesc_32.s +index ef6aee94..2a139c04 100644 +--- a/gas/testsuite/gas/loongarch/tlsdesc_32.s ++++ b/gas/testsuite/gas/loongarch/tlsdesc_32.s +@@ -4,7 +4,7 @@ + # R_LARCH_TLS_DESC_PC_LO12 var + addi.w $a0,$a0,%desc_pc_lo12(var) + # R_LARCH_TLS_DESC_LD var +- ld.w $ra,$a0,%desc_ld(var) ++ ld.w $ra,$a0,%desc_ld(var) + # R_LARCH_TLS_DESC_CALL var + jirl $ra,$ra,%desc_call(var) + +diff --git a/gas/testsuite/gas/loongarch/tlsdesc_64.s b/gas/testsuite/gas/loongarch/tlsdesc_64.s +index 9d0ccb17..9850940e 100644 +--- a/gas/testsuite/gas/loongarch/tlsdesc_64.s ++++ b/gas/testsuite/gas/loongarch/tlsdesc_64.s +@@ -4,7 +4,7 @@ + # R_LARCH_TLS_DESC_PC_LO12 var + addi.d $a0,$a0,%desc_pc_lo12(var) + # R_LARCH_TLS_DESC_LD var +- ld.d $ra,$a0,%desc_ld(var) ++ ld.d $ra,$a0,%desc_ld(var) + # R_LARCH_TLS_DESC_CALL var + jirl $ra,$ra,%desc_call(var) + +-- +2.33.0 +
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_service:tar_scm:LoongArch-add-.option-directive.patch
Added
@@ -0,0 +1,207 @@ +From fdb688f870f5d9078de4fe77a7d3fbed57df5b07 Mon Sep 17 00:00:00 2001 +From: Lulu Cai <cailulu@loongson.cn> +Date: Tue, 21 May 2024 10:14:27 +0800 +Subject: PATCH 091/123 LoongArch: add .option directive + +In some cases we may want to use different options only for certain +assembly, so the .option directive is added to control the assembler +options. + +.option can accept 4 parameters: + +push +pop + Pushes or pops the current option stack. They limit the scope of + option changes so that they do not affect other parts of the assembly + file. + +relax +norelax + Enables or disables relaxation. +--- + gas/config/tc-loongarch.c | 59 +++++++++++++++++++ + gas/testsuite/gas/loongarch/loongarch.exp | 1 + + .../gas/loongarch/pseudo_op_option.d | 36 +++++++++++ + .../gas/loongarch/pseudo_op_option.s | 19 ++++++ + .../gas/loongarch/pseudo_op_option_fail.l | 2 + + .../gas/loongarch/pseudo_op_option_fail.s | 2 + + 6 files changed, 119 insertions(+) + create mode 100644 gas/testsuite/gas/loongarch/pseudo_op_option.d + create mode 100644 gas/testsuite/gas/loongarch/pseudo_op_option.s + create mode 100644 gas/testsuite/gas/loongarch/pseudo_op_option_fail.l + create mode 100644 gas/testsuite/gas/loongarch/pseudo_op_option_fail.s + +diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c +index f039d027..72815233 100644 +--- a/gas/config/tc-loongarch.c ++++ b/gas/config/tc-loongarch.c +@@ -541,6 +541,64 @@ s_dtprel (int bytes) + demand_empty_rest_of_line (); + } + ++struct LARCH_option_stack ++{ ++ struct LARCH_option_stack *next; ++ struct loongarch_ASEs_option options; ++}; ++ ++static struct LARCH_option_stack *LARCH_opts_stack = NULL; ++ ++/* Handle the .option pseudo-op. ++ The alignment of .align is done by R_LARCH_ALIGN at link time. ++ If the .align directive is within the range controlled by ++ .option norelax, that is, relax is turned off, R_LARCH_ALIGN ++ cannot be generated, which may cause ld to be unable to handle ++ the alignment. */ ++static void ++s_loongarch_option (int x ATTRIBUTE_UNUSED) ++{ ++ char *name = input_line_pointer, ch; ++ while (!is_end_of_line(unsigned char) *input_line_pointer) ++ ++input_line_pointer; ++ ch = *input_line_pointer; ++ *input_line_pointer = '\0'; ++ ++ if (strcmp (name, "relax") == 0) ++ LARCH_opts.relax = 1; ++ else if (strcmp (name, "norelax") == 0) ++ LARCH_opts.relax = 0; ++ else if (strcmp (name, "push") == 0) ++ { ++ struct LARCH_option_stack *s; ++ ++ s = XNEW (struct LARCH_option_stack); ++ s->next = LARCH_opts_stack; ++ s->options = LARCH_opts; ++ LARCH_opts_stack = s; ++ } ++ else if (strcmp (name, "pop") == 0) ++ { ++ struct LARCH_option_stack *s; ++ ++ s = LARCH_opts_stack; ++ if (s == NULL) ++ as_bad (_(".option pop with no .option push")); ++ else ++ { ++ LARCH_opts_stack = s->next; ++ LARCH_opts = s->options; ++ free (s); ++ } ++ } ++ else ++ { ++ as_warn (_("unrecognized .option directive: %s"), name); ++ } ++ *input_line_pointer = ch; ++ demand_empty_rest_of_line (); ++} ++ + static const pseudo_typeS loongarch_pseudo_table = + { + { "dword", cons, 8 }, +@@ -548,6 +606,7 @@ static const pseudo_typeS loongarch_pseudo_table = + { "half", cons, 2 }, + { "dtprelword", s_dtprel, 4 }, + { "dtpreldword", s_dtprel, 8 }, ++ { "option", s_loongarch_option, 0}, + { NULL, NULL, 0 }, + }; + +diff --git a/gas/testsuite/gas/loongarch/loongarch.exp b/gas/testsuite/gas/loongarch/loongarch.exp +index a2ccfb13..157797c5 100644 +--- a/gas/testsuite/gas/loongarch/loongarch.exp ++++ b/gas/testsuite/gas/loongarch/loongarch.exp +@@ -35,5 +35,6 @@ if istarget loongarch*-*-* { + + if istarget loongarch64-*-* { + run_list_test "illegal-operand" ++ run_list_test "pseudo_op_option_fail" + } + } +diff --git a/gas/testsuite/gas/loongarch/pseudo_op_option.d b/gas/testsuite/gas/loongarch/pseudo_op_option.d +new file mode 100644 +index 00000000..53921a1e +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/pseudo_op_option.d +@@ -0,0 +1,36 @@ ++#as: -mrelax ++#objdump: -dr ++#skip: loongarch32-*-* ++ ++.*: file format .* ++ ++ ++Disassembly of section .text: ++ ++0.* <.text>: ++ 0: 1a000004 pcalau12i \$a0, 0 ++ 0: R_LARCH_PCALA_HI20 x ++ 0: R_LARCH_RELAX \*ABS\* ++ 4: 02c00084 addi.d \$a0, \$a0, 0 ++ 4: R_LARCH_PCALA_LO12 x ++ 4: R_LARCH_RELAX \*ABS\* ++ 8: 1a000004 pcalau12i \$a0, 0 ++ 8: R_LARCH_PCALA_HI20 x ++ c: 02c00084 addi.d \$a0, \$a0, 0 ++ c: R_LARCH_PCALA_LO12 x ++ 10: 1a000004 pcalau12i \$a0, 0 ++ 10: R_LARCH_PCALA_HI20 x ++ 10: R_LARCH_RELAX \*ABS\* ++ 14: 02c00084 addi.d \$a0, \$a0, 0 ++ 14: R_LARCH_PCALA_LO12 x ++ 14: R_LARCH_RELAX \*ABS\* ++ 18: 1a000004 pcalau12i \$a0, 0 ++ 18: R_LARCH_PCALA_HI20 x ++ 1c: 02c00084 addi.d \$a0, \$a0, 0 ++ 1c: R_LARCH_PCALA_LO12 x ++ 20: 1a000004 pcalau12i \$a0, 0 ++ 20: R_LARCH_PCALA_HI20 x ++ 20: R_LARCH_RELAX \*ABS\* ++ 24: 02c00084 addi.d \$a0, \$a0, 0 ++ 24: R_LARCH_PCALA_LO12 x ++ 24: R_LARCH_RELAX \*ABS\* +diff --git a/gas/testsuite/gas/loongarch/pseudo_op_option.s b/gas/testsuite/gas/loongarch/pseudo_op_option.s +new file mode 100644 +index 00000000..f21b7263 +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/pseudo_op_option.s +@@ -0,0 +1,19 @@ ++# Gas enables relax by default. ++# Push and pop can be nested, and each pop restores the options before ++# the most recent push. ++ .text ++.L1: ++ la.pcrel $a0,x ++ ++ .option push ++ .option norelax ++ la.pcrel $a0,x ++ ++ .option push ++ .option relax ++ la.pcrel $a0,x ++ .option pop ++ ++ la.pcrel $a0,x ++ .option pop ++ la.pcrel $a0,x +diff --git a/gas/testsuite/gas/loongarch/pseudo_op_option_fail.l b/gas/testsuite/gas/loongarch/pseudo_op_option_fail.l +new file mode 100644 +index 00000000..ffb9a72e +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/pseudo_op_option_fail.l +@@ -0,0 +1,2 @@ ++.*: Assembler messages: ++.*: Error: \.option pop with no \.option push +diff --git a/gas/testsuite/gas/loongarch/pseudo_op_option_fail.s b/gas/testsuite/gas/loongarch/pseudo_op_option_fail.s +new file mode 100644 +index 00000000..e368cdba
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_service:tar_scm:LoongArch-bfd-Add-support-for-tls-le-relax.patch
Added
@@ -0,0 +1,345 @@ +From 7bba42c3fe6dd98cf8f08fc13fcc246f4c7aee90 Mon Sep 17 00:00:00 2001 +From: changjiachen <changjiachen@stu.xupt.edu.cn> +Date: Thu, 28 Dec 2023 20:07:54 +0800 +Subject: PATCH 031/123 LoongArch: bfd: Add support for tls le relax. + +Add tls le relax support and related relocs in bfd. + +New relocation related explanation can refer to the following url: +https://github.com/loongson/la-abi-specs/blob/release/laelf.adoc + +This support does two main things: + +1. Implement support for three new relocation items in bfd. + +The three new relocation items are shown below: + +R_LARCH_TLS_LE_ADD_R +R_LARCH_TLS_LE_HI20_R +R_LARCH_TLS_LE_LO12_R + +2. ADD a new macro RELOCATE_TLS_TP32_HI20 + +Handle problems caused by symbol extensions in TLS LE, The processing +is similar to the macro RELOCATE_CALC_PC32_HI20 method. + +3. Implement the tls le relax function. + +bfd/ChangeLog: + + * bfd-in2.h: Add relocs related to tls le relax. + * elfnn-loongarch.c: + (loongarch_relax_tls_le): New function. + (RELOCATE_TLS_TP32_HI20): New macro. + (loongarch_elf_check_relocs): Add new reloc support. + (perform_relocation): Likewise. + (loongarch_elf_relocate_section): Handle new relocs related to relax. + (loongarch_elf_relax_section): Likewise. + * elfxx-loongarch.c: + (LOONGARCH_HOWTO (R_LARCH_TLS_LE_ADD_R)): New reloc how to type. + (LOONGARCH_HOWTO (R_LARCH_TLS_LE_HI20_R)): Likewise. + (LOONGARCH_HOWTO (R_LARCH_TLS_LE_LO12_R)): Likewise. + * libbfd.h: Add relocs related to tls le relax. + * reloc.c: Likewise. +--- + bfd/bfd-in2.h | 4 ++ + bfd/elfnn-loongarch.c | 105 ++++++++++++++++++++++++++++++++++++++++++ + bfd/elfxx-loongarch.c | 55 ++++++++++++++++++++-- + bfd/libbfd.h | 3 ++ + bfd/reloc.c | 7 +++ + 5 files changed, 169 insertions(+), 5 deletions(-) + +diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h +index d7b762d4..4e7ad048 100644 +--- a/bfd/bfd-in2.h ++++ b/bfd/bfd-in2.h +@@ -7356,11 +7356,15 @@ assembler and not (currently) written to any object files. */ + BFD_RELOC_LARCH_TLS_DESC64_HI12, + BFD_RELOC_LARCH_TLS_DESC_LD, + BFD_RELOC_LARCH_TLS_DESC_CALL, ++ BFD_RELOC_LARCH_TLS_LE_HI20_R, ++ BFD_RELOC_LARCH_TLS_LE_ADD_R, ++ BFD_RELOC_LARCH_TLS_LE_LO12_R, + BFD_RELOC_LARCH_TLS_LD_PCREL20_S2, + BFD_RELOC_LARCH_TLS_GD_PCREL20_S2, + BFD_RELOC_LARCH_TLS_DESC_PCREL20_S2, + BFD_RELOC_UNUSED + }; ++ + typedef enum bfd_reloc_code_real bfd_reloc_code_real_type; + + reloc_howto_type *bfd_reloc_type_lookup +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index d46bcd77..f7eb66da 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -858,6 +858,7 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, + break; + + case R_LARCH_TLS_LE_HI20: ++ case R_LARCH_TLS_LE_HI20_R: + case R_LARCH_SOP_PUSH_TLS_TPREL: + if (!bfd_link_executable (info)) + return false; +@@ -2261,6 +2262,8 @@ perform_relocation (const Elf_Internal_Rela *rel, asection *input_section, + case R_LARCH_GOT64_HI12: + case R_LARCH_TLS_LE_HI20: + case R_LARCH_TLS_LE_LO12: ++ case R_LARCH_TLS_LE_HI20_R: ++ case R_LARCH_TLS_LE_LO12_R: + case R_LARCH_TLS_LE64_LO20: + case R_LARCH_TLS_LE64_HI12: + case R_LARCH_TLS_IE_PC_HI20: +@@ -2303,6 +2306,7 @@ perform_relocation (const Elf_Internal_Rela *rel, asection *input_section, + break; + + case R_LARCH_RELAX: ++ case R_LARCH_TLS_LE_ADD_R: + break; + + default: +@@ -2483,6 +2487,16 @@ loongarch_reloc_is_fatal (struct bfd_link_info *info, + relocation += 0x1000; \ + }) + ++/* Handle problems caused by symbol extensions in TLS LE, The processing ++ is similar to the macro RELOCATE_CALC_PC32_HI20 method. */ ++#define RELOCATE_TLS_TP32_HI20(relocation) \ ++ ({ \ ++ bfd_vma __lo = (relocation) & ((bfd_vma)0xfff); \ ++ if (__lo > 0x7ff) \ ++ relocation += 0x800; \ ++ relocation = relocation & ~(bfd_vma)0xfff; \ ++ }) ++ + /* For example: pc is 0x11000010000100, symbol is 0x1812348ffff812 + offset = (0x1812348ffff812 & ~0xfff) - (0x11000010000100 & ~0xfff) + = 0x712347ffff000 +@@ -3474,6 +3488,13 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, + + break; + ++ case R_LARCH_TLS_LE_HI20_R: ++ relocation -= elf_hash_table (info)->tls_sec->vma; ++ ++ RELOCATE_TLS_TP32_HI20 (relocation); ++ ++ break; ++ + case R_LARCH_PCALA_LO12: + /* Not support if sym_addr in 2k page edge. + pcalau12i pc_hi20 (sym_addr) +@@ -3644,6 +3665,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, + + case R_LARCH_TLS_LE_HI20: + case R_LARCH_TLS_LE_LO12: ++ case R_LARCH_TLS_LE_LO12_R: + case R_LARCH_TLS_LE64_LO20: + case R_LARCH_TLS_LE64_HI12: + BFD_ASSERT (resolved_local && elf_hash_table (info)->tls_sec); +@@ -4082,6 +4104,82 @@ loongarch_relax_delete_bytes (bfd *abfd, + + return true; + } ++/* Relax tls le, mainly relax the process of getting TLS le symbolic addresses. ++ there are three situations in which an assembly instruction sequence needs to ++ be relaxed: ++ symbol address = tp + offset (symbol),offset (symbol) = le_hi20_r + le_lo12_r ++ ++ Case 1: ++ in this case, the rd register in the st.{w/d} instruction does not store the ++ full tls symbolic address, but tp + le_hi20_r, which is a part of the tls ++ symbolic address, and then obtains the rd + le_lo12_r address through the ++ st.w instruction feature. ++ this is the full tls symbolic address (tp + le_hi20_r + le_lo12_r). ++ ++ before relax: after relax: ++ ++ lu12i.w $rd,%le_hi20_r (sym) ==> (instruction deleted) ++ add.{w/d} $rd,$rd,$tp,%le_add_r (sym) ==> (instruction deleted) ++ st.{w/d} $rs,$rd,%le_lo12_r (sym) ==> st.{w/d} $rs,$tp,%le_lo12_r (sym) ++ ++ Case 2: ++ in this case, ld.{w/d} is similar to st.{w/d} in case1. ++ ++ before relax: after relax: ++ ++ lu12i.w $rd,%le_hi20_r (sym) ==> (instruction deleted) ++ add.{w/d} $rd,$rd,$tp,%le_add_r (sym) ==> (instruction deleted) ++ ld.{w/d} $rs,$rd,%le_lo12_r (sym) ==> ld.{w/d} $rs,$tp,%le_lo12_r (sym) ++ ++ Case 3: ++ in this case,the rs register in addi.{w/d} stores the full address of the tls ++ symbol (tp + le_hi20_r + le_lo12_r). ++ ++ before relax: after relax: ++ ++ lu12i.w $rd,%le_hi20_r (sym) ==> (instruction deleted) ++ add.{w/d} $rd,$rd,$tp,%le_add_r (sym) ==> (instruction deleted) ++ addi.{w/d} $rs,$rd,%le_lo12_r (sym) ==> addi.{w/d} $rs,$tp,%le_lo12_r (sym) ++*/ ++static bool ++loongarch_relax_tls_le (bfd *abfd, asection *sec, ++ Elf_Internal_Rela *rel, ++ struct bfd_link_info *link_info, ++ bfd_vma symval) ++{ ++ bfd_byte *contents = elf_section_data (sec)->this_hdr.contents; ++ uint32_t insn = bfd_get (32, abfd, contents + rel->r_offset); ++ static uint32_t insn_rj,insn_rd; ++ symval = symval - elf_hash_table (link_info)->tls_sec->vma; ++ /* Whether the symbol offset is in the interval (offset < 0x800). */ ++ if (ELFNN_R_TYPE ((rel + 1)->r_info == R_LARCH_RELAX) && (symval < 0x800)) ++ { ++ switch (ELFNN_R_TYPE (rel->r_info)) ++ { ++ case R_LARCH_TLS_LE_HI20_R: ++ case R_LARCH_TLS_LE_ADD_R: ++ /* delete insn. */ ++ rel->r_info = ELFNN_R_INFO (0, R_LARCH_NONE);
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_service:tar_scm:LoongArch-bfd-Correct-the-name-of-R_LARCH_SOP_POP_32.patch
Added
@@ -0,0 +1,26 @@ +From af43295f92b7f2c85f9613481eb92efcd348f5be Mon Sep 17 00:00:00 2001 +From: Jinyang He <hejinyang@loongson.cn> +Date: Tue, 5 Sep 2023 10:31:27 +0800 +Subject: PATCH 057/123 LoongArch: bfd: Correct the name of + R_LARCH_SOP_POP_32_U in howto_table + +--- + bfd/elfxx-loongarch.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/bfd/elfxx-loongarch.c b/bfd/elfxx-loongarch.c +index 2c40fb02..fe38f369 100644 +--- a/bfd/elfxx-loongarch.c ++++ b/bfd/elfxx-loongarch.c +@@ -548,7 +548,7 @@ static loongarch_reloc_howto_type loongarch_howto_table = + 0, /* bitpos. */ + complain_overflow_unsigned, /* complain_on_overflow. */ + bfd_elf_generic_reloc, /* special_function. */ +- "R_LARCH_SOP_POP_32_S_U", /* name. */ ++ "R_LARCH_SOP_POP_32_U", /* name. */ + false, /* partial_inplace. */ + 0xffffffff00000000, /* src_mask */ + 0x00000000ffffffff, /* dst_mask */ +-- +2.33.0 +
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_service:tar_scm:LoongArch-bfd-Fix-some-bugs-of-howto-table.patch
Added
@@ -0,0 +1,52 @@ +From 4945a32e162be2a7001ed8e8066e983d0ae41bf4 Mon Sep 17 00:00:00 2001 +From: mengqinggang <mengqinggang@loongson.cn> +Date: Thu, 22 Feb 2024 20:18:25 +0800 +Subject: PATCH 058/123 LoongArch: bfd: Fix some bugs of howto table + +R_LARCH_IRELATIVE: For dynamic relocation that does not distinguish between +32/64 bits, size and bitsize set to 8 and 64. +R_LARCH_TLS_DESC64: Change size to 8. +R_LARCH_SOP_POP_32_S_0_5_10_16_S2: Change src_mask to 0, dst_mask to +0x03fffc1f. +--- + bfd/elfxx-loongarch.c | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +diff --git a/bfd/elfxx-loongarch.c b/bfd/elfxx-loongarch.c +index fe38f369..127f3548 100644 +--- a/bfd/elfxx-loongarch.c ++++ b/bfd/elfxx-loongarch.c +@@ -278,8 +278,8 @@ static loongarch_reloc_howto_type loongarch_howto_table = + + LOONGARCH_HOWTO (R_LARCH_IRELATIVE, /* type (12). */ + 0, /* rightshift */ +- 4, /* size */ +- 32, /* bitsize */ ++ 8, /* size */ ++ 64, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ +@@ -312,7 +312,7 @@ static loongarch_reloc_howto_type loongarch_howto_table = + + LOONGARCH_HOWTO (R_LARCH_TLS_DESC64, /* type (14). */ + 0, /* rightshift. */ +- 4, /* size. */ ++ 8, /* size. */ + 64, /* bitsize. */ + false, /* pc_relative. */ + 0, /* bitpos. */ +@@ -514,8 +514,8 @@ static loongarch_reloc_howto_type loongarch_howto_table = + bfd_elf_generic_reloc, /* special_function. */ + "R_LARCH_SOP_POP_32_S_0_5_10_16_S2", /* name. */ + false, /* partial_inplace. */ +- 0xfc0003e0, /* src_mask */ +- 0xfc0003e0, /* dst_mask */ ++ 0x0, /* src_mask */ ++ 0x03fffc1f, /* dst_mask */ + false, /* pcrel_offset */ + BFD_RELOC_LARCH_SOP_POP_32_S_0_5_10_16_S2, + /* bfd_reloc_code_real_type */ +-- +2.33.0 +
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_service:tar_scm:LoongArch-gas-Add-support-for-s9-register.patch
Added
@@ -0,0 +1,98 @@ +From 0f44b5db22c6059f8b8742e08eca9ae282973c7a Mon Sep 17 00:00:00 2001 +From: mengqinggang <mengqinggang@loongson.cn> +Date: Thu, 25 Jan 2024 14:44:12 +0800 +Subject: PATCH 053/123 LoongArch: gas: Add support for s9 register + +In LoongArch ABI, r22 register can be used as frame pointer or +static register(s9). + +Link: https://github.com/loongson/la-abi-specs/blob/release/lapcs.adoc#general-purpose-registers +--- + gas/config/tc-loongarch.c | 7 +++++-- + gas/testsuite/gas/loongarch/loongarch.exp | 1 + + gas/testsuite/gas/loongarch/reg-s9.l | 1 + + gas/testsuite/gas/loongarch/reg-s9.s | 2 ++ + include/opcode/loongarch.h | 1 + + opcodes/loongarch-opc.c | 9 +++++++++ + 6 files changed, 19 insertions(+), 2 deletions(-) + create mode 100644 gas/testsuite/gas/loongarch/reg-s9.l + create mode 100644 gas/testsuite/gas/loongarch/reg-s9.s + +diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c +index 5b7f5137..0495f63a 100644 +--- a/gas/config/tc-loongarch.c ++++ b/gas/config/tc-loongarch.c +@@ -316,8 +316,11 @@ loongarch_after_parse_args () + /* Init ilp32/lp64 registers alias. */ + r_abi_names = loongarch_r_alias; + for (i = 0; i < ARRAY_SIZE (loongarch_r_alias); i++) +- str_hash_insert (r_htab, loongarch_r_aliasi, (void *) (i + 1), +- 0); ++ str_hash_insert (r_htab, loongarch_r_aliasi, (void *) (i + 1), 0); ++ ++ for (i = 0; i < ARRAY_SIZE (loongarch_r_alias_1); i++) ++ str_hash_insert (r_htab, loongarch_r_alias_1i, (void *) (i + 1), 0); ++ + for (i = 0; i < ARRAY_SIZE (loongarch_r_alias_deprecated); i++) + str_hash_insert (r_deprecated_htab, loongarch_r_alias_deprecatedi, + (void *) (i + 1), 0); +diff --git a/gas/testsuite/gas/loongarch/loongarch.exp b/gas/testsuite/gas/loongarch/loongarch.exp +index fedeeecb..1051a541 100644 +--- a/gas/testsuite/gas/loongarch/loongarch.exp ++++ b/gas/testsuite/gas/loongarch/loongarch.exp +@@ -31,4 +31,5 @@ if istarget loongarch*-*-* { + } + + run_list_test "align" ++ run_list_test "reg-s9" + } +diff --git a/gas/testsuite/gas/loongarch/reg-s9.l b/gas/testsuite/gas/loongarch/reg-s9.l +new file mode 100644 +index 00000000..8ea739b7 +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/reg-s9.l +@@ -0,0 +1 @@ ++# No warning or error expected. +diff --git a/gas/testsuite/gas/loongarch/reg-s9.s b/gas/testsuite/gas/loongarch/reg-s9.s +new file mode 100644 +index 00000000..74f40481 +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/reg-s9.s +@@ -0,0 +1,2 @@ ++# Add support for $s9 register ++addi.d $t0, $s9, 0 +diff --git a/include/opcode/loongarch.h b/include/opcode/loongarch.h +index 32ff4d8a..5fc6e190 100644 +--- a/include/opcode/loongarch.h ++++ b/include/opcode/loongarch.h +@@ -196,6 +196,7 @@ dec2 : 1-90-9? + + extern const char *const loongarch_r_normal_name32; + extern const char *const loongarch_r_alias32; ++ extern const char *const loongarch_r_alias_132; + extern const char *const loongarch_r_alias_deprecated32; + extern const char *const loongarch_f_normal_name32; + extern const char *const loongarch_f_alias32; +diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c +index cc3d1986..6afc0e8a 100644 +--- a/opcodes/loongarch-opc.c ++++ b/opcodes/loongarch-opc.c +@@ -49,6 +49,15 @@ const char *const loongarch_r_alias32 = + "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7", "$s8", + }; + ++/* Add support for $s9. */ ++const char *const loongarch_r_alias_132 = ++{ ++ "", "", "", "", "", "", "", "", ++ "", "", "", "", "", "", "", "", ++ "", "", "", "", "", "", "$s9", "", ++ "", "", "", "", "", "", "", "", ++}; ++ + const char *const loongarch_r_alias_deprecated32 = + { + "", "", "", "", "$v0", "$v1", "", "", "", "", "", "", "", "", "", "", +-- +2.33.0 +
View file
_service:tar_scm:LoongArch-gas-Add-support-for-tls-le-relax.patch
Added
@@ -0,0 +1,166 @@ +From d839b6eeb36c9d033038854e08cc8e10b34968ba Mon Sep 17 00:00:00 2001 +From: changjiachen <changjiachen@stu.xupt.edu.cn> +Date: Thu, 28 Dec 2023 19:59:39 +0800 +Subject: PATCH 034/123 LoongArch: gas: Add support for tls le relax. + +Add tls le relax related relocs support and testsuites in gas. + +The main test is three new relocation items, +R_LARCH_TLS_LE_ADD_R, R_LARCH_TLS_LE_HI20_R, +R_LARCH_TLS_LE_LO12_R can be generated properly +and tls le insn format check. + +gas/ChangeLog: + + * config/tc-loongarch.c: + (loongarch_args_parser_can_match_arg_helper): Add support for relax. + * gas/testsuite/gas/loongarch/reloc.d: Likewise. + * gas/testsuite/gas/loongarch/reloc.s: Likewise. + * gas/testsuite/gas/loongarch/loongarch.exp: Likewise. + * gas/testsuite/gas/loongarch/tls_le_insn_format_check.s: New test. +--- + gas/config/tc-loongarch.c | 32 +++++++++++++++++++ + gas/testsuite/gas/loongarch/loongarch.exp | 9 ++++++ + gas/testsuite/gas/loongarch/reloc.d | 18 +++++++++++ + gas/testsuite/gas/loongarch/reloc.s | 11 +++++++ + .../gas/loongarch/tls_le_insn_format_check.s | 15 +++++++++ + 5 files changed, 85 insertions(+) + create mode 100644 gas/testsuite/gas/loongarch/tls_le_insn_format_check.s + +diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c +index def26daf..fad18fcd 100644 +--- a/gas/config/tc-loongarch.c ++++ b/gas/config/tc-loongarch.c +@@ -636,6 +636,30 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2, + break; + } + break; ++ /* This is used for TLS, where the fourth operand is %le_add_r, ++ to get a relocation applied to an add instruction, for relaxation to use. ++ Two conditions, ip->match_now and reloc_num, are used to check tls insn ++ to prevent cases like add.d $a0,$a0,$a0,8. */ ++ case 't': ++ ip->match_now = loongarch_parse_expr (arg, ip->reloc_info + ip->reloc_num, ++ reloc_num_we_have, &reloc_num, &imm) == 0; ++ ++ if (!ip->match_now) ++ break; ++ ++ bfd_reloc_code_real_type tls_reloc_type = BFD_RELOC_LARCH_TLS_LE_ADD_R; ++ ++ if (reloc_num ++ && (ip->reloc_infoip->reloc_num.type == tls_reloc_type)) ++ { ++ ip->reloc_num += reloc_num; ++ ip->reloc_infoip->reloc_num.type = BFD_RELOC_LARCH_RELAX; ++ ip->reloc_infoip->reloc_num.value = const_0; ++ ip->reloc_num++; ++ } ++ else ++ ip->match_now = 0; ++ break; + case 's': + case 'u': + ip->match_now = +@@ -690,6 +714,14 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2, + ip->reloc_num += reloc_num; + reloc_type = ip->reloc_info0.type; + ++ if (LARCH_opts.relax ++ && (BFD_RELOC_LARCH_TLS_LE_HI20_R == reloc_type ++ || BFD_RELOC_LARCH_TLS_LE_LO12_R == reloc_type)) ++ { ++ ip->reloc_infoip->reloc_num.type = BFD_RELOC_LARCH_RELAX; ++ ip->reloc_infoip->reloc_num.value = const_0; ++ ip->reloc_num++; ++ } + if (LARCH_opts.relax && ip->macro_id + && (BFD_RELOC_LARCH_PCALA_HI20 == reloc_type + || BFD_RELOC_LARCH_PCALA_LO12 == reloc_type +diff --git a/gas/testsuite/gas/loongarch/loongarch.exp b/gas/testsuite/gas/loongarch/loongarch.exp +index 6d126fd4..c0aa593d 100644 +--- a/gas/testsuite/gas/loongarch/loongarch.exp ++++ b/gas/testsuite/gas/loongarch/loongarch.exp +@@ -21,4 +21,13 @@ + if istarget loongarch*-*-* { + run_dump_tests lsort glob -nocomplain $srcdir/$subdir/*.d + gas_test_old bfd_reloc_8.s "" "bfd_reloc_8" ++ if file exist "tls_le_insn_format_check.s " { ++ set format run_host_cmd "as" "tls_le_insn_format_check.s" ++ if { regexp ".*no match insn.*" $format } { ++ pass "loongarch tls le insn format pass" ++ } { ++ pass "loongarch tls le insn format fail" ++ } ++ } ++ + } +diff --git a/gas/testsuite/gas/loongarch/reloc.d b/gas/testsuite/gas/loongarch/reloc.d +index c3820c55..0458830f 100644 +--- a/gas/testsuite/gas/loongarch/reloc.d ++++ b/gas/testsuite/gas/loongarch/reloc.d +@@ -165,3 +165,21 @@ Disassembly of section .text: + +134: +R_LARCH_TLS_LE64_LO20 +TLSL1\+0x8 + +138: +03000085 +lu52i.d +\$a1, +\$a0, +0 + +138: +R_LARCH_TLS_LE64_HI12 +TLSL1\+0x8 ++ +13c: +14000004 +lu12i.w +\$a0, +0 ++ +13c: +R_LARCH_TLS_LE_HI20_R +TLSL1 ++ +13c: +R_LARCH_RELAX +\*ABS\* ++ +140: +001090a5 +add.d +\$a1, +\$a1, +\$a0 ++ +140: +R_LARCH_TLS_LE_ADD_R +TLSL1 ++ +140: +R_LARCH_RELAX +\*ABS\* ++ +144: +29800085 +st.w +\$a1, +\$a0, +0 ++ +144: +R_LARCH_TLS_LE_LO12_R +TLSL1 ++ +144: +R_LARCH_RELAX +\*ABS\* ++ +148: +14000004 +lu12i.w +\$a0, +0 ++ +148: +R_LARCH_TLS_LE_HI20_R +TLSL1\+0x8 ++ +148: +R_LARCH_RELAX +\*ABS\* ++ +14c: +001090a5 +add.d +\$a1, +\$a1, +\$a0 ++ +14c: +R_LARCH_TLS_LE_ADD_R +TLSL1\+0x8 ++ +14c: +R_LARCH_RELAX +\*ABS\* ++ +150: +29800085 +st.w +\$a1, +\$a0, +0 ++ +150: +R_LARCH_TLS_LE_LO12_R +TLSL1\+0x8 ++ +150: +R_LARCH_RELAX +\*ABS\* +diff --git a/gas/testsuite/gas/loongarch/reloc.s b/gas/testsuite/gas/loongarch/reloc.s +index a67fecd9..0a343c11 100644 +--- a/gas/testsuite/gas/loongarch/reloc.s ++++ b/gas/testsuite/gas/loongarch/reloc.s +@@ -142,3 +142,14 @@ lu12i.w $r4,%le_hi20(TLSL1 + 0x8) + ori $r5,$r4,%le_lo12(TLSL1 + 0x8) + lu32i.d $r4,%le64_lo20(TLSL1 + 0x8) + lu52i.d $r5,$r4,%le64_hi12(TLSL1 + 0x8) ++ ++ ++/* New TLS Insn. */ ++lu12i.w $r4,%le_hi20_r(TLSL1) ++add.d $r5,$r5,$r4,%le_add_r(TLSL1) ++st.w $r5,$r4,%le_lo12_r(TLSL1) ++ ++/* New TLS Insn with addend. */ ++lu12i.w $r4,%le_hi20_r(TLSL1 + 0x8) ++add.d $r5,$r5,$r4,%le_add_r(TLSL1 + 0x8) ++st.w $r5,$r4,%le_lo12_r(TLSL1 + 0x8) +diff --git a/gas/testsuite/gas/loongarch/tls_le_insn_format_check.s b/gas/testsuite/gas/loongarch/tls_le_insn_format_check.s +new file mode 100644 +index 00000000..1b3c9d18 +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/tls_le_insn_format_check.s +@@ -0,0 +1,15 @@ ++/* Assemble the following assembly statements using as. ++ ++ The test case is mainly to check the format of tls le type ++ symbolic address fetch instruction.Because in tls le symbolic ++ address acquisition, there will be a special add.d instruction, ++ which has four operands (add.d op1,op2,op3,op4),the first three ++ operands are registers, and the last operand is a relocation, ++ we need to format check the fourth operand.If it is not a correct ++ relocation type operand, we need to throw the relevant exception ++ message. ++ ++ if a "no match insn" exception is thrown, the test passes; ++ otherwise, the test fails. */ ++ ++add.d $a0,$a0,$a0,8 +-- +2.33.0 +
View file
_service:tar_scm:LoongArch-gas-Adjust-DWARF-CIE-alignment-factors.patch
Added
@@ -0,0 +1,49 @@ +From 3b3e724f35e119acdbac2c8c6682a11e9cae64e2 Mon Sep 17 00:00:00 2001 +From: mengqinggang <mengqinggang@loongson.cn> +Date: Mon, 29 Apr 2024 15:11:31 +0800 +Subject: PATCH 086/123 LoongArch: gas: Adjust DWARF CIE alignment factors + +Set DWARF2_CIE_DATA_ALIGNMENT (data alignment factors) to -8. +It helps to save space. + +Data Alignment Factor +A signed LEB128 encoded value that is factored out of all offset +instructions that are associated with this CIE or its FDEs. This value +shall be multiplied by the register offset argument of an offset +instruction to obtain the new offset value. +--- + gas/config/tc-loongarch.h | 14 +++++++++----- + 1 file changed, 9 insertions(+), 5 deletions(-) + +diff --git a/gas/config/tc-loongarch.h b/gas/config/tc-loongarch.h +index 0b5cdfe6..6963867e 100644 +--- a/gas/config/tc-loongarch.h ++++ b/gas/config/tc-loongarch.h +@@ -99,15 +99,19 @@ extern bool loongarch_frag_align_code (int, int); + + #define TC_FORCE_RELOCATION_LOCAL(FIX) 1 + +-/* Adjust debug_line after relaxation. */ +-#define DWARF2_USE_FIXED_ADVANCE_PC 1 +- + /* Values passed to md_apply_fix don't include symbol values. */ + #define MD_APPLY_SYM_VALUE(FIX) 0 + + #define TARGET_USE_CFIPOP 1 +-#define DWARF2_DEFAULT_RETURN_COLUMN 1 /* $ra. */ +-#define DWARF2_CIE_DATA_ALIGNMENT -4 ++/* Adjust debug_line after relaxation. */ ++#define DWARF2_USE_FIXED_ADVANCE_PC 1 ++ ++/* FDE Data Alignment Factor. ++ FDE Code Alignment Factor (DWARF2_LINE_MIN_INSN_LENGTH) should be 1 ++ because DW_CFA_advance_loc need to be relocated in bytes ++ when linker relaxation. */ ++#define DWARF2_CIE_DATA_ALIGNMENT (-8) ++#define DWARF2_DEFAULT_RETURN_COLUMN 1 /* FDE Return Address Register. */ + + #define tc_cfi_frame_initial_instructions \ + loongarch_cfi_frame_initial_instructions +-- +2.33.0 +
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_service:tar_scm:LoongArch-gas-Don-t-define-LoongArch-.align.patch
Added
@@ -0,0 +1,82 @@ +From f30bb80d462445ac5557bc65abd4672ce915b9e9 Mon Sep 17 00:00:00 2001 +From: mengqinggang <mengqinggang@loongson.cn> +Date: Sun, 1 Oct 2023 15:29:44 +0800 +Subject: PATCH 050/123 LoongArch: gas: Don't define LoongArch .align + +Gcc may generate "\t.align\t%d,54525952,4\n" before commit +b20c7ee066cb7d952fa193972e8bc6362c6e4063. To write 54525952 (NOP) to object +file, we call s_align_ptwo (-4). It result in alignment padding must be a +multiple of 4 if .align has second parameter. + +Use default s_align_ptwo for .align. +--- + gas/config/tc-loongarch.c | 13 ------------- + gas/testsuite/gas/loongarch/align.l | 1 + + gas/testsuite/gas/loongarch/align.s | 5 +++++ + gas/testsuite/gas/loongarch/loongarch.exp | 1 + + 4 files changed, 7 insertions(+), 13 deletions(-) + create mode 100644 gas/testsuite/gas/loongarch/align.l + create mode 100644 gas/testsuite/gas/loongarch/align.s + +diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c +index 1ae57b45..49470073 100644 +--- a/gas/config/tc-loongarch.c ++++ b/gas/config/tc-loongarch.c +@@ -436,18 +436,6 @@ loongarch_mach (void) + + static const expressionS const_0 = { .X_op = O_constant, .X_add_number = 0 }; + +-static void +-s_loongarch_align (int arg) +-{ +- const char *t = input_line_pointer; +- while (!is_end_of_line(unsigned char) *t && *t != ',') +- ++t; +- if (*t == ',') +- s_align_ptwo (arg); +- else +- s_align_ptwo (0); +-} +- + /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate + a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for + use in DWARF debug information. */ +@@ -479,7 +467,6 @@ s_dtprel (int bytes) + + static const pseudo_typeS loongarch_pseudo_table = + { +- { "align", s_loongarch_align, -4 }, + { "dword", cons, 8 }, + { "word", cons, 4 }, + { "half", cons, 2 }, +diff --git a/gas/testsuite/gas/loongarch/align.l b/gas/testsuite/gas/loongarch/align.l +new file mode 100644 +index 00000000..8ea739b7 +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/align.l +@@ -0,0 +1 @@ ++# No warning or error expected. +diff --git a/gas/testsuite/gas/loongarch/align.s b/gas/testsuite/gas/loongarch/align.s +new file mode 100644 +index 00000000..93f25289 +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/align.s +@@ -0,0 +1,5 @@ ++# Fix bug: alignment padding must a multiple of 4 if .align has second parameter ++.data ++ .byte 1 ++ .align 3, 2 ++ .4byte 3 +diff --git a/gas/testsuite/gas/loongarch/loongarch.exp b/gas/testsuite/gas/loongarch/loongarch.exp +index c0aa593d..fedeeecb 100644 +--- a/gas/testsuite/gas/loongarch/loongarch.exp ++++ b/gas/testsuite/gas/loongarch/loongarch.exp +@@ -30,4 +30,5 @@ if istarget loongarch*-*-* { + } + } + ++ run_list_test "align" + } +-- +2.33.0 +
View file
_service:tar_scm:LoongArch-gas-Fix-make-check-gas-crash.patch
Added
@@ -0,0 +1,26 @@ +From e80e6624e3b5aafd683706f6567e4b748c4c441f Mon Sep 17 00:00:00 2001 +From: mengqinggang <mengqinggang@loongson.cn> +Date: Fri, 18 Aug 2023 17:02:20 +0800 +Subject: PATCH 005/123 LoongArch: gas: Fix make check-gas crash + +--- + gas/testsuite/lib/gas-defs.exp | 3 --- + 1 file changed, 3 deletions(-) + +diff --git a/gas/testsuite/lib/gas-defs.exp b/gas/testsuite/lib/gas-defs.exp +index 3e134ca8..da0c24ea 100644 +--- a/gas/testsuite/lib/gas-defs.exp ++++ b/gas/testsuite/lib/gas-defs.exp +@@ -361,9 +361,6 @@ proc verbose_eval { expr { level 1 } } { + # that version gets released, and has been out in the world for a few + # months at least, it may be safe to delete this copy. + +-if { istarget loongarch*-*-* } { +- rename prune_warnings prune_warnings_other +-} + if !string length info proc prune_warnings { + # + # prune_warnings -- delete various system verbosities from TEXT. +-- +2.33.0 +
View file
_service:tar_scm:LoongArch-gas-Fix-the-types-of-symbols-referred-with.patch
Added
@@ -0,0 +1,84 @@ +From f0efc301a550708ea07b8dad127d5cb149661d24 Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao <xry111@xry111.site> +Date: Fri, 2 Feb 2024 21:00:58 +0800 +Subject: PATCH 055/123 LoongArch: gas: Fix the types of symbols referred + with %le_*_r in the symtab + +When a symbol is referred with %le_{hi20,lo12,add}_r, it's definitely a +TLS symbol and we should set its type to TLS in the symtab. Otherwise +when building Perl with gcc-14 -flto, we get: + +/usr/bin/ld: PL_current_context: TLS definition in +./miniperl.ltrans0.ltrans.o section .tbss mismatches non-TLS reference +in ./miniperl.ltrans1.ltrans.o + +A minimal reproducer: + + $ cat t1.s + .section .tbss + .globl x + x: .word 0 + $ cat t2.s + f: + lu12i.w $a0, %le_hi20_r(x) + add.d $a0, $a0, $tp, %le_add_r(x) + li.w $a1, 1 + st.w $a1, $a0, %le_lo12_r(x) + $ gas/as-new t1.s -o t1.o + $ gas/as-new t2.s -o t2.o + $ ld/ld-new t1.o t2.o + ld/ld-new: x: TLS definition in t1.o section .tbss mismatches + non-TLS reference in t2.o + +Unfortunately this was undetected before Binutils-2.42 release because +GCC < 14 does not use %le_*_r, and without LTO it's very rare to have a +TLS LE definition and its reference in two different translation units. +So this fix should be backported to Binutils-2.42 branch too. + +Signed-off-by: Xi Ruoyao <xry111@xry111.site> +--- + gas/config/tc-loongarch.c | 3 +++ + gas/testsuite/gas/loongarch/tls_le_r_sym_type.d | 3 +++ + gas/testsuite/gas/loongarch/tls_le_r_sym_type.s | 6 ++++++ + 3 files changed, 12 insertions(+) + create mode 100644 gas/testsuite/gas/loongarch/tls_le_r_sym_type.d + create mode 100644 gas/testsuite/gas/loongarch/tls_le_r_sym_type.s + +diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c +index 0495f63a..5e96f624 100644 +--- a/gas/config/tc-loongarch.c ++++ b/gas/config/tc-loongarch.c +@@ -1340,6 +1340,9 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) + case BFD_RELOC_LARCH_TLS_DESC_LO12: + case BFD_RELOC_LARCH_TLS_DESC64_LO20: + case BFD_RELOC_LARCH_TLS_DESC64_HI12: ++ case BFD_RELOC_LARCH_TLS_LE_ADD_R: ++ case BFD_RELOC_LARCH_TLS_LE_HI20_R: ++ case BFD_RELOC_LARCH_TLS_LE_LO12_R: + /* Add tls lo (got_lo reloc type). */ + if (fixP->fx_addsy == NULL) + as_bad_where (fixP->fx_file, fixP->fx_line, +diff --git a/gas/testsuite/gas/loongarch/tls_le_r_sym_type.d b/gas/testsuite/gas/loongarch/tls_le_r_sym_type.d +new file mode 100644 +index 00000000..43bcd789 +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/tls_le_r_sym_type.d +@@ -0,0 +1,3 @@ ++#readelf: -s ++#... ++.*TLS \t+GLOBAL \t+DEFAULT \t+UND \t+x +diff --git a/gas/testsuite/gas/loongarch/tls_le_r_sym_type.s b/gas/testsuite/gas/loongarch/tls_le_r_sym_type.s +new file mode 100644 +index 00000000..3ccedae9 +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/tls_le_r_sym_type.s +@@ -0,0 +1,6 @@ ++f: ++ lu12i.w $a0, %le_hi20_r(x) ++ add.d $a0, $a0, $tp, %le_add_r(x) ++ li.w $a1, 1 ++ st.w $a1, $a0, %le_lo12_r(x) ++ ret +-- +2.33.0 +
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_service:tar_scm:LoongArch-gas-Ignore-.align-if-it-is-at-the-start-of.patch
Added
@@ -0,0 +1,308 @@ +From adb3d28328bbf2d17c3a44778497827d7d35124a Mon Sep 17 00:00:00 2001 +From: mengqinggang <mengqinggang@loongson.cn> +Date: Tue, 19 Mar 2024 21:09:12 +0800 +Subject: PATCH 076/123 LoongArch: gas: Ignore .align if it is at the start + of a section + +Ignore .align if it is at the start of a section and the alignment +can be divided by the section alignment, the section alignment +can ensure this .align has a correct alignment. +--- + gas/config/tc-loongarch.c | 134 ++++++++++++++---- + .../gas/loongarch/relax-align-first.d | 12 ++ + .../gas/loongarch/relax-align-first.s | 7 + + .../ld-loongarch-elf/relax-align-first.d | 15 ++ + .../ld-loongarch-elf/relax-align-first.s | 13 ++ + ld/testsuite/ld-loongarch-elf/relax.exp | 1 + + 6 files changed, 157 insertions(+), 25 deletions(-) + create mode 100644 gas/testsuite/gas/loongarch/relax-align-first.d + create mode 100644 gas/testsuite/gas/loongarch/relax-align-first.s + create mode 100644 ld/testsuite/ld-loongarch-elf/relax-align-first.d + create mode 100644 ld/testsuite/ld-loongarch-elf/relax-align-first.s + +diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c +index 1e835f51..110b92e4 100644 +--- a/gas/config/tc-loongarch.c ++++ b/gas/config/tc-loongarch.c +@@ -128,6 +128,11 @@ static bool call36 = 0; + #define RELAX_BRANCH_ENCODE(x) \ + (BFD_RELOC_LARCH_B16 == (x) ? RELAX_BRANCH_16 : RELAX_BRANCH_21) + ++#define ALIGN_MAX_ADDEND(n, max) ((max << 8) | n) ++#define ALIGN_MAX_NOP_BYTES(addend) ((1 << (addend & 0xff)) - 4) ++#define FRAG_AT_START_OF_SECTION(frag) \ ++ (0 == frag->fr_address && 0 == frag->fr_fix) ++ + enum options + { + OPTION_IGNORE = OPTION_MD_BASE, +@@ -1647,10 +1652,32 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) + } + } + ++/* Estimate the size of a frag before relaxing. */ ++ + int +-md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED, +- asection *segtype ATTRIBUTE_UNUSED) ++md_estimate_size_before_relax (fragS *fragp, asection *sec) + { ++ /* align pseudo instunctions. */ ++ if (rs_align_code == fragp->fr_subtype) ++ { ++ offsetT nop_bytes; ++ if (NULL == fragp->fr_symbol) ++ nop_bytes = fragp->fr_offset; ++ else ++ nop_bytes = ALIGN_MAX_NOP_BYTES (fragp->fr_offset); ++ ++ /* Normally, nop_bytes should be >= 4. */ ++ gas_assert (nop_bytes > 0); ++ ++ if (FRAG_AT_START_OF_SECTION (fragp) ++ && 0 == ((1 << sec->alignment_power) % (nop_bytes + 4))) ++ return (fragp->fr_var = 0); ++ else ++ return (fragp->fr_var = nop_bytes); ++ } ++ ++ /* branch instructions and other instructions. ++ branch instructions may become 8 bytes after relaxing. */ + return (fragp->fr_var = 4); + } + +@@ -1767,8 +1794,7 @@ bool + loongarch_frag_align_code (int n, int max) + { + char *nops; +- symbolS *s; +- expressionS ex; ++ symbolS *s = NULL; + + bfd_vma insn_alignment = 4; + bfd_vma bytes = (bfd_vma) 1 << n; +@@ -1783,8 +1809,6 @@ loongarch_frag_align_code (int n, int max) + if (!LARCH_opts.relax) + return false; + +- nops = frag_more (worst_case_bytes); +- + /* If max <= 0, ignore max. + If max >= worst_case_bytes, max has no effect. + Similar to gas/write.c relax_segment function rs_align_code case: +@@ -1792,20 +1816,20 @@ loongarch_frag_align_code (int n, int max) + if (max > 0 && (bfd_vma) max < worst_case_bytes) + { + s = symbol_find (now_seg->name); +- ex.X_add_symbol = s; +- ex.X_op = O_symbol; +- ex.X_add_number = (max << 8) | n; +- } +- else +- { +- ex.X_op = O_constant; +- ex.X_add_number = worst_case_bytes; ++ worst_case_bytes = ALIGN_MAX_ADDEND (n, max); + } + +- loongarch_make_nops (nops, worst_case_bytes); ++ frag_grow (worst_case_bytes); ++ /* Use relaxable frag for .align. ++ If .align at the start of section, do nothing. Section alignment can ++ ensure correct alignment. ++ If .align is not at the start of a section, reserve NOP instructions ++ and R_LARCH_ALIGN relocation. */ ++ nops = frag_var (rs_machine_dependent, worst_case_bytes, worst_case_bytes, ++ rs_align_code, s, worst_case_bytes, NULL); + +- fix_new_exp (frag_now, nops - frag_now->fr_literal, 0, +- &ex, false, BFD_RELOC_LARCH_ALIGN); ++ /* Default write NOP for aligned bytes. */ ++ loongarch_make_nops (nops, worst_case_bytes); + + /* We need to start a new frag after the alignment which may be removed by + the linker, to prevent the assembler from computing static offsets. +@@ -1963,8 +1987,7 @@ loongarch_relaxed_branch_length (fragS *fragp, asection *sec, int update) + } + + int +-loongarch_relax_frag (asection *sec ATTRIBUTE_UNUSED, +- fragS *fragp ATTRIBUTE_UNUSED, ++loongarch_relax_frag (asection *sec, fragS *fragp, + long stretch ATTRIBUTE_UNUSED) + { + if (RELAX_BRANCH (fragp->fr_subtype)) +@@ -1973,6 +1996,27 @@ loongarch_relax_frag (asection *sec ATTRIBUTE_UNUSED, + fragp->fr_var = loongarch_relaxed_branch_length (fragp, sec, true); + return fragp->fr_var - old_var; + } ++ else if (rs_align_code == fragp->fr_subtype) ++ { ++ offsetT nop_bytes; ++ if (NULL == fragp->fr_symbol) ++ nop_bytes = fragp->fr_offset; ++ else ++ nop_bytes = ALIGN_MAX_NOP_BYTES (fragp->fr_offset); ++ ++ /* Normally, nop_bytes should be >= 4. */ ++ gas_assert (nop_bytes > 0); ++ ++ offsetT old_var = fragp->fr_var; ++ /* If .align at the start of a section, do nothing. Section alignment ++ * can ensure correct alignment. */ ++ if (FRAG_AT_START_OF_SECTION (fragp) ++ && 0 == ((1 << sec->alignment_power) % (nop_bytes + 4))) ++ fragp->fr_var = 0; ++ else ++ fragp->fr_var = nop_bytes; ++ return fragp->fr_var - old_var; ++ } + return 0; + } + +@@ -2048,13 +2092,53 @@ loongarch_convert_frag_branch (fragS *fragp) + fragp->fr_fix += fragp->fr_var; + } + +-/* Relax a machine dependent frag. This returns the amount by which +- the current size of the frag should change. */ ++/* Relax .align frag. */ ++ ++static void ++loongarch_convert_frag_align (fragS *fragp, asection *sec) ++{ ++ bfd_byte *buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; ++ ++ offsetT nop_bytes; ++ if (NULL == fragp->fr_symbol) ++ nop_bytes = fragp->fr_offset; ++ else ++ nop_bytes = ALIGN_MAX_NOP_BYTES (fragp->fr_offset); ++ ++ /* Normally, nop_bytes should be >= 4. */ ++ gas_assert (nop_bytes > 0); ++ ++ if (!(FRAG_AT_START_OF_SECTION (fragp) ++ && 0 == ((1 << sec->alignment_power) % (nop_bytes + 4)))) ++ { ++ expressionS exp; ++ exp.X_op = O_symbol; ++ exp.X_add_symbol = fragp->fr_symbol; ++ exp.X_add_number = fragp->fr_offset; ++ ++ fixS *fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, ++ nop_bytes, &exp, false, BFD_RELOC_LARCH_ALIGN); ++ fixp->fx_file = fragp->fr_file; ++ fixp->fx_line = fragp->fr_line; ++ ++ buf += nop_bytes; ++ }
View file
_service:tar_scm:LoongArch-gas-Simplify-relocations-in-sections-witho.patch
Added
@@ -0,0 +1,68 @@ +From 47494a014c00dfa3832441171255018be62ac756 Mon Sep 17 00:00:00 2001 +From: Jinyang He <hejinyang@loongson.cn> +Date: Mon, 22 Apr 2024 17:49:50 +0800 +Subject: PATCH 083/123 LoongArch: gas: Simplify relocations in sections + without code flag + +Gas should not emit ADD/SUB relocation pairs for label differences +if they are in the same section without code flag even relax enabled. +Because the real value is not be affected by relaxation and it can be +compute out in assembly stage. Thus, correct the `TC_FORCE_RELOCATION +_SUB_SAME` and the label differences in same section without code +flag can be resolved in fixup_segment(). +--- + gas/config/tc-loongarch.h | 4 +--- + gas/testsuite/gas/loongarch/relax_debug_line.d | 12 ++++++++++++ + gas/testsuite/gas/loongarch/relax_debug_line.s | 6 ++++++ + 3 files changed, 19 insertions(+), 3 deletions(-) + create mode 100644 gas/testsuite/gas/loongarch/relax_debug_line.d + create mode 100644 gas/testsuite/gas/loongarch/relax_debug_line.s + +diff --git a/gas/config/tc-loongarch.h b/gas/config/tc-loongarch.h +index 194ee107..0b5cdfe6 100644 +--- a/gas/config/tc-loongarch.h ++++ b/gas/config/tc-loongarch.h +@@ -91,9 +91,7 @@ extern bool loongarch_frag_align_code (int, int); + #define TC_FORCE_RELOCATION_SUB_SAME(FIX, SEC) \ + (LARCH_opts.relax ? \ + (GENERIC_FORCE_RELOCATION_SUB_SAME (FIX, SEC) \ +- || ((SEC)->flags & SEC_CODE) != 0 \ +- || ((SEC)->flags & SEC_DEBUGGING) != 0 \ +- || TC_FORCE_RELOCATION (FIX)) \ ++ || ((SEC)->flags & SEC_CODE) != 0) \ + : (GENERIC_FORCE_RELOCATION_SUB_SAME (FIX, SEC))) \ + + #define TC_LINKRELAX_FIXUP(seg) ((seg->flags & SEC_CODE) \ +diff --git a/gas/testsuite/gas/loongarch/relax_debug_line.d b/gas/testsuite/gas/loongarch/relax_debug_line.d +new file mode 100644 +index 00000000..c17813c2 +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/relax_debug_line.d +@@ -0,0 +1,12 @@ ++#as: --gdwarf-5 ++#readelf: -r --wide ++#skip: loongarch32-*-* ++ ++Relocation section '\.rela\.debug_line' at offset .* contains 5 entries: ++#... ++0+22.*R_LARCH_32 \t+0-9+.* ++0+2c.*R_LARCH_32 \t+0-9+.* ++0+36.*R_LARCH_64 \t+0-9+.* ++0+42.*R_LARCH_ADD16 \t+0-9+.* ++0+42.*R_LARCH_SUB16 \t+0-9+.* ++#pass +diff --git a/gas/testsuite/gas/loongarch/relax_debug_line.s b/gas/testsuite/gas/loongarch/relax_debug_line.s +new file mode 100644 +index 00000000..d2852bb9 +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/relax_debug_line.s +@@ -0,0 +1,6 @@ ++ .file 0 "test" ++ .text ++ .loc 0 10 0 ++ nop ++ ++.section .debug_line, "", @progbits +-- +2.33.0 +
View file
_service:tar_scm:LoongArch-gas-Start-a-new-frag-after-instructions-th.patch
Added
@@ -0,0 +1,143 @@ +From 04b665b402affb89a5b077516bc306da11af1e84 Mon Sep 17 00:00:00 2001 +From: mengqinggang <mengqinggang@loongson.cn> +Date: Thu, 18 Jan 2024 19:03:11 +0800 +Subject: PATCH 051/123 LoongArch: gas: Start a new frag after instructions + that can be relaxed + +For R_LARCH_TLS_{LE_HI20_R,LE_ADD_R,LD_PC_HI20,GD_PC_HI20, DESC_PC_HI20} +relocations, start a new frag to get correct eh_frame Call Frame Information +FDE DW_CFA_advance_loc info. +--- + gas/config/tc-loongarch.c | 19 ++++++-- + .../relax-cfi-fde-DW_CFA_advance_loc.d | 46 +++++++++++++++++++ + .../relax-cfi-fde-DW_CFA_advance_loc.s | 33 +++++++++++++ + 3 files changed, 93 insertions(+), 5 deletions(-) + create mode 100644 gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.d + create mode 100644 gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.s + +diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c +index 49470073..5b7f5137 100644 +--- a/gas/config/tc-loongarch.c ++++ b/gas/config/tc-loongarch.c +@@ -1070,13 +1070,22 @@ append_fixp_and_insn (struct loongarch_cl_insn *ip) + optimized away or compressed by the linker during relaxation, to prevent + the assembler from computing static offsets across such an instruction. + +- This is necessary to get correct .eh_frame cfa info. If one cfa's two +- symbol is not in the same frag, it will generate relocs to calculate +- symbol subtraction. (gas/dw2gencfi.c:output_cfi_insn: +- if (symbol_get_frag (to) == symbol_get_frag (from))) */ ++ This is necessary to get correct .eh_frame FDE DW_CFA_advance_loc info. ++ If one cfi_insn_data's two symbols are not in the same frag, it will ++ generate ADD and SUB relocations pairs to calculate DW_CFA_advance_loc. ++ (gas/dw2gencfi.c: output_cfi_insn: ++ if (symbol_get_frag (to) == symbol_get_frag (from))) ++ ++ For macro instructions, only the first instruction expanded from macro ++ need to start a new frag. */ + if (LARCH_opts.relax + && (BFD_RELOC_LARCH_PCALA_HI20 == reloc_info0.type +- || BFD_RELOC_LARCH_GOT_PC_HI20 == reloc_info0.type)) ++ || BFD_RELOC_LARCH_GOT_PC_HI20 == reloc_info0.type ++ || BFD_RELOC_LARCH_TLS_LE_HI20_R == reloc_info0.type ++ || BFD_RELOC_LARCH_TLS_LE_ADD_R == reloc_info0.type ++ || BFD_RELOC_LARCH_TLS_LD_PC_HI20 == reloc_info0.type ++ || BFD_RELOC_LARCH_TLS_GD_PC_HI20 == reloc_info0.type ++ || BFD_RELOC_LARCH_TLS_DESC_PC_HI20 == reloc_info0.type)) + { + frag_wane (frag_now); + frag_new (0); +diff --git a/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.d b/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.d +new file mode 100644 +index 00000000..367039e1 +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.d +@@ -0,0 +1,46 @@ ++#as: -mrelax ++#objdump: -Dr -j .eh_frame ++#skip: loongarch32-*-* ++ ++.*: +file format .* ++ ++ ++Disassembly of section .eh_frame: ++ ++ *0000000000000000 <.eh_frame>: ++ +0: +00000014 +.word + +0x00000014 ++ +4: +00000000 +.word + +0x00000000 ++ +8: +00527a01 +.word + +0x00527a01 ++ +c: +01017c01 +fadd.d +\$fa1, \$fa0, \$fs7 ++ +10: +0c030d1b +.word + +0x0c030d1b ++ +14: +00000016 +.word + +0x00000016 ++ +18: +00000034 +.word + +0x00000034 ++ +1c: +0000001c +.word + +0x0000001c ++ +... ++ +20: R_LARCH_32_PCREL +L0\^A ++ +24: R_LARCH_ADD32 +L0\^A ++ +24: R_LARCH_SUB32 +L0\^A ++ +28: +0cd64000 +.word + +0x0cd64000 ++ +29: R_LARCH_ADD6 +L0\^A ++ +29: R_LARCH_SUB6 +L0\^A ++ +2c: +d6400016 +.word + +0xd6400016 ++ +2e: R_LARCH_ADD6 +L0\^A ++ +2e: R_LARCH_SUB6 +L0\^A ++ +30: +4000160c +beqz +\$t4, 3145748 +# 300044 <L0\^A\+0x30000c> ++ +33: R_LARCH_ADD6 +L0\^A ++ +33: R_LARCH_SUB6 +L0\^A ++ +34: +00160cd6 +orn +\$fp, \$a2, \$sp ++ +38: +160cd640 +lu32i.d +\$zero, 26290 ++ +38: R_LARCH_ADD6 +L0\^A ++ +38: R_LARCH_SUB6 +L0\^A ++ +3c: +0cd64000 +.word + +0x0cd64000 ++ +3d: R_LARCH_ADD6 +L0\^A ++ +3d: R_LARCH_SUB6 +L0\^A ++ +40: +d6400016 +.word + +0xd6400016 ++ +42: R_LARCH_ADD6 +L0\^A ++ +42: R_LARCH_SUB6 +L0\^A ++ +44: +4000160c +beqz +\$t4, 3145748 +# 300058 <L0\^A\+0x300020> ++ +47: R_LARCH_ADD6 +L0\^A ++ +47: R_LARCH_SUB6 +L0\^A ++ +48: +000000d6 +.word + +0x000000d6 ++ +4c: +00000000 +.word + +0x00000000 +diff --git a/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.s b/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.s +new file mode 100644 +index 00000000..6e4c9b8b +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.s +@@ -0,0 +1,33 @@ ++# Emits ADD/SUB relocations for CFA FDE DW_CFA_advance_loc with -mrelax option. ++.text ++.cfi_startproc ++ ++.cfi_def_cfa 22, 0 ++la.local $t0, a ++.cfi_restore 22 ++ ++.cfi_def_cfa 22, 0 ++la.got $t0, a ++.cfi_restore 22 ++ ++.cfi_def_cfa 22, 0 ++la.tls.ld $t0, a ++.cfi_restore 22 ++ ++.cfi_def_cfa 22, 0 ++la.tls.gd $t0, a ++.cfi_restore 22 ++ ++.cfi_def_cfa 22, 0 ++la.tls.desc $t0, a ++.cfi_restore 22 ++ ++.cfi_def_cfa 22, 0 ++pcalau12i $t0, %le_hi20_r(a) ++.cfi_restore 22 ++ ++.cfi_def_cfa 22, 0 ++add.d $t0, $tp, $t0, %le_add_r(a) ++.cfi_restore 22 ++ ++.cfi_endproc +-- +2.33.0 +
View file
_service:tar_scm:LoongArch-gas-Try-to-avoid-R_LARCH_ALIGN-associate-w.patch
Added
@@ -0,0 +1,166 @@ +From 7b212e5db865a826dc15aaf5e0562133c88eb769 Mon Sep 17 00:00:00 2001 +From: mengqinggang <mengqinggang@loongson.cn> +Date: Mon, 5 Feb 2024 16:16:52 +0800 +Subject: PATCH 056/123 LoongArch: gas: Try to avoid R_LARCH_ALIGN associate + with a symbol + +The R_LARCH_ALIGN need to associated with a symbol if .align has the first +and third expressions. If R_LARCH_ALIGN associate with a symbol, the addend can +represent the first and third expression of .align. + +For '.align 3', the addend of R_LARCH_ALIGN only need to represent the alignment +and R_LARCH_ALIGN not need to associate with a symbol. + +For '.align x, , y', R_LARCH_ALIGN need to associate with a symbol if 0 < y < +2^x - 4. +--- + gas/config/tc-loongarch.c | 27 +++++++--- + gas/testsuite/gas/loongarch/relax_align.d | 64 +++++++++++++---------- + gas/testsuite/gas/loongarch/relax_align.s | 20 +++++-- + 3 files changed, 72 insertions(+), 39 deletions(-) + +diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c +index 5e96f624..e6da4e1e 100644 +--- a/gas/config/tc-loongarch.c ++++ b/gas/config/tc-loongarch.c +@@ -1746,14 +1746,25 @@ loongarch_frag_align_code (int n, int max) + + nops = frag_more (worst_case_bytes); + +- s = symbol_find (".Lla-relax-align"); +- if (s == NULL) +- s = (symbolS *)local_symbol_make (".Lla-relax-align", now_seg, +- &zero_address_frag, 0); +- +- ex.X_add_symbol = s; +- ex.X_op = O_symbol; +- ex.X_add_number = (max << 8) | n; ++ /* If max <= 0, ignore max. ++ If max >= worst_case_bytes, max has no effect. ++ Similar to gas/write.c relax_segment function rs_align_code case: ++ if (fragP->fr_subtype != 0 && offset > fragP->fr_subtype). */ ++ if (max > 0 && (bfd_vma) max < worst_case_bytes) ++ { ++ s = symbol_find (".Lla-relax-align"); ++ if (s == NULL) ++ s = (symbolS *)local_symbol_make (".Lla-relax-align", now_seg, ++ &zero_address_frag, 0); ++ ex.X_add_symbol = s; ++ ex.X_op = O_symbol; ++ ex.X_add_number = (max << 8) | n; ++ } ++ else ++ { ++ ex.X_op = O_constant; ++ ex.X_add_number = worst_case_bytes; ++ } + + loongarch_make_nops (nops, worst_case_bytes); + +diff --git a/gas/testsuite/gas/loongarch/relax_align.d b/gas/testsuite/gas/loongarch/relax_align.d +index 2cc6c86d..fc1fd032 100644 +--- a/gas/testsuite/gas/loongarch/relax_align.d ++++ b/gas/testsuite/gas/loongarch/relax_align.d +@@ -1,4 +1,4 @@ +-#as: --no-warn ++#as: + #objdump: -dr + #skip: loongarch32-*-* + +@@ -8,29 +8,39 @@ + Disassembly of section .text: + + *0000000000000000 <.Lla-relax-align>: +- +0: +1a000004 +pcalau12i +\$a0, 0 +- +0: R_LARCH_PCALA_HI20 +L1 +- +0: R_LARCH_RELAX +\*ABS\* +- +4: +02c00084 +addi.d +\$a0, \$a0, 0 +- +4: R_LARCH_PCALA_LO12 +L1 +- +4: R_LARCH_RELAX +\*ABS\* +- +8: +03400000 +nop.* +- +8: R_LARCH_ALIGN +.Lla-relax-align\+0x4 +- +c: +03400000 +nop.* +- +10: +03400000 +nop.* +- +14: +1a000004 +pcalau12i +\$a0, 0 +- +14: R_LARCH_PCALA_HI20 +L1 +- +14: R_LARCH_RELAX +\*ABS\* +- +18: +02c00084 +addi.d +\$a0, \$a0, 0 +- +18: R_LARCH_PCALA_LO12 +L1 +- +18: R_LARCH_RELAX +\*ABS\* +- +1c: +03400000 +nop.* +- +1c: R_LARCH_ALIGN +.Lla-relax-align\+0x404 +- +20: +03400000 +nop.* +- +24: +03400000 +nop.* +- +28: +1a000004 +pcalau12i +\$a0, 0 +- +28: R_LARCH_PCALA_HI20 +L1 +- +28: R_LARCH_RELAX +\*ABS\* +- +2c: +02c00084 +addi.d +\$a0, \$a0, 0 +- +2c: R_LARCH_PCALA_LO12 +L1 +- +2c: R_LARCH_RELAX +\*ABS\* ++ +0: +4c000020 +ret ++ +4: +03400000 +nop ++ +4: R_LARCH_ALIGN +\*ABS\*\+0xc ++ +8: +03400000 +nop ++ +c: +03400000 +nop ++ +10: +4c000020 +ret ++ +14: +03400000 +nop ++ +14: R_LARCH_ALIGN +\*ABS\*\+0xc ++ +18: +03400000 +nop ++ +1c: +03400000 +nop ++ +20: +4c000020 +ret ++ +24: +03400000 +nop ++ +24: R_LARCH_ALIGN +.Lla-relax-align\+0x104 ++ +28: +03400000 +nop ++ +2c: +03400000 +nop ++ +30: +4c000020 +ret ++ +34: +03400000 +nop ++ +34: R_LARCH_ALIGN +.Lla-relax-align\+0xb04 ++ +38: +03400000 +nop ++ +3c: +03400000 +nop ++ +40: +4c000020 +ret ++ +44: +03400000 +nop ++ +44: R_LARCH_ALIGN +\*ABS\*\+0xc ++ +48: +03400000 +nop ++ +4c: +03400000 +nop ++ +50: +4c000020 +ret ++ +54: +03400000 +nop ++ +54: R_LARCH_ALIGN +\*ABS\*\+0xc ++ +58: +03400000 +nop ++ +5c: +03400000 +nop ++ +60: +4c000020 +ret ++ +64: +03400000 +nop ++ +64: R_LARCH_ALIGN +\*ABS\*\+0xc ++ +68: +03400000 +nop ++ +6c: +03400000 +nop ++ +70: +4c000020 +ret +diff --git a/gas/testsuite/gas/loongarch/relax_align.s b/gas/testsuite/gas/loongarch/relax_align.s +index c0177c88..4f4867fb 100644 +--- a/gas/testsuite/gas/loongarch/relax_align.s ++++ b/gas/testsuite/gas/loongarch/relax_align.s +@@ -1,7 +1,19 @@ ++# If max < -0x80000000, max becomes a positive number because type conversion ++# (bfd_signed_vma -> unsigned int). + .text + .L1: +- la.local $a0, L1 ++ ret + .align 4 +- la.local $a0, L1 +- .align 4, , 4 +- la.local $a0, L1 ++ ret ++ .align 4, , 0 ++ ret ++ .align 4, , 1 ++ ret ++ .align 4, , 11 ++ ret ++ .align 4, , 12 ++ ret ++ .align 4, , -1 ++ ret ++ .align 4, , -0x80000000 ++ ret +-- +2.33.0 +
View file
_service:tar_scm:LoongArch-implement-count_-leading-trailing-_zeros.patch
Added
@@ -0,0 +1,46 @@ +From 92fd8ea969cddf3434830ea3f3cfa48cd3e23f30 Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao <xry111@xry111.site> +Date: Mon, 7 Aug 2023 13:07:08 +0200 +Subject: PATCH 004/123 LoongArch: implement count_{leading,trailing}_zeros + +LoongArch always support clz and ctz instructions, so we can always use +__builtin_{clz,ctz} for count_{leading,trailing}_zeros. This improves +the code of libgcc, and also benefits Glibc once we merge longlong.h +there. + +Bootstrapped and regtested on loongarch64-linux-gnu. + +include/ + * longlong.h __loongarch__ (count_leading_zeros): Define. + __loongarch__ (count_trailing_zeros): Likewise. + __loongarch__ (COUNT_LEADING_ZEROS_0): Likewise. +--- + include/longlong.h | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/include/longlong.h b/include/longlong.h +index 9948a587..32d2048d 100644 +--- a/include/longlong.h ++++ b/include/longlong.h +@@ -593,6 +593,18 @@ extern UDItype __umulsidi3 (USItype, USItype); + #define UMUL_TIME 14 + #endif + ++#ifdef __loongarch__ ++# if W_TYPE_SIZE == 32 ++# define count_leading_zeros(count, x) ((count) = __builtin_clz (x)) ++# define count_trailing_zeros(count, x) ((count) = __builtin_ctz (x)) ++# define COUNT_LEADING_ZEROS_0 32 ++# elif W_TYPE_SIZE == 64 ++# define count_leading_zeros(count, x) ((count) = __builtin_clzll (x)) ++# define count_trailing_zeros(count, x) ((count) = __builtin_ctzll (x)) ++# define COUNT_LEADING_ZEROS_0 64 ++# endif ++#endif ++ + #if defined (__M32R__) && W_TYPE_SIZE == 32 + #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ + /* The cmp clears the condition bit. */ \ +-- +2.33.0 +
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_service:tar_scm:LoongArch-include-Add-support-for-tls-le-relax.patch
Added
@@ -0,0 +1,43 @@ +From fd100b34ac667ad62f57800762c76ac5272ceb16 Mon Sep 17 00:00:00 2001 +From: changjiachen <changjiachen@stu.xupt.edu.cn> +Date: Thu, 28 Dec 2023 19:57:30 +0800 +Subject: PATCH 032/123 LoongArch: include: Add support for tls le relax. + +Add new relocs number for tls le relax. + +include/ChangeLog: + + * elf/loongarch.h: + (RELOC_NUMBER (R_LARCH_TLS_LE_HI20_R, 121)): New relocs number. + (RELOC_NUMBER (R_LARCH_TLS_LE_ADD_R, 122)): Likewise. + (RELOC_NUMBER (R_LARCH_TLS_LE_LO12_R, 123)): Likewise. +--- + include/elf/loongarch.h | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/include/elf/loongarch.h b/include/elf/loongarch.h +index 6cfee164..1deb6ba1 100644 +--- a/include/elf/loongarch.h ++++ b/include/elf/loongarch.h +@@ -273,6 +273,18 @@ RELOC_NUMBER (R_LARCH_TLS_DESC64_HI12, 118) + RELOC_NUMBER (R_LARCH_TLS_DESC_LD, 119) + RELOC_NUMBER (R_LARCH_TLS_DESC_CALL, 120) + ++/* TLS-LE-LUI ++ lu12i.w rd,%le_hi20_r (sym). */ ++RELOC_NUMBER (R_LARCH_TLS_LE_HI20_R, 121) ++ ++/* TLS-LE-ADD ++ add.d rd,rj,rk,%le_add_r (sym). */ ++RELOC_NUMBER (R_LARCH_TLS_LE_ADD_R, 122) ++ ++/* TLS-LE-ST ++ st.w/addi.w/ld.w rd,rj,%le_lo12_r (sym). */ ++RELOC_NUMBER (R_LARCH_TLS_LE_LO12_R, 123) ++ + RELOC_NUMBER (R_LARCH_TLS_LD_PCREL20_S2, 124) + RELOC_NUMBER (R_LARCH_TLS_GD_PCREL20_S2, 125) + RELOC_NUMBER (R_LARCH_TLS_DESC_PCREL20_S2, 126) +-- +2.33.0 +
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_service:tar_scm:LoongArch-ld-Add-support-for-TLS-LE-symbol-with-adde.patch
Added
@@ -0,0 +1,105 @@ +From 7460efab086ff238d2b4de990a6d4f89efaafc23 Mon Sep 17 00:00:00 2001 +From: mengqinggang <mengqinggang@loongson.cn> +Date: Thu, 25 Jan 2024 09:32:14 +0800 +Subject: PATCH 052/123 LoongArch: ld: Add support for TLS LE symbol with + addend + +Add support for TLS LE symbol with addend, such as: + lu12i.w $t0, %le_hi20(a + 0x8) + ori $t0, $t0, %le_lo12(a + 0x8) +--- + bfd/elfnn-loongarch.c | 5 ++--- + .../ld-loongarch-elf/ld-loongarch-elf.exp | 1 + + ld/testsuite/ld-loongarch-elf/tls-le.d | 14 ++++++++++++++ + ld/testsuite/ld-loongarch-elf/tls-le.s | 18 ++++++++++++++++++ + 4 files changed, 35 insertions(+), 3 deletions(-) + create mode 100644 ld/testsuite/ld-loongarch-elf/tls-le.d + create mode 100644 ld/testsuite/ld-loongarch-elf/tls-le.s + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index f57b6152..858b95e1 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -3487,14 +3487,12 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, + relocation += rel->r_addend; + + RELOCATE_CALC_PC32_HI20 (relocation, pc); +- + break; + + case R_LARCH_TLS_LE_HI20_R: ++ relocation += rel->r_addend; + relocation -= elf_hash_table (info)->tls_sec->vma; +- + RELOCATE_TLS_TP32_HI20 (relocation); +- + break; + + case R_LARCH_PCALA_LO12: +@@ -3675,6 +3673,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, + case R_LARCH_TLS_LE64_HI12: + BFD_ASSERT (resolved_local && elf_hash_table (info)->tls_sec); + ++ relocation += rel->r_addend; + relocation -= elf_hash_table (info)->tls_sec->vma; + break; + +diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp +index c81f20af..46b53536 100644 +--- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp ++++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp +@@ -34,6 +34,7 @@ if istarget "loongarch64-*-*" { + run_dump_test "local-ifunc-reloc" + run_dump_test "anno-sym" + run_dump_test "pcala64" ++ run_dump_test "tls-le" + } + + if istarget "loongarch32-*-*" { +diff --git a/ld/testsuite/ld-loongarch-elf/tls-le.d b/ld/testsuite/ld-loongarch-elf/tls-le.d +new file mode 100644 +index 00000000..cbd6adb8 +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/tls-le.d +@@ -0,0 +1,14 @@ ++#ld: --no-relax ++#objdump: -d ++ ++.*: +file format .* ++ ++ ++Disassembly of section .text: ++ ++ *00000001200000e8 <_start>: ++ +1200000e8: +14000004 +lu12i.w +\$a0, 0 ++ +1200000ec: +03802085 +ori +\$a1, \$a0, 0x8 ++ +1200000f0: +14000004 +lu12i.w +\$a0, 0 ++ +1200000f4: +02c02085 +addi.d +\$a1, \$a0, 8 ++ +1200000f8: +4c000020 +ret +diff --git a/ld/testsuite/ld-loongarch-elf/tls-le.s b/ld/testsuite/ld-loongarch-elf/tls-le.s +new file mode 100644 +index 00000000..2e6a9de4 +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/tls-le.s +@@ -0,0 +1,18 @@ ++# Support for TLS LE symbols with addend ++ .text ++ .globl a ++ .section .tdata,"awT",@progbits ++ .align 2 ++ .type a, @object ++ .size a, 4 ++a: ++ .word 123 ++ ++ .text ++ .global _start ++_start: ++ lu12i.w $r4,%le_hi20(a + 0x8) ++ ori $r5,$r4,%le_lo12(a + 0x8) ++ lu12i.w $r4,%le_hi20_r(a + 0x8) ++ addi.d $r5,$r4,%le_lo12_r(a + 0x8) ++ jr $ra +-- +2.33.0 +
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_service:tar_scm:LoongArch-ld-Add-support-for-tls-le-relax.patch
Added
@@ -0,0 +1,410 @@ +From 752d56ec3ba19235fd3d75fd30adaa4bec10dded Mon Sep 17 00:00:00 2001 +From: changjiachen <changjiachen@stu.xupt.edu.cn> +Date: Thu, 28 Dec 2023 20:01:15 +0800 +Subject: PATCH 035/123 LoongArch: ld: Add support for tls le relax. + +Add tls le relax related testsuites in ld. + +The new test cases are mainly tested in three aspects: + +1. tls le relax function correctness test. +2. tls le relax boundary check test. +3. tls le relax function compatibility test. + +ld/testsuite/ChangeLog: + + * ld/testsuite/ld-loongarch-elf/relax.exp: Modify test. + * ld/testsuite/ld-loongarch-elf/old-tls-le.s: New test. + * ld/testsuite/ld-loongarch-elf/relax-bound-check-tls-le.s: Likewise. + * ld/testsuite/ld-loongarch-elf/tls-relax-compatible-check-new.s: Likewise. + * ld/testsuite/ld-loongarch-elf/relax-tls-le.s: Likewise. + * ld/testsuite/ld-loongarch-elf/tls-relax-compatible-check-old.s: Likewise. +--- + ld/testsuite/ld-loongarch-elf/old-tls-le.s | 23 +++ + .../relax-bound-check-tls-le.s | 53 ++++++ + ld/testsuite/ld-loongarch-elf/relax-tls-le.s | 26 +++ + ld/testsuite/ld-loongarch-elf/relax.exp | 151 +++++++++++++++++- + .../tls-relax-compatible-check-new.s | 35 ++++ + .../tls-relax-compatible-check-old.s | 33 ++++ + 6 files changed, 320 insertions(+), 1 deletion(-) + create mode 100644 ld/testsuite/ld-loongarch-elf/old-tls-le.s + create mode 100644 ld/testsuite/ld-loongarch-elf/relax-bound-check-tls-le.s + create mode 100644 ld/testsuite/ld-loongarch-elf/relax-tls-le.s + create mode 100644 ld/testsuite/ld-loongarch-elf/tls-relax-compatible-check-new.s + create mode 100644 ld/testsuite/ld-loongarch-elf/tls-relax-compatible-check-old.s + +diff --git a/ld/testsuite/ld-loongarch-elf/old-tls-le.s b/ld/testsuite/ld-loongarch-elf/old-tls-le.s +new file mode 100644 +index 00000000..be3d2b9c +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/old-tls-le.s +@@ -0,0 +1,23 @@ ++/* This test case mainly tests whether the original ++ tls le assembly instruction can be linked normally ++ after tls le relax is added to the current ld. */ ++ ++ .text ++ .globl aa ++ .section .tbss,"awT",@nobits ++ .align 2 ++ .type aa, @object ++ .size aa, 4 ++aa: ++ .space 4 ++ .text ++ .align 2 ++ .globl main ++ .type main, @function ++main: ++ lu12i.w $r12,%le_hi20(aa) ++ ori $r12,$r12,%le_lo12(aa) ++ add.d $r12,$r12,$r2 ++ addi.w $r13,$r0,2 # 0x2 ++ stptr.w $r13,$r12,0 ++ +diff --git a/ld/testsuite/ld-loongarch-elf/relax-bound-check-tls-le.s b/ld/testsuite/ld-loongarch-elf/relax-bound-check-tls-le.s +new file mode 100644 +index 00000000..b2a64b5d +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/relax-bound-check-tls-le.s +@@ -0,0 +1,53 @@ ++/* This test case mainly tests whether the address of the ++ tls le symbol can be resolved normally when the offset ++ of the symbol is greater than 0x800. (When the symbol ++ offset is greater than 0x800, relax is not performed). */ ++ ++ .text ++ .globl count1 ++ .section .tbss,"awT",@nobits ++ .align 2 ++ .type count1, @object ++ .size count1, 4 ++count1: ++ .space 0x400 ++ .globl count2 ++ .align 2 ++ .type count2, @object ++ .size count2, 4 ++count2: ++ .space 0x400 ++ .globl count3 ++ .align 2 ++ .type count3, @object ++ .size count3, 4 ++count3: ++ .space 0x400 ++ .globl count4 ++ .align 2 ++ .type count4, @object ++ .size count4, 4 ++count4: ++ .space 4 ++ .text ++ .align 2 ++ .globl main ++ .type main, @function ++main: ++ lu12i.w $r12,%le_hi20_r(count1) ++ add.d $r12,$r12,$r2,%le_add_r(count1) ++ addi.w $r13,$r0,1 ++ st.w $r13,$r12,%le_lo12_r(count1) ++ lu12i.w $r12,%le_hi20_r(count2) ++ add.d $r12,$r12,$r2,%le_add_r(count2) ++ addi.w $r13,$r0,2 ++ st.w $r13,$r12,%le_lo12_r(count2) ++ lu12i.w $r12,%le_hi20(count3) ++ add.d $r12,$r12,$r2,%le_add_r(count3) ++ addi.w $r13,$r0,3 ++ st.w $r13,$r12,%le_lo12_r(count3) ++ lu12i.w $r12,%le_hi20(count4) ++ add.d $r12,$r12,$r2,%le_add_r(count4) ++ addi.w $r13,$r0,4 ++ st.w $r13,$r12,%le_lo12_r(count4) ++ +diff --git a/ld/testsuite/ld-loongarch-elf/relax-tls-le.s b/ld/testsuite/ld-loongarch-elf/relax-tls-le.s +new file mode 100644 +index 00000000..1ea53baf +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/relax-tls-le.s +@@ -0,0 +1,26 @@ ++/* This test case mainly tests whether the tls le variable ++ address acquisition can be relax normally. ++ ++ before relax: after relax: ++ ++ lu12i.w $r12,%le_hi20_r(sym) ====> (instruction deleted). ++ add.d $r12,$r12,$r2,%le_add_r(sym) ====> (instruction deleted). ++ st.w $r13,$r12,%le_lo12_r(sym) ====> st.w $r13,$r2,%le_lo12_r(sym). */ ++ ++ .text ++ .globl a ++ .section .tbss,"awT",@nobits ++ .align 2 ++ .type a, @object ++ .size a, 4 ++a: ++ .space 4 ++ .text ++ .align 2 ++ .globl main ++ .type main, @function ++main: ++ lu12i.w $r12,%le_hi20_r(a) ++ add.d $r12,$r12,$r2,%le_add_r(a) ++ addi.w $r13,$r0,1 # 0x1 ++ st.w $r13,$r12,%le_lo12_r(a) +diff --git a/ld/testsuite/ld-loongarch-elf/relax.exp b/ld/testsuite/ld-loongarch-elf/relax.exp +index 77323d8d..b697d015 100644 +--- a/ld/testsuite/ld-loongarch-elf/relax.exp ++++ b/ld/testsuite/ld-loongarch-elf/relax.exp +@@ -33,8 +33,90 @@ if istarget loongarch64-*-* { + "relax" \ + \ + ++ set tls_relax_builds list \ ++ list \ ++ "tls_relax_builds" \ ++ "" \ ++ "" \ ++ {relax-tls-le.s} \ ++ {} \ ++ "relax-tls-le" \ ++ \ ++ ++ set tls_no_relax_builds list \ ++ list \ ++ "tls_no_relax_builds" \ ++ "-Wl,--no-relax" \ ++ "" \ ++ {relax-tls-le.s} \ ++ {} \ ++ "no-relax-tls-le" \ ++ \ ++ ++ ++ set relax_bound_check list \ ++ list \ ++ "relax_bound_check" \ ++ "" \ ++ "" \ ++ {relax-bound-check-tls-le.s} \ ++ {} \ ++ "relax-bound-check-tls-le" \ ++ \ ++ ++ set no_relax_bound_check list \ ++ list \ ++ "no_relax_bound_check" \ ++ "-Wl,--no-relax" \ ++ "" \
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_service:tar_scm:LoongArch-ld-Adjusted-some-code-order-in-relax.exp.patch
Added
@@ -0,0 +1,340 @@ +From 075962ddaa562d7d9b9bd9de8a5204e3913ea36a Mon Sep 17 00:00:00 2001 +From: changjiachen <changjiachen@stu.xupt.edu.cn> +Date: Thu, 4 Jan 2024 14:06:09 +0800 +Subject: PATCH 042/123 LoongArch: ld: Adjusted some code order in relax.exp. + + ld/testsuite/ChangeLog: + + * ld/testsuite/ld-loongarch-elf/relax.exp: Modify test. +--- + ld/testsuite/ld-loongarch-elf/relax.exp | 298 ++++++++++++------------ + 1 file changed, 149 insertions(+), 149 deletions(-) + +diff --git a/ld/testsuite/ld-loongarch-elf/relax.exp b/ld/testsuite/ld-loongarch-elf/relax.exp +index 6c65318a..aed8457d 100644 +--- a/ld/testsuite/ld-loongarch-elf/relax.exp ++++ b/ld/testsuite/ld-loongarch-elf/relax.exp +@@ -33,90 +33,8 @@ if istarget loongarch64-*-* { + "relax" \ + \ + +- set tls_relax_builds list \ +- list \ +- "tls_relax_builds" \ +- "" \ +- "" \ +- {relax-tls-le.s} \ +- {} \ +- "relax-tls-le" \ +- \ +- +- set tls_no_relax_builds list \ +- list \ +- "tls_no_relax_builds" \ +- "-Wl,--no-relax" \ +- "" \ +- {relax-tls-le.s} \ +- {} \ +- "no-relax-tls-le" \ +- \ +- +- +- set relax_bound_check list \ +- list \ +- "relax_bound_check" \ +- "" \ +- "" \ +- {relax-bound-check-tls-le.s} \ +- {} \ +- "relax-bound-check-tls-le" \ +- \ +- +- set no_relax_bound_check list \ +- list \ +- "no_relax_bound_check" \ +- "-Wl,--no-relax" \ +- "" \ +- {relax-bound-check-tls-le.s} \ +- {} \ +- "no-relax-bound-check-tls-le" \ +- \ +- +- +- set old_tls_le list \ +- list \ +- "old_tls_le" \ +- "" \ +- "" \ +- {old-tls-le.s} \ +- {} \ +- "old-tls-le" \ +- \ +- +- +- set relax_compatible list \ +- list \ +- "relax_compatible" \ +- "" \ +- "" \ +- {tls-relax-compatible-check-new.s tls-relax-compatible-check-old.s} \ +- {} \ +- "realx-compatible" \ +- \ +- +- +- set no_relax_compatible list \ +- list \ +- "no_relax_compatible" \ +- "-Wl,--no-relax" \ +- "" \ +- {tls-relax-compatible-check-new.s tls-relax-compatible-check-old.s} \ +- {} \ +- "no-realx-compatible" \ +- \ +- +- + + run_cc_link_tests $pre_builds +- run_cc_link_tests $tls_relax_builds +- run_cc_link_tests $tls_no_relax_builds +- run_cc_link_tests $relax_bound_check +- run_cc_link_tests $no_relax_bound_check +- run_cc_link_tests $old_tls_le +- run_cc_link_tests $relax_compatible +- run_cc_link_tests $no_relax_compatible + + if file exist "tmpdir/relax" { + set objdump_output run_host_cmd "objdump" "-d tmpdir/relax" +@@ -173,6 +91,155 @@ if istarget loongarch64-*-* { + } + } + ++ run_ld_link_tests \ ++ list \ ++ list \ ++ "loongarch tls le relax .exe build" \ ++ "" "" \ ++ "" \ ++ {relax-tls-le.s} \ ++ {} \ ++ "relax-tls-le" \ ++ \ ++ ++ ++ if file exist "tmpdir/relax-tls-le" { ++ set objdump_output1 run_host_cmd "objdump" "-d tmpdir/relax-tls-le" ++ if { regexp ".addi.*st.*" $objdump_output1 } { ++ pass "loongarch relax success" ++ } { ++ fail "loongarch relax fail" ++ } ++ } ++ ++ run_ld_link_tests \ ++ list \ ++ list \ ++ "loongarch tls le no relax .exe build" \ ++ "--no-relax" "" \ ++ "" \ ++ {relax-tls-le.s} \ ++ {} \ ++ "no-relax-tls-le" \ ++ \ ++ ++ ++ if file exist "tmpdir/no-relax-tls-le" { ++ set objdump_output2 run_host_cmd "objdump" "-d tmpdir/no-relax-tls-le" ++ if { regexp ".*lu12i.*add.*addi.*st.*" $objdump_output2 } { ++ pass "loongarch no-relax success" ++ } { ++ fail "loongarch no-relax fail" ++ } ++ } ++ ++ run_ld_link_tests \ ++ list \ ++ list \ ++ "loongarch old tls le .exe build" \ ++ "" "" \ ++ "" \ ++ {old-tls-le.s} \ ++ {} \ ++ "old-tls-le" \ ++ \ ++ ++ ++ if file exist "tmpdir/old-tls-le" { ++ set objdump_output3 run_host_cmd "objdump" "-d tmpdir/old-tls-le" ++ if { regexp ".*lu12i.*ori.*add.*addi.*stptr.*" $objdump_output3 } { ++ pass "loongarch old tls le success" ++ } { ++ fail "loongarch old tls le fail" ++ } ++ } ++ ++ run_ld_link_tests \ ++ list \ ++ list \ ++ "loongarch tls le realx compatible .exe build" \ ++ "" "" \ ++ "" \ ++ {tls-relax-compatible-check-new.s tls-relax-compatible-check-old.s} \ ++ {} \ ++ "realx-compatible" \ ++ \ ++ ++ ++ if file exist "tmpdir/realx-compatible" { ++ set objdump_output4 run_host_cmd "objdump" "-d tmpdir/realx-compatible" ++ if { regexp ".addi.*st.*" $objdump_output4 && \ ++ regexp ".*lu12i.*ori.*add.*addi.*stptr.*" $objdump_output4 } { ++ pass "loongarch tls le relax compatible check success" ++ } { ++ fail "loongarch tls le relax compatible check fail" ++ } ++ } ++ ++ run_ld_link_tests \ ++ list \ ++ list \
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_service:tar_scm:LoongArch-ld-Fix-other-pop-relocs-overflow-check-and.patch
Added
@@ -0,0 +1,787 @@ +From 4fcc588a781a65c6a939dc74644c98a0f039f879 Mon Sep 17 00:00:00 2001 +From: Jinyang He <hejinyang@loongson.cn> +Date: Tue, 5 Sep 2023 10:31:28 +0800 +Subject: PATCH 059/123 LoongArch: ld: Fix other pop relocs overflow check + and add tests + +Add reloc_unsign_bits() to fix others sop_pop relocs overflow check. +Then add over/underflow tests for relocs B*, SOP_POP* and PCREL20_S2. + +bfd/ChangeLog: + + * bfd/elfxx-loongarch.c: Add reloc_unsign_bits(). + +ld/ChangeLog: + + * ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp: Add tests. + * ld/testsuite/ld-loongarch-elf/abi1_max_imm.dd: New test. + * ld/testsuite/ld-loongarch-elf/abi1_max_imm.s: New test. + * ld/testsuite/ld-loongarch-elf/abi1_sops.s: New test. + * ld/testsuite/ld-loongarch-elf/abi2_max_imm.s: New test. + * ld/testsuite/ld-loongarch-elf/abi2_overflows.s: New test. + * ld/testsuite/ld-loongarch-elf/max_imm_b16.d: New test. + * ld/testsuite/ld-loongarch-elf/max_imm_b21.d: New test. + * ld/testsuite/ld-loongarch-elf/max_imm_b26.d: New test. + * ld/testsuite/ld-loongarch-elf/max_imm_pcrel20.d: New test. + * ld/testsuite/ld-loongarch-elf/overflow_b16.d: New test. + * ld/testsuite/ld-loongarch-elf/overflow_b21.d: New test. + * ld/testsuite/ld-loongarch-elf/overflow_b26.d: New test. + * ld/testsuite/ld-loongarch-elf/overflow_pcrel20.d: New test. + * ld/testsuite/ld-loongarch-elf/overflow_s_0_10_10_16_s2.d: New test. + * ld/testsuite/ld-loongarch-elf/overflow_s_0_5_10_16_s2.d: New test. + * ld/testsuite/ld-loongarch-elf/overflow_s_10_12.d: New test. + * ld/testsuite/ld-loongarch-elf/overflow_s_10_16.d: New test. + * ld/testsuite/ld-loongarch-elf/overflow_s_10_16_s2.d: New test. + * ld/testsuite/ld-loongarch-elf/overflow_s_10_5.d: New test. + * ld/testsuite/ld-loongarch-elf/overflow_s_5_20.d: New test. + * ld/testsuite/ld-loongarch-elf/overflow_u.d: New test. + * ld/testsuite/ld-loongarch-elf/overflow_u_10_12.d: New test. + * ld/testsuite/ld-loongarch-elf/underflow_b16.d: New test. + * ld/testsuite/ld-loongarch-elf/underflow_b21.d: New test. + * ld/testsuite/ld-loongarch-elf/underflow_b26.d: New test. + * ld/testsuite/ld-loongarch-elf/underflow_pcrel20.d: New test. + * ld/testsuite/ld-loongarch-elf/underflow_s_0_10_10_16_s2.d: New test. + * ld/testsuite/ld-loongarch-elf/underflow_s_0_5_10_16_s2.d: New test. + * ld/testsuite/ld-loongarch-elf/underflow_s_10_12.d: New test. + * ld/testsuite/ld-loongarch-elf/underflow_s_10_16.d: New test. + * ld/testsuite/ld-loongarch-elf/underflow_s_10_16_s2.d: New test. + * ld/testsuite/ld-loongarch-elf/underflow_s_10_5.d: New test. + * ld/testsuite/ld-loongarch-elf/underflow_s_5_20.d: New test. +--- + bfd/elfxx-loongarch.c | 34 +++++++++++---- + ld/testsuite/ld-loongarch-elf/abi1_max_imm.dd | 18 ++++++++ + ld/testsuite/ld-loongarch-elf/abi1_max_imm.s | 39 +++++++++++++++++ + ld/testsuite/ld-loongarch-elf/abi1_sops.s | 43 +++++++++++++++++++ + ld/testsuite/ld-loongarch-elf/abi2_max_imm.s | 24 +++++++++++ + .../ld-loongarch-elf/abi2_overflows.s | 24 +++++++++++ + .../ld-loongarch-elf/ld-loongarch-elf.exp | 39 +++++++++++++++++ + ld/testsuite/ld-loongarch-elf/max_imm_b16.d | 9 ++++ + ld/testsuite/ld-loongarch-elf/max_imm_b21.d | 9 ++++ + ld/testsuite/ld-loongarch-elf/max_imm_b26.d | 9 ++++ + .../ld-loongarch-elf/max_imm_pcrel20.d | 9 ++++ + ld/testsuite/ld-loongarch-elf/overflow_b16.d | 4 ++ + ld/testsuite/ld-loongarch-elf/overflow_b21.d | 4 ++ + ld/testsuite/ld-loongarch-elf/overflow_b26.d | 4 ++ + .../ld-loongarch-elf/overflow_pcrel20.d | 4 ++ + .../overflow_s_0_10_10_16_s2.d | 4 ++ + .../overflow_s_0_5_10_16_s2.d | 4 ++ + .../ld-loongarch-elf/overflow_s_10_12.d | 4 ++ + .../ld-loongarch-elf/overflow_s_10_16.d | 4 ++ + .../ld-loongarch-elf/overflow_s_10_16_s2.d | 4 ++ + .../ld-loongarch-elf/overflow_s_10_5.d | 4 ++ + .../ld-loongarch-elf/overflow_s_5_20.d | 4 ++ + ld/testsuite/ld-loongarch-elf/overflow_u.d | 4 ++ + .../ld-loongarch-elf/overflow_u_10_12.d | 4 ++ + ld/testsuite/ld-loongarch-elf/underflow_b16.d | 4 ++ + ld/testsuite/ld-loongarch-elf/underflow_b21.d | 4 ++ + ld/testsuite/ld-loongarch-elf/underflow_b26.d | 4 ++ + .../ld-loongarch-elf/underflow_pcrel20.d | 4 ++ + .../underflow_s_0_10_10_16_s2.d | 4 ++ + .../underflow_s_0_5_10_16_s2.d | 4 ++ + .../ld-loongarch-elf/underflow_s_10_12.d | 4 ++ + .../ld-loongarch-elf/underflow_s_10_16.d | 4 ++ + .../ld-loongarch-elf/underflow_s_10_16_s2.d | 4 ++ + .../ld-loongarch-elf/underflow_s_10_5.d | 4 ++ + .../ld-loongarch-elf/underflow_s_5_20.d | 4 ++ + 35 files changed, 344 insertions(+), 9 deletions(-) + create mode 100644 ld/testsuite/ld-loongarch-elf/abi1_max_imm.dd + create mode 100644 ld/testsuite/ld-loongarch-elf/abi1_max_imm.s + create mode 100644 ld/testsuite/ld-loongarch-elf/abi1_sops.s + create mode 100644 ld/testsuite/ld-loongarch-elf/abi2_max_imm.s + create mode 100644 ld/testsuite/ld-loongarch-elf/abi2_overflows.s + create mode 100644 ld/testsuite/ld-loongarch-elf/max_imm_b16.d + create mode 100644 ld/testsuite/ld-loongarch-elf/max_imm_b21.d + create mode 100644 ld/testsuite/ld-loongarch-elf/max_imm_b26.d + create mode 100644 ld/testsuite/ld-loongarch-elf/max_imm_pcrel20.d + create mode 100644 ld/testsuite/ld-loongarch-elf/overflow_b16.d + create mode 100644 ld/testsuite/ld-loongarch-elf/overflow_b21.d + create mode 100644 ld/testsuite/ld-loongarch-elf/overflow_b26.d + create mode 100644 ld/testsuite/ld-loongarch-elf/overflow_pcrel20.d + create mode 100644 ld/testsuite/ld-loongarch-elf/overflow_s_0_10_10_16_s2.d + create mode 100644 ld/testsuite/ld-loongarch-elf/overflow_s_0_5_10_16_s2.d + create mode 100644 ld/testsuite/ld-loongarch-elf/overflow_s_10_12.d + create mode 100644 ld/testsuite/ld-loongarch-elf/overflow_s_10_16.d + create mode 100644 ld/testsuite/ld-loongarch-elf/overflow_s_10_16_s2.d + create mode 100644 ld/testsuite/ld-loongarch-elf/overflow_s_10_5.d + create mode 100644 ld/testsuite/ld-loongarch-elf/overflow_s_5_20.d + create mode 100644 ld/testsuite/ld-loongarch-elf/overflow_u.d + create mode 100644 ld/testsuite/ld-loongarch-elf/overflow_u_10_12.d + create mode 100644 ld/testsuite/ld-loongarch-elf/underflow_b16.d + create mode 100644 ld/testsuite/ld-loongarch-elf/underflow_b21.d + create mode 100644 ld/testsuite/ld-loongarch-elf/underflow_b26.d + create mode 100644 ld/testsuite/ld-loongarch-elf/underflow_pcrel20.d + create mode 100644 ld/testsuite/ld-loongarch-elf/underflow_s_0_10_10_16_s2.d + create mode 100644 ld/testsuite/ld-loongarch-elf/underflow_s_0_5_10_16_s2.d + create mode 100644 ld/testsuite/ld-loongarch-elf/underflow_s_10_12.d + create mode 100644 ld/testsuite/ld-loongarch-elf/underflow_s_10_16.d + create mode 100644 ld/testsuite/ld-loongarch-elf/underflow_s_10_16_s2.d + create mode 100644 ld/testsuite/ld-loongarch-elf/underflow_s_10_5.d + create mode 100644 ld/testsuite/ld-loongarch-elf/underflow_s_5_20.d + +diff --git a/bfd/elfxx-loongarch.c b/bfd/elfxx-loongarch.c +index 127f3548..ee1323ea 100644 +--- a/bfd/elfxx-loongarch.c ++++ b/bfd/elfxx-loongarch.c +@@ -55,6 +55,8 @@ static bool + reloc_bits (bfd *abfd, reloc_howto_type *howto, bfd_vma *val); + static bool + reloc_sign_bits (bfd *abfd, reloc_howto_type *howto, bfd_vma *fix_val); ++static bool ++reloc_unsign_bits (bfd *abfd, reloc_howto_type *howto, bfd_vma *fix_val); + + static bfd_reloc_status_type + loongarch_elf_add_sub_reloc (bfd *, arelent *, asymbol *, void *, +@@ -415,7 +417,7 @@ static loongarch_reloc_howto_type loongarch_howto_table = + 0x7c00, /* dst_mask */ + false, /* pcrel_offset */ + BFD_RELOC_LARCH_SOP_POP_32_S_10_5, /* bfd_reloc_code_real_type */ +- reloc_bits, /* adjust_reloc_bits */ ++ reloc_sign_bits, /* adjust_reloc_bits */ + NULL), /* larch_reloc_type_name */ + + LOONGARCH_HOWTO (R_LARCH_SOP_POP_32_U_10_12, /* type (39). */ +@@ -432,7 +434,7 @@ static loongarch_reloc_howto_type loongarch_howto_table = + 0x3ffc00, /* dst_mask */ + false, /* pcrel_offset */ + BFD_RELOC_LARCH_SOP_POP_32_U_10_12, /* bfd_reloc_code_real_type */ +- reloc_bits, /* adjust_reloc_bits */ ++ reloc_unsign_bits, /* adjust_reloc_bits */ + NULL), /* larch_reloc_type_name */ + + LOONGARCH_HOWTO (R_LARCH_SOP_POP_32_S_10_12, /* type (40). */ +@@ -449,7 +451,7 @@ static loongarch_reloc_howto_type loongarch_howto_table = + 0x3ffc00, /* dst_mask */ + false, /* pcrel_offset */ + BFD_RELOC_LARCH_SOP_POP_32_S_10_12, /* bfd_reloc_code_real_type */ +- reloc_bits, /* adjust_reloc_bits */ ++ reloc_sign_bits, /* adjust_reloc_bits */ + NULL), /* larch_reloc_type_name */ + + LOONGARCH_HOWTO (R_LARCH_SOP_POP_32_S_10_16, /* type (41). */ +@@ -466,7 +468,7 @@ static loongarch_reloc_howto_type loongarch_howto_table = + 0x3fffc00, /* dst_mask */ + false, /* pcrel_offset */ + BFD_RELOC_LARCH_SOP_POP_32_S_10_16, /* bfd_reloc_code_real_type */ +- reloc_bits, /* adjust_reloc_bits */ ++ reloc_sign_bits, /* adjust_reloc_bits */ + NULL), /* larch_reloc_type_name */ + + LOONGARCH_HOWTO (R_LARCH_SOP_POP_32_S_10_16_S2, /* type (42). */ +@@ -500,7 +502,7 @@ static loongarch_reloc_howto_type loongarch_howto_table = + 0x1ffffe0, /* dst_mask */ + false, /* pcrel_offset */ + BFD_RELOC_LARCH_SOP_POP_32_S_5_20, /* bfd_reloc_code_real_type */ +- reloc_bits, /* adjust_reloc_bits */ ++ reloc_sign_bits, /* adjust_reloc_bits */ + NULL), /* larch_reloc_type_name */ + + LOONGARCH_HOWTO (R_LARCH_SOP_POP_32_S_0_5_10_16_S2, +@@ -554,7 +556,7 @@ static loongarch_reloc_howto_type loongarch_howto_table = + 0x00000000ffffffff, /* dst_mask */ + false, /* pcrel_offset */ + BFD_RELOC_LARCH_SOP_POP_32_U, /* bfd_reloc_code_real_type */ +- reloc_bits, /* adjust_reloc_bits */ ++ reloc_unsign_bits, /* adjust_reloc_bits */ + NULL), /* larch_reloc_type_name */ + + /* 8-bit in-place addition, for local label subtraction. */ +@@ -1991,9 +1993,11 @@ reloc_bits (bfd *abfd ATTRIBUTE_UNUSED, + } + + static bool +-reloc_sign_bits (bfd *abfd, reloc_howto_type *howto, bfd_vma *fix_val) ++reloc_bits_sanity (bfd *abfd, reloc_howto_type *howto, bfd_vma *fix_val, ++ unsigned int sign) + { +- if (howto->complain_on_overflow != complain_overflow_signed) ++ if ((sign && howto->complain_on_overflow != complain_overflow_signed) ++ || (!sign && howto->complain_on_overflow != complain_overflow_unsigned)) + return false;
View file
_service:tar_scm:LoongArch-ld-Move-.got-.got.plt-before-.data-and-pro.patch
Added
@@ -0,0 +1,96 @@ +From b3c4d41eedd38561194a8de8c530e318f621660c Mon Sep 17 00:00:00 2001 +From: mengqinggang <mengqinggang@loongson.cn> +Date: Wed, 3 Apr 2024 10:20:27 +0800 +Subject: PATCH 078/123 LoongArch: ld: Move .got .got.plt before .data and + protect .got with relro + +Move .got .got.plt before .data so .got can be protected with -zrelro. +And the first two entries of .got.plt (_dl_runtime_resolve and link map) +are placed within the relro region. +--- + bfd/elfnn-loongarch.c | 2 ++ + ld/emulparams/elf64loongarch-defs.sh | 5 ++++- + ld/testsuite/ld-loongarch-elf/data-got.d | 16 ++++++++++++++++ + ld/testsuite/ld-loongarch-elf/data-got.s | 6 ++++++ + .../ld-loongarch-elf/ld-loongarch-elf.exp | 1 + + 5 files changed, 29 insertions(+), 1 deletion(-) + create mode 100644 ld/testsuite/ld-loongarch-elf/data-got.d + create mode 100644 ld/testsuite/ld-loongarch-elf/data-got.s + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index 7f98dce1..36f1cfd5 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -127,6 +127,8 @@ struct loongarch_elf_link_hash_table + + #define GOT_ENTRY_SIZE (LARCH_ELF_WORD_BYTES) + ++/* Reserve two entries of GOTPLT for ld.so, one is used for PLT ++ resolver _dl_runtime_resolve, the other is used for link map. */ + #define GOTPLT_HEADER_SIZE (GOT_ENTRY_SIZE * 2) + + #define elf_backend_want_got_plt 1 +diff --git a/ld/emulparams/elf64loongarch-defs.sh b/ld/emulparams/elf64loongarch-defs.sh +index c793f5d8..a8147bf7 100644 +--- a/ld/emulparams/elf64loongarch-defs.sh ++++ b/ld/emulparams/elf64loongarch-defs.sh +@@ -34,6 +34,9 @@ TEXT_START_ADDR=0x120000000 + MAXPAGESIZE="CONSTANT (MAXPAGESIZE)" + COMMONPAGESIZE="CONSTANT (COMMONPAGESIZE)" + +-SEPARATE_GOTPLT=0 ++# Put .got before .data ++DATA_GOT=" " ++# First two entries for PLT resolver _dl_runtime_resolve and link map. ++SEPARATE_GOTPLT="SIZEOF (.got.plt) >= 16 ? 16 : 0" + INITIAL_READONLY_SECTIONS=".interp : { *(.interp) } ${CREATE_PIE-${INITIAL_READONLY_SECTIONS}}" + INITIAL_READONLY_SECTIONS="${RELOCATING+${CREATE_SHLIB-${INITIAL_READONLY_SECTIONS}}}" +diff --git a/ld/testsuite/ld-loongarch-elf/data-got.d b/ld/testsuite/ld-loongarch-elf/data-got.d +new file mode 100644 +index 00000000..a754478a +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/data-got.d +@@ -0,0 +1,16 @@ ++# line 11 test the first two entries of .got.plt in relro region ++# relro segment size is .dynamic size + .got size + 0x10 ++# line 13 test .got .got.plt before .got ++# line 15 test .got in relro segment ++#as: ++#ld: -shared -z relro --hash-style=both ++#readelf: -l --wide ++#skip: loongarch32-*-* ++ ++#... ++ GNU_RELRO 0x003c10 0x0000000000007c10 0x0000000000007c10 0x0003f0 0x0003f0 R 0x1 ++#... ++ 01 .dynamic .got .got.plt .data ++#... ++ 03 .dynamic .got ++#pass +diff --git a/ld/testsuite/ld-loongarch-elf/data-got.s b/ld/testsuite/ld-loongarch-elf/data-got.s +new file mode 100644 +index 00000000..364fcf64 +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/data-got.s +@@ -0,0 +1,6 @@ ++.text ++b foo ++.section .got ++.space 0x2a8, 4 ++.data ++.zero 24 +diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp +index 0121cad9..fc7b5bfe 100644 +--- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp ++++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp +@@ -133,6 +133,7 @@ if istarget "loongarch64-*-*" { + run_dump_test "tlsdesc-dso" + run_dump_test "desc-norelax" + run_dump_test "desc-relax" ++ run_dump_test "data-got" + } + + if check_pie_support { +-- +2.33.0 +
View file
_service:tar_scm:LoongArch-ld-Report-an-error-when-seeing-an-unrecogn.patch
Added
@@ -0,0 +1,40 @@ +From ec2d7d7fe1c2bc448ff77a192fc71be1bee87593 Mon Sep 17 00:00:00 2001 +From: Lulu Cai <cailulu@loongson.cn> +Date: Thu, 21 Mar 2024 15:16:05 +0800 +Subject: PATCH 079/123 LoongArch: ld:Report an error when seeing an + unrecognized relocation + +If we generate an object file using an assembler with the new +relocations added, and then linking those files with an older +linker, the link will still complete and the linked file will +be generated. +In this case we should report an error instead of continuing +the linking process. +--- + bfd/elfnn-loongarch.c | 9 +++++++-- + 1 file changed, 7 insertions(+), 2 deletions(-) + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index 36f1cfd5..70ef28f3 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -2610,9 +2610,14 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, + bfd_vma relocation, off, ie_off, desc_off; + int i, j; + ++ /* When an unrecognized relocation is encountered, which usually ++ occurs when using a newer assembler but an older linker, an error ++ should be reported instead of continuing to the next relocation. */ + howto = loongarch_elf_rtype_to_howto (input_bfd, r_type); +- if (howto == NULL || r_type == R_LARCH_GNU_VTINHERIT +- || r_type == R_LARCH_GNU_VTENTRY) ++ if (howto == NULL) ++ return _bfd_unrecognized_reloc (input_bfd, input_section, r_type); ++ ++ if (r_type == R_LARCH_GNU_VTINHERIT || r_type == R_LARCH_GNU_VTENTRY) + continue; + + /* This is a final link. */ +-- +2.33.0 +
View file
_service:tar_scm:LoongArch-ld-Simplify-inserting-IRELATIVE-relocation.patch
Added
@@ -0,0 +1,184 @@ +From 2c70ecb7fd4c90282d75ef7e30f2afdee94dc02e Mon Sep 17 00:00:00 2001 +From: mengqinggang <mengqinggang@loongson.cn> +Date: Tue, 11 Jul 2023 11:21:18 +0800 +Subject: PATCH 002/123 LoongArch: ld: Simplify inserting IRELATIVE + relocations to .rela.dyn + +In LoongArch, the R_LARCH_IRELATIVE relocations for local ifunc symbols are +in .rela.dyn. Before, this is done by loongarch_elf_finish_dynamic_sections. +But this function is called after elf_link_sort_relocs, it need to find a +null slot to insert IRELATIVE relocation. + +Now, it is processed by elf_loongarch_output_arch_local_syms before +elf_link_sort_relocs, just need to call loongarch_elf_append_rela to +insert IRELATIVE relocation. + +bfd/ChangeLog: + + * elfnn-loongarch.c (elfNN_allocate_local_ifunc_dynrelocs): Return + type change to int. + (loongarch_elf_size_dynamic_sections): Delete (void *). + (loongarch_elf_finish_dynamic_symbol): Use loongarch_elf_append_rela + insert IRELATIVE relocation to .rela.dyn. + (elfNN_loongarch_finish_local_dynamic_symbol): Return type change to + int. + (loongarch_elf_finish_dynamic_sections): Delete process of local + ifunc symbols. + (elf_backend_output_arch_local_syms): New. + +ld/ChangeLog: + + * testsuite/ld-loongarch-elf/local-ifunc-reloc.d: Regenerated. +--- + bfd/elfnn-loongarch.c | 67 +++++++++---------- + .../ld-loongarch-elf/local-ifunc-reloc.d | 2 +- + 2 files changed, 34 insertions(+), 35 deletions(-) + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index f7dc7279..2fe4924b 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -1538,7 +1538,7 @@ elfNN_allocate_ifunc_dynrelocs (struct elf_link_hash_entry *h, void *inf) + /* Allocate space in .plt, .got and associated reloc sections for + ifunc dynamic relocs. */ + +-static bool ++static int + elfNN_allocate_local_ifunc_dynrelocs (void **slot, void *inf) + { + struct elf_link_hash_entry *h = (struct elf_link_hash_entry *) *slot; +@@ -1700,7 +1700,7 @@ loongarch_elf_size_dynamic_sections (bfd *output_bfd, + + /* Allocate .plt and .got entries, and space for local ifunc symbols. */ + htab_traverse (htab->loc_hash_table, +- (void *) elfNN_allocate_local_ifunc_dynrelocs, info); ++ elfNN_allocate_local_ifunc_dynrelocs, info); + + /* Don't allocate .got.plt section if there are no PLT. */ + if (htab->elf.sgotplt && htab->elf.sgotplt->size == GOTPLT_HEADER_SIZE +@@ -4049,12 +4049,6 @@ loongarch_elf_finish_dynamic_symbol (bfd *output_bfd, + { + struct loongarch_elf_link_hash_table *htab = loongarch_elf_hash_table (info); + const struct elf_backend_data *bed = get_elf_backend_data (output_bfd); +- asection *rela_dyn = bfd_get_section_by_name (output_bfd, ".rela.dyn"); +- struct bfd_link_order *lo = NULL; +- Elf_Internal_Rela *slot = NULL, *last_slot = NULL; +- +- if (rela_dyn) +- lo = rela_dyn->map_head.link_order; + + if (h->plt.offset != MINUS_ONE) + { +@@ -4064,7 +4058,6 @@ loongarch_elf_finish_dynamic_symbol (bfd *output_bfd, + uint32_t plt_entryPLT_ENTRY_INSNS; + bfd_byte *loc; + Elf_Internal_Rela rela; +- asection *rela_sec = NULL; + + if (htab->elf.splt) + { +@@ -4122,26 +4115,7 @@ loongarch_elf_finish_dynamic_symbol (bfd *output_bfd, + + h->root.u.def.section->output_section->vma + + h->root.u.def.section->output_offset); + +- /* Find the space after dyn sort. */ +- while (slot == last_slot || slot->r_offset != 0) +- { +- if (slot != last_slot) +- { +- slot++; +- continue; +- } +- +- BFD_ASSERT (lo != NULL); +- rela_sec = lo->u.indirect.section; +- lo = lo->next; +- +- slot = (Elf_Internal_Rela *)rela_sec->contents; +- last_slot = (Elf_Internal_Rela *)(rela_sec->contents + +- rela_sec->size); +- } +- +- bed->s->swap_reloca_out (output_bfd, &rela, (bfd_byte *)slot); +- rela_sec->reloc_count++; ++ loongarch_elf_append_rela (output_bfd, relplt, &rela); + } + else + { +@@ -4308,7 +4282,7 @@ loongarch_finish_dyn (bfd *output_bfd, struct bfd_link_info *info, bfd *dynobj, + /* Finish up local dynamic symbol handling. We set the contents of + various dynamic sections here. */ + +-static bool ++static int + elfNN_loongarch_finish_local_dynamic_symbol (void **slot, void *inf) + { + struct elf_link_hash_entry *h = (struct elf_link_hash_entry *) *slot; +@@ -4317,6 +4291,33 @@ elfNN_loongarch_finish_local_dynamic_symbol (void **slot, void *inf) + return loongarch_elf_finish_dynamic_symbol (info->output_bfd, info, h, NULL); + } + ++/* Value of struct elf_backend_data->elf_backend_output_arch_local_syms, ++ this function is called before elf_link_sort_relocs. ++ So relocation R_LARCH_IRELATIVE for local ifunc can be append to ++ .rela.dyn (.rela.got) by loongarch_elf_append_rela. */ ++ ++static bool ++elf_loongarch_output_arch_local_syms ++ (bfd *output_bfd ATTRIBUTE_UNUSED, ++ struct bfd_link_info *info, ++ void *flaginfo ATTRIBUTE_UNUSED, ++ int (*func) (void *, const char *, ++ Elf_Internal_Sym *, ++ asection *, ++ struct elf_link_hash_entry *) ATTRIBUTE_UNUSED) ++{ ++ struct loongarch_elf_link_hash_table *htab = loongarch_elf_hash_table (info); ++ if (htab == NULL) ++ return false; ++ ++ /* Fill PLT and GOT entries for local STT_GNU_IFUNC symbols. */ ++ htab_traverse (htab->loc_hash_table, ++ elfNN_loongarch_finish_local_dynamic_symbol, ++ info); ++ ++ return true; ++} ++ + static bool + loongarch_elf_finish_dynamic_sections (bfd *output_bfd, + struct bfd_link_info *info) +@@ -4395,10 +4396,6 @@ loongarch_elf_finish_dynamic_sections (bfd *output_bfd, + elf_section_data (output_section)->this_hdr.sh_entsize = GOT_ENTRY_SIZE; + } + +- /* Fill PLT and GOT entries for local STT_GNU_IFUNC symbols. */ +- htab_traverse (htab->loc_hash_table, +- (void *) elfNN_loongarch_finish_local_dynamic_symbol, info); +- + return true; + } + +@@ -4663,6 +4660,8 @@ elf_loongarch64_hash_symbol (struct elf_link_hash_entry *h) + #define elf_backend_size_dynamic_sections loongarch_elf_size_dynamic_sections + #define elf_backend_relocate_section loongarch_elf_relocate_section + #define elf_backend_finish_dynamic_symbol loongarch_elf_finish_dynamic_symbol ++#define elf_backend_output_arch_local_syms \ ++ elf_loongarch_output_arch_local_syms + #define elf_backend_finish_dynamic_sections \ + loongarch_elf_finish_dynamic_sections + #define elf_backend_object_p loongarch_elf_object_p +diff --git a/ld/testsuite/ld-loongarch-elf/local-ifunc-reloc.d b/ld/testsuite/ld-loongarch-elf/local-ifunc-reloc.d +index 29f2d3f3..bf73d9f2 100644 +--- a/ld/testsuite/ld-loongarch-elf/local-ifunc-reloc.d ++++ b/ld/testsuite/ld-loongarch-elf/local-ifunc-reloc.d +@@ -6,5 +6,5 @@ + + DYNAMIC RELOCATION RECORDS + OFFSET +TYPE +VALUE +-:xdigit:+ R_LARCH_IRELATIVE +\*ABS\*\+0x:xdigit:+ + :xdigit:+ R_LARCH_64 +test ++:xdigit:+ R_LARCH_IRELATIVE +\*ABS\*\+0x:xdigit:+ +-- +2.33.0 +
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_service:tar_scm:LoongArch-opcodes-Add-support-for-tls-le-relax.patch
Added
@@ -0,0 +1,29 @@ +From 689b6f002360f50386eb3bd83a20aff8cf61afb1 Mon Sep 17 00:00:00 2001 +From: changjiachen <changjiachen@stu.xupt.edu.cn> +Date: Thu, 28 Dec 2023 19:58:28 +0800 +Subject: PATCH 033/123 LoongArch: opcodes: Add support for tls le relax. + +Add new opcode for tls le relax. + + opcode/ChangeLog: + + * loongarch-opc.c: Add new loongarch opcode. +--- + opcodes/loongarch-opc.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c +index a632373f..44b5f612 100644 +--- a/opcodes/loongarch-opc.c ++++ b/opcodes/loongarch-opc.c +@@ -464,6 +464,7 @@ static struct loongarch_opcode loongarch_fix_opcodes = + { 0x000c0000, 0xfffc0000, "bytepick.d", "r0:5,r5:5,r10:5,u15:3", 0, 0, 0, 0 }, + { 0x00100000, 0xffff8000, "add.w", "r0:5,r5:5,r10:5", 0, 0, 0, 0 }, + { 0x00108000, 0xffff8000, "add.d", "r0:5,r5:5,r10:5", 0, 0, 0, 0 }, ++ { 0x00108000, 0xffff8000, "add.d", "r0:5,r5:5,r10:5,t", 0, 0, 0, 0 }, + { 0x00110000, 0xffff8000, "sub.w", "r0:5,r5:5,r10:5", 0, 0, 0, 0 }, + { 0x00118000, 0xffff8000, "sub.d", "r0:5,r5:5,r10:5", 0, 0, 0, 0 }, + { 0x00120000, 0xffff8000, "slt", "r0:5,r5:5,r10:5", 0, 0, 0, 0 }, +-- +2.33.0 +
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_service:tar_scm:LoongArch-readelf-d-RELASZ-excludes-.rela.plt-size.patch
Added
@@ -0,0 +1,25 @@ +From 601f6c1fb4e3b4a0174d99ec5dd6d4d19f89013e Mon Sep 17 00:00:00 2001 +From: mengqinggang <mengqinggang@loongson.cn> +Date: Mon, 31 Jul 2023 17:09:48 +0800 +Subject: PATCH 014/123 LoongArch: readelf -d RELASZ excludes .rela.plt size + +Before, readelf -d RELASZ is the sum of .rela.dyn size and .rela.plt size. +To consistent with LoongArch lld, RELASZ chang to only the size of .rela.dyn. +--- + bfd/elfnn-loongarch.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index 2fe4924b..7dbe31eb 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -4672,4 +4672,6 @@ elf_loongarch64_hash_symbol (struct elf_link_hash_entry *h) + #define elf_backend_hash_symbol elf_loongarch64_hash_symbol + #define bfd_elfNN_bfd_relax_section loongarch_elf_relax_section + ++#define elf_backend_dtrel_excludes_plt 1 ++ + #include "elfNN-target.h" +-- +2.33.0 +
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_service:tar_scm:MIPS-GAS-Add-march-loongson2f-to-loongson-2f-3-test.patch
Added
@@ -0,0 +1,25 @@ +From a06390be2ae099645373a826da3fd0f9d6c3e48a Mon Sep 17 00:00:00 2001 +From: YunQiang Su <yunqiang.su@cipunited.com> +Date: Fri, 24 Nov 2023 14:35:12 +0800 +Subject: PATCH 018/123 MIPS/GAS: Add -march=loongson2f to loongson-2f-3 test + +On MIPSr6, the encoding of JR instruction has been chaned. +This patch can fix these failures for r6 default triples: + ST Microelectronics Loongson-2F workarounds of Jump Instruction issue +--- + gas/testsuite/gas/mips/loongson-2f-3.d | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/gas/testsuite/gas/mips/loongson-2f-3.d b/gas/testsuite/gas/mips/loongson-2f-3.d +index f3ac2c97..c31d3abf 100644 +--- a/gas/testsuite/gas/mips/loongson-2f-3.d ++++ b/gas/testsuite/gas/mips/loongson-2f-3.d +@@ -1,4 +1,4 @@ +-#as: -mfix-loongson2f-jump ++#as: -march=loongson2f -mfix-loongson2f-jump + #objdump: -M reg-names=numeric -dr + #name: ST Microelectronics Loongson-2F workarounds of Jump Instruction issue + +-- +2.33.0 +
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_service:tar_scm:Make-sure-DW_CFA_advance_loc4-is-in-the-same-frag.patch
Added
@@ -0,0 +1,37 @@ +From 4c35fff684c03e27b0b4a421681be4e90cd293a2 Mon Sep 17 00:00:00 2001 +From: Jinyang He <hejinyang@loongson.cn> +Date: Thu, 10 Aug 2023 10:21:40 +0800 +Subject: PATCH 008/123 Make sure DW_CFA_advance_loc4 is in the same frag + +Do the same as commit b9d8f5601bcf in another place generating +DW_CFA_advance_loc4. The idea behind commit b9d8f5601bcf was that +when a DW_CFA_advance_loc4 of zero is seen in eh_frame_relax_frag and +eh_frame_convert_frag we want to remove the opcode entirely, not just +convert to a nop. If the opcode was split over two frags then a size +adjustment would need to be done to the first frag, not just the +second as is correct for other cases with split frags. This would +complicate the eh relaxation. It's easier to ensure the frag is not +split. + + * ehopt.c (check_eh_frame): Don't allow DW_CFA_advance_loc4 + to be placed in a different frag to the rs_cfa. +--- + gas/ehopt.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/gas/ehopt.c b/gas/ehopt.c +index feea61b9..9d6606ad 100644 +--- a/gas/ehopt.c ++++ b/gas/ehopt.c +@@ -386,7 +386,7 @@ check_eh_frame (expressionS *exp, unsigned int *pnbytes) + { + /* This might be a DW_CFA_advance_loc4. Record the frag and the + position within the frag, so that we can change it later. */ +- frag_grow (1); ++ frag_grow (1 + 4); + d->state = state_saw_loc4; + d->loc4_frag = frag_now; + d->loc4_fix = frag_now_fix (); +-- +2.33.0 +
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_service:tar_scm:Modify-test-because-of-readelf-not-update.patch
Added
@@ -0,0 +1,201 @@ +From e0968610301d68ee7bf35f2bcba0817d08e07921 Mon Sep 17 00:00:00 2001 +From: Xin Wang <wangxin03@loongson.cn> +Date: Fri, 25 Oct 2024 15:07:38 +0800 +Subject: PATCH 121/123 Modify test because of readelf not update + +--- + ld/testsuite/ld-loongarch-elf/relr-align.d | 24 +++++++++---------- + ld/testsuite/ld-loongarch-elf/relr-data-pie.d | 12 +++++----- + .../ld-loongarch-elf/relr-data-shared.d | 10 ++++---- + .../ld-loongarch-elf/relr-discard-pie.d | 8 +++---- + .../ld-loongarch-elf/relr-discard-shared.d | 6 ++--- + ld/testsuite/ld-loongarch-elf/relr-got-pie.d | 12 +++++----- + .../ld-loongarch-elf/relr-got-shared.d | 10 ++++---- + .../ld-loongarch-elf/relr-got-start.d | 6 ++--- + ld/testsuite/ld-loongarch-elf/relr-text-pie.d | 6 ++--- + .../ld-loongarch-elf/relr-text-shared.d | 6 ++--- + 10 files changed, 50 insertions(+), 50 deletions(-) + +diff --git a/ld/testsuite/ld-loongarch-elf/relr-align.d b/ld/testsuite/ld-loongarch-elf/relr-align.d +index d534243b..e95b0fb8 100644 +--- a/ld/testsuite/ld-loongarch-elf/relr-align.d ++++ b/ld/testsuite/ld-loongarch-elf/relr-align.d +@@ -8,15 +8,15 @@ Relocation section '\.rela.dyn' at offset 0x0-9a-f+ contains 3 entries: + 0000000012340019 0000000000000003 R_LARCH_RELATIVE 10000 + 0000000012340041 0000000000000003 R_LARCH_RELATIVE 10000 + +-Relocation section '\.relr.dyn' at offset 0x0-9a-f+ contains 9 entries which relocate 10 locations: +-Index: Entry Address Symbolic Address +-0000: 0000000012340000 0000000012340000 double_0 +-0001: 0000000000000003 0000000012340008 double_0 \+ 0x8 +-0002: 0000000012340022 0000000012340022 double_2 +-0003: 0000000000000003 000000001234002a double_2 \+ 0x8 +-0004: 0000000012340038 0000000012340038 single_0 +-0005: 000000001234004a 000000001234004a single_2 +-0006: 0000000012340058 0000000012340058 big +-0007: 8000000100000001 0000000012340158 big \+ 0x100 +- 0000000012340250 big \+ 0x1f8 +-0008: 0000000000000003 0000000012340258 big \+ 0x200 ++Relocation section '\.relr.dyn' at offset 0x0-9a-f+ contains 9 entries: ++ 10 offsets ++0000000012340000 ++0000000012340008 ++0000000012340022 ++000000001234002a ++0000000012340038 ++000000001234004a ++0000000012340058 ++0000000012340158 ++0000000012340250 ++0000000012340258 +diff --git a/ld/testsuite/ld-loongarch-elf/relr-data-pie.d b/ld/testsuite/ld-loongarch-elf/relr-data-pie.d +index 20ef9ac1..fe32ae34 100644 +--- a/ld/testsuite/ld-loongarch-elf/relr-data-pie.d ++++ b/ld/testsuite/ld-loongarch-elf/relr-data-pie.d +@@ -10,9 +10,9 @@ Relocation section '\.rela\.dyn' at offset 0x0-9a-f+ contains 5 entries: + 0000000012340018 0000000000000003 R_LARCH_RELATIVE 12340050 + 0000000012340040 0000000c00000002 R_LARCH_64 0000000000000000 sym_weak_undef \+ 0 + +-Relocation section '\.relr\.dyn' at offset 0x0-9a-f+ contains 2 entries which relocate 4 locations: +-Index: Entry Address Symbolic Address +-0000: 0000000012340020 0000000012340020 aligned_local +-0001: 0000000000000027 0000000012340028 aligned_hidden +- 0000000012340030 aligned_global +- 0000000012340048 aligned_DYNAMIC ++Relocation section '\.relr\.dyn' at offset 0x0-9a-f+ contains 2 entries: ++ 4 offsets ++0000000012340020 ++0000000012340028 ++0000000012340030 ++0000000012340048 +diff --git a/ld/testsuite/ld-loongarch-elf/relr-data-shared.d b/ld/testsuite/ld-loongarch-elf/relr-data-shared.d +index 37e4c0da..0521786f 100644 +--- a/ld/testsuite/ld-loongarch-elf/relr-data-shared.d ++++ b/ld/testsuite/ld-loongarch-elf/relr-data-shared.d +@@ -11,8 +11,8 @@ Relocation section '\.rela\.dyn' at offset 0x0-9a-f+ contains 6 entries: + 0000000012340030 0000000d00000002 R_LARCH_64 000000000001000c sym_global \+ 0 + 0000000012340040 0000000c00000002 R_LARCH_64 0000000000000000 sym_weak_undef \+ 0 + +-Relocation section '\.relr\.dyn' at offset 0x0-9a-f+ contains 2 entries which relocate 3 locations: +-Index: Entry Address Symbolic Address +-0000: 0000000012340020 0000000012340020 aligned_local +-0001: 0000000000000023 0000000012340028 aligned_hidden +- 0000000012340048 aligned_DYNAMIC ++Relocation section '\.relr\.dyn' at offset 0x0-9a-f+ contains 2 entries: ++ 3 offsets ++0000000012340020 ++0000000012340028 ++0000000012340048 +diff --git a/ld/testsuite/ld-loongarch-elf/relr-discard-pie.d b/ld/testsuite/ld-loongarch-elf/relr-discard-pie.d +index 4ea8ae5e..11d2dba8 100644 +--- a/ld/testsuite/ld-loongarch-elf/relr-discard-pie.d ++++ b/ld/testsuite/ld-loongarch-elf/relr-discard-pie.d +@@ -2,7 +2,7 @@ + #ld: -pie -z pack-relative-relocs -T relr-discard.ld + #readelf: -rW + +-Relocation section '\.relr\.dyn' at offset 0x0-9a-f+ contains 2 entries which relocate 2 locations: +-Index: Entry Address Symbolic Address +-0000: 0000000000020008 0000000000020008 _GLOBAL_OFFSET_TABLE_ \+ 0x8 +-0001: 0000000000000003 0000000000020010 _GLOBAL_OFFSET_TABLE_ \+ 0x10 ++Relocation section '\.relr\.dyn' at offset 0x0-9a-f+ contains 2 entries: ++ 2 offsets ++0000000000020008 ++0000000000020010 +diff --git a/ld/testsuite/ld-loongarch-elf/relr-discard-shared.d b/ld/testsuite/ld-loongarch-elf/relr-discard-shared.d +index 8bfd8ba5..2a540832 100644 +--- a/ld/testsuite/ld-loongarch-elf/relr-discard-shared.d ++++ b/ld/testsuite/ld-loongarch-elf/relr-discard-shared.d +@@ -6,6 +6,6 @@ Relocation section '\.rela\.dyn' at offset 0x0-9a-f+ contains 1 entry: + Offset Info Type Symbol's Value Symbol's Name \+ Addend + 0000000000020010 0000000300000002 R_LARCH_64 000000000001000c sym_global \+ 0 + +-Relocation section '\.relr\.dyn' at offset 0x0-9a-f+ contains 1 entry which relocates 1 location: +-Index: Entry Address Symbolic Address +-0000: 0000000000020008 0000000000020008 _GLOBAL_OFFSET_TABLE_ \+ 0x8 ++Relocation section '\.relr\.dyn' at offset 0x0-9a-f+ contains 1 entry: ++ 1 offset ++0000000000020008 +diff --git a/ld/testsuite/ld-loongarch-elf/relr-got-pie.d b/ld/testsuite/ld-loongarch-elf/relr-got-pie.d +index e994f2bf..849bf9b4 100644 +--- a/ld/testsuite/ld-loongarch-elf/relr-got-pie.d ++++ b/ld/testsuite/ld-loongarch-elf/relr-got-pie.d +@@ -7,9 +7,9 @@ Relocation section '.rela.dyn' at offset 0x0-9a-f+ contains 2 entries: + 0000000000000000 0000000000000000 R_LARCH_NONE 0 + 0000000000020030 0000000200000002 R_LARCH_64 0000000000000000 sym_weak_undef \+ 0 + +-Relocation section '.relr.dyn' at offset 0x0-9a-f+ contains 2 entries which relocate 4 locations: +-Index: Entry Address Symbolic Address +-0000: 0000000000020008 0000000000020008 _GLOBAL_OFFSET_TABLE_ \+ 0x8 +-0001: 000000000000000f 0000000000020010 _GLOBAL_OFFSET_TABLE_ \+ 0x10 +- 0000000000020018 _GLOBAL_OFFSET_TABLE_ \+ 0x18 +- 0000000000020020 _GLOBAL_OFFSET_TABLE_ \+ 0x20 ++Relocation section '.relr.dyn' at offset 0x0-9a-f+ contains 2 entries: ++ 4 offsets ++0000000000020008 ++0000000000020010 ++0000000000020018 ++0000000000020020 +diff --git a/ld/testsuite/ld-loongarch-elf/relr-got-shared.d b/ld/testsuite/ld-loongarch-elf/relr-got-shared.d +index 169e0e5d..030261af 100644 +--- a/ld/testsuite/ld-loongarch-elf/relr-got-shared.d ++++ b/ld/testsuite/ld-loongarch-elf/relr-got-shared.d +@@ -8,8 +8,8 @@ Relocation section '\.rela\.dyn' at offset 0x0-9a-f+ contains 3 entries: + 0000000000020028 0000000500000002 R_LARCH_64 000000000000002a sym_global_abs \+ 0 + 0000000000020030 0000000200000002 R_LARCH_64 0000000000000000 sym_weak_undef \+ 0 + +-Relocation section '\.relr\.dyn' at offset 0x0-9a-f+ contains 2 entries which relocate 3 locations: +-Index: Entry Address Symbolic Address +-0000: 0000000000020008 0000000000020008 _GLOBAL_OFFSET_TABLE_ \+ 0x8 +-0001: 0000000000000007 0000000000020010 _GLOBAL_OFFSET_TABLE_ \+ 0x10 +- 0000000000020018 _GLOBAL_OFFSET_TABLE_ \+ 0x18 ++Relocation section '\.relr\.dyn' at offset 0x0-9a-f+ contains 2 entries: ++ 3 offsets ++0000000000020008 ++0000000000020010 ++0000000000020018 +diff --git a/ld/testsuite/ld-loongarch-elf/relr-got-start.d b/ld/testsuite/ld-loongarch-elf/relr-got-start.d +index 0b1a5b98..b4723d6c 100644 +--- a/ld/testsuite/ld-loongarch-elf/relr-got-start.d ++++ b/ld/testsuite/ld-loongarch-elf/relr-got-start.d +@@ -2,6 +2,6 @@ + #ld: -pie -z pack-relative-relocs -T relr-relocs.ld + #readelf: -rW + +-Relocation section '\.relr\.dyn' at offset 0xa-z0-f+ contains 1 entry which relocates 1 location: +-Index: Entry Address Symbolic Address +-0000: 0000000000020008 0000000000020008 _GLOBAL_OFFSET_TABLE_ \+ 0x8 ++Relocation section '\.relr\.dyn' at offset 0xa-z0-f+ contains 1 entry: ++ 1 offset ++0000000000020008 +diff --git a/ld/testsuite/ld-loongarch-elf/relr-text-pie.d b/ld/testsuite/ld-loongarch-elf/relr-text-pie.d +index 5121313e..c39975ba 100644 +--- a/ld/testsuite/ld-loongarch-elf/relr-text-pie.d ++++ b/ld/testsuite/ld-loongarch-elf/relr-text-pie.d +@@ -9,6 +9,6 @@ + 0x0000000000000023 \(RELRSZ\) 8 \(bytes\) + 0x0000000000000025 \(RELRENT\) 8 \(bytes\) + #... +-Relocation section '\.relr\.dyn' .* contains 1 entry which relocates 1 location: +-Index: Entry Address Symbolic Address +-0000: 0000000000010000 0000000000010000 _start ++Relocation section '\.relr\.dyn' .* contains 1 entry: ++ 1 offset ++0000000000010000 +diff --git a/ld/testsuite/ld-loongarch-elf/relr-text-shared.d b/ld/testsuite/ld-loongarch-elf/relr-text-shared.d +index 8e34500f..5d86d398 100644 +--- a/ld/testsuite/ld-loongarch-elf/relr-text-shared.d ++++ b/ld/testsuite/ld-loongarch-elf/relr-text-shared.d +@@ -9,6 +9,6 @@ + 0x0000000000000023 \(RELRSZ\) 8 \(bytes\) + 0x0000000000000025 \(RELRENT\) 8 \(bytes\) + #... +-Relocation section '\.relr\.dyn' .* contains 1 entry which relocates 1 location: +-Index: Entry Address Symbolic Address +-0000: 0000000000010000 0000000000010000 _start ++Relocation section '\.relr\.dyn' .* contains 1 entry: ++ 1 offset ++0000000000010000 +--
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_service:tar_scm:Not-append-rela-for-absolute-symbol.patch
Added
@@ -0,0 +1,133 @@ +From 41abd06f7ba97c5b92a2d38c99c357772bba3ade Mon Sep 17 00:00:00 2001 +From: Xin Wang <yw987194828@gmail.com> +Date: Fri, 16 Aug 2024 11:28:10 +0800 +Subject: PATCH 113/123 Not append rela for absolute symbol + +LoongArch: Not append rela for absolute symbol + +Use la.global to get absolute symbol like la.abs. +la.global put address of a global symbol into a got +entry and append a rela for it, which will be used +to relocate by dynamic linker. Dynamic linker should +not relocate for got entry of absolute symbol as it +stores symval not symbol's address. +--- + bfd/elfnn-loongarch.c | 19 ++++++++++++++++++- + ld/testsuite/ld-loongarch-elf/abs-global.out | 1 + + ld/testsuite/ld-loongarch-elf/abs-global.s | 5 +++++ + .../ld-loongarch-elf/get_abs_global_sym.c | 7 +++++++ + .../ld-loongarch-elf/ld-loongarch-elf.exp | 12 ++++++++++++ + 5 files changed, 43 insertions(+), 1 deletion(-) + create mode 100644 ld/testsuite/ld-loongarch-elf/abs-global.out + create mode 100644 ld/testsuite/ld-loongarch-elf/abs-global.s + create mode 100644 ld/testsuite/ld-loongarch-elf/get_abs_global_sym.c + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index 770483cd..09a9513b 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -4135,6 +4135,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, + if (!WILL_CALL_FINISH_DYNAMIC_SYMBOL (is_dyn, + bfd_link_pic (info), + h) ++ && !bfd_is_abs_section(h->root.u.def.section) + && bfd_link_pic (info) + && LARCH_REF_LOCAL (info, h) + && !info->enable_dt_relr) +@@ -4157,7 +4158,8 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, + && local_got_offsetsr_symndx != MINUS_ONE); + + got_off = local_got_offsetsr_symndx & (~(bfd_vma)1); +- if ((local_got_offsetsr_symndx & 1) == 0) ++ if (sym->st_shndx != SHN_ABS ++ && (local_got_offsetsr_symndx & 1) == 0) + { + if (bfd_link_pic (info) && !info->enable_dt_relr) + { +@@ -5314,6 +5316,7 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, + bfd_vma symval; + asection *sym_sec; + bool local_got = false; ++ bool is_abs_symbol = false; + Elf_Internal_Rela *rel = relocs + i; + struct elf_link_hash_entry *h = NULL; + unsigned long r_type = ELFNN_R_TYPE (rel->r_info); +@@ -5495,7 +5498,21 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, + break; + + case R_LARCH_GOT_PC_HI20: ++ if (h) ++ is_abs_symbol = bfd_is_abs_section(h->root.u.def.section); ++ else ++ { ++ Elf_Internal_Sym *sym = (Elf_Internal_Sym *)symtab_hdr->contents ++ + ELFNN_R_SYM (rel->r_info); ++ is_abs_symbol = sym->st_shndx == SHN_ABS; ++ } ++ /* If symval is in the range -2^31, 2^31), we can relax the ++ pair of instructions from pcalau12i/ld.d to lu12i.w/ori for ++ abosulte symbol. This is not implemented yet, so we just ++ remain the r_type which will be needed when relocate for ++ absolute symbol. */ + if (local_got && 0 == info->relax_pass ++ && !is_abs_symbol + && (i + 4) <= sec->reloc_count) + { + if (loongarch_relax_pcala_ld (abfd, sec, rel)) +diff --git a/ld/testsuite/ld-loongarch-elf/abs-global.out b/ld/testsuite/ld-loongarch-elf/abs-global.out +new file mode 100644 +index 00000000..3656652b +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/abs-global.out +@@ -0,0 +1 @@ ++abba +diff --git a/ld/testsuite/ld-loongarch-elf/abs-global.s b/ld/testsuite/ld-loongarch-elf/abs-global.s +new file mode 100644 +index 00000000..93a5da6d +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/abs-global.s +@@ -0,0 +1,5 @@ ++.text ++.globl get_sym ++get_sym: ++ la.global $a0, sym ++ ret +diff --git a/ld/testsuite/ld-loongarch-elf/get_abs_global_sym.c b/ld/testsuite/ld-loongarch-elf/get_abs_global_sym.c +new file mode 100644 +index 00000000..29781ad7 +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/get_abs_global_sym.c +@@ -0,0 +1,7 @@ ++#include <stdio.h> ++ ++extern int get_sym(); ++int main() { ++ printf("%x\n", get_sym()); ++ return 0; ++} +diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp +index cb6d2296..555ebf92 100644 +--- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp ++++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp +@@ -130,6 +130,18 @@ if istarget "loongarch64-*-*" { + "a.binary" \ + \ + ++ ++ ++ run_ld_link_exec_tests list \ ++ list \ ++ "get global abs symbol test" \ ++ "-Wl,-z norelro -Wl,--defsym sym=0xabba" \ ++ "" \ ++ { abs-global.s get_abs_global_sym.c} \ ++ "abs-global" \ ++ "abs-global.out" \ ++ \ ++ + } + + if istarget "loongarch64-*-*" { +-- +2.33.0 +
View file
_service:tar_scm:PATCH-v2-gas-NEWS-ld-NEWS-Announce-LoongArch-changes.patch
Added
@@ -0,0 +1,167 @@ +From ae6dd4b75b96f999e1480287810aef41bbdc4969 Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao <xry111@xry111.site> +Date: Tue, 23 Jan 2024 16:00:32 +0000 +Subject: PATCH 049/123 PATCH v2 gas/NEWS, ld/NEWS: Announce LoongArch + changes in 2.42 + +--- + gas/NEWS | 93 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + ld/NEWS | 40 ++++++++++++++++++++++++ + 2 files changed, 133 insertions(+) + +diff --git a/gas/NEWS b/gas/NEWS +index 59bdd30a..9ad24543 100644 +--- a/gas/NEWS ++++ b/gas/NEWS +@@ -1,5 +1,98 @@ + -*- text -*- + ++Changes in 2.42: ++ ++* Experimental support in GAS to synthesize CFI for ABI-conformant, ++ hand-written asm using the new command line option --scfi=experimental on ++ x86-64. Only System V AMD64 ABI is supported. ++ ++* Add support for the Arm Scalable Vector Extension version 2.1 (SVE2.1) ++ instructions. ++ ++* Add support for the AArch64 Scalable Matrix Extension version 2.1 (SME2.1) ++ instructions. ++ ++* Add support for 'armv8.9-a' and 'armv9.4-a' for -march in Arm GAS. ++ ++* Initial support for Intel APX: 32 GPRs, NDD, PUSH2/POP2 and PUSHP/POPP. ++ ++* On RISC-V macro instructions expanding to AUIPC and a load, store, or branch ++ no longer accept x0 as an intermediate and/or destination register. ++ ++* Add support for Reliability, Availability and Serviceability extension v2 ++ (RASv2) for AArch64. ++ ++* Add support for 128-bit Atomic Instructions (LSE128) for AArch64. ++ ++* Add support for Guarded Control Stack (GCS) for AArch64. ++ ++* Add support for AArch64 Check Feature Status Extension (CHK). ++ ++* Add support for 'armv8.9-a' and 'armv9.4-a' for -march in AArch64 GAS. ++ ++* Add support for Intel USER_MSR instructions. ++ ++* Add support for Intel AVX10.1. ++ ++* Add support for Intel PBNDKB instructions. ++ ++* Add support for Intel SM4 instructions. ++ ++* Add support for Intel SM3 instructions. ++ ++* Add support for Intel SHA512 instructions. ++ ++* Add support for Intel AVX-VNNI-INT16 instructions. ++ ++* Add support for Cortex-A520 for AArch64. ++ ++* Add support for Cortex-A720 for AArch64. ++ ++* Add support for Cortex-X3 for AArch64. ++ ++* Add support for Cortex-X4 for AArch64. ++ ++* Add support for RISC-V T-Head extensions (XTheadVector, XTheadZvlsseg ++ and XTheadZvamo) from version 2.3.0 of the T-Head ISA manual. ++ ++* Add support for RISC-V CORE-V extensions (XCVmac, XCValu) with version 1.0. ++ ++* Add support for RISC-V SiFive VCIX extension (XSfVcp) with version 1.0. ++ ++* The BPF assembler now uses semi-colon (;) to separate statements, and ++ therefore they cannot longer be used to begin line comments. This matches the ++ behavior of the clang/LLVM BPF assembler. ++ ++* The BPF assembler now allows using both hash (#) and double slash (//) to ++ begin line comments. ++ ++* Add support for LoongArch v1.10 new instructions: estimated reciprocal ++ instructions, sub-word atomic instructions, atomic CAS instructions, ++ 16-byte store-conditional instruction, load-linked instructions with ++ acquire semantics, and store-conditional instructions with release ++ semantics. ++ ++* The %call36 relocation operator, along with the pseudo-instructions ++ call36 and tail36, are now usable with the LoongArch "medium" code ++ model, allowing text sections up to 128 GiB. ++ ++* TLS descriptors (TLSDESC) are now supported on LoongArch. This includes ++ the following new relocation operators: %desc_pc_hi20, %desc_pc_lo12, ++ %desc_ld, and %desc_call, and the la.tls.desc pseudo-instruction. ++ ++* TLS LE relaxation is now supported on LoongArch. New relocation ++ operators %le_hi20_r, %le_lo12r, and %le_add_r are now available. ++ ++* Add support for LoongArch branch relaxation: a conditional branch with ++ destination out of its immediate operand range, but still within ++ a "b"'s range, is now assembled as an inverted branch and a "b". This ++ works around the unreliable branch offset estimation of the compiler ++ when .align directive is encoded into a long NOP sequence with an ++ R_LARCH_RELAX by the assembler. ++ ++* Symbol or label names in LoongArch assembly can now be spelled with ++ double-quotes. ++ + Changes in 2.41: + + * Add support for Intel FRED instructions. +diff --git a/ld/NEWS b/ld/NEWS +index e1ac20b8..687b5190 100644 +--- a/ld/NEWS ++++ b/ld/NEWS +@@ -1,5 +1,45 @@ + -*- text -*- + ++Changes in 2.42: ++ ++* Add -z mark-plt/-z nomark-plt options to x86-64 ELF linker to mark PLT ++ entries with DT_X86_64_PLT, DT_X86_64_PLTSZ and DT_X86_64_PLTENT dynamic ++ tags. Also added --enable-mark-plt configure option to mark PLT entries ++ by default. ++ ++* Support Intel APX relocations. ++ ++* On RISC-V, add ld target option --no-check-uleb128. Should rebuild the ++ objects by binutils 2.42 and up if enabling the option and get warnings, ++ since the non-zero addend of SUB_ULEB128 shouldn't be generated from .uleb128 ++ directives. ++ ++* Add support for the KVX instruction set. ++ ++* A new linker script sorting directive has been added: REVERSE. This reverses ++ the order of the sorting. It may be combined with either SORT_BY_NAME or ++ SORT_BY_INIT_PRIORITY. ++ ++* Added --warn-execstack-objects to warn about executable stacks only when an ++ input object file requests one. Also added --error-execstack and ++ --error-rxw-segments options to convert warnings about executable stacks and ++ segments into errors. ++ ++ Also added --enable-error-execstack=yes|no and ++ --enable-error-rwx-segments=yes|no configure options to set the default for ++ converting warnings into errors. ++ ++* On LoongArch, various linker relaxation bugs are fixed; the most notable ++ of which is BZ 30944 (incorrect .balign semantics). ++ ++* On LoongArch, the LoongArch ABI v2.30 (LoongArch ELF psABI v20231219) is ++ now implemented. This includes new relocation types, and changed ++ semantics for PC-relative relocations handling the higher half of 64-bit ++ offsets. ++ ++* On LoongArch, link-time TLS optimization and TLS relaxation are now ++ supported. ++ + Changes in 2.41: + + * The linker now accepts a command line option of --remap-inputs +-- +2.33.0 +
View file
_service:tar_scm:Re-LoongArch-Add-support-for-b-.L1-and-beq-t0-t1-.L1.patch
Added
@@ -0,0 +1,62 @@ +From 311282d26b81bbe082f798e7b6100e8ef6f6d6ed Mon Sep 17 00:00:00 2001 +From: Alan Modra <amodra@gmail.com> +Date: Sun, 24 Dec 2023 14:41:06 +1030 +Subject: PATCH 024/123 Re: LoongArch: Add support for <b ".L1"> and <beq, + $t0, $t1, ".L1"> + +This fixes the buffer overflow added in commit 22b78fad28, and a few +other problems. + + * loongarch-coder.c (loongarch_split_args_by_comma): Don't + overflow buffer when args == "". Don't remove unbalanced + quotes. Don't trim last arg if max number of args exceeded. +--- + opcodes/loongarch-coder.c | 30 ++++++++++++++++-------------- + 1 file changed, 16 insertions(+), 14 deletions(-) + +diff --git a/opcodes/loongarch-coder.c b/opcodes/loongarch-coder.c +index 672a468b..b6835276 100644 +--- a/opcodes/loongarch-coder.c ++++ b/opcodes/loongarch-coder.c +@@ -255,22 +255,24 @@ loongarch_split_args_by_comma (char *args, const char *arg_strs) + size_t num = 0; + + if (*args) +- arg_strsnum++ = args; +- for (; *args; args++) +- if (*args == ',') +- { +- if (MAX_ARG_NUM_PLUS_2 - 1 == num) +- break; +- else +- *args = '\0', arg_strsnum++ = args + 1; +- } +- +- if (*(args-1) == '"') + { +- *(args-1) = '\0'; +- arg_strsnum-1 = arg_strsnum-1 + 1; +- } ++ arg_strsnum++ = args; ++ for (; *args; args++) ++ if (*args == ',') ++ { ++ if (MAX_ARG_NUM_PLUS_2 - 1 == num) ++ goto out; ++ *args = '\0'; ++ arg_strsnum++ = args + 1; ++ } + ++ if (*(args - 1) == '"' && *arg_strsnum - 1 == '"') ++ { ++ *(args - 1) = '\0'; ++ arg_strsnum - 1 += 1; ++ } ++ } ++ out: + arg_strsnum = NULL; + return num; + } +-- +2.33.0 +
View file
_service:tar_scm:Re-LoongArch-gas-Adjust-DWARF-CIE-alignment-factors.patch
Added
@@ -0,0 +1,94 @@ +From 2279b12faf8e02e4c3123435008a79ad615781e5 Mon Sep 17 00:00:00 2001 +From: Alan Modra <amodra@gmail.com> +Date: Thu, 23 May 2024 14:51:31 +0930 +Subject: PATCH 087/123 Re: LoongArch: gas: Adjust DWARF CIE alignment + factors + +Adjust the gas testsuite to suit commit de203ed568f6. + + * testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.d: + Expect data alignment of -8. Tidy. +--- + .../relax-cfi-fde-DW_CFA_advance_loc.d | 44 +++++++++---------- + 1 file changed, 22 insertions(+), 22 deletions(-) + +diff --git a/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.d b/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.d +index d685bd86..6da53b43 100644 +--- a/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.d ++++ b/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.d +@@ -5,50 +5,50 @@ + .*: +file format .* + + +-Disassembly of section .eh_frame: ++Disassembly of section \.eh_frame: + +- *0000000000000000 <.eh_frame>: +- +0: +00000014 +.word + +0x00000014 +- +4: +00000000 +.word + +0x00000000 +- +8: +00527a01 +.word + +0x00527a01 +- +c: +01017c01 +fadd.d +\$fa1, \$fa0, \$fs7 +- +10: +0c030d1b +.word + +0x0c030d1b +- +14: +00000016 +.word + +0x00000016 +- +18: +0000003c +.word + +0x0000003c +- +1c: +0000001c +.word + +0x0000001c ++ *0000000000000000 <\.eh_frame>: ++ +0: +00000014 .* ++ +4: +00000000 .* ++ +8: +00527a01 .* ++ +c: +01017801 .* ++ +10: +0c030d1b .* ++ +14: +00000016 .* ++ +18: +0000003c .* ++ +1c: +0000001c .* + +... + +20: R_LARCH_32_PCREL +L0\^A + +24: R_LARCH_ADD32 +L0\^A + +24: R_LARCH_SUB32 +L0\^A +- +28: +0cd64000 +.word + +0x0cd64000 ++ +28: +0cd64000 .* + +29: R_LARCH_ADD6 +L0\^A + +29: R_LARCH_SUB6 +L0\^A +- +2c: +d6400016 +.word + +0xd6400016 ++ +2c: +d6400016 .* + +2e: R_LARCH_ADD6 +L0\^A + +2e: R_LARCH_SUB6 +L0\^A +- +30: +4000160c +beqz +\$t4, 3145748 +# 300044 <L0\^A\+0x2ffff4> ++ +30: +4000160c .* + +33: R_LARCH_ADD6 +L0\^A + +33: R_LARCH_SUB6 +L0\^A +- +34: +00160cd6 +orn +\$fp, \$a2, \$sp +- +38: +160cd640 +lu32i.d +\$zero, 26290 ++ +34: +00160cd6 .* ++ +38: +160cd640 .* + +38: R_LARCH_ADD6 +L0\^A + +38: R_LARCH_SUB6 +L0\^A +- +3c: +0cd64000 +.word + +0x0cd64000 ++ +3c: +0cd64000 .* + +3d: R_LARCH_ADD6 +L0\^A + +3d: R_LARCH_SUB6 +L0\^A +- +40: +d6400016 +.word + +0xd6400016 ++ +40: +d6400016 .* + +42: R_LARCH_ADD6 +L0\^A + +42: R_LARCH_SUB6 +L0\^A +- +44: +4000160c +beqz +\$t4, 3145748 +# 300058 <L0\^A\+0x300008> ++ +44: +4000160c .* + +47: R_LARCH_ADD6 +L0\^A + +47: R_LARCH_SUB6 +L0\^A +- +48: +00160cd6 +orn +\$fp, \$a2, \$sp +- +4c: +160cd640 +lu32i.d +\$zero, 26290 ++ +48: +00160cd6 .* ++ +4c: +160cd640 .* + +4c: R_LARCH_ADD6 +L0\^A + +4c: R_LARCH_SUB6 +L0\^A +- +50: +0cd64000 +.word + +0x0cd64000 ++ +50: +0cd64000 .* + +51: R_LARCH_ADD6 +L0\^A + +51: R_LARCH_SUB6 +L0\^A +- +54: +d6400016 +.word + +0xd6400016 ++ +54: +d6400016 .* + +56: R_LARCH_ADD6 +L0\^A + +56: R_LARCH_SUB6 +L0\^A +-- +2.33.0 +
View file
_service:tar_scm:Use-32-64_PCREL-to-replace-a-pair-of-ADD32-64-and-SU.patch
Added
@@ -0,0 +1,85 @@ +From 7ce995e6e17a8ec5c139f0398dd4f598fae5ca92 Mon Sep 17 00:00:00 2001 +From: cailulu <cailulu@loongson.cn> +Date: Fri, 1 Sep 2023 11:09:00 +0800 +Subject: PATCH 006/123 Use 32/64_PCREL to replace a pair of ADD32/64 and + SUB32/64. + +Subtraction for labels that require static relocation +usually generates ADD32/64 and SUB32/64. + +If subsy of BFD_RELOC_32/64 and PC in same segment, +and disable relax or PC at start of subsy or enable +relax but not in SEC_CODE, we generate 32/64_PCREL +to replace a pair of ADD32/64 and SUB32/64. +--- + gas/config/tc-loongarch.c | 22 ++++++++++++---------- + gas/config/tc-loongarch.h | 12 ++++++++++-- + 2 files changed, 22 insertions(+), 12 deletions(-) + +diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c +index 29a14e74..38a51fc2 100644 +--- a/gas/config/tc-loongarch.c ++++ b/gas/config/tc-loongarch.c +@@ -1197,7 +1197,6 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) + static int64_t stack_top; + static int last_reloc_is_sop_push_pcrel_1 = 0; + int last_reloc_is_sop_push_pcrel = last_reloc_is_sop_push_pcrel_1; +- segT sub_segment; + last_reloc_is_sop_push_pcrel_1 = 0; + + char *buf = fixP->fx_frag->fr_literal + fixP->fx_where; +@@ -1275,16 +1274,19 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) + (use md_number_to_chars (buf, 0, fixP->fx_size)). */ + case BFD_RELOC_64: + case BFD_RELOC_32: +- if (fixP->fx_r_type == BFD_RELOC_32 +- && fixP->fx_addsy && fixP->fx_subsy +- && (sub_segment = S_GET_SEGMENT (fixP->fx_subsy)) +- && strcmp (sub_segment->name, ".eh_frame") == 0 +- && S_GET_VALUE (fixP->fx_subsy) +- == fixP->fx_frag->fr_address + fixP->fx_where) ++ if (fixP->fx_pcrel) + { +- fixP->fx_r_type = BFD_RELOC_LARCH_32_PCREL; +- fixP->fx_subsy = NULL; +- break; ++ switch (fixP->fx_r_type) ++ { ++ case BFD_RELOC_64: ++ fixP->fx_r_type = BFD_RELOC_LARCH_64_PCREL; ++ break; ++ case BFD_RELOC_32: ++ fixP->fx_r_type = BFD_RELOC_LARCH_32_PCREL; ++ break; ++ default: ++ break; ++ } + } + + if (fixP->fx_addsy && fixP->fx_subsy) +diff --git a/gas/config/tc-loongarch.h b/gas/config/tc-loongarch.h +index a9f2a0a1..d353f18d 100644 +--- a/gas/config/tc-loongarch.h ++++ b/gas/config/tc-loongarch.h +@@ -71,8 +71,16 @@ extern bool loongarch_frag_align_code (int); + relaxation, so do not resolve such expressions in the assembler. */ + #define md_allow_local_subtract(l,r,s) 0 + +-/* Values passed to md_apply_fix don't include symbol values. */ +-#define TC_FORCE_RELOCATION_SUB_LOCAL(FIX, SEG) 1 ++/* If subsy of BFD_RELOC32/64 and PC in same segment, and without relax ++ or PC at start of subsy or with relax but sub_symbol_segment not in ++ SEC_CODE, we generate 32/64_PCREL. */ ++#define TC_FORCE_RELOCATION_SUB_LOCAL(FIX, SEG) \ ++ (!((BFD_RELOC_32 || BFD_RELOC_64) \ ++ &&(!LARCH_opts.relax \ ++ || S_GET_VALUE (FIX->fx_subsy) \ ++ == FIX->fx_frag->fr_address + FIX->fx_where \ ++ || (LARCH_opts.relax \ ++ && ((S_GET_SEGMENT (FIX->fx_subsy)->flags & SEC_CODE) == 0))))) + + #define TC_VALIDATE_FIX_SUB(FIX, SEG) 1 + #define DIFF_EXPR_OK 1 +-- +2.33.0 +
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_service:tar_scm:as-add-option-for-generate-R_LARCH_32-64_PCREL.patch
Added
@@ -0,0 +1,132 @@ +From fdcb71293e3a3ca4f699a34e2c1f76c42e799f9e Mon Sep 17 00:00:00 2001 +From: cailulu <cailulu@loongson.cn> +Date: Thu, 28 Sep 2023 16:01:52 +0800 +Subject: PATCH 011/123 as: add option for generate R_LARCH_32/64_PCREL. + +Some older kernels cannot handle the newly generated R_LARCH_32/64_PCREL, +so the assembler generates R_LARCH_ADD32/64+R_LARCH_SUB32/64 by default, +and use the assembler option mthin-add-sub to generate R_LARCH_32/64_PCREL +as much as possible. + +The Option of mthin-add-sub does not affect the generation of R_LARCH_32_PCREL +relocation in .eh_frame. +--- + gas/config/tc-loongarch.c | 29 +++++++++++++++++++++++++++++ + gas/config/tc-loongarch.h | 13 +++++++------ + include/opcode/loongarch.h | 1 + + 3 files changed, 37 insertions(+), 6 deletions(-) + +diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c +index 38a51fc2..4c48382c 100644 +--- a/gas/config/tc-loongarch.c ++++ b/gas/config/tc-loongarch.c +@@ -120,6 +120,7 @@ enum options + OPTION_LA_GLOBAL_WITH_ABS, + OPTION_RELAX, + OPTION_NO_RELAX, ++ OPTION_THIN_ADD_SUB, + + OPTION_END_OF_ENUM, + }; +@@ -136,6 +137,7 @@ struct option md_longopts = + + { "mrelax", no_argument, NULL, OPTION_RELAX }, + { "mno-relax", no_argument, NULL, OPTION_NO_RELAX }, ++ { "mthin-add-sub", no_argument, NULL, OPTION_THIN_ADD_SUB}, + + { NULL, no_argument, NULL, 0 } + }; +@@ -214,6 +216,10 @@ md_parse_option (int c, const char *arg) + LARCH_opts.relax = 0; + break; + ++ case OPTION_THIN_ADD_SUB: ++ LARCH_opts.thin_add_sub = 1; ++ break; ++ + case OPTION_IGNORE: + break; + +@@ -1197,6 +1203,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) + static int64_t stack_top; + static int last_reloc_is_sop_push_pcrel_1 = 0; + int last_reloc_is_sop_push_pcrel = last_reloc_is_sop_push_pcrel_1; ++ segT sub_segment; + last_reloc_is_sop_push_pcrel_1 = 0; + + char *buf = fixP->fx_frag->fr_literal + fixP->fx_where; +@@ -1289,6 +1296,23 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) + } + } + ++ /* If symbol in .eh_frame the address may be adjusted, and contents of ++ .eh_frame will be adjusted, so use pc-relative relocation for FDE ++ initial location. ++ The Option of mthin-add-sub does not affect the generation of ++ R_LARCH_32_PCREL relocation in .eh_frame. */ ++ if (fixP->fx_r_type == BFD_RELOC_32 ++ && fixP->fx_addsy && fixP->fx_subsy ++ && (sub_segment = S_GET_SEGMENT (fixP->fx_subsy)) ++ && strcmp (sub_segment->name, ".eh_frame") == 0 ++ && S_GET_VALUE (fixP->fx_subsy) ++ == fixP->fx_frag->fr_address + fixP->fx_where) ++ { ++ fixP->fx_r_type = BFD_RELOC_LARCH_32_PCREL; ++ fixP->fx_subsy = NULL; ++ break; ++ } ++ + if (fixP->fx_addsy && fixP->fx_subsy) + { + fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP)); +@@ -1591,6 +1615,11 @@ md_show_usage (FILE *stream) + { + fprintf (stream, _("LARCH options:\n")); + /* FIXME */ ++ fprintf (stream, _("\ ++ -mthin-add-sub Convert a pair of R_LARCH_ADD32/64 and R_LARCH_SUB32/64 to\n\ ++ R_LARCH_32/64_PCREL as much as possible\n\ ++ The option does not affect the generation of R_LARCH_32_PCREL\n\ ++ relocations in .eh_frame\n")); + } + + static void +diff --git a/gas/config/tc-loongarch.h b/gas/config/tc-loongarch.h +index fd094356..4afa3842 100644 +--- a/gas/config/tc-loongarch.h ++++ b/gas/config/tc-loongarch.h +@@ -75,12 +75,13 @@ extern bool loongarch_frag_align_code (int); + or PC at start of subsy or with relax but sub_symbol_segment not in + SEC_CODE, we generate 32/64_PCREL. */ + #define TC_FORCE_RELOCATION_SUB_LOCAL(FIX, SEG) \ +- (!((BFD_RELOC_32 || BFD_RELOC_64) \ +- &&(!LARCH_opts.relax \ +- || S_GET_VALUE (FIX->fx_subsy) \ +- == FIX->fx_frag->fr_address + FIX->fx_where \ +- || (LARCH_opts.relax \ +- && ((S_GET_SEGMENT (FIX->fx_subsy)->flags & SEC_CODE) == 0))))) ++ (!(LARCH_opts.thin_add_sub \ ++ && (BFD_RELOC_32 || BFD_RELOC_64) \ ++ && (!LARCH_opts.relax \ ++ || S_GET_VALUE (FIX->fx_subsy) \ ++ == FIX->fx_frag->fr_address + FIX->fx_where \ ++ || (LARCH_opts.relax \ ++ && ((S_GET_SEGMENT (FIX->fx_subsy)->flags & SEC_CODE) == 0))))) + + #define TC_VALIDATE_FIX_SUB(FIX, SEG) 1 + #define DIFF_EXPR_OK 1 +diff --git a/include/opcode/loongarch.h b/include/opcode/loongarch.h +index e145db5e..2ed4082c 100644 +--- a/include/opcode/loongarch.h ++++ b/include/opcode/loongarch.h +@@ -236,6 +236,7 @@ dec2 : 1-90-9? + #define ase_gabs isa.use_la_global_with_abs + + int relax; ++ int thin_add_sub; + } LARCH_opts; + + extern size_t loongarch_insn_length (insn_t insn); +-- +2.33.0 +
View file
_service:tar_scm:as-fixed-internal-error-when-immediate-value-of-relo.patch
Added
@@ -0,0 +1,140 @@ +From 690ba386f3729db0f466f607eb0e53c1ed0c431f Mon Sep 17 00:00:00 2001 +From: Lulu Cai <cailulu@loongson.cn> +Date: Wed, 11 Oct 2023 10:20:45 +0800 +Subject: PATCH 016/123 as: fixed internal error when immediate value of + relocation overflow. + +The as and ld use _bfd_error_handler to output error messages when +checking relocation alignment and relocation overflow. However, the +abfd value passed by as to the function is NULL, resulting in an +internal error. The ld passes a non-null value to the function, +so it can output an error message normally. +--- + bfd/elfxx-loongarch.c | 22 ++++++++++++++++------ + gas/config/tc-loongarch.c | 2 +- + gas/testsuite/gas/loongarch/imm_overflow.d | 3 +++ + gas/testsuite/gas/loongarch/imm_overflow.l | 2 ++ + gas/testsuite/gas/loongarch/imm_overflow.s | 4 ++++ + gas/testsuite/gas/loongarch/imm_unalign.d | 3 +++ + gas/testsuite/gas/loongarch/imm_unalign.l | 2 ++ + gas/testsuite/gas/loongarch/imm_unalign.s | 6 ++++++ + 8 files changed, 37 insertions(+), 7 deletions(-) + create mode 100644 gas/testsuite/gas/loongarch/imm_overflow.d + create mode 100644 gas/testsuite/gas/loongarch/imm_overflow.l + create mode 100644 gas/testsuite/gas/loongarch/imm_overflow.s + create mode 100644 gas/testsuite/gas/loongarch/imm_unalign.d + create mode 100644 gas/testsuite/gas/loongarch/imm_unalign.l + create mode 100644 gas/testsuite/gas/loongarch/imm_unalign.s + +diff --git a/bfd/elfxx-loongarch.c b/bfd/elfxx-loongarch.c +index fd9507ce..7f298c08 100644 +--- a/bfd/elfxx-loongarch.c ++++ b/bfd/elfxx-loongarch.c +@@ -1679,9 +1679,14 @@ reloc_sign_bits (bfd *abfd, reloc_howto_type *howto, bfd_vma *fix_val) + if (howto->rightshift + && (val & ((((bfd_signed_vma) 1) << howto->rightshift) - 1))) + { +- (*_bfd_error_handler) (_("%pB: relocation %s right shift %d error 0x%lx"), +- abfd, howto->name, howto->rightshift, (long) val); +- bfd_set_error (bfd_error_bad_value); ++ /* The as passes NULL casued internal error, so it can not use _bfd_error_handler ++ output details, ld is not affected. */ ++ if (abfd != NULL) ++ { ++ (*_bfd_error_handler) (_("%pB: relocation %s right shift %d error 0x%lx"), ++ abfd, howto->name, howto->rightshift, (long) val); ++ bfd_set_error (bfd_error_bad_value); ++ } + return false; + } + +@@ -1693,9 +1698,14 @@ reloc_sign_bits (bfd *abfd, reloc_howto_type *howto, bfd_vma *fix_val) + high part: from sign bit to highest bit. */ + if ((val & ~mask) && ((val & ~mask) != ~mask)) + { +- (*_bfd_error_handler) (_("%pB: relocation %s overflow 0x%lx"), +- abfd, howto->name, (long) val); +- bfd_set_error (bfd_error_bad_value); ++ /* The as passes NULL casued internal error, so it can not use _bfd_error_handler ++ output details, ld is not affected. */ ++ if (abfd != NULL) ++ { ++ (*_bfd_error_handler) (_("%pB: relocation %s overflow 0x%lx"), ++ abfd, howto->name, (long) val); ++ bfd_set_error (bfd_error_bad_value); ++ } + return false; + } + +diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c +index 059a1711..49c70bf1 100644 +--- a/gas/config/tc-loongarch.c ++++ b/gas/config/tc-loongarch.c +@@ -1236,7 +1236,7 @@ static void fix_reloc_insn (fixS *fixP, bfd_vma reloc_val, char *buf) + insn = bfd_getl32 (buf); + + if (!loongarch_adjust_reloc_bitsfield (NULL, howto, &reloc_val)) +- as_warn_where (fixP->fx_file, fixP->fx_line, "Reloc overflow"); ++ as_bad_where (fixP->fx_file, fixP->fx_line, "Reloc overflow"); + + insn = (insn & (insn_t)howto->src_mask) + | ((insn & (~(insn_t)howto->dst_mask)) | reloc_val); +diff --git a/gas/testsuite/gas/loongarch/imm_overflow.d b/gas/testsuite/gas/loongarch/imm_overflow.d +new file mode 100644 +index 00000000..50a65b7c +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/imm_overflow.d +@@ -0,0 +1,3 @@ ++#as: ++#source: imm_overflow.s ++#error_output: imm_overflow.l +diff --git a/gas/testsuite/gas/loongarch/imm_overflow.l b/gas/testsuite/gas/loongarch/imm_overflow.l +new file mode 100644 +index 00000000..449b3c2a +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/imm_overflow.l +@@ -0,0 +1,2 @@ ++.*Assembler messages: ++.*Error: Reloc overflow +diff --git a/gas/testsuite/gas/loongarch/imm_overflow.s b/gas/testsuite/gas/loongarch/imm_overflow.s +new file mode 100644 +index 00000000..9aac396a +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/imm_overflow.s +@@ -0,0 +1,4 @@ ++.L1: ++ nop ++ .fill 0x3ffffff, 4, 0 ++ b .L1 +diff --git a/gas/testsuite/gas/loongarch/imm_unalign.d b/gas/testsuite/gas/loongarch/imm_unalign.d +new file mode 100644 +index 00000000..1deb5025 +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/imm_unalign.d +@@ -0,0 +1,3 @@ ++#as: ++#source: imm_unalign.s ++#error_output: imm_unalign.l +diff --git a/gas/testsuite/gas/loongarch/imm_unalign.l b/gas/testsuite/gas/loongarch/imm_unalign.l +new file mode 100644 +index 00000000..449b3c2a +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/imm_unalign.l +@@ -0,0 +1,2 @@ ++.*Assembler messages: ++.*Error: Reloc overflow +diff --git a/gas/testsuite/gas/loongarch/imm_unalign.s b/gas/testsuite/gas/loongarch/imm_unalign.s +new file mode 100644 +index 00000000..a853bdcb +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/imm_unalign.s +@@ -0,0 +1,6 @@ ++.L1: ++ .2byte 0x12 ++ ++.L2: ++ .fill 1, 4, 0 ++ b .L1 +-- +2.33.0 +
View file
_service:tar_scm:asan-buffer-overflow-in-loongarch_elf_rtype_to_howto.patch
Added
@@ -0,0 +1,110 @@ +From 4eb7459bdbdb37611f8d993171c5d72fa347a143 Mon Sep 17 00:00:00 2001 +From: Alan Modra <amodra@gmail.com> +Date: Tue, 26 Dec 2023 22:46:56 +1030 +Subject: PATCH 030/123 asan: buffer overflow in loongarch_elf_rtype_to_howto + +Seen when running ld-loongarch-elf/tlsdesc-dso test. +elfxx-loongarch.c:1844:32: runtime error: index 125 out of bounds for +type 'loongarch_reloc_howto_type 124' + +So either the loongarch_howto_table needs three more +LOONGARCH_EMPTY_HOWTO entries, or loongarch_elf_rtype_to_howto should +be testing for r_type < ARRAY_SIZE (loongarch_howto_table). I figure +it's worth wasting a little more space to get faster lookup. + + * elfxx-loongarch.c (loongarch_howto_table): Add + LOONGARCH_EMPTY_HOWTO entries for 121..123. + (loongarch_elf_rtype_to_howto): Don't support slow lookup. + Assert exact table size and r_type indexing. Omit return cast. + (loongarch_reloc_name_lookup): Omit assertion and return cast. + (loongarch_reloc_type_lookup): Likewise. +--- + bfd/elfxx-loongarch.c | 32 +++++++++++--------------------- + 1 file changed, 11 insertions(+), 21 deletions(-) + +diff --git a/bfd/elfxx-loongarch.c b/bfd/elfxx-loongarch.c +index 310e6d62..4fe8cbff 100644 +--- a/bfd/elfxx-loongarch.c ++++ b/bfd/elfxx-loongarch.c +@@ -1776,6 +1776,10 @@ static loongarch_reloc_howto_type loongarch_howto_table = + NULL, /* adjust_reloc_bits. */ + "desc_call"), /* larch_reloc_type_name. */ + ++ LOONGARCH_EMPTY_HOWTO (121), ++ LOONGARCH_EMPTY_HOWTO (122), ++ LOONGARCH_EMPTY_HOWTO (123), ++ + /* For pcaddi, ld_pc_hi20 + ld_pc_lo12 can relax to ld_pcrel20_s2. */ + LOONGARCH_HOWTO (R_LARCH_TLS_LD_PCREL20_S2, /* type (124). */ + 2, /* rightshift. */ +@@ -1834,19 +1838,11 @@ static loongarch_reloc_howto_type loongarch_howto_table = + reloc_howto_type * + loongarch_elf_rtype_to_howto (bfd *abfd, unsigned int r_type) + { +- if(r_type < R_LARCH_count) ++ if (r_type < R_LARCH_count) + { +- /* For search table fast. */ +- /* + BFD_ASSERT (ARRAY_SIZE (loongarch_howto_table) == R_LARCH_count); +- */ +- +- if (loongarch_howto_tabler_type.howto.type == r_type) +- return (reloc_howto_type *)&loongarch_howto_tabler_type; +- +- for (size_t i = 0; i < ARRAY_SIZE (loongarch_howto_table); i++) +- if (loongarch_howto_tablei.howto.type == r_type) +- return (reloc_howto_type *)&loongarch_howto_tablei; ++ BFD_ASSERT (loongarch_howto_tabler_type.howto.type == r_type); ++ return &loongarch_howto_tabler_type.howto; + } + + (*_bfd_error_handler) (_("%pB: unsupported relocation type %#x"), +@@ -1858,19 +1854,14 @@ loongarch_elf_rtype_to_howto (bfd *abfd, unsigned int r_type) + reloc_howto_type * + loongarch_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, const char *r_name) + { +- /* +- BFD_ASSERT (ARRAY_SIZE (loongarch_howto_table) == R_LARCH_count); +- */ +- + for (size_t i = 0; i < ARRAY_SIZE (loongarch_howto_table); i++) + if (loongarch_howto_tablei.howto.name + && strcasecmp (loongarch_howto_tablei.howto.name, r_name) == 0) +- return (reloc_howto_type *)&loongarch_howto_tablei; ++ return &loongarch_howto_tablei.howto; + + (*_bfd_error_handler) (_("%pB: unsupported relocation type %s"), + abfd, r_name); + bfd_set_error (bfd_error_bad_value); +- + return NULL; + } + +@@ -1888,20 +1879,19 @@ loongarch_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED, + { + BFD_ASSERT (BFD_RELOC_LARCH_RELAX - BFD_RELOC_LARCH_B16 + == R_LARCH_RELAX - R_LARCH_B16); +- loongarch_reloc_howto_type *ht = NULL; ++ loongarch_reloc_howto_type *ht; + ht = &loongarch_howto_tablecode - BFD_RELOC_LARCH_B16 + R_LARCH_B16; + BFD_ASSERT (ht->bfd_type == code); +- return (reloc_howto_type *)ht; ++ return &ht->howto; + } + + for (size_t i = 0; i < ARRAY_SIZE (loongarch_howto_table); i++) + if (loongarch_howto_tablei.bfd_type == code) +- return (reloc_howto_type *)&loongarch_howto_tablei; ++ return &loongarch_howto_tablei.howto; + + (*_bfd_error_handler) (_("%pB: unsupported bfd relocation type %#x"), + abfd, code); + bfd_set_error (bfd_error_bad_value); +- + return NULL; + } + +-- +2.33.0 +
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_service:tar_scm:gas-NEWS-ld-NEWS-Announce-LoongArch-changes-in-2.43.patch
Added
@@ -0,0 +1,126 @@ +From 448658bbccadde4f9170174dca842f09bc5651b7 Mon Sep 17 00:00:00 2001 +From: Lulu Cai <cailulu@loongson.cn> +Date: Fri, 26 Jul 2024 16:34:38 +0800 +Subject: PATCH 103/123 gas/NEWS, ld/NEWS: Announce LoongArch changes in 2.43 + +--- + gas/NEWS | 75 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + ld/NEWS | 18 ++++++++++++++ + 2 files changed, 93 insertions(+) + +diff --git a/gas/NEWS b/gas/NEWS +index 9ad24543..3a291e53 100644 +--- a/gas/NEWS ++++ b/gas/NEWS +@@ -1,5 +1,80 @@ + -*- text -*- + ++Changes in 2.43: ++ ++* Add support for LoongArch .option for fine-grained control of assembly ++ code options. ++ ++* The MIPS '--trap' command-line option now causes GAS to dynamically ++ track the ISA setting as code is assembled and to emit either trap or ++ breakpoint instructions according to whether the currently selected ISA ++ permits the use of trap instructions or not. Previously the ISA was ++ only checked at startup and GAS bailed out if the initial ISA was ++ incompatible with the '--trap' option. ++ ++* Support CFCMOV feature in Intel APX. Now, APX_F is fully supportted. ++ ++* Support CCMP and CTEST feature in Intel APX. ++ ++* Support zero-upper feature in Intel APX. ++ ++* Add a .base64 directive to the assembler which allows base64 encoded ++ binary data to be provided as strings. ++ ++* Add support for 'armv9.5-a' for -march in AArch64 GAS. ++ ++* In x86 Intel syntax undue mnemonic suffixes are now warned about. This is ++ a first step towards rejecting their use where unjustified. ++ ++* Assembler macros as well as the bodies of .irp / .irpc / .rept can now use ++ the syntax \+ to access the number of times a given macro has been executed. ++ This is similar to the already existing \@ syntax, except that the count is ++ maintained on a per-macro basis. ++ ++* Support the NF feature in Intel APX. ++ ++* Remove KEYLOCKER and SHA promotions from EVEX MAP4. ++ ++* References to FB and dollar labels, when supported, are no longer permitted ++ in a radix other than 10. (Note that definitions of such labels were already ++ thus restricted, except that leading zeroes were permitted.) ++ ++* Remove support for RISC-V privileged spec 1.9.1, but linker can still ++ recognize it in case of linking old objects. ++ ++* Add support for RISC-V Zacas extension with version 1.0. ++ ++* Add support for RISC-V Zcmp extension with version 1.0. ++ ++* Add support for RISC-V Zfbfmin extension with version 1.0. ++ ++* Add support for RISC-V Zvfbfmin extension with version 1.0. ++ ++* Add support for RISC-V Zvfbfwma extension with version 1.0. ++ ++* Add support for RISC-V Smcsrind/Sscsrind extension with version 1.0. ++ ++* Add support for RISC-V CORE-V extensions (XCvMem, XCvBi, XCvElw) with ++ version 1.0. ++ ++* Add support for RISC-V SiFive cease extension (XSfCease) with version 1.0. ++ ++* The base register operand in D(X,B) and D(L,B) may be explicitly omitted ++ in assembly on s390. It can now be coded as D(X,) or D(L,) instead of D(X,0) ++ D(X,%r0), D(L,0), and D(L,%r0). ++ ++* Warn when a register name type does not match the operand type on s390. ++ Add support for s390-specific option "warn-regtype-mismatch=strict|relaxed| ++ no" to override the register name type check behavior. The default ++ is "relaxed", which allows floating-point and vector register names to be ++ used interchangeably. ++ ++* Add support for 'armv9.5-a' for -march in Arm GAS. ++ ++* Add support for the AArch64 Lookup Table Extension (LUT). ++ ++* Add support for the AArch64 Lookup Table Extension v2 (LUTv2). ++ + Changes in 2.42: + + * Experimental support in GAS to synthesize CFI for ABI-conformant, +diff --git a/ld/NEWS b/ld/NEWS +index 687b5190..14e5207c 100644 +--- a/ld/NEWS ++++ b/ld/NEWS +@@ -1,5 +1,23 @@ + -*- text -*- + ++Changes in 2.43: ++ ++* Add support for LoongArch DT_RELR (compressed R_LARCH_RELATIVE). ++ ++* Put .got .got.plt in the relro to make it read-only after relocation. ++ ++* Add -z isa-level-report=none|all|needed|used to the x86 ELF linker ++ to report needed and used x86-64 ISA levels. ++ ++* Add --rosegment option which changes the -z separate-code option so that ++ only one read-only segment is created (instead of two). (The option name ++ is misleading, but it matches the name used by LLD and GOLD). ++ ++* Add --section-ordering-file <FILE> option to add extra mapping of input ++ sections to output sections. ++ ++* Add -plugin-save-temps to store plugin intermediate files permanently. ++ + Changes in 2.42: + + * Add -z mark-plt/-z nomark-plt options to x86-64 ELF linker to mark PLT +-- +2.33.0 +
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_service:tar_scm:loongarch-index-shadows-global.patch
Added
@@ -0,0 +1,31 @@ +From 8e018f9efeab0a04c045f6fd06d493a00a027dd9 Mon Sep 17 00:00:00 2001 +From: Alan Modra <amodra@gmail.com> +Date: Wed, 3 Jan 2024 16:03:48 +1030 +Subject: PATCH 040/123 loongarch: 'index' shadows global + +Avoid an error when compiling with older versions of gcc. + + * elfnn-loongarch.c (loongarch_relax_align): Rename "index" to + "sym_index". +--- + bfd/elfnn-loongarch.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index 73e4b819..3d858169 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -4302,8 +4302,8 @@ loongarch_relax_align (bfd *abfd, asection *sec, + { + bfd_vma addend, max = 0, alignment = 1; + +- int index = ELFNN_R_SYM (rel->r_info); +- if (index > 0) ++ int sym_index = ELFNN_R_SYM (rel->r_info); ++ if (sym_index > 0) + { + alignment = 1 << (rel->r_addend & 0xff); + max = rel->r_addend >> 8; +-- +2.33.0 +
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_service:tar_scm:loongarch-ld-testsuite-xpasses.patch
Added
@@ -0,0 +1,112 @@ +From 33403fb9c012c0eecf216ca9e9398a4ed8de81df Mon Sep 17 00:00:00 2001 +From: Alan Modra <amodra@gmail.com> +Date: Wed, 7 Aug 2024 07:56:33 +0930 +Subject: PATCH 106/123 loongarch ld testsuite xpasses + +Some tests started passing with commit 3a83f0342e54. However, +supporting a changed ld output format is not so simple, and the change +to the loongarch_elf_hash_table macro needs further changes to the +rest of the code. It is true that some uses of +loongarch_elf_hash_table do not need to check the type of the hash +table, but others like loongarch_elf_relax_section do need to check. +bfd_relax_section is called in lang_size_sections using the input bfd, +not the output bfd. If the input bfd may be of different type to the +output, then the hash table type must be checked before accessing +elements of the hash table. This patch corrects +loongarch_elf_relax_section. I haven't checked all the uses of the +hash table throughout the loongarch backend. + +bfd/ + * elfnn-loongarch.c (loongarch_elf_relax_section): Don't relax + unless the hash table is loongarch_elf_link_hash_table. + Move variable declarations. Formatting. +ld/ + * testsuite/ld-elf/pr21884.d: Don't xfail loongarach. + * testsuite/ld-unique/pr21529.d: Likewise. +--- + bfd/elfnn-loongarch.c | 18 ++++++++++-------- + ld/testsuite/ld-elf/pr21884.d | 2 +- + ld/testsuite/ld-unique/pr21529.d | 2 +- + 3 files changed, 12 insertions(+), 10 deletions(-) + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index c2468443..adf16ddc 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -5246,16 +5246,15 @@ loongarch_get_max_alignment (asection *sec) + + static bool + loongarch_elf_relax_section (bfd *abfd, asection *sec, +- struct bfd_link_info *info, +- bool *again) ++ struct bfd_link_info *info, ++ bool *again) + { +- struct loongarch_elf_link_hash_table *htab = loongarch_elf_hash_table (info); +- struct bfd_elf_section_data *data = elf_section_data (sec); +- Elf_Internal_Shdr *symtab_hdr = &elf_symtab_hdr (abfd); +- Elf_Internal_Rela *relocs; + *again = false; +- bfd_vma max_alignment = 0; ++ if (!is_elf_hash_table (info->hash) ++ || elf_hash_table_id (elf_hash_table (info)) != LARCH_ELF_DATA) ++ return true; + ++ struct loongarch_elf_link_hash_table *htab = loongarch_elf_hash_table (info); + if (bfd_link_relocatable (info) + || sec->sec_flg0 + || (sec->flags & SEC_RELOC) == 0 +@@ -5267,6 +5266,8 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, + || *(htab->data_segment_phase) == 4) + return true; + ++ struct bfd_elf_section_data *data = elf_section_data (sec); ++ Elf_Internal_Rela *relocs; + if (data->relocs) + relocs = data->relocs; + else if (!(relocs = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, +@@ -5277,6 +5278,7 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, + && !bfd_malloc_and_get_section (abfd, sec, &data->this_hdr.contents)) + return true; + ++ Elf_Internal_Shdr *symtab_hdr = &elf_symtab_hdr (abfd); + if (symtab_hdr->sh_info != 0 + && !symtab_hdr->contents + && !(symtab_hdr->contents = +@@ -5289,7 +5291,7 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, + + /* Estimate the maximum alignment for all output sections once time + should be enough. */ +- max_alignment = htab->max_alignment; ++ bfd_vma max_alignment = htab->max_alignment; + if (max_alignment == (bfd_vma) -1) + { + max_alignment = loongarch_get_max_alignment (sec); +diff --git a/ld/testsuite/ld-elf/pr21884.d b/ld/testsuite/ld-elf/pr21884.d +index e289b419..3d44ccfe 100644 +--- a/ld/testsuite/ld-elf/pr21884.d ++++ b/ld/testsuite/ld-elf/pr21884.d +@@ -3,7 +3,7 @@ + #ld: -T pr21884.t + #objdump: -b binary -s + #xfail: aarch64*-*-* arm*-*-* avr-*-* ia64-*-* m68hc1*-*-* nds32*-*-* +-#xfail: riscv*-*-* score-*-* v850-*-* loongarch*-*-* ++#xfail: riscv*-*-* score-*-* v850-*-* + # Skip targets which can't change output format to binary. + + .*: file format binary +diff --git a/ld/testsuite/ld-unique/pr21529.d b/ld/testsuite/ld-unique/pr21529.d +index 896f8722..fb637943 100644 +--- a/ld/testsuite/ld-unique/pr21529.d ++++ b/ld/testsuite/ld-unique/pr21529.d +@@ -1,6 +1,6 @@ + #ld: --oformat binary -T pr21529.ld -e main + #objdump: -s -b binary +-#xfail: aarch64*-*-* arm*-*-* avr-*-* ia64-*-* m68hc1*-*-* nds32*-*-* riscv*-*-* score-*-* v850-*-* loongarch*-*-* ++#xfail: aarch64*-*-* arm*-*-* avr-*-* ia64-*-* m68hc1*-*-* nds32*-*-* riscv*-*-* score-*-* v850-*-* + # Skip targets which can't change output format to binary. + + #pass +-- +2.33.0 +
View file
_service:tar_scm:remove-file-produced-by-bison.patch
Added
@@ -0,0 +1,1920 @@ +From 68485a414f2edc538ca4f4f292caea86b58acce3 Mon Sep 17 00:00:00 2001 +From: Xin Wang <wangxin03@loongson.cn> +Date: Wed, 30 Oct 2024 19:47:55 +0800 +Subject: PATCH 122/123 remove file produced by bison + +--- + gas/config/loongarch-parse.c | 1901 ---------------------------------- + 1 file changed, 1901 deletions(-) + delete mode 100644 gas/config/loongarch-parse.c + +diff --git a/gas/config/loongarch-parse.c b/gas/config/loongarch-parse.c +deleted file mode 100644 +index 2fad9e0b..00000000 +--- a/gas/config/loongarch-parse.c ++++ /dev/null +@@ -1,1901 +0,0 @@ +-/* A Bison parser, made by GNU Bison 3.8.2. */ +- +-/* Bison implementation for Yacc-like parsers in C +- +- Copyright (C) 1984, 1989-1990, 2000-2015, 2018-2021 Free Software Foundation, +- Inc. +- +- This program is free software: you can redistribute it and/or modify +- it under the terms of the GNU General Public License as published by +- the Free Software Foundation, either version 3 of the License, or +- (at your option) any later version. +- +- This program is distributed in the hope that it will be useful, +- but WITHOUT ANY WARRANTY; without even the implied warranty of +- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- GNU General Public License for more details. +- +- You should have received a copy of the GNU General Public License +- along with this program. If not, see <https://www.gnu.org/licenses/>. */ +- +-/* As a special exception, you may create a larger work that contains +- part or all of the Bison parser skeleton and distribute that work +- under terms of your choice, so long as that work isn't itself a +- parser generator using the skeleton or a modified version thereof +- as a parser skeleton. Alternatively, if you modify or redistribute +- the parser skeleton itself, you may (at your option) remove this +- special exception, which will cause the skeleton and the resulting +- Bison output files to be licensed under the GNU General Public +- License without this special exception. +- +- This special exception was added by the Free Software Foundation in +- version 2.2 of Bison. */ +- +-/* C LALR(1) parser skeleton written by Richard Stallman, by +- simplifying the original so-called "semantic" parser. */ +- +-/* DO NOT RELY ON FEATURES THAT ARE NOT DOCUMENTED in the manual, +- especially those whose name start with YY_ or yy_. They are +- private implementation details that can be changed or removed. */ +- +-/* All symbols defined below should begin with yy or YY, to avoid +- infringing on user name space. This should be done even for local +- variables, as they might otherwise be expanded by user macros. +- There are some unavoidable exceptions within include files to +- define necessary library symbols; they are noted "INFRINGES ON +- USER NAME SPACE" below. */ +- +-/* Identify Bison output, and Bison version. */ +-#define YYBISON 30802 +- +-/* Bison version string. */ +-#define YYBISON_VERSION "3.8.2" +- +-/* Skeleton name. */ +-#define YYSKELETON_NAME "yacc.c" +- +-/* Pure parsers. */ +-#define YYPURE 0 +- +-/* Push parsers. */ +-#define YYPUSH 0 +- +-/* Pull parsers. */ +-#define YYPULL 1 +- +- +- +- +-/* First part of user prologue. */ +-#line 19 "./config/loongarch-parse.y" +- +-#include "as.h" +-#include "loongarch-lex.h" +-#include "loongarch-parse.h" +-static void yyerror (const char *s ATTRIBUTE_UNUSED) +-{ +-}; +-int yylex (void); +- +- +-static struct reloc_info *top, *end; +- +-static expressionS const_0 = +-{ +- .X_op = O_constant, +- .X_add_number = 0 +-}; +- +-static int +-is_const (struct reloc_info *info) +-{ +- return (info->type == BFD_RELOC_LARCH_SOP_PUSH_ABSOLUTE +- && info->value.X_op == O_constant); +-} +- +-int +-loongarch_parse_expr (const char *expr, +- struct reloc_info *reloc_stack_top, +- size_t max_reloc_num, +- size_t *reloc_num, +- offsetT *imm) +-{ +- int ret; +- struct yy_buffer_state *buffstate; +- top = reloc_stack_top; +- end = top + max_reloc_num; +- buffstate = yy_scan_string (expr); +- ret = yyparse (); +- +- if (ret == 0) +- { +- if (is_const (top - 1)) +- *imm = (--top)->value.X_add_number; +- else +- *imm = 0; +- *reloc_num = top - reloc_stack_top; +- } +- yy_delete_buffer (buffstate); +- +- return ret; +-} +- +-static void +-emit_const (offsetT imm) +-{ +- if (end <= top) +- as_fatal (_("expr too huge")); +- top->type = BFD_RELOC_LARCH_SOP_PUSH_ABSOLUTE; +- top->value.X_op = O_constant; +- top->value.X_add_number = imm; +- top++; +-} +- +-static const char * +-my_getExpression (expressionS *ep, const char *str) +-{ +- char *save_in, *ret; +- +- if (*str == ':') +- { +- unsigned long j; +- char *str_1 = (char *) str; +- j = strtol (str_1, &str_1, 10); +- get_internal_label (ep, j, *str_1 == 'f'); +- return NULL; +- } +- save_in = input_line_pointer; +- input_line_pointer = (char *)str; +- expression (ep); +- ret = input_line_pointer; +- input_line_pointer = save_in; +- return ret; +-} +- +-static void +-emit_const_var (const char *op) +-{ +- expressionS ep; +- +- if (end <= top) +- as_fatal (_("expr too huge")); +- +- my_getExpression (&ep, op); +- +- if (ep.X_op != O_constant) +- as_bad ("illegal operand: %s", op); +- +- top->value.X_op = O_constant; +- top->value.X_add_number = ep.X_add_number; +- top->type = BFD_RELOC_LARCH_SOP_PUSH_ABSOLUTE; +- top++; +-} +- +-static void +-reloc (const char *op_c_str, const char *id_c_str, offsetT addend) +-{ +- expressionS id_sym_expr; +- bfd_reloc_code_real_type btype; +- +- if (end <= top) +- as_fatal (_("expr too huge")); +- +- /* For compatible old asm code. */
View file
_service:tar_scm:replace-space-with-tab.patch
Added
@@ -0,0 +1,500 @@ +From c4e6b6be66500cb31f7d123377a90fed17dd992a Mon Sep 17 00:00:00 2001 +From: Xin Wang <wangxin03@loongson.cn> +Date: Wed, 30 Oct 2024 19:48:09 +0800 +Subject: PATCH 123/123 replace space with tab + +--- + bfd/elfnn-loongarch.c | 322 +++++++++++++++++++++--------------------- + 1 file changed, 161 insertions(+), 161 deletions(-) + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index 8b9628f7..13216ef9 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -159,7 +159,7 @@ loongarch_elf_new_section_hook (bfd *abfd, asection *sec) + + sdata = bfd_zalloc (abfd, amt); + if (!sdata) +- return false; ++ return false; + sec->used_by_bfd = sdata; + } + +@@ -993,17 +993,17 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, + r_type = loongarch_tls_transition (abfd, info, h, r_symndx, r_type); + + /* I don't want to spend time supporting DT_RELR with old object +- files doing stack-based relocs. */ ++ files doing stack-based relocs. */ + if (info->enable_dt_relr +- && r_type >= R_LARCH_SOP_PUSH_PCREL +- && r_type <= R_LARCH_SOP_POP_32_U) +- { +- /* xgettext:c-format */ +- _bfd_error_handler (_("%pB: stack based reloc type (%u) is not " +- "supported with -z pack-relative-relocs"), +- abfd, r_type); +- return false; +- } ++ && r_type >= R_LARCH_SOP_PUSH_PCREL ++ && r_type <= R_LARCH_SOP_POP_32_U) ++ { ++ /* xgettext:c-format */ ++ _bfd_error_handler (_("%pB: stack based reloc type (%u) is not " ++ "supported with -z pack-relative-relocs"), ++ abfd, r_type); ++ return false; ++ } + + switch (r_type) + { +@@ -1218,19 +1218,19 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, + return false; + break; + +- case R_LARCH_ALIGN: +- /* Check against irrational R_LARCH_ALIGN relocs which may cause +- removing an odd number of bytes and disrupt DT_RELR. */ +- if (rel->r_offset % 4 != 0) +- { +- /* xgettext:c-format */ +- _bfd_error_handler ( +- _("%pB: R_LARCH_ALIGN with offset %" PRId64 " not aligned " +- "to instruction boundary"), +- abfd, (uint64_t) rel->r_offset); +- return false; +- } +- break; ++ case R_LARCH_ALIGN: ++ /* Check against irrational R_LARCH_ALIGN relocs which may cause ++ removing an odd number of bytes and disrupt DT_RELR. */ ++ if (rel->r_offset % 4 != 0) ++ { ++ /* xgettext:c-format */ ++ _bfd_error_handler ( ++ _("%pB: R_LARCH_ALIGN with offset %" PRId64 " not aligned " ++ "to instruction boundary"), ++ abfd, (uint64_t) rel->r_offset); ++ return false; ++ } ++ break; + + default: + break; +@@ -1948,7 +1948,7 @@ maybe_set_textrel (struct elf_link_hash_entry *h, void *info_p) + + static bool + record_relr (struct loongarch_elf_link_hash_table *htab, asection *sec, +- bfd_vma off, asection *sreloc) ++ bfd_vma off, asection *sreloc) + { + struct relr_entry **sec_relr = &loongarch_elf_section_data (sec)->relr; + +@@ -1960,14 +1960,14 @@ record_relr (struct loongarch_elf_link_hash_table *htab, asection *sec, + if (htab->relr_count >= htab->relr_alloc) + { + if (htab->relr_alloc == 0) +- htab->relr_alloc = 4096; ++ htab->relr_alloc = 4096; + else +- htab->relr_alloc *= 2; ++ htab->relr_alloc *= 2; + + htab->relr = bfd_realloc (htab->relr, +- htab->relr_alloc * sizeof (*htab->relr)); ++ htab->relr_alloc * sizeof (*htab->relr)); + if (!htab->relr) +- return false; ++ return false; + } + htab->relrhtab->relr_count.sec = sec; + htab->relrhtab->relr_count.off = off; +@@ -1994,11 +1994,11 @@ record_relr_local_got_relocs (bfd *input_bfd, struct bfd_link_info *info) + bfd_vma off = local_got_offsetsi; + + /* FIXME: If the local symbol is in SHN_ABS then emitting +- a relative relocation is not correct, but it seems to be wrong +- in loongarch_elf_relocate_section too. */ ++ a relative relocation is not correct, but it seems to be wrong ++ in loongarch_elf_relocate_section too. */ + if (local_tls_typei == GOT_NORMAL +- && !record_relr (htab, htab->elf.sgot, off, htab->elf.srelgot)) +- return false; ++ && !record_relr (htab, htab->elf.sgot, off, htab->elf.srelgot)) ++ return false; + } + + return true; +@@ -2036,7 +2036,7 @@ record_relr_dyn_got_relocs (struct elf_link_hash_entry *h, void *inf) + return true; + + if (!record_relr (htab, htab->elf.sgot, h->got.offset, +- htab->elf.srelgot)) ++ htab->elf.srelgot)) + return false; + + return true; +@@ -2044,7 +2044,7 @@ record_relr_dyn_got_relocs (struct elf_link_hash_entry *h, void *inf) + + static bool + record_relr_non_got_relocs (bfd *input_bfd, struct bfd_link_info *info, +- asection *sec) ++ asection *sec) + { + asection *sreloc; + struct loongarch_elf_link_hash_table *htab; +@@ -2072,7 +2072,7 @@ record_relr_non_got_relocs (bfd *input_bfd, struct bfd_link_info *info, + symtab_hdr = &elf_symtab_hdr (input_bfd); + sym_hashes = elf_sym_hashes (input_bfd); + relocs = _bfd_elf_link_info_read_relocs (input_bfd, info, sec, NULL, +- NULL, info->keep_memory); ++ NULL, info->keep_memory); + BFD_ASSERT (relocs != NULL); + rel_end = relocs + sec->reloc_count; + for (rel = relocs; rel < rel_end; rel++) +@@ -2083,59 +2083,59 @@ record_relr_non_got_relocs (bfd *input_bfd, struct bfd_link_info *info, + asection *def_sec = NULL; + + if ((r_type != R_LARCH_64 && r_type != R_LARCH_32) +- || rel->r_offset % 2 != 0) +- continue; ++ || rel->r_offset % 2 != 0) ++ continue; + + /* The logical below must match loongarch_elf_relocate_section. */ + if (r_symndx < symtab_hdr->sh_info) +- { +- /* A local symbol. */ +- Elf_Internal_Sym *isym; +- isym = bfd_sym_from_r_symndx (&htab->elf.sym_cache, input_bfd, +- r_symndx); +- BFD_ASSERT(isym != NULL); +- +- /* Local STT_GNU_IFUNC symbol uses R_LARCH_IRELATIVE for +- R_LARCH_NN, not R_LARCH_RELATIVE. */ +- if (ELF_ST_TYPE (isym->st_info) == STT_GNU_IFUNC) +- continue; +- def_sec = bfd_section_from_elf_index (input_bfd, isym->st_shndx); +- } ++ { ++ /* A local symbol. */ ++ Elf_Internal_Sym *isym; ++ isym = bfd_sym_from_r_symndx (&htab->elf.sym_cache, input_bfd, ++ r_symndx); ++ BFD_ASSERT(isym != NULL); ++ ++ /* Local STT_GNU_IFUNC symbol uses R_LARCH_IRELATIVE for ++ R_LARCH_NN, not R_LARCH_RELATIVE. */ ++ if (ELF_ST_TYPE (isym->st_info) == STT_GNU_IFUNC) ++ continue; ++ def_sec = bfd_section_from_elf_index (input_bfd, isym->st_shndx); ++ } + else +- { +- h = sym_hashesr_symndx - symtab_hdr->sh_info; +- while (h->root.type == bfd_link_hash_indirect +- || h->root.type == bfd_link_hash_warning) +- h = (struct elf_link_hash_entry *) h->root.u.i.link; +- +- /* Filter out symbols that cannot have a relative reloc. */
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