Projects
Eulaceura:Factory
Jailhouse
_service:obs_scm:0004-add-Phytium-e2000q-eth-sm...
Sign Up
Log In
Username
Password
Overview
Repositories
Revisions
Requests
Users
Attributes
Meta
File _service:obs_scm:0004-add-Phytium-e2000q-eth-smallcpu-isolation-configures.patch of Package Jailhouse
From e77691e0bfec299ad1975bccaf61b41fc888b0b7 Mon Sep 17 00:00:00 2001 From: huanglei <huanglei1@kylinos.cn> Date: Wed, 12 Apr 2023 19:32:37 -0700 Subject: [PATCH 04/12] add Phytium e2000q eth/smallcpu isolation configures [KEYWORDS] jailhouse [TO SOLVE] [TEST SUGGESTION] none [SUBMIT BY] huanglei [REVIEW BY] huanglei [TEST BY] huanglei --- configs/arm64/dts/e2000q_inmate_eth.dts | 197 +++ .../arm64/dts/e2000q_inmate_eth_smallcpu.dts | 194 +++ configs/arm64/dts/e2000q_main_eth.dts | 1297 +++++++++++++++++ configs/arm64/e2000q-inmate-eth-smallcpu.c | 157 ++ configs/arm64/e2000q-inmate-eth.c | 157 ++ configs/arm64/e2000q-main-eth.c | 333 +++++ 6 files changed, 2335 insertions(+) create mode 100644 configs/arm64/dts/e2000q_inmate_eth.dts create mode 100644 configs/arm64/dts/e2000q_inmate_eth_smallcpu.dts create mode 100644 configs/arm64/dts/e2000q_main_eth.dts create mode 100644 configs/arm64/e2000q-inmate-eth-smallcpu.c create mode 100644 configs/arm64/e2000q-inmate-eth.c create mode 100644 configs/arm64/e2000q-main-eth.c diff --git a/configs/arm64/dts/e2000q_inmate_eth.dts b/configs/arm64/dts/e2000q_inmate_eth.dts new file mode 100644 index 00000000..04b19549 --- /dev/null +++ b/configs/arm64/dts/e2000q_inmate_eth.dts @@ -0,0 +1,197 @@ +/dts-v1/; + +/memreserve/ 0x0000000080000000 0x0000000000010000; +/ { + compatible = "phytium,e2000q"; + interrupt-parent = <0x01>; + #address-cells = <0x02>; + #size-cells = <0x02>; + model = "E2000Q vpx board"; + + aliases { + serial1 = "/soc/uart@2800d000"; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + cpu_suspend = <0xc4000001>; + cpu_off = <0x84000002>; + cpu_on = <0xc4000003>; + sys_poweroff = <0x84000008>; + sys_reset = <0x84000009>; + }; + + cpus { + #address-cells = <0x02>; + #size-cells = <0x00>; + + cpu-map { + + cluster0 { + + core0 { + cpu = <0x06>; + }; + }; + + cluster1 { + + core0 { + cpu = <0x07>; + }; + }; + }; + + l2-cache { + compatible = "cache"; + cache-level = <0x02>; + cache-unified; + cache-size = <0x100000>; + cache-line-size = <0x40>; + cache-sets = <0x10>; + phandle = <0x0b>; + }; + + cpu@100 { + device_type = "cpu"; + compatible = "phytium,ftc664\0arm,armv8"; + reg = <0x00 0x00>; + enable-method = "psci"; + clocks = <0x0a 0x00>; + i-cache-size = <0xc000>; + i-cache-line-size = <0x40>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x40>; + next-level-cache = <0x0b>; + phandle = <0x06>; + }; + + cpu@101 { + device_type = "cpu"; + compatible = "phytium,ftc664\0arm,armv8"; + reg = <0x00 0x100>; + enable-method = "psci"; + clocks = <0x0a 0x01>; + i-cache-size = <0xc000>; + i-cache-line-size = <0x40>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x40>; + next-level-cache = <0x0b>; + phandle = <0x07>; + }; + }; + + interrupt-controller@30800000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <0x03>; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + interrupt-controller; + reg = <0x00 0x30800000 0x00 0x20000 0x00 0x30880000 0x00 0x80000 0x00 0x30840000 0x00 0x10000 0x00 0x30850000 0x00 0x10000 0x00 0x30860000 0x00 0x10000>; + interrupts = <0x01 0x09 0x08>; + phandle = <0x01>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <0x01 0x0d 0x08 0x01 0x0e 0x08 0x01 0x0b 0x08 0x01 0x0a 0x08>; + clock-frequency = <0x2faf080>; + }; + + clocks { + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + + clk48mhz { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x2dc6c00>; + phandle = <0x14>; + }; + + clk50mhz { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x2faf080>; + phandle = <0x0d>; + }; + + clk100mhz { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x5f5e100>; + phandle = <0x0e>; + }; + + clk200mhz { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0xbebc200>; + phandle = <0x12>; + }; + + clk250mhz { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0xee6b280>; + phandle = <0x13>; + }; + + clk300mhz { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x11e1a300>; + }; + + clk600mhz { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x23c34600>; + phandle = <0x0f>; + }; + + clk1200mhz { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x47868c00>; + phandle = <0x0c>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <0x02>; + #size-cells = <0x02>; + dma-coherent; + ranges; + + uart@2800d000 { + compatible = "arm,pl011\0arm,primecell"; + reg = <0x00 0x2800d000 0x00 0x1000>; + interrupts = <0x00 0x54 0x04>; + clocks = <0x0e 0x0e>; + clock-names = "uartclk\0apb_pclk"; + status = "okay"; + }; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + ethernet@3200c000 { + compatible = "phytium,gem\0cdns,phytium-gem"; + reg = <0x00 0x3200c000 0x00 0x2000>; + interrupts = <0x00 0x37 0x04 0x00 0x38 0x04 0x00 0x39 0x04 0x00 0x3a 0x04 0x00 0x1c 0x04 0x00 0x1d 0x04 0x00 0x1e 0x04 0x00 0x1f 0x04>; + clock-names = "pclk\0hclk\0tx_clk\0tsu_clk"; + clocks = <0x13 0x14 0x14 0x13>; + magic-packet; + support-tsn; + status = "okay"; + phy-mode = "sgmii"; + use-mii; + }; +}; diff --git a/configs/arm64/dts/e2000q_inmate_eth_smallcpu.dts b/configs/arm64/dts/e2000q_inmate_eth_smallcpu.dts new file mode 100644 index 00000000..f062f390 --- /dev/null +++ b/configs/arm64/dts/e2000q_inmate_eth_smallcpu.dts @@ -0,0 +1,194 @@ +/dts-v1/; + +/memreserve/ 0x0000000080000000 0x0000000000010000; +/ { + compatible = "phytium,e2000q"; + interrupt-parent = <0x01>; + #address-cells = <0x02>; + #size-cells = <0x02>; + model = "E2000Q vpx board"; + + aliases { + serial1 = "/soc/uart@2800d000"; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + cpu_suspend = <0xc4000001>; + cpu_off = <0x84000002>; + cpu_on = <0xc4000003>; + sys_poweroff = <0x84000008>; + sys_reset = <0x84000009>; + }; + + cpus { + #address-cells = <0x02>; + #size-cells = <0x00>; + + cpu-map { + + cluster0 { + + core0 { + cpu = <0x08>; + }; + + core1 { + cpu = <0x09>; + }; + }; + }; + + + cpu@0 { + device_type = "cpu"; + compatible = "phytium,ftc310\0arm,armv8"; + reg = <0x00 0x200>; + enable-method = "psci"; + clocks = <0x0a 0x02>; + i-cache-size = <0x8000>; + i-cache-line-size = <0x40>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x40>; + next-level-cache = <0x0b>; + phandle = <0x08>; + }; + + l2-cache { + compatible = "cache"; + cache-level = <0x02>; + cache-unified; + cache-size = <0x100000>; + cache-line-size = <0x40>; + cache-sets = <0x10>; + phandle = <0x0b>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "phytium,ftc310\0arm,armv8"; + reg = <0x00 0x201>; + enable-method = "psci"; + clocks = <0x0a 0x02>; + i-cache-size = <0x8000>; + i-cache-line-size = <0x40>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x40>; + next-level-cache = <0x0b>; + phandle = <0x09>; + }; + }; + interrupt-controller@30800000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <0x03>; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + interrupt-controller; + reg = <0x00 0x30800000 0x00 0x20000 0x00 0x30880000 0x00 0x80000 0x00 0x30840000 0x00 0x10000 0x00 0x30850000 0x00 0x10000 0x00 0x30860000 0x00 0x10000>; + interrupts = <0x01 0x09 0x08>; + phandle = <0x01>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <0x01 0x0d 0x08 0x01 0x0e 0x08 0x01 0x0b 0x08 0x01 0x0a 0x08>; + clock-frequency = <0x2faf080>; + }; + + clocks { + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + + clk48mhz { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x2dc6c00>; + phandle = <0x14>; + }; + + clk50mhz { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x2faf080>; + phandle = <0x0d>; + }; + + clk100mhz { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x5f5e100>; + phandle = <0x0e>; + }; + + clk200mhz { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0xbebc200>; + phandle = <0x12>; + }; + + clk250mhz { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0xee6b280>; + phandle = <0x13>; + }; + + clk300mhz { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x11e1a300>; + }; + + clk600mhz { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x23c34600>; + phandle = <0x0f>; + }; + + clk1200mhz { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x47868c00>; + phandle = <0x0c>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <0x02>; + #size-cells = <0x02>; + dma-coherent; + ranges; + + uart@2800d000 { + compatible = "arm,pl011\0arm,primecell"; + reg = <0x00 0x2800d000 0x00 0x1000>; + interrupts = <0x00 0x54 0x04>; + clocks = <0x0e 0x0e>; + clock-names = "uartclk\0apb_pclk"; + status = "okay"; + }; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + ethernet@3200c000 { + compatible = "phytium,gem\0cdns,phytium-gem"; + reg = <0x00 0x3200c000 0x00 0x2000>; + interrupts = <0x00 0x37 0x04 0x00 0x38 0x04 0x00 0x39 0x04 0x00 0x3a 0x04 0x00 0x1c 0x04 0x00 0x1d 0x04 0x00 0x1e 0x04 0x00 0x1f 0x04>; + clock-names = "pclk\0hclk\0tx_clk\0tsu_clk"; + clocks = <0x13 0x14 0x14 0x13>; + magic-packet; + support-tsn; + status = "okay"; + phy-mode = "sgmii"; + use-mii; + }; +}; diff --git a/configs/arm64/dts/e2000q_main_eth.dts b/configs/arm64/dts/e2000q_main_eth.dts new file mode 100644 index 00000000..c574988c --- /dev/null +++ b/configs/arm64/dts/e2000q_main_eth.dts @@ -0,0 +1,1297 @@ +/dts-v1/; + +/memreserve/ 0x0000000080000000 0x0000000000010000; +/ { + compatible = "phytium,e2000q"; + interrupt-parent = <0x01>; + #address-cells = <0x02>; + #size-cells = <0x02>; + model = "E2000Q vpx board"; + + aliases { + serial0 = "/soc/uart@2800c000"; + serial1 = "/soc/uart@2800d000"; + serial2 = "/soc/uart@2800e000"; + serial3 = "/soc/uart@2800f000"; + ethernet0 = "/soc/ethernet@3200c000"; + ethernet1 = "/soc/ethernet@3200e000"; + ethernet2 = "/soc/ethernet@32010000"; + ethernet3 = "/soc/ethernet@32012000"; + serial4 = "/soc/uart@2801A000"; + serial5 = "/soc/uart@28024000"; + serial6 = "/soc/uart@28028000"; + serial7 = "/soc/uart@2802A000"; + serial8 = "/soc/uart@28032000"; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + cpu_suspend = <0xc4000001>; + cpu_off = <0x84000002>; + cpu_on = <0xc4000003>; + sys_poweroff = <0x84000008>; + sys_reset = <0x84000009>; + }; + + firmware { + + scmi { + compatible = "arm,scmi"; + mboxes = <0x02 0x00 0x02 0x01>; + mbox-names = "tx\0rx"; + shmem = <0x03 0x04>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + protocol@13 { + reg = <0x13>; + #clock-cells = <0x01>; + phandle = <0x0a>; + }; + + protocol@15 { + reg = <0x15>; + #thermal-sensor-cells = <0x01>; + phandle = <0x05>; + }; + }; + + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + status = "disabled"; + }; + }; + + thermal-zones { + + sensor0 { + polling-delay-passive = <0x64>; + polling-delay = <0x3e8>; + thermal-sensors = <0x05 0x00>; + }; + + sensor1 { + polling-delay-passive = <0x64>; + polling-delay = <0x3e8>; + thermal-sensors = <0x05 0x01>; + }; + }; + + cpus { + #address-cells = <0x02>; + #size-cells = <0x00>; + + cpu-map { + + cluster0 { + + core0 { + cpu = <0x06>; + }; + }; + + cluster1 { + + core0 { + cpu = <0x07>; + }; + }; + + cluster2 { + + core0 { + cpu = <0x08>; + }; + + core1 { + cpu = <0x09>; + }; + }; + }; + + cpu@0 { + device_type = "cpu"; + compatible = "phytium,ftc310\0arm,armv8"; + reg = <0x00 0x200>; + enable-method = "psci"; + clocks = <0x0a 0x02>; + i-cache-size = <0x8000>; + i-cache-line-size = <0x40>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x40>; + next-level-cache = <0x0b>; + phandle = <0x08>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "phytium,ftc310\0arm,armv8"; + reg = <0x00 0x201>; + enable-method = "psci"; + clocks = <0x0a 0x02>; + i-cache-size = <0x8000>; + i-cache-line-size = <0x40>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x40>; + next-level-cache = <0x0b>; + phandle = <0x09>; + }; + + l2-cache { + compatible = "cache"; + cache-level = <0x02>; + cache-unified; + cache-size = <0x100000>; + cache-line-size = <0x40>; + cache-sets = <0x10>; + phandle = <0x0b>; + }; + + cpu@100 { + device_type = "cpu"; + compatible = "phytium,ftc664\0arm,armv8"; + reg = <0x00 0x00>; + enable-method = "psci"; + clocks = <0x0a 0x00>; + i-cache-size = <0xc000>; + i-cache-line-size = <0x40>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x40>; + next-level-cache = <0x0b>; + phandle = <0x06>; + }; + + cpu@101 { + device_type = "cpu"; + compatible = "phytium,ftc664\0arm,armv8"; + reg = <0x00 0x100>; + enable-method = "psci"; + clocks = <0x0a 0x01>; + i-cache-size = <0xc000>; + i-cache-line-size = <0x40>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x40>; + next-level-cache = <0x0b>; + phandle = <0x07>; + }; + }; + + interrupt-controller@30800000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <0x03>; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + interrupt-controller; + reg = <0x00 0x30800000 0x00 0x20000 0x00 0x30880000 0x00 0x80000 0x00 0x30840000 0x00 0x10000 0x00 0x30850000 0x00 0x10000 0x00 0x30860000 0x00 0x10000>; + interrupts = <0x01 0x09 0x08>; + phandle = <0x01>; + + gic-its@30820000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x00 0x30820000 0x00 0x20000>; + phandle = <0x10>; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0x01 0x07 0x08>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <0x01 0x0d 0x08 0x01 0x0e 0x08 0x01 0x0b 0x08 0x01 0x0a 0x08>; + clock-frequency = <0x2faf080>; + }; + + clocks { + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + + clk48mhz { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x2dc6c00>; + phandle = <0x14>; + }; + + clk50mhz { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x2faf080>; + phandle = <0x0d>; + }; + + clk100mhz { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x5f5e100>; + phandle = <0x0e>; + }; + + clk200mhz { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0xbebc200>; + phandle = <0x12>; + }; + + clk250mhz { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0xee6b280>; + phandle = <0x13>; + }; + + clk300mhz { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x11e1a300>; + }; + + clk600mhz { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x23c34600>; + phandle = <0x0f>; + }; + + clk1200mhz { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x47868c00>; + phandle = <0x0c>; + }; + }; + + iommu@30000000 { + compatible = "arm,smmu-v3"; + reg = <0x00 0x30000000 0x00 0x800000>; + interrupts = <0x00 0xf0 0x01 0x00 0xef 0x01 0x00 0xec 0x01 0x00 0xf2 0x01>; + interrupt-names = "eventq\0priq\0cmdq-sync\0gerror"; + dma-coherent; + #iommu-cells = <0x01>; + phandle = <0x11>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <0x02>; + #size-cells = <0x02>; + dma-coherent; + ranges; + + mmc@28000000 { + compatible = "phytium,mci"; + reg = <0x00 0x28000000 0x00 0x1000>; + interrupts = <0x00 0x48 0x04>; + clocks = <0x0c>; + clock-names = "phytium_mci_clk"; + status = "okay"; + bus-width = <0x08>; + mmc-hs200-1_8v; + max-frequency = <0x5f5e100>; + cap-mmc-hw-reset; + cap-mmc-highspeed; + no-sdio; + no-sd; + non-removable; + }; + + mmc@28001000 { + compatible = "phytium,mci"; + reg = <0x00 0x28001000 0x00 0x1000>; + interrupts = <0x00 0x49 0x04>; + clocks = <0x0c>; + clock-names = "phytium_mci_clk"; + status = "disabled"; + }; + + nand@28002000 { + compatible = "phytium,nfc"; + reg = <0x00 0x28002000 0x00 0x1000>; + interrupts = <0x00 0x4a 0x04>; + status = "disabled"; + }; + + uart@2800c000 { + compatible = "arm,pl011\0arm,primecell"; + reg = <0x00 0x2800c000 0x00 0x1000>; + interrupts = <0x00 0x53 0x04>; + clocks = <0x0e 0x0e>; + clock-names = "uartclk\0apb_pclk"; + status = "okay"; + }; + + uart@2800d000 { + compatible = "arm,pl011\0arm,primecell"; + reg = <0x00 0x2800d000 0x00 0x1000>; + interrupts = <0x00 0x54 0x04>; + clocks = <0x0e 0x0e>; + clock-names = "uartclk\0apb_pclk"; + status = "okay"; + }; + + uart@2800e000 { + compatible = "arm,pl011\0arm,primecell"; + reg = <0x00 0x2800e000 0x00 0x1000>; + interrupts = <0x00 0x55 0x04>; + clocks = <0x0e 0x0e>; + clock-names = "uartclk\0apb_pclk"; + status = "okay"; + }; + + uart@2800f000 { + compatible = "arm,pl011\0arm,primecell"; + reg = <0x00 0x2800f000 0x00 0x1000>; + interrupts = <0x00 0x56 0x04>; + clocks = <0x0e 0x0e>; + clock-names = "uartclk\0apb_pclk"; + status = "okay"; + }; + + lpc@28010000 { + compatible = "simple-mfd\0syscon"; + reg = <0x00 0x28010000 0x00 0x1000>; + reg-io-width = <0x04>; + #address-cells = <0x01>; + #size-cells = <0x01>; + ranges = <0x00 0x00 0x28010000 0x1000>; + + kcs@24 { + compatible = "phytium,e2000-kcs-bmc"; + reg = <0x24 0x01 0x30 0x01 0x3c 0x01>; + interrupts = <0x00 0x58 0x04>; + status = "disabled"; + }; + + kcs@28 { + compatible = "phytium,e2000-kcs-bmc"; + reg = <0x28 0x01 0x34 0x01 0x40 0x01>; + interrupts = <0x00 0x58 0x04>; + status = "disabled"; + }; + + kcs@2c { + compatible = "phytium,e2000-kcs-bmc"; + reg = <0x2c 0x01 0x38 0x01 0x44 0x01>; + interrupts = <0x00 0x58 0x04>; + status = "disabled"; + }; + + kcs@8c { + compatible = "phytium,e2000-kcs-bmc"; + reg = <0x8c 0x01 0x90 0x01 0x94 0x01>; + interrupts = <0x00 0x58 0x04>; + status = "disabled"; + }; + + bt@48 { + compatible = "phytium,e2000-bt-bmc"; + reg = <0x48 0x20>; + interrupts = <0x00 0x58 0x04>; + status = "disabled"; + }; + }; + + gpio@28034000 { + compatible = "phytium,gpio"; + reg = <0x00 0x28034000 0x00 0x1000>; + interrupts = <0x00 0x6c 0x04 0x00 0x6d 0x04 0x00 0x6e 0x04 0x00 0x6f 0x04 0x00 0x70 0x04 0x00 0x71 0x04 0x00 0x72 0x04 0x00 0x73 0x04 0x00 0x74 0x04 0x00 0x75 0x04 0x00 0x76 0x04 0x00 0x77 0x04 0x00 0x78 0x04 0x00 0x79 0x04 0x00 0x7a 0x04 0x00 0x7b 0x04>; + gpio-controller; + #gpio-cells = <0x02>; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "okay"; + + porta { + compatible = "phytium,gpio-port"; + reg = <0x00>; + nr-gpios = <0x10>; + }; + }; + + gpio@28035000 { + compatible = "phytium,gpio"; + reg = <0x00 0x28035000 0x00 0x1000>; + interrupts = <0x00 0x7c 0x04 0x00 0x7d 0x04 0x00 0x7e 0x04 0x00 0x7f 0x04 0x00 0x80 0x04 0x00 0x81 0x04 0x00 0x82 0x04 0x00 0x83 0x04 0x00 0x84 0x04 0x00 0x85 0x04 0x00 0x86 0x04 0x00 0x87 0x04 0x00 0x88 0x04 0x00 0x89 0x04 0x00 0x8a 0x04 0x00 0x8b 0x04>; + gpio-controller; + #gpio-cells = <0x02>; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "okay"; + + porta { + compatible = "phytium,gpio-port"; + reg = <0x00>; + nr-gpios = <0x10>; + }; + }; + + gpio@28036000 { + compatible = "phytium,gpio"; + reg = <0x00 0x28036000 0x00 0x1000>; + interrupts = <0x00 0x8c 0x04 0x00 0x8d 0x04 0x00 0x8e 0x04 0x00 0x8f 0x04 0x00 0x90 0x04 0x00 0x91 0x04 0x00 0x92 0x04 0x00 0x93 0x04 0x00 0x94 0x04 0x00 0x95 0x04 0x00 0x96 0x04 0x00 0x97 0x04 0x00 0x98 0x04 0x00 0x99 0x04 0x00 0x9a 0x04 0x00 0x9b 0x04>; + gpio-controller; + #gpio-cells = <0x02>; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "okay"; + phandle = <0x15>; + + porta { + compatible = "phytium,gpio-port"; + reg = <0x00>; + nr-gpios = <0x10>; + }; + }; + + gpio@28037000 { + compatible = "phytium,gpio"; + reg = <0x00 0x28037000 0x00 0x1000>; + interrupts = <0x00 0x9c 0x04>; + gpio-controller; + #gpio-cells = <0x02>; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "okay"; + + porta { + compatible = "phytium,gpio-port"; + reg = <0x00>; + nr-gpios = <0x10>; + }; + }; + + gpio@28038000 { + compatible = "phytium,gpio"; + reg = <0x00 0x28038000 0x00 0x1000>; + interrupts = <0x00 0x9d 0x04>; + gpio-controller; + #gpio-cells = <0x02>; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "okay"; + + porta { + compatible = "phytium,gpio-port"; + reg = <0x00>; + nr-gpios = <0x10>; + }; + }; + + gpio@28039000 { + compatible = "phytium,gpio"; + reg = <0x00 0x28039000 0x00 0x1000>; + interrupts = <0x00 0x9e 0x04>; + gpio-controller; + #gpio-cells = <0x02>; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "okay"; + + porta { + compatible = "phytium,gpio-port"; + reg = <0x00>; + nr-gpios = <0x10>; + }; + }; + + spi@2803a000 { + compatible = "phytium,spi"; + reg = <0x00 0x2803a000 0x00 0x1000>; + interrupts = <0x00 0x9f 0x04>; + clocks = <0x0d>; + num-cs = <0x04>; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "disabled"; + global-cs = <0x01>; + + w25q128@0 { + compatible = "winbond,w25q128\0jedec,spi-nor"; + spi-tx-bus-width = <0x01>; + spi-rx-bus-width = <0x01>; + spi-max-frequency = <0xb71b00>; + reg = <0x00>; + status = "disabled"; + }; + }; + + spi@2803b000 { + compatible = "phytium,spi"; + reg = <0x00 0x2803b000 0x00 0x1000>; + interrupts = <0x00 0xa0 0x04>; + clocks = <0x0d>; + num-cs = <0x04>; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "disabled"; + }; + + spi@2803c000 { + compatible = "phytium,spi"; + reg = <0x00 0x2803c000 0x00 0x1000>; + interrupts = <0x00 0xa1 0x04>; + clocks = <0x0d>; + num-cs = <0x04>; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "okay"; + global-cs = <0x01>; + + tpm_tis@0 { + compatible = "tcg,tpm_tis-spi"; + spi-tx-bus-width = <0x01>; + spi-rx-bus-width = <0x01>; + spi-max-frequency = <0xf4240>; + reg = <0x00>; + status = "okay"; + }; + + w25q128@0 { + compatible = "rohm,dh2228fv"; + spi-tx-bus-width = <0x01>; + spi-rx-bus-width = <0x01>; + spi-max-frequency = <0xf4240>; + reg = <0x00>; + status = "disabled"; + }; + }; + + spi@2803d000 { + compatible = "phytium,spi"; + reg = <0x00 0x2803d000 0x00 0x1000>; + interrupts = <0x00 0xa2 0x04>; + clocks = <0x0d>; + num-cs = <0x04>; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "disabled"; + }; + + watchdog@28040000 { + compatible = "arm,sbsa-gwdt"; + reg = <0x00 0x28041000 0x00 0x1000 0x00 0x28040000 0x00 0x1000>; + interrupts = <0x00 0xa4 0x04>; + timeout-sec = <0x1e>; + status = "disabled"; + }; + + watchdog@28042000 { + compatible = "arm,sbsa-gwdt"; + reg = <0x00 0x28043000 0x00 0x1000 0x00 0x28042000 0x00 0x1000>; + interrupts = <0x00 0xa5 0x04>; + timeout-sec = <0x1e>; + status = "disabled"; + }; + + pwm@2804a000 { + compatible = "phytium,pwm"; + reg = <0x00 0x2804a000 0x00 0x1000>; + interrupts = <0x00 0xad 0x04>; + clocks = <0x0d>; + status = "disabled"; + }; + + pwm@2804b000 { + compatible = "phytium,pwm"; + reg = <0x00 0x2804b000 0x00 0x1000>; + interrupts = <0x00 0xae 0x04>; + clocks = <0x0d>; + status = "disabled"; + }; + + tacho@28054000 { + compatible = "phytium,tacho"; + reg = <0x00 0x28054000 0x00 0x1000>; + interrupts = <0x00 0xc2 0x04>; + clocks = <0x0d>; + status = "disabled"; + }; + + tacho@28055000 { + compatible = "phytium,tacho"; + reg = <0x00 0x28055000 0x00 0x1000>; + interrupts = <0x00 0xc3 0x04>; + clocks = <0x0d>; + status = "disabled"; + }; + + tacho@28056000 { + compatible = "phytium,tacho"; + reg = <0x00 0x28056000 0x00 0x1000>; + interrupts = <0x00 0xc4 0x04>; + clocks = <0x0d>; + status = "disabled"; + }; + + tacho@28057000 { + compatible = "phytium,tacho"; + reg = <0x00 0x28057000 0x00 0x1000>; + interrupts = <0x00 0xc5 0x04>; + clocks = <0x0d>; + status = "disabled"; + }; + + tacho@28058000 { + compatible = "phytium,tacho"; + reg = <0x00 0x28058000 0x00 0x1000>; + interrupts = <0x00 0xc6 0x04>; + clocks = <0x0d>; + status = "disabled"; + }; + + tacho@28059000 { + compatible = "phytium,tacho"; + reg = <0x00 0x28059000 0x00 0x1000>; + interrupts = <0x00 0xc7 0x04>; + clocks = <0x0d>; + status = "disabled"; + }; + + tacho@2805a000 { + compatible = "phytium,tacho"; + reg = <0x00 0x2805a000 0x00 0x1000>; + interrupts = <0x00 0xc8 0x04>; + clocks = <0x0d>; + status = "disabled"; + }; + + tacho@2805b000 { + compatible = "phytium,tacho"; + reg = <0x00 0x2805b000 0x00 0x1000>; + interrupts = <0x00 0xc9 0x04>; + clocks = <0x0d>; + status = "disabled"; + }; + + tacho@2805c000 { + compatible = "phytium,tacho"; + reg = <0x00 0x2805c000 0x00 0x1000>; + interrupts = <0x00 0xca 0x04>; + clocks = <0x0d>; + status = "disabled"; + }; + + tacho@2805d000 { + compatible = "phytium,tacho"; + reg = <0x00 0x2805d000 0x00 0x1000>; + interrupts = <0x00 0xcb 0x04>; + clocks = <0x0d>; + status = "disabled"; + }; + + tacho@2805e000 { + compatible = "phytium,tacho"; + reg = <0x00 0x2805e000 0x00 0x1000>; + interrupts = <0x00 0xcc 0x04>; + clocks = <0x0d>; + status = "disabled"; + }; + + tacho@2805f000 { + compatible = "phytium,tacho"; + reg = <0x00 0x2805f000 0x00 0x1000>; + interrupts = <0x00 0xcd 0x04>; + clocks = <0x0d>; + status = "disabled"; + }; + + tacho@28060000 { + compatible = "phytium,tacho"; + reg = <0x00 0x28060000 0x00 0x1000>; + interrupts = <0x00 0xce 0x04>; + clocks = <0x0d>; + status = "disabled"; + }; + + tacho@28061000 { + compatible = "phytium,tacho"; + reg = <0x00 0x28061000 0x00 0x1000>; + interrupts = <0x00 0xcf 0x04>; + clocks = <0x0d>; + status = "disabled"; + }; + + tacho@28062000 { + compatible = "phytium,tacho"; + reg = <0x00 0x28062000 0x00 0x1000>; + interrupts = <0x00 0xd0 0x04>; + clocks = <0x0d>; + status = "disabled"; + }; + + tacho@28063000 { + compatible = "phytium,tacho"; + reg = <0x00 0x28063000 0x00 0x1000>; + interrupts = <0x00 0xd1 0x04>; + clocks = <0x0d>; + status = "disabled"; + }; + + tacho@28064000 { + compatible = "phytium,tacho"; + reg = <0x00 0x28064000 0x00 0x1000>; + interrupts = <0x00 0xd2 0x04>; + clocks = <0x0d>; + status = "disabled"; + }; + + tacho@28065000 { + compatible = "phytium,tacho"; + reg = <0x00 0x28065000 0x00 0x1000>; + interrupts = <0x00 0xd3 0x04>; + clocks = <0x0d>; + status = "disabled"; + }; + + tacho@28066000 { + compatible = "phytium,tacho"; + reg = <0x00 0x28066000 0x00 0x1000>; + interrupts = <0x00 0xd4 0x04>; + clocks = <0x0d>; + status = "disabled"; + }; + + tacho@28067000 { + compatible = "phytium,tacho"; + reg = <0x00 0x28067000 0x00 0x1000>; + interrupts = <0x00 0xd5 0x04>; + clocks = <0x0d>; + status = "disabled"; + }; + + tacho@28068000 { + compatible = "phytium,tacho"; + reg = <0x00 0x28068000 0x00 0x1000>; + interrupts = <0x00 0xd6 0x04>; + clocks = <0x0d>; + status = "disabled"; + }; + + tacho@28069000 { + compatible = "phytium,tacho"; + reg = <0x00 0x28069000 0x00 0x1000>; + interrupts = <0x00 0xd7 0x04>; + clocks = <0x0d>; + status = "disabled"; + }; + + tacho@2806a000 { + compatible = "phytium,tacho"; + reg = <0x00 0x2806a000 0x00 0x1000>; + interrupts = <0x00 0xd8 0x04>; + clocks = <0x0d>; + status = "disabled"; + }; + + tacho@2806b000 { + compatible = "phytium,tacho"; + reg = <0x00 0x2806b000 0x00 0x1000>; + interrupts = <0x00 0xd9 0x04>; + clocks = <0x0d>; + status = "disabled"; + }; + + tacho@2806c000 { + compatible = "phytium,tacho"; + reg = <0x00 0x2806c000 0x00 0x1000>; + interrupts = <0x00 0xda 0x04>; + clocks = <0x0d>; + status = "disabled"; + }; + + tacho@2806d000 { + compatible = "phytium,tacho"; + reg = <0x00 0x2806d000 0x00 0x1000>; + interrupts = <0x00 0xdb 0x04>; + clocks = <0x0d>; + status = "disabled"; + }; + + tacho@2806e000 { + compatible = "phytium,tacho"; + reg = <0x00 0x2806e000 0x00 0x1000>; + interrupts = <0x00 0xdc 0x04>; + clocks = <0x0d>; + status = "disabled"; + }; + + tacho@2806f000 { + compatible = "phytium,tacho"; + reg = <0x00 0x2806f000 0x00 0x1000>; + interrupts = <0x00 0xdd 0x04>; + clocks = <0x0d>; + status = "disabled"; + }; + + tacho@28070000 { + compatible = "phytium,tacho"; + reg = <0x00 0x28070000 0x00 0x1000>; + interrupts = <0x00 0xde 0x04>; + clocks = <0x0d>; + status = "disabled"; + }; + + tacho@28071000 { + compatible = "phytium,tacho"; + reg = <0x00 0x28071000 0x00 0x1000>; + interrupts = <0x00 0xdf 0x04>; + clocks = <0x0d>; + status = "disabled"; + }; + + tacho@28072000 { + compatible = "phytium,tacho"; + reg = <0x00 0x28072000 0x00 0x1000>; + interrupts = <0x00 0xe0 0x04>; + clocks = <0x0d>; + status = "disabled"; + }; + + tacho@28073000 { + compatible = "phytium,tacho"; + reg = <0x00 0x28073000 0x00 0x1000>; + interrupts = <0x00 0xe1 0x04>; + clocks = <0x0d>; + status = "disabled"; + }; + + tacho@28074000 { + compatible = "phytium,tacho"; + reg = <0x00 0x28074000 0x00 0x1000>; + interrupts = <0x00 0xe2 0x04>; + clocks = <0x0d>; + status = "disabled"; + }; + + tacho@28075000 { + compatible = "phytium,tacho"; + reg = <0x00 0x28075000 0x00 0x1000>; + interrupts = <0x00 0xe3 0x04>; + clocks = <0x0d>; + status = "disabled"; + }; + + tacho@28076000 { + compatible = "phytium,tacho"; + reg = <0x00 0x28076000 0x00 0x1000>; + interrupts = <0x00 0xe4 0x04>; + clocks = <0x0d>; + status = "disabled"; + }; + + tacho@28077000 { + compatible = "phytium,tacho"; + reg = <0x00 0x28077000 0x00 0x1000>; + interrupts = <0x00 0xe5 0x04>; + clocks = <0x0d>; + status = "disabled"; + }; + + tacho@28078000 { + compatible = "phytium,tacho"; + reg = <0x00 0x28078000 0x00 0x1000>; + interrupts = <0x00 0xe6 0x04>; + clocks = <0x0d>; + status = "disabled"; + }; + + tacho@28079000 { + compatible = "phytium,tacho"; + reg = <0x00 0x28079000 0x00 0x1000>; + interrupts = <0x00 0xe7 0x04>; + clocks = <0x0d>; + status = "disabled"; + }; + + usb2@31800000 { + compatible = "phytium,e2000-usb2\0cdns,usb2"; + reg = <0x00 0x31800000 0x00 0x80000 0x00 0x31990000 0x00 0x10000>; + interrupts = <0x00 0x20 0x04>; + status = "okay"; + dr_mode = "host"; + }; + + usb2@31880000 { + compatible = "phytium,e2000-usb2\0cdns,usb2"; + reg = <0x00 0x31880000 0x00 0x80000 0x00 0x319a0000 0x00 0x10000>; + interrupts = <0x00 0x21 0x04>; + status = "okay"; + dr_mode = "host"; + }; + + usb2@31900000 { + compatible = "phytium,e2000-usb2\0cdns,usb2"; + reg = <0x00 0x31900000 0x00 0x80000 0x00 0x319b0000 0x00 0x10000>; + interrupts = <0x00 0x22 0x04>; + status = "okay"; + dr_mode = "host"; + }; + + usb2@32800000 { + compatible = "phytium,e2000-usb2\0cdns,usb2"; + reg = <0x00 0x32800000 0x00 0x40000 0x00 0x32880000 0x00 0x40000>; + interrupts = <0x00 0x0e 0x04>; + status = "okay"; + dr_mode = "host"; + }; + + usb2@32840000 { + compatible = "phytium,e2000-usb2\0cdns,usb2"; + reg = <0x00 0x32840000 0x00 0x40000 0x00 0x328c0000 0x00 0x40000>; + interrupts = <0x00 0x0f 0x04>; + status = "okay"; + dr_mode = "host"; + }; + + dc@32000000 { + compatible = "phytium,dc"; + reg = <0x00 0x32000000 0x00 0x8000>; + interrupts = <0x00 0x2c 0x04>; + status = "okay"; + pipe_mask = [03]; + edp_mask = [00]; + }; + + i2s_dp0@32009000 { + compatible = "phytium,i2s"; + reg = <0x00 0x32009000 0x00 0x1000 0x00 0x32008000 0x00 0x1000>; + interrupts = <0x00 0x2f 0x04>; + clocks = <0x0f>; + clock-names = "i2s_clk"; + status = "disabled"; + dai-name = "phytium-i2s-dp0"; + }; + + i2s_dp1@3200B000 { + compatible = "phytium,i2s"; + reg = <0x00 0x3200b000 0x00 0x1000 0x00 0x3200a000 0x00 0x1000>; + interrupts = <0x00 0x30 0x04>; + clocks = <0x0f>; + clock-names = "i2s_clk"; + status = "okay"; + dai-name = "phytium-i2s-dp1"; + }; + + pmdk_dp { + compatible = "phytium,pmdk-dp"; + status = "okay"; + num-dp = <0x02>; + }; + + sram@32a10000 { + compatible = "phytium,e2000-sram-ns\0mmio-sram"; + reg = <0x00 0x32a10000 0x00 0x2000>; + #address-cells = <0x01>; + #size-cells = <0x01>; + ranges = <0x00 0x00 0x32a10000 0x2000>; + + scp-shmem@0 { + compatible = "arm,scmi-shmem"; + reg = <0x1000 0x400>; + phandle = <0x04>; + }; + + scp-shmem@1 { + compatible = "arm,scmi-shmem"; + reg = <0x1400 0x400>; + phandle = <0x03>; + }; + }; + + spinlock@32b36000 { + compatible = "phytium,hwspinlock"; + reg = <0x00 0x32b36000 0x00 0x1000>; + #hwlock-cells = <0x01>; + nr-locks = <0x20>; + status = "disabled"; + }; + + pcie@40000000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + #address-cells = <0x03>; + #size-cells = <0x02>; + #interrupt-cells = <0x01>; + reg = <0x00 0x40000000 0x00 0x10000000>; + msi-parent = <0x10>; + bus-range = <0x00 0xff>; + interrupt-map-mask = <0x00 0x00 0x00 0x07>; + interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x00 0x04 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x00 0x00 0x05 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x00 0x00 0x06 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x00 0x00 0x07 0x04>; + ranges = <0x1000000 0x00 0x00 0x00 0x50000000 0x00 0xf00000 0x2000000 0x00 0x58000000 0x00 0x58000000 0x00 0x28000000 0x3000000 0x10 0x00 0x10 0x00 0x10 0x00>; + //iommu-map = <0x00 0x11 0x00 0x10000>; + status = "okay"; + }; + + hda@28006000 { + compatible = "phytium,hda\0phytium,ft-hda"; + reg = <0x00 0x28006000 0x00 0x1000>; + interrupts = <0x00 0x4e 0x04>; + status = "okay"; + }; + + i2s@28009000 { + compatible = "phytium,i2s"; + reg = <0x00 0x28009000 0x00 0x1000 0x00 0x28005000 0x00 0x1000>; + interrupts = <0x00 0x4d 0x04>; + clocks = <0x0f>; + clock-names = "i2s_clk"; + status = "disabled"; + #sound-dai-cells = <0x00>; + dai-name = "phytium-i2s-lsd"; + }; + + can@2800a000 { + compatible = "phytium,canfd"; + reg = <0x00 0x2800a000 0x00 0x1000>; + interrupts = <0x00 0x51 0x04>; + clocks = <0x12>; + clock-names = "can_clk"; + tx-fifo-depth = <0x40>; + rx-fifo-depth = <0x40>; + status = "okay"; + }; + + can@2800b000 { + compatible = "phytium,canfd"; + reg = <0x00 0x2800b000 0x00 0x1000>; + interrupts = <0x00 0x52 0x04>; + clocks = <0x12>; + clock-names = "can_clk"; + tx-fifo-depth = <0x40>; + rx-fifo-depth = <0x40>; + status = "okay"; + }; + + keypad@2807a000 { + compatible = "phytium,keypad"; + reg = <0x00 0x2807a000 0x00 0x1000>; + interrupts = <0x00 0xbd 0x04>; + clocks = <0x0d>; + status = "disabled"; + }; + + usb3@31a08000 { + compatible = "phytium,e2000-xhci\0generic-xhci"; + reg = <0x00 0x31a08000 0x00 0x18000>; + interrupts = <0x00 0x10 0x04>; + status = "okay"; + }; + + usb3@31a28000 { + compatible = "phytium,e2000-xhci\0generic-xhci"; + reg = <0x00 0x31a28000 0x00 0x18000>; + interrupts = <0x00 0x11 0x04>; + status = "okay"; + }; + + sata@31a40000 { + compatible = "generic-ahci"; + reg = <0x00 0x31a40000 0x00 0x1000>; + interrupts = <0x00 0x2a 0x04>; + status = "okay"; + }; + + sata@32014000 { + compatible = "generic-ahci"; + reg = <0x00 0x32014000 0x00 0x1000>; + interrupts = <0x00 0x2b 0x04>; + status = "okay"; + }; +/* + ethernet@3200c000 { + compatible = "phytium,gem\0cdns,phytium-gem"; + reg = <0x00 0x3200c000 0x00 0x2000>; + interrupts = <0x00 0x37 0x04 0x00 0x38 0x04 0x00 0x39 0x04 0x00 0x3a 0x04 0x00 0x1c 0x04 0x00 0x1d 0x04 0x00 0x1e 0x04 0x00 0x1f 0x04>; + clock-names = "pclk\0hclk\0tx_clk\0tsu_clk"; + clocks = <0x13 0x14 0x14 0x13>; + magic-packet; + support-tsn; + status = "okay"; + phy-mode = "sgmii"; + use-mii; + }; +*/ + ethernet@3200e000 { + compatible = "phytium,gem\0cdns,phytium-gem"; + reg = <0x00 0x3200e000 0x00 0x2000>; + interrupts = <0x00 0x3b 0x04 0x00 0x3c 0x04 0x00 0x3d 0x04 0x00 0x3e 0x04>; + clock-names = "pclk\0hclk\0tx_clk\0tsu_clk"; + clocks = <0x13 0x14 0x14 0x13>; + magic-packet; + status = "disabled"; + }; + + ethernet@32010000 { + compatible = "phytium,gem\0cdns,phytium-gem"; + reg = <0x00 0x32010000 0x00 0x2000>; + interrupts = <0x00 0x40 0x04 0x00 0x41 0x04 0x00 0x42 0x04 0x00 0x43 0x04>; + clock-names = "pclk\0hclk\0tx_clk\0tsu_clk"; + clocks = <0x13 0x14 0x14 0x13>; + magic-packet; + status = "disabled"; + phy-mode = "rgmii"; + use-mii; + force-phy-mode; + }; + + ethernet@32012000 { + compatible = "phytium,gem\0cdns,phytium-gem"; + reg = <0x00 0x32012000 0x00 0x2000>; + interrupts = <0x00 0x44 0x04 0x00 0x45 0x04 0x00 0x46 0x04 0x00 0x47 0x04>; + clock-names = "pclk\0hclk\0tx_clk\0tsu_clk"; + clocks = <0x13 0x14 0x14 0x13>; + magic-packet; + status = "disabled"; + phy-mode = "rgmii"; + use-mii; + }; + + vpu@32b00000 { + compatible = "phytium,vpu"; + reg = <0x00 0x32b00000 0x00 0x20000>; + interrupts = <0x00 0x0c 0x04>; + status = "okay"; + }; + + i2c@28026000 { + compatible = "phytium,i2c"; + reg = <0x00 0x28026000 0x00 0x1000>; + interrupts = <0x00 0x65 0x04>; + clocks = <0x0d>; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "okay"; + + rtc@32 { + compatible = "whwave,sd3078"; + reg = <0x32>; + }; + }; + + i2c@2801a000 { + status = "okay"; + compatible = "phytium,i2c"; + reg = <0x00 0x2801a000 0x00 0x1000>; + interrupts = <0x00 0x5f 0x04>; + clocks = <0x0d>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <0x01>; + }; + }; + + uart@28018000 { + compatible = "arm,pl011\0arm,primecell"; + reg = <0x00 0x28018000 0x00 0x1000>; + interrupts = <0x00 0x5e 0x04>; + clocks = <0x0d 0x0d>; + clock-names = "uartclk\0apb_pclk"; + status = "okay"; + }; + + uart@28020000 { + compatible = "arm,pl011\0arm,primecell"; + reg = <0x00 0x28020000 0x00 0x1000>; + interrupts = <0x00 0x62 0x04>; + clocks = <0x0d 0x0d>; + clock-names = "uartclk\0apb_pclk"; + status = "okay"; + }; + + uart@28024000 { + compatible = "arm,pl011\0arm,primecell"; + reg = <0x00 0x28024000 0x00 0x1000>; + interrupts = <0x00 0x64 0x04>; + clocks = <0x0d 0x0d>; + clock-names = "uartclk\0apb_pclk"; + status = "okay"; + }; + + uart@28028000 { + compatible = "arm,pl011\0arm,primecell"; + reg = <0x00 0x28028000 0x00 0x1000>; + interrupts = <0x00 0x66 0x04>; + clocks = <0x0d 0x0d>; + clock-names = "uartclk\0apb_pclk"; + status = "okay"; + }; + + uart@28030000 { + compatible = "arm,pl011\0arm,primecell"; + reg = <0x00 0x28030000 0x00 0x1000>; + interrupts = <0x00 0x6a 0x04>; + clocks = <0x0d 0x0d>; + clock-names = "uartclk\0apb_pclk"; + status = "okay"; + }; + + uart@28032000 { + compatible = "arm,pl011\0arm,primecell"; + reg = <0x00 0x28032000 0x00 0x1000>; + interrupts = <0x00 0x6b 0x04>; + clocks = <0x0d 0x0d>; + clock-names = "uartclk\0apb_pclk"; + status = "okay"; + }; + + qspi@28008000 { + compatible = "phytium,qspi"; + reg = <0x00 0x28008000 0x00 0x1000 0x00 0x00 0x00 0xfffffff>; + reg-names = "qspi\0qspi_mm"; + clocks = <0x0d>; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "okay"; + + flash@0 { + reg = <0x00>; + spi-rx-bus-width = <0x04>; + spi-max-frequency = <0x3d0900>; + status = "okay"; + }; + }; + }; + + reserved-memory { + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + + reserved@0 { + no-map; + reg = <0x00 0xb0100000 0x00 0x19900000>; + phandle = <0x16>; + }; + reserved@a0000000 { + reg = <0x0 0xa0000000 0x0 0x10000000>; + no-map; + }; + }; + + remoteproc@0 { + compatible = "phytium,rproc"; + memory-region = <0x16>; + status = "disabled"; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + memory@00 { + device_type = "memory"; + reg = <0x00 0x80000000 0x02 0x00>; + }; +}; diff --git a/configs/arm64/e2000q-inmate-eth-smallcpu.c b/configs/arm64/e2000q-inmate-eth-smallcpu.c new file mode 100644 index 00000000..9f42f28e --- /dev/null +++ b/configs/arm64/e2000q-inmate-eth-smallcpu.c @@ -0,0 +1,157 @@ +/** + * jailhouse, a Linux-based partitioning hypervisor + * + * Copyright (C), 2022, Kylinsoft Corporation. + * + * @author huanglei1@kylinos.cn + * @date 2023.03.28 + * @brief + * @note + */ + +#include <jailhouse/types.h> +#include <jailhouse/cell-config.h> + +struct { + struct jailhouse_cell_desc cell; + __u64 cpus[1]; + struct jailhouse_memory mem_regions[10]; + struct jailhouse_irqchip irqchips[2]; + struct jailhouse_pci_device pci_devices[1]; +} __attribute__((packed)) config = { + .cell = { + .signature = JAILHOUSE_CELL_DESC_SIGNATURE, + .revision = JAILHOUSE_CONFIG_REVISION, + .name = "e2000q-guest-eth-smallcpu", + .flags = JAILHOUSE_CELL_PASSIVE_COMMREG, + + .cpu_set_size = sizeof(config.cpus), + .num_memory_regions = ARRAY_SIZE(config.mem_regions), + .num_irqchips = ARRAY_SIZE(config.irqchips), + .num_pci_devices = ARRAY_SIZE(config.pci_devices), + .vpci_irq_base = 102, + + .console = { + .address = 0x2800d000, + .type = JAILHOUSE_CON_TYPE_PL011, + .flags = JAILHOUSE_CON_ACCESS_MMIO | + JAILHOUSE_CON_REGDIST_4, + }, + }, + + .cpus = { + 0x3, + }, + + .mem_regions = { + /* IVSHMEM shared memory regions */ + { + .phys_start = 0xa7000000, + .virt_start = 0xa7000000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0xa7001000, + .virt_start = 0xa7001000, + .size = 0x9000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0xa700a000, + .virt_start = 0xa700a000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0xa700c000, + .virt_start = 0xa700c000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0xa700e000, + .virt_start = 0xa700e000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED, + }, + /* ETH 0 */ + { + .phys_start = 0x3200c000, + .virt_start = 0x3200c000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED, + }, + /* UART */{ + .phys_start = 0x2800d000, + .virt_start = 0x2800d000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED, + }, + + /* RAM */ { + .phys_start = 0xa2000000, + .virt_start = 0, + .size = 0x5000000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE, + }, + { + .phys_start = 0xa3000000, + .virt_start = 0xa3000000, + .size = 0xc000000, + .flags= JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE | + JAILHOUSE_MEM_DMA, + + + }, + /* communication region */ { + .virt_start = 0x80000000, + .size = 0x00001000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_COMM_REGION, + }, + }, + + .irqchips = { + /* GIC */ { + .address = 0x30800000, + .pin_base = 32, + .pin_bitmap = { + 1 << (60-32)|1 << (61-32)|1 << (62-32)|1 << (63-32), + 1 << (87-64)|1 << (88-64)|1 << (89-64)|1 << (90-64), + 1 << (116-96), + 1 << (102 + 32 - 128), + }, + }, + { + .address = 0x30800000, + .pin_base = 256, + .pin_bitmap = { + 0, + 1 << (268+32-288), + 0, + 0, + }, + }, + }, + + + .pci_devices = { + { + .type = JAILHOUSE_PCI_TYPE_IVSHMEM, + .domain = 1, + .bdf = 0 << 3, + .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_INTX, + .shmem_regions_start = 0, + .shmem_dev_id = 1, + .shmem_peers = 3, + .shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED, + }, + }, + + +}; diff --git a/configs/arm64/e2000q-inmate-eth.c b/configs/arm64/e2000q-inmate-eth.c new file mode 100644 index 00000000..e54b52ff --- /dev/null +++ b/configs/arm64/e2000q-inmate-eth.c @@ -0,0 +1,157 @@ +/** + * jailhouse, a Linux-based partitioning hypervisor + * + * Copyright (C), 2022, Kylinsoft Corporation. + * + * @author huanglei1@kylinos.cn + * @date 2023.03.28 + * @brief + * @note + */ + +#include <jailhouse/types.h> +#include <jailhouse/cell-config.h> + +struct { + struct jailhouse_cell_desc cell; + __u64 cpus[1]; + struct jailhouse_memory mem_regions[10]; + struct jailhouse_irqchip irqchips[2]; + struct jailhouse_pci_device pci_devices[1]; +} __attribute__((packed)) config = { + .cell = { + .signature = JAILHOUSE_CELL_DESC_SIGNATURE, + .revision = JAILHOUSE_CONFIG_REVISION, + .name = "e2000q-guest-eth", + .flags = JAILHOUSE_CELL_PASSIVE_COMMREG, + + .cpu_set_size = sizeof(config.cpus), + .num_memory_regions = ARRAY_SIZE(config.mem_regions), + .num_irqchips = ARRAY_SIZE(config.irqchips), + .num_pci_devices = ARRAY_SIZE(config.pci_devices), + .vpci_irq_base = 102, + + .console = { + .address = 0x2800d000, + .type = JAILHOUSE_CON_TYPE_PL011, + .flags = JAILHOUSE_CON_ACCESS_MMIO | + JAILHOUSE_CON_REGDIST_4, + }, + }, + + .cpus = { + 0xc, + }, + + .mem_regions = { + /* IVSHMEM shared memory regions */ + { + .phys_start = 0xa7000000, + .virt_start = 0xa7000000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0xa7001000, + .virt_start = 0xa7001000, + .size = 0x9000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0xa700a000, + .virt_start = 0xa700a000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0xa700c000, + .virt_start = 0xa700c000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0xa700e000, + .virt_start = 0xa700e000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED, + }, + /* ETH 0 */ + { + .phys_start = 0x3200c000, + .virt_start = 0x3200c000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED, + }, + /* UART */{ + .phys_start = 0x2800d000, + .virt_start = 0x2800d000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED, + }, + + /* RAM */ { + .phys_start = 0xa2000000, + .virt_start = 0, + .size = 0x5000000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE, + }, + { + .phys_start = 0xa3000000, + .virt_start = 0xa3000000, + .size = 0xc000000, + .flags= JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE | + JAILHOUSE_MEM_DMA, + + + }, + /* communication region */ { + .virt_start = 0x80000000, + .size = 0x00001000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_COMM_REGION, + }, + }, + + .irqchips = { + /* GIC */ { + .address = 0x30800000, + .pin_base = 32, + .pin_bitmap = { + 1 << (60-32)|1 << (61-32)|1 << (62-32)|1 << (63-32), + 1 << (87-64)|1 << (88-64)|1 << (89-64)|1 << (90-64), + 1 << (116-96), + 1 << (102 + 32 - 128), + }, + }, + { + .address = 0x30800000, + .pin_base = 256, + .pin_bitmap = { + 0, + 1 << (268+32-288), + 0, + 0, + }, + }, + }, + + + .pci_devices = { + { + .type = JAILHOUSE_PCI_TYPE_IVSHMEM, + .domain = 1, + .bdf = 0 << 3, + .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_INTX, + .shmem_regions_start = 0, + .shmem_dev_id = 1, + .shmem_peers = 3, + .shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED, + }, + }, + + +}; diff --git a/configs/arm64/e2000q-main-eth.c b/configs/arm64/e2000q-main-eth.c new file mode 100644 index 00000000..a8deb633 --- /dev/null +++ b/configs/arm64/e2000q-main-eth.c @@ -0,0 +1,333 @@ +/** + * jailhouse, a Linux-based partitioning hypervisor + * + * Copyright (C), 2022, Kylinsoft Corporation. + * + * @author huanglei1@kylinos.cn + * @date 2023.03.28 + * @brief + * @note + */ + +#include <jailhouse/types.h> +#include <jailhouse/cell-config.h> + +struct { + struct jailhouse_system header; + __u64 cpus[1]; + struct jailhouse_memory mem_regions[30]; + struct jailhouse_irqchip irqchips[2]; + struct jailhouse_pci_device pci_devices[1]; +} __attribute__((packed)) config = { + .header = { + .signature = JAILHOUSE_SYSTEM_SIGNATURE, + .revision = JAILHOUSE_CONFIG_REVISION, + .flags = JAILHOUSE_SYS_VIRTUAL_DEBUG_CONSOLE, + .hypervisor_memory = { + .phys_start = 0xa0000000, + .size = 0x01000000, + }, + .debug_console = { + .address = 0x2800d000, + .size = 0x1000, + .type = JAILHOUSE_CON_TYPE_PL011, + .flags = JAILHOUSE_CON_ACCESS_MMIO | + JAILHOUSE_CON_REGDIST_4, + }, + .platform_info = { + .pci_mmconfig_base = 0x40000000, + .pci_mmconfig_end_bus = 5, + .pci_is_virtual = 0, + .pci_domain = 1, + + .arm = { + .gic_version = 3, + .gicd_base = 0x30800000, + .gicr_base = 0x30880000, + .gicc_base = 0x30840000, + .gich_base = 0x30850000, + .gicv_base = 0x30860000, + .maintenance_irq = 25, + }, + }, + .root_cell = { + .name = "e2000q-main-eth", + + .cpu_set_size = sizeof(config.cpus), + .num_memory_regions = ARRAY_SIZE(config.mem_regions), + .num_irqchips = ARRAY_SIZE(config.irqchips), + .num_pci_devices = ARRAY_SIZE(config.pci_devices), + .vpci_irq_base = 100, + }, + }, + + .cpus = { + 0xf, + }, + + .mem_regions = { + /* IVSHMEM shared memory regions */ + { + .phys_start = 0xa7000000, + .virt_start = 0xa7000000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ, + }, + { + .phys_start = 0xa7001000, + .virt_start = 0xa7001000, + .size = 0x9000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE, + }, + { + .phys_start = 0xa700a000, + .virt_start = 0xa700a000, + .size = 0x200000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE, + },//section0 + { + .phys_start = 0xa720a000, + .virt_start = 0xa720a000, + .size = 0x200000, + .flags = JAILHOUSE_MEM_READ, + },//section1 + { + .phys_start = 0xa740a000, + .virt_start = 0xa740a000, + .size = 0x200000, + .flags = JAILHOUSE_MEM_READ, + },//seciton2 + + /* Main memory */ + { + .phys_start = 0x80000000, + .virt_start = 0x80000000, + .size = 0x80000000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_EXECUTE, + }, + /* Main memory*/ + { + .phys_start = 0x2000000000, + .virt_start = 0x2000000000, + .size = 0x80000000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_EXECUTE, + }, + /* UART 0-3 */ + { + .phys_start = 0x2800c000, + .virt_start = 0x2800c000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + { + .phys_start = 0x2800d000, + .virt_start = 0x2800d000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + { + .phys_start = 0x2800e000, + .virt_start = 0x2800e000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* GPIO 0-5 */ + { + .phys_start = 0x28034000, + .virt_start = 0x28034000, + .size = 0x6000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* I2C 0-3 */ + /* Watchdog 0 */ + { + .phys_start = 0x28040000, + .virt_start = 0x28040000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* Watchdog 1 */ + { + .phys_start = 0x28042000, + .virt_start = 0x28042000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /*Usb2 0-4*/ + { + .phys_start = 0x31808000, + .virt_start = 0x31808000, + .size = 0x280000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /*Usb3 0-1*/ + { + .phys_start = 0x31a08000, + .virt_start = 0x31a08000, + .size = 0x30000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /*sata 0*/ + { + .phys_start = 0x31a40000, + .virt_start = 0x31a40000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /*sata 1*/ + { + .phys_start = 0x32014000, + .virt_start = 0x32014000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /*vpu*/ + { + .phys_start = 0x32b00000, + .virt_start = 0x32b00000, + .size = 0x20000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* SPI 0-3 */ + { + .phys_start = 0x2803a000, + .virt_start = 0x2803a000, + .size = 0x4000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* QSPI */ + { + .phys_start = 0x28008000, + .virt_start = 0x28008000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* HDA */ + { + .phys_start = 0x28006000, + .virt_start = 0x28006000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* CAN 0-2 and SDCI*/ + { + .phys_start = 0x2800a000, + .virt_start = 0x2800a000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* ETH 0-3 */ + { + .phys_start = 0x3200c000, + .virt_start = 0x3200c000, + .size = 0x8000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + { + .phys_start = 0x32000000, + .virt_start = 0x32000000, + .size = 0x8000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* Mailbox */ + /* SRAM */ + { + .phys_start = 0x32a10000, + .virt_start = 0x32a10000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* GIC ITS */ + { + .phys_start = 0x30820000, + .virt_start = 0x30820000, + .size = 0x20000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* PCIe ECAM */ + { + .phys_start = 0x40000000, + .virt_start = 0x40000000, + .size = 0x10000000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* PCIe IO */ + { + .phys_start = 0x50000000, + .virt_start = 0x50000000, + .size = 0x8000000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* PCIe Mem32 */ + { + .phys_start = 0x58000000, + .virt_start = 0x58000000, + .size = 0x28000000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* PCIe Mem64 */ + { + .phys_start = 0x1000000000, + .virt_start = 0x1000000000, + .size = 0x1000000000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + }, + + .irqchips = { + /* GIC */ + { + .address = 0x30800000, + .pin_base = 32, + .pin_bitmap = { + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + }, + }, + { + .address = 0x30800000, + .pin_base = 256, + .pin_bitmap = { + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + }, + }, + }, + + .pci_devices = { + { + .type = JAILHOUSE_PCI_TYPE_IVSHMEM, + .domain = 1, + .bdf = 0 << 3, + .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_INTX, + .shmem_regions_start = 0, + .shmem_dev_id = 0, + .shmem_peers = 3, + .shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED, + }, + }, + +}; -- 2.25.1
Locations
Projects
Search
Status Monitor
Help
Open Build Service
OBS Manuals
API Documentation
OBS Portal
Reporting a Bug
Contact
Mailing List
Forums
Chat (IRC)
Twitter
Open Build Service (OBS)
is an
openSUSE project
.
浙ICP备2022010568号-2