File _service:tar_scm:0013-x86-drop-dq-b-d-_mode.patch of Package binutils

File _service:tar_scm:0013-x86-drop-dq-b-d-_mode.patch of Package binutils (Revision 733119c7e98b78b876d84ee5ce10a202)

Currently displaying revision 733119c7e98b78b876d84ee5ce10a202 , Show latest

From 5fbe0f28ae6dec9736e504cf79cdb76a9fa09dc9 Mon Sep 17 00:00:00 2001
From: Jan Beulich <jbeulich@suse.com>
Date: Thu, 22 Jul 2021 13:09:21 +0200
Subject: [PATCH] x86: drop dq{b,d}_mode

Their sole use is for {,V}EXTRACTPS / {,V}P{EXT,INS}RB respectively; for
consistency also limit use of dqw_mode to Jdqw. 64-bit disassembly
reflecting REX.W / VEX.W is not in line with the assembler's opcode
table having NoRex64 / VexWIG in all respective templates, i.e. assembly
input isn't being honored there either. Obviously the 0FC5 encodings of
{,V}PEXTRW then also need adjustment for consistency reasons.

diff --git a/gas/testsuite/gas/i386/x86-64-avx-wig.d b/gas/testsuite/gas/i386/x86-64-avx-wig.d
index 14edfb3de7d..2144746bdf0 100644
--- a/gas/testsuite/gas/i386/x86-64-avx-wig.d
+++ b/gas/testsuite/gas/i386/x86-64-avx-wig.d
@@ -58,7 +58,7 @@ Disassembly of section .text:
  +[a-f0-9]+:	c4 e1 ca 5e d4       	vdivss %xmm4,%xmm6,%xmm2
  +[a-f0-9]+:	c4 e3 c9 41 d4 07    	vdppd  \$0x7,%xmm4,%xmm6,%xmm2
  +[a-f0-9]+:	c4 e3 cd 40 d4 07    	vdpps  \$0x7,%ymm4,%ymm6,%ymm2
- +[a-f0-9]+:	c4 e3 f9 17 e1 07    	vextractps \$0x7,%xmm4,%rcx
+ +[a-f0-9]+:	c4 e3 f9 17 e1 07    	vextractps \$0x7,%xmm4,%ecx
  +[a-f0-9]+:	c4 e1 cd 7c d4       	vhaddpd %ymm4,%ymm6,%ymm2
  +[a-f0-9]+:	c4 e1 cf 7c d4       	vhaddps %ymm4,%ymm6,%ymm2
  +[a-f0-9]+:	c4 e1 cd 7d d4       	vhsubpd %ymm4,%ymm6,%ymm2
@@ -157,10 +157,10 @@ Disassembly of section .text:
  +[a-f0-9]+:	c4 e1 c9 65 d4       	vpcmpgtw %xmm4,%xmm6,%xmm2
  +[a-f0-9]+:	c4 e3 f9 63 f4 07    	vpcmpistri \$0x7,%xmm4,%xmm6
  +[a-f0-9]+:	c4 e3 f9 62 f4 07    	vpcmpistrm \$0x7,%xmm4,%xmm6
- +[a-f0-9]+:	c4 e3 f9 14 c0 00    	vpextrb \$0x0,%xmm0,%rax
+ +[a-f0-9]+:	c4 e3 f9 14 c0 00    	vpextrb \$0x0,%xmm0,%eax
  +[a-f0-9]+:	c4 e3 f9 14 00 00    	vpextrb \$0x0,%xmm0,$%rax$
- +[a-f0-9]+:	c4 e1 f9 c5 c0 00    	vpextrw \$0x0,%xmm0,%rax
- +[a-f0-9]+:	c4 e3 f9 15 c0 00    	vpextrw \$0x0,%xmm0,%rax
+ +[a-f0-9]+:	c4 e1 f9 c5 c0 00    	vpextrw \$0x0,%xmm0,%eax
+ +[a-f0-9]+:	c4 e3 f9 15 c0 00    	vpextrw \$0x0,%xmm0,%eax
  +[a-f0-9]+:	c4 e3 f9 15 00 00    	vpextrw \$0x0,%xmm0,$%rax$
  +[a-f0-9]+:	c4 e2 c9 02 d4       	vphaddd %xmm4,%xmm6,%xmm2
  +[a-f0-9]+:	c4 e2 c9 03 d4       	vphaddsw %xmm4,%xmm6,%xmm2
@@ -169,9 +169,9 @@ Disassembly of section .text:
  +[a-f0-9]+:	c4 e2 c9 06 d4       	vphsubd %xmm4,%xmm6,%xmm2
  +[a-f0-9]+:	c4 e2 c9 07 d4       	vphsubsw %xmm4,%xmm6,%xmm2
  +[a-f0-9]+:	c4 e2 c9 05 d4       	vphsubw %xmm4,%xmm6,%xmm2
- +[a-f0-9]+:	c4 e3 f9 20 c0 00    	vpinsrb \$0x0,%rax,%xmm0,%xmm0
+ +[a-f0-9]+:	c4 e3 f9 20 c0 00    	vpinsrb \$0x0,%eax,%xmm0,%xmm0
  +[a-f0-9]+:	c4 e3 f9 20 00 00    	vpinsrb \$0x0,$%rax$,%xmm0,%xmm0
- +[a-f0-9]+:	c4 e1 f9 c4 c0 00    	vpinsrw \$0x0,%rax,%xmm0,%xmm0
+ +[a-f0-9]+:	c4 e1 f9 c4 c0 00    	vpinsrw \$0x0,%eax,%xmm0,%xmm0
  +[a-f0-9]+:	c4 e1 f9 c4 00 00    	vpinsrw \$0x0,$%rax$,%xmm0,%xmm0
  +[a-f0-9]+:	c4 e2 c9 04 d4       	vpmaddubsw %xmm4,%xmm6,%xmm2
  +[a-f0-9]+:	c4 e1 c9 f5 d4       	vpmaddwd %xmm4,%xmm6,%xmm2
diff --git a/gas/testsuite/gas/i386/x86-64-avx512bw-wig1-intel.d b/gas/testsuite/gas/i386/x86-64-avx512bw-wig1-intel.d
index 79b0fdc6a1f..3a1141866aa 100644
--- a/gas/testsuite/gas/i386/x86-64-avx512bw-wig1-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-avx512bw-wig1-intel.d
@@ -159,9 +159,9 @@ Disassembly of section \.text:
 [ 	]*[a-f0-9]+:[ 	]*62 f1 8d 40 65 aa 00 20 00 00[ 	]*vpcmpgtw k5,zmm30,ZMMWORD PTR \[rdx\+0x2000\]
 [ 	]*[a-f0-9]+:[ 	]*62 f1 8d 40 65 6a 80[ 	]*vpcmpgtw k5,zmm30,ZMMWORD PTR \[rdx-0x2000\]
 [ 	]*[a-f0-9]+:[ 	]*62 f1 8d 40 65 aa c0 df ff ff[ 	]*vpcmpgtw k5,zmm30,ZMMWORD PTR \[rdx-0x2040\]
-[ 	]*[a-f0-9]+:[ 	]*62 63 fd 08 14 e8 ab[ 	]*vpextrb rax,xmm29,0xab
-[ 	]*[a-f0-9]+:[ 	]*62 63 fd 08 14 e8 7b[ 	]*vpextrb rax,xmm29,0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 43 fd 08 14 e8 7b[ 	]*vpextrb r8,xmm29,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 63 fd 08 14 e8 ab[ 	]*vpextrb eax,xmm29,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 63 fd 08 14 e8 7b[ 	]*vpextrb eax,xmm29,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 43 fd 08 14 e8 7b[ 	]*vpextrb r8d,xmm29,0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 63 fd 08 14 29 7b[ 	]*vpextrb BYTE PTR \[rcx\],xmm29,0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 23 fd 08 14 ac f0 23 01 00 00 7b[ 	]*vpextrb BYTE PTR \[rax\+r14\*8\+0x123\],xmm29,0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 63 fd 08 14 6a 7f 7b[ 	]*vpextrb BYTE PTR \[rdx\+0x7f\],xmm29,0x7b
@@ -174,23 +174,23 @@ Disassembly of section \.text:
 [ 	]*[a-f0-9]+:[ 	]*62 63 fd 08 15 aa 00 01 00 00 7b[ 	]*vpextrw WORD PTR \[rdx\+0x100\],xmm29,0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 63 fd 08 15 6a 80 7b[ 	]*vpextrw WORD PTR \[rdx-0x100\],xmm29,0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 63 fd 08 15 aa fe fe ff ff 7b[ 	]*vpextrw WORD PTR \[rdx-0x102\],xmm29,0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 91 fd 08 c5 c6 ab[ 	]*vpextrw rax,xmm30,0xab
-[ 	]*[a-f0-9]+:[ 	]*62 91 fd 08 c5 c6 7b[ 	]*vpextrw rax,xmm30,0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 11 fd 08 c5 c6 7b[ 	]*vpextrw r8,xmm30,0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f0 ab[ 	]*vpinsrb xmm30,xmm29,rax,0xab
-[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f0 7b[ 	]*vpinsrb xmm30,xmm29,rax,0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f5 7b[ 	]*vpinsrb xmm30,xmm29,rbp,0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 43 95 00 20 f5 7b[ 	]*vpinsrb xmm30,xmm29,r13,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 91 fd 08 c5 c6 ab[ 	]*vpextrw eax,xmm30,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 91 fd 08 c5 c6 7b[ 	]*vpextrw eax,xmm30,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 11 fd 08 c5 c6 7b[ 	]*vpextrw r8d,xmm30,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f0 ab[ 	]*vpinsrb xmm30,xmm29,eax,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f0 7b[ 	]*vpinsrb xmm30,xmm29,eax,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f5 7b[ 	]*vpinsrb xmm30,xmm29,ebp,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 43 95 00 20 f5 7b[ 	]*vpinsrb xmm30,xmm29,r13d,0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 31 7b[ 	]*vpinsrb xmm30,xmm29,BYTE PTR \[rcx\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 23 95 00 20 b4 f0 23 01 00 00 7b[ 	]*vpinsrb xmm30,xmm29,BYTE PTR \[rax\+r14\*8\+0x123\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 72 7f 7b[ 	]*vpinsrb xmm30,xmm29,BYTE PTR \[rdx\+0x7f\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 b2 80 00 00 00 7b[ 	]*vpinsrb xmm30,xmm29,BYTE PTR \[rdx\+0x80\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 72 80 7b[ 	]*vpinsrb xmm30,xmm29,BYTE PTR \[rdx-0x80\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 b2 7f ff ff ff 7b[ 	]*vpinsrb xmm30,xmm29,BYTE PTR \[rdx-0x81\],0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f0 ab[ 	]*vpinsrw xmm30,xmm29,rax,0xab
-[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f0 7b[ 	]*vpinsrw xmm30,xmm29,rax,0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f5 7b[ 	]*vpinsrw xmm30,xmm29,rbp,0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 41 95 00 c4 f5 7b[ 	]*vpinsrw xmm30,xmm29,r13,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f0 ab[ 	]*vpinsrw xmm30,xmm29,eax,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f0 7b[ 	]*vpinsrw xmm30,xmm29,eax,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f5 7b[ 	]*vpinsrw xmm30,xmm29,ebp,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 41 95 00 c4 f5 7b[ 	]*vpinsrw xmm30,xmm29,r13d,0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 31 7b[ 	]*vpinsrw xmm30,xmm29,WORD PTR \[rcx\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 21 95 00 c4 b4 f0 23 01 00 00 7b[ 	]*vpinsrw xmm30,xmm29,WORD PTR \[rax\+r14\*8\+0x123\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 72 7f 7b[ 	]*vpinsrw xmm30,xmm29,WORD PTR \[rdx\+0xfe\],0x7b
@@ -690,9 +690,9 @@ Disassembly of section \.text:
 [ 	]*[a-f0-9]+:[ 	]*62 f1 8d 40 65 aa 00 20 00 00[ 	]*vpcmpgtw k5,zmm30,ZMMWORD PTR \[rdx\+0x2000\]
 [ 	]*[a-f0-9]+:[ 	]*62 f1 8d 40 65 6a 80[ 	]*vpcmpgtw k5,zmm30,ZMMWORD PTR \[rdx-0x2000\]
 [ 	]*[a-f0-9]+:[ 	]*62 f1 8d 40 65 aa c0 df ff ff[ 	]*vpcmpgtw k5,zmm30,ZMMWORD PTR \[rdx-0x2040\]
-[ 	]*[a-f0-9]+:[ 	]*62 63 fd 08 14 e8 ab[ 	]*vpextrb rax,xmm29,0xab
-[ 	]*[a-f0-9]+:[ 	]*62 63 fd 08 14 e8 7b[ 	]*vpextrb rax,xmm29,0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 43 fd 08 14 e8 7b[ 	]*vpextrb r8,xmm29,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 63 fd 08 14 e8 ab[ 	]*vpextrb eax,xmm29,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 63 fd 08 14 e8 7b[ 	]*vpextrb eax,xmm29,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 43 fd 08 14 e8 7b[ 	]*vpextrb r8d,xmm29,0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 63 fd 08 14 29 7b[ 	]*vpextrb BYTE PTR \[rcx\],xmm29,0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 23 fd 08 14 ac f0 34 12 00 00 7b[ 	]*vpextrb BYTE PTR \[rax\+r14\*8\+0x1234\],xmm29,0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 63 fd 08 14 6a 7f 7b[ 	]*vpextrb BYTE PTR \[rdx\+0x7f\],xmm29,0x7b
@@ -705,23 +705,23 @@ Disassembly of section \.text:
 [ 	]*[a-f0-9]+:[ 	]*62 63 fd 08 15 aa 00 01 00 00 7b[ 	]*vpextrw WORD PTR \[rdx\+0x100\],xmm29,0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 63 fd 08 15 6a 80 7b[ 	]*vpextrw WORD PTR \[rdx-0x100\],xmm29,0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 63 fd 08 15 aa fe fe ff ff 7b[ 	]*vpextrw WORD PTR \[rdx-0x102\],xmm29,0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 91 fd 08 c5 c6 ab[ 	]*vpextrw rax,xmm30,0xab
-[ 	]*[a-f0-9]+:[ 	]*62 91 fd 08 c5 c6 7b[ 	]*vpextrw rax,xmm30,0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 11 fd 08 c5 c6 7b[ 	]*vpextrw r8,xmm30,0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f0 ab[ 	]*vpinsrb xmm30,xmm29,rax,0xab
-[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f0 7b[ 	]*vpinsrb xmm30,xmm29,rax,0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f5 7b[ 	]*vpinsrb xmm30,xmm29,rbp,0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 43 95 00 20 f5 7b[ 	]*vpinsrb xmm30,xmm29,r13,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 91 fd 08 c5 c6 ab[ 	]*vpextrw eax,xmm30,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 91 fd 08 c5 c6 7b[ 	]*vpextrw eax,xmm30,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 11 fd 08 c5 c6 7b[ 	]*vpextrw r8d,xmm30,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f0 ab[ 	]*vpinsrb xmm30,xmm29,eax,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f0 7b[ 	]*vpinsrb xmm30,xmm29,eax,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f5 7b[ 	]*vpinsrb xmm30,xmm29,ebp,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 43 95 00 20 f5 7b[ 	]*vpinsrb xmm30,xmm29,r13d,0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 31 7b[ 	]*vpinsrb xmm30,xmm29,BYTE PTR \[rcx\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 23 95 00 20 b4 f0 34 12 00 00 7b[ 	]*vpinsrb xmm30,xmm29,BYTE PTR \[rax\+r14\*8\+0x1234\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 72 7f 7b[ 	]*vpinsrb xmm30,xmm29,BYTE PTR \[rdx\+0x7f\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 b2 80 00 00 00 7b[ 	]*vpinsrb xmm30,xmm29,BYTE PTR \[rdx\+0x80\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 72 80 7b[ 	]*vpinsrb xmm30,xmm29,BYTE PTR \[rdx-0x80\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 b2 7f ff ff ff 7b[ 	]*vpinsrb xmm30,xmm29,BYTE PTR \[rdx-0x81\],0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f0 ab[ 	]*vpinsrw xmm30,xmm29,rax,0xab
-[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f0 7b[ 	]*vpinsrw xmm30,xmm29,rax,0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f5 7b[ 	]*vpinsrw xmm30,xmm29,rbp,0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 41 95 00 c4 f5 7b[ 	]*vpinsrw xmm30,xmm29,r13,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f0 ab[ 	]*vpinsrw xmm30,xmm29,eax,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f0 7b[ 	]*vpinsrw xmm30,xmm29,eax,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f5 7b[ 	]*vpinsrw xmm30,xmm29,ebp,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 41 95 00 c4 f5 7b[ 	]*vpinsrw xmm30,xmm29,r13d,0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 31 7b[ 	]*vpinsrw xmm30,xmm29,WORD PTR \[rcx\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 21 95 00 c4 b4 f0 34 12 00 00 7b[ 	]*vpinsrw xmm30,xmm29,WORD PTR \[rax\+r14\*8\+0x1234\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 72 7f 7b[ 	]*vpinsrw xmm30,xmm29,WORD PTR \[rdx\+0xfe\],0x7b
diff --git a/gas/testsuite/gas/i386/x86-64-avx512bw-wig1.d b/gas/testsuite/gas/i386/x86-64-avx512bw-wig1.d
index f48e5e6ff85..d2687009a24 100644
--- a/gas/testsuite/gas/i386/x86-64-avx512bw-wig1.d
+++ b/gas/testsuite/gas/i386/x86-64-avx512bw-wig1.d
@@ -159,9 +159,9 @@ Disassembly of section \.text:
 [ 	]*[a-f0-9]+:[ 	]*62 f1 8d 40 65 aa 00 20 00 00[ 	]*vpcmpgtw 0x2000$%rdx$,%zmm30,%k5
 [ 	]*[a-f0-9]+:[ 	]*62 f1 8d 40 65 6a 80[ 	]*vpcmpgtw -0x2000$%rdx$,%zmm30,%k5
 [ 	]*[a-f0-9]+:[ 	]*62 f1 8d 40 65 aa c0 df ff ff[ 	]*vpcmpgtw -0x2040$%rdx$,%zmm30,%k5
-[ 	]*[a-f0-9]+:[ 	]*62 63 fd 08 14 e8 ab[ 	]*vpextrb \$0xab,%xmm29,%rax
-[ 	]*[a-f0-9]+:[ 	]*62 63 fd 08 14 e8 7b[ 	]*vpextrb \$0x7b,%xmm29,%rax
-[ 	]*[a-f0-9]+:[ 	]*62 43 fd 08 14 e8 7b[ 	]*vpextrb \$0x7b,%xmm29,%r8
+[ 	]*[a-f0-9]+:[ 	]*62 63 fd 08 14 e8 ab[ 	]*vpextrb \$0xab,%xmm29,%eax
+[ 	]*[a-f0-9]+:[ 	]*62 63 fd 08 14 e8 7b[ 	]*vpextrb \$0x7b,%xmm29,%eax
+[ 	]*[a-f0-9]+:[ 	]*62 43 fd 08 14 e8 7b[ 	]*vpextrb \$0x7b,%xmm29,%r8d
 [ 	]*[a-f0-9]+:[ 	]*62 63 fd 08 14 29 7b[ 	]*vpextrb \$0x7b,%xmm29,$%rcx$
 [ 	]*[a-f0-9]+:[ 	]*62 23 fd 08 14 ac f0 23 01 00 00 7b[ 	]*vpextrb \$0x7b,%xmm29,0x123$%rax,%r14,8$
 [ 	]*[a-f0-9]+:[ 	]*62 63 fd 08 14 6a 7f 7b[ 	]*vpextrb \$0x7b,%xmm29,0x7f$%rdx$
@@ -174,23 +174,23 @@ Disassembly of section \.text:
 [ 	]*[a-f0-9]+:[ 	]*62 63 fd 08 15 aa 00 01 00 00 7b[ 	]*vpextrw \$0x7b,%xmm29,0x100$%rdx$
 [ 	]*[a-f0-9]+:[ 	]*62 63 fd 08 15 6a 80 7b[ 	]*vpextrw \$0x7b,%xmm29,-0x100$%rdx$
 [ 	]*[a-f0-9]+:[ 	]*62 63 fd 08 15 aa fe fe ff ff 7b[ 	]*vpextrw \$0x7b,%xmm29,-0x102$%rdx$
-[ 	]*[a-f0-9]+:[ 	]*62 91 fd 08 c5 c6 ab[ 	]*vpextrw \$0xab,%xmm30,%rax
-[ 	]*[a-f0-9]+:[ 	]*62 91 fd 08 c5 c6 7b[ 	]*vpextrw \$0x7b,%xmm30,%rax
-[ 	]*[a-f0-9]+:[ 	]*62 11 fd 08 c5 c6 7b[ 	]*vpextrw \$0x7b,%xmm30,%r8
-[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f0 ab[ 	]*vpinsrb \$0xab,%rax,%xmm29,%xmm30
-[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f0 7b[ 	]*vpinsrb \$0x7b,%rax,%xmm29,%xmm30
-[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f5 7b[ 	]*vpinsrb \$0x7b,%rbp,%xmm29,%xmm30
-[ 	]*[a-f0-9]+:[ 	]*62 43 95 00 20 f5 7b[ 	]*vpinsrb \$0x7b,%r13,%xmm29,%xmm30
+[ 	]*[a-f0-9]+:[ 	]*62 91 fd 08 c5 c6 ab[ 	]*vpextrw \$0xab,%xmm30,%eax
+[ 	]*[a-f0-9]+:[ 	]*62 91 fd 08 c5 c6 7b[ 	]*vpextrw \$0x7b,%xmm30,%eax
+[ 	]*[a-f0-9]+:[ 	]*62 11 fd 08 c5 c6 7b[ 	]*vpextrw \$0x7b,%xmm30,%r8d
+[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f0 ab[ 	]*vpinsrb \$0xab,%eax,%xmm29,%xmm30
+[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f0 7b[ 	]*vpinsrb \$0x7b,%eax,%xmm29,%xmm30
+[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f5 7b[ 	]*vpinsrb \$0x7b,%ebp,%xmm29,%xmm30
+[ 	]*[a-f0-9]+:[ 	]*62 43 95 00 20 f5 7b[ 	]*vpinsrb \$0x7b,%r13d,%xmm29,%xmm30
 [ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 31 7b[ 	]*vpinsrb \$0x7b,$%rcx$,%xmm29,%xmm30
 [ 	]*[a-f0-9]+:[ 	]*62 23 95 00 20 b4 f0 23 01 00 00 7b[ 	]*vpinsrb \$0x7b,0x123$%rax,%r14,8$,%xmm29,%xmm30
 [ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 72 7f 7b[ 	]*vpinsrb \$0x7b,0x7f$%rdx$,%xmm29,%xmm30
 [ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 b2 80 00 00 00 7b[ 	]*vpinsrb \$0x7b,0x80$%rdx$,%xmm29,%xmm30
 [ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 72 80 7b[ 	]*vpinsrb \$0x7b,-0x80$%rdx$,%xmm29,%xmm30
 [ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 b2 7f ff ff ff 7b[ 	]*vpinsrb \$0x7b,-0x81$%rdx$,%xmm29,%xmm30
-[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f0 ab[ 	]*vpinsrw \$0xab,%rax,%xmm29,%xmm30
-[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f0 7b[ 	]*vpinsrw \$0x7b,%rax,%xmm29,%xmm30
-[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f5 7b[ 	]*vpinsrw \$0x7b,%rbp,%xmm29,%xmm30
-[ 	]*[a-f0-9]+:[ 	]*62 41 95 00 c4 f5 7b[ 	]*vpinsrw \$0x7b,%r13,%xmm29,%xmm30
+[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f0 ab[ 	]*vpinsrw \$0xab,%eax,%xmm29,%xmm30
+[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f0 7b[ 	]*vpinsrw \$0x7b,%eax,%xmm29,%xmm30
+[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f5 7b[ 	]*vpinsrw \$0x7b,%ebp,%xmm29,%xmm30
+[ 	]*[a-f0-9]+:[ 	]*62 41 95 00 c4 f5 7b[ 	]*vpinsrw \$0x7b,%r13d,%xmm29,%xmm30
 [ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 31 7b[ 	]*vpinsrw \$0x7b,$%rcx$,%xmm29,%xmm30
 [ 	]*[a-f0-9]+:[ 	]*62 21 95 00 c4 b4 f0 23 01 00 00 7b[ 	]*vpinsrw \$0x7b,0x123$%rax,%r14,8$,%xmm29,%xmm30
 [ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 72 7f 7b[ 	]*vpinsrw \$0x7b,0xfe$%rdx$,%xmm29,%xmm30
@@ -690,9 +690,9 @@ Disassembly of section \.text:
 [ 	]*[a-f0-9]+:[ 	]*62 f1 8d 40 65 aa 00 20 00 00[ 	]*vpcmpgtw 0x2000$%rdx$,%zmm30,%k5
 [ 	]*[a-f0-9]+:[ 	]*62 f1 8d 40 65 6a 80[ 	]*vpcmpgtw -0x2000$%rdx$,%zmm30,%k5
 [ 	]*[a-f0-9]+:[ 	]*62 f1 8d 40 65 aa c0 df ff ff[ 	]*vpcmpgtw -0x2040$%rdx$,%zmm30,%k5
-[ 	]*[a-f0-9]+:[ 	]*62 63 fd 08 14 e8 ab[ 	]*vpextrb \$0xab,%xmm29,%rax
-[ 	]*[a-f0-9]+:[ 	]*62 63 fd 08 14 e8 7b[ 	]*vpextrb \$0x7b,%xmm29,%rax
-[ 	]*[a-f0-9]+:[ 	]*62 43 fd 08 14 e8 7b[ 	]*vpextrb \$0x7b,%xmm29,%r8
+[ 	]*[a-f0-9]+:[ 	]*62 63 fd 08 14 e8 ab[ 	]*vpextrb \$0xab,%xmm29,%eax
+[ 	]*[a-f0-9]+:[ 	]*62 63 fd 08 14 e8 7b[ 	]*vpextrb \$0x7b,%xmm29,%eax
+[ 	]*[a-f0-9]+:[ 	]*62 43 fd 08 14 e8 7b[ 	]*vpextrb \$0x7b,%xmm29,%r8d
 [ 	]*[a-f0-9]+:[ 	]*62 63 fd 08 14 29 7b[ 	]*vpextrb \$0x7b,%xmm29,$%rcx$
 [ 	]*[a-f0-9]+:[ 	]*62 23 fd 08 14 ac f0 34 12 00 00 7b[ 	]*vpextrb \$0x7b,%xmm29,0x1234$%rax,%r14,8$
 [ 	]*[a-f0-9]+:[ 	]*62 63 fd 08 14 6a 7f 7b[ 	]*vpextrb \$0x7b,%xmm29,0x7f$%rdx$
@@ -705,23 +705,23 @@ Disassembly of section \.text:
 [ 	]*[a-f0-9]+:[ 	]*62 63 fd 08 15 aa 00 01 00 00 7b[ 	]*vpextrw \$0x7b,%xmm29,0x100$%rdx$
 [ 	]*[a-f0-9]+:[ 	]*62 63 fd 08 15 6a 80 7b[ 	]*vpextrw \$0x7b,%xmm29,-0x100$%rdx$
 [ 	]*[a-f0-9]+:[ 	]*62 63 fd 08 15 aa fe fe ff ff 7b[ 	]*vpextrw \$0x7b,%xmm29,-0x102$%rdx$
-[ 	]*[a-f0-9]+:[ 	]*62 91 fd 08 c5 c6 ab[ 	]*vpextrw \$0xab,%xmm30,%rax
-[ 	]*[a-f0-9]+:[ 	]*62 91 fd 08 c5 c6 7b[ 	]*vpextrw \$0x7b,%xmm30,%rax
-[ 	]*[a-f0-9]+:[ 	]*62 11 fd 08 c5 c6 7b[ 	]*vpextrw \$0x7b,%xmm30,%r8
-[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f0 ab[ 	]*vpinsrb \$0xab,%rax,%xmm29,%xmm30
-[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f0 7b[ 	]*vpinsrb \$0x7b,%rax,%xmm29,%xmm30
-[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f5 7b[ 	]*vpinsrb \$0x7b,%rbp,%xmm29,%xmm30
-[ 	]*[a-f0-9]+:[ 	]*62 43 95 00 20 f5 7b[ 	]*vpinsrb \$0x7b,%r13,%xmm29,%xmm30
+[ 	]*[a-f0-9]+:[ 	]*62 91 fd 08 c5 c6 ab[ 	]*vpextrw \$0xab,%xmm30,%eax
+[ 	]*[a-f0-9]+:[ 	]*62 91 fd 08 c5 c6 7b[ 	]*vpextrw \$0x7b,%xmm30,%eax
+[ 	]*[a-f0-9]+:[ 	]*62 11 fd 08 c5 c6 7b[ 	]*vpextrw \$0x7b,%xmm30,%r8d
+[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f0 ab[ 	]*vpinsrb \$0xab,%eax,%xmm29,%xmm30
+[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f0 7b[ 	]*vpinsrb \$0x7b,%eax,%xmm29,%xmm30
+[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f5 7b[ 	]*vpinsrb \$0x7b,%ebp,%xmm29,%xmm30
+[ 	]*[a-f0-9]+:[ 	]*62 43 95 00 20 f5 7b[ 	]*vpinsrb \$0x7b,%r13d,%xmm29,%xmm30
 [ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 31 7b[ 	]*vpinsrb \$0x7b,$%rcx$,%xmm29,%xmm30
 [ 	]*[a-f0-9]+:[ 	]*62 23 95 00 20 b4 f0 34 12 00 00 7b[ 	]*vpinsrb \$0x7b,0x1234$%rax,%r14,8$,%xmm29,%xmm30
 [ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 72 7f 7b[ 	]*vpinsrb \$0x7b,0x7f$%rdx$,%xmm29,%xmm30
 [ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 b2 80 00 00 00 7b[ 	]*vpinsrb \$0x7b,0x80$%rdx$,%xmm29,%xmm30
 [ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 72 80 7b[ 	]*vpinsrb \$0x7b,-0x80$%rdx$,%xmm29,%xmm30
 [ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 b2 7f ff ff ff 7b[ 	]*vpinsrb \$0x7b,-0x81$%rdx$,%xmm29,%xmm30
-[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f0 ab[ 	]*vpinsrw \$0xab,%rax,%xmm29,%xmm30
-[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f0 7b[ 	]*vpinsrw \$0x7b,%rax,%xmm29,%xmm30
-[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f5 7b[ 	]*vpinsrw \$0x7b,%rbp,%xmm29,%xmm30
-[ 	]*[a-f0-9]+:[ 	]*62 41 95 00 c4 f5 7b[ 	]*vpinsrw \$0x7b,%r13,%xmm29,%xmm30
+[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f0 ab[ 	]*vpinsrw \$0xab,%eax,%xmm29,%xmm30
+[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f0 7b[ 	]*vpinsrw \$0x7b,%eax,%xmm29,%xmm30
+[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f5 7b[ 	]*vpinsrw \$0x7b,%ebp,%xmm29,%xmm30
+[ 	]*[a-f0-9]+:[ 	]*62 41 95 00 c4 f5 7b[ 	]*vpinsrw \$0x7b,%r13d,%xmm29,%xmm30
 [ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 31 7b[ 	]*vpinsrw \$0x7b,$%rcx$,%xmm29,%xmm30
 [ 	]*[a-f0-9]+:[ 	]*62 21 95 00 c4 b4 f0 34 12 00 00 7b[ 	]*vpinsrw \$0x7b,0x1234$%rax,%r14,8$,%xmm29,%xmm30
 [ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 72 7f 7b[ 	]*vpinsrw \$0x7b,0xfe$%rdx$,%xmm29,%xmm30
diff --git a/gas/testsuite/gas/i386/x86-64-evex-wig1-intel.d b/gas/testsuite/gas/i386/x86-64-evex-wig1-intel.d
index f6031f27968..e1abc7ecb35 100644
--- a/gas/testsuite/gas/i386/x86-64-evex-wig1-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-evex-wig1-intel.d
@@ -9,23 +9,23 @@
 Disassembly of section .text:
 
 0+ <_start>:
-[ 	]*[a-f0-9]+:	62 63 fd 08 17 e8 ab 	vextractps rax,xmm29,0xab
-[ 	]*[a-f0-9]+:	62 63 fd 08 17 e8 7b 	vextractps rax,xmm29,0x7b
-[ 	]*[a-f0-9]+:	62 43 fd 08 17 e8 7b 	vextractps r8,xmm29,0x7b
+[ 	]*[a-f0-9]+:	62 63 fd 08 17 e8 ab 	vextractps eax,xmm29,0xab
+[ 	]*[a-f0-9]+:	62 63 fd 08 17 e8 7b 	vextractps eax,xmm29,0x7b
+[ 	]*[a-f0-9]+:	62 43 fd 08 17 e8 7b 	vextractps r8d,xmm29,0x7b
 [ 	]*[a-f0-9]+:	62 63 fd 08 17 29 7b 	vextractps DWORD PTR \[rcx\],xmm29,0x7b
 [ 	]*[a-f0-9]+:	62 23 fd 08 17 ac f0 23 01 00 00 7b 	vextractps DWORD PTR \[rax\+r14\*8\+0x123\],xmm29,0x7b
 [ 	]*[a-f0-9]+:	62 63 fd 08 17 6a 7f 7b 	vextractps DWORD PTR \[rdx\+0x1fc\],xmm29,0x7b
 [ 	]*[a-f0-9]+:	62 63 fd 08 17 aa 00 02 00 00 7b 	vextractps DWORD PTR \[rdx\+0x200\],xmm29,0x7b
 [ 	]*[a-f0-9]+:	62 63 fd 08 17 6a 80 7b 	vextractps DWORD PTR \[rdx-0x200\],xmm29,0x7b
 [ 	]*[a-f0-9]+:	62 63 fd 08 17 aa fc fd ff ff 7b 	vextractps DWORD PTR \[rdx-0x204\],xmm29,0x7b
-[ 	]*[a-f0-9]+:	62 f3 fd 08 14 c0 00 	vpextrb rax,xmm0,0x0
+[ 	]*[a-f0-9]+:	62 f3 fd 08 14 c0 00 	vpextrb eax,xmm0,0x0
 [ 	]*[a-f0-9]+:	62 f3 fd 08 14 00 00 	vpextrb BYTE PTR \[rax\],xmm0,0x0
-[ 	]*[a-f0-9]+:	62 f1 fd 08 c5 c0 00 	vpextrw rax,xmm0,0x0
-[ 	]*[a-f0-9]+:	62 f3 fd 08 15 c0 00 	vpextrw rax,xmm0,0x0
+[ 	]*[a-f0-9]+:	62 f1 fd 08 c5 c0 00 	vpextrw eax,xmm0,0x0
+[ 	]*[a-f0-9]+:	62 f3 fd 08 15 c0 00 	vpextrw eax,xmm0,0x0
 [ 	]*[a-f0-9]+:	62 f3 fd 08 15 00 00 	vpextrw WORD PTR \[rax\],xmm0,0x0
-[ 	]*[a-f0-9]+:	62 f3 fd 08 20 c0 00 	vpinsrb xmm0,xmm0,rax,0x0
+[ 	]*[a-f0-9]+:	62 f3 fd 08 20 c0 00 	vpinsrb xmm0,xmm0,eax,0x0
 [ 	]*[a-f0-9]+:	62 f3 fd 08 20 00 00 	vpinsrb xmm0,xmm0,BYTE PTR \[rax\],0x0
-[ 	]*[a-f0-9]+:	62 f1 fd 08 c4 c0 00 	vpinsrw xmm0,xmm0,rax,0x0
+[ 	]*[a-f0-9]+:	62 f1 fd 08 c4 c0 00 	vpinsrw xmm0,xmm0,eax,0x0
 [ 	]*[a-f0-9]+:	62 f1 fd 08 c4 00 00 	vpinsrw xmm0,xmm0,WORD PTR \[rax\],0x0
 [ 	]*[a-f0-9]+:	62 02 fd 4f 21 f5    	vpmovsxbd zmm30\{k7\},xmm29
 [ 	]*[a-f0-9]+:	62 02 fd cf 21 f5    	vpmovsxbd zmm30\{k7\}\{z\},xmm29
@@ -91,9 +91,9 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	62 62 fd 4f 34 b2 00 08 00 00 	vpmovzxwq zmm30\{k7\},XMMWORD PTR \[rdx\+0x800\]
 [ 	]*[a-f0-9]+:	62 62 fd 4f 34 72 80 	vpmovzxwq zmm30\{k7\},XMMWORD PTR \[rdx-0x800\]
 [ 	]*[a-f0-9]+:	62 62 fd 4f 34 b2 f0 f7 ff ff 	vpmovzxwq zmm30\{k7\},XMMWORD PTR \[rdx-0x810\]
-[ 	]*[a-f0-9]+:	62 63 fd 08 17 e8 ab 	vextractps rax,xmm29,0xab
-[ 	]*[a-f0-9]+:	62 63 fd 08 17 e8 7b 	vextractps rax,xmm29,0x7b
-[ 	]*[a-f0-9]+:	62 43 fd 08 17 e8 7b 	vextractps r8,xmm29,0x7b
+[ 	]*[a-f0-9]+:	62 63 fd 08 17 e8 ab 	vextractps eax,xmm29,0xab
+[ 	]*[a-f0-9]+:	62 63 fd 08 17 e8 7b 	vextractps eax,xmm29,0x7b
+[ 	]*[a-f0-9]+:	62 43 fd 08 17 e8 7b 	vextractps r8d,xmm29,0x7b
 [ 	]*[a-f0-9]+:	62 63 fd 08 17 29 7b 	vextractps DWORD PTR \[rcx\],xmm29,0x7b
 [ 	]*[a-f0-9]+:	62 23 fd 08 17 ac f0 34 12 00 00 7b 	vextractps DWORD PTR \[rax\+r14\*8\+0x1234\],xmm29,0x7b
 [ 	]*[a-f0-9]+:	62 63 fd 08 17 6a 7f 7b 	vextractps DWORD PTR \[rdx\+0x1fc\],xmm29,0x7b
diff --git a/gas/testsuite/gas/i386/x86-64-evex-wig1.d b/gas/testsuite/gas/i386/x86-64-evex-wig1.d
index 9c49f1c7105..e62e8f4405f 100644
--- a/gas/testsuite/gas/i386/x86-64-evex-wig1.d
+++ b/gas/testsuite/gas/i386/x86-64-evex-wig1.d
@@ -9,23 +9,23 @@
 Disassembly of section .text:
 
 0+ <_start>:
-[ 	]*[a-f0-9]+:	62 63 fd 08 17 e8 ab 	vextractps \$0xab,%xmm29,%rax
-[ 	]*[a-f0-9]+:	62 63 fd 08 17 e8 7b 	vextractps \$0x7b,%xmm29,%rax
-[ 	]*[a-f0-9]+:	62 43 fd 08 17 e8 7b 	vextractps \$0x7b,%xmm29,%r8
+[ 	]*[a-f0-9]+:	62 63 fd 08 17 e8 ab 	vextractps \$0xab,%xmm29,%eax
+[ 	]*[a-f0-9]+:	62 63 fd 08 17 e8 7b 	vextractps \$0x7b,%xmm29,%eax
+[ 	]*[a-f0-9]+:	62 43 fd 08 17 e8 7b 	vextractps \$0x7b,%xmm29,%r8d
 [ 	]*[a-f0-9]+:	62 63 fd 08 17 29 7b 	vextractps \$0x7b,%xmm29,$%rcx$
 [ 	]*[a-f0-9]+:	62 23 fd 08 17 ac f0 23 01 00 00 7b 	vextractps \$0x7b,%xmm29,0x123$%rax,%r14,8$
 [ 	]*[a-f0-9]+:	62 63 fd 08 17 6a 7f 7b 	vextractps \$0x7b,%xmm29,0x1fc$%rdx$
 [ 	]*[a-f0-9]+:	62 63 fd 08 17 aa 00 02 00 00 7b 	vextractps \$0x7b,%xmm29,0x200$%rdx$
 [ 	]*[a-f0-9]+:	62 63 fd 08 17 6a 80 7b 	vextractps \$0x7b,%xmm29,-0x200$%rdx$
 [ 	]*[a-f0-9]+:	62 63 fd 08 17 aa fc fd ff ff 7b 	vextractps \$0x7b,%xmm29,-0x204$%rdx$
-[ 	]*[a-f0-9]+:	62 f3 fd 08 14 c0 00 	vpextrb \$0x0,%xmm0,%rax
+[ 	]*[a-f0-9]+:	62 f3 fd 08 14 c0 00 	vpextrb \$0x0,%xmm0,%eax
 [ 	]*[a-f0-9]+:	62 f3 fd 08 14 00 00 	vpextrb \$0x0,%xmm0,$%rax$
-[ 	]*[a-f0-9]+:	62 f1 fd 08 c5 c0 00 	vpextrw \$0x0,%xmm0,%rax
-[ 	]*[a-f0-9]+:	62 f3 fd 08 15 c0 00 	vpextrw \$0x0,%xmm0,%rax
+[ 	]*[a-f0-9]+:	62 f1 fd 08 c5 c0 00 	vpextrw \$0x0,%xmm0,%eax
+[ 	]*[a-f0-9]+:	62 f3 fd 08 15 c0 00 	vpextrw \$0x0,%xmm0,%eax
 [ 	]*[a-f0-9]+:	62 f3 fd 08 15 00 00 	vpextrw \$0x0,%xmm0,$%rax$
-[ 	]*[a-f0-9]+:	62 f3 fd 08 20 c0 00 	vpinsrb \$0x0,%rax,%xmm0,%xmm0
+[ 	]*[a-f0-9]+:	62 f3 fd 08 20 c0 00 	vpinsrb \$0x0,%eax,%xmm0,%xmm0
 [ 	]*[a-f0-9]+:	62 f3 fd 08 20 00 00 	vpinsrb \$0x0,$%rax$,%xmm0,%xmm0
-[ 	]*[a-f0-9]+:	62 f1 fd 08 c4 c0 00 	vpinsrw \$0x0,%rax,%xmm0,%xmm0
+[ 	]*[a-f0-9]+:	62 f1 fd 08 c4 c0 00 	vpinsrw \$0x0,%eax,%xmm0,%xmm0
 [ 	]*[a-f0-9]+:	62 f1 fd 08 c4 00 00 	vpinsrw \$0x0,$%rax$,%xmm0,%xmm0
 [ 	]*[a-f0-9]+:	62 02 fd 4f 21 f5    	vpmovsxbd %xmm29,%zmm30\{%k7\}
 [ 	]*[a-f0-9]+:	62 02 fd cf 21 f5    	vpmovsxbd %xmm29,%zmm30\{%k7\}\{z\}
@@ -91,9 +91,9 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	62 62 fd 4f 34 b2 00 08 00 00 	vpmovzxwq 0x800$%rdx$,%zmm30\{%k7\}
 [ 	]*[a-f0-9]+:	62 62 fd 4f 34 72 80 	vpmovzxwq -0x800$%rdx$,%zmm30\{%k7\}
 [ 	]*[a-f0-9]+:	62 62 fd 4f 34 b2 f0 f7 ff ff 	vpmovzxwq -0x810$%rdx$,%zmm30\{%k7\}
-[ 	]*[a-f0-9]+:	62 63 fd 08 17 e8 ab 	vextractps \$0xab,%xmm29,%rax
-[ 	]*[a-f0-9]+:	62 63 fd 08 17 e8 7b 	vextractps \$0x7b,%xmm29,%rax
-[ 	]*[a-f0-9]+:	62 43 fd 08 17 e8 7b 	vextractps \$0x7b,%xmm29,%r8
+[ 	]*[a-f0-9]+:	62 63 fd 08 17 e8 ab 	vextractps \$0xab,%xmm29,%eax
+[ 	]*[a-f0-9]+:	62 63 fd 08 17 e8 7b 	vextractps \$0x7b,%xmm29,%eax
+[ 	]*[a-f0-9]+:	62 43 fd 08 17 e8 7b 	vextractps \$0x7b,%xmm29,%r8d
 [ 	]*[a-f0-9]+:	62 63 fd 08 17 29 7b 	vextractps \$0x7b,%xmm29,$%rcx$
 [ 	]*[a-f0-9]+:	62 23 fd 08 17 ac f0 34 12 00 00 7b 	vextractps \$0x7b,%xmm29,0x1234$%rax,%r14,8$
 [ 	]*[a-f0-9]+:	62 63 fd 08 17 6a 7f 7b 	vextractps \$0x7b,%xmm29,0x1fc$%rdx$
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 6efc15b851b..521d6899338 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -240,11 +240,8 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
 #define EvS { OP_E, v_swap_mode }
 #define Ed { OP_E, d_mode }
 #define Edq { OP_E, dq_mode }
-#define Edqw { OP_E, dqw_mode }
-#define Edqb { OP_E, dqb_mode }
 #define Edb { OP_E, db_mode }
 #define Edw { OP_E, dw_mode }
-#define Edqd { OP_E, dqd_mode }
 #define Eq { OP_E, q_mode }
 #define indirEv { OP_indirE, indir_v_mode }
 #define indirEp { OP_indirE, f_mode }
@@ -509,8 +506,7 @@ enum
   v_bndmk_mode,
   /* operand size depends on REX.W / VEX.W.  */
   dq_mode,
-  /* registers like dq_mode, memory like w_mode, displacements like
-     v_mode without considering Intel64 ISA.  */
+  /* Displacements like v_mode without considering Intel64 ISA.  */
   dqw_mode,
   /* bounds operand */
   bnd_mode,
@@ -527,14 +523,10 @@ enum
   z_mode,
   /* 16-byte operand */
   o_mode,
-  /* registers like dq_mode, memory like b_mode.  */
-  dqb_mode,
   /* registers like d_mode, memory like b_mode.  */
   db_mode,
   /* registers like d_mode, memory like w_mode.  */
   dw_mode,
-  /* registers like dq_mode, memory like d_mode.  */
-  dqd_mode,
 
   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
   vex_vsib_d_w_dq_mode,
@@ -2182,8 +2174,8 @@ static const struct dis386 dis386_twobyte[] = {
   { "xaddS",		{ Evh1, Gv }, 0 },
   { PREFIX_TABLE (PREFIX_0FC2) },
   { MOD_TABLE (MOD_0FC3) },
-  { "pinsrw",		{ MX, Edqw, Ib }, PREFIX_OPCODE },
-  { "pextrw",		{ Gdq, MS, Ib }, PREFIX_OPCODE },
+  { "pinsrw",		{ MX, Edw, Ib }, PREFIX_OPCODE },
+  { "pextrw",		{ Gd, MS, Ib }, PREFIX_OPCODE },
   { "shufpX",		{ XM, EXx, Ib }, PREFIX_OPCODE },
   { REG_TABLE (REG_0FC7) },
   /* c8 */
@@ -4687,10 +4679,10 @@ static const struct dis386 three_byte_table[][256] = {
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
-    { "pextrb",	{ Edqb, XM, Ib }, PREFIX_DATA },
-    { "pextrw",	{ Edqw, XM, Ib }, PREFIX_DATA },
+    { "pextrb",	{ Edb, XM, Ib }, PREFIX_DATA },
+    { "pextrw",	{ Edw, XM, Ib }, PREFIX_DATA },
     { "pextrK",	{ Edq, XM, Ib }, PREFIX_DATA },
-    { "extractps", { Edqd, XM, Ib }, PREFIX_DATA },
+    { "extractps", { Ed, XM, Ib }, PREFIX_DATA },
     /* 18 */
     { Bad_Opcode },
     { Bad_Opcode },
@@ -4701,7 +4693,7 @@ static const struct dis386 three_byte_table[][256] = {
     { Bad_Opcode },
     { Bad_Opcode },
     /* 20 */
-    { "pinsrb",	{ XM, Edqb, Ib }, PREFIX_DATA },
+    { "pinsrb",	{ XM, Edb, Ib }, PREFIX_DATA },
     { "insertps", { XM, EXd, Ib }, PREFIX_DATA },
     { "pinsrK",	{ XM, Edq, Ib }, PREFIX_DATA },
     { Bad_Opcode },
@@ -6850,12 +6842,12 @@ static const struct dis386 vex_len_table[][2] = {
 
   /* VEX_LEN_0FC4 */
   {
-    { "vpinsrw",	{ XM, Vex, Edqw, Ib }, PREFIX_DATA },
+    { "vpinsrw",	{ XM, Vex, Edw, Ib }, PREFIX_DATA },
   },
 
   /* VEX_LEN_0FC5 */
   {
-    { "vpextrw",	{ Gdq, XS, Ib }, PREFIX_DATA },
+    { "vpextrw",	{ Gd, XS, Ib }, PREFIX_DATA },
   },
 
   /* VEX_LEN_0FD6 */
@@ -7012,12 +7004,12 @@ static const struct dis386 vex_len_table[][2] = {
 
   /* VEX_LEN_0F3A14 */
   {
-    { "vpextrb",	{ Edqb, XM, Ib }, PREFIX_DATA },
+    { "vpextrb",	{ Edb, XM, Ib }, PREFIX_DATA },
   },
 
   /* VEX_LEN_0F3A15 */
   {
-    { "vpextrw",	{ Edqw, XM, Ib }, PREFIX_DATA },
+    { "vpextrw",	{ Edw, XM, Ib }, PREFIX_DATA },
   },
 
   /* VEX_LEN_0F3A16  */
@@ -7027,7 +7019,7 @@ static const struct dis386 vex_len_table[][2] = {
 
   /* VEX_LEN_0F3A17 */
   {
-    { "vextractps",	{ Edqd, XM, Ib }, PREFIX_DATA },
+    { "vextractps",	{ Ed, XM, Ib }, PREFIX_DATA },
   },
 
   /* VEX_LEN_0F3A18 */
@@ -7044,7 +7036,7 @@ static const struct dis386 vex_len_table[][2] = {
 
   /* VEX_LEN_0F3A20 */
   {
-    { "vpinsrb",	{ XM, Vex, Edqb, Ib }, PREFIX_DATA },
+    { "vpinsrb",	{ XM, Vex, Edb, Ib }, PREFIX_DATA },
   },
 
   /* VEX_LEN_0F3A21 */
@@ -10957,13 +10949,11 @@ intel_operand_size (int bytemode, int sizeflag)
     {
     case b_mode:
     case b_swap_mode:
-    case dqb_mode:
     case db_mode:
       oappend ("BYTE PTR ");
       break;
     case w_mode:
     case dw_mode:
-    case dqw_mode:
       oappend ("WORD PTR ");
       break;
     case indir_v_mode:
@@ -11020,7 +11010,6 @@ intel_operand_size (int bytemode, int sizeflag)
       break;
     case d_mode:
     case d_swap_mode:
-    case dqd_mode:
       oappend ("DWORD PTR ");
       break;
     case q_mode:
@@ -11263,9 +11252,6 @@ print_register (unsigned int reg, unsigned int rexmask, int bytemode, int sizefl
     case v_mode:
     case v_swap_mode:
     case dq_mode:
-    case dqb_mode:
-    case dqd_mode:
-    case dqw_mode:
       USED_REX (REX_W);
       if (rex & REX_W)
 	names = names64;
@@ -11340,12 +11326,10 @@ OP_E_memory (int bytemode, int sizeflag)
 	}
       switch (bytemode)
 	{
-	case dqw_mode:
 	case dw_mode:
 	case w_mode:
 	  shift = 1;
 	  break;
-	case dqb_mode:
 	case db_mode:
 	case b_mode:
 	  shift = 0;
@@ -11353,7 +11337,6 @@ OP_E_memory (int bytemode, int sizeflag)
 	case dq_mode:
 	  if (address_mode != mode_64bit)
 	    {
-	case dqd_mode:
 	case d_mode:
 	case d_swap_mode:
 	      shift = 2;
-- 
2.33.0