File _service:tar_scm:add-loongarch-support.patch of Package libpq

File _service:tar_scm:add-loongarch-support.patch of Package libpq (Revision cb9ec0b0b467f70be295f42f99feda29)

Currently displaying revision cb9ec0b0b467f70be295f42f99feda29 , Show latest

diff --git a/src/include/storage/s_lock.h b/src/include/storage/s_lock.h
index 6b368a5..86e0e84 100644
--- a/src/include/storage/s_lock.h
+++ b/src/include/storage/s_lock.h
@@ -696,6 +696,45 @@ do \
 
 #endif /* __mips__ && !__sgi */
 
+#if defined(__loongarch__)   /* loongarch */
+#define HAS_TEST_AND_SET
+
+typedef unsigned int slock_t;
+
+#define TAS(lock) tas(lock)
+
+static __inline__ int
+tas(volatile slock_t *lock)
+{
+	register volatile slock_t *_l = lock;
+	register int _res;
+	register int _tmp;
+
+	__asm__ __volatile__(
+		"       ll.w    %0, %2      \n"
+		"       ori     %1, %0, 1   \n"
+		"       sc.w    %1, %2      \n"
+		"       xori    %1, %1, 1   \n"
+		"       or      %0, %0, %1  \n"
+		"       dbar    0           \n"
+:              "=&r" (_res), "=&r" (_tmp), "+R" (*_l)
+:              /* no inputs */
+:              "memory");
+	return _res;
+}
+
+#define S_UNLOCK(lock) \
+do \
+{ \
+	__asm__ __volatile__( \
+		"  dbar  0 \n" \
+:              /* no outputs */ \
+:              /* no inputs */ \
+:              "memory"); \
+	*((volatile slock_t *) (lock)) = 0; \
+} while (0)
+#endif /* __loongarch__ */
+
 
 #if defined(__m32r__) && defined(HAVE_SYS_TAS_H)	/* Renesas' M32R */
 #define HAS_TEST_AND_SET