Projects
home:Eustace:branches:Eulaceura:Factory
Jailhouse
_service:obs_scm:0003-add-e2000-surpport-and-ch...
Sign Up
Log In
Username
Password
Overview
Repositories
Revisions
Requests
Users
Attributes
Meta
File _service:obs_scm:0003-add-e2000-surpport-and-change-directory-KEYWORDS-e20.patch of Package Jailhouse
From 02e23005df6a3da1385bd0c6681de0c9ae266436 Mon Sep 17 00:00:00 2001 From: zhangyunfei <zhangyunfei@kylinos.cn> Date: Fri, 30 Dec 2022 11:18:35 +0800 Subject: [PATCH 03/12] add e2000 surpport and change directory [KEYWORDS] e2000 [TO SOLVE] [TEST SUGGESTION] none [SUBMIT BY] zhangyunfei [REVIEW BY] zhangyunfei [TEST BY] zhangyunfei --- .../{phytium => }/d2000-inmate-board-rtos.c | 0 .../{phytium => }/d2000-main-board-rtos.c | 0 .../{phytium => }/d2000-pc-inmate-rtos.c | 0 .../arm64/{phytium => }/d2000-pc-main-rtos.c | 0 .../dts/{phytium => }/e2000-cluster0.dts | 0 configs/arm64/dts/e2000-main-reserve.dts | 870 ++++++++++++++++++ .../dts/{phytium => }/ft2004-AMA0-ivshmem.dts | 0 .../dts/{phytium => }/ft2004-AMA0-uart.dts | 0 .../arm64/dts/{phytium => }/ft2004-AMA0.dts | 0 .../dts/{phytium => }/ft2004-AMA1-ivshmem.dts | 0 .../dts/{phytium => }/ft2004-AMA1-uart.dts | 0 .../dts/{phytium => }/ft2004-guest-eth.dts | 0 .../dts/{phytium => }/ft2004-main-eth.dts | 0 configs/arm64/dts/{phytium => }/ft2004.dts | 0 .../arm64/dts/{phytium => }/ftd2000-AMA0.dts | 0 .../arm64/dts/{phytium => }/ftd2000-AMA1.dts | 0 configs/arm64/e2000-guest-demo.c | 128 +++ configs/arm64/e2000-linux-demo.c | 149 +++ configs/arm64/e2000-rtos-32-uart2.c | 190 ++++ configs/arm64/e2000-rtos32-demo.c | 129 +++ configs/arm64/e2000q-dev.c | 333 +++++++ .../arm64/{phytium => }/ft2004-inmate-eth.c | 0 .../{phytium => }/ft2004-inmate-ivshmem.c | 0 configs/arm64/{phytium => }/ft2004-inmate.c | 0 configs/arm64/{phytium => }/ft2004-main-eth.c | 0 .../arm64/{phytium => }/ft2004-main-ivshmem.c | 0 configs/arm64/{phytium => }/ft2004-main.c | 0 27 files changed, 1799 insertions(+) rename configs/arm64/{phytium => }/d2000-inmate-board-rtos.c (100%) rename configs/arm64/{phytium => }/d2000-main-board-rtos.c (100%) rename configs/arm64/{phytium => }/d2000-pc-inmate-rtos.c (100%) rename configs/arm64/{phytium => }/d2000-pc-main-rtos.c (100%) rename configs/arm64/dts/{phytium => }/e2000-cluster0.dts (100%) create mode 100644 configs/arm64/dts/e2000-main-reserve.dts rename configs/arm64/dts/{phytium => }/ft2004-AMA0-ivshmem.dts (100%) rename configs/arm64/dts/{phytium => }/ft2004-AMA0-uart.dts (100%) rename configs/arm64/dts/{phytium => }/ft2004-AMA0.dts (100%) rename configs/arm64/dts/{phytium => }/ft2004-AMA1-ivshmem.dts (100%) rename configs/arm64/dts/{phytium => }/ft2004-AMA1-uart.dts (100%) rename configs/arm64/dts/{phytium => }/ft2004-guest-eth.dts (100%) rename configs/arm64/dts/{phytium => }/ft2004-main-eth.dts (100%) rename configs/arm64/dts/{phytium => }/ft2004.dts (100%) rename configs/arm64/dts/{phytium => }/ftd2000-AMA0.dts (100%) rename configs/arm64/dts/{phytium => }/ftd2000-AMA1.dts (100%) create mode 100644 configs/arm64/e2000-guest-demo.c create mode 100644 configs/arm64/e2000-linux-demo.c create mode 100644 configs/arm64/e2000-rtos-32-uart2.c create mode 100644 configs/arm64/e2000-rtos32-demo.c create mode 100644 configs/arm64/e2000q-dev.c rename configs/arm64/{phytium => }/ft2004-inmate-eth.c (100%) rename configs/arm64/{phytium => }/ft2004-inmate-ivshmem.c (100%) rename configs/arm64/{phytium => }/ft2004-inmate.c (100%) rename configs/arm64/{phytium => }/ft2004-main-eth.c (100%) rename configs/arm64/{phytium => }/ft2004-main-ivshmem.c (100%) rename configs/arm64/{phytium => }/ft2004-main.c (100%) diff --git a/configs/arm64/phytium/d2000-inmate-board-rtos.c b/configs/arm64/d2000-inmate-board-rtos.c similarity index 100% rename from configs/arm64/phytium/d2000-inmate-board-rtos.c rename to configs/arm64/d2000-inmate-board-rtos.c diff --git a/configs/arm64/phytium/d2000-main-board-rtos.c b/configs/arm64/d2000-main-board-rtos.c similarity index 100% rename from configs/arm64/phytium/d2000-main-board-rtos.c rename to configs/arm64/d2000-main-board-rtos.c diff --git a/configs/arm64/phytium/d2000-pc-inmate-rtos.c b/configs/arm64/d2000-pc-inmate-rtos.c similarity index 100% rename from configs/arm64/phytium/d2000-pc-inmate-rtos.c rename to configs/arm64/d2000-pc-inmate-rtos.c diff --git a/configs/arm64/phytium/d2000-pc-main-rtos.c b/configs/arm64/d2000-pc-main-rtos.c similarity index 100% rename from configs/arm64/phytium/d2000-pc-main-rtos.c rename to configs/arm64/d2000-pc-main-rtos.c diff --git a/configs/arm64/dts/phytium/e2000-cluster0.dts b/configs/arm64/dts/e2000-cluster0.dts similarity index 100% rename from configs/arm64/dts/phytium/e2000-cluster0.dts rename to configs/arm64/dts/e2000-cluster0.dts diff --git a/configs/arm64/dts/e2000-main-reserve.dts b/configs/arm64/dts/e2000-main-reserve.dts new file mode 100644 index 00000000..e4083ef2 --- /dev/null +++ b/configs/arm64/dts/e2000-main-reserve.dts @@ -0,0 +1,870 @@ +/dts-v1/; +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/memreserve/ 0x0000000080000000 0x0000000000010000; +/ { + compatible = "phytium,e2000q"; + interrupt-parent = <0x1>; + #address-cells = <0x2>; + #size-cells = <0x2>; + model = "E2000Q TESTA DDR4 Board"; + + aliases { + serial0 = "/soc/uart@2800c000"; + serial1 = "/soc/uart@2800d000"; + serial2 = "/soc/uart@2800e000"; + serial3 = "/soc/uart@2800f000"; + ethernet0 = "/soc/ethernet@3200c000"; + ethernet1 = "/soc/ethernet@3200e000"; + ethernet2 = "/soc/ethernet@32010000"; + ethernet3 = "/soc/ethernet@32012000"; + }; + + reserved-memory { + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + + reserved@90000000 { + reg = <0x0 0x90000000 0x0 0x20000000>; + no-map; + }; + }; + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + cpu_suspend = <0xc4000001>; + cpu_off = <0x84000002>; + cpu_on = <0xc4000003>; + sys_poweroff = <0x84000008>; + sys_reset = <0x84000009>; + }; + + firmware { + + scmi { + compatible = "arm,scmi"; + mboxes = <0x2 0x0 0x2 0x1>; + mbox-names = "tx", "rx"; + shmem = <0x3 0x4>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + protocol@13 { + reg = <0x13>; + #clock-cells = <0x1>; + phandle = <0xa>; + }; + + protocol@15 { + reg = <0x15>; + #thermal-sensor-cells = <0x1>; + phandle = <0x5>; + }; + }; + }; + + thermal-zones { + + sensor0 { + polling-delay-passive = <0x64>; + polling-delay = <0x3e8>; + thermal-sensors = <0x5 0x0>; + }; + + sensor1 { + polling-delay-passive = <0x64>; + polling-delay = <0x3e8>; + thermal-sensors = <0x5 0x1>; + }; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu-map { + + cluster0 { + + core0 { + cpu = <0x6>; + }; + + core1 { + cpu = <0x7>; + }; + }; + + cluster1 { + + core0 { + cpu = <0x8>; + }; + + cluster2 { + + core0 { + cpu = <0x9>; + }; + }; + }; + }; + + cpu@0 { + device_type = "cpu"; + compatible = "phytium,ftc310", "arm,armv8"; + reg = <0x0 0x200>; + enable-method = "psci"; + clocks = <0xa 0x2>; + phandle = <0x6>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "phytium,ftc310", "arm,armv8"; + reg = <0x0 0x201>; + enable-method = "psci"; + clocks = <0xa 0x2>; + phandle = <0x7>; + }; + + cpu@100 { + device_type = "cpu"; + compatible = "phytium,ftc664", "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + clocks = <0xa 0x0>; + phandle = <0x8>; + }; + + cpu@101 { + device_type = "cpu"; + compatible = "phytium,ftc664", "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + clocks = <0xa 0x1>; + phandle = <0x9>; + }; + }; + + interrupt-controller@30800000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <0x3>; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + interrupt-controller; + reg = <0x0 0x30800000 0x0 0x20000 0x0 0x30880000 0x0 0x80000 0x0 0x30840000 0x0 0x10000 0x0 0x30850000 0x0 0x10000 0x0 0x30860000 0x0 0x10000>; + interrupts = <0x1 0x9 0x8>; + phandle = <0x1>; + + gic-its@30820000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0x30820000 0x0 0x20000>; + phandle = <0xe>; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0x1 0x7 0x8>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <0x1 0xd 0x8 0x1 0xe 0x8 0x1 0xb 0x8 0x1 0xa 0x8>; + clock-frequency = <0x2faf080>; + }; + + clocks { + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + + clk48mhz { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <0x2dc6c00>; + phandle = <0x12>; + }; + + clk50mhz { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <0x2faf080>; + phandle = <0xc>; + }; + + clk100mhz { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <0x5f5e100>; + phandle = <0xd>; + }; + + clk200mhz { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <0xbebc200>; + phandle = <0x10>; + }; + + clk250mhz { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <0xee6b280>; + phandle = <0x11>; + }; + + clk300mhz { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <0x11e1a300>; + }; + + clk600mhz { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <0x23c34600>; + phandle = <0xf>; + }; + + clk1200mhz { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <0x47868c00>; + phandle = <0xb>; + }; + }; + + + soc { + compatible = "simple-bus"; + #address-cells = <0x2>; + #size-cells = <0x2>; + dma-coherent; + ranges; + + mmc@28000000 { + compatible = "phytium,mci"; + reg = <0x0 0x28000000 0x0 0x1000>; + interrupts = <0x0 0x48 0x4>; + clocks = <0xb>; + clock-names = "phytium_mci_clk"; + status = "disabled"; + bus-width = <0x8>; + max-frequency = <0x17d7840>; + cap-mmc-hw-reset; + cap-mmc-highspeed; + no-sdio; + no-sd; + non-removable; + }; + + mmc@28001000 { + compatible = "phytium,mci"; + reg = <0x0 0x28001000 0x0 0x1000>; + interrupts = <0x0 0x49 0x4>; + clocks = <0xb>; + clock-names = "phytium_mci_clk"; + status = "disabled"; + }; + + nand@28002000 { + compatible = "phytium,nfc"; + reg = <0x0 0x28002000 0x0 0x1000>; + interrupts = <0x0 0x4a 0x4>; + status = "disabled"; + }; + + qspi@28008000 { + compatible = "phytium,qspi"; + reg = <0x0 0x28008000 0x0 0x1000 0x0 0x0 0x0 0xfffffff>; + reg-names = "qspi", "qspi_mm"; + clocks = <0xc>; + status = "disabled"; + + flash@0 { + spi-rx-bus-width = <0x1>; + spi-max-frequency = <0x2faf080>; + }; + }; + + uart@2800c000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x2800c000 0x0 0x1000>; + interrupts = <0x0 0x53 0x4>; + clocks = <0xd 0xd>; + clock-names = "uartclk", "apb_pclk"; + status = "okay"; + }; + + uart@2800d000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x2800d000 0x0 0x1000>; + interrupts = <0x0 0x54 0x4>; + clocks = <0xd 0xd>; + clock-names = "uartclk", "apb_pclk"; + status = "okay"; + }; + + uart@2800e000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x2800e000 0x0 0x1000>; + interrupts = <0x0 0x55 0x4>; + clocks = <0xd 0xd>; + clock-names = "uartclk", "apb_pclk"; + status = "okay"; //modify by lrx + }; + + uart@2800f000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x2800f000 0x0 0x1000>; + interrupts = <0x0 0x56 0x4>; + clocks = <0xd 0xd>; + clock-names = "uartclk", "apb_pclk"; + status = "okay"; + }; + + lpc@28010000 { + compatible = "simple-mfd", "syscon"; + reg = <0x0 0x28010000 0x0 0x1000>; + reg-io-width = <0x4>; + #address-cells = <0x1>; + #size-cells = <0x1>; + ranges = <0x0 0x0 0x28010000 0x1000>; + + kcs@24 { + compatible = "phytium,e2000-kcs-bmc"; + reg = <0x24 0x1 0x30 0x1 0x3c 0x1>; + interrupts = <0x0 0x58 0x4>; + status = "disabled"; + }; + + kcs@28 { + compatible = "phytium,e2000-kcs-bmc"; + reg = <0x28 0x1 0x34 0x1 0x40 0x1>; + interrupts = <0x0 0x58 0x4>; + status = "disabled"; + }; + + kcs@2c { + compatible = "phytium,e2000-kcs-bmc"; + reg = <0x2c 0x1 0x38 0x1 0x44 0x1>; + interrupts = <0x0 0x58 0x4>; + status = "disabled"; + }; + + kcs@8c { + compatible = "phytium,e2000-kcs-bmc"; + reg = <0x8c 0x1 0x90 0x1 0x94 0x1>; + interrupts = <0x0 0x58 0x4>; + status = "disabled"; + }; + + ibt@250 { + compatible = "phytium,e2000-ibt-bmc"; + reg = <0x250 0x1c>; + interrupts = <0x0 0x58 0x4>; + status = "disabled"; + }; + }; + + gpio@28034000 { + compatible = "phytium,gpio"; + reg = <0x0 0x28034000 0x0 0x1000>; + interrupts = <0x0 0x6c 0x4 0x0 0x6d 0x4 0x0 0x6e 0x4 0x0 0x6f 0x4 0x0 0x70 0x4 0x0 0x71 0x4 0x0 0x72 0x4 0x0 0x73 0x4 0x0 0x74 0x4 0x0 0x75 0x4 0x0 0x76 0x4 0x0 0x77 0x4 0x0 0x78 0x4 0x0 0x79 0x4 0x0 0x7a 0x4 0x0 0x7b 0x4>; + gpio-controller; + #gpio-cells = <0x2>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "disabled"; + + porta { + compatible = "phytium,gpio-port"; + reg = <0x0>; + nr-gpios = <0x10>; + }; + }; + + gpio@28035000 { + compatible = "phytium,gpio"; + reg = <0x0 0x28035000 0x0 0x1000>; + interrupts = <0x0 0x7c 0x4 0x0 0x7d 0x4 0x0 0x7e 0x4 0x0 0x7f 0x4 0x0 0x80 0x4 0x0 0x81 0x4 0x0 0x82 0x4 0x0 0x83 0x4 0x0 0x84 0x4 0x0 0x85 0x4 0x0 0x86 0x4 0x0 0x87 0x4 0x0 0x88 0x4 0x0 0x89 0x4 0x0 0x8a 0x4 0x0 0x8b 0x4>; + gpio-controller; + #gpio-cells = <0x2>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "disabled"; + + porta { + compatible = "phytium,gpio-port"; + reg = <0x0>; + nr-gpios = <0x10>; + }; + }; + + gpio@28036000 { + compatible = "phytium,gpio"; + reg = <0x0 0x28036000 0x0 0x1000>; + interrupts = <0x0 0x8c 0x4 0x0 0x8d 0x4 0x0 0x8e 0x4 0x0 0x8f 0x4 0x0 0x90 0x4 0x0 0x91 0x4 0x0 0x92 0x4 0x0 0x93 0x4 0x0 0x94 0x4 0x0 0x95 0x4 0x0 0x96 0x4 0x0 0x97 0x4 0x0 0x98 0x4 0x0 0x99 0x4 0x0 0x9a 0x4 0x0 0x9b 0x4>; + gpio-controller; + #gpio-cells = <0x2>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "disabled"; + + porta { + compatible = "phytium,gpio-port"; + reg = <0x0>; + nr-gpios = <0x10>; + }; + }; + + gpio@28037000 { + compatible = "phytium,gpio"; + reg = <0x0 0x28037000 0x0 0x1000>; + interrupts = <0x0 0x9c 0x4>; + gpio-controller; + #gpio-cells = <0x2>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "disabled"; + + porta { + compatible = "phytium,gpio-port"; + reg = <0x0>; + nr-gpios = <0x10>; + }; + }; + + gpio@28038000 { + compatible = "phytium,gpio"; + reg = <0x0 0x28038000 0x0 0x1000>; + interrupts = <0x0 0x9d 0x4>; + gpio-controller; + #gpio-cells = <0x2>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "disabled"; + + porta { + compatible = "phytium,gpio-port"; + reg = <0x0>; + nr-gpios = <0x10>; + }; + }; + + gpio@28039000 { + compatible = "phytium,gpio"; + reg = <0x0 0x28039000 0x0 0x1000>; + interrupts = <0x0 0x9e 0x4>; + gpio-controller; + #gpio-cells = <0x2>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "disabled"; + + porta { + compatible = "phytium,gpio-port"; + reg = <0x0>; + nr-gpios = <0x10>; + }; + }; + + spi@2803a000 { + compatible = "phytium,spi"; + reg = <0x0 0x2803a000 0x0 0x1000>; + interrupts = <0x0 0x9f 0x4>; + clocks = <0xc>; + num-cs = <0x4>; + status = "okay"; + }; + + spi@2803b000 { + compatible = "phytium,spi"; + reg = <0x0 0x2803b000 0x0 0x1000>; + interrupts = <0x0 0xa0 0x4>; + clocks = <0xc>; + num-cs = <0x4>; + status = "disabled"; + }; + + spi@2803c000 { + compatible = "phytium,spi"; + reg = <0x0 0x2803c000 0x0 0x1000>; + interrupts = <0x0 0xa1 0x4>; + clocks = <0xc>; + num-cs = <0x4>; + status = "disabled"; + }; + + spi@2803d000 { + compatible = "phytium,spi"; + reg = <0x0 0x2803d000 0x0 0x1000>; + interrupts = <0x0 0xa2 0x4>; + clocks = <0xc>; + num-cs = <0x4>; + status = "disabled"; + }; + + watchdog@28040000 { + compatible = "arm,sbsa-gwdt"; + reg = <0x0 0x28041000 0x0 0x1000 0x0 0x28040000 0x0 0x1000>; + interrupts = <0x0 0xa4 0x4>; + timeout-sec = <0x1e>; + status = "disabled"; + }; + + watchdog@28042000 { + compatible = "arm,sbsa-gwdt"; + reg = <0x0 0x28043000 0x0 0x1000 0x0 0x28042000 0x0 0x1000>; + interrupts = <0x0 0xa5 0x4>; + timeout-sec = <0x1e>; + status = "disabled"; + }; + + pwm@2804a000 { + compatible = "phytium,pwm"; + reg = <0x0 0x2804a000 0x0 0x1000>; + interrupts = <0x0 0xad 0x4>; + clocks = <0xc>; + status = "disabled"; + }; + + pwm@2804b000 { + compatible = "phytium,pwm"; + reg = <0x0 0x2804b000 0x0 0x1000>; + interrupts = <0x0 0xae 0x4>; + clocks = <0xc>; + status = "disabled"; + }; + + pwm@2804c000 { + compatible = "phytium,pwm"; + reg = <0x0 0x2804c000 0x0 0x1000>; + interrupts = <0x0 0xaf 0x4>; + clocks = <0xc>; + status = "disabled"; + }; + + pwm@2804d000 { + compatible = "phytium,pwm"; + reg = <0x0 0x2804d000 0x0 0x1000>; + interrupts = <0x0 0xb0 0x4>; + clocks = <0xc>; + status = "disabled"; + }; + + usb2@31800000 { + compatible = "cdns,usb2"; + reg = <0x0 0x31800000 0x0 0x80000>; + interrupts = <0x0 0x20 0x4>; + status = "okay"; + dr_mode = "host"; + }; + + /*usb2@31880000 { + compatible = "cdns,usb2"; + reg = <0x0 0x31880000 0x0 0x80000>; + interrupts = <0x0 0x21 0x4>; + status = "okay"; + dr_mode = "host"; + }; + + usb2@31900000 { + compatible = "cdns,usb2"; + reg = <0x0 0x31900000 0x0 0x80000>; + interrupts = <0x0 0x22 0x4>; + status = "okay"; + dr_mode = "host"; + };*/ + + usb2_1: usb2@31880000 { + compatible = "cdns,usb2"; + reg = <0x0 0x31880000 0x0 0x80000>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; + }; + + usb2_2: usb2@31900000 { + compatible = "cdns,usb2"; + reg = <0x0 0x31900000 0x0 0x80000>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; + }; + + usb2@32800000 { + compatible = "cdns,usb2"; + reg = <0x0 0x32800000 0x0 0x40000>; + interrupts = <0x0 0xe 0x4>; + status = "okay"; + dr_mode = "host"; + }; + + usb2@32840000 { + compatible = "cdns,usb2"; + reg = <0x0 0x32840000 0x0 0x40000>; + interrupts = <0x0 0xf 0x4>; + status = "okay"; + dr_mode = "host"; + }; + + dc@32000000 { + compatible = "phytium,dc"; + reg = <0x0 0x32000000 0x0 0x8000>; + interrupts = <0x0 0x2c 0x4>; + status = "okay"; + pipe_mask = [03]; + edp_mask = [00]; + }; + + mhu@32a00000 { + compatible = "arm,mhu"; + reg = <0x0 0x32a00000 0x0 0x1000>; + interrupts = <0x0 0x16 0x4 0x0 0x15 0x4>; + interrupt-names = "mhu_lpri_rx", "mhu_hpri_rx"; + #mbox-cells = <0x1>; + clocks = <0x12>; + clock-names = "apb_pclk"; + phandle = <0x2>; + status = "disabled"; + }; + + rng@32a36000 { + compatible = "phytium,rng"; + reg = <0x0 0x32a36000 0x0 0x1000>; + status = "disabled"; + }; + + sram@32a10000 { + compatible = "phytium,e2000-sram-ns", "mmio-sram"; + reg = <0x0 0x32a10000 0x0 0x2000>; + #address-cells = <0x1>; + #size-cells = <0x1>; + ranges = <0x0 0x0 0x32a10000 0x2000>; + + scp-shmem@0 { + compatible = "arm,scmi-shmem"; + reg = <0x1000 0x400>; + phandle = <0x4>; + }; + + scp-shmem@1 { + compatible = "arm,scmi-shmem"; + reg = <0x1400 0x400>; + phandle = <0x3>; + }; + }; + + spinlock@32b36000 { + compatible = "phytium,hwspinlock"; + reg = <0x0 0x32b36000 0x0 0x1000>; + #hwlock-cells = <0x1>; + nr-locks = <0x20>; + status = "disabled"; + }; + + pcie@40000000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + #address-cells = <0x3>; + #size-cells = <0x2>; + #interrupt-cells = <0x1>; + reg = <0x0 0x40000000 0x0 0x10000000>; + msi-parent = <0xe>; + bus-range = <0x0 0xff>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x4 0x4 0x0 0x0 0x0 0x2 0x1 0x0 0x0 0x0 0x5 0x4 0x0 0x0 0x0 0x3 0x1 0x0 0x0 0x0 0x6 0x4 0x0 0x0 0x0 0x4 0x1 0x0 0x0 0x0 0x7 0x4>; + ranges = <0x1000000 0x0 0x0 0x0 0x50000000 0x0 0xf00000 0x2000000 0x0 0x58000000 0x0 0x58000000 0x0 0x28000000 0x3000000 0x10 0x0 0x10 0x0 0x10 0x0>; + status = "okay"; + }; + + hda@28006000 { + compatible = "phytium,hda"; + reg = <0x0 0x28006000 0x0 0x1000>; + interrupts = <0x0 0x4e 0x4>; + status = "disabled"; + }; + + i2s@28009000 { + compatible = "phytium,i2s"; + reg = <0x0 0x28009000 0x0 0x1000 0x0 0x28005000 0x0 0x1000>; + interrupts = <0x0 0x4d 0x4>; + clocks = <0xf>; + clock-names = "i2s_clk"; + status = "disabled"; + }; + + can@2800a000 { + compatible = "phytium,canfd"; + reg = <0x0 0x2800a000 0x0 0x1000>; + interrupts = <0x0 0x51 0x4>; + clocks = <0x10>; + clock-names = "can_clk"; + tx-fifo-depth = <0x40>; + rx-fifo-depth = <0x40>; + status = "okay"; + }; + + can@2800b000 { + compatible = "phytium,canfd"; + reg = <0x0 0x2800b000 0x0 0x1000>; + interrupts = <0x0 0x52 0x4>; + clocks = <0x10>; + clock-names = "can_clk"; + tx-fifo-depth = <0x40>; + rx-fifo-depth = <0x40>; + status = "okay"; + }; + + keypad@2807a000 { + compatible = "phytium,keypad"; + reg = <0x0 0x2807a000 0x0 0x1000>; + interrupts = <0x0 0xbd 0x4>; + clocks = <0xc>; + status = "disabled"; + }; + + usb3@31a08000 { + compatible = "generic-xhci"; + reg = <0x0 0x31a08000 0x0 0x18000>; + interrupts = <0x0 0x10 0x4>; + status = "okay"; + }; + + usb3@31a28000 { + compatible = "generic-xhci"; + reg = <0x0 0x31a28000 0x0 0x18000>; + interrupts = <0x0 0x11 0x4>; + status = "okay"; + }; + + sata@31a40000 { + compatible = "generic-ahci"; + reg = <0x0 0x31a40000 0x0 0x1000>; + interrupts = <0x0 0x2a 0x4>; + status = "okay"; + }; + + sata@32014000 { + compatible = "generic-ahci"; + reg = <0x0 0x32014000 0x0 0x1000>; + interrupts = <0x0 0x2b 0x4>; + status = "disabled"; + }; + + + ethernet@3200c000 { + compatible = "cdns,phytium-gem"; + reg = <0x0 0x3200c000 0x0 0x2000>; + interrupts = <0x0 0x37 0x4 0x0 0x38 0x4 0x0 0x39 0x4 0x0 0x3a 0x4 0x0 0x1c 0x4 0x0 0x1d 0x4 0x0 0x1e 0x4 0x0 0x1f 0x4>; + clock-names = "pclk", "hclk", "tx_clk", "tsu_clk"; + clocks = <0x11 0x12 0x12 0x11>; + magic-packet; + support-tsn; + status = "okay"; + phy-mode = "sgmii"; + use-mii; + }; + + ethernet@3200e000 { + compatible = "cdns,phytium-gem"; + reg = <0x0 0x3200e000 0x0 0x2000>; + interrupts = <0x0 0x3b 0x4 0x0 0x3c 0x4 0x0 0x3d 0x4 0x0 0x3e 0x4>; + clock-names = "pclk", "hclk", "tx_clk", "tsu_clk"; + clocks = <0x11 0x12 0x12 0x11>; + magic-packet; + status = "okay"; + phy-mode = "sgmii"; + use-mii; + }; + + ethernet@32010000 { + compatible = "cdns,phytium-gem"; + reg = <0x0 0x32010000 0x0 0x2000>; + interrupts = <0x0 0x40 0x4 0x0 0x41 0x4 0x0 0x42 0x4 0x0 0x43 0x4>; + clock-names = "pclk", "hclk", "tx_clk", "tsu_clk"; + clocks = <0x11 0x12 0x12 0x11>; + magic-packet; + status = "okay"; + phy-mode = "rgmii"; + use-mii; + }; + + ethernet@32012000 { + compatible = "cdns,phytium-gem"; + reg = <0x0 0x32012000 0x0 0x2000>; + interrupts = <0x0 0x44 0x4 0x0 0x45 0x4 0x0 0x46 0x4 0x0 0x47 0x4>; + clock-names = "pclk", "hclk", "tx_clk", "tsu_clk"; + clocks = <0x11 0x12 0x12 0x11>; + magic-packet; + status = "okay"; + phy-mode = "rgmii"; + use-mii; + }; + + vpu@32b00000 { + compatible = "phytium,vpu"; + reg = <0x0 0x32b00000 0x0 0x20000>; + interrupts = <0x0 0xc 0x4>; + status = "disabled"; + }; + + uart@2801a000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x2801a000 0x0 0x1000>; + interrupts = <0x0 0x5f 0x4>; + clocks = <0xc 0xc>; + clock-names = "uartclk", "apb_pclk"; + status = "okay"; + }; + + uart@28024000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x28024000 0x0 0x1000>; + interrupts = <0x0 0x64 0x4>; + clocks = <0xc 0xc>; + clock-names = "uartclk", "apb_pclk"; + status = "okay"; + }; + + uart@28028000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x28028000 0x0 0x1000>; + interrupts = <0x0 0x66 0x4>; + clocks = <0xc 0xc>; + clock-names = "uartclk", "apb_pclk"; + status = "okay"; + }; + + uart@28030000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x28030000 0x0 0x1000>; + interrupts = <0x0 0x6a 0x4>; + clocks = <0xc 0xc>; + clock-names = "uartclk", "apb_pclk"; + status = "okay"; + }; + + uart@28032000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x28032000 0x0 0x1000>; + interrupts = <0x0 0x6b 0x4>; + clocks = <0xc 0xc>; + clock-names = "uartclk", "apb_pclk"; + status = "okay"; + }; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + memory@00 { + device_type = "memory"; + reg = <0x0 0x80000000 0x2 0x0>; + }; +}; diff --git a/configs/arm64/dts/phytium/ft2004-AMA0-ivshmem.dts b/configs/arm64/dts/ft2004-AMA0-ivshmem.dts similarity index 100% rename from configs/arm64/dts/phytium/ft2004-AMA0-ivshmem.dts rename to configs/arm64/dts/ft2004-AMA0-ivshmem.dts diff --git a/configs/arm64/dts/phytium/ft2004-AMA0-uart.dts b/configs/arm64/dts/ft2004-AMA0-uart.dts similarity index 100% rename from configs/arm64/dts/phytium/ft2004-AMA0-uart.dts rename to configs/arm64/dts/ft2004-AMA0-uart.dts diff --git a/configs/arm64/dts/phytium/ft2004-AMA0.dts b/configs/arm64/dts/ft2004-AMA0.dts similarity index 100% rename from configs/arm64/dts/phytium/ft2004-AMA0.dts rename to configs/arm64/dts/ft2004-AMA0.dts diff --git a/configs/arm64/dts/phytium/ft2004-AMA1-ivshmem.dts b/configs/arm64/dts/ft2004-AMA1-ivshmem.dts similarity index 100% rename from configs/arm64/dts/phytium/ft2004-AMA1-ivshmem.dts rename to configs/arm64/dts/ft2004-AMA1-ivshmem.dts diff --git a/configs/arm64/dts/phytium/ft2004-AMA1-uart.dts b/configs/arm64/dts/ft2004-AMA1-uart.dts similarity index 100% rename from configs/arm64/dts/phytium/ft2004-AMA1-uart.dts rename to configs/arm64/dts/ft2004-AMA1-uart.dts diff --git a/configs/arm64/dts/phytium/ft2004-guest-eth.dts b/configs/arm64/dts/ft2004-guest-eth.dts similarity index 100% rename from configs/arm64/dts/phytium/ft2004-guest-eth.dts rename to configs/arm64/dts/ft2004-guest-eth.dts diff --git a/configs/arm64/dts/phytium/ft2004-main-eth.dts b/configs/arm64/dts/ft2004-main-eth.dts similarity index 100% rename from configs/arm64/dts/phytium/ft2004-main-eth.dts rename to configs/arm64/dts/ft2004-main-eth.dts diff --git a/configs/arm64/dts/phytium/ft2004.dts b/configs/arm64/dts/ft2004.dts similarity index 100% rename from configs/arm64/dts/phytium/ft2004.dts rename to configs/arm64/dts/ft2004.dts diff --git a/configs/arm64/dts/phytium/ftd2000-AMA0.dts b/configs/arm64/dts/ftd2000-AMA0.dts similarity index 100% rename from configs/arm64/dts/phytium/ftd2000-AMA0.dts rename to configs/arm64/dts/ftd2000-AMA0.dts diff --git a/configs/arm64/dts/phytium/ftd2000-AMA1.dts b/configs/arm64/dts/ftd2000-AMA1.dts similarity index 100% rename from configs/arm64/dts/phytium/ftd2000-AMA1.dts rename to configs/arm64/dts/ftd2000-AMA1.dts diff --git a/configs/arm64/e2000-guest-demo.c b/configs/arm64/e2000-guest-demo.c new file mode 100644 index 00000000..e65a6653 --- /dev/null +++ b/configs/arm64/e2000-guest-demo.c @@ -0,0 +1,128 @@ +/** + * Jailhouse, a Linux-based partitioning hypervisor + * + * Copyright (C), 2022, Kylinsoft Corporation. + * + * @author zhangyunfei@kylinos.cn + * @date 2022.08.05 + * @brief + * @note + */ + +#include <jailhouse/types.h> +#include <jailhouse/cell-config.h> + +struct { + struct jailhouse_cell_desc cell; + __u64 cpus[1]; + struct jailhouse_memory mem_regions[8]; + struct jailhouse_irqchip irqchips[1]; + struct jailhouse_pci_device pci_devices[1]; +} __attribute__((packed)) config = { + .cell = { + .signature = JAILHOUSE_CELL_DESC_SIGNATURE, + .revision = JAILHOUSE_CONFIG_REVISION, + .name = "e2000-guest-demo", + .flags = JAILHOUSE_CELL_PASSIVE_COMMREG, + + .cpu_set_size = sizeof(config.cpus), + .num_memory_regions = ARRAY_SIZE(config.mem_regions), + .num_irqchips = ARRAY_SIZE(config.irqchips), + .num_pci_devices = ARRAY_SIZE(config.pci_devices), + .vpci_irq_base = 102, + + .console = { + .address = 0x2800d000, + .type = JAILHOUSE_CON_TYPE_PL011, + .flags = JAILHOUSE_CON_ACCESS_MMIO | + JAILHOUSE_CON_REGDIST_4, + }, + }, + + .cpus = { + 0x2, + }, + + .irqchips = { + { + .address = 0x30800000, + .pin_base = 32, + .pin_bitmap = { + 0, + 0, + 1 << (116-96), + 1 << (102 + 32 - 128), + }, + }, + }, + + .mem_regions = { + /* IVSHMEM shared memory regions */ + { + .phys_start = 0xa7000000, + .virt_start = 0xa7000000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0xa7001000, + .virt_start = 0xa7001000, + .size = 0x9000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0xa700a000, + .virt_start = 0xa700a000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0xa700c000, + .virt_start = 0xa700c000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0xa700e000, + .virt_start = 0xa700e000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED, + }, + + + /* UART */{ + .phys_start = 0x2800d000, + .virt_start = 0x2800d000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED, + }, + /* RAM */ { + .phys_start = 0x92000000, + .virt_start = 0, + .size = 0x08000000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE, + }, + /* communication region */{ + .virt_start = 0x80000000, + .size = 0x00001000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_COMM_REGION, + }, + }, + + .pci_devices = { + { + .type = JAILHOUSE_PCI_TYPE_IVSHMEM, + .domain = 1, + .bdf = 0 << 3, + .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_INTX, + .shmem_regions_start = 0, + .shmem_dev_id = 1, + .shmem_peers = 3, + .shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED, + }, + }, + +}; diff --git a/configs/arm64/e2000-linux-demo.c b/configs/arm64/e2000-linux-demo.c new file mode 100644 index 00000000..64a3c9df --- /dev/null +++ b/configs/arm64/e2000-linux-demo.c @@ -0,0 +1,149 @@ +/** + * Jailhouse, a Linux-based partitioning hypervisor + * + * Copyright (C), 2022, Kylinsoft Corporation. + * + * @author zhangyunfei@kylinos.cn + * @date 2022.08.05 + * @brief + * @note + */ + +#include <jailhouse/types.h> +#include <jailhouse/cell-config.h> + +struct { + struct jailhouse_cell_desc cell; + __u64 cpus[1]; + struct jailhouse_memory mem_regions[9]; + struct jailhouse_irqchip irqchips[2]; + struct jailhouse_pci_device pci_devices[1]; +} __attribute__((packed)) config = { + .cell = { + .signature = JAILHOUSE_CELL_DESC_SIGNATURE, + .revision = JAILHOUSE_CONFIG_REVISION, + .name = "e2000-linux-demo", + .flags = JAILHOUSE_CELL_PASSIVE_COMMREG, + + .cpu_set_size = sizeof(config.cpus), + .num_memory_regions = ARRAY_SIZE(config.mem_regions), + .num_irqchips = ARRAY_SIZE(config.irqchips), + .num_pci_devices = ARRAY_SIZE(config.pci_devices), + .vpci_irq_base = 102, + + .console = { + .address = 0x2800d000, + .type = JAILHOUSE_CON_TYPE_PL011, + .flags = JAILHOUSE_CON_ACCESS_MMIO | + JAILHOUSE_CON_REGDIST_4, + }, + }, + + .cpus = { + 0x3, + }, + + .mem_regions = { + /* IVSHMEM shared memory regions */ + { + .phys_start = 0xa7000000, + .virt_start = 0xa7000000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0xa7001000, + .virt_start = 0xa7001000, + .size = 0x9000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0xa700a000, + .virt_start = 0xa700a000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0xa700c000, + .virt_start = 0xa700c000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0xa700e000, + .virt_start = 0xa700e000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED, + }, + /* UART */{ + .phys_start = 0x2800d000, + .virt_start = 0x2800d000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED, + }, + + /* RAM */ { + .phys_start = 0x92000000, + .virt_start = 0, + .size = 0x5000000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE, + }, + { + .phys_start = 0x93000000, + .virt_start = 0x93000000, + .size = 0x14000000, + .flags= JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE | + JAILHOUSE_MEM_DMA, + + + }, + /* communication region */ { + .virt_start = 0x80000000, + .size = 0x00001000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_COMM_REGION, + }, + }, + + .irqchips = { + /* GIC */ { + .address = 0x30800000, + .pin_base = 32, + .pin_bitmap = { + 0, + 0, + 1 << (116-96), + 1 << (102 + 32 - 128), + }, + }, + { + .address = 0x30800000, + .pin_base = 256, + .pin_bitmap = { + 0, + 1 << (268+32-288), + 0, + 0, + }, + }, + }, + + + .pci_devices = { + { + .type = JAILHOUSE_PCI_TYPE_IVSHMEM, + .domain = 1, + .bdf = 0 << 3, + .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_INTX, + .shmem_regions_start = 0, + .shmem_dev_id = 1, + .shmem_peers = 3, + .shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED, + }, + }, + + +}; diff --git a/configs/arm64/e2000-rtos-32-uart2.c b/configs/arm64/e2000-rtos-32-uart2.c new file mode 100644 index 00000000..895a838e --- /dev/null +++ b/configs/arm64/e2000-rtos-32-uart2.c @@ -0,0 +1,190 @@ +/** + * JAILHOUSE, a Linux-based partitioning hypervisor + * + * Copyright (C), 2022, Kylinsoft Corporation. + * + * @author zhangyunfei@kylinos.cn + * @date 2022.09.22 + * @brief + * @note + */ + +#include <jailhouse/types.h> +#include <jailhouse/cell-config.h> + +struct { + struct jailhouse_cell_desc cell; + __u64 cpus[1]; + struct jailhouse_memory mem_regions[17]; + struct jailhouse_irqchip irqchips[2]; + struct jailhouse_pci_device pci_devices[1]; +} __attribute__((packed)) config = { + .cell = { + .signature = JAILHOUSE_CELL_DESC_SIGNATURE, + .revision = JAILHOUSE_CONFIG_REVISION, + .name = "e2000-rtos-demo", + .flags = JAILHOUSE_CELL_PASSIVE_COMMREG|JAILHOUSE_CELL_AARCH32, + + .cpu_set_size = sizeof(config.cpus), + .cpu_reset_address = 0x80100000, + .num_memory_regions = ARRAY_SIZE(config.mem_regions), + .num_irqchips = ARRAY_SIZE(config.irqchips), + .num_pci_devices = ARRAY_SIZE(config.pci_devices), + .vpci_irq_base = 100, + + .console = { + .address = 0x2800e000, + .type = JAILHOUSE_CON_TYPE_PL011, + .flags = JAILHOUSE_CON_ACCESS_MMIO | + JAILHOUSE_CON_REGDIST_4, + }, + }, + + .cpus = { + 0x4, + }, + + .irqchips = { + { + .address = 0x30800000, + .pin_base = 32, + .pin_bitmap = { + 0,//32 + 0,//64 + 1 << (117-96),//96 + (1 << (102 + 32 - 128))|(1 << (100 + 32 - 128)), + }, + }, + { + .address = 0x30800000, + .pin_base = 160, + .pin_bitmap = { + 1<<(173-160)|1<<(172-160), + 0,//192 + 0, + 0, + }, + }, + }, + + .mem_regions = { + /* IVSHMEM shared memory regions */ + { + .phys_start = 0xa7000000, + .virt_start = 0xa7000000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED, + },//state + { + .phys_start = 0xa7001000, + .virt_start = 0xa7001000, + .size = 0x9000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_ROOTSHARED, + }, //rw + { + .phys_start = 0xa700a000, + .virt_start = 0xa700a000, + .size = 0x200000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED, + },//section0 + { + .phys_start = 0xa720a000, + .virt_start = 0xa720a000, + .size = 0x200000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_ROOTSHARED, + },//section1 + { + .phys_start = 0xa740a000, + .virt_start = 0xa740a000, + .size = 0x200000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED, + },//seciton2 + /* UART1 */ + { + .phys_start = 0x2800d000, + .virt_start = 0x2800d000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED, + }, + + /* UART 2*/{ + .phys_start = 0x2800E000, + .virt_start = 0x2800E000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED, + }, + /* mio10 */{ + .phys_start = 0x28028000, + .virt_start = 0x28028000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED, + }, + /* gpio2 */{ + .phys_start = 0x28036000, + .virt_start = 0x28036000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED, + }, + /* gpio3 */{ + .phys_start = 0x28037000, + .virt_start = 0x28037000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED, + }, + /* gpio5 */{ + .phys_start = 0x28039000, + .virt_start = 0x28039000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED, + }, + /* gpio mux */{ + .phys_start = 0x32b30000, + .virt_start = 0x32b30000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED, + }, + /* inttrupt */{ + .phys_start = 0x30806000, + .virt_start = 0x30806000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED, + }, + /* RAM */ { + .phys_start = 0x92000000, + .virt_start = 0x80100000, + .size = 0x06000000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE, + }, + /* RAM */ { + .phys_start = 0x98000000, + .virt_start = 0x0, + .size = 0x02000000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE, + }, + /* communication region */{ + .virt_start = 0x80000000, + .size = 0x00001000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_COMM_REGION, }, + }, + .pci_devices = { + { + .type = JAILHOUSE_PCI_TYPE_IVSHMEM, + .domain = 1, + .bdf = 0 << 3, + .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_INTX, + .shmem_regions_start = 0, + .shmem_dev_id = 1, + .shmem_peers = 3, + .shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED, + }, + }, +}; diff --git a/configs/arm64/e2000-rtos32-demo.c b/configs/arm64/e2000-rtos32-demo.c new file mode 100644 index 00000000..8e21ccea --- /dev/null +++ b/configs/arm64/e2000-rtos32-demo.c @@ -0,0 +1,129 @@ +/** + * JAILHOUSE, a Linux-based partitioning hypervisor + * + * Copyright (C), 2022, Kylinsoft Corporation. + * + * @author zhangyunfei@kylinos.cn + * @date 2022.08.05 + * @brief + * @note + */ + +#include <jailhouse/types.h> +#include <jailhouse/cell-config.h> + +struct { + struct jailhouse_cell_desc cell; + __u64 cpus[1]; + struct jailhouse_memory mem_regions[8]; + struct jailhouse_irqchip irqchips[1]; + struct jailhouse_pci_device pci_devices[1]; +} __attribute__((packed)) config = { + .cell = { + .signature = JAILHOUSE_CELL_DESC_SIGNATURE, + .revision = JAILHOUSE_CONFIG_REVISION, + .name = "e2000-rtos-demo", + .flags = JAILHOUSE_CELL_PASSIVE_COMMREG | JAILHOUSE_CELL_AARCH32, + + .cpu_set_size = sizeof(config.cpus), + .cpu_reset_address = 0x80100000, + .num_memory_regions = ARRAY_SIZE(config.mem_regions), + .num_irqchips = ARRAY_SIZE(config.irqchips), + .num_pci_devices = ARRAY_SIZE(config.pci_devices), + .vpci_irq_base = 102, + + .console = { + .address = 0x2800d000, + .type = JAILHOUSE_CON_TYPE_PL011, + .flags = JAILHOUSE_CON_ACCESS_MMIO | + JAILHOUSE_CON_REGDIST_4, + }, + }, + + .cpus = { + 0x1, + }, + + .irqchips = { + { + .address = 0x30800000, + .pin_base = 32, + .pin_bitmap = { + 0, + 0, + 1 << (116-96), + 1 << (102 + 32 - 128), + }, + }, + }, + + .mem_regions = { + /* IVSHMEM shared memory regions */ + { + .phys_start = 0xa7000000, + .virt_start = 0xa7000000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0xa7001000, + .virt_start = 0xa7001000, + .size = 0x9000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0xa700a000, + .virt_start = 0xa700a000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0xa700c000, + .virt_start = 0xa700c000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0xa700e000, + .virt_start = 0xa700e000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED, + }, + /* UART */ + { + .phys_start = 0x2800d000, + .virt_start = 0x2800d000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED, + }, + /* RAM */ + { + .phys_start = 0x92000000, + .virt_start = 0x80100000, + .size = 0x10000000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE, + }, + /* communication region */ + { + .virt_start = 0x80000000, + .size = 0x00001000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_COMM_REGION, + }, + }, + + .pci_devices = { + { + .type = JAILHOUSE_PCI_TYPE_IVSHMEM, + .domain = 1, + .bdf = 0 << 3, + .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_INTX, + .shmem_regions_start = 0, + .shmem_dev_id = 1, + .shmem_peers = 3, + .shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED, + }, + }, +}; diff --git a/configs/arm64/e2000q-dev.c b/configs/arm64/e2000q-dev.c new file mode 100644 index 00000000..43fba26e --- /dev/null +++ b/configs/arm64/e2000q-dev.c @@ -0,0 +1,333 @@ +/** + * Kvisor, a Linux-based partitioning hypervisor + * + * Copyright (C), 2022, Kylinsoft Corporation. + * + * @author zhangyunfei@kylinos.cn + * @date 2022.08.05 + * @brief + * @note + */ + +#include <jailhouse/types.h> +#include <jailhouse/cell-config.h> + +struct { + struct jailhouse_system header; + __u64 cpus[1]; + struct jailhouse_memory mem_regions[30]; + struct jailhouse_irqchip irqchips[2]; + struct jailhouse_pci_device pci_devices[1]; +} __attribute__((packed)) config = { + .header = { + .signature = JAILHOUSE_SYSTEM_SIGNATURE, + .revision = JAILHOUSE_CONFIG_REVISION, + .flags = JAILHOUSE_SYS_VIRTUAL_DEBUG_CONSOLE, + .hypervisor_memory = { + .phys_start = 0x90000000, + .size = 0x01000000, + }, + .debug_console = { + .address = 0x2800d000, + .size = 0x1000, + .type = JAILHOUSE_CON_TYPE_PL011, + .flags = JAILHOUSE_CON_ACCESS_MMIO | + JAILHOUSE_CON_REGDIST_4, + }, + .platform_info = { + .pci_mmconfig_base = 0x30000000, + .pci_mmconfig_end_bus = 0, + .pci_is_virtual = 1, + .pci_domain = 1, + + .arm = { + .gic_version = 3, + .gicd_base = 0x30800000, + .gicr_base = 0x30880000, + .gicc_base = 0x30840000, + .gich_base = 0x30850000, + .gicv_base = 0x30860000, + .maintenance_irq = 25, + }, + }, + .root_cell = { + .name = "e2000", + + .cpu_set_size = sizeof(config.cpus), + .num_memory_regions = ARRAY_SIZE(config.mem_regions), + .num_irqchips = ARRAY_SIZE(config.irqchips), + .num_pci_devices = ARRAY_SIZE(config.pci_devices), + .vpci_irq_base = 101, + }, + }, + + .cpus = { + 0xf, + }, + + .mem_regions = { + /* IVSHMEM shared memory regions */ + { + .phys_start = 0xa7000000, + .virt_start = 0xa7000000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ, + }, + { + .phys_start = 0xa7001000, + .virt_start = 0xa7001000, + .size = 0x9000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE, + }, + { + .phys_start = 0xa700a000, + .virt_start = 0xa700a000, + .size = 0x200000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE, + },//section0 + { + .phys_start = 0xa720a000, + .virt_start = 0xa720a000, + .size = 0x200000, + .flags = JAILHOUSE_MEM_READ, + },//section1 + { + .phys_start = 0xa740a000, + .virt_start = 0xa740a000, + .size = 0x200000, + .flags = JAILHOUSE_MEM_READ, + },//seciton2 + + /* Main memory */ + { + .phys_start = 0x80000000, + .virt_start = 0x80000000, + .size = 0x80000000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_EXECUTE, + }, + /* Main memory*/ + { + .phys_start = 0x2000000000, + .virt_start = 0x2000000000, + .size = 0x80000000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_EXECUTE, + }, + /* UART 0-3 */ + { + .phys_start = 0x2800c000, + .virt_start = 0x2800c000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + { + .phys_start = 0x2800d000, + .virt_start = 0x2800d000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + { + .phys_start = 0x2800e000, + .virt_start = 0x2800e000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* GPIO 0-5 */ + { + .phys_start = 0x28034000, + .virt_start = 0x28034000, + .size = 0x6000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* I2C 0-3 */ + /* Watchdog 0 */ + { + .phys_start = 0x28040000, + .virt_start = 0x28040000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* Watchdog 1 */ + { + .phys_start = 0x28042000, + .virt_start = 0x28042000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /*Usb2 0-4*/ + { + .phys_start = 0x31808000, + .virt_start = 0x31808000, + .size = 0x280000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /*Usb3 0-1*/ + { + .phys_start = 0x31a08000, + .virt_start = 0x31a08000, + .size = 0x30000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /*sata 0*/ + { + .phys_start = 0x31a40000, + .virt_start = 0x31a40000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /*sata 1*/ + { + .phys_start = 0x32014000, + .virt_start = 0x32014000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /*vpu*/ + { + .phys_start = 0x32b00000, + .virt_start = 0x32b00000, + .size = 0x20000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* SPI 0-3 */ + { + .phys_start = 0x2803a000, + .virt_start = 0x2803a000, + .size = 0x4000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* QSPI */ + { + .phys_start = 0x28008000, + .virt_start = 0x28008000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* HDA */ + { + .phys_start = 0x28006000, + .virt_start = 0x28006000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* CAN 0-2 and SDCI*/ + { + .phys_start = 0x2800a000, + .virt_start = 0x2800a000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* ETH 0-3 */ + { + .phys_start = 0x3200c000, + .virt_start = 0x3200c000, + .size = 0x8000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + { + .phys_start = 0x32000000, + .virt_start = 0x32000000, + .size = 0x8000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* Mailbox */ + /* SRAM */ + { + .phys_start = 0x32a10000, + .virt_start = 0x32a10000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* GIC ITS */ + { + .phys_start = 0x30820000, + .virt_start = 0x30820000, + .size = 0x20000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* PCIe ECAM */ + { + .phys_start = 0x40000000, + .virt_start = 0x40000000, + .size = 0x10000000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* PCIe IO */ + { + .phys_start = 0x50000000, + .virt_start = 0x50000000, + .size = 0x8000000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* PCIe Mem32 */ + { + .phys_start = 0x58000000, + .virt_start = 0x58000000, + .size = 0x28000000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* PCIe Mem64 */ + { + .phys_start = 0x1000000000, + .virt_start = 0x1000000000, + .size = 0x1000000000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + }, + + .irqchips = { + /* GIC */ + { + .address = 0x30800000, + .pin_base = 32, + .pin_bitmap = { + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + }, + }, + { + .address = 0x30800000, + .pin_base = 160, + .pin_bitmap = { + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + }, + }, + }, + + .pci_devices = { + { + .type = JAILHOUSE_PCI_TYPE_IVSHMEM, + .domain = 1, + .bdf = 0 << 3, + .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_INTX, + .shmem_regions_start = 0, + .shmem_dev_id = 0, + .shmem_peers = 3, + .shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED, + }, + }, + +}; diff --git a/configs/arm64/phytium/ft2004-inmate-eth.c b/configs/arm64/ft2004-inmate-eth.c similarity index 100% rename from configs/arm64/phytium/ft2004-inmate-eth.c rename to configs/arm64/ft2004-inmate-eth.c diff --git a/configs/arm64/phytium/ft2004-inmate-ivshmem.c b/configs/arm64/ft2004-inmate-ivshmem.c similarity index 100% rename from configs/arm64/phytium/ft2004-inmate-ivshmem.c rename to configs/arm64/ft2004-inmate-ivshmem.c diff --git a/configs/arm64/phytium/ft2004-inmate.c b/configs/arm64/ft2004-inmate.c similarity index 100% rename from configs/arm64/phytium/ft2004-inmate.c rename to configs/arm64/ft2004-inmate.c diff --git a/configs/arm64/phytium/ft2004-main-eth.c b/configs/arm64/ft2004-main-eth.c similarity index 100% rename from configs/arm64/phytium/ft2004-main-eth.c rename to configs/arm64/ft2004-main-eth.c diff --git a/configs/arm64/phytium/ft2004-main-ivshmem.c b/configs/arm64/ft2004-main-ivshmem.c similarity index 100% rename from configs/arm64/phytium/ft2004-main-ivshmem.c rename to configs/arm64/ft2004-main-ivshmem.c diff --git a/configs/arm64/phytium/ft2004-main.c b/configs/arm64/ft2004-main.c similarity index 100% rename from configs/arm64/phytium/ft2004-main.c rename to configs/arm64/ft2004-main.c -- 2.25.1
Locations
Projects
Search
Status Monitor
Help
Open Build Service
OBS Manuals
API Documentation
OBS Portal
Reporting a Bug
Contact
Mailing List
Forums
Chat (IRC)
Twitter
Open Build Service (OBS)
is an
openSUSE project
.
浙ICP备2022010568号-2