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File _service:obs_scm:0006-add-Phytium-e2000d-cell-configures-and-dts.patch of Package Jailhouse
From d9a896c91519810919ed5e77e3503f095fe305ce Mon Sep 17 00:00:00 2001 From: mashuai <mashuai01@kylinos.cn> Date: Wed, 12 Apr 2023 20:31:30 -0700 Subject: [PATCH 06/12] add Phytium e2000d cell configures and dts [KEYWORDS] jailhouse [TO SOLVE] [TEST SUGGESTION] none [SUBMIT BY] mashuai [REVIEW BY] mashuai [TEST BY] mashuai --- configs/arm64/dts/e2000d-inmate-eth.dts | 171 ++++ configs/arm64/dts/e2000d-main-eth.dts | 1184 +++++++++++++++++++++++ configs/arm64/e2000d-inmate-eth.c | 151 +++ configs/arm64/e2000d-main-eth.c | 371 +++++++ 4 files changed, 1877 insertions(+) create mode 100755 configs/arm64/dts/e2000d-inmate-eth.dts create mode 100755 configs/arm64/dts/e2000d-main-eth.dts create mode 100755 configs/arm64/e2000d-inmate-eth.c create mode 100755 configs/arm64/e2000d-main-eth.c diff --git a/configs/arm64/dts/e2000d-inmate-eth.dts b/configs/arm64/dts/e2000d-inmate-eth.dts new file mode 100755 index 00000000..38a241ef --- /dev/null +++ b/configs/arm64/dts/e2000d-inmate-eth.dts @@ -0,0 +1,171 @@ +/dts-v1/; + +/memreserve/ 0x0000000080000000 0x0000000000010000; +/ { + compatible = "phytium,e2000d"; + interrupt-parent = <0x01>; + #address-cells = <0x02>; + #size-cells = <0x02>; + model = "E2000DS SLT Board"; + + aliases { + serial1 = "/soc/uart@2800d000"; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + cpu_suspend = <0xc4000001>; + cpu_off = <0x84000002>; + cpu_on = <0xc4000003>; + sys_poweroff = <0x84000008>; + sys_reset = <0x84000009>; + }; + + cpus { + #address-cells = <0x02>; + #size-cells = <0x00>; + + cpu-map { + + cluster0 { + + core0 { + cpu = <0x6>; + }; + + + }; + }; + + + cpu@0 { + device_type = "cpu"; + compatible = "phytium,ftc310", "arm,armv8"; + reg = <0x0 0x200>; + enable-method = "psci"; + clocks = <0x8 0x2>; + i-cache-size = <0x8000>; + i-cache-line-size = <0x40>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x40>; + next-level-cache = <0x9>; + phandle = <0x6>; + }; + + }; + interrupt-controller@30800000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <0x3>; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + interrupt-controller; + reg = <0x0 0x30800000 0x0 0x20000 0x0 0x308c0000 0x0 0x80000 0x0 0x30840000 0x0 0x10000 0x0 0x30850000 0x0 0x10000 0x0 0x30860000 0x0 0x10000>; + interrupts = <0x1 0x9 0x8>; + phandle = <0x1>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <0x01 0x0d 0x08 0x01 0x0e 0x08 0x01 0x0b 0x08 0x01 0x0a 0x08>; + clock-frequency = <0x2faf080>; + }; + + clocks { + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + + clk48mhz { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <0x2dc6c00>; + phandle = <0x12>; + }; + + clk50mhz { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <0x2faf080>; + phandle = <0xb>; + }; + + clk100mhz { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <0x5f5e100>; + phandle = <0xc>; + }; + + clk200mhz { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <0xbebc200>; + phandle = <0x10>; + }; + + clk250mhz { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <0xee6b280>; + phandle = <0x11>; + }; + + clk300mhz { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <0x11e1a300>; + }; + + clk600mhz { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <0x23c34600>; + phandle = <0xd>; + }; + + clk1200mhz { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <0x47868c00>; + phandle = <0xa>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <0x02>; + #size-cells = <0x02>; + dma-coherent; + ranges; + + uart@2800d000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x2800d000 0x0 0x1000>; + interrupts = <0x0 0x54 0x4>; + clocks = <0xc 0xc>; + clock-names = "uartclk", "apb_pclk"; + status = "okay"; + }; + + ethernet@3200c000 { + compatible = "phytium,gem", "cdns,phytium-gem"; + reg = <0x0 0x3200c000 0x0 0x2000>; + interrupts = <0x0 0x37 0x4 0x0 0x38 0x4 0x0 0x39 0x4 0x0 0x3a 0x4 0x0 0x1c 0x4 0x0 0x1d 0x4 0x0 0x1e 0x4 0x0 0x1f 0x4>; + clock-names = "pclk", "hclk", "tx_clk", "tsu_clk"; + clocks = <0x11 0x12 0x12 0x11>; + magic-packet; + status = "okay"; + phy-mode = "sgmii"; + use-mii; + }; + + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + +}; diff --git a/configs/arm64/dts/e2000d-main-eth.dts b/configs/arm64/dts/e2000d-main-eth.dts new file mode 100755 index 00000000..64e1e4da --- /dev/null +++ b/configs/arm64/dts/e2000d-main-eth.dts @@ -0,0 +1,1184 @@ +/dts-v1/; + +/memreserve/ 0x0000000080000000 0x0000000000010000; +/ { + compatible = "phytium,e2000d"; + interrupt-parent = <0x1>; + #address-cells = <0x2>; + #size-cells = <0x2>; + model = "E2000DS SLT Board"; + + aliases { + serial0 = "/soc/uart@2800c000"; + serial1 = "/soc/uart@2800d000"; + serial2 = "/soc/uart@2800e000"; + serial3 = "/soc/uart@2800f000"; + ethernet1 = "/soc/ethernet@3200e000"; + ethernet2 = "/soc/ethernet@32010000"; + ethernet3 = "/soc/ethernet@32012000"; + }; + + reserved-memory { + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + + reserved@a0000000 { + reg = <0x0 0xa0000000 0x0 0x10000000>; + no-map; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + cpu_suspend = <0xc4000001>; + cpu_off = <0x84000002>; + cpu_on = <0xc4000003>; + sys_poweroff = <0x84000008>; + sys_reset = <0x84000009>; + }; + + firmware { + + scmi { + compatible = "arm,scmi"; + mboxes = <0x2 0x0 0x2 0x1>; + mbox-names = "tx", "rx"; + shmem = <0x3 0x4>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + protocol@13 { + reg = <0x13>; + #clock-cells = <0x1>; + phandle = <0x8>; + }; + + protocol@15 { + reg = <0x15>; + #thermal-sensor-cells = <0x1>; + phandle = <0x5>; + }; + }; + + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + status = "disabled"; + }; + }; + + thermal-zones { + + sensor0 { + polling-delay-passive = <0x64>; + polling-delay = <0x3e8>; + thermal-sensors = <0x5 0x0>; + }; + + sensor1 { + polling-delay-passive = <0x64>; + polling-delay = <0x3e8>; + thermal-sensors = <0x5 0x1>; + }; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu-map { + + cluster0 { + + core0 { + cpu = <0x6>; + }; + + core1 { + cpu = <0x7>; + }; + }; + }; + + cpu@0 { + device_type = "cpu"; + compatible = "phytium,ftc310", "arm,armv8"; + reg = <0x0 0x200>; + enable-method = "psci"; + clocks = <0x8 0x2>; + i-cache-size = <0x8000>; + i-cache-line-size = <0x40>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x40>; + next-level-cache = <0x9>; + phandle = <0x6>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "phytium,ftc310", "arm,armv8"; + reg = <0x0 0x201>; + enable-method = "psci"; + clocks = <0x8 0x2>; + i-cache-size = <0x8000>; + i-cache-line-size = <0x40>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x40>; + next-level-cache = <0x9>; + phandle = <0x7>; + }; + + l2-cache { + compatible = "cache"; + cache-level = <0x2>; + cache-unified; + cache-size = <0x40000>; + cache-line-size = <0x40>; + cache-sets = <0x10>; + phandle = <0x9>; + }; + }; + + interrupt-controller@30800000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <0x3>; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + interrupt-controller; + reg = <0x0 0x30800000 0x0 0x20000 0x0 0x308c0000 0x0 0x80000 0x0 0x30840000 0x0 0x10000 0x0 0x30850000 0x0 0x10000 0x0 0x30860000 0x0 0x10000>; + interrupts = <0x1 0x9 0x8>; + phandle = <0x1>; + + gic-its@30820000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0x30820000 0x0 0x20000>; + phandle = <0xe>; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0x1 0x7 0x8>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <0x1 0xd 0x8 0x1 0xe 0x8 0x1 0xb 0x8 0x1 0xa 0x8>; + clock-frequency = <0x2faf080>; + }; + + clocks { + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + + clk48mhz { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <0x2dc6c00>; + phandle = <0x12>; + }; + + clk50mhz { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <0x2faf080>; + phandle = <0xb>; + }; + + clk100mhz { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <0x5f5e100>; + phandle = <0xc>; + }; + + clk200mhz { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <0xbebc200>; + phandle = <0x10>; + }; + + clk250mhz { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <0xee6b280>; + phandle = <0x11>; + }; + + clk300mhz { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <0x11e1a300>; + }; + + clk600mhz { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <0x23c34600>; + phandle = <0xd>; + }; + + clk1200mhz { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <0x47868c00>; + phandle = <0xa>; + }; + }; + + iommu@30000000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0x30000000 0x0 0x800000>; + interrupts = <0x0 0xf0 0x1 0x0 0xef 0x1 0x0 0xec 0x1 0x0 0xf2 0x1>; + interrupt-names = "eventq", "priq", "cmdq-sync", "gerror"; + dma-coherent; + #iommu-cells = <0x1>; + phandle = <0xf>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <0x2>; + #size-cells = <0x2>; + dma-coherent; + ranges; + + mmc@28000000 { + compatible = "phytium,mci"; + reg = <0x0 0x28000000 0x0 0x1000>; + interrupts = <0x0 0x48 0x4>; + clocks = <0xa>; + clock-names = "phytium_mci_clk"; + status = "okay"; + bus-width = <0x8>; + max-frequency = <0x2faf080>; + cap-mmc-hw-reset; + cap-mmc-highspeed; + no-sdio; + no-sd; + non-removable; + }; + + mmc@28001000 { + compatible = "phytium,mci"; + reg = <0x0 0x28001000 0x0 0x1000>; + interrupts = <0x0 0x49 0x4>; + clocks = <0xa>; + clock-names = "phytium_mci_clk"; + status = "okay"; + }; + + nand@28002000 { + compatible = "phytium,nfc"; + reg = <0x0 0x28002000 0x0 0x1000>; + interrupts = <0x0 0x4a 0x4>; + status = "disabled"; + }; + + spi@28008000 { + compatible = "phytium,qspi"; + reg = <0x0 0x28008000 0x0 0x1000 0x0 0x0 0x0 0xfffffff>; + reg-names = "qspi", "qspi_mm"; + clocks = <0xb>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "disabled"; + + flash@0 { + reg = <0x0>; + spi-rx-bus-width = <0x1>; + spi-max-frequency = <0x2faf080>; + status = "disabled"; + }; + }; + + uart@2800c000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x2800c000 0x0 0x1000>; + interrupts = <0x0 0x53 0x4>; + clocks = <0xc 0xc>; + clock-names = "uartclk", "apb_pclk"; + status = "okay"; + }; + + uart@2800d000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x2800d000 0x0 0x1000>; + interrupts = <0x0 0x54 0x4>; + clocks = <0xc 0xc>; + clock-names = "uartclk", "apb_pclk"; + status = "okay"; + }; + + uart@2800e000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x2800e000 0x0 0x1000>; + interrupts = <0x0 0x55 0x4>; + clocks = <0xc 0xc>; + clock-names = "uartclk", "apb_pclk"; + status = "okay"; + }; + + uart@2800f000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x2800f000 0x0 0x1000>; + interrupts = <0x0 0x56 0x4>; + clocks = <0xc 0xc>; + clock-names = "uartclk", "apb_pclk"; + status = "okay"; + }; + + lpc@28010000 { + compatible = "simple-mfd", "syscon"; + reg = <0x0 0x28010000 0x0 0x1000>; + reg-io-width = <0x4>; + #address-cells = <0x1>; + #size-cells = <0x1>; + ranges = <0x0 0x0 0x28010000 0x1000>; + + kcs@24 { + compatible = "phytium,e2000-kcs-bmc"; + reg = <0x24 0x1 0x30 0x1 0x3c 0x1>; + interrupts = <0x0 0x58 0x4>; + status = "disabled"; + }; + + kcs@28 { + compatible = "phytium,e2000-kcs-bmc"; + reg = <0x28 0x1 0x34 0x1 0x40 0x1>; + interrupts = <0x0 0x58 0x4>; + status = "disabled"; + }; + + kcs@2c { + compatible = "phytium,e2000-kcs-bmc"; + reg = <0x2c 0x1 0x38 0x1 0x44 0x1>; + interrupts = <0x0 0x58 0x4>; + status = "disabled"; + }; + + kcs@8c { + compatible = "phytium,e2000-kcs-bmc"; + reg = <0x8c 0x1 0x90 0x1 0x94 0x1>; + interrupts = <0x0 0x58 0x4>; + status = "disabled"; + }; + + bt@48 { + compatible = "phytium,e2000-bt-bmc"; + reg = <0x48 0x20>; + interrupts = <0x0 0x58 0x4>; + status = "disabled"; + }; + }; + + gpio@28034000 { + compatible = "phytium,gpio"; + reg = <0x0 0x28034000 0x0 0x1000>; + interrupts = <0x0 0x6c 0x4 0x0 0x6d 0x4 0x0 0x6e 0x4 0x0 0x6f 0x4 0x0 0x70 0x4 0x0 0x71 0x4 0x0 0x72 0x4 0x0 0x73 0x4 0x0 0x74 0x4 0x0 0x75 0x4 0x0 0x76 0x4 0x0 0x77 0x4 0x0 0x78 0x4 0x0 0x79 0x4 0x0 0x7a 0x4 0x0 0x7b 0x4>; + gpio-controller; + #gpio-cells = <0x2>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "okay"; + + porta { + compatible = "phytium,gpio-port"; + reg = <0x0>; + nr-gpios = <0x10>; + }; + }; + + gpio@28035000 { + compatible = "phytium,gpio"; + reg = <0x0 0x28035000 0x0 0x1000>; + interrupts = <0x0 0x7c 0x4 0x0 0x7d 0x4 0x0 0x7e 0x4 0x0 0x7f 0x4 0x0 0x80 0x4 0x0 0x81 0x4 0x0 0x82 0x4 0x0 0x83 0x4 0x0 0x84 0x4 0x0 0x85 0x4 0x0 0x86 0x4 0x0 0x87 0x4 0x0 0x88 0x4 0x0 0x89 0x4 0x0 0x8a 0x4 0x0 0x8b 0x4>; + gpio-controller; + #gpio-cells = <0x2>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "okay"; + + porta { + compatible = "phytium,gpio-port"; + reg = <0x0>; + nr-gpios = <0x10>; + }; + }; + + gpio@28036000 { + compatible = "phytium,gpio"; + reg = <0x0 0x28036000 0x0 0x1000>; + interrupts = <0x0 0x8c 0x4 0x0 0x8d 0x4 0x0 0x8e 0x4 0x0 0x8f 0x4 0x0 0x90 0x4 0x0 0x91 0x4 0x0 0x92 0x4 0x0 0x93 0x4 0x0 0x94 0x4 0x0 0x95 0x4 0x0 0x96 0x4 0x0 0x97 0x4 0x0 0x98 0x4 0x0 0x99 0x4 0x0 0x9a 0x4 0x0 0x9b 0x4>; + gpio-controller; + #gpio-cells = <0x2>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "okay"; + + porta { + compatible = "phytium,gpio-port"; + reg = <0x0>; + nr-gpios = <0x10>; + }; + }; + + gpio@28037000 { + compatible = "phytium,gpio"; + reg = <0x0 0x28037000 0x0 0x1000>; + interrupts = <0x0 0x9c 0x4>; + gpio-controller; + #gpio-cells = <0x2>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "okay"; + + porta { + compatible = "phytium,gpio-port"; + reg = <0x0>; + nr-gpios = <0x10>; + }; + }; + + gpio@28038000 { + compatible = "phytium,gpio"; + reg = <0x0 0x28038000 0x0 0x1000>; + interrupts = <0x0 0x9d 0x4>; + gpio-controller; + #gpio-cells = <0x2>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "okay"; + + porta { + compatible = "phytium,gpio-port"; + reg = <0x0>; + nr-gpios = <0x10>; + }; + }; + + gpio@28039000 { + compatible = "phytium,gpio"; + reg = <0x0 0x28039000 0x0 0x1000>; + interrupts = <0x0 0x9e 0x4>; + gpio-controller; + #gpio-cells = <0x2>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "okay"; + + porta { + compatible = "phytium,gpio-port"; + reg = <0x0>; + nr-gpios = <0x10>; + }; + }; + + spi@2803a000 { + compatible = "phytium,spi"; + reg = <0x0 0x2803a000 0x0 0x1000>; + interrupts = <0x0 0x9f 0x4>; + clocks = <0xb>; + num-cs = <0x4>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "okay"; + }; + + spi@2803b000 { + compatible = "phytium,spi"; + reg = <0x0 0x2803b000 0x0 0x1000>; + interrupts = <0x0 0xa0 0x4>; + clocks = <0xb>; + num-cs = <0x4>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "disabled"; + }; + + spi@2803c000 { + compatible = "phytium,spi"; + reg = <0x0 0x2803c000 0x0 0x1000>; + interrupts = <0x0 0xa1 0x4>; + clocks = <0xb>; + num-cs = <0x4>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "disabled"; + }; + + spi@2803d000 { + compatible = "phytium,spi"; + reg = <0x0 0x2803d000 0x0 0x1000>; + interrupts = <0x0 0xa2 0x4>; + clocks = <0xb>; + num-cs = <0x4>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "disabled"; + }; + + watchdog@28040000 { + compatible = "arm,sbsa-gwdt"; + reg = <0x0 0x28041000 0x0 0x1000 0x0 0x28040000 0x0 0x1000>; + interrupts = <0x0 0xa4 0x4>; + timeout-sec = <0x1e>; + status = "disabled"; + }; + + watchdog@28042000 { + compatible = "arm,sbsa-gwdt"; + reg = <0x0 0x28043000 0x0 0x1000 0x0 0x28042000 0x0 0x1000>; + interrupts = <0x0 0xa5 0x4>; + timeout-sec = <0x1e>; + status = "disabled"; + }; + + pwm@2804a000 { + compatible = "phytium,pwm"; + reg = <0x0 0x2804a000 0x0 0x1000>; + interrupts = <0x0 0xad 0x4>; + clocks = <0xb>; + status = "disabled"; + }; + + pwm@2804b000 { + compatible = "phytium,pwm"; + reg = <0x0 0x2804b000 0x0 0x1000>; + interrupts = <0x0 0xae 0x4>; + clocks = <0xb>; + status = "disabled"; + }; + + tacho@28054000 { + compatible = "phytium,tacho"; + reg = <0x0 0x28054000 0x0 0x1000>; + interrupts = <0x0 0xc2 0x4>; + clocks = <0xb>; + status = "disabled"; + }; + + tacho@28055000 { + compatible = "phytium,tacho"; + reg = <0x0 0x28055000 0x0 0x1000>; + interrupts = <0x0 0xc3 0x4>; + clocks = <0xb>; + status = "disabled"; + }; + + tacho@28056000 { + compatible = "phytium,tacho"; + reg = <0x0 0x28056000 0x0 0x1000>; + interrupts = <0x0 0xc4 0x4>; + clocks = <0xb>; + status = "disabled"; + }; + + tacho@28057000 { + compatible = "phytium,tacho"; + reg = <0x0 0x28057000 0x0 0x1000>; + interrupts = <0x0 0xc5 0x4>; + clocks = <0xb>; + status = "disabled"; + }; + + tacho@28058000 { + compatible = "phytium,tacho"; + reg = <0x0 0x28058000 0x0 0x1000>; + interrupts = <0x0 0xc6 0x4>; + clocks = <0xb>; + status = "disabled"; + }; + + tacho@28059000 { + compatible = "phytium,tacho"; + reg = <0x0 0x28059000 0x0 0x1000>; + interrupts = <0x0 0xc7 0x4>; + clocks = <0xb>; + status = "disabled"; + }; + + tacho@2805a000 { + compatible = "phytium,tacho"; + reg = <0x0 0x2805a000 0x0 0x1000>; + interrupts = <0x0 0xc8 0x4>; + clocks = <0xb>; + status = "disabled"; + }; + + tacho@2805b000 { + compatible = "phytium,tacho"; + reg = <0x0 0x2805b000 0x0 0x1000>; + interrupts = <0x0 0xc9 0x4>; + clocks = <0xb>; + status = "disabled"; + }; + + tacho@2805c000 { + compatible = "phytium,tacho"; + reg = <0x0 0x2805c000 0x0 0x1000>; + interrupts = <0x0 0xca 0x4>; + clocks = <0xb>; + status = "disabled"; + }; + + tacho@2805d000 { + compatible = "phytium,tacho"; + reg = <0x0 0x2805d000 0x0 0x1000>; + interrupts = <0x0 0xcb 0x4>; + clocks = <0xb>; + status = "disabled"; + }; + + tacho@2805e000 { + compatible = "phytium,tacho"; + reg = <0x0 0x2805e000 0x0 0x1000>; + interrupts = <0x0 0xcc 0x4>; + clocks = <0xb>; + status = "disabled"; + }; + + tacho@2805f000 { + compatible = "phytium,tacho"; + reg = <0x0 0x2805f000 0x0 0x1000>; + interrupts = <0x0 0xcd 0x4>; + clocks = <0xb>; + status = "disabled"; + }; + + tacho@28060000 { + compatible = "phytium,tacho"; + reg = <0x0 0x28060000 0x0 0x1000>; + interrupts = <0x0 0xce 0x4>; + clocks = <0xb>; + status = "disabled"; + }; + + tacho@28061000 { + compatible = "phytium,tacho"; + reg = <0x0 0x28061000 0x0 0x1000>; + interrupts = <0x0 0xcf 0x4>; + clocks = <0xb>; + status = "disabled"; + }; + + tacho@28062000 { + compatible = "phytium,tacho"; + reg = <0x0 0x28062000 0x0 0x1000>; + interrupts = <0x0 0xd0 0x4>; + clocks = <0xb>; + status = "disabled"; + }; + + tacho@28063000 { + compatible = "phytium,tacho"; + reg = <0x0 0x28063000 0x0 0x1000>; + interrupts = <0x0 0xd1 0x4>; + clocks = <0xb>; + status = "disabled"; + }; + + tacho@28064000 { + compatible = "phytium,tacho"; + reg = <0x0 0x28064000 0x0 0x1000>; + interrupts = <0x0 0xd2 0x4>; + clocks = <0xb>; + status = "disabled"; + }; + + tacho@28065000 { + compatible = "phytium,tacho"; + reg = <0x0 0x28065000 0x0 0x1000>; + interrupts = <0x0 0xd3 0x4>; + clocks = <0xb>; + status = "disabled"; + }; + + tacho@28066000 { + compatible = "phytium,tacho"; + reg = <0x0 0x28066000 0x0 0x1000>; + interrupts = <0x0 0xd4 0x4>; + clocks = <0xb>; + status = "disabled"; + }; + + tacho@28067000 { + compatible = "phytium,tacho"; + reg = <0x0 0x28067000 0x0 0x1000>; + interrupts = <0x0 0xd5 0x4>; + clocks = <0xb>; + status = "disabled"; + }; + + tacho@28068000 { + compatible = "phytium,tacho"; + reg = <0x0 0x28068000 0x0 0x1000>; + interrupts = <0x0 0xd6 0x4>; + clocks = <0xb>; + status = "disabled"; + }; + + tacho@28069000 { + compatible = "phytium,tacho"; + reg = <0x0 0x28069000 0x0 0x1000>; + interrupts = <0x0 0xd7 0x4>; + clocks = <0xb>; + status = "disabled"; + }; + + tacho@2806a000 { + compatible = "phytium,tacho"; + reg = <0x0 0x2806a000 0x0 0x1000>; + interrupts = <0x0 0xd8 0x4>; + clocks = <0xb>; + status = "disabled"; + }; + + tacho@2806b000 { + compatible = "phytium,tacho"; + reg = <0x0 0x2806b000 0x0 0x1000>; + interrupts = <0x0 0xd9 0x4>; + clocks = <0xb>; + status = "disabled"; + }; + + tacho@2806c000 { + compatible = "phytium,tacho"; + reg = <0x0 0x2806c000 0x0 0x1000>; + interrupts = <0x0 0xda 0x4>; + clocks = <0xb>; + status = "disabled"; + }; + + tacho@2806d000 { + compatible = "phytium,tacho"; + reg = <0x0 0x2806d000 0x0 0x1000>; + interrupts = <0x0 0xdb 0x4>; + clocks = <0xb>; + status = "disabled"; + }; + + tacho@2806e000 { + compatible = "phytium,tacho"; + reg = <0x0 0x2806e000 0x0 0x1000>; + interrupts = <0x0 0xdc 0x4>; + clocks = <0xb>; + status = "disabled"; + }; + + tacho@2806f000 { + compatible = "phytium,tacho"; + reg = <0x0 0x2806f000 0x0 0x1000>; + interrupts = <0x0 0xdd 0x4>; + clocks = <0xb>; + status = "disabled"; + }; + + tacho@28070000 { + compatible = "phytium,tacho"; + reg = <0x0 0x28070000 0x0 0x1000>; + interrupts = <0x0 0xde 0x4>; + clocks = <0xb>; + status = "disabled"; + }; + + tacho@28071000 { + compatible = "phytium,tacho"; + reg = <0x0 0x28071000 0x0 0x1000>; + interrupts = <0x0 0xdf 0x4>; + clocks = <0xb>; + status = "disabled"; + }; + + tacho@28072000 { + compatible = "phytium,tacho"; + reg = <0x0 0x28072000 0x0 0x1000>; + interrupts = <0x0 0xe0 0x4>; + clocks = <0xb>; + status = "disabled"; + }; + + tacho@28073000 { + compatible = "phytium,tacho"; + reg = <0x0 0x28073000 0x0 0x1000>; + interrupts = <0x0 0xe1 0x4>; + clocks = <0xb>; + status = "disabled"; + }; + + tacho@28074000 { + compatible = "phytium,tacho"; + reg = <0x0 0x28074000 0x0 0x1000>; + interrupts = <0x0 0xe2 0x4>; + clocks = <0xb>; + status = "disabled"; + }; + + tacho@28075000 { + compatible = "phytium,tacho"; + reg = <0x0 0x28075000 0x0 0x1000>; + interrupts = <0x0 0xe3 0x4>; + clocks = <0xb>; + status = "disabled"; + }; + + tacho@28076000 { + compatible = "phytium,tacho"; + reg = <0x0 0x28076000 0x0 0x1000>; + interrupts = <0x0 0xe4 0x4>; + clocks = <0xb>; + status = "disabled"; + }; + + tacho@28077000 { + compatible = "phytium,tacho"; + reg = <0x0 0x28077000 0x0 0x1000>; + interrupts = <0x0 0xe5 0x4>; + clocks = <0xb>; + status = "disabled"; + }; + + tacho@28078000 { + compatible = "phytium,tacho"; + reg = <0x0 0x28078000 0x0 0x1000>; + interrupts = <0x0 0xe6 0x4>; + clocks = <0xb>; + status = "disabled"; + }; + + tacho@28079000 { + compatible = "phytium,tacho"; + reg = <0x0 0x28079000 0x0 0x1000>; + interrupts = <0x0 0xe7 0x4>; + clocks = <0xb>; + status = "disabled"; + }; + + usb2@31800000 { + compatible = "phytium,e2000-usb2"; + reg = <0x0 0x31800000 0x0 0x80000 0x0 0x31990000 0x0 0x10000>; + interrupts = <0x0 0x20 0x4>; + status = "okay"; + dr_mode = "host"; + }; + + usb2@31880000 { + compatible = "phytium,e2000-usb2"; + reg = <0x0 0x31880000 0x0 0x80000 0x0 0x319a0000 0x0 0x10000>; + interrupts = <0x0 0x21 0x4>; + status = "disabled"; + }; + + usb2@31900000 { + compatible = "phytium,e2000-usb2"; + reg = <0x0 0x31900000 0x0 0x80000 0x0 0x319b0000 0x0 0x10000>; + interrupts = <0x0 0x22 0x4>; + status = "disabled"; + }; + + usb2@32800000 { + compatible = "phytium,e2000-usb2"; + reg = <0x0 0x32800000 0x0 0x40000 0x0 0x32880000 0x0 0x40000>; + interrupts = <0x0 0xe 0x4>; + status = "okay"; + dr_mode = "host"; + }; + + usb2@32840000 { + compatible = "phytium,e2000-usb2"; + reg = <0x0 0x32840000 0x0 0x40000 0x0 0x328c0000 0x0 0x40000>; + interrupts = <0x0 0xf 0x4>; + status = "okay"; + dr_mode = "host"; + }; + + dc@32000000 { + compatible = "phytium,dc"; + reg = <0x0 0x32000000 0x0 0x8000>; + interrupts = <0x0 0x2c 0x4>; + status = "okay"; + pipe_mask = [02]; + edp_mask = [00]; + }; + + i2s_dp0@32009000 { + compatible = "phytium,i2s"; + reg = <0x0 0x32009000 0x0 0x1000 0x0 0x32008000 0x0 0x1000>; + interrupts = <0x0 0x2f 0x4>; + clocks = <0xd>; + clock-names = "i2s_clk"; + status = "disabled"; + }; + + pmdk_dp { + compatible = "phytium,pmdk-dp"; + status = "disabled"; + }; + + mailbox@32a00000 { + compatible = "phytium,mbox"; + reg = <0x0 0x32a00000 0x0 0x1000>; + interrupts = <0x0 0x16 0x4>; + #mbox-cells = <0x1>; + phandle = <0x2>; + }; + + sce@32a30000 { + compatible = "phytium,sce"; + reg = <0x0 0x32a30000 0x0 0x6000>; + interrupts = <0x0 0x19 0x4>; + }; + + rng@32a36000 { + compatible = "phytium,rng"; + reg = <0x0 0x32a36000 0x0 0x1000>; + status = "disabled"; + }; + + sram@32a10000 { + compatible = "phytium,e2000-sram-ns", "mmio-sram"; + reg = <0x0 0x32a10000 0x0 0x2000>; + #address-cells = <0x1>; + #size-cells = <0x1>; + ranges = <0x0 0x0 0x32a10000 0x2000>; + + scp-shmem@0 { + compatible = "arm,scmi-shmem"; + reg = <0x1000 0x400>; + phandle = <0x4>; + }; + + scp-shmem@1 { + compatible = "arm,scmi-shmem"; + reg = <0x1400 0x400>; + phandle = <0x3>; + }; + }; + + spinlock@32b36000 { + compatible = "phytium,hwspinlock"; + reg = <0x0 0x32b36000 0x0 0x1000>; + #hwlock-cells = <0x1>; + nr-locks = <0x20>; + status = "disabled"; + }; + + pcie@40000000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + #address-cells = <0x3>; + #size-cells = <0x2>; + #interrupt-cells = <0x1>; + reg = <0x0 0x40000000 0x0 0x10000000>; + msi-parent = <0xe>; + bus-range = <0x0 0xff>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x4 0x4 0x0 0x0 0x0 0x2 0x1 0x0 0x0 0x0 0x5 0x4 0x0 0x0 0x0 0x3 0x1 0x0 0x0 0x0 0x6 0x4 0x0 0x0 0x0 0x4 0x1 0x0 0x0 0x0 0x7 0x4>; + ranges = <0x1000000 0x0 0x0 0x0 0x50000000 0x0 0xf00000 0x2000000 0x0 0x58000000 0x0 0x58000000 0x0 0x28000000 0x3000000 0x10 0x0 0x10 0x0 0x10 0x0>; + iommu-map = <0x0 0xf 0x0 0x10000>; + status = "okay"; + }; + + hda@28006000 { + compatible = "phytium,hda"; + reg = <0x0 0x28006000 0x0 0x1000>; + interrupts = <0x0 0x4e 0x4>; + status = "disabled"; + }; + + i2s@28009000 { + compatible = "phytium,i2s"; + reg = <0x0 0x28009000 0x0 0x1000 0x0 0x28005000 0x0 0x1000>; + interrupts = <0x0 0x4d 0x4>; + clocks = <0xd>; + clock-names = "i2s_clk"; + status = "disabled"; + }; + + can@2800a000 { + compatible = "phytium,canfd"; + reg = <0x0 0x2800a000 0x0 0x1000>; + interrupts = <0x0 0x51 0x4>; + clocks = <0x10>; + clock-names = "can_clk"; + tx-fifo-depth = <0x40>; + rx-fifo-depth = <0x40>; + status = "okay"; + }; + + can@2800b000 { + compatible = "phytium,canfd"; + reg = <0x0 0x2800b000 0x0 0x1000>; + interrupts = <0x0 0x52 0x4>; + clocks = <0x10>; + clock-names = "can_clk"; + tx-fifo-depth = <0x40>; + rx-fifo-depth = <0x40>; + status = "okay"; + }; + + keypad@2807a000 { + compatible = "phytium,keypad"; + reg = <0x0 0x2807a000 0x0 0x1000>; + interrupts = <0x0 0xbd 0x4>; + clocks = <0xb>; + status = "disabled"; + }; + + usb3@31a08000 { + compatible = "phytium,e2000-xhci"; + reg = <0x0 0x31a08000 0x0 0x18000>; + interrupts = <0x0 0x10 0x4>; + status = "okay"; + }; + + usb3@31a28000 { + compatible = "phytium,e2000-xhci"; + reg = <0x0 0x31a28000 0x0 0x18000>; + interrupts = <0x0 0x11 0x4>; + status = "okay"; + }; + + sata@31a40000 { + compatible = "generic-ahci"; + reg = <0x0 0x31a40000 0x0 0x1000>; + interrupts = <0x0 0x2a 0x4>; + status = "disabled"; + }; + + sata@32014000 { + compatible = "generic-ahci"; + reg = <0x0 0x32014000 0x0 0x1000>; + interrupts = <0x0 0x2b 0x4>; + status = "disabled"; + }; + + + ethernet@3200e000 { + compatible = "phytium,gem", "cdns,phytium-gem"; + reg = <0x0 0x3200e000 0x0 0x2000>; + interrupts = <0x0 0x3b 0x4 0x0 0x3c 0x4 0x0 0x3d 0x4 0x0 0x3e 0x4>; + clock-names = "pclk", "hclk", "tx_clk", "tsu_clk"; + clocks = <0x11 0x12 0x12 0x11>; + magic-packet; + status = "okay"; + phy-mode = "sgmii"; + use-mii; + }; + + ethernet@32010000 { + compatible = "phytium,gem", "cdns,phytium-gem"; + reg = <0x0 0x32010000 0x0 0x2000>; + interrupts = <0x0 0x40 0x4 0x0 0x41 0x4 0x0 0x42 0x4 0x0 0x43 0x4>; + clock-names = "pclk", "hclk", "tx_clk", "tsu_clk"; + clocks = <0x11 0x12 0x12 0x11>; + magic-packet; + use-mii; + status = "okay"; + phy-mode = "sgmii"; + }; + + ethernet@32012000 { + compatible = "phytium,gem", "cdns,phytium-gem"; + reg = <0x0 0x32012000 0x0 0x2000>; + interrupts = <0x0 0x44 0x4 0x0 0x45 0x4 0x0 0x46 0x4 0x0 0x47 0x4>; + clock-names = "pclk", "hclk", "tx_clk", "tsu_clk"; + clocks = <0x11 0x12 0x12 0x11>; + magic-packet; + use-mii; + status = "disabled"; + phy-mode = "sgmii"; + }; + + i2c@28026000 { + compatible = "phytium,i2c"; + reg = <0x0 0x28026000 0x0 0x1000>; + interrupts = <0x0 0x65 0x4>; + clocks = <0xb>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "okay"; + + rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; + }; + + i2c@28020000 { + status = "okay"; + compatible = "phytium,i2c"; + reg = <0x0 0x28020000 0x0 0x1000>; + interrupts = <0x0 0x62 0x4>; + clocks = <0xb>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <0x1>; + }; + }; + + uart@28028000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x28028000 0x0 0x1000>; + interrupts = <0x0 0x66 0x4>; + clocks = <0xb 0xb>; + clock-names = "uartclk", "apb_pclk"; + status = "okay"; + }; + + uart@2802a000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x2802a000 0x0 0x1000>; + interrupts = <0x0 0x67 0x4>; + clocks = <0xb 0xb>; + clock-names = "uartclk", "apb_pclk"; + status = "okay"; + }; + + uart@2802e000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x2802e000 0x0 0x1000>; + interrupts = <0x0 0x69 0x4>; + clocks = <0xb 0xb>; + clock-names = "uartclk", "apb_pclk"; + status = "okay"; + }; + + uart@28030000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x28030000 0x0 0x1000>; + interrupts = <0x0 0x6a 0x4>; + clocks = <0xb 0xb>; + clock-names = "uartclk", "apb_pclk"; + status = "okay"; + }; + + uart@28032000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x28032000 0x0 0x1000>; + interrupts = <0x0 0x6b 0x4>; + clocks = <0xb 0xb>; + clock-names = "uartclk", "apb_pclk"; + status = "okay"; + }; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + memory@00 { + device_type = "memory"; + reg = <0x0 0x80000000 0x1 0x0>; + }; +}; diff --git a/configs/arm64/e2000d-inmate-eth.c b/configs/arm64/e2000d-inmate-eth.c new file mode 100755 index 00000000..1fd3744f --- /dev/null +++ b/configs/arm64/e2000d-inmate-eth.c @@ -0,0 +1,151 @@ +/** + * jailhouse, a Linux-based partitioning hypervisor + * + * Copyright (C), 2022, Kylinsoft Corporation. + * + * @author mashuai01@kylinos.cn + * @date 2023.03.31 + * @brief + * @note + */ + +#include <jailhouse/types.h> +#include <jailhouse/cell-config.h> + +struct { + struct jailhouse_cell_desc cell; + __u64 cpus[1]; + struct jailhouse_memory mem_regions[10]; + struct jailhouse_irqchip irqchips[2]; + struct jailhouse_pci_device pci_devices[0]; +} __attribute__((packed)) config = { + .cell = { + .signature = JAILHOUSE_CELL_DESC_SIGNATURE, + .revision = JAILHOUSE_CONFIG_REVISION, + .name = "e2000d-guest-eth", + .flags = JAILHOUSE_CELL_PASSIVE_COMMREG, + + .cpu_set_size = sizeof(config.cpus), + .num_memory_regions = ARRAY_SIZE(config.mem_regions), + .num_irqchips = ARRAY_SIZE(config.irqchips), + .num_pci_devices = ARRAY_SIZE(config.pci_devices), + + + .vpci_irq_base = 102, + + .console = { + .address = 0x2800d000, + .type = JAILHOUSE_CON_TYPE_PL011, + .flags = JAILHOUSE_CON_ACCESS_MMIO | + JAILHOUSE_CON_REGDIST_4, + }, + }, + + .cpus = { + 0x1, + }, + + .mem_regions = { + /* IVSHMEM shared memory regions */ + { + .phys_start = 0xa7000000, + .virt_start = 0xa7000000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0xa7001000, + .virt_start = 0xa7001000, + .size = 0x9000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0xa700a000, + .virt_start = 0xa700a000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0xa700c000, + .virt_start = 0xa700c000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0xa700e000, + .virt_start = 0xa700e000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED, + }, + /* ETH 0 */ + { + .phys_start = 0x3200c000, + .virt_start = 0x3200c000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED, + }, + /* UART */ + { + .phys_start = 0x2800d000, + .virt_start = 0x2800d000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED, + }, + + /* RAM */ + { + .phys_start = 0xa2000000, + .virt_start = 0, + .size = 0x5000000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE, + }, + { + .phys_start = 0xa3000000, + .virt_start = 0xa3000000, + .size = 0xc000000, + .flags= JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE | + JAILHOUSE_MEM_DMA, + + + }, + /* communication region */ + { + .virt_start = 0x80000000, + .size = 0x00001000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_COMM_REGION, + }, +}, + .irqchips = { + /* GIC */ { + .address = 0x30800000, + .pin_base = 32, + .pin_bitmap = { + 1 << (60 - 32) | 1 << (61 - 32) | 1 << (62 - 32) | 1 << (63 - 32), + 1 << (87 - 64) | 1 << (88 - 64) | 1 << (89 - 64) | 1 << (90 - 64), + 1 << (116 - 96), + 0, + }, + }, + { + .address = 0x30800000, + .pin_base = 256, + .pin_bitmap = { + 0, + 0, + 0, + 0, + }, + }, + }, + + + .pci_devices = { + + }, + +}; diff --git a/configs/arm64/e2000d-main-eth.c b/configs/arm64/e2000d-main-eth.c new file mode 100755 index 00000000..9eeac20a --- /dev/null +++ b/configs/arm64/e2000d-main-eth.c @@ -0,0 +1,371 @@ +/** + * jailhouse, a Linux-based partitioning hypervisor + * + * Copyright (C), 2022, Kylinsoft Corporation. + * + * @author mashuai01@kylinos.cn + * @date 2023.03.27 + * @brief + * @note + */ + +#include <jailhouse/types.h> +#include <jailhouse/cell-config.h> + +struct { + struct jailhouse_system header; + __u64 cpus[1]; + struct jailhouse_memory mem_regions[35]; + struct jailhouse_irqchip irqchips[2]; + struct jailhouse_pci_device pci_devices[0]; +} __attribute__((packed)) config = { + .header = { + .signature = JAILHOUSE_SYSTEM_SIGNATURE, + .revision = JAILHOUSE_CONFIG_REVISION, + .flags = JAILHOUSE_SYS_VIRTUAL_DEBUG_CONSOLE, + .hypervisor_memory = { + .phys_start = 0xa0000000, + .size = 0x01000000, + }, + .debug_console = { + .address = 0x2800d000, + .size = 0x1000, + .type = JAILHOUSE_CON_TYPE_PL011, + .flags = JAILHOUSE_CON_ACCESS_MMIO | + JAILHOUSE_CON_REGDIST_4, + }, + .platform_info = { + .pci_mmconfig_base = 0x40000000, + .pci_mmconfig_end_bus = 5, + .pci_is_virtual = 0, + .pci_domain = 1, + + .arm = { + .gic_version = 3, + .gicd_base = 0x30800000, + .gicr_base = 0x308c0000, + .gicc_base = 0x30840000, + .gich_base = 0x30850000, + .gicv_base = 0x30860000, + .maintenance_irq = 25, + }, + }, + .root_cell = { + .name = "e2000d", + + .cpu_set_size = sizeof(config.cpus), + .num_memory_regions = ARRAY_SIZE(config.mem_regions), + .num_irqchips = ARRAY_SIZE(config.irqchips), + .num_pci_devices = ARRAY_SIZE(config.pci_devices), + + .vpci_irq_base = 100, + }, + }, + + .cpus = { + 0x3, + }, + + .mem_regions = { + /* IVSHMEM shared memory regions */ + { + .phys_start = 0xa7000000, + .virt_start = 0xa7000000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ, + }, + { + .phys_start = 0xa7001000, + .virt_start = 0xa7001000, + .size = 0x9000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE, + }, + { + .phys_start = 0xa700a000, + .virt_start = 0xa700a000, + .size = 0x200000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE, + },//section0 + { + .phys_start = 0xa720a000, + .virt_start = 0xa720a000, + .size = 0x200000, + .flags = JAILHOUSE_MEM_READ, + },//section1 + { + .phys_start = 0xa740a000, + .virt_start = 0xa740a000, + .size = 0x200000, + .flags = JAILHOUSE_MEM_READ, + },//seciton2 + + /* Main memory */ + { + .phys_start = 0x80000000, + .virt_start = 0x80000000, + .size = 0x80000000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_EXECUTE, + }, + /* Main memory*/ + { + .phys_start = 0x2000000000, + .virt_start = 0x2000000000, + .size = 0x80000000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_EXECUTE, + }, + /* UART 0-3 */ + { + .phys_start = 0x2800c000, + .virt_start = 0x2800c000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + { + .phys_start = 0x2800d000, + .virt_start = 0x2800d000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + { + .phys_start = 0x2800e000, + .virt_start = 0x2800e000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* GPIO 0-5 */ + { + .phys_start = 0x28034000, + .virt_start = 0x28034000, + .size = 0x6000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* I2C 0-1 */ + { + .phys_start = 0x28020000, + .virt_start = 0x28020000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + { + .phys_start = 0x28026000, + .virt_start = 0x28026000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* Watchdog 0 */ + { + .phys_start = 0x28040000, + .virt_start = 0x28040000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* Watchdog 1 */ + { + .phys_start = 0x28042000, + .virt_start = 0x28042000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* IOMMU */ + { + .phys_start = 0x30000000, + .virt_start = 0x30000000, + .size = 0x800000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /*Usb2 0-4*/ + { + .phys_start = 0x31808000, + .virt_start = 0x31808000, + .size = 0x280000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /*Usb3 0-1*/ + { + .phys_start = 0x31a08000, + .virt_start = 0x31a08000, + .size = 0x30000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /*sata 0*/ + { + .phys_start = 0x31a40000, + .virt_start = 0x31a40000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /*sata 1*/ + { + .phys_start = 0x32014000, + .virt_start = 0x32014000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /*vpu:no vpu in e2000d dts*/ + /*{ + .phys_start = 0x32b00000, + .virt_start = 0x32b00000, + .size = 0x20000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + },*/ + /* SPI 0-3 */ + { + .phys_start = 0x2803a000, + .virt_start = 0x2803a000, + .size = 0x4000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* QSPI:disable in dts */ + { + .phys_start = 0x28008000, + .virt_start = 0x28008000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* HDA */ + { + .phys_start = 0x28006000, + .virt_start = 0x28006000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* CAN 0-2 and SDCI*/ + { + .phys_start = 0x2800a000, + .virt_start = 0x2800a000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* ETH 0-3 */ + { + .phys_start = 0x3200c000, + .virt_start = 0x3200c000, + .size = 0x8000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* dc */ + { + .phys_start = 0x32000000, + .virt_start = 0x32000000, + .size = 0x8000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* Mailbox */ + { + .phys_start = 0x32a00000, + .virt_start = 0x32a00000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* sce */ + { + .phys_start = 0x32a30000, + .virt_start = 0x32a30000, + .size = 0x6000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* rng */ + { + .phys_start = 0x32a36000, + .virt_start = 0x32a36000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* SRAM */ + { + .phys_start = 0x32a10000, + .virt_start = 0x32a10000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* GIC ITS */ + { + .phys_start = 0x30820000, + .virt_start = 0x30820000, + .size = 0x20000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* PCIe ECAM */ + { + .phys_start = 0x40000000, + .virt_start = 0x40000000, + .size = 0x10000000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* PCIe IO */ + { + .phys_start = 0x50000000, + .virt_start = 0x50000000, + .size = 0x8000000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* PCIe Mem32 */ + { + .phys_start = 0x58000000, + .virt_start = 0x58000000, + .size = 0x28000000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* PCIe Mem64 */ + { + .phys_start = 0x1000000000, + .virt_start = 0x1000000000, + .size = 0x1000000000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + }, + + .irqchips = { + /* GIC */ + { + .address = 0x30800000, + .pin_base = 32, + .pin_bitmap = { + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + }, + }, + { + .address = 0x30800000, + .pin_base = 256, + .pin_bitmap = { + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + }, + }, + + }, + + .pci_devices = { + }, + +}; -- 2.25.1
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