File _service:obs_scm:0007-add-Phytium-e2000d-cell-c... of Package Jailhouse

File _service:obs_scm:0007-add-Phytium-e2000d-cell-configures-and-dts.patch of Package Jailhouse

From 60ac51f0315af111e8e79c278589087df9db63cc Mon Sep 17 00:00:00 2001
From: mashuai <mashuai01@kylinos.cn>
Date: Mon, 29 May 2023 04:28:27 -0700
Subject: [PATCH 07/12] add Phytium e2000d cell configures and dts

[KEYWORDS] none
[TO SOLVE]
[TEST SUGGESTION] none

[SUBMIT BY] mashuai
[REVIEW BY] mashuai
[TEST   BY] mashuai
---
 configs/arm64/e2000d-rtos32.c | 151 ++++++++++++++++++++++++++++++++++
 configs/arm64/e2000d-rtos64.c | 151 ++++++++++++++++++++++++++++++++++
 2 files changed, 302 insertions(+)
 create mode 100644 configs/arm64/e2000d-rtos32.c
 create mode 100644 configs/arm64/e2000d-rtos64.c

diff --git a/configs/arm64/e2000d-rtos32.c b/configs/arm64/e2000d-rtos32.c
new file mode 100644
index 00000000..433968a5
--- /dev/null
+++ b/configs/arm64/e2000d-rtos32.c
@@ -0,0 +1,151 @@
+/**
+ * jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Copyright (C), 2022, Kylinsoft Corporation.
+ *
+ * @author mashuai01@kylinos.cn
+ * @date 2023.05.26
+ * @brief 
+ * @note 
+ */
+
+#include <jailhouse/types.h>
+#include <jailhouse/cell-config.h>
+
+struct {
+	struct jailhouse_cell_desc cell;
+	__u64 cpus[1];
+	struct jailhouse_memory mem_regions[10];
+	struct jailhouse_irqchip irqchips[2];
+	struct jailhouse_pci_device pci_devices[0];
+} __attribute__((packed)) config = {
+	.cell = {
+		.signature = JAILHOUSE_CELL_DESC_SIGNATURE,
+		.revision = JAILHOUSE_CONFIG_REVISION,
+		.name = "e2000d-rtos32",
+		.flags = JAILHOUSE_CELL_PASSIVE_COMMREG | JAILHOUSE_CELL_AARCH32,
+
+		.cpu_set_size = sizeof(config.cpus),
+		.cpu_reset_address = 0x80100000,
+		.num_memory_regions = ARRAY_SIZE(config.mem_regions),
+		.num_irqchips = ARRAY_SIZE(config.irqchips),
+		.num_pci_devices = ARRAY_SIZE(config.pci_devices),
+        
+
+		.vpci_irq_base = 102,
+
+		.console = {
+			.address = 0x2800d000,
+			.type = JAILHOUSE_CON_TYPE_PL011,
+			.flags = JAILHOUSE_CON_ACCESS_MMIO |
+				 JAILHOUSE_CON_REGDIST_4,
+		},
+	},
+
+	.cpus = {
+		0x1,
+	},
+
+	.mem_regions = {
+	/* IVSHMEM shared memory regions */
+	{
+		.phys_start = 0xa7000000,
+		.virt_start = 0xa7000000,
+		.size = 0x1000,
+		.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED,
+	},
+	{
+		.phys_start = 0xa7001000,
+		.virt_start = 0xa7001000,
+		.size = 0x9000,
+		.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_ROOTSHARED,
+	},
+	{
+		.phys_start = 0xa700a000,
+		.virt_start = 0xa700a000,
+		.size = 0x2000,
+		.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED,
+	},
+	{
+		.phys_start = 0xa700c000,
+		.virt_start = 0xa700c000,
+		.size = 0x2000,
+		.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_ROOTSHARED,
+	},
+	{
+		.phys_start = 0xa700e000,
+		.virt_start = 0xa700e000,
+		.size = 0x2000,
+		.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED,
+	},
+	/* ETH 0 */
+	{
+		.phys_start = 0x3200c000,
+		.virt_start = 0x3200c000,
+		.size = 0x2000,
+		.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+			JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED,
+	},
+		/* UART */
+		{
+			.phys_start = 0x2800d000,
+			.virt_start = 0x2800d000,
+			.size = 0x1000,
+			.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+				JAILHOUSE_MEM_IO  | JAILHOUSE_MEM_ROOTSHARED,
+		},
+		/* RAM */ 
+		{
+			.phys_start = 0xa2000000,
+			.virt_start = 0x80100000,
+			.size = 0x6000000,
+			.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+				JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,
+		},
+		{
+		   	.phys_start = 0xa3000000,
+			.virt_start = 0xa3000000,
+			.size = 0xc000000,
+			.flags= JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+				JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE |
+				JAILHOUSE_MEM_DMA,
+		
+		
+		},
+		/* communication region */ 
+		{
+			.virt_start = 0x80000000,
+			.size = 0x00001000,
+			.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+				 JAILHOUSE_MEM_COMM_REGION,
+		},
+},
+	.irqchips = {
+		/* GIC */ {
+			.address = 0x30800000,
+			.pin_base = 32,
+			.pin_bitmap = {
+				0,
+				0,
+				1 << (116 - 96),
+				(1 << (102 + 32 - 128)) | (1 << (100 + 32 - 128)),
+			},
+		},
+		{
+			.address = 0x30800000,
+			.pin_base = 256,
+			.pin_bitmap = {
+				1 << (173 - 160) | 1 << (172 - 160),
+				0,
+				0,
+				0,
+			},
+		},
+	},
+
+
+	.pci_devices = {
+
+	},
+
+};
diff --git a/configs/arm64/e2000d-rtos64.c b/configs/arm64/e2000d-rtos64.c
new file mode 100644
index 00000000..38c4f6e5
--- /dev/null
+++ b/configs/arm64/e2000d-rtos64.c
@@ -0,0 +1,151 @@
+/**
+ * jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Copyright (C), 2022, Kylinsoft Corporation.
+ *
+ * @author mashuai01@kylinos.cn
+ * @date 2023.05.29
+ * @brief 
+ * @note 
+ */
+
+#include <jailhouse/types.h>
+#include <jailhouse/cell-config.h>
+
+struct {
+	struct jailhouse_cell_desc cell;
+	__u64 cpus[1];
+	struct jailhouse_memory mem_regions[10];
+	struct jailhouse_irqchip irqchips[2];
+	struct jailhouse_pci_device pci_devices[0];
+} __attribute__((packed)) config = {
+	.cell = {
+		.signature = JAILHOUSE_CELL_DESC_SIGNATURE,
+		.revision = JAILHOUSE_CONFIG_REVISION,
+		.name = "e2000d-rtos64",
+		.flags = JAILHOUSE_CELL_PASSIVE_COMMREG,
+
+		.cpu_set_size = sizeof(config.cpus),
+		.cpu_reset_address = 0x80100000,
+		.num_memory_regions = ARRAY_SIZE(config.mem_regions),
+		.num_irqchips = ARRAY_SIZE(config.irqchips),
+		.num_pci_devices = ARRAY_SIZE(config.pci_devices),
+        
+
+		.vpci_irq_base = 102,
+
+		.console = {
+			.address = 0x2800d000,
+			.type = JAILHOUSE_CON_TYPE_PL011,
+			.flags = JAILHOUSE_CON_ACCESS_MMIO |
+				 JAILHOUSE_CON_REGDIST_4,
+		},
+	},
+
+	.cpus = {
+		0x1,
+	},
+
+	.mem_regions = {
+	/* IVSHMEM shared memory regions */
+	{
+		.phys_start = 0xa7000000,
+		.virt_start = 0xa7000000,
+		.size = 0x1000,
+		.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED,
+	},
+	{
+		.phys_start = 0xa7001000,
+		.virt_start = 0xa7001000,
+		.size = 0x9000,
+		.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_ROOTSHARED,
+	},
+	{
+		.phys_start = 0xa700a000,
+		.virt_start = 0xa700a000,
+		.size = 0x2000,
+		.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED,
+	},
+	{
+		.phys_start = 0xa700c000,
+		.virt_start = 0xa700c000,
+		.size = 0x2000,
+		.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_ROOTSHARED,
+	},
+	{
+		.phys_start = 0xa700e000,
+		.virt_start = 0xa700e000,
+		.size = 0x2000,
+		.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED,
+	},
+	/* ETH 0 */
+	{
+		.phys_start = 0x3200c000,
+		.virt_start = 0x3200c000,
+		.size = 0x2000,
+		.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+			JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED,
+	},
+		/* UART */
+		{
+			.phys_start = 0x2800d000,
+			.virt_start = 0x2800d000,
+			.size = 0x1000,
+			.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+				JAILHOUSE_MEM_IO  | JAILHOUSE_MEM_ROOTSHARED,
+		},
+		/* RAM */ 
+		{
+			.phys_start = 0xa2000000,
+			.virt_start = 0x80100000,
+			.size = 0x6000000,
+			.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+				JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,
+		},
+		{
+		   	.phys_start = 0xa3000000,
+			.virt_start = 0xa3000000,
+			.size = 0xc000000,
+			.flags= JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+				JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE |
+				JAILHOUSE_MEM_DMA,
+		
+		
+		},
+		/* communication region */ 
+		{
+			.virt_start = 0x80000000,
+			.size = 0x00001000,
+			.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+				 JAILHOUSE_MEM_COMM_REGION,
+		},
+},
+	.irqchips = {
+		/* GIC */ {
+			.address = 0x30800000,
+			.pin_base = 32,
+			.pin_bitmap = {
+				0,
+				0,
+				1 << (116 - 96),
+				(1 << (102 + 32 - 128)) | (1 << (100 + 32 - 128)),
+			},
+		},
+		{
+			.address = 0x30800000,
+			.pin_base = 256,
+			.pin_bitmap = {
+				1 << (173 - 160) | 1 << (172 - 160),
+				0,
+				0,
+				0,
+			},
+		},
+	},
+
+
+	.pci_devices = {
+
+	},
+
+};
-- 
2.25.1