File _service:tar_scm:llvmpipe-add-riscv-support-in-... of Package Mesa

File _service:tar_scm:llvmpipe-add-riscv-support-in-orcjit.patch of Package Mesa

From b4cc97ac05b70fa328ad57cf6defee8113666cac Mon Sep 17 00:00:00 2001
From: Alex Fan <alex.fan.q@gmail.com>
Date: Fri, 29 Jul 2022 12:44:14 +1000
Subject: [PATCH] llvmpipe: add riscv support in orcjit

assume cpu supports extension +i,+m,+a,+f,+d,+c
---
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_init_orc.cpp b/src/gallium/auxiliary/gallivm/lp_bld_init_orc.cpp
index 8ea4df7..91dde78 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_init_orc.cpp
+++ b/src/gallium/auxiliary/gallivm/lp_bld_init_orc.cpp
@@ -44,7 +44,7 @@
 /* conflict with ObjectLinkingLayer.h */
 #include "util/u_memory.h"
 
-#if (defined(_WIN32) && LLVM_VERSION_MAJOR >= 15)
+#if defined(PIPE_ARCH_RISCV64) || defined(PIPE_ARCH_RISCV32) || (defined(_WIN32) && LLVM_VERSION_MAJOR >= 15)
 /* use ObjectLinkingLayer (JITLINK backend) */
 #define USE_JITLINK
 #endif
@@ -551,6 +551,30 @@ llvm::orc::JITTargetMachineBuilder LPJit::create_jtdb() {
    options.StackAlignmentOverride = 4;
 #endif
 
+#if defined(PIPE_ARCH_RISCV64)
+#if defined(__riscv_float_abi_soft)
+   options.MCOptions.ABIName = "lp64";
+#elif defined(__riscv_float_abi_single)
+   options.MCOptions.ABIName = "lp64f";
+#elif defined(__riscv_float_abi_double)
+   options.MCOptions.ABIName = "lp64d";
+#else
+#error "GALLIVM: unknown target riscv float abi"
+#endif
+#endif
+
+#if defined(PIPE_ARCH_RISCV32)
+#if defined(__riscv_float_abi_soft)
+   options.MCOptions.ABIName = "ilp32";
+#elif defined(__riscv_float_abi_single)
+   options.MCOptions.ABIName = "ilp32f";
+#elif defined(__riscv_float_abi_double)
+   options.MCOptions.ABIName = "ilp32d";
+#else
+#error "GALLIVM: unknown target riscv float abi"
+#endif
+#endif
+
    JTMB.setOptions(options);
 
    std::vector<std::string> MAttrs;
@@ -649,6 +673,14 @@ llvm::orc::JITTargetMachineBuilder LPJit::create_jtdb() {
    MAttrs.push_back("+fp64");
 #endif
 
+#if defined(PIPE_ARCH_RISCV64)
+   /* Before riscv is more matured and util_get_cpu_caps() is implemented,
+    * assume this for now since most of linux capable riscv machine are
+    * riscv64gc
+    */
+   MAttrs = {"+m","+c","+a","+d","+f"};
+#endif
+
    JTMB.addFeatures(MAttrs);
 
    if (::gallivm_debug & (GALLIVM_DEBUG_IR | GALLIVM_DEBUG_ASM | GALLIVM_DEBUG_DUMP_BC)) {
@@ -716,6 +748,30 @@ llvm::orc::JITTargetMachineBuilder LPJit::create_jtdb() {
       MCPU = util_get_cpu_caps()->has_msa ? "mips64r5" : "mips64r2";
 #endif
 
+#if defined(PIPE_ARCH_RISCV64)
+   /**
+    * should be fixed with https://reviews.llvm.org/D121149 in llvm 15,
+    * set it anyway for llvm 14
+    */
+   if (MCPU == "generic")
+      MCPU = "generic-rv64";
+
+   JTMB.setCodeModel(CodeModel::Medium);
+   JTMB.setRelocationModel(Reloc::PIC_);
+#endif
+
+#if defined(PIPE_ARCH_RISCV32)
+   /**
+    * should be fixed with https://reviews.llvm.org/D121149 in llvm 15,
+    * set it anyway for llvm 14
+    */
+   if (MCPU == "generic")
+      MCPU = "generic-rv32";
+
+   JTMB.setCodeModel(CodeModel::Medium);
+   JTMB.setRelocationModel(Reloc::PIC_);
+#endif
+
    JTMB.setCPU(MCPU);
    if (gallivm_debug & (GALLIVM_DEBUG_IR | GALLIVM_DEBUG_ASM | GALLIVM_DEBUG_DUMP_BC)) {
       debug_printf("llc -mcpu option: %s\n", MCPU.c_str());
diff --git a/src/util/detect_arch.h b/src/util/detect_arch.h
index 334358f..8c7bd15 100644
--- a/src/util/detect_arch.h
+++ b/src/util/detect_arch.h
@@ -137,4 +137,14 @@
 #define DETECT_ARCH_MIPS 0
 #endif
 
+#if defined(__riscv)
+#if __riscv_xlen == 64
+#define PIPE_ARCH_RISCV64
+#elif __riscv_xlen == 32
+#define PIPE_ARCH_RISCV32
+#else
+#error "pipe: unknown target riscv xlen"
+#endif
+#endif
+
 #endif /* UTIL_DETECT_ARCH_H_ */