File _service:tar_scm:i386-cache-passthrough-Update-... of Package qemu

File _service:tar_scm:i386-cache-passthrough-Update-AMD-8000_001D.EAX-25-1.patch of Package qemu

From ff43e9201aba8f4047e6fd5edb93a4861cc8fed2 Mon Sep 17 00:00:00 2001
From: Yanan Wang <wangyanan55@huawei.com>
Date: Thu, 28 Mar 2024 18:57:56 +0800
Subject: [PATCH] i386: cache passthrough: Update AMD 8000_001D.EAX[25:14]
 based on vCPU topo

On AMD target, when host cache passthrough is disabled we will
emulate the guest caches with default values and initialize the
shared cpu list of the caches based on vCPU topology. However
when host cache passthrough is enabled, the shared cpu list is
consistent with host regardless what the vCPU topology is.

For example, when cache passthrough is enabled, running a guest
with vThreads=1 on a host with pThreads=2, we will get that there
are every *two* logical vCPUs sharing a L1/L2 cache, which is not
consistent with the vCPU topology (vThreads=1).

So let's reinitialize BITs[25:14] of AMD CPUID 8000_001D.EAX
based on the actual vCPU topology instead of host pCPU topology.

Signed-off-by: Yanan Wang <wangyanan55@huawei.com>
Signed-off-by: Yuan Zhang <zhangyuan162@huawei.com>
---
 target/i386/cpu.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index f94405c02b..491cf40cc7 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6597,9 +6597,31 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
         }
         break;
     case 0x8000001D:
+	/* Populate AMD Processor Cache Information */
         *eax = 0;
         if (cpu->cache_info_passthrough) {
             x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx);
+
+	    /*
+             * Clear BITs[25:14] and then update them based on the guest
+             * vCPU topology, like what we do in encode_cache_cpuid8000001d
+             * when cache_info_passthrough is not enabled.
+             */
+            *eax &= ~0x03FFC000;
+            switch (count) {
+            case 0: /* L1 dcache info */
+            case 1: /* L1 icache info */
+            case 2: /* L2 cache info */
+                *eax |= ((topo_info.threads_per_core - 1) << 14);
+                break;
+            case 3: /* L3 cache info */
+                *eax |= ((topo_info.cores_per_die *
+                          topo_info.threads_per_core - 1) << 14);
+                break;
+            default: /* end of info */
+                *eax = *ebx = *ecx = *edx = 0;
+                break;
+            }
             break;
         }
         switch (count) {
-- 
2.27.0