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File _service:tar_scm:0189-LoongArch-fix-building-errors.patch of Package gcc
From 142ae446cab26f1beb81a53a7da3c477ce42df40 Mon Sep 17 00:00:00 2001 From: Peng Fan <fanpeng@loongson.cn> Date: Mon, 28 Oct 2024 09:02:51 +0000 Subject: [PATCH] LoongArch: fix building errors. --- config/mt-loongarch-mlib | 2 +- gcc/config/loongarch/loongarch-evolution.h | 2 +- gcc/config/loongarch/loongarch-opts.cc | 1 + gcc/config/loongarch/loongarch-str.h | 11 +++--- gcc/config/loongarch/loongarch.cc | 9 +---- gcc/config/loongarch/loongarch.md | 44 ++++++++++++++++------ gcc/config/loongarch/simd.md | 15 +++++--- gcc/doc/invoke.texi | 3 +- 8 files changed, 53 insertions(+), 34 deletions(-) diff --git a/config/mt-loongarch-mlib b/config/mt-loongarch-mlib index 4cfe568f1..bbbba277f 100644 --- a/config/mt-loongarch-mlib +++ b/config/mt-loongarch-mlib @@ -1 +1 @@ -FLAGS_FOR_TARGET += -fmultiflags +FLAGS_FOR_TARGET += diff --git a/gcc/config/loongarch/loongarch-evolution.h b/gcc/config/loongarch/loongarch-evolution.h index d64996481..7e8e602c7 100644 --- a/gcc/config/loongarch/loongarch-evolution.h +++ b/gcc/config/loongarch/loongarch-evolution.h @@ -1,7 +1,7 @@ /* Generated automatically by "genstr" from "isa-evolution.in". Please do not edit this file directly. - Copyright (C) 2023 Free Software Foundation, Inc. + Copyright (C) 2023-2024 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/loongarch/loongarch-opts.cc b/gcc/config/loongarch/loongarch-opts.cc index 735daeb7c..1d08bb6a1 100644 --- a/gcc/config/loongarch/loongarch-opts.cc +++ b/gcc/config/loongarch/loongarch-opts.cc @@ -1071,6 +1071,7 @@ loongarch_init_misc_options (struct gcc_options *opts, #undef INIT_TARGET_FLAG +#define TARGET_DIRECT_EXTERN_ACCESS_OPTS_P(opts) (((opts->x_target_flags) & MASK_DIRECT_EXTERN_ACCESS) != 0) /* Set mexplicit-relocs default. */ if (opts->x_la_opt_explicit_relocs == M_OPT_UNSET) opts->x_la_opt_explicit_relocs = (HAVE_AS_EXPLICIT_RELOCS diff --git a/gcc/config/loongarch/loongarch-str.h b/gcc/config/loongarch/loongarch-str.h index 3cbe12f7b..13d161a8c 100644 --- a/gcc/config/loongarch/loongarch-str.h +++ b/gcc/config/loongarch/loongarch-str.h @@ -66,9 +66,10 @@ along with GCC; see the file COPYING3. If not see #define STR_CMODEL_LARGE "large" #define STR_CMODEL_EXTREME "extreme" -#define OPTSTR_FRECIPE "frecipe" -#define OPTSTR_DIV32 "div32" -#define OPTSTR_LAM_BH "lam-bh" -#define OPTSTR_LAMCAS "lamcas" -#define OPTSTR_LD_SEQ_SA "ld-seq-sa" +#define OPTSTR_FRECIPE "frecipe" +#define OPTSTR_DIV32 "div32" +#define OPTSTR_LAM_BH "lam-bh" +#define OPTSTR_LAMCAS "lamcas" +#define OPTSTR_LD_SEQ_SA "ld-seq-sa" + #endif /* LOONGARCH_STR_H */ diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc index 53bd8d7ec..6be0d80b3 100644 --- a/gcc/config/loongarch/loongarch.cc +++ b/gcc/config/loongarch/loongarch.cc @@ -764,14 +764,7 @@ loongarch_setup_incoming_varargs (cumulative_args_t cum, argument. Advance a local copy of CUM past the last "real" named argument, to find out how many registers are left over. */ local_cum = *get_cumulative_args (cum); - - /* For a C23 variadic function w/o any named argument, and w/o an - artifical argument for large return value, skip advancing args. - There is such an artifical argument iff. arg.type is non-NULL - (PR 114175). */ - if (!TYPE_NO_NAMED_ARGS_STDARG_P (TREE_TYPE (current_function_decl)) - || arg.type != NULL_TREE) - loongarch_function_arg_advance (pack_cumulative_args (&local_cum), arg); + loongarch_function_arg_advance (pack_cumulative_args (&local_cum), arg); /* Found out how many registers we need to save. */ gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs; diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index 66236a7c7..d8d444c7a 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -32,6 +32,7 @@ UNSPEC_FCLASS UNSPEC_FMAX UNSPEC_FMIN + UNSPEC_COPYSIGN UNSPEC_FTINT UNSPEC_FTINTRM UNSPEC_FTINTRP @@ -415,11 +416,13 @@ ;; A mode for anything with 32 bits or more, and able to be loaded with ;; the same addressing mode as ld.w. -(define_mode_iterator LD_AT_LEAST_32_BIT [GPR ANYF]) +;; (define_mode_iterator LD_AT_LEAST_32_BIT [GPR ANYF]) +(define_mode_iterator LD_AT_LEAST_32_BIT [(SI "") (DI "TARGET_64BIT") (SF "TARGET_HARD_FLOAT") (DF "TARGET_DOUBLE_FLOAT")]) ;; A mode for anything able to be stored with the same addressing mode as ;; st.w. -(define_mode_iterator ST_ANY [QHWD ANYF]) +;; (define_mode_iterator ST_ANY [QHWD ANYF]) +(define_mode_iterator ST_ANY [(QI "") (HI "") (SI "") (DI "TARGET_64BIT") (SF "TARGET_HARD_FLOAT") (DF "TARGET_DOUBLE_FLOAT")]) ;; A mode for anything legal as a input of a div or mod instruction. (define_mode_iterator DIV [(DI "TARGET_64BIT") @@ -590,6 +593,10 @@ (define_code_attr sel [(eq "masknez") (ne "maskeqz")]) (define_code_attr selinv [(eq "maskeqz") (ne "masknez")]) +(define_int_attr lrint_allow_inexact [(UNSPEC_FTINT "1") + (UNSPEC_FTINTRM "0") + (UNSPEC_FTINTRP "0")]) + ;; Iterator and attributes for floating-point to fixed-point conversion ;; instructions. (define_int_iterator LRINT [UNSPEC_FTINT UNSPEC_FTINTRM UNSPEC_FTINTRP]) @@ -625,7 +632,8 @@ ;; so the redundant sign extension can be removed if the output is used as ;; an input of a bitwise operation. Note plus, rotl, and div are handled ;; separately. -(define_code_iterator shift_w [any_shift rotatert]) +;; (define_code_iterator shift_w [any_shift rotatert]) +(define_code_iterator shift_w [ashift ashiftrt lshiftrt rotatert]) (define_code_iterator arith_w [minus mult]) (define_expand "<optab><mode>3" @@ -1324,8 +1332,9 @@ (define_insn "copysign<mode>3" [(set (match_operand:ANYF 0 "register_operand" "=f") - (copysign:ANYF (match_operand:ANYF 1 "register_operand" "f") - (match_operand:ANYF 2 "register_operand" "f")))] + (unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f") + (match_operand:ANYF 2 "register_operand" "f")] + UNSPEC_COPYSIGN))] "TARGET_HARD_FLOAT" "fcopysign.<fmt>\t%0,%1,%2" [(set_attr "type" "fcopysign") @@ -2722,12 +2731,13 @@ (set_attr "mode" "<MODE>")]) ;; Convert floating-point numbers to integers +;; (<LRINT> == UNSPEC_FTINT (define_insn "<lrint_pattern><ANYF:mode><ANYFI:mode>2" [(set (match_operand:ANYFI 0 "register_operand" "=f") (unspec:ANYFI [(match_operand:ANYF 1 "register_operand" "f")] LRINT))] "TARGET_HARD_FLOAT && - (<LRINT> == UNSPEC_FTINT + (<lrint_allow_inexact> || flag_fp_int_builtin_inexact || !flag_trapping_math)" "ftint<lrint_submenmonic>.<ANYFI:ifmt>.<ANYF:fmt> %0,%1" @@ -4135,15 +4145,26 @@ (136 "isnormal") (952 "isfinite")]) -(define_expand "<FCLASS_MASK:fclass_optab><ANYF:mode>2" +;;(define_expand "<FCLASS_MASK:fclass_optab><ANYF:mode>2" +;; [(match_operand:SI 0 "register_operand" "=r") +;; (match_operand:ANYF 1 "register_operand" " f") +;; (const_int FCLASS_MASK)] +;; "TARGET_HARD_FLOAT" +;; { +;; rtx ft0 = gen_reg_rtx (SImode); +;; rtx t0 = gen_reg_rtx (word_mode); +;; rtx mask = GEN_INT (<FCLASS_MASK>); + +(define_expand "fclass_optab<ANYF:mode>2" + [(unspec:ANYF [(match_operand:SI 0 "register_operand" "=r") - (match_operand:ANYF 1 "register_operand" " f") - (const_int FCLASS_MASK)] + (match_operand:ANYF 1 "register_operand" " f")] + UNSPEC_FCLASS)] "TARGET_HARD_FLOAT" { rtx ft0 = gen_reg_rtx (SImode); rtx t0 = gen_reg_rtx (word_mode); - rtx mask = GEN_INT (<FCLASS_MASK>); + rtx mask = GEN_INT (GET_MODE_MASK (<MODE>mode)); emit_insn (gen_fclass_<ANYF:fmt> (ft0, operands[1])); @@ -4165,7 +4186,8 @@ emit_move_insn (operands[0], t0); DONE; - }) + } + [(set_attr "mode" "<ANYF:MODE>")]) (define_insn "bytepick_w_<bytepick_imm>" [(set (match_operand:SI 0 "register_operand" "=r") diff --git a/gcc/config/loongarch/simd.md b/gcc/config/loongarch/simd.md index c28b95282..9e4c08196 100644 --- a/gcc/config/loongarch/simd.md +++ b/gcc/config/loongarch/simd.md @@ -30,10 +30,13 @@ (define_mode_iterator FLASX [V4DF V8SF]) ;; All integer modes available -(define_mode_iterator IVEC [(ILSX "ISA_HAS_LSX") (ILASX "ISA_HAS_LASX")]) +;; (define_mode_iterator IVEC [(ILSX "ISA_HAS_LSX") (ILASX "ISA_HAS_LASX")]) +(define_mode_iterator IVEC [(V2DI "ISA_HAS_LSX") (V4SI "ISA_HAS_LSX") (V8HI "ISA_HAS_LSX") (V16QI "ISA_HAS_LSX") + (V4DI "ISA_HAS_LASX") (V8SI "ISA_HAS_LASX") (V16HI "ISA_HAS_LASX") (V32QI "ISA_HAS_LASX")]) ;; All FP modes available -(define_mode_iterator FVEC [(FLSX "ISA_HAS_LSX") (FLASX "ISA_HAS_LASX")]) +(define_mode_iterator FVEC [(V2DF "ISA_HAS_LSX") (V4SF "ISA_HAS_LSX") + (V4DF "ISA_HAS_LASX") (V8SF "ISA_HAS_LASX")]) ;; Mnemonic prefix, "x" for LASX modes. (define_mode_attr x [(V2DI "") (V4SI "") (V8HI "") (V16QI "") @@ -162,12 +165,12 @@ ;; Expand the standard-named patterns to <x>vfrint instructions if ;; raising inexact exception is allowed. +;; "<SIMD_FRINT> == UNSPEC_SIMD_FRINT || (define_expand "<simd_frint_pattern><mode>2" [(set (match_operand:FVEC 0 "register_operand" "=f") (unspec:FVEC [(match_operand:FVEC 1 "register_operand" "f")] SIMD_FRINT))] - "<SIMD_FRINT> == UNSPEC_SIMD_FRINT || - flag_fp_int_builtin_inexact || + "flag_fp_int_builtin_inexact || !flag_trapping_math") ;; ftrunc is like btrunc, but it's allowed to raise inexact exception @@ -221,13 +224,13 @@ ;; Expand the standard-named patterns to <x>vftint instructions if ;; raising inexact exception. +;; "<SIMD_FRINT> == UNSPEC_SIMD_FRINT || (define_expand "l<simd_frint_pattern><mode><vimode>2" [(set (match_operand:<VIMODE> 0 "register_operand" "=f") (fix:<VIMODE> (unspec:FVEC [(match_operand:FVEC 1 "register_operand" "f")] SIMD_FRINT)))] - "<SIMD_FRINT> == UNSPEC_SIMD_FRINT || - flag_fp_int_builtin_inexact || + "flag_fp_int_builtin_inexact || !flag_trapping_math") ;; fix_trunc is allowed to raise inexact exception even if diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index d2c52cdf4..8a09938fc 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1006,8 +1006,7 @@ Objective-C and Objective-C++ Dialects}. -mcond-move-float -mno-cond-move-float @gol -memcpy -mno-memcpy -mstrict-align -mno-strict-align @gol -mmax-inline-memcpy-size=@var{n} @gol --mexplicit-relocs -mno-explicit-relocs @gol --mdirect-extern-access -mno-direct-extern-access @gol +-mexplicit-relocs=@var{style} -mexplicit-relocs -mno-explicit-relocs @gol -mcmodel=@var{code-model} -mrelax -mpass-mrelax-to-as @gol -mrecip -mrecip=@var{opt} -mfrecipe -mno-frecipe -mdiv32 -mno-div32 @gol -mlam-bh -mno-lam-bh -mlamcas -mno-lamcas -mld-seq-sa -mno-ld-seq-sa @gol -- 2.45.2
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